SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
96.89 | 97.99 | 95.95 | 93.38 | 97.67 | 98.55 | 98.76 | 95.94 |
T817 | /workspace/coverage/default/11.lc_ctrl_sec_mubi.3484425284 | Jun 30 06:55:50 PM PDT 24 | Jun 30 06:56:06 PM PDT 24 | 457975120 ps | ||
T818 | /workspace/coverage/default/5.lc_ctrl_jtag_errors.280771810 | Jun 30 06:55:26 PM PDT 24 | Jun 30 06:56:06 PM PDT 24 | 7320564844 ps | ||
T819 | /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.4169059098 | Jun 30 06:56:05 PM PDT 24 | Jun 30 06:56:19 PM PDT 24 | 790325648 ps | ||
T820 | /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.1270115499 | Jun 30 06:57:41 PM PDT 24 | Jun 30 06:57:42 PM PDT 24 | 49146471 ps | ||
T821 | /workspace/coverage/default/3.lc_ctrl_sec_token_digest.2033624676 | Jun 30 06:55:04 PM PDT 24 | Jun 30 06:55:15 PM PDT 24 | 3368373445 ps | ||
T822 | /workspace/coverage/default/4.lc_ctrl_sec_token_mux.462585942 | Jun 30 06:55:09 PM PDT 24 | Jun 30 06:55:22 PM PDT 24 | 323023622 ps | ||
T823 | /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.1315968659 | Jun 30 06:56:15 PM PDT 24 | Jun 30 06:56:46 PM PDT 24 | 4742728191 ps | ||
T824 | /workspace/coverage/default/16.lc_ctrl_state_post_trans.2871887241 | Jun 30 06:56:04 PM PDT 24 | Jun 30 06:56:15 PM PDT 24 | 272275085 ps | ||
T825 | /workspace/coverage/default/17.lc_ctrl_jtag_access.823208822 | Jun 30 06:56:21 PM PDT 24 | Jun 30 06:56:32 PM PDT 24 | 303972117 ps | ||
T826 | /workspace/coverage/default/11.lc_ctrl_security_escalation.1969383530 | Jun 30 06:55:42 PM PDT 24 | Jun 30 06:55:55 PM PDT 24 | 299436388 ps | ||
T827 | /workspace/coverage/default/16.lc_ctrl_jtag_access.693164273 | Jun 30 06:56:11 PM PDT 24 | Jun 30 06:56:25 PM PDT 24 | 5837311797 ps | ||
T828 | /workspace/coverage/default/44.lc_ctrl_smoke.4098289820 | Jun 30 06:57:35 PM PDT 24 | Jun 30 06:57:39 PM PDT 24 | 34061818 ps | ||
T829 | /workspace/coverage/default/8.lc_ctrl_jtag_errors.2243426739 | Jun 30 06:55:33 PM PDT 24 | Jun 30 06:57:20 PM PDT 24 | 8257349209 ps | ||
T830 | /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.2737160853 | Jun 30 06:54:59 PM PDT 24 | Jun 30 06:55:03 PM PDT 24 | 286224057 ps | ||
T831 | /workspace/coverage/default/44.lc_ctrl_alert_test.339614255 | Jun 30 06:57:35 PM PDT 24 | Jun 30 06:57:37 PM PDT 24 | 19028392 ps | ||
T832 | /workspace/coverage/default/21.lc_ctrl_errors.1476303830 | Jun 30 06:56:31 PM PDT 24 | Jun 30 06:56:50 PM PDT 24 | 1461569938 ps | ||
T833 | /workspace/coverage/default/48.lc_ctrl_sec_mubi.1496390700 | Jun 30 06:57:48 PM PDT 24 | Jun 30 06:58:09 PM PDT 24 | 1008550915 ps | ||
T834 | /workspace/coverage/default/4.lc_ctrl_prog_failure.284976692 | Jun 30 06:55:04 PM PDT 24 | Jun 30 06:55:08 PM PDT 24 | 42737695 ps | ||
T835 | /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.2576231973 | Jun 30 06:55:24 PM PDT 24 | Jun 30 06:55:36 PM PDT 24 | 2280858171 ps | ||
T836 | /workspace/coverage/default/40.lc_ctrl_sec_token_digest.3814567566 | Jun 30 06:57:26 PM PDT 24 | Jun 30 06:57:45 PM PDT 24 | 1673671648 ps | ||
T837 | /workspace/coverage/default/43.lc_ctrl_sec_mubi.122524301 | Jun 30 06:57:36 PM PDT 24 | Jun 30 06:57:51 PM PDT 24 | 1550165938 ps | ||
T838 | /workspace/coverage/default/30.lc_ctrl_errors.2085271582 | Jun 30 06:56:54 PM PDT 24 | Jun 30 06:57:05 PM PDT 24 | 239817629 ps | ||
T839 | /workspace/coverage/default/22.lc_ctrl_sec_token_digest.2898486720 | Jun 30 06:56:37 PM PDT 24 | Jun 30 06:56:51 PM PDT 24 | 522723248 ps | ||
T840 | /workspace/coverage/default/15.lc_ctrl_state_failure.1472250100 | Jun 30 06:56:06 PM PDT 24 | Jun 30 06:56:28 PM PDT 24 | 193658192 ps | ||
T841 | /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.197036740 | Jun 30 06:55:51 PM PDT 24 | Jun 30 06:57:00 PM PDT 24 | 1607851858 ps | ||
T842 | /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.1466999917 | Jun 30 06:56:20 PM PDT 24 | Jun 30 06:56:29 PM PDT 24 | 1136110606 ps | ||
T843 | /workspace/coverage/default/43.lc_ctrl_alert_test.4053147392 | Jun 30 06:57:33 PM PDT 24 | Jun 30 06:57:35 PM PDT 24 | 21001383 ps | ||
T844 | /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.3170063866 | Jun 30 06:56:30 PM PDT 24 | Jun 30 06:56:35 PM PDT 24 | 18727218 ps | ||
T845 | /workspace/coverage/default/41.lc_ctrl_state_post_trans.205156620 | Jun 30 06:57:31 PM PDT 24 | Jun 30 06:57:39 PM PDT 24 | 309016853 ps | ||
T846 | /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.2948910786 | Jun 30 06:55:04 PM PDT 24 | Jun 30 06:57:20 PM PDT 24 | 43164188235 ps | ||
T847 | /workspace/coverage/default/14.lc_ctrl_state_failure.4072449021 | Jun 30 06:56:05 PM PDT 24 | Jun 30 06:56:27 PM PDT 24 | 242137110 ps | ||
T848 | /workspace/coverage/default/9.lc_ctrl_smoke.723611053 | Jun 30 06:55:35 PM PDT 24 | Jun 30 06:55:38 PM PDT 24 | 32851140 ps | ||
T849 | /workspace/coverage/default/2.lc_ctrl_claim_transition_if.2599414489 | Jun 30 06:54:57 PM PDT 24 | Jun 30 06:54:59 PM PDT 24 | 51348324 ps | ||
T850 | /workspace/coverage/default/48.lc_ctrl_smoke.3819904881 | Jun 30 06:57:47 PM PDT 24 | Jun 30 06:57:51 PM PDT 24 | 163970473 ps | ||
T106 | /workspace/coverage/default/3.lc_ctrl_sec_cm.639108024 | Jun 30 06:55:02 PM PDT 24 | Jun 30 06:55:40 PM PDT 24 | 204499424 ps | ||
T851 | /workspace/coverage/default/9.lc_ctrl_prog_failure.465641165 | Jun 30 06:55:37 PM PDT 24 | Jun 30 06:55:40 PM PDT 24 | 213866665 ps | ||
T852 | /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.148591323 | Jun 30 06:55:59 PM PDT 24 | Jun 30 06:56:17 PM PDT 24 | 2288211011 ps | ||
T853 | /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.4053678566 | Jun 30 06:56:12 PM PDT 24 | Jun 30 06:56:35 PM PDT 24 | 2362914430 ps | ||
T854 | /workspace/coverage/default/38.lc_ctrl_state_post_trans.685345463 | Jun 30 06:57:24 PM PDT 24 | Jun 30 06:57:33 PM PDT 24 | 164581691 ps | ||
T855 | /workspace/coverage/default/4.lc_ctrl_jtag_priority.3160189898 | Jun 30 06:55:08 PM PDT 24 | Jun 30 06:55:10 PM PDT 24 | 85408225 ps | ||
T856 | /workspace/coverage/default/42.lc_ctrl_sec_token_mux.3446735156 | Jun 30 06:57:31 PM PDT 24 | Jun 30 06:57:44 PM PDT 24 | 289436003 ps | ||
T857 | /workspace/coverage/default/33.lc_ctrl_state_post_trans.4211573881 | Jun 30 06:57:05 PM PDT 24 | Jun 30 06:57:10 PM PDT 24 | 109354009 ps | ||
T858 | /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.186182986 | Jun 30 06:54:57 PM PDT 24 | Jun 30 06:54:59 PM PDT 24 | 47860362 ps | ||
T859 | /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.980070160 | Jun 30 06:56:04 PM PDT 24 | Jun 30 06:56:24 PM PDT 24 | 561047694 ps | ||
T118 | /workspace/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.2443489716 | Jun 30 06:57:11 PM PDT 24 | Jun 30 07:07:15 PM PDT 24 | 119921140756 ps | ||
T860 | /workspace/coverage/default/38.lc_ctrl_sec_mubi.726237688 | Jun 30 06:57:22 PM PDT 24 | Jun 30 06:57:40 PM PDT 24 | 2663684946 ps | ||
T861 | /workspace/coverage/default/22.lc_ctrl_state_post_trans.749973330 | Jun 30 06:56:37 PM PDT 24 | Jun 30 06:56:49 PM PDT 24 | 215644649 ps | ||
T862 | /workspace/coverage/default/14.lc_ctrl_security_escalation.2312036353 | Jun 30 06:56:03 PM PDT 24 | Jun 30 06:56:15 PM PDT 24 | 239521183 ps | ||
T863 | /workspace/coverage/default/13.lc_ctrl_state_failure.4176279936 | Jun 30 06:55:58 PM PDT 24 | Jun 30 06:56:27 PM PDT 24 | 201397878 ps | ||
T864 | /workspace/coverage/default/36.lc_ctrl_stress_all.2979597343 | Jun 30 06:57:20 PM PDT 24 | Jun 30 07:00:55 PM PDT 24 | 31568724842 ps | ||
T865 | /workspace/coverage/default/7.lc_ctrl_security_escalation.1209255779 | Jun 30 06:55:27 PM PDT 24 | Jun 30 06:55:39 PM PDT 24 | 968490714 ps | ||
T866 | /workspace/coverage/default/33.lc_ctrl_prog_failure.3891230069 | Jun 30 06:57:05 PM PDT 24 | Jun 30 06:57:10 PM PDT 24 | 76569202 ps | ||
T867 | /workspace/coverage/default/20.lc_ctrl_security_escalation.581771851 | Jun 30 06:56:25 PM PDT 24 | Jun 30 06:56:42 PM PDT 24 | 337154049 ps | ||
T868 | /workspace/coverage/default/20.lc_ctrl_smoke.3748213596 | Jun 30 06:56:27 PM PDT 24 | Jun 30 06:56:34 PM PDT 24 | 188311871 ps | ||
T869 | /workspace/coverage/default/20.lc_ctrl_state_failure.3014895704 | Jun 30 06:56:27 PM PDT 24 | Jun 30 06:56:49 PM PDT 24 | 186666580 ps | ||
T870 | /workspace/coverage/default/0.lc_ctrl_claim_transition_if.1484097218 | Jun 30 06:54:45 PM PDT 24 | Jun 30 06:54:47 PM PDT 24 | 12868565 ps | ||
T871 | /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.1989972211 | Jun 30 06:55:25 PM PDT 24 | Jun 30 06:55:56 PM PDT 24 | 2136222396 ps | ||
T872 | /workspace/coverage/default/28.lc_ctrl_prog_failure.1071455830 | Jun 30 06:56:49 PM PDT 24 | Jun 30 06:56:55 PM PDT 24 | 64052178 ps | ||
T873 | /workspace/coverage/default/4.lc_ctrl_jtag_smoke.2550154430 | Jun 30 06:55:05 PM PDT 24 | Jun 30 06:55:09 PM PDT 24 | 160391951 ps | ||
T874 | /workspace/coverage/default/48.lc_ctrl_errors.705604066 | Jun 30 06:57:49 PM PDT 24 | Jun 30 06:57:58 PM PDT 24 | 312842660 ps | ||
T875 | /workspace/coverage/default/12.lc_ctrl_state_failure.2215834208 | Jun 30 06:55:51 PM PDT 24 | Jun 30 06:56:20 PM PDT 24 | 232705796 ps | ||
T876 | /workspace/coverage/default/0.lc_ctrl_sec_mubi.502640972 | Jun 30 06:54:49 PM PDT 24 | Jun 30 06:55:03 PM PDT 24 | 1044386242 ps | ||
T877 | /workspace/coverage/default/44.lc_ctrl_security_escalation.1429179140 | Jun 30 06:57:34 PM PDT 24 | Jun 30 06:57:45 PM PDT 24 | 1812913171 ps | ||
T119 | /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3359739881 | Jun 30 06:58:11 PM PDT 24 | Jun 30 06:58:15 PM PDT 24 | 224491774 ps | ||
T120 | /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3776948701 | Jun 30 06:58:23 PM PDT 24 | Jun 30 06:58:28 PM PDT 24 | 463051110 ps | ||
T128 | /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2271354191 | Jun 30 06:58:15 PM PDT 24 | Jun 30 06:58:17 PM PDT 24 | 42271508 ps | ||
T155 | /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.4124784748 | Jun 30 06:58:13 PM PDT 24 | Jun 30 06:58:18 PM PDT 24 | 1031323278 ps | ||
T125 | /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3795236659 | Jun 30 06:58:25 PM PDT 24 | Jun 30 06:58:27 PM PDT 24 | 123561579 ps | ||
T217 | /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.4151007136 | Jun 30 06:57:53 PM PDT 24 | Jun 30 06:57:56 PM PDT 24 | 16600971 ps | ||
T121 | /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2807111954 | Jun 30 06:57:57 PM PDT 24 | Jun 30 06:58:01 PM PDT 24 | 667271159 ps | ||
T878 | /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1410557312 | Jun 30 06:58:02 PM PDT 24 | Jun 30 06:58:04 PM PDT 24 | 26423530 ps | ||
T124 | /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2817436320 | Jun 30 06:58:35 PM PDT 24 | Jun 30 06:58:37 PM PDT 24 | 25893202 ps | ||
T158 | /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1721399213 | Jun 30 06:58:19 PM PDT 24 | Jun 30 06:58:22 PM PDT 24 | 695124174 ps | ||
T159 | /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.3279312395 | Jun 30 06:58:11 PM PDT 24 | Jun 30 06:58:31 PM PDT 24 | 965510707 ps | ||
T140 | /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.401773787 | Jun 30 06:58:23 PM PDT 24 | Jun 30 06:58:26 PM PDT 24 | 84092568 ps | ||
T156 | /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2983469581 | Jun 30 06:58:12 PM PDT 24 | Jun 30 06:58:15 PM PDT 24 | 66865198 ps | ||
T203 | /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1738410792 | Jun 30 06:58:24 PM PDT 24 | Jun 30 06:58:25 PM PDT 24 | 12930421 ps | ||
T879 | /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.216449374 | Jun 30 06:58:19 PM PDT 24 | Jun 30 06:58:21 PM PDT 24 | 31717494 ps | ||
T138 | /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2280011112 | Jun 30 06:57:55 PM PDT 24 | Jun 30 06:57:58 PM PDT 24 | 22584139 ps | ||
T157 | /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3896544489 | Jun 30 06:57:54 PM PDT 24 | Jun 30 06:57:58 PM PDT 24 | 1012160512 ps | ||
T880 | /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.4215596837 | Jun 30 06:57:58 PM PDT 24 | Jun 30 06:58:10 PM PDT 24 | 4805839122 ps | ||
T881 | /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2805332108 | Jun 30 06:58:11 PM PDT 24 | Jun 30 06:58:13 PM PDT 24 | 15920133 ps | ||
T223 | /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.58663695 | Jun 30 06:57:53 PM PDT 24 | Jun 30 06:58:11 PM PDT 24 | 1921993714 ps | ||
T882 | /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.369364742 | Jun 30 06:57:52 PM PDT 24 | Jun 30 06:58:09 PM PDT 24 | 2826428369 ps | ||
T218 | /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.1615120402 | Jun 30 06:58:29 PM PDT 24 | Jun 30 06:58:31 PM PDT 24 | 27149885 ps | ||
T126 | /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.20570168 | Jun 30 06:58:23 PM PDT 24 | Jun 30 06:58:24 PM PDT 24 | 127835460 ps | ||
T883 | /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3122700986 | Jun 30 06:57:59 PM PDT 24 | Jun 30 06:58:01 PM PDT 24 | 48738421 ps | ||
T141 | /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.13772001 | Jun 30 06:58:19 PM PDT 24 | Jun 30 06:58:21 PM PDT 24 | 24635495 ps | ||
T219 | /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1244932164 | Jun 30 06:58:15 PM PDT 24 | Jun 30 06:58:17 PM PDT 24 | 24451149 ps | ||
T127 | /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3864610651 | Jun 30 06:58:24 PM PDT 24 | Jun 30 06:58:27 PM PDT 24 | 23352504 ps | ||
T204 | /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1776602503 | Jun 30 06:58:24 PM PDT 24 | Jun 30 06:58:26 PM PDT 24 | 11841310 ps | ||
T884 | /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1739519999 | Jun 30 06:58:13 PM PDT 24 | Jun 30 06:58:16 PM PDT 24 | 103769084 ps | ||
T224 | /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1511480394 | Jun 30 06:58:13 PM PDT 24 | Jun 30 06:58:21 PM PDT 24 | 1386233565 ps | ||
T885 | /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1556787017 | Jun 30 06:58:13 PM PDT 24 | Jun 30 06:58:16 PM PDT 24 | 186579510 ps | ||
T886 | /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3379685974 | Jun 30 06:58:10 PM PDT 24 | Jun 30 06:58:31 PM PDT 24 | 2611955699 ps | ||
T132 | /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.978240361 | Jun 30 06:58:30 PM PDT 24 | Jun 30 06:58:33 PM PDT 24 | 25445394 ps | ||
T133 | /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.336693169 | Jun 30 06:58:11 PM PDT 24 | Jun 30 06:58:16 PM PDT 24 | 46850091 ps | ||
T163 | /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.4182267547 | Jun 30 06:58:17 PM PDT 24 | Jun 30 06:58:20 PM PDT 24 | 75311532 ps | ||
T887 | /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.2233632711 | Jun 30 06:58:10 PM PDT 24 | Jun 30 06:58:12 PM PDT 24 | 179729619 ps | ||
T136 | /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.96644876 | Jun 30 06:58:27 PM PDT 24 | Jun 30 06:58:30 PM PDT 24 | 161984391 ps | ||
T888 | /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2852816928 | Jun 30 06:58:01 PM PDT 24 | Jun 30 06:58:04 PM PDT 24 | 169242927 ps | ||
T889 | /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2542026753 | Jun 30 06:57:51 PM PDT 24 | Jun 30 06:57:53 PM PDT 24 | 34493822 ps | ||
T152 | /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3554075571 | Jun 30 06:58:10 PM PDT 24 | Jun 30 06:58:17 PM PDT 24 | 1023942166 ps | ||
T220 | /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2282594898 | Jun 30 06:58:12 PM PDT 24 | Jun 30 06:58:15 PM PDT 24 | 157031297 ps | ||
T164 | /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2897942041 | Jun 30 06:58:36 PM PDT 24 | Jun 30 06:58:38 PM PDT 24 | 112666555 ps | ||
T890 | /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.189409219 | Jun 30 06:58:16 PM PDT 24 | Jun 30 06:58:19 PM PDT 24 | 165689830 ps | ||
T221 | /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3840844279 | Jun 30 06:58:25 PM PDT 24 | Jun 30 06:58:28 PM PDT 24 | 17922166 ps | ||
T891 | /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1708267219 | Jun 30 06:58:06 PM PDT 24 | Jun 30 06:58:13 PM PDT 24 | 476396316 ps | ||
T129 | /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2486618668 | Jun 30 06:58:12 PM PDT 24 | Jun 30 06:58:18 PM PDT 24 | 664851748 ps | ||
T165 | /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3061463165 | Jun 30 06:58:26 PM PDT 24 | Jun 30 06:58:27 PM PDT 24 | 31046138 ps | ||
T892 | /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2514357784 | Jun 30 06:58:24 PM PDT 24 | Jun 30 06:58:26 PM PDT 24 | 19394190 ps | ||
T135 | /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.791772546 | Jun 30 06:57:59 PM PDT 24 | Jun 30 06:58:03 PM PDT 24 | 1198707978 ps | ||
T166 | /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2285801107 | Jun 30 06:58:29 PM PDT 24 | Jun 30 06:58:32 PM PDT 24 | 181645546 ps | ||
T893 | /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1837292394 | Jun 30 06:58:18 PM PDT 24 | Jun 30 06:58:31 PM PDT 24 | 2482282172 ps | ||
T144 | /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3615442754 | Jun 30 06:58:30 PM PDT 24 | Jun 30 06:58:34 PM PDT 24 | 73155067 ps | ||
T894 | /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2590607536 | Jun 30 06:58:11 PM PDT 24 | Jun 30 06:58:15 PM PDT 24 | 43000603 ps | ||
T895 | /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.943843935 | Jun 30 06:58:02 PM PDT 24 | Jun 30 06:58:05 PM PDT 24 | 36365492 ps | ||
T896 | /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.218394272 | Jun 30 06:58:28 PM PDT 24 | Jun 30 06:58:31 PM PDT 24 | 113026889 ps | ||
T205 | /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3451009768 | Jun 30 06:58:07 PM PDT 24 | Jun 30 06:58:09 PM PDT 24 | 57122283 ps | ||
T153 | /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3600289238 | Jun 30 06:58:04 PM PDT 24 | Jun 30 06:58:06 PM PDT 24 | 121050638 ps | ||
T897 | /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3017280924 | Jun 30 06:58:00 PM PDT 24 | Jun 30 06:58:03 PM PDT 24 | 53470309 ps | ||
T898 | /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1068569365 | Jun 30 06:58:17 PM PDT 24 | Jun 30 06:58:20 PM PDT 24 | 102987836 ps | ||
T206 | /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1166205701 | Jun 30 06:58:21 PM PDT 24 | Jun 30 06:58:22 PM PDT 24 | 54217613 ps | ||
T134 | /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.4290798743 | Jun 30 06:58:24 PM PDT 24 | Jun 30 06:58:28 PM PDT 24 | 320115832 ps | ||
T154 | /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2920722778 | Jun 30 06:57:55 PM PDT 24 | Jun 30 06:57:59 PM PDT 24 | 95167688 ps | ||
T146 | /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3409795549 | Jun 30 06:58:15 PM PDT 24 | Jun 30 06:58:19 PM PDT 24 | 108460553 ps | ||
T899 | /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2804159227 | Jun 30 06:58:16 PM PDT 24 | Jun 30 06:58:20 PM PDT 24 | 406508225 ps | ||
T900 | /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1903984692 | Jun 30 06:58:04 PM PDT 24 | Jun 30 06:58:07 PM PDT 24 | 42406818 ps | ||
T148 | /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3964603929 | Jun 30 06:58:30 PM PDT 24 | Jun 30 06:58:34 PM PDT 24 | 803772697 ps | ||
T901 | /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3477426215 | Jun 30 06:58:11 PM PDT 24 | Jun 30 06:58:16 PM PDT 24 | 108023861 ps | ||
T902 | /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.798536587 | Jun 30 06:58:05 PM PDT 24 | Jun 30 06:58:07 PM PDT 24 | 69693362 ps | ||
T903 | /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.4052528862 | Jun 30 06:58:17 PM PDT 24 | Jun 30 06:58:19 PM PDT 24 | 36296210 ps | ||
T904 | /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1535546826 | Jun 30 06:58:21 PM PDT 24 | Jun 30 06:58:23 PM PDT 24 | 245860271 ps | ||
T905 | /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3566434804 | Jun 30 06:58:08 PM PDT 24 | Jun 30 06:58:10 PM PDT 24 | 26526560 ps | ||
T906 | /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2429111306 | Jun 30 06:58:15 PM PDT 24 | Jun 30 06:58:17 PM PDT 24 | 172686646 ps | ||
T907 | /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3404904883 | Jun 30 06:58:07 PM PDT 24 | Jun 30 06:58:11 PM PDT 24 | 355617396 ps | ||
T908 | /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2670782910 | Jun 30 06:58:13 PM PDT 24 | Jun 30 06:58:16 PM PDT 24 | 60060280 ps | ||
T207 | /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3074493682 | Jun 30 06:58:24 PM PDT 24 | Jun 30 06:58:25 PM PDT 24 | 50389615 ps | ||
T909 | /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1173970329 | Jun 30 06:58:25 PM PDT 24 | Jun 30 06:58:27 PM PDT 24 | 37823794 ps | ||
T910 | /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3199072439 | Jun 30 06:58:30 PM PDT 24 | Jun 30 06:58:33 PM PDT 24 | 291630802 ps | ||
T911 | /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3204994193 | Jun 30 06:58:29 PM PDT 24 | Jun 30 06:58:31 PM PDT 24 | 30454186 ps | ||
T912 | /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3570777019 | Jun 30 06:58:03 PM PDT 24 | Jun 30 06:58:23 PM PDT 24 | 9171486537 ps | ||
T913 | /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3752486150 | Jun 30 06:58:34 PM PDT 24 | Jun 30 06:58:36 PM PDT 24 | 31689356 ps | ||
T914 | /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.641493944 | Jun 30 06:58:16 PM PDT 24 | Jun 30 06:58:18 PM PDT 24 | 27791477 ps | ||
T915 | /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3258149189 | Jun 30 06:58:01 PM PDT 24 | Jun 30 06:58:06 PM PDT 24 | 89346772 ps | ||
T916 | /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3432444908 | Jun 30 06:58:10 PM PDT 24 | Jun 30 06:58:13 PM PDT 24 | 57624876 ps | ||
T917 | /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1079522592 | Jun 30 06:57:54 PM PDT 24 | Jun 30 06:57:59 PM PDT 24 | 374763965 ps | ||
T918 | /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.2054643262 | Jun 30 06:58:19 PM PDT 24 | Jun 30 06:58:21 PM PDT 24 | 15440390 ps | ||
T919 | /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.4164116748 | Jun 30 06:58:08 PM PDT 24 | Jun 30 06:58:09 PM PDT 24 | 13060561 ps | ||
T920 | /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.1650762732 | Jun 30 06:58:04 PM PDT 24 | Jun 30 06:58:07 PM PDT 24 | 246031706 ps | ||
T921 | /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3088763560 | Jun 30 06:58:00 PM PDT 24 | Jun 30 06:58:03 PM PDT 24 | 94467173 ps | ||
T922 | /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.615374874 | Jun 30 06:58:08 PM PDT 24 | Jun 30 06:58:10 PM PDT 24 | 15900540 ps | ||
T923 | /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.843627196 | Jun 30 06:58:23 PM PDT 24 | Jun 30 06:58:26 PM PDT 24 | 43400139 ps | ||
T924 | /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.662782578 | Jun 30 06:58:16 PM PDT 24 | Jun 30 06:58:19 PM PDT 24 | 98523800 ps | ||
T925 | /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3570987310 | Jun 30 06:58:11 PM PDT 24 | Jun 30 06:58:29 PM PDT 24 | 7433594088 ps | ||
T926 | /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2804612009 | Jun 30 06:58:15 PM PDT 24 | Jun 30 06:58:18 PM PDT 24 | 124907274 ps | ||
T927 | /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2393445355 | Jun 30 06:58:05 PM PDT 24 | Jun 30 06:58:12 PM PDT 24 | 1161827025 ps | ||
T928 | /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1794832270 | Jun 30 06:58:17 PM PDT 24 | Jun 30 06:58:21 PM PDT 24 | 213767471 ps | ||
T929 | /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1320404138 | Jun 30 06:58:13 PM PDT 24 | Jun 30 06:58:33 PM PDT 24 | 796630223 ps | ||
T930 | /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1847162354 | Jun 30 06:57:55 PM PDT 24 | Jun 30 06:57:59 PM PDT 24 | 100042683 ps | ||
T931 | /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.2435026521 | Jun 30 06:58:05 PM PDT 24 | Jun 30 06:58:23 PM PDT 24 | 3058448047 ps | ||
T208 | /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1320032790 | Jun 30 06:58:28 PM PDT 24 | Jun 30 06:58:30 PM PDT 24 | 16934681 ps | ||
T932 | /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.133806044 | Jun 30 06:58:19 PM PDT 24 | Jun 30 06:58:22 PM PDT 24 | 120540993 ps | ||
T933 | /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2516178321 | Jun 30 06:58:05 PM PDT 24 | Jun 30 06:58:07 PM PDT 24 | 82836346 ps | ||
T209 | /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1440645084 | Jun 30 06:58:06 PM PDT 24 | Jun 30 06:58:10 PM PDT 24 | 372016529 ps | ||
T934 | /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.618243397 | Jun 30 06:58:23 PM PDT 24 | Jun 30 06:58:25 PM PDT 24 | 69727478 ps | ||
T935 | /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.123633107 | Jun 30 06:58:14 PM PDT 24 | Jun 30 06:58:16 PM PDT 24 | 30974876 ps | ||
T936 | /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.325444695 | Jun 30 06:58:24 PM PDT 24 | Jun 30 06:58:26 PM PDT 24 | 103114751 ps | ||
T937 | /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3979548879 | Jun 30 06:57:59 PM PDT 24 | Jun 30 06:58:01 PM PDT 24 | 14730302 ps | ||
T210 | /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.394403883 | Jun 30 06:58:26 PM PDT 24 | Jun 30 06:58:28 PM PDT 24 | 16857816 ps | ||
T143 | /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3515733487 | Jun 30 06:58:25 PM PDT 24 | Jun 30 06:58:29 PM PDT 24 | 197976410 ps | ||
T145 | /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.251614250 | Jun 30 06:57:54 PM PDT 24 | Jun 30 06:58:00 PM PDT 24 | 259519188 ps | ||
T130 | /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3519316348 | Jun 30 06:58:27 PM PDT 24 | Jun 30 06:58:31 PM PDT 24 | 449480520 ps | ||
T149 | /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3625020813 | Jun 30 06:58:06 PM PDT 24 | Jun 30 06:58:09 PM PDT 24 | 342055342 ps | ||
T211 | /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3518585109 | Jun 30 06:57:55 PM PDT 24 | Jun 30 06:57:58 PM PDT 24 | 57092821 ps | ||
T938 | /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.271777672 | Jun 30 06:58:01 PM PDT 24 | Jun 30 06:58:03 PM PDT 24 | 22404412 ps | ||
T939 | /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.193922973 | Jun 30 06:57:53 PM PDT 24 | Jun 30 06:57:57 PM PDT 24 | 198967391 ps | ||
T940 | /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1206441073 | Jun 30 06:58:18 PM PDT 24 | Jun 30 06:58:28 PM PDT 24 | 884922573 ps | ||
T147 | /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2987596216 | Jun 30 06:58:14 PM PDT 24 | Jun 30 06:58:18 PM PDT 24 | 44879687 ps | ||
T941 | /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1486722803 | Jun 30 06:58:13 PM PDT 24 | Jun 30 06:58:16 PM PDT 24 | 199482856 ps | ||
T942 | /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1911455787 | Jun 30 06:58:08 PM PDT 24 | Jun 30 06:58:11 PM PDT 24 | 48855249 ps | ||
T212 | /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.4107681534 | Jun 30 06:58:00 PM PDT 24 | Jun 30 06:58:03 PM PDT 24 | 39119343 ps | ||
T213 | /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1789716267 | Jun 30 06:58:05 PM PDT 24 | Jun 30 06:58:07 PM PDT 24 | 37386729 ps | ||
T943 | /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3818598177 | Jun 30 06:58:00 PM PDT 24 | Jun 30 06:58:03 PM PDT 24 | 314673510 ps | ||
T944 | /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.244190742 | Jun 30 06:57:53 PM PDT 24 | Jun 30 06:57:56 PM PDT 24 | 156782927 ps | ||
T945 | /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2622750890 | Jun 30 06:58:17 PM PDT 24 | Jun 30 06:58:19 PM PDT 24 | 65724871 ps | ||
T946 | /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2290351821 | Jun 30 06:57:57 PM PDT 24 | Jun 30 06:58:00 PM PDT 24 | 157997317 ps | ||
T947 | /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.75965400 | Jun 30 06:58:00 PM PDT 24 | Jun 30 06:58:05 PM PDT 24 | 491076426 ps | ||
T948 | /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2793672095 | Jun 30 06:58:11 PM PDT 24 | Jun 30 06:58:15 PM PDT 24 | 44198653 ps | ||
T949 | /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3856448846 | Jun 30 06:57:55 PM PDT 24 | Jun 30 06:57:58 PM PDT 24 | 78138404 ps | ||
T950 | /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.993205522 | Jun 30 06:58:06 PM PDT 24 | Jun 30 06:58:09 PM PDT 24 | 63406276 ps | ||
T951 | /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1584008570 | Jun 30 06:58:12 PM PDT 24 | Jun 30 06:58:15 PM PDT 24 | 156949301 ps | ||
T952 | /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3724982414 | Jun 30 06:58:28 PM PDT 24 | Jun 30 06:58:30 PM PDT 24 | 33312651 ps | ||
T953 | /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2228526094 | Jun 30 06:58:30 PM PDT 24 | Jun 30 06:58:34 PM PDT 24 | 186443411 ps | ||
T954 | /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.410556315 | Jun 30 06:58:11 PM PDT 24 | Jun 30 06:58:14 PM PDT 24 | 486380650 ps | ||
T955 | /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.269965514 | Jun 30 06:58:19 PM PDT 24 | Jun 30 06:58:26 PM PDT 24 | 253654245 ps | ||
T956 | /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3526790364 | Jun 30 06:58:24 PM PDT 24 | Jun 30 06:58:27 PM PDT 24 | 369593788 ps | ||
T957 | /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2671000249 | Jun 30 06:58:26 PM PDT 24 | Jun 30 06:58:28 PM PDT 24 | 122105273 ps | ||
T958 | /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.719117181 | Jun 30 06:58:06 PM PDT 24 | Jun 30 06:58:08 PM PDT 24 | 163658970 ps | ||
T959 | /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2777933526 | Jun 30 06:58:25 PM PDT 24 | Jun 30 06:58:27 PM PDT 24 | 72160959 ps | ||
T960 | /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3838180446 | Jun 30 06:58:13 PM PDT 24 | Jun 30 06:58:16 PM PDT 24 | 324262337 ps | ||
T961 | /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1018864048 | Jun 30 06:58:13 PM PDT 24 | Jun 30 06:58:15 PM PDT 24 | 35786523 ps | ||
T962 | /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.9659395 | Jun 30 06:58:17 PM PDT 24 | Jun 30 06:58:20 PM PDT 24 | 17163294 ps | ||
T139 | /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3479020414 | Jun 30 06:58:17 PM PDT 24 | Jun 30 06:58:21 PM PDT 24 | 347962234 ps | ||
T963 | /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2703997149 | Jun 30 06:58:36 PM PDT 24 | Jun 30 06:58:38 PM PDT 24 | 35711087 ps | ||
T151 | /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1569318323 | Jun 30 06:58:27 PM PDT 24 | Jun 30 06:58:32 PM PDT 24 | 74141421 ps | ||
T964 | /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2529936783 | Jun 30 06:58:11 PM PDT 24 | Jun 30 06:58:13 PM PDT 24 | 160820495 ps | ||
T142 | /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3999390677 | Jun 30 06:58:30 PM PDT 24 | Jun 30 06:58:35 PM PDT 24 | 113318386 ps | ||
T965 | /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.802464441 | Jun 30 06:58:17 PM PDT 24 | Jun 30 06:58:20 PM PDT 24 | 26515726 ps | ||
T966 | /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.4179503833 | Jun 30 06:58:26 PM PDT 24 | Jun 30 06:58:29 PM PDT 24 | 113982370 ps | ||
T967 | /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2756684013 | Jun 30 06:58:16 PM PDT 24 | Jun 30 06:58:18 PM PDT 24 | 16168613 ps | ||
T968 | /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2287135980 | Jun 30 06:58:06 PM PDT 24 | Jun 30 06:58:08 PM PDT 24 | 203217182 ps | ||
T969 | /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2355197544 | Jun 30 06:57:56 PM PDT 24 | Jun 30 06:58:00 PM PDT 24 | 151388620 ps | ||
T970 | /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.208771242 | Jun 30 06:58:29 PM PDT 24 | Jun 30 06:58:31 PM PDT 24 | 172948266 ps | ||
T971 | /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1917462586 | Jun 30 06:58:00 PM PDT 24 | Jun 30 06:58:03 PM PDT 24 | 124804858 ps | ||
T972 | /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2735979523 | Jun 30 06:58:01 PM PDT 24 | Jun 30 06:58:03 PM PDT 24 | 22858642 ps | ||
T973 | /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2237238619 | Jun 30 06:58:12 PM PDT 24 | Jun 30 06:58:15 PM PDT 24 | 202018570 ps | ||
T974 | /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.275883248 | Jun 30 06:58:30 PM PDT 24 | Jun 30 06:58:33 PM PDT 24 | 76829142 ps | ||
T975 | /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3280425640 | Jun 30 06:58:17 PM PDT 24 | Jun 30 06:58:36 PM PDT 24 | 6304542449 ps | ||
T976 | /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1146048150 | Jun 30 06:58:01 PM PDT 24 | Jun 30 06:58:05 PM PDT 24 | 185945574 ps | ||
T977 | /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.564174501 | Jun 30 06:58:18 PM PDT 24 | Jun 30 06:58:22 PM PDT 24 | 516229272 ps | ||
T978 | /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.4253263295 | Jun 30 06:57:59 PM PDT 24 | Jun 30 06:58:20 PM PDT 24 | 3216599406 ps | ||
T979 | /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2445671355 | Jun 30 06:58:30 PM PDT 24 | Jun 30 06:58:33 PM PDT 24 | 23377977 ps | ||
T214 | /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2472115195 | Jun 30 06:57:55 PM PDT 24 | Jun 30 06:57:58 PM PDT 24 | 33657038 ps | ||
T980 | /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2007145240 | Jun 30 06:58:16 PM PDT 24 | Jun 30 06:58:19 PM PDT 24 | 66510964 ps | ||
T981 | /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2450241584 | Jun 30 06:58:03 PM PDT 24 | Jun 30 06:58:05 PM PDT 24 | 26263382 ps | ||
T982 | /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.4028930734 | Jun 30 06:57:56 PM PDT 24 | Jun 30 06:57:59 PM PDT 24 | 356395228 ps | ||
T983 | /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1436150313 | Jun 30 06:58:13 PM PDT 24 | Jun 30 06:58:16 PM PDT 24 | 289659675 ps | ||
T984 | /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1717620783 | Jun 30 06:58:06 PM PDT 24 | Jun 30 06:58:10 PM PDT 24 | 132722233 ps | ||
T985 | /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1271739082 | Jun 30 06:58:29 PM PDT 24 | Jun 30 06:58:32 PM PDT 24 | 124945759 ps | ||
T215 | /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.384179682 | Jun 30 06:58:09 PM PDT 24 | Jun 30 06:58:11 PM PDT 24 | 62842511 ps | ||
T986 | /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.4122205990 | Jun 30 06:58:06 PM PDT 24 | Jun 30 06:58:08 PM PDT 24 | 26034103 ps | ||
T987 | /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3985103110 | Jun 30 06:58:11 PM PDT 24 | Jun 30 06:58:13 PM PDT 24 | 49458235 ps | ||
T988 | /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3942841318 | Jun 30 06:57:59 PM PDT 24 | Jun 30 06:58:25 PM PDT 24 | 1247441012 ps | ||
T989 | /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2005336854 | Jun 30 06:58:22 PM PDT 24 | Jun 30 06:58:24 PM PDT 24 | 268323356 ps | ||
T990 | /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.210048835 | Jun 30 06:58:18 PM PDT 24 | Jun 30 06:58:28 PM PDT 24 | 3379551013 ps | ||
T991 | /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2434941049 | Jun 30 06:58:01 PM PDT 24 | Jun 30 06:58:04 PM PDT 24 | 44363388 ps | ||
T992 | /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.277051752 | Jun 30 06:58:11 PM PDT 24 | Jun 30 06:58:14 PM PDT 24 | 56837593 ps | ||
T993 | /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1563700230 | Jun 30 06:58:07 PM PDT 24 | Jun 30 06:58:10 PM PDT 24 | 123572794 ps | ||
T216 | /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1040897775 | Jun 30 06:57:58 PM PDT 24 | Jun 30 06:58:01 PM PDT 24 | 152278721 ps | ||
T994 | /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.1436564868 | Jun 30 06:58:34 PM PDT 24 | Jun 30 06:58:36 PM PDT 24 | 30313429 ps | ||
T995 | /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.2599590982 | Jun 30 06:58:28 PM PDT 24 | Jun 30 06:58:30 PM PDT 24 | 12280671 ps | ||
T150 | /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2654688218 | Jun 30 06:58:19 PM PDT 24 | Jun 30 06:58:22 PM PDT 24 | 286497618 ps | ||
T131 | /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2436981835 | Jun 30 06:58:29 PM PDT 24 | Jun 30 06:58:32 PM PDT 24 | 240503817 ps | ||
T996 | /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.93773079 | Jun 30 06:58:14 PM PDT 24 | Jun 30 06:58:16 PM PDT 24 | 20423271 ps | ||
T997 | /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2823762371 | Jun 30 06:58:08 PM PDT 24 | Jun 30 06:58:26 PM PDT 24 | 4970042577 ps | ||
T998 | /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1960631559 | Jun 30 06:58:06 PM PDT 24 | Jun 30 06:58:08 PM PDT 24 | 19521879 ps | ||
T137 | /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3813983737 | Jun 30 06:58:04 PM PDT 24 | Jun 30 06:58:08 PM PDT 24 | 307313145 ps |
Test location | /workspace/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.520800459 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 14357684909 ps |
CPU time | 308.44 seconds |
Started | Jun 30 06:56:38 PM PDT 24 |
Finished | Jun 30 07:01:49 PM PDT 24 |
Peak memory | 300028 kb |
Host | smart-6fb724f6-01fa-4398-84e1-f3d803d1b080 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=520800459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all_with_rand_reset.520800459 |
Directory | /workspace/22.lc_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/43.lc_ctrl_security_escalation.3902451104 |
Short name | T311 |
Test name | |
Test status | |
Simulation time | 2243318826 ps |
CPU time | 13.35 seconds |
Started | Jun 30 06:57:36 PM PDT 24 |
Finished | Jun 30 06:57:50 PM PDT 24 |
Peak memory | 226504 kb |
Host | smart-c6f7a2f0-5676-46aa-82a5-220d5a98a8c4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3902451104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.3902451104 |
Directory | /workspace/43.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/37.lc_ctrl_sec_mubi.2981743783 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 2124082350 ps |
CPU time | 19.96 seconds |
Started | Jun 30 06:57:21 PM PDT 24 |
Finished | Jun 30 06:57:42 PM PDT 24 |
Peak memory | 226456 kb |
Host | smart-b765d430-6a03-496d-af94-3c20e9d2ea24 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981743783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.2981743783 |
Directory | /workspace/37.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/7.lc_ctrl_stress_all.2850886622 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 82256959534 ps |
CPU time | 461.28 seconds |
Started | Jun 30 06:55:28 PM PDT 24 |
Finished | Jun 30 07:03:10 PM PDT 24 |
Peak memory | 253224 kb |
Host | smart-a53284f4-6e06-4697-bde7-1a61685e304a |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850886622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all.2850886622 |
Directory | /workspace/7.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2807111954 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 667271159 ps |
CPU time | 2.85 seconds |
Started | Jun 30 06:57:57 PM PDT 24 |
Finished | Jun 30 06:58:01 PM PDT 24 |
Peak memory | 222184 kb |
Host | smart-dc59a7b9-8089-439d-a830-5e1234562690 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807111954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_ err.2807111954 |
Directory | /workspace/1.lc_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.1646975656 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 69196000 ps |
CPU time | 0.9 seconds |
Started | Jun 30 06:55:38 PM PDT 24 |
Finished | Jun 30 06:55:41 PM PDT 24 |
Peak memory | 209444 kb |
Host | smart-0ffafd36-4778-455a-8f98-cb5d0c351fe8 |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646975656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c trl_volatile_unlock_smoke.1646975656 |
Directory | /workspace/10.lc_ctrl_volatile_unlock_smoke/latest |
Test location | /workspace/coverage/default/23.lc_ctrl_sec_token_mux.1469707561 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 1357020739 ps |
CPU time | 11.28 seconds |
Started | Jun 30 06:56:38 PM PDT 24 |
Finished | Jun 30 06:56:52 PM PDT 24 |
Peak memory | 218584 kb |
Host | smart-f6086e04-06bf-414e-8918-f7cd031d0eaf |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469707561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux. 1469707561 |
Directory | /workspace/23.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/0.lc_ctrl_sec_cm.1807282779 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 131354462 ps |
CPU time | 21.76 seconds |
Started | Jun 30 06:54:49 PM PDT 24 |
Finished | Jun 30 06:55:12 PM PDT 24 |
Peak memory | 281884 kb |
Host | smart-98af4bf2-b189-4e3f-bfb1-97a91146b4c8 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807282779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.1807282779 |
Directory | /workspace/0.lc_ctrl_sec_cm/latest |
Test location | /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2817436320 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 25893202 ps |
CPU time | 1.58 seconds |
Started | Jun 30 06:58:35 PM PDT 24 |
Finished | Jun 30 06:58:37 PM PDT 24 |
Peak memory | 217360 kb |
Host | smart-b390acc0-9c7b-4174-a8f3-7830cc7e2d03 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817436320 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.2817436320 |
Directory | /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/default/33.lc_ctrl_alert_test.4152826696 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 269361890 ps |
CPU time | 1.13 seconds |
Started | Jun 30 06:57:11 PM PDT 24 |
Finished | Jun 30 06:57:13 PM PDT 24 |
Peak memory | 209380 kb |
Host | smart-88bf26a2-9304-4054-947c-0c4888005e5c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152826696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.4152826696 |
Directory | /workspace/33.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/19.lc_ctrl_jtag_access.907513806 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 108067785 ps |
CPU time | 2.82 seconds |
Started | Jun 30 06:56:23 PM PDT 24 |
Finished | Jun 30 06:56:29 PM PDT 24 |
Peak memory | 217460 kb |
Host | smart-f0d29f7a-e963-4973-90c5-26542111b779 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907513806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.907513806 |
Directory | /workspace/19.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2897942041 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 112666555 ps |
CPU time | 1.07 seconds |
Started | Jun 30 06:58:36 PM PDT 24 |
Finished | Jun 30 06:58:38 PM PDT 24 |
Peak memory | 209256 kb |
Host | smart-c5c01ba4-ee40-49e1-8159-fd5ae33d25ee |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897942041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.2897942041 |
Directory | /workspace/17.lc_ctrl_csr_rw/latest |
Test location | /workspace/coverage/default/46.lc_ctrl_stress_all.310232754 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 2769097831 ps |
CPU time | 88.9 seconds |
Started | Jun 30 06:57:43 PM PDT 24 |
Finished | Jun 30 06:59:12 PM PDT 24 |
Peak memory | 251412 kb |
Host | smart-f432c4e3-c7bd-43cb-bbb1-09e5b14450da |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310232754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all.310232754 |
Directory | /workspace/46.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.369364742 |
Short name | T882 |
Test name | |
Test status | |
Simulation time | 2826428369 ps |
CPU time | 16.37 seconds |
Started | Jun 30 06:57:52 PM PDT 24 |
Finished | Jun 30 06:58:09 PM PDT 24 |
Peak memory | 217068 kb |
Host | smart-a96feb41-2814-4546-9b7d-b30d02460a09 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369364742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 0.lc_ctrl_jtag_csr_aliasing.369364742 |
Directory | /workspace/0.lc_ctrl_jtag_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3519316348 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 449480520 ps |
CPU time | 3.05 seconds |
Started | Jun 30 06:58:27 PM PDT 24 |
Finished | Jun 30 06:58:31 PM PDT 24 |
Peak memory | 221952 kb |
Host | smart-6d21123d-dc5b-4b22-b4a5-3241097fa7af |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519316348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg _err.3519316348 |
Directory | /workspace/12.lc_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/27.lc_ctrl_stress_all.1016242233 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 12458447502 ps |
CPU time | 75.75 seconds |
Started | Jun 30 06:56:51 PM PDT 24 |
Finished | Jun 30 06:58:09 PM PDT 24 |
Peak memory | 280884 kb |
Host | smart-5fcfa3e3-850d-469a-831c-69baaebe7550 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016242233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all.1016242233 |
Directory | /workspace/27.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/3.lc_ctrl_security_escalation.3391889815 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 1568540072 ps |
CPU time | 12.66 seconds |
Started | Jun 30 06:54:57 PM PDT 24 |
Finished | Jun 30 06:55:10 PM PDT 24 |
Peak memory | 218808 kb |
Host | smart-b0f93672-d1bf-447d-a9af-4b6416ad7e18 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3391889815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.3391889815 |
Directory | /workspace/3.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.4290798743 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 320115832 ps |
CPU time | 3.61 seconds |
Started | Jun 30 06:58:24 PM PDT 24 |
Finished | Jun 30 06:58:28 PM PDT 24 |
Peak memory | 217368 kb |
Host | smart-ca0a09d6-a205-430a-8227-4647d5bea103 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290798743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg _err.4290798743 |
Directory | /workspace/11.lc_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.1276652227 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 23744833587 ps |
CPU time | 471.53 seconds |
Started | Jun 30 06:56:13 PM PDT 24 |
Finished | Jun 30 07:04:08 PM PDT 24 |
Peak memory | 283244 kb |
Host | smart-dec038b5-4d87-4093-9289-231cf0f4ec36 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1276652227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all_with_rand_reset.1276652227 |
Directory | /workspace/16.lc_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2486618668 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 664851748 ps |
CPU time | 3.86 seconds |
Started | Jun 30 06:58:12 PM PDT 24 |
Finished | Jun 30 06:58:18 PM PDT 24 |
Peak memory | 217276 kb |
Host | smart-4a46d84d-0947-43cc-87e1-94cc3f9c085d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486618668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.2486618668 |
Directory | /workspace/5.lc_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3515733487 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 197976410 ps |
CPU time | 2.72 seconds |
Started | Jun 30 06:58:25 PM PDT 24 |
Finished | Jun 30 06:58:29 PM PDT 24 |
Peak memory | 222136 kb |
Host | smart-78ae581b-3b56-47d1-9e17-6c1a9a390f47 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515733487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg _err.3515733487 |
Directory | /workspace/13.lc_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.2443489716 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 119921140756 ps |
CPU time | 602.72 seconds |
Started | Jun 30 06:57:11 PM PDT 24 |
Finished | Jun 30 07:07:15 PM PDT 24 |
Peak memory | 333468 kb |
Host | smart-85f40ad9-b611-4e7b-9470-fa7e7cad213e |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2443489716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.2443489716 |
Directory | /workspace/35.lc_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2920722778 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 95167688 ps |
CPU time | 2.75 seconds |
Started | Jun 30 06:57:55 PM PDT 24 |
Finished | Jun 30 06:57:59 PM PDT 24 |
Peak memory | 210520 kb |
Host | smart-ae5583fd-c226-4d56-a014-39c6653409c8 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920722778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.2920722778 |
Directory | /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest |
Test location | /workspace/coverage/default/30.lc_ctrl_sec_token_digest.308193748 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 396138002 ps |
CPU time | 12.57 seconds |
Started | Jun 30 06:57:02 PM PDT 24 |
Finished | Jun 30 06:57:15 PM PDT 24 |
Peak memory | 218620 kb |
Host | smart-94df6b63-be4a-4a87-94b3-67bcd9366e37 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308193748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_di gest.308193748 |
Directory | /workspace/30.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2987596216 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 44879687 ps |
CPU time | 2.45 seconds |
Started | Jun 30 06:58:14 PM PDT 24 |
Finished | Jun 30 06:58:18 PM PDT 24 |
Peak memory | 221820 kb |
Host | smart-83d3371c-2aa5-4042-a915-1a58d3303cf1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987596216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_ err.2987596216 |
Directory | /workspace/6.lc_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3409795549 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 108460553 ps |
CPU time | 2.83 seconds |
Started | Jun 30 06:58:15 PM PDT 24 |
Finished | Jun 30 06:58:19 PM PDT 24 |
Peak memory | 221932 kb |
Host | smart-9d83f5d7-450e-499f-b53c-1d997a60222f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409795549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_ err.3409795549 |
Directory | /workspace/8.lc_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.lc_ctrl_claim_transition_if.1484097218 |
Short name | T870 |
Test name | |
Test status | |
Simulation time | 12868565 ps |
CPU time | 0.96 seconds |
Started | Jun 30 06:54:45 PM PDT 24 |
Finished | Jun 30 06:54:47 PM PDT 24 |
Peak memory | 209380 kb |
Host | smart-9f51a57c-0e07-4838-8634-dbc504bcaf94 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1484097218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.1484097218 |
Directory | /workspace/0.lc_ctrl_claim_transition_if/latest |
Test location | /workspace/coverage/default/18.lc_ctrl_security_escalation.124263852 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 796827144 ps |
CPU time | 8.31 seconds |
Started | Jun 30 06:56:17 PM PDT 24 |
Finished | Jun 30 06:56:30 PM PDT 24 |
Peak memory | 225584 kb |
Host | smart-ca90dea2-76d2-44dd-addc-56d04e540bf3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=124263852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.124263852 |
Directory | /workspace/18.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/9.lc_ctrl_claim_transition_if.1173630821 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 15219426 ps |
CPU time | 0.83 seconds |
Started | Jun 30 06:55:34 PM PDT 24 |
Finished | Jun 30 06:55:35 PM PDT 24 |
Peak memory | 209220 kb |
Host | smart-9d4c4348-1c31-4910-ab0f-ff10d5f5227c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1173630821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.1173630821 |
Directory | /workspace/9.lc_ctrl_claim_transition_if/latest |
Test location | /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.251614250 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 259519188 ps |
CPU time | 4.54 seconds |
Started | Jun 30 06:57:54 PM PDT 24 |
Finished | Jun 30 06:58:00 PM PDT 24 |
Peak memory | 217400 kb |
Host | smart-46410f00-df43-442f-8500-7c939ff8b0b6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251614250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_e rr.251614250 |
Directory | /workspace/0.lc_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.401773787 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 84092568 ps |
CPU time | 2.24 seconds |
Started | Jun 30 06:58:23 PM PDT 24 |
Finished | Jun 30 06:58:26 PM PDT 24 |
Peak memory | 221348 kb |
Host | smart-3f7f64fa-c941-42ab-bb48-502d5bc55073 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401773787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg_ err.401773787 |
Directory | /workspace/10.lc_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1569318323 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 74141421 ps |
CPU time | 3.49 seconds |
Started | Jun 30 06:58:27 PM PDT 24 |
Finished | Jun 30 06:58:32 PM PDT 24 |
Peak memory | 222168 kb |
Host | smart-ec510542-21a0-4f0e-aeff-ea381926ec8e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569318323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg _err.1569318323 |
Directory | /workspace/16.lc_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3999390677 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 113318386 ps |
CPU time | 4.25 seconds |
Started | Jun 30 06:58:30 PM PDT 24 |
Finished | Jun 30 06:58:35 PM PDT 24 |
Peak memory | 217388 kb |
Host | smart-ecd96c35-536b-40c1-a56c-77dee9bfd040 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999390677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg _err.3999390677 |
Directory | /workspace/19.lc_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3813983737 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 307313145 ps |
CPU time | 3.51 seconds |
Started | Jun 30 06:58:04 PM PDT 24 |
Finished | Jun 30 06:58:08 PM PDT 24 |
Peak memory | 222188 kb |
Host | smart-9db4d200-5fe3-469e-9eed-1e22bcea0014 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813983737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_ err.3813983737 |
Directory | /workspace/2.lc_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3625020813 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 342055342 ps |
CPU time | 1.93 seconds |
Started | Jun 30 06:58:06 PM PDT 24 |
Finished | Jun 30 06:58:09 PM PDT 24 |
Peak memory | 213004 kb |
Host | smart-92880530-037d-4142-addc-63aa47a90a20 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625020813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_ err.3625020813 |
Directory | /workspace/4.lc_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.35156022 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 12780948528 ps |
CPU time | 279.61 seconds |
Started | Jun 30 06:56:05 PM PDT 24 |
Finished | Jun 30 07:00:47 PM PDT 24 |
Peak memory | 282460 kb |
Host | smart-0c9f06ad-9586-40bf-b29e-288cacca9380 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=35156022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all_with_rand_reset.35156022 |
Directory | /workspace/14.lc_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.3656198811 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 30405854071 ps |
CPU time | 413.83 seconds |
Started | Jun 30 06:56:16 PM PDT 24 |
Finished | Jun 30 07:03:15 PM PDT 24 |
Peak memory | 422696 kb |
Host | smart-69a242b9-1093-4742-886c-513dd03a5b56 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3656198811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.3656198811 |
Directory | /workspace/18.lc_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/27.lc_ctrl_sec_token_mux.2102427086 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 1083917641 ps |
CPU time | 18.34 seconds |
Started | Jun 30 06:56:49 PM PDT 24 |
Finished | Jun 30 06:57:10 PM PDT 24 |
Peak memory | 218588 kb |
Host | smart-d77dac99-fd74-43f4-bc3e-198711407e30 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102427086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux. 2102427086 |
Directory | /workspace/27.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/11.lc_ctrl_sec_token_mux.1908745151 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 287672951 ps |
CPU time | 10.11 seconds |
Started | Jun 30 06:55:50 PM PDT 24 |
Finished | Jun 30 06:56:03 PM PDT 24 |
Peak memory | 218588 kb |
Host | smart-717a0e60-d3de-4734-85e8-65dc5b4ef3a9 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908745151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux. 1908745151 |
Directory | /workspace/11.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2472115195 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 33657038 ps |
CPU time | 1.34 seconds |
Started | Jun 30 06:57:55 PM PDT 24 |
Finished | Jun 30 06:57:58 PM PDT 24 |
Peak memory | 209120 kb |
Host | smart-9e5ba2a7-ed10-4850-b36b-9993dcc805d9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472115195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin g.2472115195 |
Directory | /workspace/0.lc_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.4028930734 |
Short name | T982 |
Test name | |
Test status | |
Simulation time | 356395228 ps |
CPU time | 1.45 seconds |
Started | Jun 30 06:57:56 PM PDT 24 |
Finished | Jun 30 06:57:59 PM PDT 24 |
Peak memory | 217092 kb |
Host | smart-6f1ee7a5-5246-43dd-9942-e7387219d9fa |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028930734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas h.4028930734 |
Directory | /workspace/0.lc_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2542026753 |
Short name | T889 |
Test name | |
Test status | |
Simulation time | 34493822 ps |
CPU time | 0.85 seconds |
Started | Jun 30 06:57:51 PM PDT 24 |
Finished | Jun 30 06:57:53 PM PDT 24 |
Peak memory | 209444 kb |
Host | smart-64e5dd69-6fa6-4b53-aa77-e47255cc53e3 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542026753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese t.2542026753 |
Directory | /workspace/0.lc_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2280011112 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 22584139 ps |
CPU time | 1.47 seconds |
Started | Jun 30 06:57:55 PM PDT 24 |
Finished | Jun 30 06:57:58 PM PDT 24 |
Peak memory | 217456 kb |
Host | smart-a097312e-5938-4205-b32e-603a1c7c71a8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280011112 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.2280011112 |
Directory | /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3518585109 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 57092821 ps |
CPU time | 1.05 seconds |
Started | Jun 30 06:57:55 PM PDT 24 |
Finished | Jun 30 06:57:58 PM PDT 24 |
Peak memory | 209100 kb |
Host | smart-f0afbd02-011a-4900-ba5a-9d293b32984f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518585109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.3518585109 |
Directory | /workspace/0.lc_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.193922973 |
Short name | T939 |
Test name | |
Test status | |
Simulation time | 198967391 ps |
CPU time | 1.97 seconds |
Started | Jun 30 06:57:53 PM PDT 24 |
Finished | Jun 30 06:57:57 PM PDT 24 |
Peak memory | 208964 kb |
Host | smart-ca35988c-f7b5-4b2a-9f47-450921882f75 |
User | root |
Command | /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193922973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 0.lc_ctrl_jtag_alert_test.193922973 |
Directory | /workspace/0.lc_ctrl_jtag_alert_test/latest |
Test location | /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.58663695 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 1921993714 ps |
CPU time | 16.83 seconds |
Started | Jun 30 06:57:53 PM PDT 24 |
Finished | Jun 30 06:58:11 PM PDT 24 |
Peak memory | 209056 kb |
Host | smart-47cfa058-1465-4aeb-9c65-b72fd7e56145 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58663695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.58663695 |
Directory | /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1079522592 |
Short name | T917 |
Test name | |
Test status | |
Simulation time | 374763965 ps |
CPU time | 2.18 seconds |
Started | Jun 30 06:57:54 PM PDT 24 |
Finished | Jun 30 06:57:59 PM PDT 24 |
Peak memory | 210184 kb |
Host | smart-3e6ab5d7-a1bb-44ed-9dcd-1c8fde566de2 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079522592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.1079522592 |
Directory | /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3896544489 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 1012160512 ps |
CPU time | 1.87 seconds |
Started | Jun 30 06:57:54 PM PDT 24 |
Finished | Jun 30 06:57:58 PM PDT 24 |
Peak memory | 217456 kb |
Host | smart-74e61330-3a91-451b-a339-092f74dd6695 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389654 4489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3896544489 |
Directory | /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1847162354 |
Short name | T930 |
Test name | |
Test status | |
Simulation time | 100042683 ps |
CPU time | 1.58 seconds |
Started | Jun 30 06:57:55 PM PDT 24 |
Finished | Jun 30 06:57:59 PM PDT 24 |
Peak memory | 208988 kb |
Host | smart-2905bf23-6744-4838-926a-31d2d70f3e83 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847162354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_rw.1847162354 |
Directory | /workspace/0.lc_ctrl_jtag_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.244190742 |
Short name | T944 |
Test name | |
Test status | |
Simulation time | 156782927 ps |
CPU time | 1.96 seconds |
Started | Jun 30 06:57:53 PM PDT 24 |
Finished | Jun 30 06:57:56 PM PDT 24 |
Peak memory | 217324 kb |
Host | smart-8ddf93e9-3d5d-498c-8864-bcb1f74f8b6c |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244190742 -assert nopostproc +UVM_TESTNAM E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.244190742 |
Directory | /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.4151007136 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 16600971 ps |
CPU time | 1.28 seconds |
Started | Jun 30 06:57:53 PM PDT 24 |
Finished | Jun 30 06:57:56 PM PDT 24 |
Peak memory | 209248 kb |
Host | smart-98f70836-382b-4663-ae46-33d4a9b154b8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151007136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl _same_csr_outstanding.4151007136 |
Directory | /workspace/0.lc_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2355197544 |
Short name | T969 |
Test name | |
Test status | |
Simulation time | 151388620 ps |
CPU time | 2.77 seconds |
Started | Jun 30 06:57:56 PM PDT 24 |
Finished | Jun 30 06:58:00 PM PDT 24 |
Peak memory | 218304 kb |
Host | smart-97b1e9a9-f462-4f7d-a111-6f1b25891d92 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355197544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.2355197544 |
Directory | /workspace/0.lc_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2735979523 |
Short name | T972 |
Test name | |
Test status | |
Simulation time | 22858642 ps |
CPU time | 1.03 seconds |
Started | Jun 30 06:58:01 PM PDT 24 |
Finished | Jun 30 06:58:03 PM PDT 24 |
Peak memory | 209108 kb |
Host | smart-399c85d4-e183-4f07-b75e-d2c2ec192714 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735979523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin g.2735979523 |
Directory | /workspace/1.lc_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1146048150 |
Short name | T976 |
Test name | |
Test status | |
Simulation time | 185945574 ps |
CPU time | 2.29 seconds |
Started | Jun 30 06:58:01 PM PDT 24 |
Finished | Jun 30 06:58:05 PM PDT 24 |
Peak memory | 209024 kb |
Host | smart-d70a97d4-7b54-4bfd-908e-9fb6d56b2328 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146048150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas h.1146048150 |
Directory | /workspace/1.lc_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1410557312 |
Short name | T878 |
Test name | |
Test status | |
Simulation time | 26423530 ps |
CPU time | 0.95 seconds |
Started | Jun 30 06:58:02 PM PDT 24 |
Finished | Jun 30 06:58:04 PM PDT 24 |
Peak memory | 209564 kb |
Host | smart-d1884643-e75c-4d2f-bc29-2038546eee39 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410557312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese t.1410557312 |
Directory | /workspace/1.lc_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2434941049 |
Short name | T991 |
Test name | |
Test status | |
Simulation time | 44363388 ps |
CPU time | 1.57 seconds |
Started | Jun 30 06:58:01 PM PDT 24 |
Finished | Jun 30 06:58:04 PM PDT 24 |
Peak memory | 217396 kb |
Host | smart-934e3021-8528-43ce-a8c7-1d4a76d8aa5d |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434941049 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.2434941049 |
Directory | /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3979548879 |
Short name | T937 |
Test name | |
Test status | |
Simulation time | 14730302 ps |
CPU time | 0.89 seconds |
Started | Jun 30 06:57:59 PM PDT 24 |
Finished | Jun 30 06:58:01 PM PDT 24 |
Peak memory | 209128 kb |
Host | smart-41cdce3a-9c74-4441-929a-6e442d37ec37 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979548879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.3979548879 |
Directory | /workspace/1.lc_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2852816928 |
Short name | T888 |
Test name | |
Test status | |
Simulation time | 169242927 ps |
CPU time | 1.71 seconds |
Started | Jun 30 06:58:01 PM PDT 24 |
Finished | Jun 30 06:58:04 PM PDT 24 |
Peak memory | 208484 kb |
Host | smart-7757ab16-5c89-4231-abf1-c934ed859ade |
User | root |
Command | /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852816928 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 1.lc_ctrl_jtag_alert_test.2852816928 |
Directory | /workspace/1.lc_ctrl_jtag_alert_test/latest |
Test location | /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.4253263295 |
Short name | T978 |
Test name | |
Test status | |
Simulation time | 3216599406 ps |
CPU time | 19.7 seconds |
Started | Jun 30 06:57:59 PM PDT 24 |
Finished | Jun 30 06:58:20 PM PDT 24 |
Peak memory | 209116 kb |
Host | smart-9c0dc1ca-1965-4af2-a3c6-447f37ee5d45 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253263295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.4253263295 |
Directory | /workspace/1.lc_ctrl_jtag_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3942841318 |
Short name | T988 |
Test name | |
Test status | |
Simulation time | 1247441012 ps |
CPU time | 24.33 seconds |
Started | Jun 30 06:57:59 PM PDT 24 |
Finished | Jun 30 06:58:25 PM PDT 24 |
Peak memory | 208676 kb |
Host | smart-718c3be6-7c3f-4bcf-a61f-1bb5a2b57bfe |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942841318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.3942841318 |
Directory | /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1917462586 |
Short name | T971 |
Test name | |
Test status | |
Simulation time | 124804858 ps |
CPU time | 1.56 seconds |
Started | Jun 30 06:58:00 PM PDT 24 |
Finished | Jun 30 06:58:03 PM PDT 24 |
Peak memory | 217804 kb |
Host | smart-c339d58d-9ad5-4633-bed3-4af9c6d2aef3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191746 2586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1917462586 |
Directory | /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3856448846 |
Short name | T949 |
Test name | |
Test status | |
Simulation time | 78138404 ps |
CPU time | 1.41 seconds |
Started | Jun 30 06:57:55 PM PDT 24 |
Finished | Jun 30 06:57:58 PM PDT 24 |
Peak memory | 209036 kb |
Host | smart-2642df9a-1e2c-4cc8-acf3-bfe78f07574b |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856448846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_rw.3856448846 |
Directory | /workspace/1.lc_ctrl_jtag_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.271777672 |
Short name | T938 |
Test name | |
Test status | |
Simulation time | 22404412 ps |
CPU time | 1.14 seconds |
Started | Jun 30 06:58:01 PM PDT 24 |
Finished | Jun 30 06:58:03 PM PDT 24 |
Peak memory | 209104 kb |
Host | smart-d232adfb-27b4-43be-8ce6-15317b67c8c3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271777672 -assert nopostproc +UVM_TESTNAM E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.271777672 |
Directory | /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2450241584 |
Short name | T981 |
Test name | |
Test status | |
Simulation time | 26263382 ps |
CPU time | 0.95 seconds |
Started | Jun 30 06:58:03 PM PDT 24 |
Finished | Jun 30 06:58:05 PM PDT 24 |
Peak memory | 217280 kb |
Host | smart-46a8c6d9-06c2-466c-b1d5-22ac6c0aa6aa |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450241584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl _same_csr_outstanding.2450241584 |
Directory | /workspace/1.lc_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.791772546 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 1198707978 ps |
CPU time | 3.01 seconds |
Started | Jun 30 06:57:59 PM PDT 24 |
Finished | Jun 30 06:58:03 PM PDT 24 |
Peak memory | 217280 kb |
Host | smart-71002e43-0653-4f85-bf11-9c48279c437d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791772546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.791772546 |
Directory | /workspace/1.lc_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3061463165 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 31046138 ps |
CPU time | 1.02 seconds |
Started | Jun 30 06:58:26 PM PDT 24 |
Finished | Jun 30 06:58:27 PM PDT 24 |
Peak memory | 217668 kb |
Host | smart-52bc8fe7-fab2-4ef7-94cc-379b42379df8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061463165 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.3061463165 |
Directory | /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3074493682 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 50389615 ps |
CPU time | 1.01 seconds |
Started | Jun 30 06:58:24 PM PDT 24 |
Finished | Jun 30 06:58:25 PM PDT 24 |
Peak memory | 208768 kb |
Host | smart-e001b548-85ea-4431-b53e-50ac484847fe |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074493682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.3074493682 |
Directory | /workspace/10.lc_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3840844279 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 17922166 ps |
CPU time | 1.42 seconds |
Started | Jun 30 06:58:25 PM PDT 24 |
Finished | Jun 30 06:58:28 PM PDT 24 |
Peak memory | 211240 kb |
Host | smart-b619595b-80de-4042-a362-04abfe92d167 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840844279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr l_same_csr_outstanding.3840844279 |
Directory | /workspace/10.lc_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2777933526 |
Short name | T959 |
Test name | |
Test status | |
Simulation time | 72160959 ps |
CPU time | 2.18 seconds |
Started | Jun 30 06:58:25 PM PDT 24 |
Finished | Jun 30 06:58:27 PM PDT 24 |
Peak memory | 217848 kb |
Host | smart-247f3567-ed15-4eab-8587-4250c34f3dac |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777933526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.2777933526 |
Directory | /workspace/10.lc_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.325444695 |
Short name | T936 |
Test name | |
Test status | |
Simulation time | 103114751 ps |
CPU time | 1.59 seconds |
Started | Jun 30 06:58:24 PM PDT 24 |
Finished | Jun 30 06:58:26 PM PDT 24 |
Peak memory | 217368 kb |
Host | smart-63c00c0c-9b1c-44c5-ba93-b2b17d238272 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325444695 -assert nopostproc +UVM_TESTNAME= lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.325444695 |
Directory | /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1738410792 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 12930421 ps |
CPU time | 0.85 seconds |
Started | Jun 30 06:58:24 PM PDT 24 |
Finished | Jun 30 06:58:25 PM PDT 24 |
Peak memory | 208740 kb |
Host | smart-a58e675b-ed65-4440-9b1a-e3a64d5d9fa5 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738410792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.1738410792 |
Directory | /workspace/11.lc_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.843627196 |
Short name | T923 |
Test name | |
Test status | |
Simulation time | 43400139 ps |
CPU time | 2 seconds |
Started | Jun 30 06:58:23 PM PDT 24 |
Finished | Jun 30 06:58:26 PM PDT 24 |
Peak memory | 217340 kb |
Host | smart-84b13e4e-4c08-4fa3-a392-6e06ac927a5e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843627196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl _same_csr_outstanding.843627196 |
Directory | /workspace/11.lc_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3864610651 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 23352504 ps |
CPU time | 1.95 seconds |
Started | Jun 30 06:58:24 PM PDT 24 |
Finished | Jun 30 06:58:27 PM PDT 24 |
Peak memory | 217344 kb |
Host | smart-8f58c1eb-ce6b-4e2a-8995-9bbc4fa09490 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864610651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.3864610651 |
Directory | /workspace/11.lc_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1535546826 |
Short name | T904 |
Test name | |
Test status | |
Simulation time | 245860271 ps |
CPU time | 1.45 seconds |
Started | Jun 30 06:58:21 PM PDT 24 |
Finished | Jun 30 06:58:23 PM PDT 24 |
Peak memory | 218360 kb |
Host | smart-10da030a-86b7-4037-8a0b-ef2ddbef6610 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535546826 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.1535546826 |
Directory | /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1776602503 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 11841310 ps |
CPU time | 0.91 seconds |
Started | Jun 30 06:58:24 PM PDT 24 |
Finished | Jun 30 06:58:26 PM PDT 24 |
Peak memory | 208916 kb |
Host | smart-795bf2c1-7e93-42f4-a44c-f7e9032289d8 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776602503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.1776602503 |
Directory | /workspace/12.lc_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.618243397 |
Short name | T934 |
Test name | |
Test status | |
Simulation time | 69727478 ps |
CPU time | 1.29 seconds |
Started | Jun 30 06:58:23 PM PDT 24 |
Finished | Jun 30 06:58:25 PM PDT 24 |
Peak memory | 217276 kb |
Host | smart-f7ad41f9-0da2-47ed-b390-41f3b84d0272 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618243397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl _same_csr_outstanding.618243397 |
Directory | /workspace/12.lc_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.20570168 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 127835460 ps |
CPU time | 1.46 seconds |
Started | Jun 30 06:58:23 PM PDT 24 |
Finished | Jun 30 06:58:24 PM PDT 24 |
Peak memory | 217324 kb |
Host | smart-2fcdef8f-f85d-4f8c-8287-066a582b91e6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20570168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.20570168 |
Directory | /workspace/12.lc_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3795236659 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 123561579 ps |
CPU time | 1.82 seconds |
Started | Jun 30 06:58:25 PM PDT 24 |
Finished | Jun 30 06:58:27 PM PDT 24 |
Peak memory | 217392 kb |
Host | smart-92a51228-2abc-44a9-b9cf-3ed767fafd85 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795236659 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.3795236659 |
Directory | /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.394403883 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 16857816 ps |
CPU time | 0.9 seconds |
Started | Jun 30 06:58:26 PM PDT 24 |
Finished | Jun 30 06:58:28 PM PDT 24 |
Peak memory | 209048 kb |
Host | smart-676a0bda-f6ca-4c5b-a174-167b1ebf6c86 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394403883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.394403883 |
Directory | /workspace/13.lc_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2671000249 |
Short name | T957 |
Test name | |
Test status | |
Simulation time | 122105273 ps |
CPU time | 1.4 seconds |
Started | Jun 30 06:58:26 PM PDT 24 |
Finished | Jun 30 06:58:28 PM PDT 24 |
Peak memory | 211180 kb |
Host | smart-6b533ea2-676d-48c2-b74f-f851eb6b1e4b |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671000249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr l_same_csr_outstanding.2671000249 |
Directory | /workspace/13.lc_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2005336854 |
Short name | T989 |
Test name | |
Test status | |
Simulation time | 268323356 ps |
CPU time | 2.12 seconds |
Started | Jun 30 06:58:22 PM PDT 24 |
Finished | Jun 30 06:58:24 PM PDT 24 |
Peak memory | 217480 kb |
Host | smart-f9ed675d-db2f-4210-abcf-c1f0c965fa03 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005336854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.2005336854 |
Directory | /workspace/13.lc_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2514357784 |
Short name | T892 |
Test name | |
Test status | |
Simulation time | 19394190 ps |
CPU time | 0.84 seconds |
Started | Jun 30 06:58:24 PM PDT 24 |
Finished | Jun 30 06:58:26 PM PDT 24 |
Peak memory | 208536 kb |
Host | smart-7f55fe72-4608-45bb-b304-20195f59b1f9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514357784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.2514357784 |
Directory | /workspace/14.lc_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1173970329 |
Short name | T909 |
Test name | |
Test status | |
Simulation time | 37823794 ps |
CPU time | 1.5 seconds |
Started | Jun 30 06:58:25 PM PDT 24 |
Finished | Jun 30 06:58:27 PM PDT 24 |
Peak memory | 209244 kb |
Host | smart-685097ed-0a84-4496-8340-30af6c309a59 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173970329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr l_same_csr_outstanding.1173970329 |
Directory | /workspace/14.lc_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3526790364 |
Short name | T956 |
Test name | |
Test status | |
Simulation time | 369593788 ps |
CPU time | 2.96 seconds |
Started | Jun 30 06:58:24 PM PDT 24 |
Finished | Jun 30 06:58:27 PM PDT 24 |
Peak memory | 217280 kb |
Host | smart-c8b56b09-9777-4efe-9ed6-0ddb1b724641 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526790364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.3526790364 |
Directory | /workspace/14.lc_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3776948701 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 463051110 ps |
CPU time | 4.23 seconds |
Started | Jun 30 06:58:23 PM PDT 24 |
Finished | Jun 30 06:58:28 PM PDT 24 |
Peak memory | 217304 kb |
Host | smart-0147d1f2-0639-4b6e-a6f9-9c0b80f0864b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776948701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg _err.3776948701 |
Directory | /workspace/14.lc_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.1436564868 |
Short name | T994 |
Test name | |
Test status | |
Simulation time | 30313429 ps |
CPU time | 1.44 seconds |
Started | Jun 30 06:58:34 PM PDT 24 |
Finished | Jun 30 06:58:36 PM PDT 24 |
Peak memory | 218816 kb |
Host | smart-19c1968a-36d8-438a-81b7-7f728fe9cfa1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436564868 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.1436564868 |
Directory | /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3204994193 |
Short name | T911 |
Test name | |
Test status | |
Simulation time | 30454186 ps |
CPU time | 0.89 seconds |
Started | Jun 30 06:58:29 PM PDT 24 |
Finished | Jun 30 06:58:31 PM PDT 24 |
Peak memory | 209112 kb |
Host | smart-1e188327-fb79-428a-b1f0-8f852984afd6 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204994193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.3204994193 |
Directory | /workspace/15.lc_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.208771242 |
Short name | T970 |
Test name | |
Test status | |
Simulation time | 172948266 ps |
CPU time | 1.38 seconds |
Started | Jun 30 06:58:29 PM PDT 24 |
Finished | Jun 30 06:58:31 PM PDT 24 |
Peak memory | 209244 kb |
Host | smart-1853a61c-3a20-4d47-bc1c-c34825de2b8a |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208771242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl _same_csr_outstanding.208771242 |
Directory | /workspace/15.lc_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2228526094 |
Short name | T953 |
Test name | |
Test status | |
Simulation time | 186443411 ps |
CPU time | 3.13 seconds |
Started | Jun 30 06:58:30 PM PDT 24 |
Finished | Jun 30 06:58:34 PM PDT 24 |
Peak memory | 217252 kb |
Host | smart-a521a378-d7d3-47d5-8706-8807b3068828 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228526094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.2228526094 |
Directory | /workspace/15.lc_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.96644876 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 161984391 ps |
CPU time | 1.67 seconds |
Started | Jun 30 06:58:27 PM PDT 24 |
Finished | Jun 30 06:58:30 PM PDT 24 |
Peak memory | 221484 kb |
Host | smart-d0568338-8ad6-4597-8ff5-40111fddecec |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96644876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg_e rr.96644876 |
Directory | /workspace/15.lc_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3199072439 |
Short name | T910 |
Test name | |
Test status | |
Simulation time | 291630802 ps |
CPU time | 1.82 seconds |
Started | Jun 30 06:58:30 PM PDT 24 |
Finished | Jun 30 06:58:33 PM PDT 24 |
Peak memory | 217508 kb |
Host | smart-a13bc95e-29bc-42d5-97f7-a2099e2cc592 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199072439 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.3199072439 |
Directory | /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.2599590982 |
Short name | T995 |
Test name | |
Test status | |
Simulation time | 12280671 ps |
CPU time | 0.97 seconds |
Started | Jun 30 06:58:28 PM PDT 24 |
Finished | Jun 30 06:58:30 PM PDT 24 |
Peak memory | 209100 kb |
Host | smart-049b1c3c-bbeb-4ec7-9fd1-be855f9349bc |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599590982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.2599590982 |
Directory | /workspace/16.lc_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2285801107 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 181645546 ps |
CPU time | 1.98 seconds |
Started | Jun 30 06:58:29 PM PDT 24 |
Finished | Jun 30 06:58:32 PM PDT 24 |
Peak memory | 211172 kb |
Host | smart-7d50e93f-0d8e-400b-8e55-4a44d3bf9182 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285801107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr l_same_csr_outstanding.2285801107 |
Directory | /workspace/16.lc_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3615442754 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 73155067 ps |
CPU time | 3.02 seconds |
Started | Jun 30 06:58:30 PM PDT 24 |
Finished | Jun 30 06:58:34 PM PDT 24 |
Peak memory | 217276 kb |
Host | smart-20832f65-b31b-4677-9cb2-e0db3e440ed4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615442754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.3615442754 |
Directory | /workspace/16.lc_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.978240361 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 25445394 ps |
CPU time | 1.58 seconds |
Started | Jun 30 06:58:30 PM PDT 24 |
Finished | Jun 30 06:58:33 PM PDT 24 |
Peak memory | 219480 kb |
Host | smart-3399a847-59be-425c-bcd5-83960176e091 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978240361 -assert nopostproc +UVM_TESTNAME= lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.978240361 |
Directory | /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.1615120402 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 27149885 ps |
CPU time | 1.25 seconds |
Started | Jun 30 06:58:29 PM PDT 24 |
Finished | Jun 30 06:58:31 PM PDT 24 |
Peak memory | 209120 kb |
Host | smart-7636f2e5-26bf-4cca-995f-835d4933243e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615120402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr l_same_csr_outstanding.1615120402 |
Directory | /workspace/17.lc_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.4179503833 |
Short name | T966 |
Test name | |
Test status | |
Simulation time | 113982370 ps |
CPU time | 2.15 seconds |
Started | Jun 30 06:58:26 PM PDT 24 |
Finished | Jun 30 06:58:29 PM PDT 24 |
Peak memory | 218436 kb |
Host | smart-86602de7-16d4-43c6-97ac-ca8c092421c7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179503833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.4179503833 |
Directory | /workspace/17.lc_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2436981835 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 240503817 ps |
CPU time | 2.01 seconds |
Started | Jun 30 06:58:29 PM PDT 24 |
Finished | Jun 30 06:58:32 PM PDT 24 |
Peak memory | 217540 kb |
Host | smart-82294120-94cc-4a39-9d60-2edbd28835fc |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436981835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg _err.2436981835 |
Directory | /workspace/17.lc_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2703997149 |
Short name | T963 |
Test name | |
Test status | |
Simulation time | 35711087 ps |
CPU time | 1.5 seconds |
Started | Jun 30 06:58:36 PM PDT 24 |
Finished | Jun 30 06:58:38 PM PDT 24 |
Peak memory | 217508 kb |
Host | smart-2105d010-a00d-47fa-9c5a-751caa845f8d |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703997149 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.2703997149 |
Directory | /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3724982414 |
Short name | T952 |
Test name | |
Test status | |
Simulation time | 33312651 ps |
CPU time | 0.9 seconds |
Started | Jun 30 06:58:28 PM PDT 24 |
Finished | Jun 30 06:58:30 PM PDT 24 |
Peak memory | 208952 kb |
Host | smart-f1171dfa-8ad2-4b28-b726-30502c3a4e4a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724982414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.3724982414 |
Directory | /workspace/18.lc_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2445671355 |
Short name | T979 |
Test name | |
Test status | |
Simulation time | 23377977 ps |
CPU time | 1.05 seconds |
Started | Jun 30 06:58:30 PM PDT 24 |
Finished | Jun 30 06:58:33 PM PDT 24 |
Peak memory | 217316 kb |
Host | smart-26de530b-5183-447d-8e4d-3f4b439a1187 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445671355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr l_same_csr_outstanding.2445671355 |
Directory | /workspace/18.lc_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.275883248 |
Short name | T974 |
Test name | |
Test status | |
Simulation time | 76829142 ps |
CPU time | 1.45 seconds |
Started | Jun 30 06:58:30 PM PDT 24 |
Finished | Jun 30 06:58:33 PM PDT 24 |
Peak memory | 218348 kb |
Host | smart-7562e9fe-6dde-4706-b79f-5d8d2dcad058 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275883248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.275883248 |
Directory | /workspace/18.lc_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3964603929 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 803772697 ps |
CPU time | 2.1 seconds |
Started | Jun 30 06:58:30 PM PDT 24 |
Finished | Jun 30 06:58:34 PM PDT 24 |
Peak memory | 217320 kb |
Host | smart-2cb0bf5c-e15e-407b-a6a8-e5a88dd01408 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964603929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg _err.3964603929 |
Directory | /workspace/18.lc_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3752486150 |
Short name | T913 |
Test name | |
Test status | |
Simulation time | 31689356 ps |
CPU time | 1.4 seconds |
Started | Jun 30 06:58:34 PM PDT 24 |
Finished | Jun 30 06:58:36 PM PDT 24 |
Peak memory | 218808 kb |
Host | smart-be61fe2b-2d1d-4590-9ce7-a304e74cb090 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752486150 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.3752486150 |
Directory | /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1320032790 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 16934681 ps |
CPU time | 0.94 seconds |
Started | Jun 30 06:58:28 PM PDT 24 |
Finished | Jun 30 06:58:30 PM PDT 24 |
Peak memory | 209120 kb |
Host | smart-9ad21190-6029-4ba3-a90a-2655be62f64d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320032790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.1320032790 |
Directory | /workspace/19.lc_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1271739082 |
Short name | T985 |
Test name | |
Test status | |
Simulation time | 124945759 ps |
CPU time | 1.81 seconds |
Started | Jun 30 06:58:29 PM PDT 24 |
Finished | Jun 30 06:58:32 PM PDT 24 |
Peak memory | 217280 kb |
Host | smart-364fce8e-d375-4fb7-8175-8b0279814c75 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271739082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr l_same_csr_outstanding.1271739082 |
Directory | /workspace/19.lc_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.218394272 |
Short name | T896 |
Test name | |
Test status | |
Simulation time | 113026889 ps |
CPU time | 2.43 seconds |
Started | Jun 30 06:58:28 PM PDT 24 |
Finished | Jun 30 06:58:31 PM PDT 24 |
Peak memory | 217520 kb |
Host | smart-b99b944d-f580-4fdc-8026-d45452be6ece |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218394272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.218394272 |
Directory | /workspace/19.lc_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1040897775 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 152278721 ps |
CPU time | 1.7 seconds |
Started | Jun 30 06:57:58 PM PDT 24 |
Finished | Jun 30 06:58:01 PM PDT 24 |
Peak memory | 209120 kb |
Host | smart-dbbc5d19-6c83-4701-ace0-b993db95c141 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040897775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin g.1040897775 |
Directory | /workspace/2.lc_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2290351821 |
Short name | T946 |
Test name | |
Test status | |
Simulation time | 157997317 ps |
CPU time | 1.69 seconds |
Started | Jun 30 06:57:57 PM PDT 24 |
Finished | Jun 30 06:58:00 PM PDT 24 |
Peak memory | 216812 kb |
Host | smart-6982e2a2-aadd-4d43-b160-d0b6302c86a9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290351821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas h.2290351821 |
Directory | /workspace/2.lc_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.4107681534 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 39119343 ps |
CPU time | 1.09 seconds |
Started | Jun 30 06:58:00 PM PDT 24 |
Finished | Jun 30 06:58:03 PM PDT 24 |
Peak memory | 217936 kb |
Host | smart-93d057f9-bf69-4ead-ae72-d5cea6a33834 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107681534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese t.4107681534 |
Directory | /workspace/2.lc_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.615374874 |
Short name | T922 |
Test name | |
Test status | |
Simulation time | 15900540 ps |
CPU time | 1.28 seconds |
Started | Jun 30 06:58:08 PM PDT 24 |
Finished | Jun 30 06:58:10 PM PDT 24 |
Peak memory | 217436 kb |
Host | smart-9e6095d1-f6e6-47cb-ac26-a0b1521b7408 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615374874 -assert nopostproc +UVM_TESTNAME= lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.615374874 |
Directory | /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3122700986 |
Short name | T883 |
Test name | |
Test status | |
Simulation time | 48738421 ps |
CPU time | 1.13 seconds |
Started | Jun 30 06:57:59 PM PDT 24 |
Finished | Jun 30 06:58:01 PM PDT 24 |
Peak memory | 208848 kb |
Host | smart-97c7808f-2dab-4520-bc81-cd398ebe14fb |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122700986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.3122700986 |
Directory | /workspace/2.lc_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3017280924 |
Short name | T897 |
Test name | |
Test status | |
Simulation time | 53470309 ps |
CPU time | 1.27 seconds |
Started | Jun 30 06:58:00 PM PDT 24 |
Finished | Jun 30 06:58:03 PM PDT 24 |
Peak memory | 208960 kb |
Host | smart-f00ec6e3-6019-4c32-895a-c3d6592b73cb |
User | root |
Command | /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017280924 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 2.lc_ctrl_jtag_alert_test.3017280924 |
Directory | /workspace/2.lc_ctrl_jtag_alert_test/latest |
Test location | /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.4215596837 |
Short name | T880 |
Test name | |
Test status | |
Simulation time | 4805839122 ps |
CPU time | 10.05 seconds |
Started | Jun 30 06:57:58 PM PDT 24 |
Finished | Jun 30 06:58:10 PM PDT 24 |
Peak memory | 217128 kb |
Host | smart-b6fdf8ed-f822-421e-a031-32ace2af33c7 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215596837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.4215596837 |
Directory | /workspace/2.lc_ctrl_jtag_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3570777019 |
Short name | T912 |
Test name | |
Test status | |
Simulation time | 9171486537 ps |
CPU time | 18.91 seconds |
Started | Jun 30 06:58:03 PM PDT 24 |
Finished | Jun 30 06:58:23 PM PDT 24 |
Peak memory | 217116 kb |
Host | smart-0b9e11e5-2f79-44d4-95d8-085a9b435e9d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570777019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.3570777019 |
Directory | /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3088763560 |
Short name | T921 |
Test name | |
Test status | |
Simulation time | 94467173 ps |
CPU time | 1.67 seconds |
Started | Jun 30 06:58:00 PM PDT 24 |
Finished | Jun 30 06:58:03 PM PDT 24 |
Peak memory | 210696 kb |
Host | smart-caa2b09a-8f7b-4deb-8c52-f7bd5912edef |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088763560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.3088763560 |
Directory | /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3258149189 |
Short name | T915 |
Test name | |
Test status | |
Simulation time | 89346772 ps |
CPU time | 3.59 seconds |
Started | Jun 30 06:58:01 PM PDT 24 |
Finished | Jun 30 06:58:06 PM PDT 24 |
Peak memory | 222700 kb |
Host | smart-c6248055-ece1-4fa7-acf9-8896027a472f |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325814 9189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3258149189 |
Directory | /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3600289238 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 121050638 ps |
CPU time | 1.31 seconds |
Started | Jun 30 06:58:04 PM PDT 24 |
Finished | Jun 30 06:58:06 PM PDT 24 |
Peak memory | 208904 kb |
Host | smart-a741a97b-9a76-4c10-9724-5134376295d0 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600289238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_rw.3600289238 |
Directory | /workspace/2.lc_ctrl_jtag_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3818598177 |
Short name | T943 |
Test name | |
Test status | |
Simulation time | 314673510 ps |
CPU time | 1.28 seconds |
Started | Jun 30 06:58:00 PM PDT 24 |
Finished | Jun 30 06:58:03 PM PDT 24 |
Peak memory | 209080 kb |
Host | smart-83f57b71-e833-4258-bfc4-606f1dc72d2a |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818598177 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.3818598177 |
Directory | /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.943843935 |
Short name | T895 |
Test name | |
Test status | |
Simulation time | 36365492 ps |
CPU time | 1.37 seconds |
Started | Jun 30 06:58:02 PM PDT 24 |
Finished | Jun 30 06:58:05 PM PDT 24 |
Peak memory | 217352 kb |
Host | smart-75c37d6d-95f6-45d3-ba67-683f9cc6b637 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943843935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_ same_csr_outstanding.943843935 |
Directory | /workspace/2.lc_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.75965400 |
Short name | T947 |
Test name | |
Test status | |
Simulation time | 491076426 ps |
CPU time | 3.74 seconds |
Started | Jun 30 06:58:00 PM PDT 24 |
Finished | Jun 30 06:58:05 PM PDT 24 |
Peak memory | 218692 kb |
Host | smart-b604c632-ae9e-4d3b-baea-0406d7680b04 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75965400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.75965400 |
Directory | /workspace/2.lc_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1789716267 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 37386729 ps |
CPU time | 1.28 seconds |
Started | Jun 30 06:58:05 PM PDT 24 |
Finished | Jun 30 06:58:07 PM PDT 24 |
Peak memory | 217292 kb |
Host | smart-5179ee9d-4457-4a06-aa1b-7d2223b2af35 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789716267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin g.1789716267 |
Directory | /workspace/3.lc_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1440645084 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 372016529 ps |
CPU time | 3.23 seconds |
Started | Jun 30 06:58:06 PM PDT 24 |
Finished | Jun 30 06:58:10 PM PDT 24 |
Peak memory | 209072 kb |
Host | smart-a5a66b90-f5be-4e4a-acec-f707139795ca |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440645084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas h.1440645084 |
Directory | /workspace/3.lc_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1903984692 |
Short name | T900 |
Test name | |
Test status | |
Simulation time | 42406818 ps |
CPU time | 0.9 seconds |
Started | Jun 30 06:58:04 PM PDT 24 |
Finished | Jun 30 06:58:07 PM PDT 24 |
Peak memory | 209556 kb |
Host | smart-9329f873-fc86-4b89-9c58-6c8b1b6eebe3 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903984692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese t.1903984692 |
Directory | /workspace/3.lc_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3566434804 |
Short name | T905 |
Test name | |
Test status | |
Simulation time | 26526560 ps |
CPU time | 1.75 seconds |
Started | Jun 30 06:58:08 PM PDT 24 |
Finished | Jun 30 06:58:10 PM PDT 24 |
Peak memory | 219612 kb |
Host | smart-c73ed1e8-3c9a-4c13-bfc8-bd1a9499e4cf |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566434804 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.3566434804 |
Directory | /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1960631559 |
Short name | T998 |
Test name | |
Test status | |
Simulation time | 19521879 ps |
CPU time | 0.97 seconds |
Started | Jun 30 06:58:06 PM PDT 24 |
Finished | Jun 30 06:58:08 PM PDT 24 |
Peak memory | 209124 kb |
Host | smart-c7e7ca03-1422-4175-a9dd-66a1003166e9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960631559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.1960631559 |
Directory | /workspace/3.lc_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.277051752 |
Short name | T992 |
Test name | |
Test status | |
Simulation time | 56837593 ps |
CPU time | 1.14 seconds |
Started | Jun 30 06:58:11 PM PDT 24 |
Finished | Jun 30 06:58:14 PM PDT 24 |
Peak memory | 208920 kb |
Host | smart-977d1601-a19e-4e9f-a1f6-174038c286c7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277051752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 3.lc_ctrl_jtag_alert_test.277051752 |
Directory | /workspace/3.lc_ctrl_jtag_alert_test/latest |
Test location | /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2823762371 |
Short name | T997 |
Test name | |
Test status | |
Simulation time | 4970042577 ps |
CPU time | 16.45 seconds |
Started | Jun 30 06:58:08 PM PDT 24 |
Finished | Jun 30 06:58:26 PM PDT 24 |
Peak memory | 209020 kb |
Host | smart-4e962878-73e5-4a14-998d-f511974be1ae |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823762371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.2823762371 |
Directory | /workspace/3.lc_ctrl_jtag_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.2435026521 |
Short name | T931 |
Test name | |
Test status | |
Simulation time | 3058448047 ps |
CPU time | 17.52 seconds |
Started | Jun 30 06:58:05 PM PDT 24 |
Finished | Jun 30 06:58:23 PM PDT 24 |
Peak memory | 217112 kb |
Host | smart-2bdfe556-6d1b-45c8-a0ce-0dd1be3ce20e |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435026521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.2435026521 |
Directory | /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1708267219 |
Short name | T891 |
Test name | |
Test status | |
Simulation time | 476396316 ps |
CPU time | 5.74 seconds |
Started | Jun 30 06:58:06 PM PDT 24 |
Finished | Jun 30 06:58:13 PM PDT 24 |
Peak memory | 210676 kb |
Host | smart-2af59ab3-0251-4dd4-b29d-d46976411fc0 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708267219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.1708267219 |
Directory | /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1717620783 |
Short name | T984 |
Test name | |
Test status | |
Simulation time | 132722233 ps |
CPU time | 2.51 seconds |
Started | Jun 30 06:58:06 PM PDT 24 |
Finished | Jun 30 06:58:10 PM PDT 24 |
Peak memory | 217368 kb |
Host | smart-182b7624-1942-4f3c-be8f-8155a39a1e0f |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171762 0783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1717620783 |
Directory | /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1563700230 |
Short name | T993 |
Test name | |
Test status | |
Simulation time | 123572794 ps |
CPU time | 2.2 seconds |
Started | Jun 30 06:58:07 PM PDT 24 |
Finished | Jun 30 06:58:10 PM PDT 24 |
Peak memory | 209044 kb |
Host | smart-9f5e4bde-e0d0-4ca1-a969-6a375f593230 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563700230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_rw.1563700230 |
Directory | /workspace/3.lc_ctrl_jtag_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3985103110 |
Short name | T987 |
Test name | |
Test status | |
Simulation time | 49458235 ps |
CPU time | 0.91 seconds |
Started | Jun 30 06:58:11 PM PDT 24 |
Finished | Jun 30 06:58:13 PM PDT 24 |
Peak memory | 209128 kb |
Host | smart-4b7d3fd0-a8e8-4333-af0e-e732751baf49 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985103110 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.3985103110 |
Directory | /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2529936783 |
Short name | T964 |
Test name | |
Test status | |
Simulation time | 160820495 ps |
CPU time | 1.4 seconds |
Started | Jun 30 06:58:11 PM PDT 24 |
Finished | Jun 30 06:58:13 PM PDT 24 |
Peak memory | 217276 kb |
Host | smart-5fe7478d-cf16-45e3-b7b2-d9cae5ad0b49 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529936783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl _same_csr_outstanding.2529936783 |
Directory | /workspace/3.lc_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.798536587 |
Short name | T902 |
Test name | |
Test status | |
Simulation time | 69693362 ps |
CPU time | 1.46 seconds |
Started | Jun 30 06:58:05 PM PDT 24 |
Finished | Jun 30 06:58:07 PM PDT 24 |
Peak memory | 217348 kb |
Host | smart-24e976c2-9da3-4101-a329-123167e03669 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798536587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.798536587 |
Directory | /workspace/3.lc_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.993205522 |
Short name | T950 |
Test name | |
Test status | |
Simulation time | 63406276 ps |
CPU time | 2.55 seconds |
Started | Jun 30 06:58:06 PM PDT 24 |
Finished | Jun 30 06:58:09 PM PDT 24 |
Peak memory | 217336 kb |
Host | smart-f3adff37-dfc3-474a-873d-4bb51eb8a712 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993205522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_e rr.993205522 |
Directory | /workspace/3.lc_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.384179682 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 62842511 ps |
CPU time | 1.14 seconds |
Started | Jun 30 06:58:09 PM PDT 24 |
Finished | Jun 30 06:58:11 PM PDT 24 |
Peak memory | 209068 kb |
Host | smart-adefcda7-03a3-4d6f-8586-3373329653dd |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384179682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasing .384179682 |
Directory | /workspace/4.lc_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3404904883 |
Short name | T907 |
Test name | |
Test status | |
Simulation time | 355617396 ps |
CPU time | 3 seconds |
Started | Jun 30 06:58:07 PM PDT 24 |
Finished | Jun 30 06:58:11 PM PDT 24 |
Peak memory | 209124 kb |
Host | smart-30574332-bc44-4b7e-9e40-418c70a11113 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404904883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas h.3404904883 |
Directory | /workspace/4.lc_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3451009768 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 57122283 ps |
CPU time | 1.01 seconds |
Started | Jun 30 06:58:07 PM PDT 24 |
Finished | Jun 30 06:58:09 PM PDT 24 |
Peak memory | 210052 kb |
Host | smart-e2ebdc34-ef9b-4a0b-b7ba-1573f376a7f4 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451009768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese t.3451009768 |
Directory | /workspace/4.lc_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.4122205990 |
Short name | T986 |
Test name | |
Test status | |
Simulation time | 26034103 ps |
CPU time | 1.54 seconds |
Started | Jun 30 06:58:06 PM PDT 24 |
Finished | Jun 30 06:58:08 PM PDT 24 |
Peak memory | 217408 kb |
Host | smart-6a91e8cc-e7db-4eda-9e1b-f399f007ebfa |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122205990 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.4122205990 |
Directory | /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.4164116748 |
Short name | T919 |
Test name | |
Test status | |
Simulation time | 13060561 ps |
CPU time | 0.89 seconds |
Started | Jun 30 06:58:08 PM PDT 24 |
Finished | Jun 30 06:58:09 PM PDT 24 |
Peak memory | 208628 kb |
Host | smart-d7f924ed-c24a-4163-b06b-b4975d633552 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164116748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.4164116748 |
Directory | /workspace/4.lc_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2516178321 |
Short name | T933 |
Test name | |
Test status | |
Simulation time | 82836346 ps |
CPU time | 1.33 seconds |
Started | Jun 30 06:58:05 PM PDT 24 |
Finished | Jun 30 06:58:07 PM PDT 24 |
Peak memory | 208964 kb |
Host | smart-0a01d73b-389a-4231-bccc-13c0b05b199c |
User | root |
Command | /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516178321 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 4.lc_ctrl_jtag_alert_test.2516178321 |
Directory | /workspace/4.lc_ctrl_jtag_alert_test/latest |
Test location | /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2393445355 |
Short name | T927 |
Test name | |
Test status | |
Simulation time | 1161827025 ps |
CPU time | 5.83 seconds |
Started | Jun 30 06:58:05 PM PDT 24 |
Finished | Jun 30 06:58:12 PM PDT 24 |
Peak memory | 208724 kb |
Host | smart-85f2d5c8-ffd0-464d-9ea6-faa2b0300a6c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393445355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.2393445355 |
Directory | /workspace/4.lc_ctrl_jtag_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3570987310 |
Short name | T925 |
Test name | |
Test status | |
Simulation time | 7433594088 ps |
CPU time | 16.15 seconds |
Started | Jun 30 06:58:11 PM PDT 24 |
Finished | Jun 30 06:58:29 PM PDT 24 |
Peak memory | 216996 kb |
Host | smart-6eb84a58-e4ec-4fd1-943a-245babcb2a7a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570987310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.3570987310 |
Directory | /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.1650762732 |
Short name | T920 |
Test name | |
Test status | |
Simulation time | 246031706 ps |
CPU time | 1.4 seconds |
Started | Jun 30 06:58:04 PM PDT 24 |
Finished | Jun 30 06:58:07 PM PDT 24 |
Peak memory | 210476 kb |
Host | smart-1055569c-d626-40cb-92e3-23641cd84755 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650762732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.1650762732 |
Directory | /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3432444908 |
Short name | T916 |
Test name | |
Test status | |
Simulation time | 57624876 ps |
CPU time | 2.34 seconds |
Started | Jun 30 06:58:10 PM PDT 24 |
Finished | Jun 30 06:58:13 PM PDT 24 |
Peak memory | 217912 kb |
Host | smart-ed081ca0-ce4d-4a55-aef6-3c499fda24eb |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343244 4908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3432444908 |
Directory | /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2287135980 |
Short name | T968 |
Test name | |
Test status | |
Simulation time | 203217182 ps |
CPU time | 1.21 seconds |
Started | Jun 30 06:58:06 PM PDT 24 |
Finished | Jun 30 06:58:08 PM PDT 24 |
Peak memory | 209048 kb |
Host | smart-d9f7ed82-6dd9-46f1-a2b4-132f1f4fe1d7 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287135980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_rw.2287135980 |
Directory | /workspace/4.lc_ctrl_jtag_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.719117181 |
Short name | T958 |
Test name | |
Test status | |
Simulation time | 163658970 ps |
CPU time | 1.46 seconds |
Started | Jun 30 06:58:06 PM PDT 24 |
Finished | Jun 30 06:58:08 PM PDT 24 |
Peak memory | 217404 kb |
Host | smart-caafe4d5-7499-4014-a5fb-0eb437d10571 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719117181 -assert nopostproc +UVM_TESTNAM E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.719117181 |
Directory | /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1911455787 |
Short name | T942 |
Test name | |
Test status | |
Simulation time | 48855249 ps |
CPU time | 2.08 seconds |
Started | Jun 30 06:58:08 PM PDT 24 |
Finished | Jun 30 06:58:11 PM PDT 24 |
Peak memory | 211172 kb |
Host | smart-0f4c06cb-fcf1-4de7-89ad-67a2d621e88c |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911455787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl _same_csr_outstanding.1911455787 |
Directory | /workspace/4.lc_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2590607536 |
Short name | T894 |
Test name | |
Test status | |
Simulation time | 43000603 ps |
CPU time | 1.68 seconds |
Started | Jun 30 06:58:11 PM PDT 24 |
Finished | Jun 30 06:58:15 PM PDT 24 |
Peak memory | 217204 kb |
Host | smart-e7c2ae0f-e2eb-45d4-b1c1-5b957b17685d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590607536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.2590607536 |
Directory | /workspace/4.lc_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2429111306 |
Short name | T906 |
Test name | |
Test status | |
Simulation time | 172686646 ps |
CPU time | 1.44 seconds |
Started | Jun 30 06:58:15 PM PDT 24 |
Finished | Jun 30 06:58:17 PM PDT 24 |
Peak memory | 217324 kb |
Host | smart-55caeb50-2a33-492f-b29a-beaed0459af1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429111306 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.2429111306 |
Directory | /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2805332108 |
Short name | T881 |
Test name | |
Test status | |
Simulation time | 15920133 ps |
CPU time | 0.9 seconds |
Started | Jun 30 06:58:11 PM PDT 24 |
Finished | Jun 30 06:58:13 PM PDT 24 |
Peak memory | 209116 kb |
Host | smart-378bd582-b50e-41f1-a377-f3555f5a030d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805332108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.2805332108 |
Directory | /workspace/5.lc_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1739519999 |
Short name | T884 |
Test name | |
Test status | |
Simulation time | 103769084 ps |
CPU time | 1.09 seconds |
Started | Jun 30 06:58:13 PM PDT 24 |
Finished | Jun 30 06:58:16 PM PDT 24 |
Peak memory | 208976 kb |
Host | smart-b62608ae-f0d6-4ccb-919a-a02798adb06a |
User | root |
Command | /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739519999 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 5.lc_ctrl_jtag_alert_test.1739519999 |
Directory | /workspace/5.lc_ctrl_jtag_alert_test/latest |
Test location | /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.4124784748 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 1031323278 ps |
CPU time | 3.37 seconds |
Started | Jun 30 06:58:13 PM PDT 24 |
Finished | Jun 30 06:58:18 PM PDT 24 |
Peak memory | 208824 kb |
Host | smart-e154f160-54ba-47a9-b0df-bfbb3283212a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124784748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.4124784748 |
Directory | /workspace/5.lc_ctrl_jtag_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3379685974 |
Short name | T886 |
Test name | |
Test status | |
Simulation time | 2611955699 ps |
CPU time | 19.78 seconds |
Started | Jun 30 06:58:10 PM PDT 24 |
Finished | Jun 30 06:58:31 PM PDT 24 |
Peak memory | 217096 kb |
Host | smart-4e341a88-9ff9-4f37-8259-db36a2a0309a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379685974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.3379685974 |
Directory | /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2983469581 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 66865198 ps |
CPU time | 1.45 seconds |
Started | Jun 30 06:58:12 PM PDT 24 |
Finished | Jun 30 06:58:15 PM PDT 24 |
Peak memory | 217208 kb |
Host | smart-a24aa00e-c3eb-4e91-a458-e1f9b41fcf82 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983469581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.2983469581 |
Directory | /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1436150313 |
Short name | T983 |
Test name | |
Test status | |
Simulation time | 289659675 ps |
CPU time | 1.71 seconds |
Started | Jun 30 06:58:13 PM PDT 24 |
Finished | Jun 30 06:58:16 PM PDT 24 |
Peak memory | 218452 kb |
Host | smart-547fb1f2-8370-4499-9014-420c45ab9ce9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143615 0313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1436150313 |
Directory | /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1556787017 |
Short name | T885 |
Test name | |
Test status | |
Simulation time | 186579510 ps |
CPU time | 1.51 seconds |
Started | Jun 30 06:58:13 PM PDT 24 |
Finished | Jun 30 06:58:16 PM PDT 24 |
Peak memory | 209076 kb |
Host | smart-869eeea7-892b-468e-b9be-3ccb4d0af235 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556787017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_rw.1556787017 |
Directory | /workspace/5.lc_ctrl_jtag_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1244932164 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 24451149 ps |
CPU time | 1.3 seconds |
Started | Jun 30 06:58:15 PM PDT 24 |
Finished | Jun 30 06:58:17 PM PDT 24 |
Peak memory | 209184 kb |
Host | smart-be6793b7-dc10-4cac-8d79-e17bd6825743 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244932164 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.1244932164 |
Directory | /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2282594898 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 157031297 ps |
CPU time | 1.34 seconds |
Started | Jun 30 06:58:12 PM PDT 24 |
Finished | Jun 30 06:58:15 PM PDT 24 |
Peak memory | 209192 kb |
Host | smart-c74ce43b-fc2e-4eeb-a53b-cfbdd16afb47 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282594898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl _same_csr_outstanding.2282594898 |
Directory | /workspace/5.lc_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3359739881 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 224491774 ps |
CPU time | 2.19 seconds |
Started | Jun 30 06:58:11 PM PDT 24 |
Finished | Jun 30 06:58:15 PM PDT 24 |
Peak memory | 212796 kb |
Host | smart-67794239-31d0-4dc6-af39-abe8d78580f6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359739881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_ err.3359739881 |
Directory | /workspace/5.lc_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.123633107 |
Short name | T935 |
Test name | |
Test status | |
Simulation time | 30974876 ps |
CPU time | 1.02 seconds |
Started | Jun 30 06:58:14 PM PDT 24 |
Finished | Jun 30 06:58:16 PM PDT 24 |
Peak memory | 217388 kb |
Host | smart-00394ba5-417a-4819-ae93-91dba32cde8a |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123633107 -assert nopostproc +UVM_TESTNAME= lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.123633107 |
Directory | /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1018864048 |
Short name | T961 |
Test name | |
Test status | |
Simulation time | 35786523 ps |
CPU time | 1.02 seconds |
Started | Jun 30 06:58:13 PM PDT 24 |
Finished | Jun 30 06:58:15 PM PDT 24 |
Peak memory | 209104 kb |
Host | smart-98266ae5-6cd7-4d39-b4a5-359395d9c54e |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018864048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.1018864048 |
Directory | /workspace/6.lc_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.410556315 |
Short name | T954 |
Test name | |
Test status | |
Simulation time | 486380650 ps |
CPU time | 1.14 seconds |
Started | Jun 30 06:58:11 PM PDT 24 |
Finished | Jun 30 06:58:14 PM PDT 24 |
Peak memory | 209052 kb |
Host | smart-1a5a6288-e849-4eab-b1d0-d0b29310d6a9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410556315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 6.lc_ctrl_jtag_alert_test.410556315 |
Directory | /workspace/6.lc_ctrl_jtag_alert_test/latest |
Test location | /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1320404138 |
Short name | T929 |
Test name | |
Test status | |
Simulation time | 796630223 ps |
CPU time | 17.81 seconds |
Started | Jun 30 06:58:13 PM PDT 24 |
Finished | Jun 30 06:58:33 PM PDT 24 |
Peak memory | 208976 kb |
Host | smart-af4bc0ff-2127-424d-a309-92c53ec7b12b |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320404138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.1320404138 |
Directory | /workspace/6.lc_ctrl_jtag_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1511480394 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 1386233565 ps |
CPU time | 6.44 seconds |
Started | Jun 30 06:58:13 PM PDT 24 |
Finished | Jun 30 06:58:21 PM PDT 24 |
Peak memory | 208708 kb |
Host | smart-39560ef0-f657-402e-a0b8-7f193d8f2aaa |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511480394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.1511480394 |
Directory | /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2237238619 |
Short name | T973 |
Test name | |
Test status | |
Simulation time | 202018570 ps |
CPU time | 1.27 seconds |
Started | Jun 30 06:58:12 PM PDT 24 |
Finished | Jun 30 06:58:15 PM PDT 24 |
Peak memory | 217256 kb |
Host | smart-1ea91a03-3d60-48b4-9a92-cbabbe6e6377 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237238619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.2237238619 |
Directory | /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2804159227 |
Short name | T899 |
Test name | |
Test status | |
Simulation time | 406508225 ps |
CPU time | 3.38 seconds |
Started | Jun 30 06:58:16 PM PDT 24 |
Finished | Jun 30 06:58:20 PM PDT 24 |
Peak memory | 218112 kb |
Host | smart-02955eec-5cca-45c5-805d-daa6a0171ce7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280415 9227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2804159227 |
Directory | /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.2233632711 |
Short name | T887 |
Test name | |
Test status | |
Simulation time | 179729619 ps |
CPU time | 1.15 seconds |
Started | Jun 30 06:58:10 PM PDT 24 |
Finished | Jun 30 06:58:12 PM PDT 24 |
Peak memory | 208968 kb |
Host | smart-d929b351-c819-422d-8c6f-82ded82f442b |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233632711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_rw.2233632711 |
Directory | /workspace/6.lc_ctrl_jtag_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2271354191 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 42271508 ps |
CPU time | 1.4 seconds |
Started | Jun 30 06:58:15 PM PDT 24 |
Finished | Jun 30 06:58:17 PM PDT 24 |
Peak memory | 209160 kb |
Host | smart-bff297d1-4cda-4608-b38f-2d257fa48deb |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271354191 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.2271354191 |
Directory | /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.93773079 |
Short name | T996 |
Test name | |
Test status | |
Simulation time | 20423271 ps |
CPU time | 1.02 seconds |
Started | Jun 30 06:58:14 PM PDT 24 |
Finished | Jun 30 06:58:16 PM PDT 24 |
Peak memory | 209188 kb |
Host | smart-d6f4b6a9-ef33-4b41-8a68-5a8930027b43 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93773079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_s ame_csr_outstanding.93773079 |
Directory | /workspace/6.lc_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2793672095 |
Short name | T948 |
Test name | |
Test status | |
Simulation time | 44198653 ps |
CPU time | 2.69 seconds |
Started | Jun 30 06:58:11 PM PDT 24 |
Finished | Jun 30 06:58:15 PM PDT 24 |
Peak memory | 218392 kb |
Host | smart-97e60fd0-3049-4a0b-8011-fbe71f686d7b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793672095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.2793672095 |
Directory | /workspace/6.lc_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2756684013 |
Short name | T967 |
Test name | |
Test status | |
Simulation time | 16168613 ps |
CPU time | 1.28 seconds |
Started | Jun 30 06:58:16 PM PDT 24 |
Finished | Jun 30 06:58:18 PM PDT 24 |
Peak memory | 217536 kb |
Host | smart-e8dfeb1f-1f1a-4175-91ca-78930dc2c2a2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756684013 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.2756684013 |
Directory | /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.216449374 |
Short name | T879 |
Test name | |
Test status | |
Simulation time | 31717494 ps |
CPU time | 0.9 seconds |
Started | Jun 30 06:58:19 PM PDT 24 |
Finished | Jun 30 06:58:21 PM PDT 24 |
Peak memory | 208908 kb |
Host | smart-f8d174be-ea0a-4b3c-93a0-5986319bf0ae |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216449374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.216449374 |
Directory | /workspace/7.lc_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3477426215 |
Short name | T901 |
Test name | |
Test status | |
Simulation time | 108023861 ps |
CPU time | 3.11 seconds |
Started | Jun 30 06:58:11 PM PDT 24 |
Finished | Jun 30 06:58:16 PM PDT 24 |
Peak memory | 208968 kb |
Host | smart-834cf266-7aea-4660-8965-40686470ea76 |
User | root |
Command | /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477426215 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 7.lc_ctrl_jtag_alert_test.3477426215 |
Directory | /workspace/7.lc_ctrl_jtag_alert_test/latest |
Test location | /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3554075571 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 1023942166 ps |
CPU time | 5.34 seconds |
Started | Jun 30 06:58:10 PM PDT 24 |
Finished | Jun 30 06:58:17 PM PDT 24 |
Peak memory | 208968 kb |
Host | smart-035abaf8-a4c7-4086-b1aa-c4fd3cf5e867 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554075571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.3554075571 |
Directory | /workspace/7.lc_ctrl_jtag_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.3279312395 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 965510707 ps |
CPU time | 17.88 seconds |
Started | Jun 30 06:58:11 PM PDT 24 |
Finished | Jun 30 06:58:31 PM PDT 24 |
Peak memory | 208788 kb |
Host | smart-b47739d7-eb92-400c-a9d4-ac4534bea2f5 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279312395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.3279312395 |
Directory | /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2670782910 |
Short name | T908 |
Test name | |
Test status | |
Simulation time | 60060280 ps |
CPU time | 1.38 seconds |
Started | Jun 30 06:58:13 PM PDT 24 |
Finished | Jun 30 06:58:16 PM PDT 24 |
Peak memory | 210444 kb |
Host | smart-175f3338-1955-42a8-ab5a-ceb4818b65f5 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670782910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.2670782910 |
Directory | /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3838180446 |
Short name | T960 |
Test name | |
Test status | |
Simulation time | 324262337 ps |
CPU time | 1.51 seconds |
Started | Jun 30 06:58:13 PM PDT 24 |
Finished | Jun 30 06:58:16 PM PDT 24 |
Peak memory | 217496 kb |
Host | smart-63421872-e851-43ab-9937-ec9af0d639c2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383818 0446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3838180446 |
Directory | /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1584008570 |
Short name | T951 |
Test name | |
Test status | |
Simulation time | 156949301 ps |
CPU time | 1.14 seconds |
Started | Jun 30 06:58:12 PM PDT 24 |
Finished | Jun 30 06:58:15 PM PDT 24 |
Peak memory | 209012 kb |
Host | smart-f8c5e7d9-e275-4b91-b150-3c87583c55b9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584008570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_rw.1584008570 |
Directory | /workspace/7.lc_ctrl_jtag_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1486722803 |
Short name | T941 |
Test name | |
Test status | |
Simulation time | 199482856 ps |
CPU time | 2 seconds |
Started | Jun 30 06:58:13 PM PDT 24 |
Finished | Jun 30 06:58:16 PM PDT 24 |
Peak memory | 210928 kb |
Host | smart-1fde4322-854f-4c54-bb08-7123cfba4464 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486722803 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.1486722803 |
Directory | /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.4182267547 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 75311532 ps |
CPU time | 1.3 seconds |
Started | Jun 30 06:58:17 PM PDT 24 |
Finished | Jun 30 06:58:20 PM PDT 24 |
Peak memory | 211048 kb |
Host | smart-7c327798-0f67-460d-8bd2-c9a7ddfcc95a |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182267547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl _same_csr_outstanding.4182267547 |
Directory | /workspace/7.lc_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.336693169 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 46850091 ps |
CPU time | 3.19 seconds |
Started | Jun 30 06:58:11 PM PDT 24 |
Finished | Jun 30 06:58:16 PM PDT 24 |
Peak memory | 217240 kb |
Host | smart-009a3b84-7450-47ef-b9fb-f7afdb2c90dd |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336693169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.336693169 |
Directory | /workspace/7.lc_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2654688218 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 286497618 ps |
CPU time | 1.84 seconds |
Started | Jun 30 06:58:19 PM PDT 24 |
Finished | Jun 30 06:58:22 PM PDT 24 |
Peak memory | 221536 kb |
Host | smart-1bf964b1-8fbf-40bf-9e5d-1187a063a301 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654688218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_ err.2654688218 |
Directory | /workspace/7.lc_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.13772001 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 24635495 ps |
CPU time | 1.53 seconds |
Started | Jun 30 06:58:19 PM PDT 24 |
Finished | Jun 30 06:58:21 PM PDT 24 |
Peak memory | 217392 kb |
Host | smart-b2b4e9cd-0fb0-46fa-99e9-0e4ee35b8612 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13772001 -assert nopostproc +UVM_TESTNAME=l c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.13772001 |
Directory | /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1166205701 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 54217613 ps |
CPU time | 1.02 seconds |
Started | Jun 30 06:58:21 PM PDT 24 |
Finished | Jun 30 06:58:22 PM PDT 24 |
Peak memory | 208808 kb |
Host | smart-4cef22cf-44fe-4637-ad18-f6471b5c73ff |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166205701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.1166205701 |
Directory | /workspace/8.lc_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1721399213 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 695124174 ps |
CPU time | 1.82 seconds |
Started | Jun 30 06:58:19 PM PDT 24 |
Finished | Jun 30 06:58:22 PM PDT 24 |
Peak memory | 208952 kb |
Host | smart-3ae8af4c-29f7-4be0-80be-ba8cce0b9bd5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721399213 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 8.lc_ctrl_jtag_alert_test.1721399213 |
Directory | /workspace/8.lc_ctrl_jtag_alert_test/latest |
Test location | /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1206441073 |
Short name | T940 |
Test name | |
Test status | |
Simulation time | 884922573 ps |
CPU time | 9.09 seconds |
Started | Jun 30 06:58:18 PM PDT 24 |
Finished | Jun 30 06:58:28 PM PDT 24 |
Peak memory | 208748 kb |
Host | smart-49a9ab4b-c59b-4839-8d98-f2a759410a52 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206441073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.1206441073 |
Directory | /workspace/8.lc_ctrl_jtag_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1837292394 |
Short name | T893 |
Test name | |
Test status | |
Simulation time | 2482282172 ps |
CPU time | 12.48 seconds |
Started | Jun 30 06:58:18 PM PDT 24 |
Finished | Jun 30 06:58:31 PM PDT 24 |
Peak memory | 209008 kb |
Host | smart-822fe42b-4ce8-41ff-99c6-b7445bbabe5a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837292394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.1837292394 |
Directory | /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.133806044 |
Short name | T932 |
Test name | |
Test status | |
Simulation time | 120540993 ps |
CPU time | 2.09 seconds |
Started | Jun 30 06:58:19 PM PDT 24 |
Finished | Jun 30 06:58:22 PM PDT 24 |
Peak memory | 210508 kb |
Host | smart-5a24e701-4f87-41f5-be2c-3f186e9bcf9a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133806044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.133806044 |
Directory | /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.269965514 |
Short name | T955 |
Test name | |
Test status | |
Simulation time | 253654245 ps |
CPU time | 6.19 seconds |
Started | Jun 30 06:58:19 PM PDT 24 |
Finished | Jun 30 06:58:26 PM PDT 24 |
Peak memory | 217500 kb |
Host | smart-d90b69df-0700-4365-ab2d-2821d4b745a4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269965 514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.269965514 |
Directory | /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.189409219 |
Short name | T890 |
Test name | |
Test status | |
Simulation time | 165689830 ps |
CPU time | 1.49 seconds |
Started | Jun 30 06:58:16 PM PDT 24 |
Finished | Jun 30 06:58:19 PM PDT 24 |
Peak memory | 209224 kb |
Host | smart-d940b10f-3b72-4986-9bd9-d6e10222cb03 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189409219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_rw.189409219 |
Directory | /workspace/8.lc_ctrl_jtag_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.4052528862 |
Short name | T903 |
Test name | |
Test status | |
Simulation time | 36296210 ps |
CPU time | 1.08 seconds |
Started | Jun 30 06:58:17 PM PDT 24 |
Finished | Jun 30 06:58:19 PM PDT 24 |
Peak memory | 209152 kb |
Host | smart-ecd4018f-8c20-4889-892f-a69e2fe647ea |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052528862 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.4052528862 |
Directory | /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.9659395 |
Short name | T962 |
Test name | |
Test status | |
Simulation time | 17163294 ps |
CPU time | 1.34 seconds |
Started | Jun 30 06:58:17 PM PDT 24 |
Finished | Jun 30 06:58:20 PM PDT 24 |
Peak memory | 209404 kb |
Host | smart-c90ff06a-6238-4a77-80b4-29f8500a968e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9659395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sa me_csr_outstanding.9659395 |
Directory | /workspace/8.lc_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1068569365 |
Short name | T898 |
Test name | |
Test status | |
Simulation time | 102987836 ps |
CPU time | 1.44 seconds |
Started | Jun 30 06:58:17 PM PDT 24 |
Finished | Jun 30 06:58:20 PM PDT 24 |
Peak memory | 217400 kb |
Host | smart-1e4d4188-9987-4ac0-a2ba-720feda734a3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068569365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.1068569365 |
Directory | /workspace/8.lc_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.802464441 |
Short name | T965 |
Test name | |
Test status | |
Simulation time | 26515726 ps |
CPU time | 1.2 seconds |
Started | Jun 30 06:58:17 PM PDT 24 |
Finished | Jun 30 06:58:20 PM PDT 24 |
Peak memory | 217452 kb |
Host | smart-d5a93b2f-1386-413f-b640-c2048e8de4c4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802464441 -assert nopostproc +UVM_TESTNAME= lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.802464441 |
Directory | /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.2054643262 |
Short name | T918 |
Test name | |
Test status | |
Simulation time | 15440390 ps |
CPU time | 0.89 seconds |
Started | Jun 30 06:58:19 PM PDT 24 |
Finished | Jun 30 06:58:21 PM PDT 24 |
Peak memory | 209120 kb |
Host | smart-8ae0555e-a385-4a83-957a-00ecb069db9d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054643262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.2054643262 |
Directory | /workspace/9.lc_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2622750890 |
Short name | T945 |
Test name | |
Test status | |
Simulation time | 65724871 ps |
CPU time | 1.04 seconds |
Started | Jun 30 06:58:17 PM PDT 24 |
Finished | Jun 30 06:58:19 PM PDT 24 |
Peak memory | 208980 kb |
Host | smart-d13a7cb2-6129-49da-bf83-27d8c0f9e812 |
User | root |
Command | /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622750890 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 9.lc_ctrl_jtag_alert_test.2622750890 |
Directory | /workspace/9.lc_ctrl_jtag_alert_test/latest |
Test location | /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3280425640 |
Short name | T975 |
Test name | |
Test status | |
Simulation time | 6304542449 ps |
CPU time | 18.17 seconds |
Started | Jun 30 06:58:17 PM PDT 24 |
Finished | Jun 30 06:58:36 PM PDT 24 |
Peak memory | 217128 kb |
Host | smart-dd2490d6-1291-423e-8784-ecc35c7b4aa1 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280425640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.3280425640 |
Directory | /workspace/9.lc_ctrl_jtag_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.210048835 |
Short name | T990 |
Test name | |
Test status | |
Simulation time | 3379551013 ps |
CPU time | 8.65 seconds |
Started | Jun 30 06:58:18 PM PDT 24 |
Finished | Jun 30 06:58:28 PM PDT 24 |
Peak memory | 209120 kb |
Host | smart-48124e58-f4e3-4d0f-820c-109f45ba29c3 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210048835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.210048835 |
Directory | /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1794832270 |
Short name | T928 |
Test name | |
Test status | |
Simulation time | 213767471 ps |
CPU time | 2.67 seconds |
Started | Jun 30 06:58:17 PM PDT 24 |
Finished | Jun 30 06:58:21 PM PDT 24 |
Peak memory | 210804 kb |
Host | smart-76f1cc1b-d6ba-4495-af9c-6b5a5a126366 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794832270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.1794832270 |
Directory | /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.662782578 |
Short name | T924 |
Test name | |
Test status | |
Simulation time | 98523800 ps |
CPU time | 1.52 seconds |
Started | Jun 30 06:58:16 PM PDT 24 |
Finished | Jun 30 06:58:19 PM PDT 24 |
Peak memory | 217356 kb |
Host | smart-80eb45c3-3388-4523-bc9b-be0cd71f6886 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662782 578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.662782578 |
Directory | /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2007145240 |
Short name | T980 |
Test name | |
Test status | |
Simulation time | 66510964 ps |
CPU time | 1.52 seconds |
Started | Jun 30 06:58:16 PM PDT 24 |
Finished | Jun 30 06:58:19 PM PDT 24 |
Peak memory | 209060 kb |
Host | smart-0e10c9cd-0263-41fc-9d52-621e75244061 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007145240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_rw.2007145240 |
Directory | /workspace/9.lc_ctrl_jtag_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2804612009 |
Short name | T926 |
Test name | |
Test status | |
Simulation time | 124907274 ps |
CPU time | 1.22 seconds |
Started | Jun 30 06:58:15 PM PDT 24 |
Finished | Jun 30 06:58:18 PM PDT 24 |
Peak memory | 209108 kb |
Host | smart-294cda18-391b-442c-9ce1-f4188a601213 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804612009 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.2804612009 |
Directory | /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.641493944 |
Short name | T914 |
Test name | |
Test status | |
Simulation time | 27791477 ps |
CPU time | 1.21 seconds |
Started | Jun 30 06:58:16 PM PDT 24 |
Finished | Jun 30 06:58:18 PM PDT 24 |
Peak memory | 209280 kb |
Host | smart-fb8bae25-3f35-4f5c-90b4-92e274c0df53 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641493944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_ same_csr_outstanding.641493944 |
Directory | /workspace/9.lc_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.564174501 |
Short name | T977 |
Test name | |
Test status | |
Simulation time | 516229272 ps |
CPU time | 2.32 seconds |
Started | Jun 30 06:58:18 PM PDT 24 |
Finished | Jun 30 06:58:22 PM PDT 24 |
Peak memory | 217220 kb |
Host | smart-3c2b5471-99ec-49d1-8b96-40ad3e8a67bf |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564174501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.564174501 |
Directory | /workspace/9.lc_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3479020414 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 347962234 ps |
CPU time | 3.55 seconds |
Started | Jun 30 06:58:17 PM PDT 24 |
Finished | Jun 30 06:58:21 PM PDT 24 |
Peak memory | 217220 kb |
Host | smart-1c899c21-1de1-4b75-acb1-be60916551fa |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479020414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_ err.3479020414 |
Directory | /workspace/9.lc_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.lc_ctrl_alert_test.606087790 |
Short name | T293 |
Test name | |
Test status | |
Simulation time | 15041383 ps |
CPU time | 0.97 seconds |
Started | Jun 30 06:54:46 PM PDT 24 |
Finished | Jun 30 06:54:49 PM PDT 24 |
Peak memory | 209360 kb |
Host | smart-688b4a25-783b-49ba-967a-49771a5a1ddf |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606087790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.606087790 |
Directory | /workspace/0.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/0.lc_ctrl_errors.3041079763 |
Short name | T711 |
Test name | |
Test status | |
Simulation time | 1784090536 ps |
CPU time | 14.26 seconds |
Started | Jun 30 06:54:45 PM PDT 24 |
Finished | Jun 30 06:55:02 PM PDT 24 |
Peak memory | 218876 kb |
Host | smart-c229b1c9-16fb-42d3-ac50-fa64f9047c06 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3041079763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.3041079763 |
Directory | /workspace/0.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/0.lc_ctrl_jtag_access.2272129943 |
Short name | T728 |
Test name | |
Test status | |
Simulation time | 124142911 ps |
CPU time | 3.95 seconds |
Started | Jun 30 06:54:46 PM PDT 24 |
Finished | Jun 30 06:54:52 PM PDT 24 |
Peak memory | 217440 kb |
Host | smart-315840a4-575a-44eb-a734-2b03d707cf01 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272129943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.2272129943 |
Directory | /workspace/0.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/0.lc_ctrl_jtag_errors.3201206725 |
Short name | T299 |
Test name | |
Test status | |
Simulation time | 6072361559 ps |
CPU time | 45.06 seconds |
Started | Jun 30 06:54:46 PM PDT 24 |
Finished | Jun 30 06:55:33 PM PDT 24 |
Peak memory | 219292 kb |
Host | smart-44ae27ae-db3c-4c96-92ba-e9a3f536f609 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201206725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er rors.3201206725 |
Directory | /workspace/0.lc_ctrl_jtag_errors/latest |
Test location | /workspace/coverage/default/0.lc_ctrl_jtag_priority.3673669569 |
Short name | T475 |
Test name | |
Test status | |
Simulation time | 664643682 ps |
CPU time | 6.55 seconds |
Started | Jun 30 06:54:47 PM PDT 24 |
Finished | Jun 30 06:54:55 PM PDT 24 |
Peak memory | 218104 kb |
Host | smart-857b10bd-0035-4eb3-9345-72dd7c0da620 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673669569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.3 673669569 |
Directory | /workspace/0.lc_ctrl_jtag_priority/latest |
Test location | /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.2532151765 |
Short name | T588 |
Test name | |
Test status | |
Simulation time | 1796593106 ps |
CPU time | 24.34 seconds |
Started | Jun 30 06:54:46 PM PDT 24 |
Finished | Jun 30 06:55:12 PM PDT 24 |
Peak memory | 219224 kb |
Host | smart-56b8176e-2c77-4ee4-a788-4a7f2997e815 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532151765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag _prog_failure.2532151765 |
Directory | /workspace/0.lc_ctrl_jtag_prog_failure/latest |
Test location | /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.856280576 |
Short name | T286 |
Test name | |
Test status | |
Simulation time | 1190144647 ps |
CPU time | 33.48 seconds |
Started | Jun 30 06:54:46 PM PDT 24 |
Finished | Jun 30 06:55:22 PM PDT 24 |
Peak memory | 217956 kb |
Host | smart-d080e941-d594-49c0-a4a5-e795a1696819 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856280576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j tag_regwen_during_op.856280576 |
Directory | /workspace/0.lc_ctrl_jtag_regwen_during_op/latest |
Test location | /workspace/coverage/default/0.lc_ctrl_jtag_smoke.2281407793 |
Short name | T758 |
Test name | |
Test status | |
Simulation time | 198570066 ps |
CPU time | 6.14 seconds |
Started | Jun 30 06:54:45 PM PDT 24 |
Finished | Jun 30 06:54:52 PM PDT 24 |
Peak memory | 218004 kb |
Host | smart-f373ce79-cb7f-40e8-ba18-7526a336a8a3 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281407793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke. 2281407793 |
Directory | /workspace/0.lc_ctrl_jtag_smoke/latest |
Test location | /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.602361621 |
Short name | T485 |
Test name | |
Test status | |
Simulation time | 4131640372 ps |
CPU time | 82.39 seconds |
Started | Jun 30 06:54:47 PM PDT 24 |
Finished | Jun 30 06:56:11 PM PDT 24 |
Peak memory | 284092 kb |
Host | smart-218285dc-639c-429d-8d39-0323b4675778 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602361621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag _state_failure.602361621 |
Directory | /workspace/0.lc_ctrl_jtag_state_failure/latest |
Test location | /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.3738276130 |
Short name | T745 |
Test name | |
Test status | |
Simulation time | 2344185334 ps |
CPU time | 14.06 seconds |
Started | Jun 30 06:54:50 PM PDT 24 |
Finished | Jun 30 06:55:04 PM PDT 24 |
Peak memory | 251324 kb |
Host | smart-a991077c-bb93-485a-95f3-a42a66570885 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738276130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_ jtag_state_post_trans.3738276130 |
Directory | /workspace/0.lc_ctrl_jtag_state_post_trans/latest |
Test location | /workspace/coverage/default/0.lc_ctrl_prog_failure.3980790131 |
Short name | T395 |
Test name | |
Test status | |
Simulation time | 376290216 ps |
CPU time | 2.92 seconds |
Started | Jun 30 06:54:47 PM PDT 24 |
Finished | Jun 30 06:54:51 PM PDT 24 |
Peak memory | 218632 kb |
Host | smart-dc6f861e-18f7-4c70-b2d1-b53efbb8c5a6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3980790131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.3980790131 |
Directory | /workspace/0.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/0.lc_ctrl_regwen_during_op.3435394861 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 1732755165 ps |
CPU time | 9.55 seconds |
Started | Jun 30 06:54:45 PM PDT 24 |
Finished | Jun 30 06:54:56 PM PDT 24 |
Peak memory | 215000 kb |
Host | smart-b6697005-78d2-4905-a838-8cf2ffed6ac7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3435394861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.3435394861 |
Directory | /workspace/0.lc_ctrl_regwen_during_op/latest |
Test location | /workspace/coverage/default/0.lc_ctrl_sec_mubi.502640972 |
Short name | T876 |
Test name | |
Test status | |
Simulation time | 1044386242 ps |
CPU time | 12.91 seconds |
Started | Jun 30 06:54:49 PM PDT 24 |
Finished | Jun 30 06:55:03 PM PDT 24 |
Peak memory | 226412 kb |
Host | smart-15755133-2cc8-4e64-9355-84e405c2d186 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502640972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.502640972 |
Directory | /workspace/0.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/0.lc_ctrl_sec_token_digest.4077413052 |
Short name | T350 |
Test name | |
Test status | |
Simulation time | 202909897 ps |
CPU time | 7.55 seconds |
Started | Jun 30 06:54:48 PM PDT 24 |
Finished | Jun 30 06:54:56 PM PDT 24 |
Peak memory | 218572 kb |
Host | smart-ecfd92d1-111a-4488-be34-5c2ce45d1174 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077413052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di gest.4077413052 |
Directory | /workspace/0.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/0.lc_ctrl_sec_token_mux.456584269 |
Short name | T442 |
Test name | |
Test status | |
Simulation time | 197382639 ps |
CPU time | 6.11 seconds |
Started | Jun 30 06:54:47 PM PDT 24 |
Finished | Jun 30 06:54:54 PM PDT 24 |
Peak memory | 225052 kb |
Host | smart-fa65c73b-39d0-4a62-9f2a-06f2507619d8 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456584269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.456584269 |
Directory | /workspace/0.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/0.lc_ctrl_security_escalation.4158556984 |
Short name | T375 |
Test name | |
Test status | |
Simulation time | 264837302 ps |
CPU time | 6.93 seconds |
Started | Jun 30 06:54:44 PM PDT 24 |
Finished | Jun 30 06:54:52 PM PDT 24 |
Peak memory | 218792 kb |
Host | smart-6c8c82c2-d5b2-49de-a989-586b15bc3f46 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4158556984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.4158556984 |
Directory | /workspace/0.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/0.lc_ctrl_smoke.2347238269 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 87804855 ps |
CPU time | 1.14 seconds |
Started | Jun 30 06:54:40 PM PDT 24 |
Finished | Jun 30 06:54:42 PM PDT 24 |
Peak memory | 222048 kb |
Host | smart-0def66df-5785-4edd-8848-9bfbb125fd74 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2347238269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.2347238269 |
Directory | /workspace/0.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/0.lc_ctrl_state_failure.3269627284 |
Short name | T451 |
Test name | |
Test status | |
Simulation time | 891668243 ps |
CPU time | 18.28 seconds |
Started | Jun 30 06:54:41 PM PDT 24 |
Finished | Jun 30 06:55:00 PM PDT 24 |
Peak memory | 251340 kb |
Host | smart-8cc24c8c-8883-4b6d-bfaa-89a4cbacc876 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3269627284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.3269627284 |
Directory | /workspace/0.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/0.lc_ctrl_state_post_trans.899248028 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 223496075 ps |
CPU time | 8.82 seconds |
Started | Jun 30 06:54:48 PM PDT 24 |
Finished | Jun 30 06:54:58 PM PDT 24 |
Peak memory | 251332 kb |
Host | smart-af59c862-67b6-417d-bf88-f7a58dfe72d7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=899248028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.899248028 |
Directory | /workspace/0.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/0.lc_ctrl_stress_all.2315654565 |
Short name | T694 |
Test name | |
Test status | |
Simulation time | 10918088262 ps |
CPU time | 59.92 seconds |
Started | Jun 30 06:54:49 PM PDT 24 |
Finished | Jun 30 06:55:50 PM PDT 24 |
Peak memory | 251492 kb |
Host | smart-1d99f15f-3a29-4fbc-900f-2934249e55ec |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315654565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all.2315654565 |
Directory | /workspace/0.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.631559798 |
Short name | T345 |
Test name | |
Test status | |
Simulation time | 12081822 ps |
CPU time | 0.82 seconds |
Started | Jun 30 06:54:42 PM PDT 24 |
Finished | Jun 30 06:54:43 PM PDT 24 |
Peak memory | 209216 kb |
Host | smart-080d73fc-cee5-4a0f-8bce-4cc7c908cbbd |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631559798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctr l_volatile_unlock_smoke.631559798 |
Directory | /workspace/0.lc_ctrl_volatile_unlock_smoke/latest |
Test location | /workspace/coverage/default/1.lc_ctrl_alert_test.95396774 |
Short name | T714 |
Test name | |
Test status | |
Simulation time | 216433071 ps |
CPU time | 1.04 seconds |
Started | Jun 30 06:54:54 PM PDT 24 |
Finished | Jun 30 06:54:55 PM PDT 24 |
Peak memory | 209384 kb |
Host | smart-0171a1a4-79a9-4d40-b239-8270a9e05c56 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95396774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.95396774 |
Directory | /workspace/1.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/1.lc_ctrl_claim_transition_if.4009523428 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 13144444 ps |
CPU time | 0.81 seconds |
Started | Jun 30 06:54:49 PM PDT 24 |
Finished | Jun 30 06:54:51 PM PDT 24 |
Peak memory | 209056 kb |
Host | smart-d554a17b-b1dc-4321-8881-e243a2eec13e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4009523428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.4009523428 |
Directory | /workspace/1.lc_ctrl_claim_transition_if/latest |
Test location | /workspace/coverage/default/1.lc_ctrl_errors.202319457 |
Short name | T801 |
Test name | |
Test status | |
Simulation time | 514748131 ps |
CPU time | 12.31 seconds |
Started | Jun 30 06:54:46 PM PDT 24 |
Finished | Jun 30 06:55:00 PM PDT 24 |
Peak memory | 218580 kb |
Host | smart-92370e37-aee5-41c6-ab8d-f8b1680f24cc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=202319457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.202319457 |
Directory | /workspace/1.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/1.lc_ctrl_jtag_access.3868679935 |
Short name | T702 |
Test name | |
Test status | |
Simulation time | 347351034 ps |
CPU time | 9.56 seconds |
Started | Jun 30 06:54:53 PM PDT 24 |
Finished | Jun 30 06:55:03 PM PDT 24 |
Peak memory | 217688 kb |
Host | smart-8f4bf57b-a5fc-4181-b3ef-4337652439de |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868679935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.3868679935 |
Directory | /workspace/1.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/1.lc_ctrl_jtag_errors.3357791051 |
Short name | T532 |
Test name | |
Test status | |
Simulation time | 5605836049 ps |
CPU time | 41.24 seconds |
Started | Jun 30 06:54:51 PM PDT 24 |
Finished | Jun 30 06:55:34 PM PDT 24 |
Peak memory | 219228 kb |
Host | smart-cdc20480-3b56-4301-98d8-ae53a7bfc36f |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357791051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er rors.3357791051 |
Directory | /workspace/1.lc_ctrl_jtag_errors/latest |
Test location | /workspace/coverage/default/1.lc_ctrl_jtag_priority.67288926 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 1284676624 ps |
CPU time | 4.44 seconds |
Started | Jun 30 06:54:51 PM PDT 24 |
Finished | Jun 30 06:54:57 PM PDT 24 |
Peak memory | 218112 kb |
Host | smart-2ccc96b0-f9b6-48a4-b45f-7b6e0327b276 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67288926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.67288926 |
Directory | /workspace/1.lc_ctrl_jtag_priority/latest |
Test location | /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.2668297969 |
Short name | T781 |
Test name | |
Test status | |
Simulation time | 181202357 ps |
CPU time | 6.11 seconds |
Started | Jun 30 06:54:56 PM PDT 24 |
Finished | Jun 30 06:55:02 PM PDT 24 |
Peak memory | 218576 kb |
Host | smart-6cb032e7-3f4b-435a-a8a5-799f4d3d5c31 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668297969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag _prog_failure.2668297969 |
Directory | /workspace/1.lc_ctrl_jtag_prog_failure/latest |
Test location | /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.3709538571 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 3334331711 ps |
CPU time | 24.53 seconds |
Started | Jun 30 06:54:53 PM PDT 24 |
Finished | Jun 30 06:55:18 PM PDT 24 |
Peak memory | 218128 kb |
Host | smart-5eaa1505-5aa1-4312-b634-071c5e483d6c |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709538571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_ jtag_regwen_during_op.3709538571 |
Directory | /workspace/1.lc_ctrl_jtag_regwen_during_op/latest |
Test location | /workspace/coverage/default/1.lc_ctrl_jtag_smoke.3018525366 |
Short name | T328 |
Test name | |
Test status | |
Simulation time | 1247124442 ps |
CPU time | 5.14 seconds |
Started | Jun 30 06:54:45 PM PDT 24 |
Finished | Jun 30 06:54:51 PM PDT 24 |
Peak memory | 217980 kb |
Host | smart-7a8c791f-c4ee-4085-b957-56e349ee9ba4 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018525366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke. 3018525366 |
Directory | /workspace/1.lc_ctrl_jtag_smoke/latest |
Test location | /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.3349671034 |
Short name | T670 |
Test name | |
Test status | |
Simulation time | 16466391916 ps |
CPU time | 46.61 seconds |
Started | Jun 30 06:54:52 PM PDT 24 |
Finished | Jun 30 06:55:40 PM PDT 24 |
Peak memory | 251328 kb |
Host | smart-029da764-328d-46e6-83b7-13d60a196222 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349671034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta g_state_failure.3349671034 |
Directory | /workspace/1.lc_ctrl_jtag_state_failure/latest |
Test location | /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.1199825760 |
Short name | T776 |
Test name | |
Test status | |
Simulation time | 1303787515 ps |
CPU time | 16.36 seconds |
Started | Jun 30 06:54:52 PM PDT 24 |
Finished | Jun 30 06:55:10 PM PDT 24 |
Peak memory | 251280 kb |
Host | smart-0fac663b-ca38-42df-aff5-997d106b0f1d |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199825760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_ jtag_state_post_trans.1199825760 |
Directory | /workspace/1.lc_ctrl_jtag_state_post_trans/latest |
Test location | /workspace/coverage/default/1.lc_ctrl_prog_failure.1224413246 |
Short name | T337 |
Test name | |
Test status | |
Simulation time | 280322794 ps |
CPU time | 3.34 seconds |
Started | Jun 30 06:54:48 PM PDT 24 |
Finished | Jun 30 06:54:52 PM PDT 24 |
Peak memory | 218636 kb |
Host | smart-c21415e8-d6b7-4bf7-a43d-7659c4220c77 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1224413246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.1224413246 |
Directory | /workspace/1.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/1.lc_ctrl_regwen_during_op.2202059024 |
Short name | T473 |
Test name | |
Test status | |
Simulation time | 689642386 ps |
CPU time | 16.65 seconds |
Started | Jun 30 06:54:50 PM PDT 24 |
Finished | Jun 30 06:55:08 PM PDT 24 |
Peak memory | 215020 kb |
Host | smart-853a9c1c-5bc0-4dc1-af1c-aa2c2c5da4bb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2202059024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.2202059024 |
Directory | /workspace/1.lc_ctrl_regwen_during_op/latest |
Test location | /workspace/coverage/default/1.lc_ctrl_sec_cm.2762286903 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 432961596 ps |
CPU time | 36.94 seconds |
Started | Jun 30 06:54:52 PM PDT 24 |
Finished | Jun 30 06:55:30 PM PDT 24 |
Peak memory | 282220 kb |
Host | smart-e8d8e94b-ca0c-44ae-a770-620ae982d496 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762286903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.2762286903 |
Directory | /workspace/1.lc_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/1.lc_ctrl_sec_mubi.4221397009 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 2930824141 ps |
CPU time | 10.76 seconds |
Started | Jun 30 06:54:51 PM PDT 24 |
Finished | Jun 30 06:55:03 PM PDT 24 |
Peak memory | 226460 kb |
Host | smart-3a08019f-ae46-456e-9e62-2e368a9afec7 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221397009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.4221397009 |
Directory | /workspace/1.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/1.lc_ctrl_sec_token_digest.1942065575 |
Short name | T506 |
Test name | |
Test status | |
Simulation time | 663509482 ps |
CPU time | 11.2 seconds |
Started | Jun 30 06:54:52 PM PDT 24 |
Finished | Jun 30 06:55:04 PM PDT 24 |
Peak memory | 218676 kb |
Host | smart-97bfea2e-3eb1-4d01-b34d-ff00767e97d9 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942065575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di gest.1942065575 |
Directory | /workspace/1.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/1.lc_ctrl_sec_token_mux.4043003311 |
Short name | T632 |
Test name | |
Test status | |
Simulation time | 294122584 ps |
CPU time | 11.34 seconds |
Started | Jun 30 06:54:55 PM PDT 24 |
Finished | Jun 30 06:55:07 PM PDT 24 |
Peak memory | 218592 kb |
Host | smart-8d5e4b9c-0d0e-4969-8931-2699a511ff04 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043003311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.4 043003311 |
Directory | /workspace/1.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/1.lc_ctrl_security_escalation.1839912253 |
Short name | T462 |
Test name | |
Test status | |
Simulation time | 1247761993 ps |
CPU time | 7.71 seconds |
Started | Jun 30 06:54:49 PM PDT 24 |
Finished | Jun 30 06:54:58 PM PDT 24 |
Peak memory | 225420 kb |
Host | smart-5f23e45b-535b-4225-9805-5795229a6a98 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1839912253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.1839912253 |
Directory | /workspace/1.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/1.lc_ctrl_smoke.575855589 |
Short name | T387 |
Test name | |
Test status | |
Simulation time | 704790204 ps |
CPU time | 6.92 seconds |
Started | Jun 30 06:54:47 PM PDT 24 |
Finished | Jun 30 06:54:55 PM PDT 24 |
Peak memory | 218020 kb |
Host | smart-7cb84a2f-8f6f-4c47-b838-9e62745873a0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=575855589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.575855589 |
Directory | /workspace/1.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/1.lc_ctrl_state_failure.3559529152 |
Short name | T402 |
Test name | |
Test status | |
Simulation time | 320138167 ps |
CPU time | 23.44 seconds |
Started | Jun 30 06:54:46 PM PDT 24 |
Finished | Jun 30 06:55:11 PM PDT 24 |
Peak memory | 251336 kb |
Host | smart-ee1f8366-bc67-4c15-9da1-b33271f100c5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3559529152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.3559529152 |
Directory | /workspace/1.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/1.lc_ctrl_state_post_trans.3795849877 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 493427889 ps |
CPU time | 3.52 seconds |
Started | Jun 30 06:54:46 PM PDT 24 |
Finished | Jun 30 06:54:51 PM PDT 24 |
Peak memory | 222816 kb |
Host | smart-cb424d76-823c-4d49-b5b6-f28e30fba9c4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3795849877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.3795849877 |
Directory | /workspace/1.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/1.lc_ctrl_stress_all.2019211664 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 3031602207 ps |
CPU time | 84.72 seconds |
Started | Jun 30 06:54:51 PM PDT 24 |
Finished | Jun 30 06:56:17 PM PDT 24 |
Peak memory | 251384 kb |
Host | smart-bedfba28-0e68-43ad-839f-a19ef6990b78 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019211664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all.2019211664 |
Directory | /workspace/1.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.3462857356 |
Short name | T606 |
Test name | |
Test status | |
Simulation time | 21109302785 ps |
CPU time | 183.49 seconds |
Started | Jun 30 06:54:51 PM PDT 24 |
Finished | Jun 30 06:57:55 PM PDT 24 |
Peak memory | 251460 kb |
Host | smart-87242e22-7a32-4e3e-880d-109f8665e1de |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3462857356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all_with_rand_reset.3462857356 |
Directory | /workspace/1.lc_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.439493840 |
Short name | T343 |
Test name | |
Test status | |
Simulation time | 14333397 ps |
CPU time | 0.8 seconds |
Started | Jun 30 06:54:47 PM PDT 24 |
Finished | Jun 30 06:54:49 PM PDT 24 |
Peak memory | 209160 kb |
Host | smart-3a7b6ef9-b7d6-4eb5-af31-1942075eafb3 |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439493840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctr l_volatile_unlock_smoke.439493840 |
Directory | /workspace/1.lc_ctrl_volatile_unlock_smoke/latest |
Test location | /workspace/coverage/default/10.lc_ctrl_alert_test.3169685819 |
Short name | T717 |
Test name | |
Test status | |
Simulation time | 27006644 ps |
CPU time | 1.37 seconds |
Started | Jun 30 06:55:43 PM PDT 24 |
Finished | Jun 30 06:55:47 PM PDT 24 |
Peak memory | 209364 kb |
Host | smart-5a1eb629-608d-473f-bef1-7dad365a6d59 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169685819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.3169685819 |
Directory | /workspace/10.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/10.lc_ctrl_errors.3386203822 |
Short name | T296 |
Test name | |
Test status | |
Simulation time | 2642959361 ps |
CPU time | 17.2 seconds |
Started | Jun 30 06:55:38 PM PDT 24 |
Finished | Jun 30 06:55:58 PM PDT 24 |
Peak memory | 226496 kb |
Host | smart-42febf5d-66a6-4b0e-9d73-26c4204680c5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3386203822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.3386203822 |
Directory | /workspace/10.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/10.lc_ctrl_jtag_access.3383516604 |
Short name | T421 |
Test name | |
Test status | |
Simulation time | 3114122002 ps |
CPU time | 15.4 seconds |
Started | Jun 30 06:55:43 PM PDT 24 |
Finished | Jun 30 06:56:01 PM PDT 24 |
Peak memory | 218140 kb |
Host | smart-55dee95b-1880-4fd3-b653-c0bdb2b07a8f |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383516604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.3383516604 |
Directory | /workspace/10.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/10.lc_ctrl_jtag_errors.1892257969 |
Short name | T291 |
Test name | |
Test status | |
Simulation time | 11348818807 ps |
CPU time | 42.03 seconds |
Started | Jun 30 06:55:43 PM PDT 24 |
Finished | Jun 30 06:56:27 PM PDT 24 |
Peak memory | 219240 kb |
Host | smart-d908d077-83ae-46cc-887f-e6c8fdaec185 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892257969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e rrors.1892257969 |
Directory | /workspace/10.lc_ctrl_jtag_errors/latest |
Test location | /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.1313021892 |
Short name | T537 |
Test name | |
Test status | |
Simulation time | 594038068 ps |
CPU time | 6.55 seconds |
Started | Jun 30 06:55:43 PM PDT 24 |
Finished | Jun 30 06:55:52 PM PDT 24 |
Peak memory | 218560 kb |
Host | smart-02cc5de7-a10f-43a4-8f4c-b63c2a2ce11d |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313021892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta g_prog_failure.1313021892 |
Directory | /workspace/10.lc_ctrl_jtag_prog_failure/latest |
Test location | /workspace/coverage/default/10.lc_ctrl_jtag_smoke.991780432 |
Short name | T383 |
Test name | |
Test status | |
Simulation time | 461036044 ps |
CPU time | 8.21 seconds |
Started | Jun 30 06:55:42 PM PDT 24 |
Finished | Jun 30 06:55:53 PM PDT 24 |
Peak memory | 217948 kb |
Host | smart-4fb8fdc3-0fa4-4b86-a91d-67ed0529969d |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991780432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke. 991780432 |
Directory | /workspace/10.lc_ctrl_jtag_smoke/latest |
Test location | /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.3456118790 |
Short name | T478 |
Test name | |
Test status | |
Simulation time | 3628804209 ps |
CPU time | 34.36 seconds |
Started | Jun 30 06:55:42 PM PDT 24 |
Finished | Jun 30 06:56:20 PM PDT 24 |
Peak memory | 275912 kb |
Host | smart-abadaceb-e9a1-4373-bfd7-0a1368ae129c |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456118790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt ag_state_failure.3456118790 |
Directory | /workspace/10.lc_ctrl_jtag_state_failure/latest |
Test location | /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.1434264721 |
Short name | T446 |
Test name | |
Test status | |
Simulation time | 371423028 ps |
CPU time | 12.28 seconds |
Started | Jun 30 06:55:43 PM PDT 24 |
Finished | Jun 30 06:55:58 PM PDT 24 |
Peak memory | 247616 kb |
Host | smart-24781bc1-ab11-4f54-90af-c1cfa350ed32 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434264721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl _jtag_state_post_trans.1434264721 |
Directory | /workspace/10.lc_ctrl_jtag_state_post_trans/latest |
Test location | /workspace/coverage/default/10.lc_ctrl_prog_failure.439635473 |
Short name | T358 |
Test name | |
Test status | |
Simulation time | 116437009 ps |
CPU time | 1.98 seconds |
Started | Jun 30 06:55:36 PM PDT 24 |
Finished | Jun 30 06:55:39 PM PDT 24 |
Peak memory | 222496 kb |
Host | smart-a6fdfc5d-6f5e-4564-ac1b-18d5d9551e6f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=439635473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.439635473 |
Directory | /workspace/10.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/10.lc_ctrl_sec_mubi.2935527170 |
Short name | T795 |
Test name | |
Test status | |
Simulation time | 357870109 ps |
CPU time | 15.92 seconds |
Started | Jun 30 06:55:42 PM PDT 24 |
Finished | Jun 30 06:56:01 PM PDT 24 |
Peak memory | 226440 kb |
Host | smart-8bb9da0b-c060-42e4-b6db-21cbe0e0bb87 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935527170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.2935527170 |
Directory | /workspace/10.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/10.lc_ctrl_sec_token_digest.847304556 |
Short name | T443 |
Test name | |
Test status | |
Simulation time | 264369624 ps |
CPU time | 8.63 seconds |
Started | Jun 30 06:55:44 PM PDT 24 |
Finished | Jun 30 06:55:55 PM PDT 24 |
Peak memory | 218844 kb |
Host | smart-0d7b14fa-b393-4170-a8e4-c39233bd13b2 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847304556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_di gest.847304556 |
Directory | /workspace/10.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/10.lc_ctrl_sec_token_mux.1317329282 |
Short name | T409 |
Test name | |
Test status | |
Simulation time | 749281289 ps |
CPU time | 11.16 seconds |
Started | Jun 30 06:55:41 PM PDT 24 |
Finished | Jun 30 06:55:56 PM PDT 24 |
Peak memory | 218560 kb |
Host | smart-b7e67795-b7b5-4163-ab9b-cd69a8555793 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317329282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux. 1317329282 |
Directory | /workspace/10.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/10.lc_ctrl_security_escalation.471789233 |
Short name | T651 |
Test name | |
Test status | |
Simulation time | 345583283 ps |
CPU time | 9.04 seconds |
Started | Jun 30 06:55:43 PM PDT 24 |
Finished | Jun 30 06:55:55 PM PDT 24 |
Peak memory | 218704 kb |
Host | smart-e3aba99c-fa27-4df4-b07d-cd0656fe9a56 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=471789233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.471789233 |
Directory | /workspace/10.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/10.lc_ctrl_smoke.163264499 |
Short name | T543 |
Test name | |
Test status | |
Simulation time | 24009856 ps |
CPU time | 1.63 seconds |
Started | Jun 30 06:55:38 PM PDT 24 |
Finished | Jun 30 06:55:42 PM PDT 24 |
Peak memory | 214252 kb |
Host | smart-dab2d882-bf99-4b61-8eb2-22787cb5f182 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=163264499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.163264499 |
Directory | /workspace/10.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/10.lc_ctrl_state_failure.2998736141 |
Short name | T773 |
Test name | |
Test status | |
Simulation time | 1508157856 ps |
CPU time | 33.04 seconds |
Started | Jun 30 06:55:35 PM PDT 24 |
Finished | Jun 30 06:56:09 PM PDT 24 |
Peak memory | 251280 kb |
Host | smart-81a623ac-0e31-4b17-8e1c-836a07f93507 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2998736141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.2998736141 |
Directory | /workspace/10.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/10.lc_ctrl_state_post_trans.2979200884 |
Short name | T740 |
Test name | |
Test status | |
Simulation time | 682052652 ps |
CPU time | 6.97 seconds |
Started | Jun 30 06:55:39 PM PDT 24 |
Finished | Jun 30 06:55:48 PM PDT 24 |
Peak memory | 249552 kb |
Host | smart-31e9326c-1c30-46c1-abca-5e21949d7344 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2979200884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.2979200884 |
Directory | /workspace/10.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/10.lc_ctrl_stress_all.4196898584 |
Short name | T529 |
Test name | |
Test status | |
Simulation time | 4727959123 ps |
CPU time | 96.06 seconds |
Started | Jun 30 06:55:45 PM PDT 24 |
Finished | Jun 30 06:57:23 PM PDT 24 |
Peak memory | 281964 kb |
Host | smart-b04fc309-a1b2-4131-b757-c85628fe8701 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196898584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all.4196898584 |
Directory | /workspace/10.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.2193154113 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 9379186662 ps |
CPU time | 220.12 seconds |
Started | Jun 30 06:55:41 PM PDT 24 |
Finished | Jun 30 06:59:24 PM PDT 24 |
Peak memory | 272648 kb |
Host | smart-333f5fb3-2a1d-4d0d-b9ba-ea6fa8926f35 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2193154113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.2193154113 |
Directory | /workspace/10.lc_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/11.lc_ctrl_alert_test.2358302208 |
Short name | T549 |
Test name | |
Test status | |
Simulation time | 200021626 ps |
CPU time | 0.91 seconds |
Started | Jun 30 06:55:49 PM PDT 24 |
Finished | Jun 30 06:55:52 PM PDT 24 |
Peak memory | 209612 kb |
Host | smart-53b890ca-8b74-4fa7-93a0-27064a459f4b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358302208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.2358302208 |
Directory | /workspace/11.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/11.lc_ctrl_errors.2834589318 |
Short name | T348 |
Test name | |
Test status | |
Simulation time | 1417497102 ps |
CPU time | 12.28 seconds |
Started | Jun 30 06:55:42 PM PDT 24 |
Finished | Jun 30 06:55:57 PM PDT 24 |
Peak memory | 226436 kb |
Host | smart-e7796657-6af8-455c-840f-e41c59926b36 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2834589318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.2834589318 |
Directory | /workspace/11.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/11.lc_ctrl_jtag_access.2752935748 |
Short name | T307 |
Test name | |
Test status | |
Simulation time | 236213617 ps |
CPU time | 4.62 seconds |
Started | Jun 30 06:55:48 PM PDT 24 |
Finished | Jun 30 06:55:54 PM PDT 24 |
Peak memory | 217420 kb |
Host | smart-5aeffebd-5aea-41fe-96f4-446a1d44ef79 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752935748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.2752935748 |
Directory | /workspace/11.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/11.lc_ctrl_jtag_errors.503725227 |
Short name | T710 |
Test name | |
Test status | |
Simulation time | 1283353091 ps |
CPU time | 21.1 seconds |
Started | Jun 30 06:55:49 PM PDT 24 |
Finished | Jun 30 06:56:12 PM PDT 24 |
Peak memory | 218616 kb |
Host | smart-f4615a5c-1fd0-4ed0-8417-509ca08a0ef3 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503725227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_er rors.503725227 |
Directory | /workspace/11.lc_ctrl_jtag_errors/latest |
Test location | /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.2279256783 |
Short name | T527 |
Test name | |
Test status | |
Simulation time | 419521643 ps |
CPU time | 7.71 seconds |
Started | Jun 30 06:55:51 PM PDT 24 |
Finished | Jun 30 06:56:02 PM PDT 24 |
Peak memory | 218560 kb |
Host | smart-bf780441-6b80-4b81-a43f-b703bba57d11 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279256783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta g_prog_failure.2279256783 |
Directory | /workspace/11.lc_ctrl_jtag_prog_failure/latest |
Test location | /workspace/coverage/default/11.lc_ctrl_jtag_smoke.3463150814 |
Short name | T678 |
Test name | |
Test status | |
Simulation time | 200446540 ps |
CPU time | 6.28 seconds |
Started | Jun 30 06:55:41 PM PDT 24 |
Finished | Jun 30 06:55:50 PM PDT 24 |
Peak memory | 217984 kb |
Host | smart-3e604ec3-9833-43de-8fa1-1f2846e0b7f7 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463150814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke .3463150814 |
Directory | /workspace/11.lc_ctrl_jtag_smoke/latest |
Test location | /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.271987183 |
Short name | T672 |
Test name | |
Test status | |
Simulation time | 8267788960 ps |
CPU time | 78.49 seconds |
Started | Jun 30 06:55:49 PM PDT 24 |
Finished | Jun 30 06:57:10 PM PDT 24 |
Peak memory | 283980 kb |
Host | smart-8a44e0f2-4151-452b-b019-9713b735a758 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271987183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta g_state_failure.271987183 |
Directory | /workspace/11.lc_ctrl_jtag_state_failure/latest |
Test location | /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.803697727 |
Short name | T422 |
Test name | |
Test status | |
Simulation time | 665454556 ps |
CPU time | 16.58 seconds |
Started | Jun 30 06:55:50 PM PDT 24 |
Finished | Jun 30 06:56:10 PM PDT 24 |
Peak memory | 251288 kb |
Host | smart-e6f7270c-0634-4af3-b3cf-898dc141c38f |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803697727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_ jtag_state_post_trans.803697727 |
Directory | /workspace/11.lc_ctrl_jtag_state_post_trans/latest |
Test location | /workspace/coverage/default/11.lc_ctrl_prog_failure.1484721341 |
Short name | T321 |
Test name | |
Test status | |
Simulation time | 87046929 ps |
CPU time | 2.86 seconds |
Started | Jun 30 06:55:40 PM PDT 24 |
Finished | Jun 30 06:55:46 PM PDT 24 |
Peak memory | 218636 kb |
Host | smart-9c09e2db-d1be-44bb-bc6b-e632fc8b0e14 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1484721341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.1484721341 |
Directory | /workspace/11.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/11.lc_ctrl_sec_mubi.3484425284 |
Short name | T817 |
Test name | |
Test status | |
Simulation time | 457975120 ps |
CPU time | 12.48 seconds |
Started | Jun 30 06:55:50 PM PDT 24 |
Finished | Jun 30 06:56:06 PM PDT 24 |
Peak memory | 226444 kb |
Host | smart-d307cdcd-43a2-44e3-903e-e430b5901522 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484425284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.3484425284 |
Directory | /workspace/11.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/11.lc_ctrl_sec_token_digest.2584184800 |
Short name | T761 |
Test name | |
Test status | |
Simulation time | 919973554 ps |
CPU time | 9.48 seconds |
Started | Jun 30 06:55:51 PM PDT 24 |
Finished | Jun 30 06:56:05 PM PDT 24 |
Peak memory | 218256 kb |
Host | smart-37485f3d-b607-46c9-8db6-9139276f7018 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584184800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d igest.2584184800 |
Directory | /workspace/11.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/11.lc_ctrl_security_escalation.1969383530 |
Short name | T826 |
Test name | |
Test status | |
Simulation time | 299436388 ps |
CPU time | 10.81 seconds |
Started | Jun 30 06:55:42 PM PDT 24 |
Finished | Jun 30 06:55:55 PM PDT 24 |
Peak memory | 226460 kb |
Host | smart-1501159c-db39-4231-be77-053bd6cad6e3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1969383530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.1969383530 |
Directory | /workspace/11.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/11.lc_ctrl_smoke.4106757988 |
Short name | T645 |
Test name | |
Test status | |
Simulation time | 396373535 ps |
CPU time | 2.41 seconds |
Started | Jun 30 06:55:41 PM PDT 24 |
Finished | Jun 30 06:55:46 PM PDT 24 |
Peak memory | 214472 kb |
Host | smart-4d0d778e-a680-4490-a884-cb8b55d279f6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4106757988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.4106757988 |
Directory | /workspace/11.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/11.lc_ctrl_state_failure.1851746844 |
Short name | T658 |
Test name | |
Test status | |
Simulation time | 303998586 ps |
CPU time | 29.72 seconds |
Started | Jun 30 06:55:40 PM PDT 24 |
Finished | Jun 30 06:56:12 PM PDT 24 |
Peak memory | 251316 kb |
Host | smart-30ee26c1-70fe-4a95-a8a9-079d362cb2d2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1851746844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.1851746844 |
Directory | /workspace/11.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/11.lc_ctrl_state_post_trans.2945881499 |
Short name | T641 |
Test name | |
Test status | |
Simulation time | 191692607 ps |
CPU time | 6.69 seconds |
Started | Jun 30 06:55:44 PM PDT 24 |
Finished | Jun 30 06:55:53 PM PDT 24 |
Peak memory | 247100 kb |
Host | smart-72020e48-b1a9-47f0-8526-58eb2fa2fdda |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2945881499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.2945881499 |
Directory | /workspace/11.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/11.lc_ctrl_stress_all.1861190208 |
Short name | T297 |
Test name | |
Test status | |
Simulation time | 7533850510 ps |
CPU time | 108.33 seconds |
Started | Jun 30 06:55:50 PM PDT 24 |
Finished | Jun 30 06:57:42 PM PDT 24 |
Peak memory | 224544 kb |
Host | smart-646ca989-6838-4883-848a-82eeed32a6db |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861190208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all.1861190208 |
Directory | /workspace/11.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.626035749 |
Short name | T372 |
Test name | |
Test status | |
Simulation time | 11551374 ps |
CPU time | 0.93 seconds |
Started | Jun 30 06:55:42 PM PDT 24 |
Finished | Jun 30 06:55:46 PM PDT 24 |
Peak memory | 209304 kb |
Host | smart-2770216d-1958-4e3b-8ba2-eabcf7dd1213 |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626035749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ct rl_volatile_unlock_smoke.626035749 |
Directory | /workspace/11.lc_ctrl_volatile_unlock_smoke/latest |
Test location | /workspace/coverage/default/12.lc_ctrl_alert_test.696384814 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 21767048 ps |
CPU time | 0.88 seconds |
Started | Jun 30 06:55:52 PM PDT 24 |
Finished | Jun 30 06:55:57 PM PDT 24 |
Peak memory | 209328 kb |
Host | smart-80222b4d-dd45-4298-a77e-41f4b4c1199c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696384814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.696384814 |
Directory | /workspace/12.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/12.lc_ctrl_errors.102869618 |
Short name | T798 |
Test name | |
Test status | |
Simulation time | 713533248 ps |
CPU time | 16.72 seconds |
Started | Jun 30 06:55:52 PM PDT 24 |
Finished | Jun 30 06:56:12 PM PDT 24 |
Peak memory | 218636 kb |
Host | smart-ef606241-f17b-4873-a2f2-f1cf3c8d270e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=102869618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.102869618 |
Directory | /workspace/12.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/12.lc_ctrl_jtag_access.3100645514 |
Short name | T630 |
Test name | |
Test status | |
Simulation time | 5096053786 ps |
CPU time | 8.71 seconds |
Started | Jun 30 06:55:50 PM PDT 24 |
Finished | Jun 30 06:56:02 PM PDT 24 |
Peak memory | 218108 kb |
Host | smart-851b9b3e-f6eb-45f5-a2d0-1a19bbaea71d |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100645514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.3100645514 |
Directory | /workspace/12.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/12.lc_ctrl_jtag_errors.370763365 |
Short name | T411 |
Test name | |
Test status | |
Simulation time | 16650063599 ps |
CPU time | 27.89 seconds |
Started | Jun 30 06:55:50 PM PDT 24 |
Finished | Jun 30 06:56:22 PM PDT 24 |
Peak memory | 219248 kb |
Host | smart-f30d70d0-2a09-4a30-9bb1-5f842db9e842 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370763365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_er rors.370763365 |
Directory | /workspace/12.lc_ctrl_jtag_errors/latest |
Test location | /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.4253425763 |
Short name | T391 |
Test name | |
Test status | |
Simulation time | 491310813 ps |
CPU time | 4.98 seconds |
Started | Jun 30 06:55:52 PM PDT 24 |
Finished | Jun 30 06:56:01 PM PDT 24 |
Peak memory | 218576 kb |
Host | smart-f3b41b23-e61a-405d-a106-df0e0d456da7 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253425763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta g_prog_failure.4253425763 |
Directory | /workspace/12.lc_ctrl_jtag_prog_failure/latest |
Test location | /workspace/coverage/default/12.lc_ctrl_jtag_smoke.3721967717 |
Short name | T734 |
Test name | |
Test status | |
Simulation time | 2861119983 ps |
CPU time | 8.98 seconds |
Started | Jun 30 06:55:51 PM PDT 24 |
Finished | Jun 30 06:56:03 PM PDT 24 |
Peak memory | 218036 kb |
Host | smart-3184a841-960d-4f40-aad9-ddc7f5cbb028 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721967717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke .3721967717 |
Directory | /workspace/12.lc_ctrl_jtag_smoke/latest |
Test location | /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.197036740 |
Short name | T841 |
Test name | |
Test status | |
Simulation time | 1607851858 ps |
CPU time | 64.7 seconds |
Started | Jun 30 06:55:51 PM PDT 24 |
Finished | Jun 30 06:57:00 PM PDT 24 |
Peak memory | 267576 kb |
Host | smart-c1f9fe66-31cb-41f4-bd29-0ed7317ed546 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197036740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta g_state_failure.197036740 |
Directory | /workspace/12.lc_ctrl_jtag_state_failure/latest |
Test location | /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.1403441131 |
Short name | T423 |
Test name | |
Test status | |
Simulation time | 883615195 ps |
CPU time | 6.39 seconds |
Started | Jun 30 06:55:51 PM PDT 24 |
Finished | Jun 30 06:56:01 PM PDT 24 |
Peak memory | 226668 kb |
Host | smart-77166420-f550-4a1a-9f66-5afe6deba637 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403441131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl _jtag_state_post_trans.1403441131 |
Directory | /workspace/12.lc_ctrl_jtag_state_post_trans/latest |
Test location | /workspace/coverage/default/12.lc_ctrl_prog_failure.4033413209 |
Short name | T780 |
Test name | |
Test status | |
Simulation time | 65364782 ps |
CPU time | 3.6 seconds |
Started | Jun 30 06:55:50 PM PDT 24 |
Finished | Jun 30 06:55:56 PM PDT 24 |
Peak memory | 222932 kb |
Host | smart-e406ae8b-e081-4b57-9a40-edafedf0ad43 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4033413209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.4033413209 |
Directory | /workspace/12.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/12.lc_ctrl_sec_mubi.3081762744 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 547834955 ps |
CPU time | 11.19 seconds |
Started | Jun 30 06:55:51 PM PDT 24 |
Finished | Jun 30 06:56:06 PM PDT 24 |
Peak memory | 226436 kb |
Host | smart-345846cf-eaa0-4c86-a803-df4000101b36 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081762744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.3081762744 |
Directory | /workspace/12.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/12.lc_ctrl_sec_token_digest.3086393448 |
Short name | T289 |
Test name | |
Test status | |
Simulation time | 1138355825 ps |
CPU time | 14.55 seconds |
Started | Jun 30 06:55:51 PM PDT 24 |
Finished | Jun 30 06:56:09 PM PDT 24 |
Peak memory | 218604 kb |
Host | smart-97c26816-1e60-441d-9f91-d87b6ec89cde |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086393448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d igest.3086393448 |
Directory | /workspace/12.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/12.lc_ctrl_sec_token_mux.3307893114 |
Short name | T280 |
Test name | |
Test status | |
Simulation time | 358868127 ps |
CPU time | 9.02 seconds |
Started | Jun 30 06:55:52 PM PDT 24 |
Finished | Jun 30 06:56:05 PM PDT 24 |
Peak memory | 218592 kb |
Host | smart-fd0740f9-f67a-4e5d-abba-91642536f345 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307893114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux. 3307893114 |
Directory | /workspace/12.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/12.lc_ctrl_security_escalation.672057243 |
Short name | T403 |
Test name | |
Test status | |
Simulation time | 1656901542 ps |
CPU time | 14.12 seconds |
Started | Jun 30 06:55:50 PM PDT 24 |
Finished | Jun 30 06:56:08 PM PDT 24 |
Peak memory | 226440 kb |
Host | smart-93e0da8e-77d1-45d8-80d5-fd9a4e3c6104 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=672057243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.672057243 |
Directory | /workspace/12.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/12.lc_ctrl_smoke.2565056086 |
Short name | T413 |
Test name | |
Test status | |
Simulation time | 26469725 ps |
CPU time | 1.76 seconds |
Started | Jun 30 06:55:50 PM PDT 24 |
Finished | Jun 30 06:55:55 PM PDT 24 |
Peak memory | 214428 kb |
Host | smart-98273465-7ac8-45c9-8279-61db612de677 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2565056086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.2565056086 |
Directory | /workspace/12.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/12.lc_ctrl_state_failure.2215834208 |
Short name | T875 |
Test name | |
Test status | |
Simulation time | 232705796 ps |
CPU time | 25.39 seconds |
Started | Jun 30 06:55:51 PM PDT 24 |
Finished | Jun 30 06:56:20 PM PDT 24 |
Peak memory | 251324 kb |
Host | smart-94a7af59-817b-4bd8-aa92-ac6e17608e3d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2215834208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.2215834208 |
Directory | /workspace/12.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/12.lc_ctrl_state_post_trans.3843858623 |
Short name | T491 |
Test name | |
Test status | |
Simulation time | 89814698 ps |
CPU time | 6.02 seconds |
Started | Jun 30 06:55:50 PM PDT 24 |
Finished | Jun 30 06:56:00 PM PDT 24 |
Peak memory | 247312 kb |
Host | smart-31015d77-1ead-45db-b48b-51704a3d6a16 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3843858623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.3843858623 |
Directory | /workspace/12.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/12.lc_ctrl_stress_all.3576742631 |
Short name | T522 |
Test name | |
Test status | |
Simulation time | 4730281087 ps |
CPU time | 160.87 seconds |
Started | Jun 30 06:55:51 PM PDT 24 |
Finished | Jun 30 06:58:36 PM PDT 24 |
Peak memory | 226444 kb |
Host | smart-54c70a16-587e-4227-999f-cc7d2a44e4ba |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576742631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all.3576742631 |
Directory | /workspace/12.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.2258715375 |
Short name | T362 |
Test name | |
Test status | |
Simulation time | 36163439 ps |
CPU time | 0.9 seconds |
Started | Jun 30 06:55:51 PM PDT 24 |
Finished | Jun 30 06:55:56 PM PDT 24 |
Peak memory | 209228 kb |
Host | smart-0c7a91ae-ac0d-46a5-90d3-dad56e1be1b6 |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258715375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c trl_volatile_unlock_smoke.2258715375 |
Directory | /workspace/12.lc_ctrl_volatile_unlock_smoke/latest |
Test location | /workspace/coverage/default/13.lc_ctrl_alert_test.4176272605 |
Short name | T524 |
Test name | |
Test status | |
Simulation time | 33357203 ps |
CPU time | 0.85 seconds |
Started | Jun 30 06:56:03 PM PDT 24 |
Finished | Jun 30 06:56:06 PM PDT 24 |
Peak memory | 209348 kb |
Host | smart-a58d5158-0e64-4819-9dd5-2bc89d3d10e9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176272605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.4176272605 |
Directory | /workspace/13.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/13.lc_ctrl_errors.526277806 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 283619780 ps |
CPU time | 12.67 seconds |
Started | Jun 30 06:56:00 PM PDT 24 |
Finished | Jun 30 06:56:15 PM PDT 24 |
Peak memory | 218584 kb |
Host | smart-a77cfcd6-fa8a-42aa-b989-d8de5bddbf65 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=526277806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.526277806 |
Directory | /workspace/13.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/13.lc_ctrl_jtag_access.2520989497 |
Short name | T557 |
Test name | |
Test status | |
Simulation time | 562795465 ps |
CPU time | 13.4 seconds |
Started | Jun 30 06:56:00 PM PDT 24 |
Finished | Jun 30 06:56:16 PM PDT 24 |
Peak memory | 217688 kb |
Host | smart-35dc91c3-53f4-4574-99ae-b2e67cebdd53 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520989497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.2520989497 |
Directory | /workspace/13.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/13.lc_ctrl_jtag_errors.3469303787 |
Short name | T435 |
Test name | |
Test status | |
Simulation time | 1053704746 ps |
CPU time | 33.13 seconds |
Started | Jun 30 06:56:00 PM PDT 24 |
Finished | Jun 30 06:56:35 PM PDT 24 |
Peak memory | 218420 kb |
Host | smart-1c24f686-0971-49c6-8707-933eaa204486 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469303787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e rrors.3469303787 |
Directory | /workspace/13.lc_ctrl_jtag_errors/latest |
Test location | /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.763986685 |
Short name | T459 |
Test name | |
Test status | |
Simulation time | 1459526204 ps |
CPU time | 11.82 seconds |
Started | Jun 30 06:56:19 PM PDT 24 |
Finished | Jun 30 06:56:35 PM PDT 24 |
Peak memory | 218556 kb |
Host | smart-476df12e-f4cb-4064-af4f-527157afdb1a |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763986685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag _prog_failure.763986685 |
Directory | /workspace/13.lc_ctrl_jtag_prog_failure/latest |
Test location | /workspace/coverage/default/13.lc_ctrl_jtag_smoke.3946306336 |
Short name | T752 |
Test name | |
Test status | |
Simulation time | 831833481 ps |
CPU time | 7.91 seconds |
Started | Jun 30 06:55:59 PM PDT 24 |
Finished | Jun 30 06:56:09 PM PDT 24 |
Peak memory | 218072 kb |
Host | smart-1ae91fdc-ebdd-4177-bcb2-6e470cad6a5e |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946306336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke .3946306336 |
Directory | /workspace/13.lc_ctrl_jtag_smoke/latest |
Test location | /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.3179801811 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 5075079117 ps |
CPU time | 43.59 seconds |
Started | Jun 30 06:56:01 PM PDT 24 |
Finished | Jun 30 06:56:47 PM PDT 24 |
Peak memory | 275904 kb |
Host | smart-16312bd5-410f-4ce2-bae3-e746c8f3d6c0 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179801811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt ag_state_failure.3179801811 |
Directory | /workspace/13.lc_ctrl_jtag_state_failure/latest |
Test location | /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.148591323 |
Short name | T852 |
Test name | |
Test status | |
Simulation time | 2288211011 ps |
CPU time | 15.89 seconds |
Started | Jun 30 06:55:59 PM PDT 24 |
Finished | Jun 30 06:56:17 PM PDT 24 |
Peak memory | 224220 kb |
Host | smart-afcbbf94-60fa-491b-a8d4-67f79d5855ae |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148591323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_ jtag_state_post_trans.148591323 |
Directory | /workspace/13.lc_ctrl_jtag_state_post_trans/latest |
Test location | /workspace/coverage/default/13.lc_ctrl_prog_failure.3062838412 |
Short name | T315 |
Test name | |
Test status | |
Simulation time | 173911228 ps |
CPU time | 2.36 seconds |
Started | Jun 30 06:55:59 PM PDT 24 |
Finished | Jun 30 06:56:03 PM PDT 24 |
Peak memory | 218624 kb |
Host | smart-12e636c9-4c08-43dc-8aa4-3bab3ce686fa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3062838412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.3062838412 |
Directory | /workspace/13.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/13.lc_ctrl_sec_mubi.205723770 |
Short name | T625 |
Test name | |
Test status | |
Simulation time | 370008152 ps |
CPU time | 14.1 seconds |
Started | Jun 30 06:56:02 PM PDT 24 |
Finished | Jun 30 06:56:18 PM PDT 24 |
Peak memory | 226460 kb |
Host | smart-165ba80c-cd27-4aaa-ac78-cd5a6714624c |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205723770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.205723770 |
Directory | /workspace/13.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/13.lc_ctrl_sec_token_digest.1458321588 |
Short name | T432 |
Test name | |
Test status | |
Simulation time | 1005761922 ps |
CPU time | 11.98 seconds |
Started | Jun 30 06:56:01 PM PDT 24 |
Finished | Jun 30 06:56:15 PM PDT 24 |
Peak memory | 218668 kb |
Host | smart-e0e87730-0ed4-4168-a360-015e073381a7 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458321588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d igest.1458321588 |
Directory | /workspace/13.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/13.lc_ctrl_sec_token_mux.1724041845 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 793553191 ps |
CPU time | 10.99 seconds |
Started | Jun 30 06:56:02 PM PDT 24 |
Finished | Jun 30 06:56:16 PM PDT 24 |
Peak memory | 226384 kb |
Host | smart-6bebeb33-fe0d-41ec-aeb5-6f9ad61c2786 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724041845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux. 1724041845 |
Directory | /workspace/13.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/13.lc_ctrl_security_escalation.885776929 |
Short name | T566 |
Test name | |
Test status | |
Simulation time | 445282937 ps |
CPU time | 12.35 seconds |
Started | Jun 30 06:55:59 PM PDT 24 |
Finished | Jun 30 06:56:13 PM PDT 24 |
Peak memory | 225744 kb |
Host | smart-18bd3ebb-3064-4ea4-8d33-8e9f5b0fbab1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=885776929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.885776929 |
Directory | /workspace/13.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/13.lc_ctrl_smoke.1778452048 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 411301950 ps |
CPU time | 5.36 seconds |
Started | Jun 30 06:55:52 PM PDT 24 |
Finished | Jun 30 06:56:01 PM PDT 24 |
Peak memory | 218028 kb |
Host | smart-6bcb3afc-7872-4f87-b178-ce6f9738b028 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1778452048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.1778452048 |
Directory | /workspace/13.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/13.lc_ctrl_state_failure.4176279936 |
Short name | T863 |
Test name | |
Test status | |
Simulation time | 201397878 ps |
CPU time | 27.36 seconds |
Started | Jun 30 06:55:58 PM PDT 24 |
Finished | Jun 30 06:56:27 PM PDT 24 |
Peak memory | 251240 kb |
Host | smart-3f06b3db-3283-44d7-accb-af1d3a78d427 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4176279936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.4176279936 |
Directory | /workspace/13.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/13.lc_ctrl_state_post_trans.2599253505 |
Short name | T575 |
Test name | |
Test status | |
Simulation time | 206110347 ps |
CPU time | 8.96 seconds |
Started | Jun 30 06:55:59 PM PDT 24 |
Finished | Jun 30 06:56:09 PM PDT 24 |
Peak memory | 251288 kb |
Host | smart-40bc5299-61e0-4518-9a13-81aab1c1f69c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2599253505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.2599253505 |
Directory | /workspace/13.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/13.lc_ctrl_stress_all.1797427666 |
Short name | T609 |
Test name | |
Test status | |
Simulation time | 2139500726 ps |
CPU time | 64.68 seconds |
Started | Jun 30 06:56:03 PM PDT 24 |
Finished | Jun 30 06:57:10 PM PDT 24 |
Peak memory | 267672 kb |
Host | smart-bf5b0b46-0f29-4780-97b9-468fe56a3453 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797427666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all.1797427666 |
Directory | /workspace/13.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.654906617 |
Short name | T384 |
Test name | |
Test status | |
Simulation time | 119804671 ps |
CPU time | 0.96 seconds |
Started | Jun 30 06:56:01 PM PDT 24 |
Finished | Jun 30 06:56:04 PM PDT 24 |
Peak memory | 213240 kb |
Host | smart-eb11528d-5ed6-4ce2-a71c-7cc66853a4a8 |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654906617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ct rl_volatile_unlock_smoke.654906617 |
Directory | /workspace/13.lc_ctrl_volatile_unlock_smoke/latest |
Test location | /workspace/coverage/default/14.lc_ctrl_alert_test.4021363853 |
Short name | T722 |
Test name | |
Test status | |
Simulation time | 16808333 ps |
CPU time | 0.84 seconds |
Started | Jun 30 06:56:07 PM PDT 24 |
Finished | Jun 30 06:56:10 PM PDT 24 |
Peak memory | 209356 kb |
Host | smart-edea8788-80b0-4508-bf45-667e9c8b9ec4 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021363853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.4021363853 |
Directory | /workspace/14.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/14.lc_ctrl_errors.852700631 |
Short name | T590 |
Test name | |
Test status | |
Simulation time | 1624485881 ps |
CPU time | 13.71 seconds |
Started | Jun 30 06:56:00 PM PDT 24 |
Finished | Jun 30 06:56:16 PM PDT 24 |
Peak memory | 218512 kb |
Host | smart-e4537aed-6514-42d6-9fbb-b03124779494 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=852700631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.852700631 |
Directory | /workspace/14.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/14.lc_ctrl_jtag_access.3117725654 |
Short name | T504 |
Test name | |
Test status | |
Simulation time | 2471045144 ps |
CPU time | 7.31 seconds |
Started | Jun 30 06:56:02 PM PDT 24 |
Finished | Jun 30 06:56:12 PM PDT 24 |
Peak memory | 218128 kb |
Host | smart-ee205de7-8050-44b6-818d-961a374c32bf |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117725654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.3117725654 |
Directory | /workspace/14.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/14.lc_ctrl_jtag_errors.1469826375 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 2543477506 ps |
CPU time | 69.53 seconds |
Started | Jun 30 06:56:03 PM PDT 24 |
Finished | Jun 30 06:57:15 PM PDT 24 |
Peak memory | 219496 kb |
Host | smart-3e095583-eede-452e-9b23-e7018f851568 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469826375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e rrors.1469826375 |
Directory | /workspace/14.lc_ctrl_jtag_errors/latest |
Test location | /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.2227070649 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 271490938 ps |
CPU time | 9.61 seconds |
Started | Jun 30 06:56:03 PM PDT 24 |
Finished | Jun 30 06:56:15 PM PDT 24 |
Peak memory | 218588 kb |
Host | smart-398a7760-77b8-465b-8ae3-318e51e13870 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227070649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta g_prog_failure.2227070649 |
Directory | /workspace/14.lc_ctrl_jtag_prog_failure/latest |
Test location | /workspace/coverage/default/14.lc_ctrl_jtag_smoke.687935946 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 1282319009 ps |
CPU time | 8.79 seconds |
Started | Jun 30 06:56:02 PM PDT 24 |
Finished | Jun 30 06:56:13 PM PDT 24 |
Peak memory | 217936 kb |
Host | smart-ff0e021e-3358-40d1-8d09-dec33fe69106 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687935946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke. 687935946 |
Directory | /workspace/14.lc_ctrl_jtag_smoke/latest |
Test location | /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.2393613406 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 8928248391 ps |
CPU time | 85.35 seconds |
Started | Jun 30 06:56:03 PM PDT 24 |
Finished | Jun 30 06:57:31 PM PDT 24 |
Peak memory | 278060 kb |
Host | smart-623e9ad6-80b2-4ffc-96c8-a588df22cfbe |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393613406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt ag_state_failure.2393613406 |
Directory | /workspace/14.lc_ctrl_jtag_state_failure/latest |
Test location | /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.980070160 |
Short name | T859 |
Test name | |
Test status | |
Simulation time | 561047694 ps |
CPU time | 17.32 seconds |
Started | Jun 30 06:56:04 PM PDT 24 |
Finished | Jun 30 06:56:24 PM PDT 24 |
Peak memory | 223444 kb |
Host | smart-c4a30d50-cf77-4606-a0e3-7559a7b24041 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980070160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_ jtag_state_post_trans.980070160 |
Directory | /workspace/14.lc_ctrl_jtag_state_post_trans/latest |
Test location | /workspace/coverage/default/14.lc_ctrl_prog_failure.2801172971 |
Short name | T599 |
Test name | |
Test status | |
Simulation time | 218765485 ps |
CPU time | 3.12 seconds |
Started | Jun 30 06:56:03 PM PDT 24 |
Finished | Jun 30 06:56:08 PM PDT 24 |
Peak memory | 222848 kb |
Host | smart-f4478014-821b-4030-b071-526425992b45 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2801172971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.2801172971 |
Directory | /workspace/14.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/14.lc_ctrl_sec_mubi.1253469241 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 2312139977 ps |
CPU time | 16.54 seconds |
Started | Jun 30 06:56:05 PM PDT 24 |
Finished | Jun 30 06:56:24 PM PDT 24 |
Peak memory | 226496 kb |
Host | smart-066c0c26-a9cc-45c4-9c14-afe6dd8ada11 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253469241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.1253469241 |
Directory | /workspace/14.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/14.lc_ctrl_sec_token_digest.3045243058 |
Short name | T600 |
Test name | |
Test status | |
Simulation time | 1884689511 ps |
CPU time | 14.19 seconds |
Started | Jun 30 06:56:04 PM PDT 24 |
Finished | Jun 30 06:56:20 PM PDT 24 |
Peak memory | 218620 kb |
Host | smart-ec225da3-31a3-485b-b3f1-f797989766c4 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045243058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d igest.3045243058 |
Directory | /workspace/14.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/14.lc_ctrl_sec_token_mux.4095479114 |
Short name | T816 |
Test name | |
Test status | |
Simulation time | 1362676798 ps |
CPU time | 5.7 seconds |
Started | Jun 30 06:55:59 PM PDT 24 |
Finished | Jun 30 06:56:06 PM PDT 24 |
Peak memory | 225072 kb |
Host | smart-049a12cb-4345-410d-abaa-c73516cba870 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095479114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux. 4095479114 |
Directory | /workspace/14.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/14.lc_ctrl_security_escalation.2312036353 |
Short name | T862 |
Test name | |
Test status | |
Simulation time | 239521183 ps |
CPU time | 9.55 seconds |
Started | Jun 30 06:56:03 PM PDT 24 |
Finished | Jun 30 06:56:15 PM PDT 24 |
Peak memory | 226440 kb |
Host | smart-74eeb37b-692e-4e2f-ab3c-0bb89d067319 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2312036353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.2312036353 |
Directory | /workspace/14.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/14.lc_ctrl_smoke.3299443447 |
Short name | T471 |
Test name | |
Test status | |
Simulation time | 76850503 ps |
CPU time | 4.11 seconds |
Started | Jun 30 06:56:01 PM PDT 24 |
Finished | Jun 30 06:56:07 PM PDT 24 |
Peak memory | 217996 kb |
Host | smart-ed61ba4e-6fd6-437a-a25d-1385bc549ccd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3299443447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.3299443447 |
Directory | /workspace/14.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/14.lc_ctrl_state_failure.4072449021 |
Short name | T847 |
Test name | |
Test status | |
Simulation time | 242137110 ps |
CPU time | 19.87 seconds |
Started | Jun 30 06:56:05 PM PDT 24 |
Finished | Jun 30 06:56:27 PM PDT 24 |
Peak memory | 251288 kb |
Host | smart-91547518-013b-43bd-abb3-42bd82a55cf8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4072449021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.4072449021 |
Directory | /workspace/14.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/14.lc_ctrl_state_post_trans.4111712889 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 201680799 ps |
CPU time | 5.71 seconds |
Started | Jun 30 06:56:01 PM PDT 24 |
Finished | Jun 30 06:56:08 PM PDT 24 |
Peak memory | 247188 kb |
Host | smart-f4e3ffd8-0075-40f7-ae1c-3085117f360c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4111712889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.4111712889 |
Directory | /workspace/14.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/14.lc_ctrl_stress_all.3057887112 |
Short name | T489 |
Test name | |
Test status | |
Simulation time | 14542634364 ps |
CPU time | 224.5 seconds |
Started | Jun 30 06:56:04 PM PDT 24 |
Finished | Jun 30 06:59:50 PM PDT 24 |
Peak memory | 276080 kb |
Host | smart-fbaf5837-a82a-4a53-b813-2cbf266913f6 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057887112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all.3057887112 |
Directory | /workspace/14.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.1662622102 |
Short name | T736 |
Test name | |
Test status | |
Simulation time | 50391284 ps |
CPU time | 0.92 seconds |
Started | Jun 30 06:56:05 PM PDT 24 |
Finished | Jun 30 06:56:08 PM PDT 24 |
Peak memory | 213196 kb |
Host | smart-e5066512-a4ab-4e0e-9689-4ff54e37dc5e |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662622102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c trl_volatile_unlock_smoke.1662622102 |
Directory | /workspace/14.lc_ctrl_volatile_unlock_smoke/latest |
Test location | /workspace/coverage/default/15.lc_ctrl_alert_test.3422397758 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 54841281 ps |
CPU time | 0.85 seconds |
Started | Jun 30 06:56:06 PM PDT 24 |
Finished | Jun 30 06:56:09 PM PDT 24 |
Peak memory | 209248 kb |
Host | smart-dca26f96-133d-4b43-a820-3637bb7bec1d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422397758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.3422397758 |
Directory | /workspace/15.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/15.lc_ctrl_errors.1148006592 |
Short name | T564 |
Test name | |
Test status | |
Simulation time | 1396479740 ps |
CPU time | 11.92 seconds |
Started | Jun 30 06:56:07 PM PDT 24 |
Finished | Jun 30 06:56:21 PM PDT 24 |
Peak memory | 218620 kb |
Host | smart-3549d48f-cee8-49d1-893d-794bfc2382d6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1148006592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.1148006592 |
Directory | /workspace/15.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/15.lc_ctrl_jtag_access.3196523091 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 871064585 ps |
CPU time | 5.22 seconds |
Started | Jun 30 06:56:07 PM PDT 24 |
Finished | Jun 30 06:56:14 PM PDT 24 |
Peak memory | 217684 kb |
Host | smart-e096801f-09f8-4226-ac88-a94860c0818e |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196523091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.3196523091 |
Directory | /workspace/15.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/15.lc_ctrl_jtag_errors.4001951144 |
Short name | T617 |
Test name | |
Test status | |
Simulation time | 6348412726 ps |
CPU time | 38.61 seconds |
Started | Jun 30 06:56:05 PM PDT 24 |
Finished | Jun 30 06:56:46 PM PDT 24 |
Peak memory | 219152 kb |
Host | smart-1c004b15-cb30-4802-b4ce-689ecc752e02 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001951144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e rrors.4001951144 |
Directory | /workspace/15.lc_ctrl_jtag_errors/latest |
Test location | /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.2717362194 |
Short name | T429 |
Test name | |
Test status | |
Simulation time | 2419592101 ps |
CPU time | 12.8 seconds |
Started | Jun 30 06:56:07 PM PDT 24 |
Finished | Jun 30 06:56:22 PM PDT 24 |
Peak memory | 218680 kb |
Host | smart-7c1be870-10f8-43d2-90a2-bc98b2845831 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717362194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta g_prog_failure.2717362194 |
Directory | /workspace/15.lc_ctrl_jtag_prog_failure/latest |
Test location | /workspace/coverage/default/15.lc_ctrl_jtag_smoke.3472541056 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 283002821 ps |
CPU time | 4.03 seconds |
Started | Jun 30 06:56:04 PM PDT 24 |
Finished | Jun 30 06:56:10 PM PDT 24 |
Peak memory | 217960 kb |
Host | smart-9504b680-3e3d-4280-9370-7241e0f8d8b6 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472541056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke .3472541056 |
Directory | /workspace/15.lc_ctrl_jtag_smoke/latest |
Test location | /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.1103086062 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 16295294249 ps |
CPU time | 30.01 seconds |
Started | Jun 30 06:56:08 PM PDT 24 |
Finished | Jun 30 06:56:39 PM PDT 24 |
Peak memory | 268020 kb |
Host | smart-453f3f20-8513-4f35-b7ff-58f7efe3c1cb |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103086062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt ag_state_failure.1103086062 |
Directory | /workspace/15.lc_ctrl_jtag_state_failure/latest |
Test location | /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.4169059098 |
Short name | T819 |
Test name | |
Test status | |
Simulation time | 790325648 ps |
CPU time | 12.31 seconds |
Started | Jun 30 06:56:05 PM PDT 24 |
Finished | Jun 30 06:56:19 PM PDT 24 |
Peak memory | 251176 kb |
Host | smart-08b5c641-ba13-49e3-a2d1-147837c3d4f7 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169059098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl _jtag_state_post_trans.4169059098 |
Directory | /workspace/15.lc_ctrl_jtag_state_post_trans/latest |
Test location | /workspace/coverage/default/15.lc_ctrl_prog_failure.2785827690 |
Short name | T750 |
Test name | |
Test status | |
Simulation time | 290589277 ps |
CPU time | 2.89 seconds |
Started | Jun 30 06:56:08 PM PDT 24 |
Finished | Jun 30 06:56:13 PM PDT 24 |
Peak memory | 222532 kb |
Host | smart-0f206d62-053b-4f2a-a9eb-56f5d81f3872 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2785827690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.2785827690 |
Directory | /workspace/15.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/15.lc_ctrl_sec_mubi.1924733289 |
Short name | T715 |
Test name | |
Test status | |
Simulation time | 353714217 ps |
CPU time | 15.26 seconds |
Started | Jun 30 06:56:07 PM PDT 24 |
Finished | Jun 30 06:56:24 PM PDT 24 |
Peak memory | 226428 kb |
Host | smart-2b1349bc-743a-4cb2-b47c-b608f05e84bc |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924733289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.1924733289 |
Directory | /workspace/15.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/15.lc_ctrl_sec_token_digest.2285450059 |
Short name | T684 |
Test name | |
Test status | |
Simulation time | 479673356 ps |
CPU time | 7.69 seconds |
Started | Jun 30 06:56:08 PM PDT 24 |
Finished | Jun 30 06:56:17 PM PDT 24 |
Peak memory | 218616 kb |
Host | smart-d91282ab-b044-4100-94e1-af71b0f43dd6 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285450059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d igest.2285450059 |
Directory | /workspace/15.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/15.lc_ctrl_sec_token_mux.1601162039 |
Short name | T292 |
Test name | |
Test status | |
Simulation time | 243692888 ps |
CPU time | 9.84 seconds |
Started | Jun 30 06:56:06 PM PDT 24 |
Finished | Jun 30 06:56:18 PM PDT 24 |
Peak memory | 226296 kb |
Host | smart-4fc4d3be-084d-496a-8b19-c446dc7983fb |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601162039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux. 1601162039 |
Directory | /workspace/15.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/15.lc_ctrl_security_escalation.2343627334 |
Short name | T699 |
Test name | |
Test status | |
Simulation time | 622597479 ps |
CPU time | 6.21 seconds |
Started | Jun 30 06:56:08 PM PDT 24 |
Finished | Jun 30 06:56:16 PM PDT 24 |
Peak memory | 218744 kb |
Host | smart-49cd0169-4c80-4247-9b25-0589e1dd44af |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2343627334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.2343627334 |
Directory | /workspace/15.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/15.lc_ctrl_smoke.4028546981 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 50460390 ps |
CPU time | 1.87 seconds |
Started | Jun 30 06:56:06 PM PDT 24 |
Finished | Jun 30 06:56:10 PM PDT 24 |
Peak memory | 214456 kb |
Host | smart-147db6b0-eb9a-41a3-a192-92403c99f277 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4028546981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.4028546981 |
Directory | /workspace/15.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/15.lc_ctrl_state_failure.1472250100 |
Short name | T840 |
Test name | |
Test status | |
Simulation time | 193658192 ps |
CPU time | 19.96 seconds |
Started | Jun 30 06:56:06 PM PDT 24 |
Finished | Jun 30 06:56:28 PM PDT 24 |
Peak memory | 245108 kb |
Host | smart-94853842-4e23-4623-b6d3-9d3f57c48763 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1472250100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.1472250100 |
Directory | /workspace/15.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/15.lc_ctrl_state_post_trans.1454552627 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 261139696 ps |
CPU time | 8.52 seconds |
Started | Jun 30 06:56:07 PM PDT 24 |
Finished | Jun 30 06:56:17 PM PDT 24 |
Peak memory | 251312 kb |
Host | smart-a03f2b1b-eb49-49a0-90a0-526ef35534cc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1454552627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.1454552627 |
Directory | /workspace/15.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/15.lc_ctrl_stress_all.2337343325 |
Short name | T677 |
Test name | |
Test status | |
Simulation time | 2962104955 ps |
CPU time | 103.99 seconds |
Started | Jun 30 06:56:06 PM PDT 24 |
Finished | Jun 30 06:57:52 PM PDT 24 |
Peak memory | 281596 kb |
Host | smart-78df3a1a-eb61-487f-a575-616d5b0557c1 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337343325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all.2337343325 |
Directory | /workspace/15.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.2070863224 |
Short name | T700 |
Test name | |
Test status | |
Simulation time | 35916972 ps |
CPU time | 1.06 seconds |
Started | Jun 30 06:56:07 PM PDT 24 |
Finished | Jun 30 06:56:10 PM PDT 24 |
Peak memory | 212228 kb |
Host | smart-abfe894a-2d15-4915-8ea4-4acaca4ccb2c |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070863224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c trl_volatile_unlock_smoke.2070863224 |
Directory | /workspace/15.lc_ctrl_volatile_unlock_smoke/latest |
Test location | /workspace/coverage/default/16.lc_ctrl_alert_test.3817544037 |
Short name | T392 |
Test name | |
Test status | |
Simulation time | 147118130 ps |
CPU time | 1.12 seconds |
Started | Jun 30 06:56:12 PM PDT 24 |
Finished | Jun 30 06:56:15 PM PDT 24 |
Peak memory | 209420 kb |
Host | smart-1d29af99-1d29-4a37-ba7b-c849c4d976de |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817544037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.3817544037 |
Directory | /workspace/16.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/16.lc_ctrl_errors.1324403332 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 758893281 ps |
CPU time | 8.01 seconds |
Started | Jun 30 06:56:13 PM PDT 24 |
Finished | Jun 30 06:56:25 PM PDT 24 |
Peak memory | 218568 kb |
Host | smart-59c8792a-296b-4d85-b82d-56fa03e6dc46 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1324403332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.1324403332 |
Directory | /workspace/16.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/16.lc_ctrl_jtag_access.693164273 |
Short name | T827 |
Test name | |
Test status | |
Simulation time | 5837311797 ps |
CPU time | 12.7 seconds |
Started | Jun 30 06:56:11 PM PDT 24 |
Finished | Jun 30 06:56:25 PM PDT 24 |
Peak memory | 218088 kb |
Host | smart-fb72b729-d63f-4fe2-b674-1186ed41125f |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693164273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.693164273 |
Directory | /workspace/16.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/16.lc_ctrl_jtag_errors.2814662361 |
Short name | T493 |
Test name | |
Test status | |
Simulation time | 5799037060 ps |
CPU time | 24.11 seconds |
Started | Jun 30 06:56:13 PM PDT 24 |
Finished | Jun 30 06:56:41 PM PDT 24 |
Peak memory | 219280 kb |
Host | smart-14e2c0f4-ea89-451f-b628-124a329d0464 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814662361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e rrors.2814662361 |
Directory | /workspace/16.lc_ctrl_jtag_errors/latest |
Test location | /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.4053678566 |
Short name | T853 |
Test name | |
Test status | |
Simulation time | 2362914430 ps |
CPU time | 22.94 seconds |
Started | Jun 30 06:56:12 PM PDT 24 |
Finished | Jun 30 06:56:35 PM PDT 24 |
Peak memory | 219276 kb |
Host | smart-d50f5977-9478-48aa-926f-5171d42812b3 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053678566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta g_prog_failure.4053678566 |
Directory | /workspace/16.lc_ctrl_jtag_prog_failure/latest |
Test location | /workspace/coverage/default/16.lc_ctrl_jtag_smoke.1872940374 |
Short name | T649 |
Test name | |
Test status | |
Simulation time | 141465612 ps |
CPU time | 4.4 seconds |
Started | Jun 30 06:56:12 PM PDT 24 |
Finished | Jun 30 06:56:19 PM PDT 24 |
Peak memory | 217964 kb |
Host | smart-ff2967ff-40c7-43d9-b373-99d0b8f36cdd |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872940374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke .1872940374 |
Directory | /workspace/16.lc_ctrl_jtag_smoke/latest |
Test location | /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.2294147138 |
Short name | T691 |
Test name | |
Test status | |
Simulation time | 4678625400 ps |
CPU time | 52.56 seconds |
Started | Jun 30 06:56:15 PM PDT 24 |
Finished | Jun 30 06:57:12 PM PDT 24 |
Peak memory | 276368 kb |
Host | smart-b394b730-7153-4c00-96d9-3a5779e5aca9 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294147138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt ag_state_failure.2294147138 |
Directory | /workspace/16.lc_ctrl_jtag_state_failure/latest |
Test location | /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.1531909910 |
Short name | T487 |
Test name | |
Test status | |
Simulation time | 1718092720 ps |
CPU time | 22.08 seconds |
Started | Jun 30 06:56:15 PM PDT 24 |
Finished | Jun 30 06:56:42 PM PDT 24 |
Peak memory | 251196 kb |
Host | smart-f3f496f2-1b25-40c1-8e9e-6c5a6162a7e9 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531909910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl _jtag_state_post_trans.1531909910 |
Directory | /workspace/16.lc_ctrl_jtag_state_post_trans/latest |
Test location | /workspace/coverage/default/16.lc_ctrl_prog_failure.201281740 |
Short name | T344 |
Test name | |
Test status | |
Simulation time | 156475380 ps |
CPU time | 2.29 seconds |
Started | Jun 30 06:56:13 PM PDT 24 |
Finished | Jun 30 06:56:18 PM PDT 24 |
Peak memory | 218620 kb |
Host | smart-cdac7c0a-0098-4bf1-bd9a-068e94c0bdd4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=201281740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.201281740 |
Directory | /workspace/16.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/16.lc_ctrl_sec_mubi.2661696232 |
Short name | T300 |
Test name | |
Test status | |
Simulation time | 3020674792 ps |
CPU time | 21.03 seconds |
Started | Jun 30 06:56:12 PM PDT 24 |
Finished | Jun 30 06:56:34 PM PDT 24 |
Peak memory | 226460 kb |
Host | smart-0394006a-815d-4e35-ac1d-dc299dcc5a35 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661696232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.2661696232 |
Directory | /workspace/16.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/16.lc_ctrl_sec_token_digest.1098997754 |
Short name | T288 |
Test name | |
Test status | |
Simulation time | 312244119 ps |
CPU time | 11.8 seconds |
Started | Jun 30 06:56:13 PM PDT 24 |
Finished | Jun 30 06:56:29 PM PDT 24 |
Peak memory | 218624 kb |
Host | smart-2e7a0255-53bc-4b35-9a5e-056b27688a71 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098997754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d igest.1098997754 |
Directory | /workspace/16.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/16.lc_ctrl_sec_token_mux.2159586791 |
Short name | T552 |
Test name | |
Test status | |
Simulation time | 465511837 ps |
CPU time | 8.93 seconds |
Started | Jun 30 06:56:12 PM PDT 24 |
Finished | Jun 30 06:56:22 PM PDT 24 |
Peak memory | 218592 kb |
Host | smart-ddc022b4-8adb-4944-8371-b836ecb59ebb |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159586791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux. 2159586791 |
Directory | /workspace/16.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/16.lc_ctrl_security_escalation.601226970 |
Short name | T525 |
Test name | |
Test status | |
Simulation time | 2769493933 ps |
CPU time | 11.38 seconds |
Started | Jun 30 06:56:13 PM PDT 24 |
Finished | Jun 30 06:56:28 PM PDT 24 |
Peak memory | 218760 kb |
Host | smart-161b3ab6-4ca8-4ffa-a8a2-865b0c222cb3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=601226970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.601226970 |
Directory | /workspace/16.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/16.lc_ctrl_smoke.3509369192 |
Short name | T469 |
Test name | |
Test status | |
Simulation time | 85792513 ps |
CPU time | 2.8 seconds |
Started | Jun 30 06:56:09 PM PDT 24 |
Finished | Jun 30 06:56:13 PM PDT 24 |
Peak memory | 218080 kb |
Host | smart-96abd390-0bff-4f87-a1e1-d4a45ff805b3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3509369192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.3509369192 |
Directory | /workspace/16.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/16.lc_ctrl_state_failure.3781382583 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 270630512 ps |
CPU time | 26.56 seconds |
Started | Jun 30 06:56:04 PM PDT 24 |
Finished | Jun 30 06:56:33 PM PDT 24 |
Peak memory | 251284 kb |
Host | smart-ec2e97ce-8aae-4ff7-a422-09bd8380b824 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3781382583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.3781382583 |
Directory | /workspace/16.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/16.lc_ctrl_state_post_trans.2871887241 |
Short name | T824 |
Test name | |
Test status | |
Simulation time | 272275085 ps |
CPU time | 8.04 seconds |
Started | Jun 30 06:56:04 PM PDT 24 |
Finished | Jun 30 06:56:15 PM PDT 24 |
Peak memory | 251320 kb |
Host | smart-88031742-5dcc-4d5a-860c-f76904aa0817 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2871887241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.2871887241 |
Directory | /workspace/16.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/16.lc_ctrl_stress_all.4047813578 |
Short name | T555 |
Test name | |
Test status | |
Simulation time | 15122685184 ps |
CPU time | 267.57 seconds |
Started | Jun 30 06:56:14 PM PDT 24 |
Finished | Jun 30 07:00:45 PM PDT 24 |
Peak memory | 300704 kb |
Host | smart-c720c59d-6e6d-4c02-8269-e535c8b695a9 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047813578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all.4047813578 |
Directory | /workspace/16.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.188670908 |
Short name | T642 |
Test name | |
Test status | |
Simulation time | 19926918 ps |
CPU time | 0.79 seconds |
Started | Jun 30 06:56:07 PM PDT 24 |
Finished | Jun 30 06:56:10 PM PDT 24 |
Peak memory | 209240 kb |
Host | smart-ccfb5a99-90f4-4100-ba61-3d885964bd39 |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188670908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ct rl_volatile_unlock_smoke.188670908 |
Directory | /workspace/16.lc_ctrl_volatile_unlock_smoke/latest |
Test location | /workspace/coverage/default/17.lc_ctrl_alert_test.2990701137 |
Short name | T305 |
Test name | |
Test status | |
Simulation time | 36515988 ps |
CPU time | 1.19 seconds |
Started | Jun 30 06:56:24 PM PDT 24 |
Finished | Jun 30 06:56:28 PM PDT 24 |
Peak memory | 209520 kb |
Host | smart-36aea4cd-4067-44fb-a544-43c49dd618b9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990701137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.2990701137 |
Directory | /workspace/17.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/17.lc_ctrl_errors.1949498160 |
Short name | T646 |
Test name | |
Test status | |
Simulation time | 1858527157 ps |
CPU time | 14.24 seconds |
Started | Jun 30 06:56:14 PM PDT 24 |
Finished | Jun 30 06:56:33 PM PDT 24 |
Peak memory | 218916 kb |
Host | smart-9c9c1beb-9328-457a-9e47-c79a30d0c45f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1949498160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.1949498160 |
Directory | /workspace/17.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/17.lc_ctrl_jtag_access.823208822 |
Short name | T825 |
Test name | |
Test status | |
Simulation time | 303972117 ps |
CPU time | 6.94 seconds |
Started | Jun 30 06:56:21 PM PDT 24 |
Finished | Jun 30 06:56:32 PM PDT 24 |
Peak memory | 217660 kb |
Host | smart-a010906f-5d81-44bf-83b6-a4541d6d5b28 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823208822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.823208822 |
Directory | /workspace/17.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/17.lc_ctrl_jtag_errors.128283005 |
Short name | T619 |
Test name | |
Test status | |
Simulation time | 18479401924 ps |
CPU time | 54.02 seconds |
Started | Jun 30 06:56:14 PM PDT 24 |
Finished | Jun 30 06:57:12 PM PDT 24 |
Peak memory | 226428 kb |
Host | smart-0ec61790-a0b5-4cf9-a874-34c4cdb834ae |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128283005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_er rors.128283005 |
Directory | /workspace/17.lc_ctrl_jtag_errors/latest |
Test location | /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.476523725 |
Short name | T754 |
Test name | |
Test status | |
Simulation time | 474501120 ps |
CPU time | 2.68 seconds |
Started | Jun 30 06:56:23 PM PDT 24 |
Finished | Jun 30 06:56:29 PM PDT 24 |
Peak memory | 218560 kb |
Host | smart-f516d863-14ac-4c07-8e33-b0f6ef691050 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476523725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag _prog_failure.476523725 |
Directory | /workspace/17.lc_ctrl_jtag_prog_failure/latest |
Test location | /workspace/coverage/default/17.lc_ctrl_jtag_smoke.130164771 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 147753690 ps |
CPU time | 5.29 seconds |
Started | Jun 30 06:56:18 PM PDT 24 |
Finished | Jun 30 06:56:28 PM PDT 24 |
Peak memory | 217936 kb |
Host | smart-cf16dc57-339b-4ecc-94b6-295a3622458b |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130164771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke. 130164771 |
Directory | /workspace/17.lc_ctrl_jtag_smoke/latest |
Test location | /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.1414665096 |
Short name | T551 |
Test name | |
Test status | |
Simulation time | 1945498123 ps |
CPU time | 53.68 seconds |
Started | Jun 30 06:56:16 PM PDT 24 |
Finished | Jun 30 06:57:15 PM PDT 24 |
Peak memory | 268516 kb |
Host | smart-01efdc95-c0fc-4c6b-88d9-a80e373229b6 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414665096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt ag_state_failure.1414665096 |
Directory | /workspace/17.lc_ctrl_jtag_state_failure/latest |
Test location | /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.1315968659 |
Short name | T823 |
Test name | |
Test status | |
Simulation time | 4742728191 ps |
CPU time | 26.69 seconds |
Started | Jun 30 06:56:15 PM PDT 24 |
Finished | Jun 30 06:56:46 PM PDT 24 |
Peak memory | 251320 kb |
Host | smart-ac206235-8cc9-41d6-a1b3-dffd7b97dfb8 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315968659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl _jtag_state_post_trans.1315968659 |
Directory | /workspace/17.lc_ctrl_jtag_state_post_trans/latest |
Test location | /workspace/coverage/default/17.lc_ctrl_prog_failure.3494125865 |
Short name | T406 |
Test name | |
Test status | |
Simulation time | 110025117 ps |
CPU time | 4.61 seconds |
Started | Jun 30 06:56:24 PM PDT 24 |
Finished | Jun 30 06:56:32 PM PDT 24 |
Peak memory | 218624 kb |
Host | smart-a1759ec3-44ae-435b-995e-552853163364 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3494125865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.3494125865 |
Directory | /workspace/17.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/17.lc_ctrl_sec_mubi.1229641425 |
Short name | T664 |
Test name | |
Test status | |
Simulation time | 1449894506 ps |
CPU time | 13.28 seconds |
Started | Jun 30 06:56:14 PM PDT 24 |
Finished | Jun 30 06:56:31 PM PDT 24 |
Peak memory | 226324 kb |
Host | smart-9fb2ff8f-5e0b-4da9-af28-2e35e2e119ad |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229641425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.1229641425 |
Directory | /workspace/17.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/17.lc_ctrl_sec_token_digest.3621353817 |
Short name | T437 |
Test name | |
Test status | |
Simulation time | 667129388 ps |
CPU time | 16.26 seconds |
Started | Jun 30 06:56:15 PM PDT 24 |
Finished | Jun 30 06:56:36 PM PDT 24 |
Peak memory | 218912 kb |
Host | smart-4c9d4ef2-653d-42ef-814b-74bec20c29d5 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621353817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d igest.3621353817 |
Directory | /workspace/17.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/17.lc_ctrl_sec_token_mux.1583047508 |
Short name | T719 |
Test name | |
Test status | |
Simulation time | 891217869 ps |
CPU time | 8.54 seconds |
Started | Jun 30 06:56:16 PM PDT 24 |
Finished | Jun 30 06:56:29 PM PDT 24 |
Peak memory | 226364 kb |
Host | smart-4aa3abe5-4cf2-4129-b811-c1fe8dff17b7 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583047508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux. 1583047508 |
Directory | /workspace/17.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/17.lc_ctrl_security_escalation.1762525436 |
Short name | T458 |
Test name | |
Test status | |
Simulation time | 412633065 ps |
CPU time | 8.7 seconds |
Started | Jun 30 06:56:18 PM PDT 24 |
Finished | Jun 30 06:56:31 PM PDT 24 |
Peak memory | 226436 kb |
Host | smart-2dcce74b-1e6f-457f-9150-f46442b81040 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1762525436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.1762525436 |
Directory | /workspace/17.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/17.lc_ctrl_smoke.4277790123 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 22906921 ps |
CPU time | 1.56 seconds |
Started | Jun 30 06:56:13 PM PDT 24 |
Finished | Jun 30 06:56:18 PM PDT 24 |
Peak memory | 214088 kb |
Host | smart-da056868-ce88-485b-b804-57f375d9628a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4277790123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.4277790123 |
Directory | /workspace/17.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/17.lc_ctrl_state_failure.2547818766 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 532271331 ps |
CPU time | 28.44 seconds |
Started | Jun 30 06:56:14 PM PDT 24 |
Finished | Jun 30 06:56:46 PM PDT 24 |
Peak memory | 251328 kb |
Host | smart-eaee41a3-670b-4443-9ee5-82b461162a4c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2547818766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.2547818766 |
Directory | /workspace/17.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/17.lc_ctrl_state_post_trans.4081385569 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 376713632 ps |
CPU time | 7.63 seconds |
Started | Jun 30 06:56:15 PM PDT 24 |
Finished | Jun 30 06:56:27 PM PDT 24 |
Peak memory | 247284 kb |
Host | smart-f40f48e5-6da5-4140-a024-5da38b8ddf62 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4081385569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.4081385569 |
Directory | /workspace/17.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/17.lc_ctrl_stress_all.2372260784 |
Short name | T770 |
Test name | |
Test status | |
Simulation time | 25149964001 ps |
CPU time | 122.45 seconds |
Started | Jun 30 06:56:13 PM PDT 24 |
Finished | Jun 30 06:58:19 PM PDT 24 |
Peak memory | 259580 kb |
Host | smart-5e99a1b0-724f-49aa-ac86-8b984f80435b |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372260784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all.2372260784 |
Directory | /workspace/17.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.1835962059 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 60598752 ps |
CPU time | 0.94 seconds |
Started | Jun 30 06:56:21 PM PDT 24 |
Finished | Jun 30 06:56:26 PM PDT 24 |
Peak memory | 209480 kb |
Host | smart-86961e77-2fbb-4243-a0a8-4609c1c8a2cf |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835962059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c trl_volatile_unlock_smoke.1835962059 |
Directory | /workspace/17.lc_ctrl_volatile_unlock_smoke/latest |
Test location | /workspace/coverage/default/18.lc_ctrl_alert_test.4292905737 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 15377300 ps |
CPU time | 1.08 seconds |
Started | Jun 30 06:56:23 PM PDT 24 |
Finished | Jun 30 06:56:27 PM PDT 24 |
Peak memory | 209376 kb |
Host | smart-cd3a0967-2061-4250-8acf-c30ad1da8ab8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292905737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.4292905737 |
Directory | /workspace/18.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/18.lc_ctrl_errors.1684766974 |
Short name | T693 |
Test name | |
Test status | |
Simulation time | 302522035 ps |
CPU time | 10.73 seconds |
Started | Jun 30 06:56:17 PM PDT 24 |
Finished | Jun 30 06:56:33 PM PDT 24 |
Peak memory | 218664 kb |
Host | smart-067c3bee-3924-4f51-b22e-795b4e6aa6cd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1684766974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.1684766974 |
Directory | /workspace/18.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/18.lc_ctrl_jtag_access.2301529239 |
Short name | T417 |
Test name | |
Test status | |
Simulation time | 5546084689 ps |
CPU time | 5.7 seconds |
Started | Jun 30 06:56:18 PM PDT 24 |
Finished | Jun 30 06:56:29 PM PDT 24 |
Peak memory | 218152 kb |
Host | smart-63474794-0dec-45ab-89ca-831aeba8b28b |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301529239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.2301529239 |
Directory | /workspace/18.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/18.lc_ctrl_jtag_errors.3018563624 |
Short name | T749 |
Test name | |
Test status | |
Simulation time | 9519435407 ps |
CPU time | 34.81 seconds |
Started | Jun 30 06:56:17 PM PDT 24 |
Finished | Jun 30 06:56:57 PM PDT 24 |
Peak memory | 219256 kb |
Host | smart-964519ef-d1b8-46e3-bb81-f6b52128e4bc |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018563624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e rrors.3018563624 |
Directory | /workspace/18.lc_ctrl_jtag_errors/latest |
Test location | /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.2639681990 |
Short name | T431 |
Test name | |
Test status | |
Simulation time | 1078467732 ps |
CPU time | 8.65 seconds |
Started | Jun 30 06:56:22 PM PDT 24 |
Finished | Jun 30 06:56:34 PM PDT 24 |
Peak memory | 223448 kb |
Host | smart-b0cadf1e-ff4f-4d0c-9dcd-3f728a19cf03 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639681990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta g_prog_failure.2639681990 |
Directory | /workspace/18.lc_ctrl_jtag_prog_failure/latest |
Test location | /workspace/coverage/default/18.lc_ctrl_jtag_smoke.2165155420 |
Short name | T536 |
Test name | |
Test status | |
Simulation time | 262568924 ps |
CPU time | 4.91 seconds |
Started | Jun 30 06:56:17 PM PDT 24 |
Finished | Jun 30 06:56:27 PM PDT 24 |
Peak memory | 217996 kb |
Host | smart-36cea21a-a8a1-4d04-8935-f1c7de3429b9 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165155420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke .2165155420 |
Directory | /workspace/18.lc_ctrl_jtag_smoke/latest |
Test location | /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.3193156389 |
Short name | T380 |
Test name | |
Test status | |
Simulation time | 8514904761 ps |
CPU time | 61.53 seconds |
Started | Jun 30 06:56:21 PM PDT 24 |
Finished | Jun 30 06:57:26 PM PDT 24 |
Peak memory | 275916 kb |
Host | smart-8f368a2a-c8ff-4ff3-ad8b-bd7b31e55b8f |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193156389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt ag_state_failure.3193156389 |
Directory | /workspace/18.lc_ctrl_jtag_state_failure/latest |
Test location | /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.1691970817 |
Short name | T334 |
Test name | |
Test status | |
Simulation time | 481479599 ps |
CPU time | 13.05 seconds |
Started | Jun 30 06:56:19 PM PDT 24 |
Finished | Jun 30 06:56:36 PM PDT 24 |
Peak memory | 250480 kb |
Host | smart-dc5aa13d-a8f7-45b8-a910-3cbc5d99acd1 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691970817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl _jtag_state_post_trans.1691970817 |
Directory | /workspace/18.lc_ctrl_jtag_state_post_trans/latest |
Test location | /workspace/coverage/default/18.lc_ctrl_prog_failure.308364668 |
Short name | T582 |
Test name | |
Test status | |
Simulation time | 158586809 ps |
CPU time | 2.55 seconds |
Started | Jun 30 06:56:14 PM PDT 24 |
Finished | Jun 30 06:56:21 PM PDT 24 |
Peak memory | 222800 kb |
Host | smart-ba8c59a6-9723-4c28-b8f4-cf382ffb8c05 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=308364668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.308364668 |
Directory | /workspace/18.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/18.lc_ctrl_sec_mubi.470457687 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 179963243 ps |
CPU time | 9.7 seconds |
Started | Jun 30 06:56:20 PM PDT 24 |
Finished | Jun 30 06:56:34 PM PDT 24 |
Peak memory | 218644 kb |
Host | smart-12665c09-83e5-47a8-8a88-577d7d7db5fb |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470457687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.470457687 |
Directory | /workspace/18.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/18.lc_ctrl_sec_token_digest.3221588070 |
Short name | T294 |
Test name | |
Test status | |
Simulation time | 1866729959 ps |
CPU time | 25.07 seconds |
Started | Jun 30 06:56:20 PM PDT 24 |
Finished | Jun 30 06:56:49 PM PDT 24 |
Peak memory | 218596 kb |
Host | smart-466853f9-7a29-4591-a89f-fa40cf51504a |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221588070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d igest.3221588070 |
Directory | /workspace/18.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/18.lc_ctrl_sec_token_mux.226874507 |
Short name | T472 |
Test name | |
Test status | |
Simulation time | 311639582 ps |
CPU time | 9.81 seconds |
Started | Jun 30 06:56:17 PM PDT 24 |
Finished | Jun 30 06:56:32 PM PDT 24 |
Peak memory | 226360 kb |
Host | smart-15ee5607-0f2b-4dbe-bc3d-6d8cf88d835a |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226874507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.226874507 |
Directory | /workspace/18.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/18.lc_ctrl_smoke.575908841 |
Short name | T660 |
Test name | |
Test status | |
Simulation time | 90133339 ps |
CPU time | 1.38 seconds |
Started | Jun 30 06:56:16 PM PDT 24 |
Finished | Jun 30 06:56:22 PM PDT 24 |
Peak memory | 214200 kb |
Host | smart-5f165155-bc7e-4d76-8fb5-7011b0a57508 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=575908841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.575908841 |
Directory | /workspace/18.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/18.lc_ctrl_state_failure.677349047 |
Short name | T622 |
Test name | |
Test status | |
Simulation time | 302197262 ps |
CPU time | 23.32 seconds |
Started | Jun 30 06:56:16 PM PDT 24 |
Finished | Jun 30 06:56:44 PM PDT 24 |
Peak memory | 251272 kb |
Host | smart-95527a6d-77b0-4ef5-9012-5cd90ec068e9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=677349047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.677349047 |
Directory | /workspace/18.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/18.lc_ctrl_state_post_trans.2366372397 |
Short name | T793 |
Test name | |
Test status | |
Simulation time | 92896609 ps |
CPU time | 3.56 seconds |
Started | Jun 30 06:56:18 PM PDT 24 |
Finished | Jun 30 06:56:26 PM PDT 24 |
Peak memory | 222672 kb |
Host | smart-50a861bc-e7eb-41dd-86e4-a33d1dd4a432 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2366372397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.2366372397 |
Directory | /workspace/18.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/18.lc_ctrl_stress_all.2684323405 |
Short name | T768 |
Test name | |
Test status | |
Simulation time | 3459758878 ps |
CPU time | 11.06 seconds |
Started | Jun 30 06:56:21 PM PDT 24 |
Finished | Jun 30 06:56:36 PM PDT 24 |
Peak memory | 226500 kb |
Host | smart-9d37e5f9-fe6c-43a3-bea8-302bc79e449e |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684323405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all.2684323405 |
Directory | /workspace/18.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.3166332950 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 14065447 ps |
CPU time | 0.99 seconds |
Started | Jun 30 06:56:18 PM PDT 24 |
Finished | Jun 30 06:56:23 PM PDT 24 |
Peak memory | 209348 kb |
Host | smart-48d7465b-a115-4261-9e90-ebbe4ec4e980 |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166332950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c trl_volatile_unlock_smoke.3166332950 |
Directory | /workspace/18.lc_ctrl_volatile_unlock_smoke/latest |
Test location | /workspace/coverage/default/19.lc_ctrl_alert_test.3388521421 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 24924715 ps |
CPU time | 1.41 seconds |
Started | Jun 30 06:56:24 PM PDT 24 |
Finished | Jun 30 06:56:29 PM PDT 24 |
Peak memory | 209452 kb |
Host | smart-4d098662-fb4e-4c98-9e84-fe6300740aa4 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388521421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.3388521421 |
Directory | /workspace/19.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/19.lc_ctrl_errors.85894349 |
Short name | T703 |
Test name | |
Test status | |
Simulation time | 422005299 ps |
CPU time | 16.51 seconds |
Started | Jun 30 06:56:20 PM PDT 24 |
Finished | Jun 30 06:56:41 PM PDT 24 |
Peak memory | 218652 kb |
Host | smart-b8754aee-1480-4c5f-a01e-37a02ddd5bf9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=85894349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.85894349 |
Directory | /workspace/19.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/19.lc_ctrl_jtag_errors.1020622256 |
Short name | T349 |
Test name | |
Test status | |
Simulation time | 7294140307 ps |
CPU time | 54.84 seconds |
Started | Jun 30 06:56:19 PM PDT 24 |
Finished | Jun 30 06:57:18 PM PDT 24 |
Peak memory | 226412 kb |
Host | smart-eefcd7e6-d6b0-418b-95e3-3425b95d9fa0 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020622256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e rrors.1020622256 |
Directory | /workspace/19.lc_ctrl_jtag_errors/latest |
Test location | /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.1466999917 |
Short name | T842 |
Test name | |
Test status | |
Simulation time | 1136110606 ps |
CPU time | 5.14 seconds |
Started | Jun 30 06:56:20 PM PDT 24 |
Finished | Jun 30 06:56:29 PM PDT 24 |
Peak memory | 223412 kb |
Host | smart-72708c10-e970-4962-b5d6-dcbaa36ac271 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466999917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta g_prog_failure.1466999917 |
Directory | /workspace/19.lc_ctrl_jtag_prog_failure/latest |
Test location | /workspace/coverage/default/19.lc_ctrl_jtag_smoke.826154560 |
Short name | T338 |
Test name | |
Test status | |
Simulation time | 151313868 ps |
CPU time | 2.15 seconds |
Started | Jun 30 06:56:20 PM PDT 24 |
Finished | Jun 30 06:56:26 PM PDT 24 |
Peak memory | 217980 kb |
Host | smart-15bc656b-9d50-4f4d-a985-7e7e82c6dca6 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826154560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke. 826154560 |
Directory | /workspace/19.lc_ctrl_jtag_smoke/latest |
Test location | /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.3879469707 |
Short name | T407 |
Test name | |
Test status | |
Simulation time | 4426335415 ps |
CPU time | 51.61 seconds |
Started | Jun 30 06:56:17 PM PDT 24 |
Finished | Jun 30 06:57:13 PM PDT 24 |
Peak memory | 251336 kb |
Host | smart-09a17ec6-2297-48eb-be9f-5f3d5dba1858 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879469707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt ag_state_failure.3879469707 |
Directory | /workspace/19.lc_ctrl_jtag_state_failure/latest |
Test location | /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.1585059080 |
Short name | T386 |
Test name | |
Test status | |
Simulation time | 421029747 ps |
CPU time | 14.05 seconds |
Started | Jun 30 06:56:19 PM PDT 24 |
Finished | Jun 30 06:56:37 PM PDT 24 |
Peak memory | 226676 kb |
Host | smart-a057feb1-4652-4768-8eef-e45f3a805cbc |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585059080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl _jtag_state_post_trans.1585059080 |
Directory | /workspace/19.lc_ctrl_jtag_state_post_trans/latest |
Test location | /workspace/coverage/default/19.lc_ctrl_prog_failure.1390047399 |
Short name | T371 |
Test name | |
Test status | |
Simulation time | 94925283 ps |
CPU time | 3.42 seconds |
Started | Jun 30 06:56:23 PM PDT 24 |
Finished | Jun 30 06:56:30 PM PDT 24 |
Peak memory | 218604 kb |
Host | smart-1d9e9846-f21f-4553-bc75-4dd61b0b077e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1390047399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.1390047399 |
Directory | /workspace/19.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/19.lc_ctrl_sec_mubi.2618703145 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 199211822 ps |
CPU time | 10.95 seconds |
Started | Jun 30 06:56:25 PM PDT 24 |
Finished | Jun 30 06:56:38 PM PDT 24 |
Peak memory | 226532 kb |
Host | smart-6faf1fb5-d20d-47b8-bea1-98a7b60d6860 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618703145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.2618703145 |
Directory | /workspace/19.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/19.lc_ctrl_sec_token_digest.3102019601 |
Short name | T675 |
Test name | |
Test status | |
Simulation time | 321541436 ps |
CPU time | 10.05 seconds |
Started | Jun 30 06:56:26 PM PDT 24 |
Finished | Jun 30 06:56:39 PM PDT 24 |
Peak memory | 218660 kb |
Host | smart-d972ce9a-3a56-412a-a32e-d939725727dc |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102019601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d igest.3102019601 |
Directory | /workspace/19.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/19.lc_ctrl_sec_token_mux.3111895578 |
Short name | T381 |
Test name | |
Test status | |
Simulation time | 1186448442 ps |
CPU time | 10.99 seconds |
Started | Jun 30 06:56:27 PM PDT 24 |
Finished | Jun 30 06:56:42 PM PDT 24 |
Peak memory | 218592 kb |
Host | smart-2b58a9b9-ecf7-471d-93dc-f48050c296f2 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111895578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux. 3111895578 |
Directory | /workspace/19.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/19.lc_ctrl_security_escalation.1001381368 |
Short name | T635 |
Test name | |
Test status | |
Simulation time | 890615937 ps |
CPU time | 9.87 seconds |
Started | Jun 30 06:56:22 PM PDT 24 |
Finished | Jun 30 06:56:36 PM PDT 24 |
Peak memory | 226392 kb |
Host | smart-4fe1cf47-5631-4369-8b3f-0d948be40cb4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1001381368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.1001381368 |
Directory | /workspace/19.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/19.lc_ctrl_smoke.3174081959 |
Short name | T706 |
Test name | |
Test status | |
Simulation time | 32293345 ps |
CPU time | 1.48 seconds |
Started | Jun 30 06:56:17 PM PDT 24 |
Finished | Jun 30 06:56:23 PM PDT 24 |
Peak memory | 214336 kb |
Host | smart-b366d7b1-62ff-4590-a13c-510a1eee9b62 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3174081959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.3174081959 |
Directory | /workspace/19.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/19.lc_ctrl_state_failure.1726680873 |
Short name | T633 |
Test name | |
Test status | |
Simulation time | 1519270276 ps |
CPU time | 33.04 seconds |
Started | Jun 30 06:56:18 PM PDT 24 |
Finished | Jun 30 06:56:56 PM PDT 24 |
Peak memory | 251324 kb |
Host | smart-8e121cc7-ab89-4807-8e2b-507ef5edec05 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1726680873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.1726680873 |
Directory | /workspace/19.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/19.lc_ctrl_state_post_trans.1369090993 |
Short name | T803 |
Test name | |
Test status | |
Simulation time | 407800460 ps |
CPU time | 3.56 seconds |
Started | Jun 30 06:56:24 PM PDT 24 |
Finished | Jun 30 06:56:31 PM PDT 24 |
Peak memory | 222820 kb |
Host | smart-0b40adcd-87c7-4913-8b44-73335146475b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1369090993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.1369090993 |
Directory | /workspace/19.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/19.lc_ctrl_stress_all.252028848 |
Short name | T385 |
Test name | |
Test status | |
Simulation time | 1892477202 ps |
CPU time | 44.43 seconds |
Started | Jun 30 06:56:25 PM PDT 24 |
Finished | Jun 30 06:57:13 PM PDT 24 |
Peak memory | 246176 kb |
Host | smart-363cbe57-ea1c-422b-a2d5-52982c8f0a95 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252028848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all.252028848 |
Directory | /workspace/19.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.1734831223 |
Short name | T316 |
Test name | |
Test status | |
Simulation time | 23793328 ps |
CPU time | 1.09 seconds |
Started | Jun 30 06:56:23 PM PDT 24 |
Finished | Jun 30 06:56:27 PM PDT 24 |
Peak memory | 218260 kb |
Host | smart-1246005f-06b7-463e-91db-a55620354f53 |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734831223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c trl_volatile_unlock_smoke.1734831223 |
Directory | /workspace/19.lc_ctrl_volatile_unlock_smoke/latest |
Test location | /workspace/coverage/default/2.lc_ctrl_alert_test.2015358873 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 43886163 ps |
CPU time | 0.84 seconds |
Started | Jun 30 06:54:58 PM PDT 24 |
Finished | Jun 30 06:54:59 PM PDT 24 |
Peak memory | 209364 kb |
Host | smart-d6365f81-c618-455b-9ea9-e904872a55d7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015358873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.2015358873 |
Directory | /workspace/2.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/2.lc_ctrl_claim_transition_if.2599414489 |
Short name | T849 |
Test name | |
Test status | |
Simulation time | 51348324 ps |
CPU time | 0.84 seconds |
Started | Jun 30 06:54:57 PM PDT 24 |
Finished | Jun 30 06:54:59 PM PDT 24 |
Peak memory | 209088 kb |
Host | smart-55531526-90d1-45b0-815e-428bdf95e790 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2599414489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.2599414489 |
Directory | /workspace/2.lc_ctrl_claim_transition_if/latest |
Test location | /workspace/coverage/default/2.lc_ctrl_errors.3554038678 |
Short name | T612 |
Test name | |
Test status | |
Simulation time | 474752225 ps |
CPU time | 16.55 seconds |
Started | Jun 30 06:54:53 PM PDT 24 |
Finished | Jun 30 06:55:10 PM PDT 24 |
Peak memory | 218608 kb |
Host | smart-736389c0-ebb5-412e-b188-e7801312ce06 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3554038678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.3554038678 |
Directory | /workspace/2.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/2.lc_ctrl_jtag_access.1632264285 |
Short name | T563 |
Test name | |
Test status | |
Simulation time | 963871725 ps |
CPU time | 6.59 seconds |
Started | Jun 30 06:54:57 PM PDT 24 |
Finished | Jun 30 06:55:04 PM PDT 24 |
Peak memory | 217648 kb |
Host | smart-73d17a26-bf95-4679-9e3c-9af3e75fc401 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632264285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.1632264285 |
Directory | /workspace/2.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/2.lc_ctrl_jtag_errors.1768546019 |
Short name | T802 |
Test name | |
Test status | |
Simulation time | 1127714743 ps |
CPU time | 20.16 seconds |
Started | Jun 30 06:54:56 PM PDT 24 |
Finished | Jun 30 06:55:17 PM PDT 24 |
Peak memory | 218572 kb |
Host | smart-90304f51-d848-4c01-bb9b-c6fcebac772f |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768546019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er rors.1768546019 |
Directory | /workspace/2.lc_ctrl_jtag_errors/latest |
Test location | /workspace/coverage/default/2.lc_ctrl_jtag_priority.3818706445 |
Short name | T438 |
Test name | |
Test status | |
Simulation time | 1495133591 ps |
CPU time | 2.7 seconds |
Started | Jun 30 06:54:57 PM PDT 24 |
Finished | Jun 30 06:55:00 PM PDT 24 |
Peak memory | 218144 kb |
Host | smart-e9c6e031-756a-42c1-a794-5974c6d2778a |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818706445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.3 818706445 |
Directory | /workspace/2.lc_ctrl_jtag_priority/latest |
Test location | /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.2737160853 |
Short name | T830 |
Test name | |
Test status | |
Simulation time | 286224057 ps |
CPU time | 2.23 seconds |
Started | Jun 30 06:54:59 PM PDT 24 |
Finished | Jun 30 06:55:03 PM PDT 24 |
Peak memory | 218580 kb |
Host | smart-cbc8bc98-d734-43c4-aa76-0065cf265bfb |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737160853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag _prog_failure.2737160853 |
Directory | /workspace/2.lc_ctrl_jtag_prog_failure/latest |
Test location | /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.409360199 |
Short name | T791 |
Test name | |
Test status | |
Simulation time | 576266975 ps |
CPU time | 16.55 seconds |
Started | Jun 30 06:54:57 PM PDT 24 |
Finished | Jun 30 06:55:14 PM PDT 24 |
Peak memory | 217996 kb |
Host | smart-5c3638e9-aae0-4e8d-9cfa-0d943b0a7dc0 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409360199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j tag_regwen_during_op.409360199 |
Directory | /workspace/2.lc_ctrl_jtag_regwen_during_op/latest |
Test location | /workspace/coverage/default/2.lc_ctrl_jtag_smoke.4100024706 |
Short name | T503 |
Test name | |
Test status | |
Simulation time | 2711672034 ps |
CPU time | 4.19 seconds |
Started | Jun 30 06:54:58 PM PDT 24 |
Finished | Jun 30 06:55:03 PM PDT 24 |
Peak memory | 218028 kb |
Host | smart-cae08053-1cec-4e50-a283-3fc591aca27e |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100024706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke. 4100024706 |
Directory | /workspace/2.lc_ctrl_jtag_smoke/latest |
Test location | /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.1804774065 |
Short name | T399 |
Test name | |
Test status | |
Simulation time | 10539189032 ps |
CPU time | 34.54 seconds |
Started | Jun 30 06:54:58 PM PDT 24 |
Finished | Jun 30 06:55:33 PM PDT 24 |
Peak memory | 270824 kb |
Host | smart-9c8e2293-5775-459c-aadf-08e10cd4dbea |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804774065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta g_state_failure.1804774065 |
Directory | /workspace/2.lc_ctrl_jtag_state_failure/latest |
Test location | /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.3444033671 |
Short name | T712 |
Test name | |
Test status | |
Simulation time | 674324634 ps |
CPU time | 11.95 seconds |
Started | Jun 30 06:55:01 PM PDT 24 |
Finished | Jun 30 06:55:14 PM PDT 24 |
Peak memory | 251368 kb |
Host | smart-3c2f5dd5-bff1-4843-b6b6-03eea3a9408f |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444033671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_ jtag_state_post_trans.3444033671 |
Directory | /workspace/2.lc_ctrl_jtag_state_post_trans/latest |
Test location | /workspace/coverage/default/2.lc_ctrl_prog_failure.1587175881 |
Short name | T634 |
Test name | |
Test status | |
Simulation time | 56485012 ps |
CPU time | 2.53 seconds |
Started | Jun 30 06:54:52 PM PDT 24 |
Finished | Jun 30 06:54:55 PM PDT 24 |
Peak memory | 218632 kb |
Host | smart-f55dc56f-7137-4582-bb3a-b60c052fcdcd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1587175881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.1587175881 |
Directory | /workspace/2.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/2.lc_ctrl_regwen_during_op.1903611501 |
Short name | T751 |
Test name | |
Test status | |
Simulation time | 257747967 ps |
CPU time | 5.93 seconds |
Started | Jun 30 06:55:01 PM PDT 24 |
Finished | Jun 30 06:55:07 PM PDT 24 |
Peak memory | 218068 kb |
Host | smart-f2b45e3b-1b9d-4e06-b73b-e36655df5e58 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1903611501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.1903611501 |
Directory | /workspace/2.lc_ctrl_regwen_during_op/latest |
Test location | /workspace/coverage/default/2.lc_ctrl_sec_cm.1647984557 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 120291831 ps |
CPU time | 21.51 seconds |
Started | Jun 30 06:54:56 PM PDT 24 |
Finished | Jun 30 06:55:19 PM PDT 24 |
Peak memory | 284516 kb |
Host | smart-090837bb-a13b-4fff-bfd9-268dab106a10 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647984557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.1647984557 |
Directory | /workspace/2.lc_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/2.lc_ctrl_sec_mubi.1843826318 |
Short name | T318 |
Test name | |
Test status | |
Simulation time | 1320375976 ps |
CPU time | 13.41 seconds |
Started | Jun 30 06:54:57 PM PDT 24 |
Finished | Jun 30 06:55:11 PM PDT 24 |
Peak memory | 226432 kb |
Host | smart-0c9c02b5-4f76-4d37-97d9-3c0cda691ce5 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843826318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.1843826318 |
Directory | /workspace/2.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/2.lc_ctrl_sec_token_digest.406493054 |
Short name | T336 |
Test name | |
Test status | |
Simulation time | 472507078 ps |
CPU time | 10.96 seconds |
Started | Jun 30 06:55:01 PM PDT 24 |
Finished | Jun 30 06:55:12 PM PDT 24 |
Peak memory | 218532 kb |
Host | smart-3a1c870c-5341-48bd-a96c-382e056aede0 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406493054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_dig est.406493054 |
Directory | /workspace/2.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/2.lc_ctrl_sec_token_mux.276542774 |
Short name | T363 |
Test name | |
Test status | |
Simulation time | 625614092 ps |
CPU time | 7.85 seconds |
Started | Jun 30 06:55:01 PM PDT 24 |
Finished | Jun 30 06:55:10 PM PDT 24 |
Peak memory | 218656 kb |
Host | smart-47cf9ee8-350e-4caa-be2c-213592fba125 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276542774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.276542774 |
Directory | /workspace/2.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/2.lc_ctrl_security_escalation.2647846132 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 288834935 ps |
CPU time | 7.85 seconds |
Started | Jun 30 06:54:52 PM PDT 24 |
Finished | Jun 30 06:55:01 PM PDT 24 |
Peak memory | 218736 kb |
Host | smart-9bb067d5-4987-45f4-9652-1c89cbb92327 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2647846132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.2647846132 |
Directory | /workspace/2.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/2.lc_ctrl_smoke.698342622 |
Short name | T508 |
Test name | |
Test status | |
Simulation time | 172300254 ps |
CPU time | 2.75 seconds |
Started | Jun 30 06:54:56 PM PDT 24 |
Finished | Jun 30 06:54:59 PM PDT 24 |
Peak memory | 215016 kb |
Host | smart-fa28750b-9ec0-4f58-b998-aff9e7058e17 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=698342622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.698342622 |
Directory | /workspace/2.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/2.lc_ctrl_state_failure.2098142416 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 242216857 ps |
CPU time | 28.5 seconds |
Started | Jun 30 06:54:54 PM PDT 24 |
Finished | Jun 30 06:55:23 PM PDT 24 |
Peak memory | 251320 kb |
Host | smart-828e0604-3da5-46ff-bd48-d18f49a52aa7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2098142416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.2098142416 |
Directory | /workspace/2.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/2.lc_ctrl_state_post_trans.921214085 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 120703667 ps |
CPU time | 6.82 seconds |
Started | Jun 30 06:54:51 PM PDT 24 |
Finished | Jun 30 06:54:59 PM PDT 24 |
Peak memory | 250712 kb |
Host | smart-b1b2ca0d-21f6-4ad4-8ffa-30bd95041a14 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=921214085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.921214085 |
Directory | /workspace/2.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/2.lc_ctrl_stress_all.1091004242 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 11060596828 ps |
CPU time | 181.33 seconds |
Started | Jun 30 06:54:57 PM PDT 24 |
Finished | Jun 30 06:57:59 PM PDT 24 |
Peak memory | 276028 kb |
Host | smart-de859428-e69c-4d87-92c1-f4d5157cfe82 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091004242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all.1091004242 |
Directory | /workspace/2.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.1062784518 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 10585417 ps |
CPU time | 0.79 seconds |
Started | Jun 30 06:54:50 PM PDT 24 |
Finished | Jun 30 06:54:52 PM PDT 24 |
Peak memory | 209216 kb |
Host | smart-eb71e4f0-b635-49f4-a957-d087b87738c0 |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062784518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct rl_volatile_unlock_smoke.1062784518 |
Directory | /workspace/2.lc_ctrl_volatile_unlock_smoke/latest |
Test location | /workspace/coverage/default/20.lc_ctrl_alert_test.673629510 |
Short name | T352 |
Test name | |
Test status | |
Simulation time | 11774204 ps |
CPU time | 0.94 seconds |
Started | Jun 30 06:56:27 PM PDT 24 |
Finished | Jun 30 06:56:32 PM PDT 24 |
Peak memory | 209624 kb |
Host | smart-1063b7b9-2727-415b-a4ea-d1af95a1efa6 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673629510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.673629510 |
Directory | /workspace/20.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/20.lc_ctrl_errors.1988344929 |
Short name | T365 |
Test name | |
Test status | |
Simulation time | 397763994 ps |
CPU time | 10.14 seconds |
Started | Jun 30 06:56:29 PM PDT 24 |
Finished | Jun 30 06:56:42 PM PDT 24 |
Peak memory | 218572 kb |
Host | smart-cd4efd2c-ce91-4be3-bb1c-182bf3c8e53f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1988344929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.1988344929 |
Directory | /workspace/20.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/20.lc_ctrl_jtag_access.2764030392 |
Short name | T526 |
Test name | |
Test status | |
Simulation time | 264967011 ps |
CPU time | 3.19 seconds |
Started | Jun 30 06:56:27 PM PDT 24 |
Finished | Jun 30 06:56:33 PM PDT 24 |
Peak memory | 217540 kb |
Host | smart-3a21ff42-59c6-4fcb-a88b-d6a032498eda |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764030392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.2764030392 |
Directory | /workspace/20.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/20.lc_ctrl_prog_failure.3013964028 |
Short name | T696 |
Test name | |
Test status | |
Simulation time | 49173801 ps |
CPU time | 1.68 seconds |
Started | Jun 30 06:56:25 PM PDT 24 |
Finished | Jun 30 06:56:30 PM PDT 24 |
Peak memory | 218628 kb |
Host | smart-7bdc4969-a746-43cf-b121-ba2f9c1f1666 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3013964028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.3013964028 |
Directory | /workspace/20.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/20.lc_ctrl_sec_mubi.4143701797 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 3333402495 ps |
CPU time | 19.22 seconds |
Started | Jun 30 06:56:29 PM PDT 24 |
Finished | Jun 30 06:56:52 PM PDT 24 |
Peak memory | 226500 kb |
Host | smart-a603bf32-4ed2-44d5-aa69-a4d9c0eee45c |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143701797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.4143701797 |
Directory | /workspace/20.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/20.lc_ctrl_sec_token_digest.2190768226 |
Short name | T786 |
Test name | |
Test status | |
Simulation time | 311331585 ps |
CPU time | 12.36 seconds |
Started | Jun 30 06:56:26 PM PDT 24 |
Finished | Jun 30 06:56:42 PM PDT 24 |
Peak memory | 218676 kb |
Host | smart-995b5254-759e-4b70-8bf0-9d0f9bac0ae0 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190768226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d igest.2190768226 |
Directory | /workspace/20.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/20.lc_ctrl_sec_token_mux.3448190265 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 294092209 ps |
CPU time | 11.74 seconds |
Started | Jun 30 06:56:27 PM PDT 24 |
Finished | Jun 30 06:56:42 PM PDT 24 |
Peak memory | 218588 kb |
Host | smart-bdb03e5b-b9f1-43f8-8ee7-23d912701fa1 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448190265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux. 3448190265 |
Directory | /workspace/20.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/20.lc_ctrl_security_escalation.581771851 |
Short name | T867 |
Test name | |
Test status | |
Simulation time | 337154049 ps |
CPU time | 13.61 seconds |
Started | Jun 30 06:56:25 PM PDT 24 |
Finished | Jun 30 06:56:42 PM PDT 24 |
Peak memory | 226444 kb |
Host | smart-6e1cf2e1-d07a-431f-9bb8-07de3056fdfb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=581771851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.581771851 |
Directory | /workspace/20.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/20.lc_ctrl_smoke.3748213596 |
Short name | T868 |
Test name | |
Test status | |
Simulation time | 188311871 ps |
CPU time | 3.05 seconds |
Started | Jun 30 06:56:27 PM PDT 24 |
Finished | Jun 30 06:56:34 PM PDT 24 |
Peak memory | 218072 kb |
Host | smart-8e53e833-9967-4a0e-900c-d177c704e083 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3748213596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.3748213596 |
Directory | /workspace/20.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/20.lc_ctrl_state_failure.3014895704 |
Short name | T869 |
Test name | |
Test status | |
Simulation time | 186666580 ps |
CPU time | 17.73 seconds |
Started | Jun 30 06:56:27 PM PDT 24 |
Finished | Jun 30 06:56:49 PM PDT 24 |
Peak memory | 251324 kb |
Host | smart-a7fd0ac2-7f3c-4931-8396-edecd9e4af8a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3014895704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.3014895704 |
Directory | /workspace/20.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/20.lc_ctrl_state_post_trans.2818924534 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 84757576 ps |
CPU time | 9.03 seconds |
Started | Jun 30 06:56:25 PM PDT 24 |
Finished | Jun 30 06:56:37 PM PDT 24 |
Peak memory | 251344 kb |
Host | smart-cc7e98a2-e727-4046-a766-d386a3eb2f04 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2818924534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.2818924534 |
Directory | /workspace/20.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/20.lc_ctrl_stress_all.1442039963 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 6798592560 ps |
CPU time | 237.41 seconds |
Started | Jun 30 06:56:29 PM PDT 24 |
Finished | Jun 30 07:00:30 PM PDT 24 |
Peak memory | 316884 kb |
Host | smart-1077b6f7-61ae-4882-bcfc-ae6e991c2361 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442039963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all.1442039963 |
Directory | /workspace/20.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.1785170259 |
Short name | T739 |
Test name | |
Test status | |
Simulation time | 14975715 ps |
CPU time | 1.04 seconds |
Started | Jun 30 06:56:24 PM PDT 24 |
Finished | Jun 30 06:56:28 PM PDT 24 |
Peak memory | 212256 kb |
Host | smart-8ca9c1b8-5270-4fdd-b974-0cf1a733258e |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785170259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c trl_volatile_unlock_smoke.1785170259 |
Directory | /workspace/20.lc_ctrl_volatile_unlock_smoke/latest |
Test location | /workspace/coverage/default/21.lc_ctrl_alert_test.2229148942 |
Short name | T464 |
Test name | |
Test status | |
Simulation time | 37822931 ps |
CPU time | 0.99 seconds |
Started | Jun 30 06:56:31 PM PDT 24 |
Finished | Jun 30 06:56:36 PM PDT 24 |
Peak memory | 209360 kb |
Host | smart-e13d9673-234e-4d8f-8271-f5eb9654894e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229148942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.2229148942 |
Directory | /workspace/21.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/21.lc_ctrl_errors.1476303830 |
Short name | T832 |
Test name | |
Test status | |
Simulation time | 1461569938 ps |
CPU time | 15.53 seconds |
Started | Jun 30 06:56:31 PM PDT 24 |
Finished | Jun 30 06:56:50 PM PDT 24 |
Peak memory | 226416 kb |
Host | smart-79bc90b1-b5b1-4f3b-b91c-61919c71ff10 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1476303830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.1476303830 |
Directory | /workspace/21.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/21.lc_ctrl_jtag_access.3702745193 |
Short name | T778 |
Test name | |
Test status | |
Simulation time | 1763430545 ps |
CPU time | 22.02 seconds |
Started | Jun 30 06:56:35 PM PDT 24 |
Finished | Jun 30 06:56:59 PM PDT 24 |
Peak memory | 217772 kb |
Host | smart-85a14c63-39d3-41f7-82d4-3622139fba38 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702745193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.3702745193 |
Directory | /workspace/21.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/21.lc_ctrl_prog_failure.427091164 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 686794656 ps |
CPU time | 2.03 seconds |
Started | Jun 30 06:56:28 PM PDT 24 |
Finished | Jun 30 06:56:34 PM PDT 24 |
Peak memory | 222836 kb |
Host | smart-b951ffcd-064c-4e20-b6ab-64bc11e01d80 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=427091164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.427091164 |
Directory | /workspace/21.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/21.lc_ctrl_sec_mubi.2356916931 |
Short name | T595 |
Test name | |
Test status | |
Simulation time | 296188369 ps |
CPU time | 11.87 seconds |
Started | Jun 30 06:56:36 PM PDT 24 |
Finished | Jun 30 06:56:50 PM PDT 24 |
Peak memory | 226444 kb |
Host | smart-44c22759-9e90-4a79-97c6-e7c82bb109f0 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356916931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.2356916931 |
Directory | /workspace/21.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/21.lc_ctrl_sec_token_digest.736337739 |
Short name | T765 |
Test name | |
Test status | |
Simulation time | 357186331 ps |
CPU time | 9.61 seconds |
Started | Jun 30 06:56:30 PM PDT 24 |
Finished | Jun 30 06:56:44 PM PDT 24 |
Peak memory | 218560 kb |
Host | smart-8cacd5d7-c37e-43cd-af73-6e9764bc1289 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736337739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_di gest.736337739 |
Directory | /workspace/21.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/21.lc_ctrl_sec_token_mux.4227171934 |
Short name | T538 |
Test name | |
Test status | |
Simulation time | 408710575 ps |
CPU time | 9.55 seconds |
Started | Jun 30 06:56:35 PM PDT 24 |
Finished | Jun 30 06:56:47 PM PDT 24 |
Peak memory | 226332 kb |
Host | smart-5d92e25c-d8be-4cbb-9113-1571e1165cff |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227171934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux. 4227171934 |
Directory | /workspace/21.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/21.lc_ctrl_security_escalation.4115120740 |
Short name | T686 |
Test name | |
Test status | |
Simulation time | 1020884454 ps |
CPU time | 10.05 seconds |
Started | Jun 30 06:56:29 PM PDT 24 |
Finished | Jun 30 06:56:44 PM PDT 24 |
Peak memory | 225364 kb |
Host | smart-beb2e5c1-5b2b-4f0e-945f-8efeda36cee6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4115120740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.4115120740 |
Directory | /workspace/21.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/21.lc_ctrl_smoke.412372670 |
Short name | T813 |
Test name | |
Test status | |
Simulation time | 365780314 ps |
CPU time | 4.47 seconds |
Started | Jun 30 06:56:27 PM PDT 24 |
Finished | Jun 30 06:56:36 PM PDT 24 |
Peak memory | 218048 kb |
Host | smart-3b7ec893-3bf9-459e-ad82-b88ac234a52e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=412372670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.412372670 |
Directory | /workspace/21.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/21.lc_ctrl_state_failure.2384591110 |
Short name | T742 |
Test name | |
Test status | |
Simulation time | 1601802359 ps |
CPU time | 27.24 seconds |
Started | Jun 30 06:56:30 PM PDT 24 |
Finished | Jun 30 06:57:02 PM PDT 24 |
Peak memory | 251292 kb |
Host | smart-1286fd0c-93b1-446d-9499-e89b45ef9756 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2384591110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.2384591110 |
Directory | /workspace/21.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/21.lc_ctrl_state_post_trans.1272638968 |
Short name | T613 |
Test name | |
Test status | |
Simulation time | 80882461 ps |
CPU time | 9.13 seconds |
Started | Jun 30 06:56:29 PM PDT 24 |
Finished | Jun 30 06:56:42 PM PDT 24 |
Peak memory | 251296 kb |
Host | smart-e2fd8687-9c93-4a1e-b580-518980d1624f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1272638968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.1272638968 |
Directory | /workspace/21.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/21.lc_ctrl_stress_all.3215562962 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 2372203968 ps |
CPU time | 107.2 seconds |
Started | Jun 30 06:56:29 PM PDT 24 |
Finished | Jun 30 06:58:20 PM PDT 24 |
Peak memory | 271960 kb |
Host | smart-2a6daa4d-9dab-457c-8307-7ab5cc7ad2d9 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215562962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all.3215562962 |
Directory | /workspace/21.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.1911813228 |
Short name | T516 |
Test name | |
Test status | |
Simulation time | 16296532 ps |
CPU time | 1.06 seconds |
Started | Jun 30 06:56:27 PM PDT 24 |
Finished | Jun 30 06:56:32 PM PDT 24 |
Peak memory | 212284 kb |
Host | smart-cddff6d2-8af8-4501-9677-e20a4a7d94be |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911813228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c trl_volatile_unlock_smoke.1911813228 |
Directory | /workspace/21.lc_ctrl_volatile_unlock_smoke/latest |
Test location | /workspace/coverage/default/22.lc_ctrl_alert_test.1957885194 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 38659541 ps |
CPU time | 1.03 seconds |
Started | Jun 30 06:56:29 PM PDT 24 |
Finished | Jun 30 06:56:34 PM PDT 24 |
Peak memory | 209348 kb |
Host | smart-b2e8a75a-0de6-4e03-8f65-8f3b1c227b97 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957885194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.1957885194 |
Directory | /workspace/22.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/22.lc_ctrl_errors.302897913 |
Short name | T589 |
Test name | |
Test status | |
Simulation time | 2076746722 ps |
CPU time | 13.77 seconds |
Started | Jun 30 06:56:35 PM PDT 24 |
Finished | Jun 30 06:56:52 PM PDT 24 |
Peak memory | 226396 kb |
Host | smart-c845cac8-66b1-4844-b6c1-8d087bdb3ffa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=302897913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.302897913 |
Directory | /workspace/22.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/22.lc_ctrl_jtag_access.216597736 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 384813250 ps |
CPU time | 10.52 seconds |
Started | Jun 30 06:56:33 PM PDT 24 |
Finished | Jun 30 06:56:47 PM PDT 24 |
Peak memory | 217820 kb |
Host | smart-fbcfd774-8963-4738-b4fa-6bac9d48ac74 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216597736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.216597736 |
Directory | /workspace/22.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/22.lc_ctrl_prog_failure.2391527074 |
Short name | T528 |
Test name | |
Test status | |
Simulation time | 161003144 ps |
CPU time | 3.07 seconds |
Started | Jun 30 06:56:39 PM PDT 24 |
Finished | Jun 30 06:56:44 PM PDT 24 |
Peak memory | 222604 kb |
Host | smart-0583a718-1ae0-46bd-bf30-2a9646e409ea |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2391527074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.2391527074 |
Directory | /workspace/22.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/22.lc_ctrl_sec_mubi.61127286 |
Short name | T312 |
Test name | |
Test status | |
Simulation time | 431121806 ps |
CPU time | 11.41 seconds |
Started | Jun 30 06:56:35 PM PDT 24 |
Finished | Jun 30 06:56:49 PM PDT 24 |
Peak memory | 226396 kb |
Host | smart-654e433f-4809-456c-82e1-2c68f823b240 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61127286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.61127286 |
Directory | /workspace/22.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/22.lc_ctrl_sec_token_digest.2898486720 |
Short name | T839 |
Test name | |
Test status | |
Simulation time | 522723248 ps |
CPU time | 11.71 seconds |
Started | Jun 30 06:56:37 PM PDT 24 |
Finished | Jun 30 06:56:51 PM PDT 24 |
Peak memory | 218588 kb |
Host | smart-b3cfe2d0-36b3-45d2-b882-f6beea926998 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898486720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d igest.2898486720 |
Directory | /workspace/22.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/22.lc_ctrl_sec_token_mux.849632281 |
Short name | T467 |
Test name | |
Test status | |
Simulation time | 1049726566 ps |
CPU time | 13 seconds |
Started | Jun 30 06:56:33 PM PDT 24 |
Finished | Jun 30 06:56:50 PM PDT 24 |
Peak memory | 218584 kb |
Host | smart-c3e02127-00a1-45ce-adb7-a0b1397f43c3 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849632281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.849632281 |
Directory | /workspace/22.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/22.lc_ctrl_security_escalation.1646647855 |
Short name | T743 |
Test name | |
Test status | |
Simulation time | 1102243369 ps |
CPU time | 10.34 seconds |
Started | Jun 30 06:56:37 PM PDT 24 |
Finished | Jun 30 06:56:50 PM PDT 24 |
Peak memory | 226428 kb |
Host | smart-e3cff420-a993-4a06-9700-40315d71e187 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1646647855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.1646647855 |
Directory | /workspace/22.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/22.lc_ctrl_smoke.2298283626 |
Short name | T433 |
Test name | |
Test status | |
Simulation time | 100070888 ps |
CPU time | 2.27 seconds |
Started | Jun 30 06:56:34 PM PDT 24 |
Finished | Jun 30 06:56:39 PM PDT 24 |
Peak memory | 218052 kb |
Host | smart-96786cac-dcfb-4485-a3f2-0304439fdefe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2298283626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.2298283626 |
Directory | /workspace/22.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/22.lc_ctrl_state_failure.1558197747 |
Short name | T539 |
Test name | |
Test status | |
Simulation time | 414833273 ps |
CPU time | 26.59 seconds |
Started | Jun 30 06:56:30 PM PDT 24 |
Finished | Jun 30 06:57:00 PM PDT 24 |
Peak memory | 251228 kb |
Host | smart-63f31196-ada5-430c-a4be-07a25d93d251 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1558197747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.1558197747 |
Directory | /workspace/22.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/22.lc_ctrl_state_post_trans.749973330 |
Short name | T861 |
Test name | |
Test status | |
Simulation time | 215644649 ps |
CPU time | 9.64 seconds |
Started | Jun 30 06:56:37 PM PDT 24 |
Finished | Jun 30 06:56:49 PM PDT 24 |
Peak memory | 251328 kb |
Host | smart-bc290f34-8237-460c-9c61-16f889fe5a71 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=749973330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.749973330 |
Directory | /workspace/22.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/22.lc_ctrl_stress_all.3342433072 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 14986447507 ps |
CPU time | 328.49 seconds |
Started | Jun 30 06:56:31 PM PDT 24 |
Finished | Jun 30 07:02:03 PM PDT 24 |
Peak memory | 283704 kb |
Host | smart-a9bb5a06-b28a-4227-a144-d44aaf937010 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342433072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all.3342433072 |
Directory | /workspace/22.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.3170063866 |
Short name | T844 |
Test name | |
Test status | |
Simulation time | 18727218 ps |
CPU time | 0.88 seconds |
Started | Jun 30 06:56:30 PM PDT 24 |
Finished | Jun 30 06:56:35 PM PDT 24 |
Peak memory | 212292 kb |
Host | smart-60944813-1c8e-4f1b-89e4-bf2b7ab3cf4f |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170063866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c trl_volatile_unlock_smoke.3170063866 |
Directory | /workspace/22.lc_ctrl_volatile_unlock_smoke/latest |
Test location | /workspace/coverage/default/23.lc_ctrl_alert_test.2477965341 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 24225650 ps |
CPU time | 0.97 seconds |
Started | Jun 30 06:56:37 PM PDT 24 |
Finished | Jun 30 06:56:41 PM PDT 24 |
Peak memory | 209376 kb |
Host | smart-f7183b0e-b083-43ba-82a5-70c8b5b1bca1 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477965341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.2477965341 |
Directory | /workspace/23.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/23.lc_ctrl_errors.3229792120 |
Short name | T805 |
Test name | |
Test status | |
Simulation time | 1157224302 ps |
CPU time | 10.92 seconds |
Started | Jun 30 06:56:32 PM PDT 24 |
Finished | Jun 30 06:56:47 PM PDT 24 |
Peak memory | 218636 kb |
Host | smart-64b748fb-229d-4d5b-a9c2-7d166dd29291 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3229792120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.3229792120 |
Directory | /workspace/23.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/23.lc_ctrl_jtag_access.3572173303 |
Short name | T420 |
Test name | |
Test status | |
Simulation time | 453048018 ps |
CPU time | 3.31 seconds |
Started | Jun 30 06:56:35 PM PDT 24 |
Finished | Jun 30 06:56:41 PM PDT 24 |
Peak memory | 217372 kb |
Host | smart-cb724ddc-ea78-429f-82f6-077bdd043881 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572173303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.3572173303 |
Directory | /workspace/23.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/23.lc_ctrl_prog_failure.3620814158 |
Short name | T425 |
Test name | |
Test status | |
Simulation time | 81039365 ps |
CPU time | 2.77 seconds |
Started | Jun 30 06:56:31 PM PDT 24 |
Finished | Jun 30 06:56:38 PM PDT 24 |
Peak memory | 218648 kb |
Host | smart-e1bf35a6-8a91-4635-8112-064e9644bd32 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3620814158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.3620814158 |
Directory | /workspace/23.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/23.lc_ctrl_sec_mubi.3509409064 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 1216718566 ps |
CPU time | 13.91 seconds |
Started | Jun 30 06:56:30 PM PDT 24 |
Finished | Jun 30 06:56:48 PM PDT 24 |
Peak memory | 226456 kb |
Host | smart-db7e7ee0-e7b2-4b40-ab9e-18a998304ddf |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509409064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.3509409064 |
Directory | /workspace/23.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/23.lc_ctrl_sec_token_digest.3771689066 |
Short name | T470 |
Test name | |
Test status | |
Simulation time | 653094683 ps |
CPU time | 12.76 seconds |
Started | Jun 30 06:56:36 PM PDT 24 |
Finished | Jun 30 06:56:51 PM PDT 24 |
Peak memory | 218604 kb |
Host | smart-c98d9cf4-c38d-4830-ab74-fc2ecd5f14a0 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771689066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d igest.3771689066 |
Directory | /workspace/23.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/23.lc_ctrl_security_escalation.1792736389 |
Short name | T454 |
Test name | |
Test status | |
Simulation time | 3004431992 ps |
CPU time | 9.17 seconds |
Started | Jun 30 06:56:32 PM PDT 24 |
Finished | Jun 30 06:56:45 PM PDT 24 |
Peak memory | 218760 kb |
Host | smart-c968efeb-4e48-4d34-94c3-2cad96544db5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1792736389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.1792736389 |
Directory | /workspace/23.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/23.lc_ctrl_smoke.3350399567 |
Short name | T322 |
Test name | |
Test status | |
Simulation time | 15315088 ps |
CPU time | 1.05 seconds |
Started | Jun 30 06:56:30 PM PDT 24 |
Finished | Jun 30 06:56:35 PM PDT 24 |
Peak memory | 212276 kb |
Host | smart-5cc17acf-153d-4d6e-a5ed-15c2a6cbe6cf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3350399567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.3350399567 |
Directory | /workspace/23.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/23.lc_ctrl_state_failure.3848306170 |
Short name | T603 |
Test name | |
Test status | |
Simulation time | 934434047 ps |
CPU time | 32.61 seconds |
Started | Jun 30 06:56:30 PM PDT 24 |
Finished | Jun 30 06:57:07 PM PDT 24 |
Peak memory | 251312 kb |
Host | smart-6d5c040c-9461-4248-99cf-679bc890b5be |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3848306170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.3848306170 |
Directory | /workspace/23.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/23.lc_ctrl_state_post_trans.2875071416 |
Short name | T631 |
Test name | |
Test status | |
Simulation time | 86055823 ps |
CPU time | 6.5 seconds |
Started | Jun 30 06:56:32 PM PDT 24 |
Finished | Jun 30 06:56:42 PM PDT 24 |
Peak memory | 247336 kb |
Host | smart-7a56bd8b-9451-40f2-bb25-a9dc6efb5666 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2875071416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.2875071416 |
Directory | /workspace/23.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/23.lc_ctrl_stress_all.2748233342 |
Short name | T811 |
Test name | |
Test status | |
Simulation time | 54978130925 ps |
CPU time | 98.98 seconds |
Started | Jun 30 06:56:37 PM PDT 24 |
Finished | Jun 30 06:58:18 PM PDT 24 |
Peak memory | 251288 kb |
Host | smart-d853395d-1f88-40e6-af22-b45d2fb93d5f |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748233342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all.2748233342 |
Directory | /workspace/23.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.2578453241 |
Short name | T436 |
Test name | |
Test status | |
Simulation time | 23668311 ps |
CPU time | 0.91 seconds |
Started | Jun 30 06:56:32 PM PDT 24 |
Finished | Jun 30 06:56:37 PM PDT 24 |
Peak memory | 209500 kb |
Host | smart-fa08a704-fee7-4538-8f00-a7b61fd444c9 |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578453241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c trl_volatile_unlock_smoke.2578453241 |
Directory | /workspace/23.lc_ctrl_volatile_unlock_smoke/latest |
Test location | /workspace/coverage/default/24.lc_ctrl_alert_test.3897711266 |
Short name | T285 |
Test name | |
Test status | |
Simulation time | 48106784 ps |
CPU time | 0.99 seconds |
Started | Jun 30 06:56:38 PM PDT 24 |
Finished | Jun 30 06:56:41 PM PDT 24 |
Peak memory | 209380 kb |
Host | smart-d54d3284-b6ae-4d30-85b2-f488404bb293 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897711266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.3897711266 |
Directory | /workspace/24.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/24.lc_ctrl_errors.3317813194 |
Short name | T608 |
Test name | |
Test status | |
Simulation time | 3931871987 ps |
CPU time | 20.8 seconds |
Started | Jun 30 06:56:37 PM PDT 24 |
Finished | Jun 30 06:57:00 PM PDT 24 |
Peak memory | 219320 kb |
Host | smart-28168a59-75ae-4e55-a468-2ddea2cb39f6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3317813194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.3317813194 |
Directory | /workspace/24.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/24.lc_ctrl_jtag_access.1248651649 |
Short name | T460 |
Test name | |
Test status | |
Simulation time | 364543461 ps |
CPU time | 9.96 seconds |
Started | Jun 30 06:56:37 PM PDT 24 |
Finished | Jun 30 06:56:49 PM PDT 24 |
Peak memory | 217740 kb |
Host | smart-bde921cb-23bf-42c5-b93b-e02d4feebe26 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248651649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.1248651649 |
Directory | /workspace/24.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/24.lc_ctrl_prog_failure.4196742205 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 293875732 ps |
CPU time | 3.14 seconds |
Started | Jun 30 06:56:36 PM PDT 24 |
Finished | Jun 30 06:56:41 PM PDT 24 |
Peak memory | 222724 kb |
Host | smart-cc67116f-5d59-4cea-b300-9922f000e74a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4196742205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.4196742205 |
Directory | /workspace/24.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/24.lc_ctrl_sec_mubi.3554436369 |
Short name | T479 |
Test name | |
Test status | |
Simulation time | 410785303 ps |
CPU time | 14.49 seconds |
Started | Jun 30 06:56:38 PM PDT 24 |
Finished | Jun 30 06:56:55 PM PDT 24 |
Peak memory | 226428 kb |
Host | smart-16fba744-0e0c-4eba-b07c-4e98cb82f3f6 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554436369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.3554436369 |
Directory | /workspace/24.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/24.lc_ctrl_sec_token_digest.917669392 |
Short name | T484 |
Test name | |
Test status | |
Simulation time | 10053280305 ps |
CPU time | 17.12 seconds |
Started | Jun 30 06:56:38 PM PDT 24 |
Finished | Jun 30 06:56:57 PM PDT 24 |
Peak memory | 218756 kb |
Host | smart-ae44e04f-d604-4d3a-bce3-7df67a69a15e |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917669392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_di gest.917669392 |
Directory | /workspace/24.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/24.lc_ctrl_sec_token_mux.10760370 |
Short name | T587 |
Test name | |
Test status | |
Simulation time | 394331844 ps |
CPU time | 9.63 seconds |
Started | Jun 30 06:56:38 PM PDT 24 |
Finished | Jun 30 06:56:50 PM PDT 24 |
Peak memory | 218576 kb |
Host | smart-3e074060-d927-4f20-8440-18d7c9ac3e3d |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10760370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.10760370 |
Directory | /workspace/24.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/24.lc_ctrl_security_escalation.2274038409 |
Short name | T733 |
Test name | |
Test status | |
Simulation time | 314781341 ps |
CPU time | 8.55 seconds |
Started | Jun 30 06:56:39 PM PDT 24 |
Finished | Jun 30 06:56:49 PM PDT 24 |
Peak memory | 226428 kb |
Host | smart-a85f18f1-f1a8-4997-b9d9-b515946710b3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2274038409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.2274038409 |
Directory | /workspace/24.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/24.lc_ctrl_smoke.939078076 |
Short name | T408 |
Test name | |
Test status | |
Simulation time | 172593881 ps |
CPU time | 1.9 seconds |
Started | Jun 30 06:56:38 PM PDT 24 |
Finished | Jun 30 06:56:42 PM PDT 24 |
Peak memory | 218068 kb |
Host | smart-b440c302-3509-4737-b469-c7dd904a3188 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=939078076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.939078076 |
Directory | /workspace/24.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/24.lc_ctrl_state_failure.467038175 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 4211784764 ps |
CPU time | 29.02 seconds |
Started | Jun 30 06:56:36 PM PDT 24 |
Finished | Jun 30 06:57:08 PM PDT 24 |
Peak memory | 251480 kb |
Host | smart-35d076dd-242d-49c8-b6a2-9e6e8917c9b6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=467038175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.467038175 |
Directory | /workspace/24.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/24.lc_ctrl_state_post_trans.4251604493 |
Short name | T565 |
Test name | |
Test status | |
Simulation time | 80779562 ps |
CPU time | 7.52 seconds |
Started | Jun 30 06:56:38 PM PDT 24 |
Finished | Jun 30 06:56:48 PM PDT 24 |
Peak memory | 251160 kb |
Host | smart-af6203d6-a472-413d-8bce-4bb0d5925790 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4251604493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.4251604493 |
Directory | /workspace/24.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/24.lc_ctrl_stress_all.4216705813 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 2481235133 ps |
CPU time | 91.94 seconds |
Started | Jun 30 06:56:38 PM PDT 24 |
Finished | Jun 30 06:58:12 PM PDT 24 |
Peak memory | 276192 kb |
Host | smart-a0a8f0e2-426f-42fe-b672-3602380c4d55 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216705813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all.4216705813 |
Directory | /workspace/24.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.1823228476 |
Short name | T626 |
Test name | |
Test status | |
Simulation time | 31396744 ps |
CPU time | 0.9 seconds |
Started | Jun 30 06:56:38 PM PDT 24 |
Finished | Jun 30 06:56:41 PM PDT 24 |
Peak memory | 209296 kb |
Host | smart-2a44778f-6a14-40fb-925d-4904b1aef5e8 |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823228476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c trl_volatile_unlock_smoke.1823228476 |
Directory | /workspace/24.lc_ctrl_volatile_unlock_smoke/latest |
Test location | /workspace/coverage/default/25.lc_ctrl_alert_test.3312299086 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 38483641 ps |
CPU time | 1 seconds |
Started | Jun 30 06:56:42 PM PDT 24 |
Finished | Jun 30 06:56:44 PM PDT 24 |
Peak memory | 209324 kb |
Host | smart-af528de6-7691-409f-b2c5-30774e08e17f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312299086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.3312299086 |
Directory | /workspace/25.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/25.lc_ctrl_errors.2932476185 |
Short name | T278 |
Test name | |
Test status | |
Simulation time | 6754923900 ps |
CPU time | 11.33 seconds |
Started | Jun 30 06:56:43 PM PDT 24 |
Finished | Jun 30 06:56:56 PM PDT 24 |
Peak memory | 218696 kb |
Host | smart-d350eee1-3120-4f26-8590-0c7acf605eaa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2932476185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.2932476185 |
Directory | /workspace/25.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/25.lc_ctrl_jtag_access.2330623254 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 14546114376 ps |
CPU time | 14.14 seconds |
Started | Jun 30 06:56:42 PM PDT 24 |
Finished | Jun 30 06:56:58 PM PDT 24 |
Peak memory | 218032 kb |
Host | smart-0334b97d-a290-4906-a5ca-ae73a9926a86 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330623254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.2330623254 |
Directory | /workspace/25.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/25.lc_ctrl_prog_failure.2282380335 |
Short name | T457 |
Test name | |
Test status | |
Simulation time | 99700576 ps |
CPU time | 2.63 seconds |
Started | Jun 30 06:56:42 PM PDT 24 |
Finished | Jun 30 06:56:47 PM PDT 24 |
Peak memory | 222776 kb |
Host | smart-19398d2c-b3a9-413d-9d32-99230f0f1b23 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2282380335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.2282380335 |
Directory | /workspace/25.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/25.lc_ctrl_sec_mubi.2273085501 |
Short name | T486 |
Test name | |
Test status | |
Simulation time | 1893737147 ps |
CPU time | 12.27 seconds |
Started | Jun 30 06:56:43 PM PDT 24 |
Finished | Jun 30 06:56:57 PM PDT 24 |
Peak memory | 226440 kb |
Host | smart-5398cdce-d0ce-4c20-b177-dadaf848e912 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273085501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.2273085501 |
Directory | /workspace/25.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/25.lc_ctrl_sec_token_digest.898162601 |
Short name | T577 |
Test name | |
Test status | |
Simulation time | 4029921633 ps |
CPU time | 11.81 seconds |
Started | Jun 30 06:56:41 PM PDT 24 |
Finished | Jun 30 06:56:54 PM PDT 24 |
Peak memory | 218592 kb |
Host | smart-c19b7fb8-d6dc-4b77-b985-16979edb34bc |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898162601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_di gest.898162601 |
Directory | /workspace/25.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/25.lc_ctrl_sec_token_mux.3295236784 |
Short name | T518 |
Test name | |
Test status | |
Simulation time | 954827628 ps |
CPU time | 7.2 seconds |
Started | Jun 30 06:56:45 PM PDT 24 |
Finished | Jun 30 06:56:53 PM PDT 24 |
Peak memory | 218584 kb |
Host | smart-e1922303-9033-4e69-b436-7d56bdf68350 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295236784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux. 3295236784 |
Directory | /workspace/25.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/25.lc_ctrl_security_escalation.997935339 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 184448968 ps |
CPU time | 5.49 seconds |
Started | Jun 30 06:56:42 PM PDT 24 |
Finished | Jun 30 06:56:49 PM PDT 24 |
Peak memory | 218700 kb |
Host | smart-ba714e68-5f4f-4a45-856f-cf4078225ea3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=997935339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.997935339 |
Directory | /workspace/25.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/25.lc_ctrl_smoke.1231635660 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 38918157 ps |
CPU time | 2.15 seconds |
Started | Jun 30 06:56:37 PM PDT 24 |
Finished | Jun 30 06:56:42 PM PDT 24 |
Peak memory | 223588 kb |
Host | smart-1d640a16-a767-4310-b6b1-3b880119f758 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1231635660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.1231635660 |
Directory | /workspace/25.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/25.lc_ctrl_state_failure.3547891543 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 296053382 ps |
CPU time | 28.48 seconds |
Started | Jun 30 06:56:42 PM PDT 24 |
Finished | Jun 30 06:57:12 PM PDT 24 |
Peak memory | 251412 kb |
Host | smart-986b2905-e8ec-4de3-a958-2a6c046cd8cd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3547891543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.3547891543 |
Directory | /workspace/25.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/25.lc_ctrl_state_post_trans.3907142510 |
Short name | T789 |
Test name | |
Test status | |
Simulation time | 269493181 ps |
CPU time | 3.2 seconds |
Started | Jun 30 06:56:42 PM PDT 24 |
Finished | Jun 30 06:56:47 PM PDT 24 |
Peak memory | 218624 kb |
Host | smart-338733a6-046a-4154-bd19-8baab092950f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3907142510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.3907142510 |
Directory | /workspace/25.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/25.lc_ctrl_stress_all.3351568683 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 10586339531 ps |
CPU time | 40.85 seconds |
Started | Jun 30 06:56:43 PM PDT 24 |
Finished | Jun 30 06:57:25 PM PDT 24 |
Peak memory | 226504 kb |
Host | smart-0d56bea2-9108-46cf-9f96-ee431e737ba6 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351568683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_stress_all.3351568683 |
Directory | /workspace/25.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.3016929136 |
Short name | T785 |
Test name | |
Test status | |
Simulation time | 35936246 ps |
CPU time | 0.75 seconds |
Started | Jun 30 06:56:36 PM PDT 24 |
Finished | Jun 30 06:56:39 PM PDT 24 |
Peak memory | 209052 kb |
Host | smart-22668a4b-2d5d-4cd5-a52f-a5621e297f5b |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016929136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c trl_volatile_unlock_smoke.3016929136 |
Directory | /workspace/25.lc_ctrl_volatile_unlock_smoke/latest |
Test location | /workspace/coverage/default/26.lc_ctrl_alert_test.2710435198 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 19396007 ps |
CPU time | 1.19 seconds |
Started | Jun 30 06:56:48 PM PDT 24 |
Finished | Jun 30 06:56:52 PM PDT 24 |
Peak memory | 209368 kb |
Host | smart-4c5a9826-c282-4d2f-9b18-7799d731d5af |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710435198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.2710435198 |
Directory | /workspace/26.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/26.lc_ctrl_errors.3268758318 |
Short name | T488 |
Test name | |
Test status | |
Simulation time | 1194732994 ps |
CPU time | 12.86 seconds |
Started | Jun 30 06:56:44 PM PDT 24 |
Finished | Jun 30 06:56:58 PM PDT 24 |
Peak memory | 218636 kb |
Host | smart-e94d527f-9f8a-4597-b32c-aa107a007f3e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3268758318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.3268758318 |
Directory | /workspace/26.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/26.lc_ctrl_jtag_access.861815803 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 2078667417 ps |
CPU time | 6.79 seconds |
Started | Jun 30 06:56:43 PM PDT 24 |
Finished | Jun 30 06:56:52 PM PDT 24 |
Peak memory | 217744 kb |
Host | smart-1794867b-67b0-4ec9-9ab9-d6cdbe89719d |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861815803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.861815803 |
Directory | /workspace/26.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/26.lc_ctrl_prog_failure.781062414 |
Short name | T615 |
Test name | |
Test status | |
Simulation time | 76058825 ps |
CPU time | 3.5 seconds |
Started | Jun 30 06:56:44 PM PDT 24 |
Finished | Jun 30 06:56:49 PM PDT 24 |
Peak memory | 218640 kb |
Host | smart-7316cd6f-af5b-45e1-8de5-b1c8212dcb95 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=781062414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.781062414 |
Directory | /workspace/26.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/26.lc_ctrl_sec_mubi.1883094950 |
Short name | T353 |
Test name | |
Test status | |
Simulation time | 638642988 ps |
CPU time | 14.51 seconds |
Started | Jun 30 06:56:48 PM PDT 24 |
Finished | Jun 30 06:57:05 PM PDT 24 |
Peak memory | 218652 kb |
Host | smart-572c20b4-6b28-472f-bd18-7c243ec1615a |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883094950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.1883094950 |
Directory | /workspace/26.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/26.lc_ctrl_sec_token_digest.1039902001 |
Short name | T689 |
Test name | |
Test status | |
Simulation time | 983441412 ps |
CPU time | 11.84 seconds |
Started | Jun 30 06:56:49 PM PDT 24 |
Finished | Jun 30 06:57:03 PM PDT 24 |
Peak memory | 218596 kb |
Host | smart-15fac1b5-91f5-4737-b9c6-238e2f0e2c1e |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039902001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d igest.1039902001 |
Directory | /workspace/26.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/26.lc_ctrl_sec_token_mux.4008241760 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 1699128255 ps |
CPU time | 11.21 seconds |
Started | Jun 30 06:56:49 PM PDT 24 |
Finished | Jun 30 06:57:03 PM PDT 24 |
Peak memory | 218584 kb |
Host | smart-16b08c77-ff69-46d0-bc94-61b93b61deac |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008241760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux. 4008241760 |
Directory | /workspace/26.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/26.lc_ctrl_security_escalation.3771033867 |
Short name | T682 |
Test name | |
Test status | |
Simulation time | 855738548 ps |
CPU time | 10.09 seconds |
Started | Jun 30 06:56:43 PM PDT 24 |
Finished | Jun 30 06:56:54 PM PDT 24 |
Peak memory | 218692 kb |
Host | smart-8141d1c0-00df-4638-a184-0f733322d130 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3771033867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.3771033867 |
Directory | /workspace/26.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/26.lc_ctrl_smoke.4216891920 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 53069003 ps |
CPU time | 2.99 seconds |
Started | Jun 30 06:56:42 PM PDT 24 |
Finished | Jun 30 06:56:46 PM PDT 24 |
Peak memory | 218096 kb |
Host | smart-73a6cc45-56a2-453e-af3d-ff5cf6a877d4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4216891920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.4216891920 |
Directory | /workspace/26.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/26.lc_ctrl_state_failure.782486570 |
Short name | T317 |
Test name | |
Test status | |
Simulation time | 845574094 ps |
CPU time | 23.38 seconds |
Started | Jun 30 06:56:41 PM PDT 24 |
Finished | Jun 30 06:57:06 PM PDT 24 |
Peak memory | 251336 kb |
Host | smart-419254ab-f49a-4ed2-9510-de02ce7d1e50 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=782486570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.782486570 |
Directory | /workspace/26.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/26.lc_ctrl_state_post_trans.4185231160 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 206898537 ps |
CPU time | 6.49 seconds |
Started | Jun 30 06:56:42 PM PDT 24 |
Finished | Jun 30 06:56:50 PM PDT 24 |
Peak memory | 247216 kb |
Host | smart-0cc91c3f-7e2f-4c4b-9860-bcad234b1e96 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4185231160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.4185231160 |
Directory | /workspace/26.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/26.lc_ctrl_stress_all.833442207 |
Short name | T441 |
Test name | |
Test status | |
Simulation time | 4677207952 ps |
CPU time | 127.22 seconds |
Started | Jun 30 06:56:49 PM PDT 24 |
Finished | Jun 30 06:58:59 PM PDT 24 |
Peak memory | 276604 kb |
Host | smart-ebde5bc2-3f86-4403-b5ce-64d5f5598aaf |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833442207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all.833442207 |
Directory | /workspace/26.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.2757382981 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 56627859008 ps |
CPU time | 616.8 seconds |
Started | Jun 30 06:56:48 PM PDT 24 |
Finished | Jun 30 07:07:08 PM PDT 24 |
Peak memory | 448164 kb |
Host | smart-b18c147d-e355-4d9f-b385-0115e02dd160 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2757382981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all_with_rand_reset.2757382981 |
Directory | /workspace/26.lc_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1227741816 |
Short name | T605 |
Test name | |
Test status | |
Simulation time | 17572520 ps |
CPU time | 0.95 seconds |
Started | Jun 30 06:56:40 PM PDT 24 |
Finished | Jun 30 06:56:43 PM PDT 24 |
Peak memory | 212212 kb |
Host | smart-b7700965-6b0a-4919-9dd1-1f140eaa4397 |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227741816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c trl_volatile_unlock_smoke.1227741816 |
Directory | /workspace/26.lc_ctrl_volatile_unlock_smoke/latest |
Test location | /workspace/coverage/default/27.lc_ctrl_alert_test.2987751605 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 42307407 ps |
CPU time | 0.85 seconds |
Started | Jun 30 06:56:50 PM PDT 24 |
Finished | Jun 30 06:56:53 PM PDT 24 |
Peak memory | 209204 kb |
Host | smart-05a48641-71a1-4888-b45e-8ced115d4867 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987751605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.2987751605 |
Directory | /workspace/27.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/27.lc_ctrl_errors.3961969361 |
Short name | T465 |
Test name | |
Test status | |
Simulation time | 868370083 ps |
CPU time | 21.36 seconds |
Started | Jun 30 06:56:49 PM PDT 24 |
Finished | Jun 30 06:57:13 PM PDT 24 |
Peak memory | 218588 kb |
Host | smart-d0ad7e9c-1136-4b16-81e0-7ca558c5aea1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3961969361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.3961969361 |
Directory | /workspace/27.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/27.lc_ctrl_jtag_access.2427865868 |
Short name | T483 |
Test name | |
Test status | |
Simulation time | 1491940439 ps |
CPU time | 5.31 seconds |
Started | Jun 30 06:56:47 PM PDT 24 |
Finished | Jun 30 06:56:54 PM PDT 24 |
Peak memory | 217524 kb |
Host | smart-aa2191ce-2f0a-4801-ab6c-b10f4ad2c693 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427865868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.2427865868 |
Directory | /workspace/27.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/27.lc_ctrl_prog_failure.3766487145 |
Short name | T534 |
Test name | |
Test status | |
Simulation time | 43430925 ps |
CPU time | 2.29 seconds |
Started | Jun 30 06:56:46 PM PDT 24 |
Finished | Jun 30 06:56:51 PM PDT 24 |
Peak memory | 218636 kb |
Host | smart-2da8a30a-54d4-4c51-be33-76a755162c9b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3766487145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.3766487145 |
Directory | /workspace/27.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/27.lc_ctrl_sec_mubi.877288507 |
Short name | T788 |
Test name | |
Test status | |
Simulation time | 307630259 ps |
CPU time | 10.34 seconds |
Started | Jun 30 06:56:48 PM PDT 24 |
Finished | Jun 30 06:57:01 PM PDT 24 |
Peak memory | 226452 kb |
Host | smart-bd64312e-cfb0-4256-a578-c287061da32b |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877288507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.877288507 |
Directory | /workspace/27.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/27.lc_ctrl_sec_token_digest.1324694477 |
Short name | T393 |
Test name | |
Test status | |
Simulation time | 209000908 ps |
CPU time | 9.14 seconds |
Started | Jun 30 06:56:47 PM PDT 24 |
Finished | Jun 30 06:56:59 PM PDT 24 |
Peak memory | 218596 kb |
Host | smart-bfadef2b-e67e-4060-bb6e-315d3a0af781 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324694477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d igest.1324694477 |
Directory | /workspace/27.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/27.lc_ctrl_security_escalation.4229219962 |
Short name | T492 |
Test name | |
Test status | |
Simulation time | 1539875855 ps |
CPU time | 11.71 seconds |
Started | Jun 30 06:56:49 PM PDT 24 |
Finished | Jun 30 06:57:03 PM PDT 24 |
Peak memory | 218704 kb |
Host | smart-02d17ecb-0ce4-41f8-a6f3-ad22469a45c3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4229219962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.4229219962 |
Directory | /workspace/27.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/27.lc_ctrl_smoke.2965457267 |
Short name | T652 |
Test name | |
Test status | |
Simulation time | 360111005 ps |
CPU time | 1.8 seconds |
Started | Jun 30 06:56:48 PM PDT 24 |
Finished | Jun 30 06:56:52 PM PDT 24 |
Peak memory | 214296 kb |
Host | smart-06723e1d-c921-4298-8f4e-0d6aa5f36775 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2965457267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.2965457267 |
Directory | /workspace/27.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/27.lc_ctrl_state_failure.65349946 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 691324961 ps |
CPU time | 29.72 seconds |
Started | Jun 30 06:56:47 PM PDT 24 |
Finished | Jun 30 06:57:19 PM PDT 24 |
Peak memory | 251304 kb |
Host | smart-d8fc26f9-2859-4751-9f61-84274d5db779 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=65349946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.65349946 |
Directory | /workspace/27.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/27.lc_ctrl_state_post_trans.751476507 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 417820528 ps |
CPU time | 6.95 seconds |
Started | Jun 30 06:56:49 PM PDT 24 |
Finished | Jun 30 06:56:58 PM PDT 24 |
Peak memory | 251320 kb |
Host | smart-0cd93dcd-c918-4a0d-8c63-39453235cddd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=751476507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.751476507 |
Directory | /workspace/27.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.943944043 |
Short name | T455 |
Test name | |
Test status | |
Simulation time | 22867157 ps |
CPU time | 0.96 seconds |
Started | Jun 30 06:56:50 PM PDT 24 |
Finished | Jun 30 06:56:53 PM PDT 24 |
Peak memory | 209284 kb |
Host | smart-6c794577-4f8d-4def-9980-c9720399ca30 |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943944043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ct rl_volatile_unlock_smoke.943944043 |
Directory | /workspace/27.lc_ctrl_volatile_unlock_smoke/latest |
Test location | /workspace/coverage/default/28.lc_ctrl_alert_test.4289917779 |
Short name | T282 |
Test name | |
Test status | |
Simulation time | 84395473 ps |
CPU time | 1.15 seconds |
Started | Jun 30 06:56:54 PM PDT 24 |
Finished | Jun 30 06:56:57 PM PDT 24 |
Peak memory | 209352 kb |
Host | smart-1db2f6d4-9725-4c4d-bb78-c4ed7bd2478d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289917779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.4289917779 |
Directory | /workspace/28.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/28.lc_ctrl_errors.3626903860 |
Short name | T512 |
Test name | |
Test status | |
Simulation time | 241084840 ps |
CPU time | 9.73 seconds |
Started | Jun 30 06:56:50 PM PDT 24 |
Finished | Jun 30 06:57:02 PM PDT 24 |
Peak memory | 218632 kb |
Host | smart-92a45c9a-efec-4389-a6b2-f11ed62815d9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3626903860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.3626903860 |
Directory | /workspace/28.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/28.lc_ctrl_jtag_access.3264915769 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 376468317 ps |
CPU time | 5.87 seconds |
Started | Jun 30 06:56:55 PM PDT 24 |
Finished | Jun 30 06:57:02 PM PDT 24 |
Peak memory | 217744 kb |
Host | smart-1d5d9c48-e2a1-47d6-a973-c8383536843f |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264915769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.3264915769 |
Directory | /workspace/28.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/28.lc_ctrl_prog_failure.1071455830 |
Short name | T872 |
Test name | |
Test status | |
Simulation time | 64052178 ps |
CPU time | 3.53 seconds |
Started | Jun 30 06:56:49 PM PDT 24 |
Finished | Jun 30 06:56:55 PM PDT 24 |
Peak memory | 222848 kb |
Host | smart-39a9fd61-c1dc-4cd3-8213-1d975824221f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1071455830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.1071455830 |
Directory | /workspace/28.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/28.lc_ctrl_sec_mubi.1839078590 |
Short name | T323 |
Test name | |
Test status | |
Simulation time | 437116154 ps |
CPU time | 11.84 seconds |
Started | Jun 30 06:56:53 PM PDT 24 |
Finished | Jun 30 06:57:07 PM PDT 24 |
Peak memory | 226476 kb |
Host | smart-ec3685f7-35b5-41c9-a4db-56490ee1f9f0 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839078590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.1839078590 |
Directory | /workspace/28.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/28.lc_ctrl_sec_token_digest.1024660644 |
Short name | T656 |
Test name | |
Test status | |
Simulation time | 409427691 ps |
CPU time | 8.8 seconds |
Started | Jun 30 06:56:54 PM PDT 24 |
Finished | Jun 30 06:57:04 PM PDT 24 |
Peak memory | 218668 kb |
Host | smart-52f9b341-e0a6-48c5-b65a-df90333dbcbd |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024660644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d igest.1024660644 |
Directory | /workspace/28.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/28.lc_ctrl_sec_token_mux.556979621 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 1002659598 ps |
CPU time | 9.91 seconds |
Started | Jun 30 06:56:54 PM PDT 24 |
Finished | Jun 30 06:57:05 PM PDT 24 |
Peak memory | 218528 kb |
Host | smart-4a4880e5-fdf5-455c-81ac-d4220489fbfe |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556979621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.556979621 |
Directory | /workspace/28.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/28.lc_ctrl_security_escalation.917902010 |
Short name | T814 |
Test name | |
Test status | |
Simulation time | 4472835836 ps |
CPU time | 12.31 seconds |
Started | Jun 30 06:56:49 PM PDT 24 |
Finished | Jun 30 06:57:03 PM PDT 24 |
Peak memory | 226504 kb |
Host | smart-a3d020eb-bee9-45ec-b553-558d07680d0d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=917902010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.917902010 |
Directory | /workspace/28.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/28.lc_ctrl_smoke.1599988758 |
Short name | T287 |
Test name | |
Test status | |
Simulation time | 36762365 ps |
CPU time | 3.01 seconds |
Started | Jun 30 06:56:49 PM PDT 24 |
Finished | Jun 30 06:56:55 PM PDT 24 |
Peak memory | 224064 kb |
Host | smart-514b3fa2-87ef-4aaf-8032-fc6498f26703 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1599988758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.1599988758 |
Directory | /workspace/28.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/28.lc_ctrl_state_failure.2225842477 |
Short name | T521 |
Test name | |
Test status | |
Simulation time | 214112422 ps |
CPU time | 24.85 seconds |
Started | Jun 30 06:56:51 PM PDT 24 |
Finished | Jun 30 06:57:18 PM PDT 24 |
Peak memory | 251412 kb |
Host | smart-94ba0fa2-c02a-470c-8188-a10d10a2100b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2225842477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.2225842477 |
Directory | /workspace/28.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/28.lc_ctrl_state_post_trans.3776401482 |
Short name | T339 |
Test name | |
Test status | |
Simulation time | 285719125 ps |
CPU time | 8.5 seconds |
Started | Jun 30 06:56:49 PM PDT 24 |
Finished | Jun 30 06:56:59 PM PDT 24 |
Peak memory | 251340 kb |
Host | smart-410b586e-572a-499d-9fff-1b31b7ba0595 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3776401482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.3776401482 |
Directory | /workspace/28.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/28.lc_ctrl_stress_all.169167360 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 17192268732 ps |
CPU time | 362.34 seconds |
Started | Jun 30 06:56:52 PM PDT 24 |
Finished | Jun 30 07:02:56 PM PDT 24 |
Peak memory | 272972 kb |
Host | smart-9f794710-48b2-4a15-91d2-f266e0212ceb |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169167360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all.169167360 |
Directory | /workspace/28.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.759628669 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 37239129 ps |
CPU time | 0.77 seconds |
Started | Jun 30 06:56:49 PM PDT 24 |
Finished | Jun 30 06:56:52 PM PDT 24 |
Peak memory | 209040 kb |
Host | smart-330ebd63-781a-4ba2-a208-54ea29cf19af |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759628669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ct rl_volatile_unlock_smoke.759628669 |
Directory | /workspace/28.lc_ctrl_volatile_unlock_smoke/latest |
Test location | /workspace/coverage/default/29.lc_ctrl_alert_test.1077625128 |
Short name | T584 |
Test name | |
Test status | |
Simulation time | 97188351 ps |
CPU time | 0.82 seconds |
Started | Jun 30 06:56:54 PM PDT 24 |
Finished | Jun 30 06:56:57 PM PDT 24 |
Peak memory | 209380 kb |
Host | smart-9c891cf1-7f1e-42c0-8a0d-68f165ec1cfe |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077625128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.1077625128 |
Directory | /workspace/29.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/29.lc_ctrl_errors.1717301785 |
Short name | T366 |
Test name | |
Test status | |
Simulation time | 4179921072 ps |
CPU time | 18.44 seconds |
Started | Jun 30 06:56:54 PM PDT 24 |
Finished | Jun 30 06:57:14 PM PDT 24 |
Peak memory | 226708 kb |
Host | smart-1eedc399-a34a-4101-aca0-d11db48b92b2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1717301785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.1717301785 |
Directory | /workspace/29.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/29.lc_ctrl_jtag_access.2889525676 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 151981238 ps |
CPU time | 2.65 seconds |
Started | Jun 30 06:56:55 PM PDT 24 |
Finished | Jun 30 06:56:59 PM PDT 24 |
Peak memory | 217544 kb |
Host | smart-5b023b3e-8876-427c-a022-bfdb2f5ef3e5 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889525676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.2889525676 |
Directory | /workspace/29.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/29.lc_ctrl_prog_failure.129120392 |
Short name | T604 |
Test name | |
Test status | |
Simulation time | 173294105 ps |
CPU time | 2.42 seconds |
Started | Jun 30 06:56:53 PM PDT 24 |
Finished | Jun 30 06:56:57 PM PDT 24 |
Peak memory | 222568 kb |
Host | smart-e3f3064e-aa32-4926-bb45-8609931cc1d4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=129120392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.129120392 |
Directory | /workspace/29.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/29.lc_ctrl_sec_mubi.305167335 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 470713318 ps |
CPU time | 18.55 seconds |
Started | Jun 30 06:56:54 PM PDT 24 |
Finished | Jun 30 06:57:14 PM PDT 24 |
Peak memory | 226456 kb |
Host | smart-9731fae8-c54a-4a00-a3d7-d4f21e118f28 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305167335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.305167335 |
Directory | /workspace/29.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/29.lc_ctrl_sec_token_digest.198118472 |
Short name | T569 |
Test name | |
Test status | |
Simulation time | 893159556 ps |
CPU time | 8.83 seconds |
Started | Jun 30 06:56:57 PM PDT 24 |
Finished | Jun 30 06:57:07 PM PDT 24 |
Peak memory | 218736 kb |
Host | smart-e443bd52-743b-4649-becc-283665085d2c |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198118472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_di gest.198118472 |
Directory | /workspace/29.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/29.lc_ctrl_sec_token_mux.1078591237 |
Short name | T676 |
Test name | |
Test status | |
Simulation time | 629243354 ps |
CPU time | 13.23 seconds |
Started | Jun 30 06:56:54 PM PDT 24 |
Finished | Jun 30 06:57:09 PM PDT 24 |
Peak memory | 218516 kb |
Host | smart-64e0393a-364f-40e4-9198-1c632105e095 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078591237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux. 1078591237 |
Directory | /workspace/29.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/29.lc_ctrl_security_escalation.311722767 |
Short name | T490 |
Test name | |
Test status | |
Simulation time | 250155501 ps |
CPU time | 7.31 seconds |
Started | Jun 30 06:56:57 PM PDT 24 |
Finished | Jun 30 06:57:05 PM PDT 24 |
Peak memory | 225656 kb |
Host | smart-64ab51fd-9456-41f0-9e6c-d86128248394 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=311722767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.311722767 |
Directory | /workspace/29.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/29.lc_ctrl_smoke.1854984070 |
Short name | T663 |
Test name | |
Test status | |
Simulation time | 102526209 ps |
CPU time | 3.1 seconds |
Started | Jun 30 06:56:57 PM PDT 24 |
Finished | Jun 30 06:57:01 PM PDT 24 |
Peak memory | 215356 kb |
Host | smart-5df1b536-91fa-4edd-9600-d0debe68adb0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1854984070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.1854984070 |
Directory | /workspace/29.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/29.lc_ctrl_state_failure.2867953487 |
Short name | T418 |
Test name | |
Test status | |
Simulation time | 682121054 ps |
CPU time | 25.32 seconds |
Started | Jun 30 06:56:55 PM PDT 24 |
Finished | Jun 30 06:57:22 PM PDT 24 |
Peak memory | 251244 kb |
Host | smart-0989d875-ac1d-40df-9f32-56b0e0ff768b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2867953487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.2867953487 |
Directory | /workspace/29.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/29.lc_ctrl_state_post_trans.1475940603 |
Short name | T636 |
Test name | |
Test status | |
Simulation time | 292007851 ps |
CPU time | 7.21 seconds |
Started | Jun 30 06:56:54 PM PDT 24 |
Finished | Jun 30 06:57:03 PM PDT 24 |
Peak memory | 247096 kb |
Host | smart-ea5c65e8-5dfc-479b-9173-e6b6e4814ad0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1475940603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.1475940603 |
Directory | /workspace/29.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/29.lc_ctrl_stress_all.1765136508 |
Short name | T430 |
Test name | |
Test status | |
Simulation time | 4587000773 ps |
CPU time | 53.38 seconds |
Started | Jun 30 06:57:00 PM PDT 24 |
Finished | Jun 30 06:57:55 PM PDT 24 |
Peak memory | 251372 kb |
Host | smart-1e3e7cea-1305-4384-9b2c-028d86a11894 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765136508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all.1765136508 |
Directory | /workspace/29.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.226719602 |
Short name | T378 |
Test name | |
Test status | |
Simulation time | 30413929 ps |
CPU time | 0.86 seconds |
Started | Jun 30 06:57:00 PM PDT 24 |
Finished | Jun 30 06:57:03 PM PDT 24 |
Peak memory | 209280 kb |
Host | smart-cf936d4a-0861-4f1c-8078-2ef8c6f413f7 |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226719602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ct rl_volatile_unlock_smoke.226719602 |
Directory | /workspace/29.lc_ctrl_volatile_unlock_smoke/latest |
Test location | /workspace/coverage/default/3.lc_ctrl_alert_test.2476632187 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 25121585 ps |
CPU time | 1.01 seconds |
Started | Jun 30 06:55:03 PM PDT 24 |
Finished | Jun 30 06:55:05 PM PDT 24 |
Peak memory | 209344 kb |
Host | smart-755d92b5-0c4c-419f-801a-7cc91373e764 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476632187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.2476632187 |
Directory | /workspace/3.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/3.lc_ctrl_claim_transition_if.3841501866 |
Short name | T695 |
Test name | |
Test status | |
Simulation time | 35775820 ps |
CPU time | 0.78 seconds |
Started | Jun 30 06:55:01 PM PDT 24 |
Finished | Jun 30 06:55:03 PM PDT 24 |
Peak memory | 209304 kb |
Host | smart-b41a54c5-2b88-4abd-bb7d-15da1b3f5044 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3841501866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.3841501866 |
Directory | /workspace/3.lc_ctrl_claim_transition_if/latest |
Test location | /workspace/coverage/default/3.lc_ctrl_errors.2287184056 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 1099254691 ps |
CPU time | 11.38 seconds |
Started | Jun 30 06:54:58 PM PDT 24 |
Finished | Jun 30 06:55:10 PM PDT 24 |
Peak memory | 218652 kb |
Host | smart-cde77c3d-ab3c-45a5-b09e-44d3ca147a6b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2287184056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.2287184056 |
Directory | /workspace/3.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/3.lc_ctrl_jtag_access.1115533639 |
Short name | T424 |
Test name | |
Test status | |
Simulation time | 1061222432 ps |
CPU time | 23.29 seconds |
Started | Jun 30 06:55:03 PM PDT 24 |
Finished | Jun 30 06:55:27 PM PDT 24 |
Peak memory | 217688 kb |
Host | smart-0cb3554d-582c-4ba3-be0e-7bac35a892c7 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115533639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.1115533639 |
Directory | /workspace/3.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/3.lc_ctrl_jtag_errors.4036148352 |
Short name | T331 |
Test name | |
Test status | |
Simulation time | 2411074673 ps |
CPU time | 36.07 seconds |
Started | Jun 30 06:55:02 PM PDT 24 |
Finished | Jun 30 06:55:39 PM PDT 24 |
Peak memory | 220480 kb |
Host | smart-ba61462a-69ea-474f-8b60-4d5adfaca4f5 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036148352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er rors.4036148352 |
Directory | /workspace/3.lc_ctrl_jtag_errors/latest |
Test location | /workspace/coverage/default/3.lc_ctrl_jtag_priority.1382699410 |
Short name | T560 |
Test name | |
Test status | |
Simulation time | 225752176 ps |
CPU time | 5.6 seconds |
Started | Jun 30 06:55:01 PM PDT 24 |
Finished | Jun 30 06:55:08 PM PDT 24 |
Peak memory | 218028 kb |
Host | smart-6f7734b3-a22d-40ce-9b1e-fa25aa00c460 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382699410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.1 382699410 |
Directory | /workspace/3.lc_ctrl_jtag_priority/latest |
Test location | /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.3470280228 |
Short name | T466 |
Test name | |
Test status | |
Simulation time | 462354954 ps |
CPU time | 8.45 seconds |
Started | Jun 30 06:55:02 PM PDT 24 |
Finished | Jun 30 06:55:12 PM PDT 24 |
Peak memory | 218500 kb |
Host | smart-c7fd6f89-e902-4f4b-8cbf-aef5c948ad8f |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470280228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag _prog_failure.3470280228 |
Directory | /workspace/3.lc_ctrl_jtag_prog_failure/latest |
Test location | /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.3230398006 |
Short name | T810 |
Test name | |
Test status | |
Simulation time | 1205117415 ps |
CPU time | 34.62 seconds |
Started | Jun 30 06:55:04 PM PDT 24 |
Finished | Jun 30 06:55:40 PM PDT 24 |
Peak memory | 217868 kb |
Host | smart-07cc5f8f-37b6-4239-8ca9-3c4dfd295673 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230398006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_ jtag_regwen_during_op.3230398006 |
Directory | /workspace/3.lc_ctrl_jtag_regwen_during_op/latest |
Test location | /workspace/coverage/default/3.lc_ctrl_jtag_smoke.931140863 |
Short name | T450 |
Test name | |
Test status | |
Simulation time | 2441257020 ps |
CPU time | 10.76 seconds |
Started | Jun 30 06:55:03 PM PDT 24 |
Finished | Jun 30 06:55:16 PM PDT 24 |
Peak memory | 218052 kb |
Host | smart-35cf305b-fd0b-4fa9-9399-0efbfc574902 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931140863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.931140863 |
Directory | /workspace/3.lc_ctrl_jtag_smoke/latest |
Test location | /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.2948910786 |
Short name | T846 |
Test name | |
Test status | |
Simulation time | 43164188235 ps |
CPU time | 134.85 seconds |
Started | Jun 30 06:55:04 PM PDT 24 |
Finished | Jun 30 06:57:20 PM PDT 24 |
Peak memory | 284068 kb |
Host | smart-44d11024-c176-49fe-bec0-e253082a9cd4 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948910786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta g_state_failure.2948910786 |
Directory | /workspace/3.lc_ctrl_jtag_state_failure/latest |
Test location | /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.608853946 |
Short name | T379 |
Test name | |
Test status | |
Simulation time | 3151256193 ps |
CPU time | 14.19 seconds |
Started | Jun 30 06:55:03 PM PDT 24 |
Finished | Jun 30 06:55:19 PM PDT 24 |
Peak memory | 251320 kb |
Host | smart-b1bab637-01f1-4d51-97e1-c5f45544a137 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608853946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_j tag_state_post_trans.608853946 |
Directory | /workspace/3.lc_ctrl_jtag_state_post_trans/latest |
Test location | /workspace/coverage/default/3.lc_ctrl_prog_failure.3601620461 |
Short name | T586 |
Test name | |
Test status | |
Simulation time | 38837008 ps |
CPU time | 1.5 seconds |
Started | Jun 30 06:55:00 PM PDT 24 |
Finished | Jun 30 06:55:03 PM PDT 24 |
Peak memory | 218628 kb |
Host | smart-9c722782-b728-4104-8859-4195efe9d801 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3601620461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.3601620461 |
Directory | /workspace/3.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/3.lc_ctrl_regwen_during_op.3399564756 |
Short name | T523 |
Test name | |
Test status | |
Simulation time | 1732117801 ps |
CPU time | 16.13 seconds |
Started | Jun 30 06:54:58 PM PDT 24 |
Finished | Jun 30 06:55:15 PM PDT 24 |
Peak memory | 214436 kb |
Host | smart-e5ed97be-1795-4586-852b-21fc06241eae |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3399564756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.3399564756 |
Directory | /workspace/3.lc_ctrl_regwen_during_op/latest |
Test location | /workspace/coverage/default/3.lc_ctrl_sec_cm.639108024 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 204499424 ps |
CPU time | 35.96 seconds |
Started | Jun 30 06:55:02 PM PDT 24 |
Finished | Jun 30 06:55:40 PM PDT 24 |
Peak memory | 282320 kb |
Host | smart-14a2b6da-40e6-4c55-834a-8d6ef0326000 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639108024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.639108024 |
Directory | /workspace/3.lc_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/3.lc_ctrl_sec_mubi.1540529175 |
Short name | T309 |
Test name | |
Test status | |
Simulation time | 1008789866 ps |
CPU time | 12.77 seconds |
Started | Jun 30 06:55:02 PM PDT 24 |
Finished | Jun 30 06:55:16 PM PDT 24 |
Peak memory | 226448 kb |
Host | smart-3ce31b8c-ecc8-46e0-b416-0e9134935a61 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540529175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.1540529175 |
Directory | /workspace/3.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/3.lc_ctrl_sec_token_digest.2033624676 |
Short name | T821 |
Test name | |
Test status | |
Simulation time | 3368373445 ps |
CPU time | 10.01 seconds |
Started | Jun 30 06:55:04 PM PDT 24 |
Finished | Jun 30 06:55:15 PM PDT 24 |
Peak memory | 218740 kb |
Host | smart-9381c852-0157-4001-95aa-7618ae0c65c0 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033624676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di gest.2033624676 |
Directory | /workspace/3.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/3.lc_ctrl_sec_token_mux.2032179858 |
Short name | T648 |
Test name | |
Test status | |
Simulation time | 1124475922 ps |
CPU time | 7 seconds |
Started | Jun 30 06:55:03 PM PDT 24 |
Finished | Jun 30 06:55:11 PM PDT 24 |
Peak memory | 218584 kb |
Host | smart-78269613-1c70-4d1f-b4db-5f4dcd3a1473 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032179858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.2 032179858 |
Directory | /workspace/3.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/3.lc_ctrl_smoke.3041523487 |
Short name | T579 |
Test name | |
Test status | |
Simulation time | 183808569 ps |
CPU time | 4.91 seconds |
Started | Jun 30 06:54:56 PM PDT 24 |
Finished | Jun 30 06:55:01 PM PDT 24 |
Peak memory | 218088 kb |
Host | smart-6878248e-243e-403a-a4dd-3d3345d844c0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3041523487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.3041523487 |
Directory | /workspace/3.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/3.lc_ctrl_state_failure.3091412921 |
Short name | T546 |
Test name | |
Test status | |
Simulation time | 438437651 ps |
CPU time | 30.34 seconds |
Started | Jun 30 06:54:58 PM PDT 24 |
Finished | Jun 30 06:55:30 PM PDT 24 |
Peak memory | 251332 kb |
Host | smart-2610a18b-ef7c-49ad-a38c-97cf0fd87a23 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3091412921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.3091412921 |
Directory | /workspace/3.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/3.lc_ctrl_state_post_trans.4153331217 |
Short name | T326 |
Test name | |
Test status | |
Simulation time | 168457338 ps |
CPU time | 6.81 seconds |
Started | Jun 30 06:55:01 PM PDT 24 |
Finished | Jun 30 06:55:09 PM PDT 24 |
Peak memory | 247120 kb |
Host | smart-3c7c1613-a050-4bc6-a0b9-296d492ae3a3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4153331217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.4153331217 |
Directory | /workspace/3.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/3.lc_ctrl_stress_all.4226728083 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 22832049036 ps |
CPU time | 103.42 seconds |
Started | Jun 30 06:55:05 PM PDT 24 |
Finished | Jun 30 06:56:49 PM PDT 24 |
Peak memory | 234980 kb |
Host | smart-be445714-989a-47bf-a562-361c69e60099 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226728083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all.4226728083 |
Directory | /workspace/3.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.3445268773 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 11544354262 ps |
CPU time | 220.29 seconds |
Started | Jun 30 06:55:03 PM PDT 24 |
Finished | Jun 30 06:58:45 PM PDT 24 |
Peak memory | 259720 kb |
Host | smart-ed695ac2-2110-4b32-b895-db1c808bfeb8 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3445268773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all_with_rand_reset.3445268773 |
Directory | /workspace/3.lc_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.186182986 |
Short name | T858 |
Test name | |
Test status | |
Simulation time | 47860362 ps |
CPU time | 1.08 seconds |
Started | Jun 30 06:54:57 PM PDT 24 |
Finished | Jun 30 06:54:59 PM PDT 24 |
Peak memory | 212296 kb |
Host | smart-e72f1433-4251-4ab7-b2d6-2075ec35ac69 |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186182986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctr l_volatile_unlock_smoke.186182986 |
Directory | /workspace/3.lc_ctrl_volatile_unlock_smoke/latest |
Test location | /workspace/coverage/default/30.lc_ctrl_alert_test.2971923224 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 69063018 ps |
CPU time | 1.16 seconds |
Started | Jun 30 06:57:00 PM PDT 24 |
Finished | Jun 30 06:57:03 PM PDT 24 |
Peak memory | 209388 kb |
Host | smart-c87c95d4-c77f-40e9-9dab-c17849dc1ebb |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971923224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.2971923224 |
Directory | /workspace/30.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/30.lc_ctrl_errors.2085271582 |
Short name | T838 |
Test name | |
Test status | |
Simulation time | 239817629 ps |
CPU time | 8.71 seconds |
Started | Jun 30 06:56:54 PM PDT 24 |
Finished | Jun 30 06:57:05 PM PDT 24 |
Peak memory | 226456 kb |
Host | smart-481c046d-6e89-4f05-a462-00111f2de050 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2085271582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.2085271582 |
Directory | /workspace/30.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/30.lc_ctrl_jtag_access.3794489560 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 109421638 ps |
CPU time | 1.88 seconds |
Started | Jun 30 06:56:57 PM PDT 24 |
Finished | Jun 30 06:57:00 PM PDT 24 |
Peak memory | 217572 kb |
Host | smart-bb6bf383-c858-4f28-bcf5-d046c322bbf5 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794489560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.3794489560 |
Directory | /workspace/30.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/30.lc_ctrl_prog_failure.3990576792 |
Short name | T333 |
Test name | |
Test status | |
Simulation time | 371961433 ps |
CPU time | 4.05 seconds |
Started | Jun 30 06:56:53 PM PDT 24 |
Finished | Jun 30 06:56:59 PM PDT 24 |
Peak memory | 223096 kb |
Host | smart-bc101bd8-d270-4f17-a87d-b41515f5e433 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3990576792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.3990576792 |
Directory | /workspace/30.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/30.lc_ctrl_sec_mubi.1143772705 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 224341626 ps |
CPU time | 11.4 seconds |
Started | Jun 30 06:57:00 PM PDT 24 |
Finished | Jun 30 06:57:13 PM PDT 24 |
Peak memory | 226416 kb |
Host | smart-057f17b6-9ec1-458a-b30c-1d97e47448d6 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143772705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.1143772705 |
Directory | /workspace/30.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/30.lc_ctrl_sec_token_mux.1814043435 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 490369360 ps |
CPU time | 9.63 seconds |
Started | Jun 30 06:56:53 PM PDT 24 |
Finished | Jun 30 06:57:05 PM PDT 24 |
Peak memory | 218592 kb |
Host | smart-f6db8541-3100-494d-8477-a2cca5d47b12 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814043435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux. 1814043435 |
Directory | /workspace/30.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/30.lc_ctrl_security_escalation.1645089235 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 7541045190 ps |
CPU time | 14.55 seconds |
Started | Jun 30 06:56:53 PM PDT 24 |
Finished | Jun 30 06:57:09 PM PDT 24 |
Peak memory | 226412 kb |
Host | smart-2630d26e-048d-4400-9b90-e6faae00b2ff |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1645089235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.1645089235 |
Directory | /workspace/30.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/30.lc_ctrl_smoke.2006950202 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 30752402 ps |
CPU time | 2.05 seconds |
Started | Jun 30 06:56:52 PM PDT 24 |
Finished | Jun 30 06:56:56 PM PDT 24 |
Peak memory | 214656 kb |
Host | smart-a2b43947-0a29-49da-b561-a6c4efa08efb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2006950202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.2006950202 |
Directory | /workspace/30.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/30.lc_ctrl_state_failure.4086930408 |
Short name | T295 |
Test name | |
Test status | |
Simulation time | 626424527 ps |
CPU time | 30.94 seconds |
Started | Jun 30 06:56:57 PM PDT 24 |
Finished | Jun 30 06:57:29 PM PDT 24 |
Peak memory | 251328 kb |
Host | smart-b0910eb5-cda5-4d06-8924-8f70323f4b64 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4086930408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.4086930408 |
Directory | /workspace/30.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/30.lc_ctrl_state_post_trans.3114099748 |
Short name | T449 |
Test name | |
Test status | |
Simulation time | 390719884 ps |
CPU time | 6.86 seconds |
Started | Jun 30 06:56:57 PM PDT 24 |
Finished | Jun 30 06:57:05 PM PDT 24 |
Peak memory | 247352 kb |
Host | smart-3f18da38-171d-43c1-bdee-c77f64924c66 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3114099748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.3114099748 |
Directory | /workspace/30.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/30.lc_ctrl_stress_all.4229993670 |
Short name | T809 |
Test name | |
Test status | |
Simulation time | 5599522759 ps |
CPU time | 120.45 seconds |
Started | Jun 30 06:57:00 PM PDT 24 |
Finished | Jun 30 06:59:02 PM PDT 24 |
Peak memory | 274764 kb |
Host | smart-b18a08b9-2e02-4124-81da-eb7ba4b5b303 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229993670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all.4229993670 |
Directory | /workspace/30.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.2663297579 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 13078899433 ps |
CPU time | 419.99 seconds |
Started | Jun 30 06:57:03 PM PDT 24 |
Finished | Jun 30 07:04:03 PM PDT 24 |
Peak memory | 316928 kb |
Host | smart-6a4f3aac-8797-47cb-a7c0-43c41043604b |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2663297579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.2663297579 |
Directory | /workspace/30.lc_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.182983985 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 95720007 ps |
CPU time | 1 seconds |
Started | Jun 30 06:56:55 PM PDT 24 |
Finished | Jun 30 06:56:58 PM PDT 24 |
Peak memory | 212220 kb |
Host | smart-fa862e37-39bb-4311-b22d-3791197a5a18 |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182983985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ct rl_volatile_unlock_smoke.182983985 |
Directory | /workspace/30.lc_ctrl_volatile_unlock_smoke/latest |
Test location | /workspace/coverage/default/31.lc_ctrl_alert_test.4024742179 |
Short name | T591 |
Test name | |
Test status | |
Simulation time | 16451729 ps |
CPU time | 1.08 seconds |
Started | Jun 30 06:57:04 PM PDT 24 |
Finished | Jun 30 06:57:07 PM PDT 24 |
Peak memory | 209456 kb |
Host | smart-097ae908-7556-406b-b877-4b909432869e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024742179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.4024742179 |
Directory | /workspace/31.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/31.lc_ctrl_errors.2873894453 |
Short name | T744 |
Test name | |
Test status | |
Simulation time | 1012354226 ps |
CPU time | 10.54 seconds |
Started | Jun 30 06:57:00 PM PDT 24 |
Finished | Jun 30 06:57:12 PM PDT 24 |
Peak memory | 218592 kb |
Host | smart-38041c61-8603-40ec-bc3a-d7aa9f29c369 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2873894453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.2873894453 |
Directory | /workspace/31.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/31.lc_ctrl_jtag_access.1704497633 |
Short name | T737 |
Test name | |
Test status | |
Simulation time | 596593174 ps |
CPU time | 8.25 seconds |
Started | Jun 30 06:57:01 PM PDT 24 |
Finished | Jun 30 06:57:11 PM PDT 24 |
Peak memory | 217764 kb |
Host | smart-da127213-ab36-4a9a-9d67-0a51c0198361 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704497633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.1704497633 |
Directory | /workspace/31.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/31.lc_ctrl_prog_failure.1215876975 |
Short name | T683 |
Test name | |
Test status | |
Simulation time | 326329322 ps |
CPU time | 3.67 seconds |
Started | Jun 30 06:57:03 PM PDT 24 |
Finished | Jun 30 06:57:07 PM PDT 24 |
Peak memory | 218632 kb |
Host | smart-90fbaa1a-d222-41c9-8dfa-2598f8b351f7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1215876975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.1215876975 |
Directory | /workspace/31.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/31.lc_ctrl_sec_mubi.156773845 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 5947315528 ps |
CPU time | 11.55 seconds |
Started | Jun 30 06:56:58 PM PDT 24 |
Finished | Jun 30 06:57:12 PM PDT 24 |
Peak memory | 226424 kb |
Host | smart-e792d2d8-44a1-47c9-8e8c-11ad61b6fba2 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156773845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.156773845 |
Directory | /workspace/31.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/31.lc_ctrl_sec_token_digest.243888056 |
Short name | T692 |
Test name | |
Test status | |
Simulation time | 1146177253 ps |
CPU time | 14.84 seconds |
Started | Jun 30 06:56:59 PM PDT 24 |
Finished | Jun 30 06:57:16 PM PDT 24 |
Peak memory | 218684 kb |
Host | smart-86347633-9c82-4ef6-b74f-3e92918faa5c |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243888056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_di gest.243888056 |
Directory | /workspace/31.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/31.lc_ctrl_sec_token_mux.2173761388 |
Short name | T782 |
Test name | |
Test status | |
Simulation time | 1224561759 ps |
CPU time | 7.94 seconds |
Started | Jun 30 06:57:00 PM PDT 24 |
Finished | Jun 30 06:57:10 PM PDT 24 |
Peak memory | 218608 kb |
Host | smart-cdefb334-4f95-4d91-aea6-4b4cd605f496 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173761388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux. 2173761388 |
Directory | /workspace/31.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/31.lc_ctrl_security_escalation.826586642 |
Short name | T653 |
Test name | |
Test status | |
Simulation time | 631103517 ps |
CPU time | 7.47 seconds |
Started | Jun 30 06:57:01 PM PDT 24 |
Finished | Jun 30 06:57:10 PM PDT 24 |
Peak memory | 218740 kb |
Host | smart-6748008f-0e1b-4183-903d-af6d36eec77b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=826586642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.826586642 |
Directory | /workspace/31.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/31.lc_ctrl_smoke.222550079 |
Short name | T359 |
Test name | |
Test status | |
Simulation time | 128266469 ps |
CPU time | 1.93 seconds |
Started | Jun 30 06:57:01 PM PDT 24 |
Finished | Jun 30 06:57:04 PM PDT 24 |
Peak memory | 218036 kb |
Host | smart-5bc42368-f6e8-4af6-8fb8-b4048a52c585 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=222550079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.222550079 |
Directory | /workspace/31.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/31.lc_ctrl_state_failure.328494026 |
Short name | T611 |
Test name | |
Test status | |
Simulation time | 438941297 ps |
CPU time | 27.33 seconds |
Started | Jun 30 06:57:00 PM PDT 24 |
Finished | Jun 30 06:57:29 PM PDT 24 |
Peak memory | 251340 kb |
Host | smart-18956076-956f-4a2f-b810-f6bd78e1c411 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=328494026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.328494026 |
Directory | /workspace/31.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/31.lc_ctrl_state_post_trans.2226251758 |
Short name | T412 |
Test name | |
Test status | |
Simulation time | 96689135 ps |
CPU time | 3.72 seconds |
Started | Jun 30 06:57:00 PM PDT 24 |
Finished | Jun 30 06:57:05 PM PDT 24 |
Peak memory | 223060 kb |
Host | smart-f96c3543-7baf-4802-960b-05de2d8b9667 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2226251758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.2226251758 |
Directory | /workspace/31.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/31.lc_ctrl_stress_all.235998875 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 7131543509 ps |
CPU time | 263.3 seconds |
Started | Jun 30 06:57:01 PM PDT 24 |
Finished | Jun 30 07:01:26 PM PDT 24 |
Peak memory | 275972 kb |
Host | smart-c4a425c4-949d-4eff-9eb8-2cb32e16ef2a |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235998875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all.235998875 |
Directory | /workspace/31.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.3394467574 |
Short name | T637 |
Test name | |
Test status | |
Simulation time | 24093550 ps |
CPU time | 0.94 seconds |
Started | Jun 30 06:57:00 PM PDT 24 |
Finished | Jun 30 06:57:03 PM PDT 24 |
Peak memory | 212260 kb |
Host | smart-d0406582-71f1-4db9-b97a-803225766fe9 |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394467574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c trl_volatile_unlock_smoke.3394467574 |
Directory | /workspace/31.lc_ctrl_volatile_unlock_smoke/latest |
Test location | /workspace/coverage/default/32.lc_ctrl_alert_test.898389205 |
Short name | T650 |
Test name | |
Test status | |
Simulation time | 37871785 ps |
CPU time | 0.87 seconds |
Started | Jun 30 06:57:08 PM PDT 24 |
Finished | Jun 30 06:57:10 PM PDT 24 |
Peak memory | 209332 kb |
Host | smart-44e409d0-0762-4c42-ae4c-6230d3af9e5c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898389205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.898389205 |
Directory | /workspace/32.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/32.lc_ctrl_errors.4121288473 |
Short name | T357 |
Test name | |
Test status | |
Simulation time | 1070783161 ps |
CPU time | 14.75 seconds |
Started | Jun 30 06:57:04 PM PDT 24 |
Finished | Jun 30 06:57:20 PM PDT 24 |
Peak memory | 226444 kb |
Host | smart-bac920e1-f584-45d0-96b6-40439eac3aef |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4121288473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.4121288473 |
Directory | /workspace/32.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/32.lc_ctrl_jtag_access.2868444682 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 248192239 ps |
CPU time | 6.25 seconds |
Started | Jun 30 06:57:06 PM PDT 24 |
Finished | Jun 30 06:57:14 PM PDT 24 |
Peak memory | 217416 kb |
Host | smart-30069457-df54-4b53-af3d-8071e34547c0 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868444682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.2868444682 |
Directory | /workspace/32.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/32.lc_ctrl_prog_failure.284657267 |
Short name | T583 |
Test name | |
Test status | |
Simulation time | 25893467 ps |
CPU time | 1.98 seconds |
Started | Jun 30 06:57:05 PM PDT 24 |
Finished | Jun 30 06:57:09 PM PDT 24 |
Peak memory | 218508 kb |
Host | smart-64724ec8-e8a3-4fed-aa6e-1b5e66d183d5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=284657267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.284657267 |
Directory | /workspace/32.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/32.lc_ctrl_sec_mubi.2626592172 |
Short name | T592 |
Test name | |
Test status | |
Simulation time | 312830345 ps |
CPU time | 15.88 seconds |
Started | Jun 30 06:57:12 PM PDT 24 |
Finished | Jun 30 06:57:29 PM PDT 24 |
Peak memory | 226516 kb |
Host | smart-59e3d1a1-d603-4f8c-a984-392c51427dc3 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626592172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.2626592172 |
Directory | /workspace/32.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/32.lc_ctrl_sec_token_digest.1407186754 |
Short name | T510 |
Test name | |
Test status | |
Simulation time | 2112757068 ps |
CPU time | 10.34 seconds |
Started | Jun 30 06:57:12 PM PDT 24 |
Finished | Jun 30 06:57:23 PM PDT 24 |
Peak memory | 218584 kb |
Host | smart-8ec9378a-6192-4180-988d-8f60340f84f0 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407186754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d igest.1407186754 |
Directory | /workspace/32.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/32.lc_ctrl_sec_token_mux.1740596424 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 219629921 ps |
CPU time | 8.72 seconds |
Started | Jun 30 06:57:07 PM PDT 24 |
Finished | Jun 30 06:57:18 PM PDT 24 |
Peak memory | 226336 kb |
Host | smart-fcf02817-5578-4d10-9314-200dedf20879 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740596424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux. 1740596424 |
Directory | /workspace/32.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/32.lc_ctrl_security_escalation.2027701125 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 632354837 ps |
CPU time | 10.42 seconds |
Started | Jun 30 06:57:04 PM PDT 24 |
Finished | Jun 30 06:57:16 PM PDT 24 |
Peak memory | 218576 kb |
Host | smart-69312e4e-345d-46cc-b483-55a16b3c3db3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2027701125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.2027701125 |
Directory | /workspace/32.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/32.lc_ctrl_smoke.2029507417 |
Short name | T562 |
Test name | |
Test status | |
Simulation time | 40553635 ps |
CPU time | 1.14 seconds |
Started | Jun 30 06:57:06 PM PDT 24 |
Finished | Jun 30 06:57:09 PM PDT 24 |
Peak memory | 212352 kb |
Host | smart-dec09748-1a70-4780-b248-30dcc3a8ac65 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2029507417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.2029507417 |
Directory | /workspace/32.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/32.lc_ctrl_state_failure.1214322868 |
Short name | T741 |
Test name | |
Test status | |
Simulation time | 1304099355 ps |
CPU time | 36.5 seconds |
Started | Jun 30 06:57:07 PM PDT 24 |
Finished | Jun 30 06:57:45 PM PDT 24 |
Peak memory | 251320 kb |
Host | smart-5afe693a-29b5-47e5-a6f2-bb587f27055e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1214322868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.1214322868 |
Directory | /workspace/32.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/32.lc_ctrl_state_post_trans.1749102094 |
Short name | T731 |
Test name | |
Test status | |
Simulation time | 225154441 ps |
CPU time | 6.67 seconds |
Started | Jun 30 06:57:09 PM PDT 24 |
Finished | Jun 30 06:57:17 PM PDT 24 |
Peak memory | 247140 kb |
Host | smart-6664bbdd-3304-465e-8689-57c8f21cae1a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1749102094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.1749102094 |
Directory | /workspace/32.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/32.lc_ctrl_stress_all.4027709844 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 7877370814 ps |
CPU time | 219.49 seconds |
Started | Jun 30 06:57:07 PM PDT 24 |
Finished | Jun 30 07:00:48 PM PDT 24 |
Peak memory | 277336 kb |
Host | smart-6ef65d0e-3e3a-48e2-a76c-2808a533523e |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027709844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all.4027709844 |
Directory | /workspace/32.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.1073711323 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 45240085374 ps |
CPU time | 1614.08 seconds |
Started | Jun 30 06:57:06 PM PDT 24 |
Finished | Jun 30 07:24:02 PM PDT 24 |
Peak memory | 906064 kb |
Host | smart-64329c61-719b-4a4f-a7b0-f2d7697a1c75 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1073711323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.1073711323 |
Directory | /workspace/32.lc_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.876189509 |
Short name | T327 |
Test name | |
Test status | |
Simulation time | 56922362 ps |
CPU time | 0.94 seconds |
Started | Jun 30 06:57:04 PM PDT 24 |
Finished | Jun 30 06:57:06 PM PDT 24 |
Peak memory | 209296 kb |
Host | smart-2a3fb3aa-0259-4833-82d3-627a01e4dff9 |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876189509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ct rl_volatile_unlock_smoke.876189509 |
Directory | /workspace/32.lc_ctrl_volatile_unlock_smoke/latest |
Test location | /workspace/coverage/default/33.lc_ctrl_errors.695233278 |
Short name | T610 |
Test name | |
Test status | |
Simulation time | 2151808694 ps |
CPU time | 13.5 seconds |
Started | Jun 30 06:57:06 PM PDT 24 |
Finished | Jun 30 06:57:21 PM PDT 24 |
Peak memory | 218692 kb |
Host | smart-86fd3743-aab7-453c-b69c-1a63c9b381d7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=695233278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.695233278 |
Directory | /workspace/33.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/33.lc_ctrl_jtag_access.2344212087 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 152672882 ps |
CPU time | 4.7 seconds |
Started | Jun 30 06:57:07 PM PDT 24 |
Finished | Jun 30 06:57:14 PM PDT 24 |
Peak memory | 217440 kb |
Host | smart-49365540-37d4-426e-8872-fdf73e787a24 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344212087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.2344212087 |
Directory | /workspace/33.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/33.lc_ctrl_prog_failure.3891230069 |
Short name | T866 |
Test name | |
Test status | |
Simulation time | 76569202 ps |
CPU time | 2.83 seconds |
Started | Jun 30 06:57:05 PM PDT 24 |
Finished | Jun 30 06:57:10 PM PDT 24 |
Peak memory | 218632 kb |
Host | smart-3f3abd98-bd39-471c-ba5f-1397f88406fc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3891230069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.3891230069 |
Directory | /workspace/33.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/33.lc_ctrl_sec_mubi.2176552914 |
Short name | T511 |
Test name | |
Test status | |
Simulation time | 1999675925 ps |
CPU time | 15.99 seconds |
Started | Jun 30 06:57:12 PM PDT 24 |
Finished | Jun 30 06:57:29 PM PDT 24 |
Peak memory | 220388 kb |
Host | smart-980bf7aa-a142-43be-bc6b-3c2e75ce8829 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176552914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.2176552914 |
Directory | /workspace/33.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/33.lc_ctrl_sec_token_digest.1703105162 |
Short name | T509 |
Test name | |
Test status | |
Simulation time | 273068464 ps |
CPU time | 7.53 seconds |
Started | Jun 30 06:57:12 PM PDT 24 |
Finished | Jun 30 06:57:20 PM PDT 24 |
Peak memory | 218588 kb |
Host | smart-856afc53-7e9b-4d82-8d21-38570162059c |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703105162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d igest.1703105162 |
Directory | /workspace/33.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/33.lc_ctrl_sec_token_mux.1890020965 |
Short name | T400 |
Test name | |
Test status | |
Simulation time | 628353934 ps |
CPU time | 12.18 seconds |
Started | Jun 30 06:57:05 PM PDT 24 |
Finished | Jun 30 06:57:18 PM PDT 24 |
Peak memory | 218528 kb |
Host | smart-2cdb1ebc-b155-4512-a47e-89536f47a7d4 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890020965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux. 1890020965 |
Directory | /workspace/33.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/33.lc_ctrl_security_escalation.3942739397 |
Short name | T301 |
Test name | |
Test status | |
Simulation time | 985291567 ps |
CPU time | 12.31 seconds |
Started | Jun 30 06:57:04 PM PDT 24 |
Finished | Jun 30 06:57:18 PM PDT 24 |
Peak memory | 226368 kb |
Host | smart-2666007b-4544-47cf-a4e4-002fbb7d2e3a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3942739397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.3942739397 |
Directory | /workspace/33.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/33.lc_ctrl_smoke.1450764419 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 215782937 ps |
CPU time | 2.28 seconds |
Started | Jun 30 06:57:08 PM PDT 24 |
Finished | Jun 30 06:57:12 PM PDT 24 |
Peak memory | 214844 kb |
Host | smart-bd1eceb1-2c80-49f5-99f0-ccfd42fd499b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1450764419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.1450764419 |
Directory | /workspace/33.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/33.lc_ctrl_state_failure.2455736398 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 636697292 ps |
CPU time | 31.41 seconds |
Started | Jun 30 06:57:04 PM PDT 24 |
Finished | Jun 30 06:57:37 PM PDT 24 |
Peak memory | 251332 kb |
Host | smart-3c88229d-c01f-42a5-a1a6-8ae049010f44 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2455736398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.2455736398 |
Directory | /workspace/33.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/33.lc_ctrl_state_post_trans.4211573881 |
Short name | T857 |
Test name | |
Test status | |
Simulation time | 109354009 ps |
CPU time | 3.03 seconds |
Started | Jun 30 06:57:05 PM PDT 24 |
Finished | Jun 30 06:57:10 PM PDT 24 |
Peak memory | 218644 kb |
Host | smart-dfb808c1-918f-40fe-8df7-cea44bc7affa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4211573881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.4211573881 |
Directory | /workspace/33.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/33.lc_ctrl_stress_all.1228595419 |
Short name | T519 |
Test name | |
Test status | |
Simulation time | 5381950405 ps |
CPU time | 149.96 seconds |
Started | Jun 30 06:57:07 PM PDT 24 |
Finished | Jun 30 06:59:39 PM PDT 24 |
Peak memory | 277576 kb |
Host | smart-bdc97014-99af-4493-a7fb-0f7cb5104988 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228595419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all.1228595419 |
Directory | /workspace/33.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.4032989840 |
Short name | T724 |
Test name | |
Test status | |
Simulation time | 45442580131 ps |
CPU time | 607.78 seconds |
Started | Jun 30 06:57:09 PM PDT 24 |
Finished | Jun 30 07:07:18 PM PDT 24 |
Peak memory | 448132 kb |
Host | smart-4cc7b9fb-adf2-4677-bfd4-de2631e327c9 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=4032989840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.4032989840 |
Directory | /workspace/33.lc_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.951007708 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 24344968 ps |
CPU time | 0.8 seconds |
Started | Jun 30 06:57:06 PM PDT 24 |
Finished | Jun 30 06:57:09 PM PDT 24 |
Peak memory | 209412 kb |
Host | smart-42ed092a-3190-44a2-9f54-ccacfdc18ecb |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951007708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ct rl_volatile_unlock_smoke.951007708 |
Directory | /workspace/33.lc_ctrl_volatile_unlock_smoke/latest |
Test location | /workspace/coverage/default/34.lc_ctrl_alert_test.2436133509 |
Short name | T618 |
Test name | |
Test status | |
Simulation time | 21537842 ps |
CPU time | 1.03 seconds |
Started | Jun 30 06:57:13 PM PDT 24 |
Finished | Jun 30 06:57:16 PM PDT 24 |
Peak memory | 209340 kb |
Host | smart-65ece237-3f82-43d8-8c4c-20ff0e47a314 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436133509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.2436133509 |
Directory | /workspace/34.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/34.lc_ctrl_errors.2593144527 |
Short name | T760 |
Test name | |
Test status | |
Simulation time | 365508700 ps |
CPU time | 11.95 seconds |
Started | Jun 30 06:57:13 PM PDT 24 |
Finished | Jun 30 06:57:26 PM PDT 24 |
Peak memory | 218640 kb |
Host | smart-857a2bc7-9bfc-45ea-afe5-3e1ac91d9bce |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2593144527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.2593144527 |
Directory | /workspace/34.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/34.lc_ctrl_jtag_access.1130890953 |
Short name | T580 |
Test name | |
Test status | |
Simulation time | 496837153 ps |
CPU time | 13.17 seconds |
Started | Jun 30 06:57:13 PM PDT 24 |
Finished | Jun 30 06:57:27 PM PDT 24 |
Peak memory | 217756 kb |
Host | smart-5f18e475-695f-4209-a1b9-89a88b231d1c |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130890953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.1130890953 |
Directory | /workspace/34.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/34.lc_ctrl_prog_failure.176846461 |
Short name | T427 |
Test name | |
Test status | |
Simulation time | 424570852 ps |
CPU time | 3.96 seconds |
Started | Jun 30 06:57:06 PM PDT 24 |
Finished | Jun 30 06:57:12 PM PDT 24 |
Peak memory | 218596 kb |
Host | smart-d0dee2ca-1789-4f8c-918d-3b5b06ec8d02 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=176846461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.176846461 |
Directory | /workspace/34.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/34.lc_ctrl_sec_mubi.3775775035 |
Short name | T346 |
Test name | |
Test status | |
Simulation time | 260017478 ps |
CPU time | 9.5 seconds |
Started | Jun 30 06:57:13 PM PDT 24 |
Finished | Jun 30 06:57:23 PM PDT 24 |
Peak memory | 226400 kb |
Host | smart-7cc8ee9a-66d2-42fd-9558-26ccbb06413f |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775775035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.3775775035 |
Directory | /workspace/34.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/34.lc_ctrl_sec_token_digest.1978258336 |
Short name | T390 |
Test name | |
Test status | |
Simulation time | 298446784 ps |
CPU time | 9.76 seconds |
Started | Jun 30 06:57:12 PM PDT 24 |
Finished | Jun 30 06:57:22 PM PDT 24 |
Peak memory | 218640 kb |
Host | smart-54facf2b-0f6b-4715-8579-4a79ec334fe3 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978258336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d igest.1978258336 |
Directory | /workspace/34.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/34.lc_ctrl_sec_token_mux.3149448487 |
Short name | T738 |
Test name | |
Test status | |
Simulation time | 366231459 ps |
CPU time | 7.96 seconds |
Started | Jun 30 06:57:14 PM PDT 24 |
Finished | Jun 30 06:57:24 PM PDT 24 |
Peak memory | 226400 kb |
Host | smart-c1c785ca-e570-4c45-becd-c5a1c67d2875 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149448487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux. 3149448487 |
Directory | /workspace/34.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/34.lc_ctrl_security_escalation.594504843 |
Short name | T624 |
Test name | |
Test status | |
Simulation time | 337637012 ps |
CPU time | 9.59 seconds |
Started | Jun 30 06:57:05 PM PDT 24 |
Finished | Jun 30 06:57:17 PM PDT 24 |
Peak memory | 226456 kb |
Host | smart-ea3cab2d-8393-4a38-98a3-2f4830468214 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=594504843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.594504843 |
Directory | /workspace/34.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/34.lc_ctrl_smoke.2534137101 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 15511879 ps |
CPU time | 1.01 seconds |
Started | Jun 30 06:57:06 PM PDT 24 |
Finished | Jun 30 06:57:09 PM PDT 24 |
Peak memory | 212580 kb |
Host | smart-2f7f0512-1935-42e2-9b7e-81ab2ec9bd90 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2534137101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.2534137101 |
Directory | /workspace/34.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/34.lc_ctrl_state_failure.2203702860 |
Short name | T324 |
Test name | |
Test status | |
Simulation time | 421209676 ps |
CPU time | 24.01 seconds |
Started | Jun 30 06:57:08 PM PDT 24 |
Finished | Jun 30 06:57:33 PM PDT 24 |
Peak memory | 251316 kb |
Host | smart-123028c1-771f-432f-ae5e-3bacd46cea62 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2203702860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.2203702860 |
Directory | /workspace/34.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/34.lc_ctrl_state_post_trans.741163271 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 62617650 ps |
CPU time | 8.43 seconds |
Started | Jun 30 06:57:06 PM PDT 24 |
Finished | Jun 30 06:57:16 PM PDT 24 |
Peak memory | 251332 kb |
Host | smart-bc545e46-f6cd-472d-bd13-4047e8cb823c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=741163271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.741163271 |
Directory | /workspace/34.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/34.lc_ctrl_stress_all.1426064285 |
Short name | T796 |
Test name | |
Test status | |
Simulation time | 1664409290 ps |
CPU time | 45.75 seconds |
Started | Jun 30 06:57:14 PM PDT 24 |
Finished | Jun 30 06:58:02 PM PDT 24 |
Peak memory | 267716 kb |
Host | smart-6949c33c-ed7b-4898-bf00-38558b71cf07 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426064285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all.1426064285 |
Directory | /workspace/34.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.3353065952 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 21097204928 ps |
CPU time | 628.64 seconds |
Started | Jun 30 06:57:14 PM PDT 24 |
Finished | Jun 30 07:07:45 PM PDT 24 |
Peak memory | 333396 kb |
Host | smart-8d0a8dde-0449-409f-99ce-ca0bcb024d84 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3353065952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.3353065952 |
Directory | /workspace/34.lc_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.610885691 |
Short name | T561 |
Test name | |
Test status | |
Simulation time | 55601716 ps |
CPU time | 1.03 seconds |
Started | Jun 30 06:57:08 PM PDT 24 |
Finished | Jun 30 06:57:10 PM PDT 24 |
Peak memory | 218048 kb |
Host | smart-bd1018d4-0282-4d21-8e01-031b38d35d9b |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610885691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ct rl_volatile_unlock_smoke.610885691 |
Directory | /workspace/34.lc_ctrl_volatile_unlock_smoke/latest |
Test location | /workspace/coverage/default/35.lc_ctrl_alert_test.1843400 |
Short name | T784 |
Test name | |
Test status | |
Simulation time | 22804853 ps |
CPU time | 0.85 seconds |
Started | Jun 30 06:57:15 PM PDT 24 |
Finished | Jun 30 06:57:17 PM PDT 24 |
Peak memory | 209136 kb |
Host | smart-20aaf04a-83c2-4e54-bcba-539f680d278a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.1843400 |
Directory | /workspace/35.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/35.lc_ctrl_errors.3588147134 |
Short name | T303 |
Test name | |
Test status | |
Simulation time | 834965588 ps |
CPU time | 19.39 seconds |
Started | Jun 30 06:57:15 PM PDT 24 |
Finished | Jun 30 06:57:36 PM PDT 24 |
Peak memory | 218584 kb |
Host | smart-12f7e664-c2ae-4582-9873-a7c504076c75 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3588147134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.3588147134 |
Directory | /workspace/35.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/35.lc_ctrl_jtag_access.4131780957 |
Short name | T448 |
Test name | |
Test status | |
Simulation time | 1413470589 ps |
CPU time | 11.22 seconds |
Started | Jun 30 06:57:14 PM PDT 24 |
Finished | Jun 30 06:57:27 PM PDT 24 |
Peak memory | 217812 kb |
Host | smart-d573b4ec-67b8-48c9-ab32-319d3262ee3f |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131780957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.4131780957 |
Directory | /workspace/35.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/35.lc_ctrl_prog_failure.3393100636 |
Short name | T723 |
Test name | |
Test status | |
Simulation time | 245917983 ps |
CPU time | 3.28 seconds |
Started | Jun 30 06:57:14 PM PDT 24 |
Finished | Jun 30 06:57:18 PM PDT 24 |
Peak memory | 222868 kb |
Host | smart-7c45bf80-38f7-4a11-985c-10700e468524 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3393100636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.3393100636 |
Directory | /workspace/35.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/35.lc_ctrl_sec_mubi.4077667447 |
Short name | T601 |
Test name | |
Test status | |
Simulation time | 301451692 ps |
CPU time | 12.08 seconds |
Started | Jun 30 06:57:14 PM PDT 24 |
Finished | Jun 30 06:57:27 PM PDT 24 |
Peak memory | 219288 kb |
Host | smart-e0ef7caa-4011-4bd1-ad0b-a0495f460bc8 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077667447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.4077667447 |
Directory | /workspace/35.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/35.lc_ctrl_sec_token_digest.339267271 |
Short name | T501 |
Test name | |
Test status | |
Simulation time | 1618778051 ps |
CPU time | 14.61 seconds |
Started | Jun 30 06:57:13 PM PDT 24 |
Finished | Jun 30 06:57:29 PM PDT 24 |
Peak memory | 218592 kb |
Host | smart-90cad409-6c69-4124-a1f1-edf65c3462f0 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339267271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_di gest.339267271 |
Directory | /workspace/35.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/35.lc_ctrl_sec_token_mux.1260789079 |
Short name | T704 |
Test name | |
Test status | |
Simulation time | 1410493884 ps |
CPU time | 8.58 seconds |
Started | Jun 30 06:57:14 PM PDT 24 |
Finished | Jun 30 06:57:24 PM PDT 24 |
Peak memory | 218604 kb |
Host | smart-15612e9e-8646-4227-a1bd-30b0e0c7af28 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260789079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux. 1260789079 |
Directory | /workspace/35.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/35.lc_ctrl_security_escalation.2382167014 |
Short name | T494 |
Test name | |
Test status | |
Simulation time | 1292493216 ps |
CPU time | 10.72 seconds |
Started | Jun 30 06:57:11 PM PDT 24 |
Finished | Jun 30 06:57:22 PM PDT 24 |
Peak memory | 226108 kb |
Host | smart-6446f25c-b391-4c10-8464-98fb2ca684d8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2382167014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.2382167014 |
Directory | /workspace/35.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/35.lc_ctrl_smoke.2608215096 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 48093846 ps |
CPU time | 1.15 seconds |
Started | Jun 30 06:57:14 PM PDT 24 |
Finished | Jun 30 06:57:16 PM PDT 24 |
Peak memory | 214040 kb |
Host | smart-96dbaa41-7e80-424f-a103-49686d981560 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2608215096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.2608215096 |
Directory | /workspace/35.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/35.lc_ctrl_state_failure.3381605808 |
Short name | T360 |
Test name | |
Test status | |
Simulation time | 216328191 ps |
CPU time | 31.74 seconds |
Started | Jun 30 06:57:16 PM PDT 24 |
Finished | Jun 30 06:57:49 PM PDT 24 |
Peak memory | 251240 kb |
Host | smart-09be6fef-de5b-4876-8b5c-0df01fc0b626 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3381605808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.3381605808 |
Directory | /workspace/35.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/35.lc_ctrl_state_post_trans.441083049 |
Short name | T481 |
Test name | |
Test status | |
Simulation time | 227026583 ps |
CPU time | 7.84 seconds |
Started | Jun 30 06:57:13 PM PDT 24 |
Finished | Jun 30 06:57:22 PM PDT 24 |
Peak memory | 251344 kb |
Host | smart-ffdaa1ba-ce49-4cdb-ac2d-d97ea73f5989 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=441083049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.441083049 |
Directory | /workspace/35.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/35.lc_ctrl_stress_all.2662222099 |
Short name | T767 |
Test name | |
Test status | |
Simulation time | 63231949971 ps |
CPU time | 156.22 seconds |
Started | Jun 30 06:57:14 PM PDT 24 |
Finished | Jun 30 06:59:52 PM PDT 24 |
Peak memory | 277472 kb |
Host | smart-31b067f7-423f-4a8b-97d5-f19102bfa8fc |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662222099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all.2662222099 |
Directory | /workspace/35.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.2737757272 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 50981320 ps |
CPU time | 0.86 seconds |
Started | Jun 30 06:57:13 PM PDT 24 |
Finished | Jun 30 06:57:14 PM PDT 24 |
Peak memory | 209304 kb |
Host | smart-fb01a894-dfdb-4265-a546-75257a47abaa |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737757272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c trl_volatile_unlock_smoke.2737757272 |
Directory | /workspace/35.lc_ctrl_volatile_unlock_smoke/latest |
Test location | /workspace/coverage/default/36.lc_ctrl_alert_test.4146720664 |
Short name | T540 |
Test name | |
Test status | |
Simulation time | 17297778 ps |
CPU time | 0.92 seconds |
Started | Jun 30 06:57:21 PM PDT 24 |
Finished | Jun 30 06:57:24 PM PDT 24 |
Peak memory | 209376 kb |
Host | smart-e82ae737-50ca-46d7-8b80-d5609c09f939 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146720664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.4146720664 |
Directory | /workspace/36.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/36.lc_ctrl_errors.544376554 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 331950596 ps |
CPU time | 9.63 seconds |
Started | Jun 30 06:57:13 PM PDT 24 |
Finished | Jun 30 06:57:24 PM PDT 24 |
Peak memory | 218588 kb |
Host | smart-41575bea-81fc-4346-b56a-a3e8603b993e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=544376554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.544376554 |
Directory | /workspace/36.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/36.lc_ctrl_jtag_access.1164637653 |
Short name | T598 |
Test name | |
Test status | |
Simulation time | 627553968 ps |
CPU time | 4.23 seconds |
Started | Jun 30 06:57:16 PM PDT 24 |
Finished | Jun 30 06:57:21 PM PDT 24 |
Peak memory | 218044 kb |
Host | smart-bfc8a42f-67fe-4eb3-bf8c-bd81707df74e |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164637653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.1164637653 |
Directory | /workspace/36.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/36.lc_ctrl_prog_failure.2907901177 |
Short name | T681 |
Test name | |
Test status | |
Simulation time | 93964285 ps |
CPU time | 1.84 seconds |
Started | Jun 30 06:57:13 PM PDT 24 |
Finished | Jun 30 06:57:16 PM PDT 24 |
Peak memory | 218640 kb |
Host | smart-a6ca774c-c141-4910-a541-9293ad552386 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2907901177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.2907901177 |
Directory | /workspace/36.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/36.lc_ctrl_sec_mubi.3076428636 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 1557144644 ps |
CPU time | 14.15 seconds |
Started | Jun 30 06:57:13 PM PDT 24 |
Finished | Jun 30 06:57:29 PM PDT 24 |
Peak memory | 226432 kb |
Host | smart-7bf4de77-3fbe-4bfd-bf41-15789812294a |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076428636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.3076428636 |
Directory | /workspace/36.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/36.lc_ctrl_sec_token_digest.3329650884 |
Short name | T370 |
Test name | |
Test status | |
Simulation time | 830330261 ps |
CPU time | 19.49 seconds |
Started | Jun 30 06:57:23 PM PDT 24 |
Finished | Jun 30 06:57:45 PM PDT 24 |
Peak memory | 218572 kb |
Host | smart-8b8cd80c-0a7a-469b-9962-53f0c4e04e85 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329650884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d igest.3329650884 |
Directory | /workspace/36.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/36.lc_ctrl_sec_token_mux.2153347643 |
Short name | T659 |
Test name | |
Test status | |
Simulation time | 1984616325 ps |
CPU time | 8.36 seconds |
Started | Jun 30 06:57:20 PM PDT 24 |
Finished | Jun 30 06:57:29 PM PDT 24 |
Peak memory | 218596 kb |
Host | smart-0bfd6d73-d080-4580-9fbb-3f2944666ad0 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153347643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux. 2153347643 |
Directory | /workspace/36.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/36.lc_ctrl_security_escalation.3722373237 |
Short name | T753 |
Test name | |
Test status | |
Simulation time | 1663312738 ps |
CPU time | 8.96 seconds |
Started | Jun 30 06:57:11 PM PDT 24 |
Finished | Jun 30 06:57:21 PM PDT 24 |
Peak memory | 225364 kb |
Host | smart-fc593915-33d3-45d3-803f-956373b88272 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3722373237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.3722373237 |
Directory | /workspace/36.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/36.lc_ctrl_smoke.527502277 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 240957182 ps |
CPU time | 7.2 seconds |
Started | Jun 30 06:57:14 PM PDT 24 |
Finished | Jun 30 06:57:23 PM PDT 24 |
Peak memory | 218064 kb |
Host | smart-57daa803-6cb0-46fd-b4d7-a528bdedb9ca |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=527502277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.527502277 |
Directory | /workspace/36.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/36.lc_ctrl_state_failure.1598484530 |
Short name | T755 |
Test name | |
Test status | |
Simulation time | 217279323 ps |
CPU time | 24.99 seconds |
Started | Jun 30 06:57:13 PM PDT 24 |
Finished | Jun 30 06:57:40 PM PDT 24 |
Peak memory | 251520 kb |
Host | smart-dfc5d60b-e873-4ac9-ac4b-07244082b04e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1598484530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.1598484530 |
Directory | /workspace/36.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/36.lc_ctrl_state_post_trans.1427987830 |
Short name | T340 |
Test name | |
Test status | |
Simulation time | 81104111 ps |
CPU time | 8.12 seconds |
Started | Jun 30 06:57:12 PM PDT 24 |
Finished | Jun 30 06:57:21 PM PDT 24 |
Peak memory | 251264 kb |
Host | smart-2045f6a6-5b09-4dee-9422-24ef09bf7152 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1427987830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.1427987830 |
Directory | /workspace/36.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/36.lc_ctrl_stress_all.2979597343 |
Short name | T864 |
Test name | |
Test status | |
Simulation time | 31568724842 ps |
CPU time | 214.2 seconds |
Started | Jun 30 06:57:20 PM PDT 24 |
Finished | Jun 30 07:00:55 PM PDT 24 |
Peak memory | 223860 kb |
Host | smart-aad5da30-a467-4949-a471-b44a45174cc3 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979597343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all.2979597343 |
Directory | /workspace/36.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.3380829461 |
Short name | T725 |
Test name | |
Test status | |
Simulation time | 13252326 ps |
CPU time | 0.82 seconds |
Started | Jun 30 06:57:13 PM PDT 24 |
Finished | Jun 30 06:57:15 PM PDT 24 |
Peak memory | 209220 kb |
Host | smart-098ba29c-2a9c-4968-956f-e013b3b540a2 |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380829461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c trl_volatile_unlock_smoke.3380829461 |
Directory | /workspace/36.lc_ctrl_volatile_unlock_smoke/latest |
Test location | /workspace/coverage/default/37.lc_ctrl_alert_test.2240840252 |
Short name | T790 |
Test name | |
Test status | |
Simulation time | 57627234 ps |
CPU time | 0.99 seconds |
Started | Jun 30 06:57:21 PM PDT 24 |
Finished | Jun 30 06:57:24 PM PDT 24 |
Peak memory | 209300 kb |
Host | smart-cc73bb8f-f883-44d2-9b92-f97b9c2b6288 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240840252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.2240840252 |
Directory | /workspace/37.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/37.lc_ctrl_errors.312986868 |
Short name | T680 |
Test name | |
Test status | |
Simulation time | 1366117837 ps |
CPU time | 14.83 seconds |
Started | Jun 30 06:57:23 PM PDT 24 |
Finished | Jun 30 06:57:40 PM PDT 24 |
Peak memory | 226416 kb |
Host | smart-c3e5631e-b832-41b8-8c5e-ae31ebcc7911 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=312986868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.312986868 |
Directory | /workspace/37.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/37.lc_ctrl_jtag_access.324687729 |
Short name | T800 |
Test name | |
Test status | |
Simulation time | 2106418465 ps |
CPU time | 26.03 seconds |
Started | Jun 30 06:57:24 PM PDT 24 |
Finished | Jun 30 06:57:52 PM PDT 24 |
Peak memory | 217736 kb |
Host | smart-69a957ed-a587-45f9-bf42-234cd0d16862 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324687729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.324687729 |
Directory | /workspace/37.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/37.lc_ctrl_prog_failure.2857996737 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 25629679 ps |
CPU time | 1.89 seconds |
Started | Jun 30 06:57:20 PM PDT 24 |
Finished | Jun 30 06:57:23 PM PDT 24 |
Peak memory | 218636 kb |
Host | smart-35c0c45e-8fea-4a04-9fbf-75eea53913d6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2857996737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.2857996737 |
Directory | /workspace/37.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/37.lc_ctrl_sec_token_digest.1822951335 |
Short name | T341 |
Test name | |
Test status | |
Simulation time | 333851928 ps |
CPU time | 14.53 seconds |
Started | Jun 30 06:57:21 PM PDT 24 |
Finished | Jun 30 06:57:37 PM PDT 24 |
Peak memory | 218612 kb |
Host | smart-0242d3ca-69a6-47df-b8f2-1ec108b0bef4 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822951335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d igest.1822951335 |
Directory | /workspace/37.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/37.lc_ctrl_sec_token_mux.493507599 |
Short name | T535 |
Test name | |
Test status | |
Simulation time | 490909463 ps |
CPU time | 8.35 seconds |
Started | Jun 30 06:57:21 PM PDT 24 |
Finished | Jun 30 06:57:32 PM PDT 24 |
Peak memory | 226384 kb |
Host | smart-c8a7c3f3-5094-400f-8a9e-ce1117bcda8a |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493507599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.493507599 |
Directory | /workspace/37.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/37.lc_ctrl_security_escalation.1665081978 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 384873104 ps |
CPU time | 6.63 seconds |
Started | Jun 30 06:57:21 PM PDT 24 |
Finished | Jun 30 06:57:29 PM PDT 24 |
Peak memory | 218652 kb |
Host | smart-14e58e48-ece4-489b-9aed-43b12ebfdb4b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1665081978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.1665081978 |
Directory | /workspace/37.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/37.lc_ctrl_smoke.3291508216 |
Short name | T428 |
Test name | |
Test status | |
Simulation time | 180062145 ps |
CPU time | 5.43 seconds |
Started | Jun 30 06:57:22 PM PDT 24 |
Finished | Jun 30 06:57:30 PM PDT 24 |
Peak memory | 218056 kb |
Host | smart-9fb4cf9c-655c-4bf0-9383-b9a303eb11f7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3291508216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.3291508216 |
Directory | /workspace/37.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/37.lc_ctrl_state_failure.3939767286 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 582546132 ps |
CPU time | 31.47 seconds |
Started | Jun 30 06:57:22 PM PDT 24 |
Finished | Jun 30 06:57:56 PM PDT 24 |
Peak memory | 251360 kb |
Host | smart-d808279a-1a40-4e61-a5aa-ef257a2d5532 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3939767286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.3939767286 |
Directory | /workspace/37.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/37.lc_ctrl_state_post_trans.230712424 |
Short name | T709 |
Test name | |
Test status | |
Simulation time | 140573615 ps |
CPU time | 8.72 seconds |
Started | Jun 30 06:57:21 PM PDT 24 |
Finished | Jun 30 06:57:31 PM PDT 24 |
Peak memory | 251328 kb |
Host | smart-63ac2158-4aaf-4ffa-a992-4dae35293048 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=230712424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.230712424 |
Directory | /workspace/37.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/37.lc_ctrl_stress_all.181564849 |
Short name | T545 |
Test name | |
Test status | |
Simulation time | 18100739653 ps |
CPU time | 101.42 seconds |
Started | Jun 30 06:57:21 PM PDT 24 |
Finished | Jun 30 06:59:04 PM PDT 24 |
Peak memory | 267788 kb |
Host | smart-0a221473-bab4-436f-b612-1134cf6f6100 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181564849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all.181564849 |
Directory | /workspace/37.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.1304953259 |
Short name | T367 |
Test name | |
Test status | |
Simulation time | 12271604 ps |
CPU time | 0.8 seconds |
Started | Jun 30 06:57:23 PM PDT 24 |
Finished | Jun 30 06:57:26 PM PDT 24 |
Peak memory | 209372 kb |
Host | smart-04f8a424-0b37-485d-83ed-e31f0218a09e |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304953259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c trl_volatile_unlock_smoke.1304953259 |
Directory | /workspace/37.lc_ctrl_volatile_unlock_smoke/latest |
Test location | /workspace/coverage/default/38.lc_ctrl_alert_test.3847878494 |
Short name | T302 |
Test name | |
Test status | |
Simulation time | 15600170 ps |
CPU time | 1.05 seconds |
Started | Jun 30 06:57:28 PM PDT 24 |
Finished | Jun 30 06:57:30 PM PDT 24 |
Peak memory | 209616 kb |
Host | smart-9fb426ac-418e-4934-9095-68f37074050a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847878494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.3847878494 |
Directory | /workspace/38.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/38.lc_ctrl_errors.772286655 |
Short name | T304 |
Test name | |
Test status | |
Simulation time | 524593289 ps |
CPU time | 13.17 seconds |
Started | Jun 30 06:57:22 PM PDT 24 |
Finished | Jun 30 06:57:38 PM PDT 24 |
Peak memory | 218640 kb |
Host | smart-e35d5185-e35d-4d02-adbc-68820799301e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=772286655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.772286655 |
Directory | /workspace/38.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/38.lc_ctrl_jtag_access.825016251 |
Short name | T783 |
Test name | |
Test status | |
Simulation time | 295331127 ps |
CPU time | 5.73 seconds |
Started | Jun 30 06:57:23 PM PDT 24 |
Finished | Jun 30 06:57:31 PM PDT 24 |
Peak memory | 217628 kb |
Host | smart-4d261f52-7714-48eb-a3c8-1f358f749793 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825016251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.825016251 |
Directory | /workspace/38.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/38.lc_ctrl_prog_failure.3749971848 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 50332989 ps |
CPU time | 2.22 seconds |
Started | Jun 30 06:57:22 PM PDT 24 |
Finished | Jun 30 06:57:26 PM PDT 24 |
Peak memory | 222484 kb |
Host | smart-5eccaa30-4a79-447b-a6a3-9b19b9352446 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3749971848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.3749971848 |
Directory | /workspace/38.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/38.lc_ctrl_sec_mubi.726237688 |
Short name | T860 |
Test name | |
Test status | |
Simulation time | 2663684946 ps |
CPU time | 15.17 seconds |
Started | Jun 30 06:57:22 PM PDT 24 |
Finished | Jun 30 06:57:40 PM PDT 24 |
Peak memory | 220572 kb |
Host | smart-51076b77-3749-463f-a196-afa0012f93ad |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726237688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.726237688 |
Directory | /workspace/38.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/38.lc_ctrl_sec_token_digest.1588730965 |
Short name | T665 |
Test name | |
Test status | |
Simulation time | 824656208 ps |
CPU time | 12.95 seconds |
Started | Jun 30 06:57:23 PM PDT 24 |
Finished | Jun 30 06:57:38 PM PDT 24 |
Peak memory | 218512 kb |
Host | smart-3510a807-69aa-436c-a91f-8116024116a7 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588730965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d igest.1588730965 |
Directory | /workspace/38.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/38.lc_ctrl_sec_token_mux.3486199078 |
Short name | T541 |
Test name | |
Test status | |
Simulation time | 574811937 ps |
CPU time | 10.86 seconds |
Started | Jun 30 06:57:23 PM PDT 24 |
Finished | Jun 30 06:57:37 PM PDT 24 |
Peak memory | 218584 kb |
Host | smart-aa0d4459-6f36-4e55-afff-6b1feb22d4ee |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486199078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux. 3486199078 |
Directory | /workspace/38.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/38.lc_ctrl_security_escalation.2786843600 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 678510226 ps |
CPU time | 8.58 seconds |
Started | Jun 30 06:57:24 PM PDT 24 |
Finished | Jun 30 06:57:35 PM PDT 24 |
Peak memory | 226388 kb |
Host | smart-1b55f13f-aadd-4599-b75a-f7e51deb6789 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2786843600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.2786843600 |
Directory | /workspace/38.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/38.lc_ctrl_smoke.3151407083 |
Short name | T495 |
Test name | |
Test status | |
Simulation time | 91836754 ps |
CPU time | 3.21 seconds |
Started | Jun 30 06:57:23 PM PDT 24 |
Finished | Jun 30 06:57:29 PM PDT 24 |
Peak memory | 218072 kb |
Host | smart-1a88275a-a609-490b-86d8-5e1516f60760 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3151407083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.3151407083 |
Directory | /workspace/38.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/38.lc_ctrl_state_failure.3443042754 |
Short name | T313 |
Test name | |
Test status | |
Simulation time | 278339850 ps |
CPU time | 19.53 seconds |
Started | Jun 30 06:57:23 PM PDT 24 |
Finished | Jun 30 06:57:45 PM PDT 24 |
Peak memory | 251416 kb |
Host | smart-d1ef81ba-17a8-4ba9-ba0d-493430cddf06 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3443042754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.3443042754 |
Directory | /workspace/38.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/38.lc_ctrl_state_post_trans.685345463 |
Short name | T854 |
Test name | |
Test status | |
Simulation time | 164581691 ps |
CPU time | 7.22 seconds |
Started | Jun 30 06:57:24 PM PDT 24 |
Finished | Jun 30 06:57:33 PM PDT 24 |
Peak memory | 246664 kb |
Host | smart-65ecfcfd-a0e5-4c7e-a6fe-997fcb2327f7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=685345463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.685345463 |
Directory | /workspace/38.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/38.lc_ctrl_stress_all.3602744833 |
Short name | T410 |
Test name | |
Test status | |
Simulation time | 7107242406 ps |
CPU time | 161.47 seconds |
Started | Jun 30 06:57:23 PM PDT 24 |
Finished | Jun 30 07:00:07 PM PDT 24 |
Peak memory | 276848 kb |
Host | smart-d124ac4f-ae08-4048-b64e-85c70d138265 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602744833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all.3602744833 |
Directory | /workspace/38.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.3297756194 |
Short name | T355 |
Test name | |
Test status | |
Simulation time | 117503202 ps |
CPU time | 1.07 seconds |
Started | Jun 30 06:57:20 PM PDT 24 |
Finished | Jun 30 06:57:22 PM PDT 24 |
Peak memory | 218056 kb |
Host | smart-26ee1825-adf3-42d7-a098-781d25406fbb |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297756194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c trl_volatile_unlock_smoke.3297756194 |
Directory | /workspace/38.lc_ctrl_volatile_unlock_smoke/latest |
Test location | /workspace/coverage/default/39.lc_ctrl_alert_test.600822938 |
Short name | T666 |
Test name | |
Test status | |
Simulation time | 176705488 ps |
CPU time | 1.47 seconds |
Started | Jun 30 06:57:26 PM PDT 24 |
Finished | Jun 30 06:57:29 PM PDT 24 |
Peak memory | 209432 kb |
Host | smart-df9f26e0-d859-4dc1-b35f-ce0b62a2c0de |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600822938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.600822938 |
Directory | /workspace/39.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/39.lc_ctrl_errors.3475774406 |
Short name | T726 |
Test name | |
Test status | |
Simulation time | 241551086 ps |
CPU time | 12.78 seconds |
Started | Jun 30 06:57:23 PM PDT 24 |
Finished | Jun 30 06:57:39 PM PDT 24 |
Peak memory | 226460 kb |
Host | smart-814648f4-ea28-4e76-9d8b-0211dcd7dc7e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3475774406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.3475774406 |
Directory | /workspace/39.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/39.lc_ctrl_jtag_access.776397719 |
Short name | T480 |
Test name | |
Test status | |
Simulation time | 283821169 ps |
CPU time | 3.82 seconds |
Started | Jun 30 06:57:26 PM PDT 24 |
Finished | Jun 30 06:57:32 PM PDT 24 |
Peak memory | 217408 kb |
Host | smart-2caf7353-5734-4fae-bc52-61ebe10916f6 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776397719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.776397719 |
Directory | /workspace/39.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/39.lc_ctrl_prog_failure.2467343835 |
Short name | T440 |
Test name | |
Test status | |
Simulation time | 61473616 ps |
CPU time | 3.01 seconds |
Started | Jun 30 06:57:24 PM PDT 24 |
Finished | Jun 30 06:57:29 PM PDT 24 |
Peak memory | 218660 kb |
Host | smart-c280f5eb-6d98-4d57-bb06-16d5ba433a08 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2467343835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.2467343835 |
Directory | /workspace/39.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/39.lc_ctrl_sec_mubi.3173704948 |
Short name | T573 |
Test name | |
Test status | |
Simulation time | 1974496821 ps |
CPU time | 18.92 seconds |
Started | Jun 30 06:57:26 PM PDT 24 |
Finished | Jun 30 06:57:46 PM PDT 24 |
Peak memory | 226688 kb |
Host | smart-fb309b90-3c4e-4c30-be76-d9e5399203cc |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173704948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.3173704948 |
Directory | /workspace/39.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/39.lc_ctrl_sec_token_digest.3539045528 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 3496414510 ps |
CPU time | 20.76 seconds |
Started | Jun 30 06:57:29 PM PDT 24 |
Finished | Jun 30 06:57:51 PM PDT 24 |
Peak memory | 218660 kb |
Host | smart-199c8282-4eab-454e-aeef-57ffcb7a3060 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539045528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d igest.3539045528 |
Directory | /workspace/39.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/39.lc_ctrl_sec_token_mux.544994283 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 946179408 ps |
CPU time | 10.68 seconds |
Started | Jun 30 06:57:27 PM PDT 24 |
Finished | Jun 30 06:57:39 PM PDT 24 |
Peak memory | 218580 kb |
Host | smart-914abefb-c57e-4047-84e1-a73bd887b75e |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544994283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.544994283 |
Directory | /workspace/39.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/39.lc_ctrl_security_escalation.3464382520 |
Short name | T771 |
Test name | |
Test status | |
Simulation time | 384937664 ps |
CPU time | 8.82 seconds |
Started | Jun 30 06:57:26 PM PDT 24 |
Finished | Jun 30 06:57:37 PM PDT 24 |
Peak memory | 218776 kb |
Host | smart-5ef6d02a-1b81-456f-95c9-31413962c5a0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3464382520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.3464382520 |
Directory | /workspace/39.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/39.lc_ctrl_smoke.1125542613 |
Short name | T674 |
Test name | |
Test status | |
Simulation time | 156115512 ps |
CPU time | 1.85 seconds |
Started | Jun 30 06:57:22 PM PDT 24 |
Finished | Jun 30 06:57:26 PM PDT 24 |
Peak memory | 214532 kb |
Host | smart-8f8e1bbc-fd95-4168-a6e2-329786414c83 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1125542613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.1125542613 |
Directory | /workspace/39.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/39.lc_ctrl_state_failure.865000706 |
Short name | T713 |
Test name | |
Test status | |
Simulation time | 549975643 ps |
CPU time | 17.2 seconds |
Started | Jun 30 06:57:29 PM PDT 24 |
Finished | Jun 30 06:57:47 PM PDT 24 |
Peak memory | 251320 kb |
Host | smart-553c931e-4109-4d5f-85ff-e8a59b754970 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=865000706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.865000706 |
Directory | /workspace/39.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/39.lc_ctrl_state_post_trans.3943231059 |
Short name | T531 |
Test name | |
Test status | |
Simulation time | 342476302 ps |
CPU time | 7.48 seconds |
Started | Jun 30 06:57:24 PM PDT 24 |
Finished | Jun 30 06:57:34 PM PDT 24 |
Peak memory | 247200 kb |
Host | smart-eac28708-930b-4ce3-993c-64e6c614aa1f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3943231059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.3943231059 |
Directory | /workspace/39.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/39.lc_ctrl_stress_all.3730023711 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 4066471920 ps |
CPU time | 51.27 seconds |
Started | Jun 30 06:57:26 PM PDT 24 |
Finished | Jun 30 06:58:19 PM PDT 24 |
Peak memory | 251284 kb |
Host | smart-31b16926-44b5-4b58-8aef-a3e4a7adff67 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730023711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all.3730023711 |
Directory | /workspace/39.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.2796533545 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 115061229488 ps |
CPU time | 8864.63 seconds |
Started | Jun 30 06:57:23 PM PDT 24 |
Finished | Jun 30 09:25:11 PM PDT 24 |
Peak memory | 824944 kb |
Host | smart-5e19a6bb-4777-4581-ab73-dfbf0e8f9635 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2796533545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.2796533545 |
Directory | /workspace/39.lc_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.386830614 |
Short name | T279 |
Test name | |
Test status | |
Simulation time | 12326423 ps |
CPU time | 0.76 seconds |
Started | Jun 30 06:57:23 PM PDT 24 |
Finished | Jun 30 06:57:27 PM PDT 24 |
Peak memory | 208792 kb |
Host | smart-cbbc44ec-acf5-4095-ac4d-9ec70a57a20f |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386830614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ct rl_volatile_unlock_smoke.386830614 |
Directory | /workspace/39.lc_ctrl_volatile_unlock_smoke/latest |
Test location | /workspace/coverage/default/4.lc_ctrl_alert_test.2798749884 |
Short name | T354 |
Test name | |
Test status | |
Simulation time | 39720470 ps |
CPU time | 1.18 seconds |
Started | Jun 30 06:55:13 PM PDT 24 |
Finished | Jun 30 06:55:15 PM PDT 24 |
Peak memory | 209356 kb |
Host | smart-b28103c5-d312-440e-9e5f-bce27576a2a8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798749884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.2798749884 |
Directory | /workspace/4.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/4.lc_ctrl_claim_transition_if.1260121601 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 11177533 ps |
CPU time | 0.79 seconds |
Started | Jun 30 06:55:04 PM PDT 24 |
Finished | Jun 30 06:55:06 PM PDT 24 |
Peak memory | 209436 kb |
Host | smart-cba9c7c2-aea4-4108-acd4-dc4056c7e05b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1260121601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.1260121601 |
Directory | /workspace/4.lc_ctrl_claim_transition_if/latest |
Test location | /workspace/coverage/default/4.lc_ctrl_errors.1475945211 |
Short name | T667 |
Test name | |
Test status | |
Simulation time | 303118613 ps |
CPU time | 12.33 seconds |
Started | Jun 30 06:55:03 PM PDT 24 |
Finished | Jun 30 06:55:16 PM PDT 24 |
Peak memory | 226328 kb |
Host | smart-fc879261-ce99-49c8-a70f-11e7f4da8368 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1475945211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.1475945211 |
Directory | /workspace/4.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/4.lc_ctrl_jtag_access.1276821355 |
Short name | T772 |
Test name | |
Test status | |
Simulation time | 855225971 ps |
CPU time | 2.97 seconds |
Started | Jun 30 06:55:07 PM PDT 24 |
Finished | Jun 30 06:55:11 PM PDT 24 |
Peak memory | 217552 kb |
Host | smart-1f545318-d906-4db3-818a-5cdc224bb2ca |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276821355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.1276821355 |
Directory | /workspace/4.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/4.lc_ctrl_jtag_errors.2324776038 |
Short name | T661 |
Test name | |
Test status | |
Simulation time | 9730885770 ps |
CPU time | 40.37 seconds |
Started | Jun 30 06:55:09 PM PDT 24 |
Finished | Jun 30 06:55:50 PM PDT 24 |
Peak memory | 219276 kb |
Host | smart-71991809-e7ca-4dcb-96ef-bce94b000bcd |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324776038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er rors.2324776038 |
Directory | /workspace/4.lc_ctrl_jtag_errors/latest |
Test location | /workspace/coverage/default/4.lc_ctrl_jtag_priority.3160189898 |
Short name | T855 |
Test name | |
Test status | |
Simulation time | 85408225 ps |
CPU time | 1.69 seconds |
Started | Jun 30 06:55:08 PM PDT 24 |
Finished | Jun 30 06:55:10 PM PDT 24 |
Peak memory | 217932 kb |
Host | smart-de5d95ed-759b-4917-9435-ddfca544a7b6 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160189898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.3 160189898 |
Directory | /workspace/4.lc_ctrl_jtag_priority/latest |
Test location | /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.3664307042 |
Short name | T730 |
Test name | |
Test status | |
Simulation time | 272108019 ps |
CPU time | 5.18 seconds |
Started | Jun 30 06:55:07 PM PDT 24 |
Finished | Jun 30 06:55:13 PM PDT 24 |
Peak memory | 218580 kb |
Host | smart-5506c47b-95ca-41e2-96a9-2699d6b7efce |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664307042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag _prog_failure.3664307042 |
Directory | /workspace/4.lc_ctrl_jtag_prog_failure/latest |
Test location | /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.2397283675 |
Short name | T388 |
Test name | |
Test status | |
Simulation time | 1393360966 ps |
CPU time | 19.26 seconds |
Started | Jun 30 06:55:10 PM PDT 24 |
Finished | Jun 30 06:55:30 PM PDT 24 |
Peak memory | 217964 kb |
Host | smart-f47169b0-17bc-4558-b24f-34d35890a77d |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397283675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_ jtag_regwen_during_op.2397283675 |
Directory | /workspace/4.lc_ctrl_jtag_regwen_during_op/latest |
Test location | /workspace/coverage/default/4.lc_ctrl_jtag_smoke.2550154430 |
Short name | T873 |
Test name | |
Test status | |
Simulation time | 160391951 ps |
CPU time | 2.81 seconds |
Started | Jun 30 06:55:05 PM PDT 24 |
Finished | Jun 30 06:55:09 PM PDT 24 |
Peak memory | 217992 kb |
Host | smart-760167e3-7a19-48f0-a60f-e64cf3edc5fb |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550154430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke. 2550154430 |
Directory | /workspace/4.lc_ctrl_jtag_smoke/latest |
Test location | /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.3740040838 |
Short name | T468 |
Test name | |
Test status | |
Simulation time | 7100109224 ps |
CPU time | 54.57 seconds |
Started | Jun 30 06:55:08 PM PDT 24 |
Finished | Jun 30 06:56:03 PM PDT 24 |
Peak memory | 267704 kb |
Host | smart-4972e699-097b-46cb-86c4-d34e95233d04 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740040838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta g_state_failure.3740040838 |
Directory | /workspace/4.lc_ctrl_jtag_state_failure/latest |
Test location | /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.2205660424 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 767747857 ps |
CPU time | 16.77 seconds |
Started | Jun 30 06:55:14 PM PDT 24 |
Finished | Jun 30 06:55:31 PM PDT 24 |
Peak memory | 251248 kb |
Host | smart-ad1e25b2-019c-48b9-8cfd-8ad6808e85e4 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205660424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_ jtag_state_post_trans.2205660424 |
Directory | /workspace/4.lc_ctrl_jtag_state_post_trans/latest |
Test location | /workspace/coverage/default/4.lc_ctrl_prog_failure.284976692 |
Short name | T834 |
Test name | |
Test status | |
Simulation time | 42737695 ps |
CPU time | 2.51 seconds |
Started | Jun 30 06:55:04 PM PDT 24 |
Finished | Jun 30 06:55:08 PM PDT 24 |
Peak memory | 218632 kb |
Host | smart-f4b05b8b-573b-4723-8506-57ca42928b62 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=284976692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.284976692 |
Directory | /workspace/4.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/4.lc_ctrl_regwen_during_op.1165037089 |
Short name | T593 |
Test name | |
Test status | |
Simulation time | 341813091 ps |
CPU time | 18.77 seconds |
Started | Jun 30 06:55:02 PM PDT 24 |
Finished | Jun 30 06:55:22 PM PDT 24 |
Peak memory | 217980 kb |
Host | smart-830431fc-40cb-4b2d-9ef5-f5c97aa8113d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1165037089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.1165037089 |
Directory | /workspace/4.lc_ctrl_regwen_during_op/latest |
Test location | /workspace/coverage/default/4.lc_ctrl_sec_cm.2844810055 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 911429030 ps |
CPU time | 36.6 seconds |
Started | Jun 30 06:55:12 PM PDT 24 |
Finished | Jun 30 06:55:48 PM PDT 24 |
Peak memory | 282096 kb |
Host | smart-5439b1dc-73e5-4ffa-b7cf-d9bb60062f6b |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844810055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.2844810055 |
Directory | /workspace/4.lc_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/4.lc_ctrl_sec_mubi.1147902266 |
Short name | T747 |
Test name | |
Test status | |
Simulation time | 1546871043 ps |
CPU time | 11.93 seconds |
Started | Jun 30 06:55:10 PM PDT 24 |
Finished | Jun 30 06:55:22 PM PDT 24 |
Peak memory | 226444 kb |
Host | smart-17667157-1578-44a0-819b-694a5dfef066 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147902266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.1147902266 |
Directory | /workspace/4.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/4.lc_ctrl_sec_token_digest.1593516436 |
Short name | T594 |
Test name | |
Test status | |
Simulation time | 211724993 ps |
CPU time | 8.74 seconds |
Started | Jun 30 06:55:09 PM PDT 24 |
Finished | Jun 30 06:55:18 PM PDT 24 |
Peak memory | 218604 kb |
Host | smart-6f79da4c-f9f4-416e-9332-a669663eaaac |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593516436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di gest.1593516436 |
Directory | /workspace/4.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/4.lc_ctrl_sec_token_mux.462585942 |
Short name | T822 |
Test name | |
Test status | |
Simulation time | 323023622 ps |
CPU time | 12.39 seconds |
Started | Jun 30 06:55:09 PM PDT 24 |
Finished | Jun 30 06:55:22 PM PDT 24 |
Peak memory | 226364 kb |
Host | smart-a46ebd7d-a0dd-40fb-ae4b-2b5285818583 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462585942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.462585942 |
Directory | /workspace/4.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/4.lc_ctrl_security_escalation.532640414 |
Short name | T787 |
Test name | |
Test status | |
Simulation time | 791640405 ps |
CPU time | 8.41 seconds |
Started | Jun 30 06:55:03 PM PDT 24 |
Finished | Jun 30 06:55:13 PM PDT 24 |
Peak memory | 218720 kb |
Host | smart-6bf6456c-9e34-475b-86ad-2aa7f9bc0fa4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=532640414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.532640414 |
Directory | /workspace/4.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/4.lc_ctrl_smoke.3438269961 |
Short name | T397 |
Test name | |
Test status | |
Simulation time | 32584272 ps |
CPU time | 2.51 seconds |
Started | Jun 30 06:55:05 PM PDT 24 |
Finished | Jun 30 06:55:08 PM PDT 24 |
Peak memory | 214744 kb |
Host | smart-d1722849-0e27-49c2-ab04-b3b7a1996360 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3438269961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.3438269961 |
Directory | /workspace/4.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/4.lc_ctrl_state_failure.1577062074 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 913495067 ps |
CPU time | 26.76 seconds |
Started | Jun 30 06:55:03 PM PDT 24 |
Finished | Jun 30 06:55:31 PM PDT 24 |
Peak memory | 251284 kb |
Host | smart-3ec60804-6853-43fb-97d6-10430093f834 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1577062074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.1577062074 |
Directory | /workspace/4.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/4.lc_ctrl_state_post_trans.3283049373 |
Short name | T571 |
Test name | |
Test status | |
Simulation time | 152726513 ps |
CPU time | 7.64 seconds |
Started | Jun 30 06:55:04 PM PDT 24 |
Finished | Jun 30 06:55:13 PM PDT 24 |
Peak memory | 250904 kb |
Host | smart-be564454-0c9a-4c5e-88fa-669b00ffc9da |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3283049373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.3283049373 |
Directory | /workspace/4.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/4.lc_ctrl_stress_all.3685189567 |
Short name | T721 |
Test name | |
Test status | |
Simulation time | 11179966351 ps |
CPU time | 48.98 seconds |
Started | Jun 30 06:55:12 PM PDT 24 |
Finished | Jun 30 06:56:01 PM PDT 24 |
Peak memory | 221620 kb |
Host | smart-c5f0ada8-9786-4d4a-b037-f8e270d7cf5e |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685189567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all.3685189567 |
Directory | /workspace/4.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.3712825128 |
Short name | T620 |
Test name | |
Test status | |
Simulation time | 15047634 ps |
CPU time | 0.84 seconds |
Started | Jun 30 06:55:03 PM PDT 24 |
Finished | Jun 30 06:55:05 PM PDT 24 |
Peak memory | 209192 kb |
Host | smart-c18a2170-5490-4b35-ac5b-d55a8047d0a8 |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712825128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct rl_volatile_unlock_smoke.3712825128 |
Directory | /workspace/4.lc_ctrl_volatile_unlock_smoke/latest |
Test location | /workspace/coverage/default/40.lc_ctrl_alert_test.110365218 |
Short name | T401 |
Test name | |
Test status | |
Simulation time | 42596639 ps |
CPU time | 1.35 seconds |
Started | Jun 30 06:57:22 PM PDT 24 |
Finished | Jun 30 06:57:26 PM PDT 24 |
Peak memory | 209424 kb |
Host | smart-55ef2a4a-1d7b-48bc-841f-84dfe8487091 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110365218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.110365218 |
Directory | /workspace/40.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/40.lc_ctrl_errors.1940509291 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 809581085 ps |
CPU time | 13.5 seconds |
Started | Jun 30 06:57:29 PM PDT 24 |
Finished | Jun 30 06:57:43 PM PDT 24 |
Peak memory | 226268 kb |
Host | smart-0cf34076-4146-4164-b9bd-3331126bcefd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1940509291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.1940509291 |
Directory | /workspace/40.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/40.lc_ctrl_jtag_access.2811292598 |
Short name | T757 |
Test name | |
Test status | |
Simulation time | 134581155 ps |
CPU time | 1.52 seconds |
Started | Jun 30 06:57:26 PM PDT 24 |
Finished | Jun 30 06:57:30 PM PDT 24 |
Peak memory | 217408 kb |
Host | smart-40cff8b2-a21b-49d1-86c1-cf4bc45178b8 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811292598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.2811292598 |
Directory | /workspace/40.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/40.lc_ctrl_prog_failure.2877322251 |
Short name | T596 |
Test name | |
Test status | |
Simulation time | 279331847 ps |
CPU time | 3.12 seconds |
Started | Jun 30 06:57:29 PM PDT 24 |
Finished | Jun 30 06:57:33 PM PDT 24 |
Peak memory | 222612 kb |
Host | smart-36d2626e-a7b2-4dbc-ac51-6b70016ade7a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2877322251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.2877322251 |
Directory | /workspace/40.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/40.lc_ctrl_sec_mubi.180921618 |
Short name | T640 |
Test name | |
Test status | |
Simulation time | 344601305 ps |
CPU time | 11.15 seconds |
Started | Jun 30 06:57:25 PM PDT 24 |
Finished | Jun 30 06:57:38 PM PDT 24 |
Peak memory | 226456 kb |
Host | smart-fe0257a0-9ed5-4b41-aace-88d9d27fa049 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180921618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.180921618 |
Directory | /workspace/40.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/40.lc_ctrl_sec_token_digest.3814567566 |
Short name | T836 |
Test name | |
Test status | |
Simulation time | 1673671648 ps |
CPU time | 17.19 seconds |
Started | Jun 30 06:57:26 PM PDT 24 |
Finished | Jun 30 06:57:45 PM PDT 24 |
Peak memory | 218584 kb |
Host | smart-4c77a37b-9d32-497f-904d-97ee908a5cf2 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814567566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d igest.3814567566 |
Directory | /workspace/40.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/40.lc_ctrl_sec_token_mux.4056429815 |
Short name | T687 |
Test name | |
Test status | |
Simulation time | 1334593019 ps |
CPU time | 8.45 seconds |
Started | Jun 30 06:57:26 PM PDT 24 |
Finished | Jun 30 06:57:36 PM PDT 24 |
Peak memory | 218548 kb |
Host | smart-db8feac0-5109-4855-ae6d-2416995cd395 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056429815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux. 4056429815 |
Directory | /workspace/40.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/40.lc_ctrl_security_escalation.466739847 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 273858548 ps |
CPU time | 9.06 seconds |
Started | Jun 30 06:57:26 PM PDT 24 |
Finished | Jun 30 06:57:37 PM PDT 24 |
Peak memory | 218772 kb |
Host | smart-8ea0a82a-e1c3-4837-82df-f6f7a98c31d7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=466739847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.466739847 |
Directory | /workspace/40.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/40.lc_ctrl_smoke.2270256316 |
Short name | T497 |
Test name | |
Test status | |
Simulation time | 227707092 ps |
CPU time | 2.51 seconds |
Started | Jun 30 06:57:26 PM PDT 24 |
Finished | Jun 30 06:57:30 PM PDT 24 |
Peak memory | 217980 kb |
Host | smart-5265f414-f742-4d9d-ad3a-245eb1444ddc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2270256316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.2270256316 |
Directory | /workspace/40.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/40.lc_ctrl_state_failure.3095445238 |
Short name | T671 |
Test name | |
Test status | |
Simulation time | 290718994 ps |
CPU time | 32.18 seconds |
Started | Jun 30 06:57:26 PM PDT 24 |
Finished | Jun 30 06:58:00 PM PDT 24 |
Peak memory | 251312 kb |
Host | smart-d7c70912-4ba3-4a27-ad9b-b10211591574 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3095445238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.3095445238 |
Directory | /workspace/40.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/40.lc_ctrl_state_post_trans.1018753461 |
Short name | T698 |
Test name | |
Test status | |
Simulation time | 224936289 ps |
CPU time | 6.57 seconds |
Started | Jun 30 06:57:24 PM PDT 24 |
Finished | Jun 30 06:57:32 PM PDT 24 |
Peak memory | 244876 kb |
Host | smart-2a8b617a-7a40-442c-b99f-c70ce0de7a7e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1018753461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.1018753461 |
Directory | /workspace/40.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/40.lc_ctrl_stress_all.2604287485 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 2378081041 ps |
CPU time | 18.11 seconds |
Started | Jun 30 06:57:26 PM PDT 24 |
Finished | Jun 30 06:57:46 PM PDT 24 |
Peak memory | 225116 kb |
Host | smart-12fe8de0-ace5-4681-b800-ca4b63e898b2 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604287485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all.2604287485 |
Directory | /workspace/40.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.78407987 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 25447971864 ps |
CPU time | 439.75 seconds |
Started | Jun 30 06:57:29 PM PDT 24 |
Finished | Jun 30 07:04:50 PM PDT 24 |
Peak memory | 280384 kb |
Host | smart-3d83b1ce-a336-4cd6-9e78-42abead9beb2 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=78407987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all_with_rand_reset.78407987 |
Directory | /workspace/40.lc_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.3290806252 |
Short name | T281 |
Test name | |
Test status | |
Simulation time | 91875407 ps |
CPU time | 0.86 seconds |
Started | Jun 30 06:57:25 PM PDT 24 |
Finished | Jun 30 06:57:28 PM PDT 24 |
Peak memory | 209456 kb |
Host | smart-deadcc90-9714-4660-9e74-8c8919715cdf |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290806252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c trl_volatile_unlock_smoke.3290806252 |
Directory | /workspace/40.lc_ctrl_volatile_unlock_smoke/latest |
Test location | /workspace/coverage/default/41.lc_ctrl_alert_test.595534927 |
Short name | T514 |
Test name | |
Test status | |
Simulation time | 37033069 ps |
CPU time | 1.05 seconds |
Started | Jun 30 06:57:29 PM PDT 24 |
Finished | Jun 30 06:57:31 PM PDT 24 |
Peak memory | 209376 kb |
Host | smart-c6a98cfc-6fd3-4ace-8f13-94d06e9dd9d2 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595534927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.595534927 |
Directory | /workspace/41.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/41.lc_ctrl_errors.448672151 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 2054079453 ps |
CPU time | 21.76 seconds |
Started | Jun 30 06:57:30 PM PDT 24 |
Finished | Jun 30 06:57:53 PM PDT 24 |
Peak memory | 226440 kb |
Host | smart-866f62e8-7c40-41a8-b411-10bc46270c3f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=448672151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.448672151 |
Directory | /workspace/41.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/41.lc_ctrl_jtag_access.179779860 |
Short name | T558 |
Test name | |
Test status | |
Simulation time | 94893241 ps |
CPU time | 1.88 seconds |
Started | Jun 30 06:57:32 PM PDT 24 |
Finished | Jun 30 06:57:35 PM PDT 24 |
Peak memory | 217504 kb |
Host | smart-cd6f8731-b20e-463c-bd9f-8dd656a083b6 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179779860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.179779860 |
Directory | /workspace/41.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/41.lc_ctrl_prog_failure.2725110594 |
Short name | T559 |
Test name | |
Test status | |
Simulation time | 107627603 ps |
CPU time | 2.12 seconds |
Started | Jun 30 06:57:30 PM PDT 24 |
Finished | Jun 30 06:57:33 PM PDT 24 |
Peak memory | 218640 kb |
Host | smart-0c92d993-e50f-4317-89f3-c87d270f45e4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2725110594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.2725110594 |
Directory | /workspace/41.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/41.lc_ctrl_sec_mubi.504613058 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 235876892 ps |
CPU time | 9.26 seconds |
Started | Jun 30 06:57:31 PM PDT 24 |
Finished | Jun 30 06:57:41 PM PDT 24 |
Peak memory | 226420 kb |
Host | smart-f34d2ac2-c249-4d64-a42e-36a4291d0e6c |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504613058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.504613058 |
Directory | /workspace/41.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/41.lc_ctrl_sec_token_digest.548665242 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 1256888918 ps |
CPU time | 14.6 seconds |
Started | Jun 30 06:57:32 PM PDT 24 |
Finished | Jun 30 06:57:48 PM PDT 24 |
Peak memory | 218628 kb |
Host | smart-6f5ce1ec-35ad-48a1-a9f5-1433eb24dd8f |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548665242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_di gest.548665242 |
Directory | /workspace/41.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/41.lc_ctrl_sec_token_mux.1735661654 |
Short name | T621 |
Test name | |
Test status | |
Simulation time | 927769165 ps |
CPU time | 9.9 seconds |
Started | Jun 30 06:57:30 PM PDT 24 |
Finished | Jun 30 06:57:41 PM PDT 24 |
Peak memory | 218568 kb |
Host | smart-52efa8f0-da5a-4cd3-82c9-a0cfe79039a3 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735661654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux. 1735661654 |
Directory | /workspace/41.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/41.lc_ctrl_security_escalation.2404757919 |
Short name | T396 |
Test name | |
Test status | |
Simulation time | 1145521787 ps |
CPU time | 9.4 seconds |
Started | Jun 30 06:57:33 PM PDT 24 |
Finished | Jun 30 06:57:43 PM PDT 24 |
Peak memory | 225304 kb |
Host | smart-d0951b27-a2b3-4f37-ac22-4e9fb5e7cb08 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2404757919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.2404757919 |
Directory | /workspace/41.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/41.lc_ctrl_smoke.3074203184 |
Short name | T520 |
Test name | |
Test status | |
Simulation time | 1058634329 ps |
CPU time | 11.72 seconds |
Started | Jun 30 06:57:26 PM PDT 24 |
Finished | Jun 30 06:57:39 PM PDT 24 |
Peak memory | 218300 kb |
Host | smart-9bd15151-b9f0-40c6-a6ad-eefdc51d36f2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3074203184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.3074203184 |
Directory | /workspace/41.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/41.lc_ctrl_state_failure.4288761686 |
Short name | T308 |
Test name | |
Test status | |
Simulation time | 439200347 ps |
CPU time | 21.39 seconds |
Started | Jun 30 06:57:24 PM PDT 24 |
Finished | Jun 30 06:57:48 PM PDT 24 |
Peak memory | 251336 kb |
Host | smart-c0b0d836-0f32-44eb-bfe1-8c13ee284cc6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4288761686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.4288761686 |
Directory | /workspace/41.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/41.lc_ctrl_state_post_trans.205156620 |
Short name | T845 |
Test name | |
Test status | |
Simulation time | 309016853 ps |
CPU time | 6.85 seconds |
Started | Jun 30 06:57:31 PM PDT 24 |
Finished | Jun 30 06:57:39 PM PDT 24 |
Peak memory | 250792 kb |
Host | smart-a75b135f-8b97-43ae-88c1-7826dbb936f0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=205156620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.205156620 |
Directory | /workspace/41.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/41.lc_ctrl_stress_all.1798931549 |
Short name | T662 |
Test name | |
Test status | |
Simulation time | 12247212135 ps |
CPU time | 271.29 seconds |
Started | Jun 30 06:57:33 PM PDT 24 |
Finished | Jun 30 07:02:05 PM PDT 24 |
Peak memory | 277448 kb |
Host | smart-8f54842e-548f-4f65-932f-f2100a06caa8 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798931549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all.1798931549 |
Directory | /workspace/41.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.1189032637 |
Short name | T679 |
Test name | |
Test status | |
Simulation time | 74028973 ps |
CPU time | 0.92 seconds |
Started | Jun 30 06:57:29 PM PDT 24 |
Finished | Jun 30 06:57:31 PM PDT 24 |
Peak memory | 213272 kb |
Host | smart-a84f9245-92b1-4a5a-b03d-2d9b182f22ea |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189032637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c trl_volatile_unlock_smoke.1189032637 |
Directory | /workspace/41.lc_ctrl_volatile_unlock_smoke/latest |
Test location | /workspace/coverage/default/42.lc_ctrl_alert_test.3548027115 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 97488669 ps |
CPU time | 1 seconds |
Started | Jun 30 06:57:34 PM PDT 24 |
Finished | Jun 30 06:57:36 PM PDT 24 |
Peak memory | 209348 kb |
Host | smart-a26f8023-c1bb-44a9-b20d-a838e68ef062 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548027115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.3548027115 |
Directory | /workspace/42.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/42.lc_ctrl_errors.4175588270 |
Short name | T463 |
Test name | |
Test status | |
Simulation time | 455764175 ps |
CPU time | 9.19 seconds |
Started | Jun 30 06:57:36 PM PDT 24 |
Finished | Jun 30 06:57:47 PM PDT 24 |
Peak memory | 226440 kb |
Host | smart-4ec4a854-d939-4610-a4ed-cdf369a1577d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4175588270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.4175588270 |
Directory | /workspace/42.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/42.lc_ctrl_jtag_access.2998813908 |
Short name | T732 |
Test name | |
Test status | |
Simulation time | 510938941 ps |
CPU time | 11.36 seconds |
Started | Jun 30 06:57:32 PM PDT 24 |
Finished | Jun 30 06:57:45 PM PDT 24 |
Peak memory | 217476 kb |
Host | smart-ba0fa102-f9de-4a2d-9eac-44c72d02fce3 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998813908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.2998813908 |
Directory | /workspace/42.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/42.lc_ctrl_prog_failure.3926705766 |
Short name | T314 |
Test name | |
Test status | |
Simulation time | 16841410 ps |
CPU time | 1.44 seconds |
Started | Jun 30 06:57:31 PM PDT 24 |
Finished | Jun 30 06:57:34 PM PDT 24 |
Peak memory | 218660 kb |
Host | smart-0966af56-a645-41c2-9f4d-b5d70485f0e3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3926705766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.3926705766 |
Directory | /workspace/42.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/42.lc_ctrl_sec_mubi.3691128521 |
Short name | T777 |
Test name | |
Test status | |
Simulation time | 372635455 ps |
CPU time | 15.46 seconds |
Started | Jun 30 06:57:34 PM PDT 24 |
Finished | Jun 30 06:57:50 PM PDT 24 |
Peak memory | 226432 kb |
Host | smart-5040e25a-91ba-4848-b319-081df18ff97d |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691128521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.3691128521 |
Directory | /workspace/42.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/42.lc_ctrl_sec_token_digest.3882655815 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 326534894 ps |
CPU time | 14.8 seconds |
Started | Jun 30 06:57:30 PM PDT 24 |
Finished | Jun 30 06:57:46 PM PDT 24 |
Peak memory | 218556 kb |
Host | smart-dcf87b4e-34c9-47d7-8f50-2ca11eedf0bb |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882655815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d igest.3882655815 |
Directory | /workspace/42.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/42.lc_ctrl_sec_token_mux.3446735156 |
Short name | T856 |
Test name | |
Test status | |
Simulation time | 289436003 ps |
CPU time | 11.98 seconds |
Started | Jun 30 06:57:31 PM PDT 24 |
Finished | Jun 30 06:57:44 PM PDT 24 |
Peak memory | 218596 kb |
Host | smart-d9e3d05a-6771-433f-85dd-be073a3d4824 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446735156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux. 3446735156 |
Directory | /workspace/42.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/42.lc_ctrl_security_escalation.3540080410 |
Short name | T382 |
Test name | |
Test status | |
Simulation time | 1143031844 ps |
CPU time | 12.18 seconds |
Started | Jun 30 06:57:30 PM PDT 24 |
Finished | Jun 30 06:57:43 PM PDT 24 |
Peak memory | 226368 kb |
Host | smart-688ad191-9f81-4bd8-b4fa-eee323fa3096 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3540080410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.3540080410 |
Directory | /workspace/42.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/42.lc_ctrl_smoke.1329414956 |
Short name | T554 |
Test name | |
Test status | |
Simulation time | 964953510 ps |
CPU time | 2.85 seconds |
Started | Jun 30 06:57:32 PM PDT 24 |
Finished | Jun 30 06:57:36 PM PDT 24 |
Peak memory | 214760 kb |
Host | smart-092da5e9-34c2-4db8-9523-c772cbeff195 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1329414956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.1329414956 |
Directory | /workspace/42.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/42.lc_ctrl_state_failure.257704078 |
Short name | T335 |
Test name | |
Test status | |
Simulation time | 474315311 ps |
CPU time | 27.21 seconds |
Started | Jun 30 06:57:30 PM PDT 24 |
Finished | Jun 30 06:57:59 PM PDT 24 |
Peak memory | 251336 kb |
Host | smart-aafb01aa-832b-49e4-b0c2-da9adb063de0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=257704078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.257704078 |
Directory | /workspace/42.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/42.lc_ctrl_state_post_trans.3436030126 |
Short name | T319 |
Test name | |
Test status | |
Simulation time | 107599610 ps |
CPU time | 2.65 seconds |
Started | Jun 30 06:57:32 PM PDT 24 |
Finished | Jun 30 06:57:36 PM PDT 24 |
Peak memory | 226752 kb |
Host | smart-eea8141f-8cd8-4c60-b91b-305e24f81a58 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3436030126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.3436030126 |
Directory | /workspace/42.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/42.lc_ctrl_stress_all.2419065263 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 14432512478 ps |
CPU time | 394.04 seconds |
Started | Jun 30 06:57:35 PM PDT 24 |
Finished | Jun 30 07:04:10 PM PDT 24 |
Peak memory | 284068 kb |
Host | smart-6a3cd59f-2a2f-4baa-928d-862d01cfe4e9 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419065263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all.2419065263 |
Directory | /workspace/42.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.1060882000 |
Short name | T697 |
Test name | |
Test status | |
Simulation time | 53262782 ps |
CPU time | 0.95 seconds |
Started | Jun 30 06:57:32 PM PDT 24 |
Finished | Jun 30 06:57:34 PM PDT 24 |
Peak memory | 212200 kb |
Host | smart-c0b91a7d-5877-4b42-8e2d-e3064c2ac591 |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060882000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c trl_volatile_unlock_smoke.1060882000 |
Directory | /workspace/42.lc_ctrl_volatile_unlock_smoke/latest |
Test location | /workspace/coverage/default/43.lc_ctrl_alert_test.4053147392 |
Short name | T843 |
Test name | |
Test status | |
Simulation time | 21001383 ps |
CPU time | 0.99 seconds |
Started | Jun 30 06:57:33 PM PDT 24 |
Finished | Jun 30 06:57:35 PM PDT 24 |
Peak memory | 209352 kb |
Host | smart-a1fb3c7e-c42a-414d-9fc4-c32ace21fd72 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053147392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.4053147392 |
Directory | /workspace/43.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/43.lc_ctrl_errors.3388199135 |
Short name | T707 |
Test name | |
Test status | |
Simulation time | 1197652222 ps |
CPU time | 15 seconds |
Started | Jun 30 06:57:40 PM PDT 24 |
Finished | Jun 30 06:57:55 PM PDT 24 |
Peak memory | 218628 kb |
Host | smart-5e5ef7bc-8c0f-4513-a007-7170a3dfb721 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3388199135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.3388199135 |
Directory | /workspace/43.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/43.lc_ctrl_jtag_access.1202918211 |
Short name | T369 |
Test name | |
Test status | |
Simulation time | 147933161 ps |
CPU time | 1.55 seconds |
Started | Jun 30 06:57:36 PM PDT 24 |
Finished | Jun 30 06:57:38 PM PDT 24 |
Peak memory | 217444 kb |
Host | smart-cbc07ad5-bc81-45ac-83a3-5769c421fd90 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202918211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.1202918211 |
Directory | /workspace/43.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/43.lc_ctrl_prog_failure.3180397962 |
Short name | T556 |
Test name | |
Test status | |
Simulation time | 72411635 ps |
CPU time | 1.88 seconds |
Started | Jun 30 06:57:36 PM PDT 24 |
Finished | Jun 30 06:57:39 PM PDT 24 |
Peak memory | 218624 kb |
Host | smart-f9e547e9-b719-47d4-8fe1-9f537edcbde0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3180397962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.3180397962 |
Directory | /workspace/43.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/43.lc_ctrl_sec_mubi.122524301 |
Short name | T837 |
Test name | |
Test status | |
Simulation time | 1550165938 ps |
CPU time | 13.04 seconds |
Started | Jun 30 06:57:36 PM PDT 24 |
Finished | Jun 30 06:57:51 PM PDT 24 |
Peak memory | 226452 kb |
Host | smart-44c9186c-dbf3-4715-a27f-ceabeab45906 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122524301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.122524301 |
Directory | /workspace/43.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/43.lc_ctrl_sec_token_digest.2543249998 |
Short name | T769 |
Test name | |
Test status | |
Simulation time | 3817589698 ps |
CPU time | 16.53 seconds |
Started | Jun 30 06:57:35 PM PDT 24 |
Finished | Jun 30 06:57:52 PM PDT 24 |
Peak memory | 218612 kb |
Host | smart-04b29295-7f6e-4584-89d5-db02f59ebf6c |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543249998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d igest.2543249998 |
Directory | /workspace/43.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/43.lc_ctrl_sec_token_mux.2479367335 |
Short name | T298 |
Test name | |
Test status | |
Simulation time | 908829103 ps |
CPU time | 8.38 seconds |
Started | Jun 30 06:57:45 PM PDT 24 |
Finished | Jun 30 06:57:54 PM PDT 24 |
Peak memory | 218580 kb |
Host | smart-bb3f70eb-4036-4135-8924-fc3c19d1438e |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479367335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux. 2479367335 |
Directory | /workspace/43.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/43.lc_ctrl_smoke.3679476034 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 72854947 ps |
CPU time | 1.86 seconds |
Started | Jun 30 06:57:34 PM PDT 24 |
Finished | Jun 30 06:57:37 PM PDT 24 |
Peak memory | 223212 kb |
Host | smart-730d2d4e-a93c-43dc-b054-e468edb9b274 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3679476034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.3679476034 |
Directory | /workspace/43.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/43.lc_ctrl_state_failure.3450255010 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 241862177 ps |
CPU time | 31.8 seconds |
Started | Jun 30 06:57:37 PM PDT 24 |
Finished | Jun 30 06:58:11 PM PDT 24 |
Peak memory | 251408 kb |
Host | smart-3e8d50c6-329b-4cc7-87a1-dd6225a9dec6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3450255010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.3450255010 |
Directory | /workspace/43.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/43.lc_ctrl_state_post_trans.3864516865 |
Short name | T668 |
Test name | |
Test status | |
Simulation time | 78641564 ps |
CPU time | 9.68 seconds |
Started | Jun 30 06:57:35 PM PDT 24 |
Finished | Jun 30 06:57:45 PM PDT 24 |
Peak memory | 251228 kb |
Host | smart-35661b2e-e4aa-4fcb-bc03-aca79b064630 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3864516865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.3864516865 |
Directory | /workspace/43.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/43.lc_ctrl_stress_all.532465212 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 28146742656 ps |
CPU time | 237.73 seconds |
Started | Jun 30 06:57:40 PM PDT 24 |
Finished | Jun 30 07:01:38 PM PDT 24 |
Peak memory | 251364 kb |
Host | smart-f9752bc6-73e5-412b-8e83-313089fe693d |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532465212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all.532465212 |
Directory | /workspace/43.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.1967826260 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 17037133032 ps |
CPU time | 549.54 seconds |
Started | Jun 30 06:57:36 PM PDT 24 |
Finished | Jun 30 07:06:47 PM PDT 24 |
Peak memory | 284408 kb |
Host | smart-039f579e-6ce1-43ba-b2fd-555ed9ac1160 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1967826260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.1967826260 |
Directory | /workspace/43.lc_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.72952858 |
Short name | T548 |
Test name | |
Test status | |
Simulation time | 28537988 ps |
CPU time | 0.85 seconds |
Started | Jun 30 06:57:43 PM PDT 24 |
Finished | Jun 30 06:57:45 PM PDT 24 |
Peak memory | 209448 kb |
Host | smart-33fa0606-f589-4b23-ae3b-e43f4a7d4562 |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72952858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctr l_volatile_unlock_smoke.72952858 |
Directory | /workspace/43.lc_ctrl_volatile_unlock_smoke/latest |
Test location | /workspace/coverage/default/44.lc_ctrl_alert_test.339614255 |
Short name | T831 |
Test name | |
Test status | |
Simulation time | 19028392 ps |
CPU time | 1.11 seconds |
Started | Jun 30 06:57:35 PM PDT 24 |
Finished | Jun 30 06:57:37 PM PDT 24 |
Peak memory | 209372 kb |
Host | smart-48314ba7-7ce2-405d-8cc0-0aeceeec0921 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339614255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.339614255 |
Directory | /workspace/44.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/44.lc_ctrl_errors.1483663693 |
Short name | T690 |
Test name | |
Test status | |
Simulation time | 403348145 ps |
CPU time | 17.75 seconds |
Started | Jun 30 06:57:35 PM PDT 24 |
Finished | Jun 30 06:57:54 PM PDT 24 |
Peak memory | 218644 kb |
Host | smart-8aed0fff-e036-425e-9ce4-f936de83fed1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1483663693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.1483663693 |
Directory | /workspace/44.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/44.lc_ctrl_jtag_access.1470978879 |
Short name | T806 |
Test name | |
Test status | |
Simulation time | 107831198 ps |
CPU time | 1.3 seconds |
Started | Jun 30 06:57:36 PM PDT 24 |
Finished | Jun 30 06:57:39 PM PDT 24 |
Peak memory | 217468 kb |
Host | smart-b34a0316-1bc5-4381-aa3b-3cfe5cf6a38d |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470978879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.1470978879 |
Directory | /workspace/44.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/44.lc_ctrl_prog_failure.2828889763 |
Short name | T628 |
Test name | |
Test status | |
Simulation time | 68742272 ps |
CPU time | 3.24 seconds |
Started | Jun 30 06:57:37 PM PDT 24 |
Finished | Jun 30 06:57:42 PM PDT 24 |
Peak memory | 218636 kb |
Host | smart-13a25875-e8c2-4f83-b0df-b311e6e179f8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2828889763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.2828889763 |
Directory | /workspace/44.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/44.lc_ctrl_sec_mubi.1570727348 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 1135146823 ps |
CPU time | 14.35 seconds |
Started | Jun 30 06:57:34 PM PDT 24 |
Finished | Jun 30 06:57:49 PM PDT 24 |
Peak memory | 226452 kb |
Host | smart-071f46e3-2cc2-4201-acc0-9a4214753841 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570727348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.1570727348 |
Directory | /workspace/44.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/44.lc_ctrl_sec_token_digest.2871455465 |
Short name | T567 |
Test name | |
Test status | |
Simulation time | 221822924 ps |
CPU time | 10.45 seconds |
Started | Jun 30 06:57:45 PM PDT 24 |
Finished | Jun 30 06:57:56 PM PDT 24 |
Peak memory | 218664 kb |
Host | smart-47c180c4-45f4-48f8-9361-d53ba90f7ed5 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871455465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d igest.2871455465 |
Directory | /workspace/44.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/44.lc_ctrl_sec_token_mux.454839070 |
Short name | T306 |
Test name | |
Test status | |
Simulation time | 588935479 ps |
CPU time | 12 seconds |
Started | Jun 30 06:57:39 PM PDT 24 |
Finished | Jun 30 06:57:52 PM PDT 24 |
Peak memory | 218572 kb |
Host | smart-4fcf9dbf-d492-415c-a93c-a914ba459a15 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454839070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.454839070 |
Directory | /workspace/44.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/44.lc_ctrl_security_escalation.1429179140 |
Short name | T877 |
Test name | |
Test status | |
Simulation time | 1812913171 ps |
CPU time | 10.13 seconds |
Started | Jun 30 06:57:34 PM PDT 24 |
Finished | Jun 30 06:57:45 PM PDT 24 |
Peak memory | 226416 kb |
Host | smart-55b74ffc-d468-450c-9ef2-fb27db2af821 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1429179140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.1429179140 |
Directory | /workspace/44.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/44.lc_ctrl_smoke.4098289820 |
Short name | T828 |
Test name | |
Test status | |
Simulation time | 34061818 ps |
CPU time | 2.58 seconds |
Started | Jun 30 06:57:35 PM PDT 24 |
Finished | Jun 30 06:57:39 PM PDT 24 |
Peak memory | 218084 kb |
Host | smart-870b945f-136c-47c9-b30c-140601c161e1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4098289820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.4098289820 |
Directory | /workspace/44.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/44.lc_ctrl_state_failure.3542701273 |
Short name | T416 |
Test name | |
Test status | |
Simulation time | 1272297426 ps |
CPU time | 20.78 seconds |
Started | Jun 30 06:57:34 PM PDT 24 |
Finished | Jun 30 06:57:56 PM PDT 24 |
Peak memory | 246052 kb |
Host | smart-66907ad8-4c5c-4935-a63f-f36f2d0c4079 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3542701273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.3542701273 |
Directory | /workspace/44.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/44.lc_ctrl_state_post_trans.4072941575 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 43182903 ps |
CPU time | 6.12 seconds |
Started | Jun 30 06:57:37 PM PDT 24 |
Finished | Jun 30 06:57:45 PM PDT 24 |
Peak memory | 247008 kb |
Host | smart-56deda2f-38aa-42c8-9322-07a3f4ac8f12 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4072941575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.4072941575 |
Directory | /workspace/44.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/44.lc_ctrl_stress_all.2243229722 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 2174027581 ps |
CPU time | 93 seconds |
Started | Jun 30 06:57:35 PM PDT 24 |
Finished | Jun 30 06:59:09 PM PDT 24 |
Peak memory | 276360 kb |
Host | smart-06f9e99f-ae78-4db3-a445-7c7c177ac999 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243229722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all.2243229722 |
Directory | /workspace/44.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.494055822 |
Short name | T763 |
Test name | |
Test status | |
Simulation time | 15449268 ps |
CPU time | 1.03 seconds |
Started | Jun 30 06:57:35 PM PDT 24 |
Finished | Jun 30 06:57:37 PM PDT 24 |
Peak memory | 209296 kb |
Host | smart-145b6d21-d4f4-43fe-91db-0a4f9a412060 |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494055822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ct rl_volatile_unlock_smoke.494055822 |
Directory | /workspace/44.lc_ctrl_volatile_unlock_smoke/latest |
Test location | /workspace/coverage/default/45.lc_ctrl_alert_test.4167622816 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 42909700 ps |
CPU time | 1.35 seconds |
Started | Jun 30 06:57:42 PM PDT 24 |
Finished | Jun 30 06:57:45 PM PDT 24 |
Peak memory | 209536 kb |
Host | smart-2c036a4e-a87a-4735-8102-f9204288b4e1 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167622816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.4167622816 |
Directory | /workspace/45.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/45.lc_ctrl_errors.2109873213 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 403666803 ps |
CPU time | 9.75 seconds |
Started | Jun 30 06:57:42 PM PDT 24 |
Finished | Jun 30 06:57:53 PM PDT 24 |
Peak memory | 226448 kb |
Host | smart-24537126-c5a2-425f-9e8c-be74ffe82f69 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2109873213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.2109873213 |
Directory | /workspace/45.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/45.lc_ctrl_jtag_access.3834965071 |
Short name | T657 |
Test name | |
Test status | |
Simulation time | 1762497635 ps |
CPU time | 11.07 seconds |
Started | Jun 30 06:57:42 PM PDT 24 |
Finished | Jun 30 06:57:53 PM PDT 24 |
Peak memory | 217544 kb |
Host | smart-833187b0-1839-4973-91c3-8da68a50fc5b |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834965071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.3834965071 |
Directory | /workspace/45.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/45.lc_ctrl_prog_failure.458804463 |
Short name | T644 |
Test name | |
Test status | |
Simulation time | 111545621 ps |
CPU time | 2.16 seconds |
Started | Jun 30 06:57:44 PM PDT 24 |
Finished | Jun 30 06:57:47 PM PDT 24 |
Peak memory | 218624 kb |
Host | smart-6cded65e-4289-4c96-8de7-3cc215eec0e7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=458804463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.458804463 |
Directory | /workspace/45.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/45.lc_ctrl_sec_mubi.1685038634 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 620343647 ps |
CPU time | 14.87 seconds |
Started | Jun 30 06:57:44 PM PDT 24 |
Finished | Jun 30 06:57:59 PM PDT 24 |
Peak memory | 219376 kb |
Host | smart-9d888e7c-7232-4f8c-b6b4-f741a1ac85a8 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685038634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.1685038634 |
Directory | /workspace/45.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/45.lc_ctrl_sec_token_digest.3972445778 |
Short name | T729 |
Test name | |
Test status | |
Simulation time | 791561450 ps |
CPU time | 9.73 seconds |
Started | Jun 30 06:57:40 PM PDT 24 |
Finished | Jun 30 06:57:51 PM PDT 24 |
Peak memory | 218532 kb |
Host | smart-6e7035cc-28f3-44c8-aa35-46bc57d6c1f0 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972445778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d igest.3972445778 |
Directory | /workspace/45.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/45.lc_ctrl_sec_token_mux.2659027138 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 418466055 ps |
CPU time | 13.71 seconds |
Started | Jun 30 06:57:43 PM PDT 24 |
Finished | Jun 30 06:57:57 PM PDT 24 |
Peak memory | 218580 kb |
Host | smart-8fa8550a-a3e7-4acf-9fdd-63af94c5f915 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659027138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux. 2659027138 |
Directory | /workspace/45.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/45.lc_ctrl_security_escalation.2639644565 |
Short name | T482 |
Test name | |
Test status | |
Simulation time | 269462945 ps |
CPU time | 7.93 seconds |
Started | Jun 30 06:57:43 PM PDT 24 |
Finished | Jun 30 06:57:52 PM PDT 24 |
Peak memory | 226412 kb |
Host | smart-bf1d0c27-6f89-49cb-8575-f93059d46c0d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2639644565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.2639644565 |
Directory | /workspace/45.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/45.lc_ctrl_smoke.604147186 |
Short name | T426 |
Test name | |
Test status | |
Simulation time | 258497404 ps |
CPU time | 3.92 seconds |
Started | Jun 30 06:57:38 PM PDT 24 |
Finished | Jun 30 06:57:43 PM PDT 24 |
Peak memory | 218016 kb |
Host | smart-2d52ccd3-d90b-456d-8e1a-63cee4677b31 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=604147186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.604147186 |
Directory | /workspace/45.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/45.lc_ctrl_state_failure.2144463376 |
Short name | T376 |
Test name | |
Test status | |
Simulation time | 1037303007 ps |
CPU time | 23.62 seconds |
Started | Jun 30 06:57:42 PM PDT 24 |
Finished | Jun 30 06:58:07 PM PDT 24 |
Peak memory | 251400 kb |
Host | smart-1ff9f3f3-ab35-4e55-a8a8-891fe3d6b8a7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2144463376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.2144463376 |
Directory | /workspace/45.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/45.lc_ctrl_state_post_trans.3538440870 |
Short name | T602 |
Test name | |
Test status | |
Simulation time | 89277442 ps |
CPU time | 7.38 seconds |
Started | Jun 30 06:57:39 PM PDT 24 |
Finished | Jun 30 06:57:48 PM PDT 24 |
Peak memory | 251336 kb |
Host | smart-28fc6f5e-d1ad-41ec-ba3a-86e656cb2778 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3538440870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.3538440870 |
Directory | /workspace/45.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/45.lc_ctrl_stress_all.4049507271 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 4858020969 ps |
CPU time | 70.06 seconds |
Started | Jun 30 06:57:40 PM PDT 24 |
Finished | Jun 30 06:58:50 PM PDT 24 |
Peak memory | 226496 kb |
Host | smart-88c28b60-02e2-4f3d-ac3a-ad06603238c8 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049507271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all.4049507271 |
Directory | /workspace/45.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1258388364 |
Short name | T705 |
Test name | |
Test status | |
Simulation time | 52388655 ps |
CPU time | 1.08 seconds |
Started | Jun 30 06:57:44 PM PDT 24 |
Finished | Jun 30 06:57:46 PM PDT 24 |
Peak memory | 218172 kb |
Host | smart-f0bc1781-4845-431d-8f52-4eac07c8ebcb |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258388364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c trl_volatile_unlock_smoke.1258388364 |
Directory | /workspace/45.lc_ctrl_volatile_unlock_smoke/latest |
Test location | /workspace/coverage/default/46.lc_ctrl_alert_test.1054671536 |
Short name | T764 |
Test name | |
Test status | |
Simulation time | 55650862 ps |
CPU time | 0.85 seconds |
Started | Jun 30 06:57:48 PM PDT 24 |
Finished | Jun 30 06:57:50 PM PDT 24 |
Peak memory | 209072 kb |
Host | smart-52d5b1ef-96b8-444d-a7e4-ec02141767c8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054671536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.1054671536 |
Directory | /workspace/46.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/46.lc_ctrl_errors.617321886 |
Short name | T542 |
Test name | |
Test status | |
Simulation time | 668128540 ps |
CPU time | 16.8 seconds |
Started | Jun 30 06:57:42 PM PDT 24 |
Finished | Jun 30 06:58:00 PM PDT 24 |
Peak memory | 218552 kb |
Host | smart-04e0c35c-7109-4bf0-aa8b-b8cc970b1ea3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=617321886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.617321886 |
Directory | /workspace/46.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/46.lc_ctrl_jtag_access.489499810 |
Short name | T496 |
Test name | |
Test status | |
Simulation time | 721971314 ps |
CPU time | 7.17 seconds |
Started | Jun 30 06:57:44 PM PDT 24 |
Finished | Jun 30 06:57:52 PM PDT 24 |
Peak memory | 217700 kb |
Host | smart-5279b938-8b25-40fd-9954-c6c279ffadc7 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489499810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.489499810 |
Directory | /workspace/46.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/46.lc_ctrl_prog_failure.2839820845 |
Short name | T434 |
Test name | |
Test status | |
Simulation time | 54300631 ps |
CPU time | 1.77 seconds |
Started | Jun 30 06:57:44 PM PDT 24 |
Finished | Jun 30 06:57:46 PM PDT 24 |
Peak memory | 222400 kb |
Host | smart-5a5555c0-61e1-43b6-bbe9-331da90e8e3f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2839820845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.2839820845 |
Directory | /workspace/46.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/46.lc_ctrl_sec_mubi.1148417963 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 525230059 ps |
CPU time | 10.95 seconds |
Started | Jun 30 06:57:42 PM PDT 24 |
Finished | Jun 30 06:57:54 PM PDT 24 |
Peak memory | 226448 kb |
Host | smart-2cd0425a-68d1-4871-a24f-da709df9ec50 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148417963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.1148417963 |
Directory | /workspace/46.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/46.lc_ctrl_sec_token_digest.2088146638 |
Short name | T445 |
Test name | |
Test status | |
Simulation time | 364478304 ps |
CPU time | 11.15 seconds |
Started | Jun 30 06:57:43 PM PDT 24 |
Finished | Jun 30 06:57:55 PM PDT 24 |
Peak memory | 218680 kb |
Host | smart-5ac047d3-bead-4b42-b0f1-8edad639d480 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088146638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d igest.2088146638 |
Directory | /workspace/46.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/46.lc_ctrl_sec_token_mux.958776566 |
Short name | T746 |
Test name | |
Test status | |
Simulation time | 658663401 ps |
CPU time | 12.44 seconds |
Started | Jun 30 06:57:46 PM PDT 24 |
Finished | Jun 30 06:58:00 PM PDT 24 |
Peak memory | 218580 kb |
Host | smart-f155ac69-ee9a-40e7-be8b-801eb0f99750 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958776566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.958776566 |
Directory | /workspace/46.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/46.lc_ctrl_security_escalation.3486277867 |
Short name | T284 |
Test name | |
Test status | |
Simulation time | 1242575985 ps |
CPU time | 6.21 seconds |
Started | Jun 30 06:57:45 PM PDT 24 |
Finished | Jun 30 06:57:52 PM PDT 24 |
Peak memory | 224776 kb |
Host | smart-d4cb133a-7094-468c-aaa8-e242074dab2f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3486277867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.3486277867 |
Directory | /workspace/46.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/46.lc_ctrl_smoke.2903252055 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 298935474 ps |
CPU time | 3.32 seconds |
Started | Jun 30 06:57:42 PM PDT 24 |
Finished | Jun 30 06:57:47 PM PDT 24 |
Peak memory | 218152 kb |
Host | smart-e6326f58-630f-4862-a382-19b17122c1eb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2903252055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.2903252055 |
Directory | /workspace/46.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/46.lc_ctrl_state_failure.2762954703 |
Short name | T572 |
Test name | |
Test status | |
Simulation time | 336497354 ps |
CPU time | 33.82 seconds |
Started | Jun 30 06:57:41 PM PDT 24 |
Finished | Jun 30 06:58:16 PM PDT 24 |
Peak memory | 251320 kb |
Host | smart-bcc8beb4-2760-4d80-bf0f-9407d56e5dd8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2762954703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.2762954703 |
Directory | /workspace/46.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/46.lc_ctrl_state_post_trans.2025597269 |
Short name | T374 |
Test name | |
Test status | |
Simulation time | 105033751 ps |
CPU time | 7.12 seconds |
Started | Jun 30 06:57:42 PM PDT 24 |
Finished | Jun 30 06:57:49 PM PDT 24 |
Peak memory | 250896 kb |
Host | smart-48531830-f35e-4cb1-a757-4f2ce2fc2fca |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2025597269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.2025597269 |
Directory | /workspace/46.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.3379645103 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 24168336994 ps |
CPU time | 810.99 seconds |
Started | Jun 30 06:57:46 PM PDT 24 |
Finished | Jun 30 07:11:18 PM PDT 24 |
Peak memory | 313696 kb |
Host | smart-342ea037-ea0d-43c6-bbfb-9a03573988ff |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3379645103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all_with_rand_reset.3379645103 |
Directory | /workspace/46.lc_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.1270115499 |
Short name | T820 |
Test name | |
Test status | |
Simulation time | 49146471 ps |
CPU time | 0.78 seconds |
Started | Jun 30 06:57:41 PM PDT 24 |
Finished | Jun 30 06:57:42 PM PDT 24 |
Peak memory | 209028 kb |
Host | smart-957062df-d560-4046-b8b1-376d2ae686fa |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270115499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c trl_volatile_unlock_smoke.1270115499 |
Directory | /workspace/46.lc_ctrl_volatile_unlock_smoke/latest |
Test location | /workspace/coverage/default/47.lc_ctrl_alert_test.1296788255 |
Short name | T547 |
Test name | |
Test status | |
Simulation time | 43430645 ps |
CPU time | 1.02 seconds |
Started | Jun 30 06:57:48 PM PDT 24 |
Finished | Jun 30 06:57:50 PM PDT 24 |
Peak memory | 209292 kb |
Host | smart-d57f58ae-7ed5-4582-aef0-f277ef55745d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296788255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.1296788255 |
Directory | /workspace/47.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/47.lc_ctrl_errors.1972951382 |
Short name | T447 |
Test name | |
Test status | |
Simulation time | 960518505 ps |
CPU time | 11.88 seconds |
Started | Jun 30 06:57:46 PM PDT 24 |
Finished | Jun 30 06:57:59 PM PDT 24 |
Peak memory | 218644 kb |
Host | smart-615be95b-1ca6-4472-ae0d-0cd0fde57dad |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1972951382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.1972951382 |
Directory | /workspace/47.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/47.lc_ctrl_jtag_access.3336595962 |
Short name | T815 |
Test name | |
Test status | |
Simulation time | 61754535 ps |
CPU time | 1.26 seconds |
Started | Jun 30 06:57:48 PM PDT 24 |
Finished | Jun 30 06:57:50 PM PDT 24 |
Peak memory | 217408 kb |
Host | smart-6817c771-165b-4af3-8068-1bae6372d544 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336595962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.3336595962 |
Directory | /workspace/47.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/47.lc_ctrl_prog_failure.1694348571 |
Short name | T807 |
Test name | |
Test status | |
Simulation time | 16401990 ps |
CPU time | 1.66 seconds |
Started | Jun 30 06:57:49 PM PDT 24 |
Finished | Jun 30 06:57:52 PM PDT 24 |
Peak memory | 218604 kb |
Host | smart-df46c0d3-ac94-4291-9fd4-56ed3fc1def6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1694348571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.1694348571 |
Directory | /workspace/47.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/47.lc_ctrl_sec_mubi.2253993886 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 1080939253 ps |
CPU time | 10.61 seconds |
Started | Jun 30 06:57:47 PM PDT 24 |
Finished | Jun 30 06:57:59 PM PDT 24 |
Peak memory | 226460 kb |
Host | smart-4ad21a0e-5d8a-42a7-8586-b432cc572d06 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253993886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.2253993886 |
Directory | /workspace/47.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/47.lc_ctrl_sec_token_digest.880782727 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 369125423 ps |
CPU time | 14.04 seconds |
Started | Jun 30 06:57:47 PM PDT 24 |
Finished | Jun 30 06:58:02 PM PDT 24 |
Peak memory | 218608 kb |
Host | smart-7eee8134-b958-429c-917a-ee56a18e8c17 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880782727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_di gest.880782727 |
Directory | /workspace/47.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/47.lc_ctrl_sec_token_mux.3548512561 |
Short name | T654 |
Test name | |
Test status | |
Simulation time | 5794419802 ps |
CPU time | 9.4 seconds |
Started | Jun 30 06:57:46 PM PDT 24 |
Finished | Jun 30 06:57:57 PM PDT 24 |
Peak memory | 226400 kb |
Host | smart-0585d329-9476-49eb-b3c0-564129772955 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548512561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux. 3548512561 |
Directory | /workspace/47.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/47.lc_ctrl_security_escalation.807810252 |
Short name | T581 |
Test name | |
Test status | |
Simulation time | 228803522 ps |
CPU time | 6.39 seconds |
Started | Jun 30 06:57:47 PM PDT 24 |
Finished | Jun 30 06:57:55 PM PDT 24 |
Peak memory | 226476 kb |
Host | smart-7475b613-892f-4a3c-bb8a-9cfed1921395 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=807810252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.807810252 |
Directory | /workspace/47.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/47.lc_ctrl_smoke.3077790986 |
Short name | T499 |
Test name | |
Test status | |
Simulation time | 35907710 ps |
CPU time | 2.62 seconds |
Started | Jun 30 06:57:50 PM PDT 24 |
Finished | Jun 30 06:57:53 PM PDT 24 |
Peak memory | 215260 kb |
Host | smart-32f7cae2-7b02-4955-b8f9-4150c667ee61 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3077790986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.3077790986 |
Directory | /workspace/47.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/47.lc_ctrl_state_failure.2762175481 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 144928649 ps |
CPU time | 22.6 seconds |
Started | Jun 30 06:57:47 PM PDT 24 |
Finished | Jun 30 06:58:11 PM PDT 24 |
Peak memory | 246800 kb |
Host | smart-41290b31-3b3b-4a5e-b55c-3f7c6c446735 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2762175481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.2762175481 |
Directory | /workspace/47.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/47.lc_ctrl_state_post_trans.2970584593 |
Short name | T325 |
Test name | |
Test status | |
Simulation time | 290482953 ps |
CPU time | 8.51 seconds |
Started | Jun 30 06:57:54 PM PDT 24 |
Finished | Jun 30 06:58:04 PM PDT 24 |
Peak memory | 251280 kb |
Host | smart-bd13b252-40df-46a3-85f5-96df0ef17c95 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2970584593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.2970584593 |
Directory | /workspace/47.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/47.lc_ctrl_stress_all.2011653437 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 11967779253 ps |
CPU time | 118.51 seconds |
Started | Jun 30 06:57:48 PM PDT 24 |
Finished | Jun 30 06:59:48 PM PDT 24 |
Peak memory | 226496 kb |
Host | smart-4b33bb27-6fec-4384-8bcf-4da5270ab8fc |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011653437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all.2011653437 |
Directory | /workspace/47.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.299254615 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 12595951103 ps |
CPU time | 264.51 seconds |
Started | Jun 30 06:57:45 PM PDT 24 |
Finished | Jun 30 07:02:11 PM PDT 24 |
Peak memory | 265524 kb |
Host | smart-41e50fe9-d69c-4e12-9590-82b255d29f72 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=299254615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all_with_rand_reset.299254615 |
Directory | /workspace/47.lc_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.825593627 |
Short name | T329 |
Test name | |
Test status | |
Simulation time | 14124019 ps |
CPU time | 0.82 seconds |
Started | Jun 30 06:57:47 PM PDT 24 |
Finished | Jun 30 06:57:49 PM PDT 24 |
Peak memory | 209156 kb |
Host | smart-68e96d7c-c65a-4f31-93fb-a3aae43d1615 |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825593627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ct rl_volatile_unlock_smoke.825593627 |
Directory | /workspace/47.lc_ctrl_volatile_unlock_smoke/latest |
Test location | /workspace/coverage/default/48.lc_ctrl_alert_test.1699852658 |
Short name | T673 |
Test name | |
Test status | |
Simulation time | 15505143 ps |
CPU time | 1.09 seconds |
Started | Jun 30 06:57:47 PM PDT 24 |
Finished | Jun 30 06:57:50 PM PDT 24 |
Peak memory | 209376 kb |
Host | smart-5710bb51-8c3f-403a-8062-8b878cb911f7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699852658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.1699852658 |
Directory | /workspace/48.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/48.lc_ctrl_errors.705604066 |
Short name | T874 |
Test name | |
Test status | |
Simulation time | 312842660 ps |
CPU time | 8.86 seconds |
Started | Jun 30 06:57:49 PM PDT 24 |
Finished | Jun 30 06:57:58 PM PDT 24 |
Peak memory | 218632 kb |
Host | smart-f2ecc91f-9435-49d6-b18c-f5a659a12812 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=705604066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.705604066 |
Directory | /workspace/48.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/48.lc_ctrl_jtag_access.3914389799 |
Short name | T669 |
Test name | |
Test status | |
Simulation time | 473274839 ps |
CPU time | 5.96 seconds |
Started | Jun 30 06:57:49 PM PDT 24 |
Finished | Jun 30 06:57:55 PM PDT 24 |
Peak memory | 217816 kb |
Host | smart-3edebb63-93dc-4153-9d0b-c17af3b3253e |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914389799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.3914389799 |
Directory | /workspace/48.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/48.lc_ctrl_prog_failure.3711901523 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 330791296 ps |
CPU time | 3.95 seconds |
Started | Jun 30 06:57:52 PM PDT 24 |
Finished | Jun 30 06:57:57 PM PDT 24 |
Peak memory | 222752 kb |
Host | smart-faf4ddd0-75b7-47d3-8659-b2a9f70eba6e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3711901523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.3711901523 |
Directory | /workspace/48.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/48.lc_ctrl_sec_mubi.1496390700 |
Short name | T833 |
Test name | |
Test status | |
Simulation time | 1008550915 ps |
CPU time | 20.2 seconds |
Started | Jun 30 06:57:48 PM PDT 24 |
Finished | Jun 30 06:58:09 PM PDT 24 |
Peak memory | 226328 kb |
Host | smart-ae6a1f7d-fe8a-4099-9698-c69264ed8647 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496390700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.1496390700 |
Directory | /workspace/48.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/48.lc_ctrl_sec_token_digest.4210315017 |
Short name | T799 |
Test name | |
Test status | |
Simulation time | 1338571204 ps |
CPU time | 9.68 seconds |
Started | Jun 30 06:57:47 PM PDT 24 |
Finished | Jun 30 06:57:58 PM PDT 24 |
Peak memory | 218512 kb |
Host | smart-b5514891-57d1-4054-8732-cbdb66987e9d |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210315017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d igest.4210315017 |
Directory | /workspace/48.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/48.lc_ctrl_sec_token_mux.1972711317 |
Short name | T614 |
Test name | |
Test status | |
Simulation time | 3697915330 ps |
CPU time | 11.73 seconds |
Started | Jun 30 06:57:48 PM PDT 24 |
Finished | Jun 30 06:58:01 PM PDT 24 |
Peak memory | 218644 kb |
Host | smart-0c84b9ba-97c9-4942-954a-1edf63a0681d |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972711317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux. 1972711317 |
Directory | /workspace/48.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/48.lc_ctrl_security_escalation.3408524877 |
Short name | T570 |
Test name | |
Test status | |
Simulation time | 912908126 ps |
CPU time | 15.34 seconds |
Started | Jun 30 06:57:45 PM PDT 24 |
Finished | Jun 30 06:58:01 PM PDT 24 |
Peak memory | 226424 kb |
Host | smart-e827d81a-0e33-433c-b337-cb8d8e08349a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3408524877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.3408524877 |
Directory | /workspace/48.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/48.lc_ctrl_smoke.3819904881 |
Short name | T850 |
Test name | |
Test status | |
Simulation time | 163970473 ps |
CPU time | 2.68 seconds |
Started | Jun 30 06:57:47 PM PDT 24 |
Finished | Jun 30 06:57:51 PM PDT 24 |
Peak memory | 214936 kb |
Host | smart-601dde23-abff-462a-82d8-6ae1174c1b1d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3819904881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.3819904881 |
Directory | /workspace/48.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/48.lc_ctrl_state_failure.177743234 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 292077122 ps |
CPU time | 29.98 seconds |
Started | Jun 30 06:57:46 PM PDT 24 |
Finished | Jun 30 06:58:17 PM PDT 24 |
Peak memory | 251348 kb |
Host | smart-2cf4c8bc-c80a-4f03-9cee-f268a22d9c1f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=177743234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.177743234 |
Directory | /workspace/48.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/48.lc_ctrl_state_post_trans.365887700 |
Short name | T553 |
Test name | |
Test status | |
Simulation time | 886707564 ps |
CPU time | 7.76 seconds |
Started | Jun 30 06:57:49 PM PDT 24 |
Finished | Jun 30 06:57:57 PM PDT 24 |
Peak memory | 247248 kb |
Host | smart-23931974-8233-42d0-a027-b4b4a7bea04c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=365887700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.365887700 |
Directory | /workspace/48.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/48.lc_ctrl_stress_all.92708035 |
Short name | T373 |
Test name | |
Test status | |
Simulation time | 31340680503 ps |
CPU time | 226.3 seconds |
Started | Jun 30 06:57:48 PM PDT 24 |
Finished | Jun 30 07:01:35 PM PDT 24 |
Peak memory | 314784 kb |
Host | smart-e42c43cd-50de-48f4-9e98-3e3eb1c39c2f |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92708035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.lc_ctrl_stress_all.92708035 |
Directory | /workspace/48.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.3312447715 |
Short name | T347 |
Test name | |
Test status | |
Simulation time | 24571431 ps |
CPU time | 0.81 seconds |
Started | Jun 30 06:57:53 PM PDT 24 |
Finished | Jun 30 06:57:55 PM PDT 24 |
Peak memory | 209152 kb |
Host | smart-ebdff19f-4877-41ff-97d8-d0076b801d95 |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312447715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c trl_volatile_unlock_smoke.3312447715 |
Directory | /workspace/48.lc_ctrl_volatile_unlock_smoke/latest |
Test location | /workspace/coverage/default/49.lc_ctrl_alert_test.3564522255 |
Short name | T332 |
Test name | |
Test status | |
Simulation time | 80084697 ps |
CPU time | 0.99 seconds |
Started | Jun 30 06:57:53 PM PDT 24 |
Finished | Jun 30 06:57:56 PM PDT 24 |
Peak memory | 209496 kb |
Host | smart-21c85c75-aa70-4336-9ee0-54758b44c069 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564522255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.3564522255 |
Directory | /workspace/49.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/49.lc_ctrl_errors.3426378511 |
Short name | T774 |
Test name | |
Test status | |
Simulation time | 3403650011 ps |
CPU time | 14.61 seconds |
Started | Jun 30 06:57:54 PM PDT 24 |
Finished | Jun 30 06:58:10 PM PDT 24 |
Peak memory | 219376 kb |
Host | smart-b95139e3-42a8-448f-9644-e6f506938079 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3426378511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.3426378511 |
Directory | /workspace/49.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/49.lc_ctrl_jtag_access.2894342185 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 1131266644 ps |
CPU time | 10.61 seconds |
Started | Jun 30 06:57:56 PM PDT 24 |
Finished | Jun 30 06:58:08 PM PDT 24 |
Peak memory | 217740 kb |
Host | smart-624434b4-c195-41c3-88d3-e0550e10b067 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894342185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.2894342185 |
Directory | /workspace/49.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/49.lc_ctrl_prog_failure.4171985179 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 130873432 ps |
CPU time | 1.88 seconds |
Started | Jun 30 06:57:55 PM PDT 24 |
Finished | Jun 30 06:57:59 PM PDT 24 |
Peak memory | 218696 kb |
Host | smart-5bb83ded-7a32-4615-9458-98bf954e5a69 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4171985179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.4171985179 |
Directory | /workspace/49.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/49.lc_ctrl_sec_mubi.158707682 |
Short name | T320 |
Test name | |
Test status | |
Simulation time | 1714210030 ps |
CPU time | 17.93 seconds |
Started | Jun 30 06:57:54 PM PDT 24 |
Finished | Jun 30 06:58:14 PM PDT 24 |
Peak memory | 226428 kb |
Host | smart-47e2205b-e97e-4435-82e8-6216bf9e462f |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158707682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.158707682 |
Directory | /workspace/49.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/49.lc_ctrl_sec_token_digest.3485255464 |
Short name | T361 |
Test name | |
Test status | |
Simulation time | 449416163 ps |
CPU time | 9.37 seconds |
Started | Jun 30 06:57:53 PM PDT 24 |
Finished | Jun 30 06:58:04 PM PDT 24 |
Peak memory | 218616 kb |
Host | smart-f22147f4-0ee5-41c8-b8c1-449b8bc70ef4 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485255464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d igest.3485255464 |
Directory | /workspace/49.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/49.lc_ctrl_sec_token_mux.1400849856 |
Short name | T766 |
Test name | |
Test status | |
Simulation time | 230774318 ps |
CPU time | 9.58 seconds |
Started | Jun 30 06:57:52 PM PDT 24 |
Finished | Jun 30 06:58:02 PM PDT 24 |
Peak memory | 218584 kb |
Host | smart-67ea9fe5-8e0d-4d1a-b4a7-037bbb265591 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400849856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux. 1400849856 |
Directory | /workspace/49.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/49.lc_ctrl_security_escalation.1455929663 |
Short name | T452 |
Test name | |
Test status | |
Simulation time | 559238905 ps |
CPU time | 7.98 seconds |
Started | Jun 30 06:57:53 PM PDT 24 |
Finished | Jun 30 06:58:03 PM PDT 24 |
Peak memory | 218608 kb |
Host | smart-6398fd93-9a34-41ae-b0d4-55104db627d4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1455929663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.1455929663 |
Directory | /workspace/49.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/49.lc_ctrl_smoke.517170138 |
Short name | T716 |
Test name | |
Test status | |
Simulation time | 55923654 ps |
CPU time | 3.14 seconds |
Started | Jun 30 06:57:50 PM PDT 24 |
Finished | Jun 30 06:57:54 PM PDT 24 |
Peak memory | 215180 kb |
Host | smart-eab453a8-64a2-4a68-9427-a8c8387680c5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=517170138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.517170138 |
Directory | /workspace/49.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/49.lc_ctrl_state_failure.2600981169 |
Short name | T507 |
Test name | |
Test status | |
Simulation time | 1053428456 ps |
CPU time | 26.14 seconds |
Started | Jun 30 06:57:55 PM PDT 24 |
Finished | Jun 30 06:58:23 PM PDT 24 |
Peak memory | 251328 kb |
Host | smart-f1752a7d-80f5-4bd8-a381-a2518f0b9bcd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2600981169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.2600981169 |
Directory | /workspace/49.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/49.lc_ctrl_state_post_trans.1639553760 |
Short name | T708 |
Test name | |
Test status | |
Simulation time | 51843950 ps |
CPU time | 6.49 seconds |
Started | Jun 30 06:57:53 PM PDT 24 |
Finished | Jun 30 06:58:01 PM PDT 24 |
Peak memory | 250832 kb |
Host | smart-5abf40bd-c9eb-41d7-b97c-9c5717d451d0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1639553760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.1639553760 |
Directory | /workspace/49.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/49.lc_ctrl_stress_all.3535155984 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 37966578766 ps |
CPU time | 258.34 seconds |
Started | Jun 30 06:57:53 PM PDT 24 |
Finished | Jun 30 07:02:13 PM PDT 24 |
Peak memory | 292324 kb |
Host | smart-e6519a04-fbf7-47f2-a19e-0bb3d505f064 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535155984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all.3535155984 |
Directory | /workspace/49.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.1902764420 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 27725947 ps |
CPU time | 0.9 seconds |
Started | Jun 30 06:57:53 PM PDT 24 |
Finished | Jun 30 06:57:55 PM PDT 24 |
Peak memory | 208364 kb |
Host | smart-0106ea7c-c52c-484a-bfb1-2c795042518f |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902764420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c trl_volatile_unlock_smoke.1902764420 |
Directory | /workspace/49.lc_ctrl_volatile_unlock_smoke/latest |
Test location | /workspace/coverage/default/5.lc_ctrl_alert_test.2616907156 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 41335663 ps |
CPU time | 1.15 seconds |
Started | Jun 30 06:55:26 PM PDT 24 |
Finished | Jun 30 06:55:28 PM PDT 24 |
Peak memory | 209336 kb |
Host | smart-a693721c-af28-45b7-b930-a6ede09a7027 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616907156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.2616907156 |
Directory | /workspace/5.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/5.lc_ctrl_claim_transition_if.3630821030 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 29614986 ps |
CPU time | 0.89 seconds |
Started | Jun 30 06:55:27 PM PDT 24 |
Finished | Jun 30 06:55:29 PM PDT 24 |
Peak memory | 209328 kb |
Host | smart-c2db6196-4d00-409b-9ae6-ad2d66db4efa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3630821030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.3630821030 |
Directory | /workspace/5.lc_ctrl_claim_transition_if/latest |
Test location | /workspace/coverage/default/5.lc_ctrl_errors.2036504092 |
Short name | T533 |
Test name | |
Test status | |
Simulation time | 1228009621 ps |
CPU time | 12.88 seconds |
Started | Jun 30 06:55:13 PM PDT 24 |
Finished | Jun 30 06:55:26 PM PDT 24 |
Peak memory | 226440 kb |
Host | smart-ece84723-40f3-4356-b7be-e2e00dfcd26b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2036504092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.2036504092 |
Directory | /workspace/5.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/5.lc_ctrl_jtag_access.3981995980 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 310866593 ps |
CPU time | 3.56 seconds |
Started | Jun 30 06:55:14 PM PDT 24 |
Finished | Jun 30 06:55:18 PM PDT 24 |
Peak memory | 217436 kb |
Host | smart-25f2b7cd-a5c4-4432-9008-1a076a750aec |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981995980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.3981995980 |
Directory | /workspace/5.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/5.lc_ctrl_jtag_errors.280771810 |
Short name | T818 |
Test name | |
Test status | |
Simulation time | 7320564844 ps |
CPU time | 38.12 seconds |
Started | Jun 30 06:55:26 PM PDT 24 |
Finished | Jun 30 06:56:06 PM PDT 24 |
Peak memory | 219368 kb |
Host | smart-9f4096ee-2f38-480b-9b15-062250bcd404 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280771810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_err ors.280771810 |
Directory | /workspace/5.lc_ctrl_jtag_errors/latest |
Test location | /workspace/coverage/default/5.lc_ctrl_jtag_priority.3859589903 |
Short name | T597 |
Test name | |
Test status | |
Simulation time | 578781169 ps |
CPU time | 4.08 seconds |
Started | Jun 30 06:55:25 PM PDT 24 |
Finished | Jun 30 06:55:30 PM PDT 24 |
Peak memory | 218088 kb |
Host | smart-0541e213-4142-4b4a-b3db-3147c913ceae |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859589903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.3 859589903 |
Directory | /workspace/5.lc_ctrl_jtag_priority/latest |
Test location | /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.3977883926 |
Short name | T762 |
Test name | |
Test status | |
Simulation time | 636650057 ps |
CPU time | 3.48 seconds |
Started | Jun 30 06:55:26 PM PDT 24 |
Finished | Jun 30 06:55:30 PM PDT 24 |
Peak memory | 218596 kb |
Host | smart-ae40c8e2-27e7-410f-ad94-9060d5656554 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977883926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag _prog_failure.3977883926 |
Directory | /workspace/5.lc_ctrl_jtag_prog_failure/latest |
Test location | /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.4200022670 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 3695427918 ps |
CPU time | 20.55 seconds |
Started | Jun 30 06:55:25 PM PDT 24 |
Finished | Jun 30 06:55:47 PM PDT 24 |
Peak memory | 218060 kb |
Host | smart-d3a8303a-75c1-45bb-b330-e520441f3a0a |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200022670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_ jtag_regwen_during_op.4200022670 |
Directory | /workspace/5.lc_ctrl_jtag_regwen_during_op/latest |
Test location | /workspace/coverage/default/5.lc_ctrl_jtag_smoke.1438616473 |
Short name | T405 |
Test name | |
Test status | |
Simulation time | 5935940005 ps |
CPU time | 6.86 seconds |
Started | Jun 30 06:55:14 PM PDT 24 |
Finished | Jun 30 06:55:21 PM PDT 24 |
Peak memory | 218032 kb |
Host | smart-d85e6c70-c7c2-402a-b621-5b21e52768f7 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438616473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke. 1438616473 |
Directory | /workspace/5.lc_ctrl_jtag_smoke/latest |
Test location | /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.3155464477 |
Short name | T476 |
Test name | |
Test status | |
Simulation time | 3912592723 ps |
CPU time | 32.55 seconds |
Started | Jun 30 06:55:26 PM PDT 24 |
Finished | Jun 30 06:56:00 PM PDT 24 |
Peak memory | 267712 kb |
Host | smart-334cbcdd-3548-41ad-82a4-0f31a31a3403 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155464477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta g_state_failure.3155464477 |
Directory | /workspace/5.lc_ctrl_jtag_state_failure/latest |
Test location | /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.2576231973 |
Short name | T835 |
Test name | |
Test status | |
Simulation time | 2280858171 ps |
CPU time | 11.27 seconds |
Started | Jun 30 06:55:24 PM PDT 24 |
Finished | Jun 30 06:55:36 PM PDT 24 |
Peak memory | 226720 kb |
Host | smart-5e6f83f3-1857-46de-8a40-bff43943bee4 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576231973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_ jtag_state_post_trans.2576231973 |
Directory | /workspace/5.lc_ctrl_jtag_state_post_trans/latest |
Test location | /workspace/coverage/default/5.lc_ctrl_prog_failure.1408476059 |
Short name | T414 |
Test name | |
Test status | |
Simulation time | 84612856 ps |
CPU time | 1.6 seconds |
Started | Jun 30 06:55:07 PM PDT 24 |
Finished | Jun 30 06:55:09 PM PDT 24 |
Peak memory | 218628 kb |
Host | smart-fe4182ea-dc2c-4302-9edd-0b3b5b5c889b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1408476059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.1408476059 |
Directory | /workspace/5.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/5.lc_ctrl_regwen_during_op.4159158731 |
Short name | T775 |
Test name | |
Test status | |
Simulation time | 287593999 ps |
CPU time | 10.23 seconds |
Started | Jun 30 06:55:24 PM PDT 24 |
Finished | Jun 30 06:55:35 PM PDT 24 |
Peak memory | 218004 kb |
Host | smart-d8027e45-9c9d-4342-9a4b-f33d55f79600 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4159158731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.4159158731 |
Directory | /workspace/5.lc_ctrl_regwen_during_op/latest |
Test location | /workspace/coverage/default/5.lc_ctrl_sec_mubi.2126282041 |
Short name | T500 |
Test name | |
Test status | |
Simulation time | 690295974 ps |
CPU time | 7.51 seconds |
Started | Jun 30 06:55:33 PM PDT 24 |
Finished | Jun 30 06:55:41 PM PDT 24 |
Peak memory | 226628 kb |
Host | smart-5944cf3d-af9d-4fcb-83b4-e75928f50a5d |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126282041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.2126282041 |
Directory | /workspace/5.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/5.lc_ctrl_sec_token_digest.1760994042 |
Short name | T404 |
Test name | |
Test status | |
Simulation time | 1421121557 ps |
CPU time | 11.86 seconds |
Started | Jun 30 06:55:27 PM PDT 24 |
Finished | Jun 30 06:55:40 PM PDT 24 |
Peak memory | 218592 kb |
Host | smart-9008338a-9873-4da6-8346-c41dd318b9a5 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760994042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di gest.1760994042 |
Directory | /workspace/5.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/5.lc_ctrl_sec_token_mux.1057473879 |
Short name | T759 |
Test name | |
Test status | |
Simulation time | 245804730 ps |
CPU time | 7.08 seconds |
Started | Jun 30 06:55:31 PM PDT 24 |
Finished | Jun 30 06:55:39 PM PDT 24 |
Peak memory | 218548 kb |
Host | smart-51cb2088-16e9-4cd3-bf3b-29c09d32c3cf |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057473879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.1 057473879 |
Directory | /workspace/5.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/5.lc_ctrl_security_escalation.2081642534 |
Short name | T439 |
Test name | |
Test status | |
Simulation time | 7853973683 ps |
CPU time | 9.92 seconds |
Started | Jun 30 06:55:25 PM PDT 24 |
Finished | Jun 30 06:55:36 PM PDT 24 |
Peak memory | 226508 kb |
Host | smart-39043fea-1571-4e80-ac95-37a8bb814d40 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2081642534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.2081642534 |
Directory | /workspace/5.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/5.lc_ctrl_smoke.3007857340 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 243593855 ps |
CPU time | 2.12 seconds |
Started | Jun 30 06:55:08 PM PDT 24 |
Finished | Jun 30 06:55:11 PM PDT 24 |
Peak memory | 214724 kb |
Host | smart-8516daf4-dd0c-4c4c-8dca-ccda5488745e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3007857340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.3007857340 |
Directory | /workspace/5.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/5.lc_ctrl_state_failure.1125350266 |
Short name | T607 |
Test name | |
Test status | |
Simulation time | 382213267 ps |
CPU time | 27.69 seconds |
Started | Jun 30 06:55:08 PM PDT 24 |
Finished | Jun 30 06:55:36 PM PDT 24 |
Peak memory | 246892 kb |
Host | smart-af5b9908-f8e9-4629-bb97-4b77b8ed4771 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1125350266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.1125350266 |
Directory | /workspace/5.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/5.lc_ctrl_state_post_trans.3369951693 |
Short name | T643 |
Test name | |
Test status | |
Simulation time | 120234273 ps |
CPU time | 7.28 seconds |
Started | Jun 30 06:55:08 PM PDT 24 |
Finished | Jun 30 06:55:16 PM PDT 24 |
Peak memory | 247252 kb |
Host | smart-9cb4b63c-8f79-457f-aa4d-07ea36853dcf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3369951693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.3369951693 |
Directory | /workspace/5.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/5.lc_ctrl_stress_all.3798141851 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 2845546098 ps |
CPU time | 128.87 seconds |
Started | Jun 30 06:55:27 PM PDT 24 |
Finished | Jun 30 06:57:37 PM PDT 24 |
Peak memory | 273396 kb |
Host | smart-cebad384-bfe8-45da-bc1f-5df256b2f536 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798141851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all.3798141851 |
Directory | /workspace/5.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.295615618 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 70986301263 ps |
CPU time | 255.4 seconds |
Started | Jun 30 06:55:14 PM PDT 24 |
Finished | Jun 30 06:59:30 PM PDT 24 |
Peak memory | 284308 kb |
Host | smart-b732027f-2361-47e7-a236-9233509721e3 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=295615618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all_with_rand_reset.295615618 |
Directory | /workspace/5.lc_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.4200533461 |
Short name | T629 |
Test name | |
Test status | |
Simulation time | 55833734 ps |
CPU time | 0.94 seconds |
Started | Jun 30 06:55:10 PM PDT 24 |
Finished | Jun 30 06:55:12 PM PDT 24 |
Peak memory | 212296 kb |
Host | smart-4e753c72-5710-4d68-93d5-cbdc3c1dec84 |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200533461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct rl_volatile_unlock_smoke.4200533461 |
Directory | /workspace/5.lc_ctrl_volatile_unlock_smoke/latest |
Test location | /workspace/coverage/default/6.lc_ctrl_alert_test.1739370729 |
Short name | T498 |
Test name | |
Test status | |
Simulation time | 19480775 ps |
CPU time | 0.91 seconds |
Started | Jun 30 06:55:26 PM PDT 24 |
Finished | Jun 30 06:55:28 PM PDT 24 |
Peak memory | 209388 kb |
Host | smart-b6828bde-6fb1-4d16-b64e-68a6367fa71a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739370729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.1739370729 |
Directory | /workspace/6.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/6.lc_ctrl_claim_transition_if.1370506350 |
Short name | T419 |
Test name | |
Test status | |
Simulation time | 12107062 ps |
CPU time | 1.01 seconds |
Started | Jun 30 06:55:28 PM PDT 24 |
Finished | Jun 30 06:55:30 PM PDT 24 |
Peak memory | 209368 kb |
Host | smart-a5c9407e-ad99-4cfa-b3f3-6bc853ff9cc7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1370506350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.1370506350 |
Directory | /workspace/6.lc_ctrl_claim_transition_if/latest |
Test location | /workspace/coverage/default/6.lc_ctrl_errors.1620279003 |
Short name | T779 |
Test name | |
Test status | |
Simulation time | 1549519090 ps |
CPU time | 11.5 seconds |
Started | Jun 30 06:55:33 PM PDT 24 |
Finished | Jun 30 06:55:45 PM PDT 24 |
Peak memory | 218644 kb |
Host | smart-948e6fe0-7507-40a7-983b-35b5a9c0d979 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1620279003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.1620279003 |
Directory | /workspace/6.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/6.lc_ctrl_jtag_access.933464183 |
Short name | T377 |
Test name | |
Test status | |
Simulation time | 572153403 ps |
CPU time | 8.28 seconds |
Started | Jun 30 06:55:29 PM PDT 24 |
Finished | Jun 30 06:55:38 PM PDT 24 |
Peak memory | 217956 kb |
Host | smart-b414fe0f-c25c-49b0-ad93-ec134ce7464e |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933464183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.933464183 |
Directory | /workspace/6.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/6.lc_ctrl_jtag_errors.1991113798 |
Short name | T415 |
Test name | |
Test status | |
Simulation time | 2627867139 ps |
CPU time | 73.52 seconds |
Started | Jun 30 06:55:30 PM PDT 24 |
Finished | Jun 30 06:56:44 PM PDT 24 |
Peak memory | 219524 kb |
Host | smart-a343ffd9-dfb2-48e8-b612-35c0466c89f9 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991113798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er rors.1991113798 |
Directory | /workspace/6.lc_ctrl_jtag_errors/latest |
Test location | /workspace/coverage/default/6.lc_ctrl_jtag_priority.3749103712 |
Short name | T505 |
Test name | |
Test status | |
Simulation time | 399586445 ps |
CPU time | 4.9 seconds |
Started | Jun 30 06:55:31 PM PDT 24 |
Finished | Jun 30 06:55:37 PM PDT 24 |
Peak memory | 218044 kb |
Host | smart-e7eead62-ff3b-47e9-9baf-1f64799dcdbb |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749103712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.3 749103712 |
Directory | /workspace/6.lc_ctrl_jtag_priority/latest |
Test location | /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.3774533444 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 1948899815 ps |
CPU time | 8.82 seconds |
Started | Jun 30 06:55:28 PM PDT 24 |
Finished | Jun 30 06:55:37 PM PDT 24 |
Peak memory | 218560 kb |
Host | smart-4e19b119-e86f-4169-ab9a-230e51dfea61 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774533444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag _prog_failure.3774533444 |
Directory | /workspace/6.lc_ctrl_jtag_prog_failure/latest |
Test location | /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.1989972211 |
Short name | T871 |
Test name | |
Test status | |
Simulation time | 2136222396 ps |
CPU time | 30.33 seconds |
Started | Jun 30 06:55:25 PM PDT 24 |
Finished | Jun 30 06:55:56 PM PDT 24 |
Peak memory | 217900 kb |
Host | smart-2525cad7-72a5-4e94-9268-dc6366d0df24 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989972211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_ jtag_regwen_during_op.1989972211 |
Directory | /workspace/6.lc_ctrl_jtag_regwen_during_op/latest |
Test location | /workspace/coverage/default/6.lc_ctrl_jtag_smoke.4247928022 |
Short name | T364 |
Test name | |
Test status | |
Simulation time | 247476727 ps |
CPU time | 8.04 seconds |
Started | Jun 30 06:55:32 PM PDT 24 |
Finished | Jun 30 06:55:41 PM PDT 24 |
Peak memory | 217988 kb |
Host | smart-89b0d522-e495-4cfe-a723-d5f7c15973fc |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247928022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke. 4247928022 |
Directory | /workspace/6.lc_ctrl_jtag_smoke/latest |
Test location | /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.2059851776 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 1131679113 ps |
CPU time | 45.85 seconds |
Started | Jun 30 06:55:27 PM PDT 24 |
Finished | Jun 30 06:56:14 PM PDT 24 |
Peak memory | 251268 kb |
Host | smart-01a1ce6e-2035-454a-9923-28a2db985ebe |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059851776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta g_state_failure.2059851776 |
Directory | /workspace/6.lc_ctrl_jtag_state_failure/latest |
Test location | /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.3682953829 |
Short name | T368 |
Test name | |
Test status | |
Simulation time | 475922994 ps |
CPU time | 19.21 seconds |
Started | Jun 30 06:55:25 PM PDT 24 |
Finished | Jun 30 06:55:45 PM PDT 24 |
Peak memory | 250868 kb |
Host | smart-4a501077-48ba-4fc5-99a7-c3c25e887062 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682953829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_ jtag_state_post_trans.3682953829 |
Directory | /workspace/6.lc_ctrl_jtag_state_post_trans/latest |
Test location | /workspace/coverage/default/6.lc_ctrl_prog_failure.4100564356 |
Short name | T283 |
Test name | |
Test status | |
Simulation time | 202117396 ps |
CPU time | 1.62 seconds |
Started | Jun 30 06:55:30 PM PDT 24 |
Finished | Jun 30 06:55:32 PM PDT 24 |
Peak memory | 218612 kb |
Host | smart-97f134d4-7232-403e-83b9-4359e5bdba3a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4100564356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.4100564356 |
Directory | /workspace/6.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/6.lc_ctrl_regwen_during_op.4252999675 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 1550671065 ps |
CPU time | 15.8 seconds |
Started | Jun 30 06:55:32 PM PDT 24 |
Finished | Jun 30 06:55:49 PM PDT 24 |
Peak memory | 218156 kb |
Host | smart-1f9bff99-ab78-4d71-9424-16b7f913af46 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4252999675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.4252999675 |
Directory | /workspace/6.lc_ctrl_regwen_during_op/latest |
Test location | /workspace/coverage/default/6.lc_ctrl_sec_mubi.934468551 |
Short name | T727 |
Test name | |
Test status | |
Simulation time | 1020928608 ps |
CPU time | 12.42 seconds |
Started | Jun 30 06:55:25 PM PDT 24 |
Finished | Jun 30 06:55:38 PM PDT 24 |
Peak memory | 218636 kb |
Host | smart-9a49b2d6-4ac6-49a7-8e53-0e28508fed33 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934468551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.934468551 |
Directory | /workspace/6.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/6.lc_ctrl_sec_token_digest.3148712191 |
Short name | T394 |
Test name | |
Test status | |
Simulation time | 1089989463 ps |
CPU time | 10.61 seconds |
Started | Jun 30 06:55:30 PM PDT 24 |
Finished | Jun 30 06:55:41 PM PDT 24 |
Peak memory | 218648 kb |
Host | smart-a7fd1df7-089c-4ff8-ba68-1999a74e78a3 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148712191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di gest.3148712191 |
Directory | /workspace/6.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/6.lc_ctrl_sec_token_mux.3057387627 |
Short name | T330 |
Test name | |
Test status | |
Simulation time | 1422085899 ps |
CPU time | 7.72 seconds |
Started | Jun 30 06:55:29 PM PDT 24 |
Finished | Jun 30 06:55:38 PM PDT 24 |
Peak memory | 218536 kb |
Host | smart-9f44dc73-171c-4aa7-b7c5-6a11f39b4174 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057387627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.3 057387627 |
Directory | /workspace/6.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/6.lc_ctrl_security_escalation.1235305257 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 1556379266 ps |
CPU time | 8.42 seconds |
Started | Jun 30 06:55:24 PM PDT 24 |
Finished | Jun 30 06:55:33 PM PDT 24 |
Peak memory | 226320 kb |
Host | smart-57ff50cf-83f9-4fdc-a590-9d279bbf1547 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1235305257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.1235305257 |
Directory | /workspace/6.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/6.lc_ctrl_smoke.3768379252 |
Short name | T792 |
Test name | |
Test status | |
Simulation time | 77969427 ps |
CPU time | 4.7 seconds |
Started | Jun 30 06:55:28 PM PDT 24 |
Finished | Jun 30 06:55:33 PM PDT 24 |
Peak memory | 218136 kb |
Host | smart-bf4ce2cd-f2d1-4ccd-abe4-646ef5a1cd63 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3768379252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.3768379252 |
Directory | /workspace/6.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/6.lc_ctrl_state_failure.2303684714 |
Short name | T351 |
Test name | |
Test status | |
Simulation time | 481024743 ps |
CPU time | 24.15 seconds |
Started | Jun 30 06:55:26 PM PDT 24 |
Finished | Jun 30 06:55:51 PM PDT 24 |
Peak memory | 251328 kb |
Host | smart-4a03ab60-1ea7-40ca-8b28-1c5c85619b34 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2303684714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.2303684714 |
Directory | /workspace/6.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/6.lc_ctrl_state_post_trans.1441752549 |
Short name | T544 |
Test name | |
Test status | |
Simulation time | 159467609 ps |
CPU time | 7.43 seconds |
Started | Jun 30 06:55:25 PM PDT 24 |
Finished | Jun 30 06:55:33 PM PDT 24 |
Peak memory | 250932 kb |
Host | smart-21f95f1b-d527-45c7-b374-32ebff0e5857 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1441752549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.1441752549 |
Directory | /workspace/6.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/6.lc_ctrl_stress_all.4229785773 |
Short name | T453 |
Test name | |
Test status | |
Simulation time | 13416727526 ps |
CPU time | 131.53 seconds |
Started | Jun 30 06:55:26 PM PDT 24 |
Finished | Jun 30 06:57:39 PM PDT 24 |
Peak memory | 276696 kb |
Host | smart-7d1028fb-0a9f-4bd0-9dd4-14683f16a6cd |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229785773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all.4229785773 |
Directory | /workspace/6.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.1430354018 |
Short name | T474 |
Test name | |
Test status | |
Simulation time | 15456046 ps |
CPU time | 0.98 seconds |
Started | Jun 30 06:55:33 PM PDT 24 |
Finished | Jun 30 06:55:35 PM PDT 24 |
Peak memory | 212288 kb |
Host | smart-ca759664-66da-421a-a426-c0864f6beef8 |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430354018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct rl_volatile_unlock_smoke.1430354018 |
Directory | /workspace/6.lc_ctrl_volatile_unlock_smoke/latest |
Test location | /workspace/coverage/default/7.lc_ctrl_alert_test.2829724603 |
Short name | T517 |
Test name | |
Test status | |
Simulation time | 109558234 ps |
CPU time | 1.07 seconds |
Started | Jun 30 06:55:32 PM PDT 24 |
Finished | Jun 30 06:55:34 PM PDT 24 |
Peak memory | 209376 kb |
Host | smart-b8e0c3f6-bf7f-4551-b62e-1a37ee02e35f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829724603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.2829724603 |
Directory | /workspace/7.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/7.lc_ctrl_claim_transition_if.520726611 |
Short name | T444 |
Test name | |
Test status | |
Simulation time | 11050232 ps |
CPU time | 0.94 seconds |
Started | Jun 30 06:55:27 PM PDT 24 |
Finished | Jun 30 06:55:29 PM PDT 24 |
Peak memory | 209356 kb |
Host | smart-de403f1c-4535-4f5b-8e5b-e8297cad1381 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=520726611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.520726611 |
Directory | /workspace/7.lc_ctrl_claim_transition_if/latest |
Test location | /workspace/coverage/default/7.lc_ctrl_errors.3678891703 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 1498489481 ps |
CPU time | 11.29 seconds |
Started | Jun 30 06:55:26 PM PDT 24 |
Finished | Jun 30 06:55:38 PM PDT 24 |
Peak memory | 218656 kb |
Host | smart-1eb52471-f12a-4be7-9028-1f77f1d352bf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3678891703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.3678891703 |
Directory | /workspace/7.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/7.lc_ctrl_jtag_access.600992225 |
Short name | T720 |
Test name | |
Test status | |
Simulation time | 399539158 ps |
CPU time | 3.03 seconds |
Started | Jun 30 06:55:29 PM PDT 24 |
Finished | Jun 30 06:55:33 PM PDT 24 |
Peak memory | 217336 kb |
Host | smart-45e5ae1b-f9a7-4056-9f84-2620656fa68b |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600992225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.600992225 |
Directory | /workspace/7.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/7.lc_ctrl_jtag_errors.3268059118 |
Short name | T797 |
Test name | |
Test status | |
Simulation time | 2396456855 ps |
CPU time | 44.39 seconds |
Started | Jun 30 06:55:28 PM PDT 24 |
Finished | Jun 30 06:56:13 PM PDT 24 |
Peak memory | 219268 kb |
Host | smart-d1eacf69-df43-49b9-9769-87363daa42d0 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268059118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er rors.3268059118 |
Directory | /workspace/7.lc_ctrl_jtag_errors/latest |
Test location | /workspace/coverage/default/7.lc_ctrl_jtag_priority.713600325 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 273427726 ps |
CPU time | 7.52 seconds |
Started | Jun 30 06:55:33 PM PDT 24 |
Finished | Jun 30 06:55:42 PM PDT 24 |
Peak memory | 218212 kb |
Host | smart-c5e2d1b3-8696-4f51-9b34-3a39cfe38531 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713600325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.713600325 |
Directory | /workspace/7.lc_ctrl_jtag_priority/latest |
Test location | /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.4032425164 |
Short name | T627 |
Test name | |
Test status | |
Simulation time | 939896047 ps |
CPU time | 9.49 seconds |
Started | Jun 30 06:55:25 PM PDT 24 |
Finished | Jun 30 06:55:36 PM PDT 24 |
Peak memory | 218568 kb |
Host | smart-eb8d7f13-4f64-476e-8d0c-672d5f2bde39 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032425164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag _prog_failure.4032425164 |
Directory | /workspace/7.lc_ctrl_jtag_prog_failure/latest |
Test location | /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.4060784351 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 3610548489 ps |
CPU time | 24.85 seconds |
Started | Jun 30 06:55:25 PM PDT 24 |
Finished | Jun 30 06:55:51 PM PDT 24 |
Peak memory | 218048 kb |
Host | smart-0f8f492c-f72b-4269-a1e4-ea852f0b11d4 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060784351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_ jtag_regwen_during_op.4060784351 |
Directory | /workspace/7.lc_ctrl_jtag_regwen_during_op/latest |
Test location | /workspace/coverage/default/7.lc_ctrl_jtag_smoke.1019657132 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 149020297 ps |
CPU time | 2.33 seconds |
Started | Jun 30 06:55:27 PM PDT 24 |
Finished | Jun 30 06:55:30 PM PDT 24 |
Peak memory | 217980 kb |
Host | smart-d0f38229-aa22-4536-bb18-ac072e4f085c |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019657132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke. 1019657132 |
Directory | /workspace/7.lc_ctrl_jtag_smoke/latest |
Test location | /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.2560953284 |
Short name | T756 |
Test name | |
Test status | |
Simulation time | 10560280765 ps |
CPU time | 46.87 seconds |
Started | Jun 30 06:55:28 PM PDT 24 |
Finished | Jun 30 06:56:16 PM PDT 24 |
Peak memory | 251764 kb |
Host | smart-130b5d95-03b6-4cdb-8a50-1c9944db2740 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560953284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta g_state_failure.2560953284 |
Directory | /workspace/7.lc_ctrl_jtag_state_failure/latest |
Test location | /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.28773081 |
Short name | T688 |
Test name | |
Test status | |
Simulation time | 773902831 ps |
CPU time | 25.92 seconds |
Started | Jun 30 06:55:27 PM PDT 24 |
Finished | Jun 30 06:55:54 PM PDT 24 |
Peak memory | 249004 kb |
Host | smart-bfa6eda9-80e0-41b6-ae82-0ee501f593d9 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28773081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s tate_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jt ag_state_post_trans.28773081 |
Directory | /workspace/7.lc_ctrl_jtag_state_post_trans/latest |
Test location | /workspace/coverage/default/7.lc_ctrl_prog_failure.1299873973 |
Short name | T585 |
Test name | |
Test status | |
Simulation time | 78337977 ps |
CPU time | 1.62 seconds |
Started | Jun 30 06:55:33 PM PDT 24 |
Finished | Jun 30 06:55:35 PM PDT 24 |
Peak memory | 222408 kb |
Host | smart-eb93fd78-13ca-4f0c-a9e2-940853fc5163 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1299873973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.1299873973 |
Directory | /workspace/7.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/7.lc_ctrl_regwen_during_op.2749611591 |
Short name | T342 |
Test name | |
Test status | |
Simulation time | 366613376 ps |
CPU time | 9.93 seconds |
Started | Jun 30 06:55:27 PM PDT 24 |
Finished | Jun 30 06:55:38 PM PDT 24 |
Peak memory | 218068 kb |
Host | smart-80c89bd1-e6ea-4ecf-a0fb-223ad52fbf5d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2749611591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.2749611591 |
Directory | /workspace/7.lc_ctrl_regwen_during_op/latest |
Test location | /workspace/coverage/default/7.lc_ctrl_sec_mubi.357513590 |
Short name | T794 |
Test name | |
Test status | |
Simulation time | 944746135 ps |
CPU time | 12.97 seconds |
Started | Jun 30 06:55:28 PM PDT 24 |
Finished | Jun 30 06:55:42 PM PDT 24 |
Peak memory | 218608 kb |
Host | smart-71fed89b-8d42-4ec4-a7a9-26aaa3b0d832 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357513590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.357513590 |
Directory | /workspace/7.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/7.lc_ctrl_sec_token_digest.3175316291 |
Short name | T718 |
Test name | |
Test status | |
Simulation time | 1326398937 ps |
CPU time | 13.98 seconds |
Started | Jun 30 06:55:28 PM PDT 24 |
Finished | Jun 30 06:55:43 PM PDT 24 |
Peak memory | 218612 kb |
Host | smart-6e1a8395-3c6b-4194-b026-134b8b4b34f4 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175316291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di gest.3175316291 |
Directory | /workspace/7.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/7.lc_ctrl_sec_token_mux.428118731 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 263230749 ps |
CPU time | 6.88 seconds |
Started | Jun 30 06:55:29 PM PDT 24 |
Finished | Jun 30 06:55:36 PM PDT 24 |
Peak memory | 218592 kb |
Host | smart-a8e6a5aa-3f92-4c59-9765-cdd269f26f8e |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428118731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.428118731 |
Directory | /workspace/7.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/7.lc_ctrl_security_escalation.1209255779 |
Short name | T865 |
Test name | |
Test status | |
Simulation time | 968490714 ps |
CPU time | 10.96 seconds |
Started | Jun 30 06:55:27 PM PDT 24 |
Finished | Jun 30 06:55:39 PM PDT 24 |
Peak memory | 226456 kb |
Host | smart-4482b0f8-17fd-4a4f-9818-04a02d1fcb10 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1209255779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.1209255779 |
Directory | /workspace/7.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/7.lc_ctrl_smoke.34080928 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 77364271 ps |
CPU time | 1.69 seconds |
Started | Jun 30 06:55:28 PM PDT 24 |
Finished | Jun 30 06:55:30 PM PDT 24 |
Peak memory | 218068 kb |
Host | smart-ad27ce16-c786-4391-b901-c5e830b45f58 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=34080928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.34080928 |
Directory | /workspace/7.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/7.lc_ctrl_state_failure.812201886 |
Short name | T616 |
Test name | |
Test status | |
Simulation time | 319192925 ps |
CPU time | 24.09 seconds |
Started | Jun 30 06:55:31 PM PDT 24 |
Finished | Jun 30 06:55:56 PM PDT 24 |
Peak memory | 251332 kb |
Host | smart-e99223a0-f2f5-4ad5-827a-d8616a3a4d67 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=812201886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.812201886 |
Directory | /workspace/7.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/7.lc_ctrl_state_post_trans.2516765723 |
Short name | T623 |
Test name | |
Test status | |
Simulation time | 93313136 ps |
CPU time | 5.96 seconds |
Started | Jun 30 06:55:29 PM PDT 24 |
Finished | Jun 30 06:55:36 PM PDT 24 |
Peak memory | 242984 kb |
Host | smart-bb4ebb7c-e20f-44c3-bfb1-b0913304bdf3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2516765723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.2516765723 |
Directory | /workspace/7.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1455112450 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 47075758 ps |
CPU time | 0.85 seconds |
Started | Jun 30 06:55:32 PM PDT 24 |
Finished | Jun 30 06:55:34 PM PDT 24 |
Peak memory | 209620 kb |
Host | smart-80b0fea6-baaf-45cd-a175-992944184ec3 |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455112450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct rl_volatile_unlock_smoke.1455112450 |
Directory | /workspace/7.lc_ctrl_volatile_unlock_smoke/latest |
Test location | /workspace/coverage/default/8.lc_ctrl_alert_test.1375925000 |
Short name | T310 |
Test name | |
Test status | |
Simulation time | 122805821 ps |
CPU time | 1.34 seconds |
Started | Jun 30 06:55:34 PM PDT 24 |
Finished | Jun 30 06:55:37 PM PDT 24 |
Peak memory | 209384 kb |
Host | smart-feb0e3e7-fbff-4cc0-8f94-5743be604b2c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375925000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.1375925000 |
Directory | /workspace/8.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/8.lc_ctrl_claim_transition_if.3502649961 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 30596737 ps |
CPU time | 0.78 seconds |
Started | Jun 30 06:55:35 PM PDT 24 |
Finished | Jun 30 06:55:37 PM PDT 24 |
Peak memory | 209356 kb |
Host | smart-e9421912-949f-45ff-82fe-3dc39ac77a07 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3502649961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.3502649961 |
Directory | /workspace/8.lc_ctrl_claim_transition_if/latest |
Test location | /workspace/coverage/default/8.lc_ctrl_errors.3733744966 |
Short name | T502 |
Test name | |
Test status | |
Simulation time | 2251477457 ps |
CPU time | 17.1 seconds |
Started | Jun 30 06:55:30 PM PDT 24 |
Finished | Jun 30 06:55:48 PM PDT 24 |
Peak memory | 218668 kb |
Host | smart-079ec625-69b4-4f08-8963-31dcd9fb7a28 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3733744966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.3733744966 |
Directory | /workspace/8.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/8.lc_ctrl_jtag_access.3353260219 |
Short name | T701 |
Test name | |
Test status | |
Simulation time | 655192523 ps |
CPU time | 4.46 seconds |
Started | Jun 30 06:55:33 PM PDT 24 |
Finished | Jun 30 06:55:38 PM PDT 24 |
Peak memory | 217528 kb |
Host | smart-7e9fd9f9-5d89-4cda-8b07-f8e3f074daec |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353260219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.3353260219 |
Directory | /workspace/8.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/8.lc_ctrl_jtag_errors.2243426739 |
Short name | T829 |
Test name | |
Test status | |
Simulation time | 8257349209 ps |
CPU time | 105.1 seconds |
Started | Jun 30 06:55:33 PM PDT 24 |
Finished | Jun 30 06:57:20 PM PDT 24 |
Peak memory | 225236 kb |
Host | smart-ab18e77c-3b59-4d3d-9016-c01c0d9e8933 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243426739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er rors.2243426739 |
Directory | /workspace/8.lc_ctrl_jtag_errors/latest |
Test location | /workspace/coverage/default/8.lc_ctrl_jtag_priority.1233105152 |
Short name | T639 |
Test name | |
Test status | |
Simulation time | 4348423501 ps |
CPU time | 10.14 seconds |
Started | Jun 30 06:55:33 PM PDT 24 |
Finished | Jun 30 06:55:44 PM PDT 24 |
Peak memory | 216904 kb |
Host | smart-e15ae036-6312-43e3-9848-362e77a8bb14 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233105152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.1 233105152 |
Directory | /workspace/8.lc_ctrl_jtag_priority/latest |
Test location | /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.1955843419 |
Short name | T685 |
Test name | |
Test status | |
Simulation time | 1300067370 ps |
CPU time | 16.92 seconds |
Started | Jun 30 06:55:33 PM PDT 24 |
Finished | Jun 30 06:55:51 PM PDT 24 |
Peak memory | 218568 kb |
Host | smart-4964702b-fdad-4b41-8043-dbb632e4b8e8 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955843419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag _prog_failure.1955843419 |
Directory | /workspace/8.lc_ctrl_jtag_prog_failure/latest |
Test location | /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.3630940664 |
Short name | T748 |
Test name | |
Test status | |
Simulation time | 3729763031 ps |
CPU time | 24.28 seconds |
Started | Jun 30 06:55:35 PM PDT 24 |
Finished | Jun 30 06:56:01 PM PDT 24 |
Peak memory | 218056 kb |
Host | smart-328ddd4f-bf14-4c7c-9201-9e5d174a621d |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630940664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_ jtag_regwen_during_op.3630940664 |
Directory | /workspace/8.lc_ctrl_jtag_regwen_during_op/latest |
Test location | /workspace/coverage/default/8.lc_ctrl_jtag_smoke.3340904290 |
Short name | T578 |
Test name | |
Test status | |
Simulation time | 1071800544 ps |
CPU time | 5.06 seconds |
Started | Jun 30 06:55:33 PM PDT 24 |
Finished | Jun 30 06:55:39 PM PDT 24 |
Peak memory | 217952 kb |
Host | smart-c3a7fde1-9817-4dc4-bafe-a6c81ee55974 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340904290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke. 3340904290 |
Directory | /workspace/8.lc_ctrl_jtag_smoke/latest |
Test location | /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.829755698 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 1302636861 ps |
CPU time | 60.86 seconds |
Started | Jun 30 06:55:32 PM PDT 24 |
Finished | Jun 30 06:56:33 PM PDT 24 |
Peak memory | 251456 kb |
Host | smart-98c2cb3a-35f4-4edc-be60-29080467df7d |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829755698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag _state_failure.829755698 |
Directory | /workspace/8.lc_ctrl_jtag_state_failure/latest |
Test location | /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.1218805759 |
Short name | T574 |
Test name | |
Test status | |
Simulation time | 705405443 ps |
CPU time | 16.48 seconds |
Started | Jun 30 06:55:31 PM PDT 24 |
Finished | Jun 30 06:55:49 PM PDT 24 |
Peak memory | 251232 kb |
Host | smart-0f97731b-daf8-4b96-808a-991dc7ebe6d1 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218805759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_ jtag_state_post_trans.1218805759 |
Directory | /workspace/8.lc_ctrl_jtag_state_post_trans/latest |
Test location | /workspace/coverage/default/8.lc_ctrl_prog_failure.3053112562 |
Short name | T398 |
Test name | |
Test status | |
Simulation time | 53815203 ps |
CPU time | 2.43 seconds |
Started | Jun 30 06:55:31 PM PDT 24 |
Finished | Jun 30 06:55:34 PM PDT 24 |
Peak memory | 218628 kb |
Host | smart-7fe6d0cb-4bf8-4120-918f-74a06cf6da82 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3053112562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.3053112562 |
Directory | /workspace/8.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/8.lc_ctrl_regwen_during_op.1791408268 |
Short name | T655 |
Test name | |
Test status | |
Simulation time | 1015602992 ps |
CPU time | 10.4 seconds |
Started | Jun 30 06:55:35 PM PDT 24 |
Finished | Jun 30 06:55:46 PM PDT 24 |
Peak memory | 215212 kb |
Host | smart-0133beba-0002-43ba-a04b-4997fe2c17e6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1791408268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.1791408268 |
Directory | /workspace/8.lc_ctrl_regwen_during_op/latest |
Test location | /workspace/coverage/default/8.lc_ctrl_sec_mubi.1731792219 |
Short name | T461 |
Test name | |
Test status | |
Simulation time | 317322501 ps |
CPU time | 13.82 seconds |
Started | Jun 30 06:55:34 PM PDT 24 |
Finished | Jun 30 06:55:48 PM PDT 24 |
Peak memory | 219976 kb |
Host | smart-6c837341-e558-4e5a-b93d-c6c197b2eabc |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731792219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.1731792219 |
Directory | /workspace/8.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/8.lc_ctrl_sec_token_digest.2459573510 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 2765620274 ps |
CPU time | 22.04 seconds |
Started | Jun 30 06:55:36 PM PDT 24 |
Finished | Jun 30 06:55:59 PM PDT 24 |
Peak memory | 218632 kb |
Host | smart-76940d60-0e87-4a97-9046-0643c1076bbb |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459573510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di gest.2459573510 |
Directory | /workspace/8.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/8.lc_ctrl_sec_token_mux.3968878048 |
Short name | T356 |
Test name | |
Test status | |
Simulation time | 481369407 ps |
CPU time | 7.53 seconds |
Started | Jun 30 06:55:35 PM PDT 24 |
Finished | Jun 30 06:55:44 PM PDT 24 |
Peak memory | 226380 kb |
Host | smart-bde6c1c4-53bb-4016-9502-71caea808669 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968878048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.3 968878048 |
Directory | /workspace/8.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/8.lc_ctrl_security_escalation.3007244800 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 307995700 ps |
CPU time | 12.17 seconds |
Started | Jun 30 06:55:30 PM PDT 24 |
Finished | Jun 30 06:55:43 PM PDT 24 |
Peak memory | 226456 kb |
Host | smart-788d8c78-1694-4f73-8e2a-0ba2ee07d338 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3007244800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.3007244800 |
Directory | /workspace/8.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/8.lc_ctrl_smoke.834509409 |
Short name | T530 |
Test name | |
Test status | |
Simulation time | 100764210 ps |
CPU time | 2.88 seconds |
Started | Jun 30 06:55:24 PM PDT 24 |
Finished | Jun 30 06:55:28 PM PDT 24 |
Peak memory | 215380 kb |
Host | smart-65d2d06d-9a64-4982-94e4-a58dd6808cef |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=834509409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.834509409 |
Directory | /workspace/8.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/8.lc_ctrl_state_failure.3098256648 |
Short name | T550 |
Test name | |
Test status | |
Simulation time | 670680982 ps |
CPU time | 19.33 seconds |
Started | Jun 30 06:55:32 PM PDT 24 |
Finished | Jun 30 06:55:52 PM PDT 24 |
Peak memory | 251276 kb |
Host | smart-d0fd6195-720d-4e8a-a0ce-96bf2cf50739 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3098256648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.3098256648 |
Directory | /workspace/8.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/8.lc_ctrl_state_post_trans.4184601219 |
Short name | T808 |
Test name | |
Test status | |
Simulation time | 170706435 ps |
CPU time | 3.05 seconds |
Started | Jun 30 06:55:35 PM PDT 24 |
Finished | Jun 30 06:55:39 PM PDT 24 |
Peak memory | 226748 kb |
Host | smart-2951476f-900e-4491-9eb8-882942209dfe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4184601219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.4184601219 |
Directory | /workspace/8.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/8.lc_ctrl_stress_all.1305177336 |
Short name | T456 |
Test name | |
Test status | |
Simulation time | 29274940971 ps |
CPU time | 223.86 seconds |
Started | Jun 30 06:55:34 PM PDT 24 |
Finished | Jun 30 06:59:19 PM PDT 24 |
Peak memory | 251132 kb |
Host | smart-8731032d-8dd9-4976-9dff-03cc996eb368 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305177336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all.1305177336 |
Directory | /workspace/8.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/9.lc_ctrl_alert_test.3223403435 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 75915924 ps |
CPU time | 0.84 seconds |
Started | Jun 30 06:55:39 PM PDT 24 |
Finished | Jun 30 06:55:42 PM PDT 24 |
Peak memory | 209372 kb |
Host | smart-9348507c-92a2-4337-8788-39a0982842fd |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223403435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.3223403435 |
Directory | /workspace/9.lc_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/9.lc_ctrl_errors.2133668683 |
Short name | T804 |
Test name | |
Test status | |
Simulation time | 262651113 ps |
CPU time | 11.86 seconds |
Started | Jun 30 06:55:37 PM PDT 24 |
Finished | Jun 30 06:55:50 PM PDT 24 |
Peak memory | 226436 kb |
Host | smart-6a21f14e-65ba-4367-b416-ce1b34c3854f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2133668683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.2133668683 |
Directory | /workspace/9.lc_ctrl_errors/latest |
Test location | /workspace/coverage/default/9.lc_ctrl_jtag_access.2806819923 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 396827467 ps |
CPU time | 6.6 seconds |
Started | Jun 30 06:55:37 PM PDT 24 |
Finished | Jun 30 06:55:46 PM PDT 24 |
Peak memory | 217880 kb |
Host | smart-01ca06c5-ac77-4c81-9fac-b2bb2abfd631 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806819923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.2806819923 |
Directory | /workspace/9.lc_ctrl_jtag_access/latest |
Test location | /workspace/coverage/default/9.lc_ctrl_jtag_errors.3287332934 |
Short name | T568 |
Test name | |
Test status | |
Simulation time | 1130015026 ps |
CPU time | 35.79 seconds |
Started | Jun 30 06:55:38 PM PDT 24 |
Finished | Jun 30 06:56:16 PM PDT 24 |
Peak memory | 226440 kb |
Host | smart-5e707681-959f-4c34-bc72-79bf2a45b7fd |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287332934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er rors.3287332934 |
Directory | /workspace/9.lc_ctrl_jtag_errors/latest |
Test location | /workspace/coverage/default/9.lc_ctrl_jtag_priority.3361890917 |
Short name | T477 |
Test name | |
Test status | |
Simulation time | 646741589 ps |
CPU time | 6.31 seconds |
Started | Jun 30 06:55:36 PM PDT 24 |
Finished | Jun 30 06:55:44 PM PDT 24 |
Peak memory | 217740 kb |
Host | smart-143f244f-c1b2-46b2-8cc4-853778663f7d |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361890917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.3 361890917 |
Directory | /workspace/9.lc_ctrl_jtag_priority/latest |
Test location | /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.1326512086 |
Short name | T812 |
Test name | |
Test status | |
Simulation time | 2031588559 ps |
CPU time | 7.32 seconds |
Started | Jun 30 06:55:36 PM PDT 24 |
Finished | Jun 30 06:55:45 PM PDT 24 |
Peak memory | 223524 kb |
Host | smart-61012d2a-2968-4a0a-a72d-9d334322c6cb |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326512086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag _prog_failure.1326512086 |
Directory | /workspace/9.lc_ctrl_jtag_prog_failure/latest |
Test location | /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.734891363 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 690203219 ps |
CPU time | 21.13 seconds |
Started | Jun 30 06:55:38 PM PDT 24 |
Finished | Jun 30 06:56:02 PM PDT 24 |
Peak memory | 217984 kb |
Host | smart-37be4ed3-eaac-449c-af6d-cfa9009285f4 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734891363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j tag_regwen_during_op.734891363 |
Directory | /workspace/9.lc_ctrl_jtag_regwen_during_op/latest |
Test location | /workspace/coverage/default/9.lc_ctrl_jtag_smoke.2410094665 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 497359001 ps |
CPU time | 2.2 seconds |
Started | Jun 30 06:55:36 PM PDT 24 |
Finished | Jun 30 06:55:40 PM PDT 24 |
Peak memory | 217936 kb |
Host | smart-394f1aa7-b4d8-4a1d-944f-6611803d996f |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410094665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke. 2410094665 |
Directory | /workspace/9.lc_ctrl_jtag_smoke/latest |
Test location | /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.3574249109 |
Short name | T290 |
Test name | |
Test status | |
Simulation time | 1127904855 ps |
CPU time | 37.22 seconds |
Started | Jun 30 06:55:36 PM PDT 24 |
Finished | Jun 30 06:56:15 PM PDT 24 |
Peak memory | 275756 kb |
Host | smart-0db4179a-acaa-4a11-a9fb-16080ec75416 |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574249109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta g_state_failure.3574249109 |
Directory | /workspace/9.lc_ctrl_jtag_state_failure/latest |
Test location | /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.3590948558 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 532159131 ps |
CPU time | 9.47 seconds |
Started | Jun 30 06:55:37 PM PDT 24 |
Finished | Jun 30 06:55:49 PM PDT 24 |
Peak memory | 226664 kb |
Host | smart-ebe04625-14c6-4b9a-870f-2fc6d5f57a9c |
User | root |
Command | /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590948558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_ jtag_state_post_trans.3590948558 |
Directory | /workspace/9.lc_ctrl_jtag_state_post_trans/latest |
Test location | /workspace/coverage/default/9.lc_ctrl_prog_failure.465641165 |
Short name | T851 |
Test name | |
Test status | |
Simulation time | 213866665 ps |
CPU time | 1.9 seconds |
Started | Jun 30 06:55:37 PM PDT 24 |
Finished | Jun 30 06:55:40 PM PDT 24 |
Peak memory | 218868 kb |
Host | smart-9cf8cb2e-f5ee-4a38-91f6-07837dbe5098 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=465641165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.465641165 |
Directory | /workspace/9.lc_ctrl_prog_failure/latest |
Test location | /workspace/coverage/default/9.lc_ctrl_regwen_during_op.2550364621 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 1213200470 ps |
CPU time | 10.48 seconds |
Started | Jun 30 06:55:37 PM PDT 24 |
Finished | Jun 30 06:55:49 PM PDT 24 |
Peak memory | 218016 kb |
Host | smart-ee8cbb3b-fa49-406b-ae71-d1bdf96f4445 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2550364621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.2550364621 |
Directory | /workspace/9.lc_ctrl_regwen_during_op/latest |
Test location | /workspace/coverage/default/9.lc_ctrl_sec_mubi.155050701 |
Short name | T389 |
Test name | |
Test status | |
Simulation time | 439352490 ps |
CPU time | 12.68 seconds |
Started | Jun 30 06:55:39 PM PDT 24 |
Finished | Jun 30 06:55:54 PM PDT 24 |
Peak memory | 226420 kb |
Host | smart-a9a01aec-f789-49c7-a34e-5a6867807bd0 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155050701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.155050701 |
Directory | /workspace/9.lc_ctrl_sec_mubi/latest |
Test location | /workspace/coverage/default/9.lc_ctrl_sec_token_digest.310110808 |
Short name | T735 |
Test name | |
Test status | |
Simulation time | 728075840 ps |
CPU time | 6.58 seconds |
Started | Jun 30 06:55:39 PM PDT 24 |
Finished | Jun 30 06:55:48 PM PDT 24 |
Peak memory | 218568 kb |
Host | smart-1d717fcd-987b-40ad-b97e-44e1760b7c79 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310110808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_dig est.310110808 |
Directory | /workspace/9.lc_ctrl_sec_token_digest/latest |
Test location | /workspace/coverage/default/9.lc_ctrl_sec_token_mux.695276145 |
Short name | T513 |
Test name | |
Test status | |
Simulation time | 1889772709 ps |
CPU time | 15.39 seconds |
Started | Jun 30 06:55:37 PM PDT 24 |
Finished | Jun 30 06:55:55 PM PDT 24 |
Peak memory | 218592 kb |
Host | smart-1ee5cf45-2dd4-4d63-b1fc-037a6c53ff24 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695276145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.695276145 |
Directory | /workspace/9.lc_ctrl_sec_token_mux/latest |
Test location | /workspace/coverage/default/9.lc_ctrl_security_escalation.143793292 |
Short name | T647 |
Test name | |
Test status | |
Simulation time | 412393452 ps |
CPU time | 15.49 seconds |
Started | Jun 30 06:55:36 PM PDT 24 |
Finished | Jun 30 06:55:53 PM PDT 24 |
Peak memory | 226500 kb |
Host | smart-5964ee9b-7385-45ba-9677-b900f9a425b3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=143793292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.143793292 |
Directory | /workspace/9.lc_ctrl_security_escalation/latest |
Test location | /workspace/coverage/default/9.lc_ctrl_smoke.723611053 |
Short name | T848 |
Test name | |
Test status | |
Simulation time | 32851140 ps |
CPU time | 2.57 seconds |
Started | Jun 30 06:55:35 PM PDT 24 |
Finished | Jun 30 06:55:38 PM PDT 24 |
Peak memory | 214856 kb |
Host | smart-a45e3a13-7fa9-41d3-b09f-127e684af606 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=723611053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.723611053 |
Directory | /workspace/9.lc_ctrl_smoke/latest |
Test location | /workspace/coverage/default/9.lc_ctrl_state_failure.473855270 |
Short name | T515 |
Test name | |
Test status | |
Simulation time | 248327400 ps |
CPU time | 22.65 seconds |
Started | Jun 30 06:55:31 PM PDT 24 |
Finished | Jun 30 06:55:54 PM PDT 24 |
Peak memory | 247608 kb |
Host | smart-f286eba8-387f-406e-b8c2-a976530dfaf2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=473855270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.473855270 |
Directory | /workspace/9.lc_ctrl_state_failure/latest |
Test location | /workspace/coverage/default/9.lc_ctrl_state_post_trans.1796509795 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 577677041 ps |
CPU time | 3.56 seconds |
Started | Jun 30 06:55:37 PM PDT 24 |
Finished | Jun 30 06:55:42 PM PDT 24 |
Peak memory | 226772 kb |
Host | smart-c709d1db-42c3-4783-8530-94e2d469b806 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1796509795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.1796509795 |
Directory | /workspace/9.lc_ctrl_state_post_trans/latest |
Test location | /workspace/coverage/default/9.lc_ctrl_stress_all.1388968211 |
Short name | T576 |
Test name | |
Test status | |
Simulation time | 134467909774 ps |
CPU time | 185.68 seconds |
Started | Jun 30 06:55:36 PM PDT 24 |
Finished | Jun 30 06:58:42 PM PDT 24 |
Peak memory | 238556 kb |
Host | smart-39ccdf92-bb2e-404f-92ff-b88ff7149bd6 |
User | root |
Command | /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388968211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all.1388968211 |
Directory | /workspace/9.lc_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.1552352161 |
Short name | T638 |
Test name | |
Test status | |
Simulation time | 14627343 ps |
CPU time | 1.01 seconds |
Started | Jun 30 06:55:34 PM PDT 24 |
Finished | Jun 30 06:55:36 PM PDT 24 |
Peak memory | 209548 kb |
Host | smart-71c19ded-15ac-4ab1-9311-e27da2c1ff31 |
User | root |
Command | /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552352161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct rl_volatile_unlock_smoke.1552352161 |
Directory | /workspace/9.lc_ctrl_volatile_unlock_smoke/latest |
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