Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

91814953

1

T1

20704

T2

3397

T3

50623

auto[1]

1371534

1

T3

98

T14

495

T15

99

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

91786616

1

T1

20704

T2

3397

T3

50329

auto[1]

1399871

1

T3

392

T14

99

T15

198

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7057887	1			T1	5712		T2	684		T3	3411
auto[IdleSt]	20838873	1			T1	2351		T2	1043		T3	13206
auto[ClkMuxSt]	34807	1			T1	62		T2	8		T3	7
auto[CntIncrSt]	34445	1			T1	62		T2	8		T3	7
auto[CntProgSt]	1860658	1			T1	2393		T2	353		T3	14
auto[TransCheckSt]	26861	1			T1	62		T2	8		T3	7
auto[TokenHashSt]	32972789	1			T1	418		T2	88		T3	78
auto[FlashRmaSt]	28684	1			T1	41		T2	15		T3	27
auto[TokenCheck0St]	12436	1			T1	32		T2	8		T3	7
auto[TokenCheck1St]	9253	1			T1	7		T2	8		T3	7
auto[TransProgSt]	498736	1			T2	237		T3	14		T12	1465
auto[PostTransSt]	11968836	1			T1	9564		T2	937		T3	17560
auto[ScrapSt]	174560	1			T12	24		T4	1170		T17	15
auto[EscalateSt]	6542889	1			T3	6751		T14	914		T15	853
auto[InvalidSt]	11122840	1			T3	9624		T14	496		T15	665

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1933	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	11122840	1			T3	9624		T14	496		T15	665
EscalateSt	6542889	1			T3	6751		T14	914		T15	853
ScrapSt	174560	1			T12	24		T4	1170		T17	15
PostTransSt	11968836	1			T1	9564		T2	937		T3	17560
TransProgSt	498736	1			T2	237		T3	14		T12	1465
TokenCheck1St	9253	1			T1	7		T2	8		T3	7
TokenCheck0St	12436	1			T1	32		T2	8		T3	7
FlashRmaSt	28684	1			T1	41		T2	15		T3	27
TokenHashSt	32972789	1			T1	418		T2	88		T3	78
TransCheckSt	26861	1			T1	62		T2	8		T3	7
CntProgSt	1860658	1			T1	2393		T2	353		T3	14
CntIncrSt	34445	1			T1	62		T2	8		T3	7
ClkMuxSt	34807	1			T1	62		T2	8		T3	7
IdleSt	20838873	1			T1	2351		T2	1043		T3	13206
ResetSt	7057887	1			T1	5712		T2	684		T3	3411
arcs[ResetSt=>IdleSt]	52676	1			T1	63		T2	8		T3	14
arcs[IdleSt=>ScrapSt]	277	1			T12	1		T4	4		T17	1
arcs[IdleSt=>ClkMuxSt]	34512	1			T1	62		T2	8		T3	7
arcs[ClkMuxSt=>CntIncrSt]	34445	1			T1	62		T2	8		T3	7
arcs[CntIncrSt=>PostTransSt]	1718	1			T4	24		T17	21		T19	10
arcs[CntIncrSt=>CntProgSt]	32664	1			T1	62		T2	8		T3	7
arcs[CntProgSt=>PostTransSt]	4638	1			T4	13		T17	46		T45	19
arcs[CntProgSt=>TransCheckSt]	26861	1			T1	62		T2	8		T3	7
arcs[TransCheckSt=>PostTransSt]	3626	1			T1	24		T11	40		T13	48
arcs[TransCheckSt=>TokenHashSt]	23083	1			T1	38		T2	8		T3	7
arcs[TokenHashSt=>PostTransSt]	9886	1			T1	6		T11	5		T13	15
arcs[TokenHashSt=>FlashRmaSt]	12551	1			T1	32		T2	8		T3	7
arcs[FlashRmaSt=>TokenCheck0St]	12436	1			T1	32		T2	8		T3	7
arcs[TokenCheck0St=>PostTransSt]	3159	1			T1	25		T11	23		T13	27
arcs[TokenCheck0St=>TokenCheck1St]	9253	1			T1	7		T2	8		T3	7
arcs[TokenCheck1St=>PostTransSt]	653	1			T1	7		T11	10		T13	8
arcs[TransProgSt=>PostTransSt]	7677	1			T2	8		T3	7		T12	5
arcs[IdleSt=>EscalateSt]	170	1			T54	6		T55	3		T56	7
arcs[ClkMuxSt=>EscalateSt]	67	1			T54	2		T55	2		T56	1
arcs[CntIncrSt=>EscalateSt]	63	1			T54	2		T55	1		T57	2
arcs[CntProgSt=>EscalateSt]	1165	1			T54	18		T55	7		T56	9
arcs[TransCheckSt=>EscalateSt]	152	1			T55	9		T56	3		T57	10
arcs[TokenHashSt=>EscalateSt]	646	1			T54	3		T55	13		T56	14
arcs[FlashRmaSt=>EscalateSt]	115	1			T54	2		T55	2		T56	1
arcs[TokenCheck0St=>EscalateSt]	24	1			T57	1		T58	2		T60	1
arcs[TokenCheck1St=>EscalateSt]	165	1			T54	2		T55	1		T56	2
arcs[TransProgSt=>EscalateSt]	758	1			T54	14		T55	8		T56	6
arcs[PostTransSt=>EscalateSt]	4897	1			T4	13		T17	46		T45	19
arcs[InvalidSt=>EscalateSt]	13706	1			T3	5		T14	6		T15	3

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7057701	1			T1	5712		T2	684		T3	3411
auto[0]	auto[IdleSt]	20838768	1			T1	2351		T2	1043		T3	13206
auto[0]	auto[ClkMuxSt]	34771	1			T1	62		T2	8		T3	7
auto[0]	auto[CntIncrSt]	34401	1			T1	62		T2	8		T3	7
auto[0]	auto[CntProgSt]	1859871	1			T1	2393		T2	353		T3	14
auto[0]	auto[TransCheckSt]	26760	1			T1	62		T2	8		T3	7
auto[0]	auto[TokenHashSt]	32972369	1			T1	418		T2	88		T3	78
auto[0]	auto[FlashRmaSt]	28607	1			T1	41		T2	15		T3	27
auto[0]	auto[TokenCheck0St]	12420	1			T1	32		T2	8		T3	7
auto[0]	auto[TokenCheck1St]	9154	1			T1	7		T2	8		T3	7
auto[0]	auto[TransProgSt]	498241	1			T2	237		T3	14		T12	1465
auto[0]	auto[PostTransSt]	11966352	1			T1	9564		T2	937		T3	17560
auto[0]	auto[ScrapSt]	174529	1			T12	24		T4	1170		T17	15
auto[0]	auto[EscalateSt]	5182991	1			T3	6654		T14	424		T15	755
auto[0]	auto[InvalidSt]	11116085	1			T3	9623		T14	491		T15	664
auto[1]	auto[ResetSt]	186	1			T54	9		T55	4		T56	3
auto[1]	auto[IdleSt]	105	1			T54	5		T55	1		T56	5
auto[1]	auto[ClkMuxSt]	36	1			T54	1		T55	2		T58	2
auto[1]	auto[CntIncrSt]	44	1			T54	2		T57	2		T227	2
auto[1]	auto[CntProgSt]	787	1			T54	12		T55	2		T56	6
auto[1]	auto[TransCheckSt]	101	1			T55	4		T56	3		T57	5
auto[1]	auto[TokenHashSt]	420	1			T54	2		T55	8		T56	10
auto[1]	auto[FlashRmaSt]	77	1			T54	2		T55	2		T56	1
auto[1]	auto[TokenCheck0St]	16	1			T58	2		T228	1		T229	2
auto[1]	auto[TokenCheck1St]	99	1			T54	1		T55	1		T56	2
auto[1]	auto[TransProgSt]	495	1			T54	10		T55	4		T56	3
auto[1]	auto[PostTransSt]	2484	1			T4	9		T17	24		T45	13
auto[1]	auto[ScrapSt]	31	1			T56	3		T58	1		T227	1
auto[1]	auto[EscalateSt]	1359898	1			T3	97		T14	490		T15	98
auto[1]	auto[InvalidSt]	6755	1			T3	1		T14	5		T15	1

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7057733	1			T1	5712		T2	684		T3	3411
auto[0]	auto[IdleSt]	20838754	1			T1	2351		T2	1043		T3	13206
auto[0]	auto[ClkMuxSt]	34760	1			T1	62		T2	8		T3	7
auto[0]	auto[CntIncrSt]	34408	1			T1	62		T2	8		T3	7
auto[0]	auto[CntProgSt]	1859877	1			T1	2393		T2	353		T3	14
auto[0]	auto[TransCheckSt]	26761	1			T1	62		T2	8		T3	7
auto[0]	auto[TokenHashSt]	32972344	1			T1	418		T2	88		T3	78
auto[0]	auto[FlashRmaSt]	28600	1			T1	41		T2	15		T3	27
auto[0]	auto[TokenCheck0St]	12420	1			T1	32		T2	8		T3	7
auto[0]	auto[TokenCheck1St]	9133	1			T1	7		T2	8		T3	7
auto[0]	auto[TransProgSt]	498217	1			T2	237		T3	14		T12	1465
auto[0]	auto[PostTransSt]	11966350	1			T1	9564		T2	937		T3	17560
auto[0]	auto[ScrapSt]	174523	1			T12	24		T4	1170		T17	15
auto[0]	auto[EscalateSt]	5154914	1			T3	6363		T14	816		T15	657
auto[0]	auto[InvalidSt]	11115889	1			T3	9620		T14	495		T15	663
auto[1]	auto[ResetSt]	154	1			T54	5		T55	2		T56	3
auto[1]	auto[IdleSt]	119	1			T54	4		T55	3		T56	4
auto[1]	auto[ClkMuxSt]	47	1			T54	1		T55	2		T56	1
auto[1]	auto[CntIncrSt]	37	1			T54	1		T55	1		T57	1
auto[1]	auto[CntProgSt]	781	1			T54	12		T55	5		T56	5
auto[1]	auto[TransCheckSt]	100	1			T55	5		T56	3		T57	8
auto[1]	auto[TokenHashSt]	445	1			T54	3		T55	9		T56	12
auto[1]	auto[FlashRmaSt]	84	1			T54	2		T56	1		T57	2
auto[1]	auto[TokenCheck0St]	16	1			T57	1		T58	1		T60	1
auto[1]	auto[TokenCheck1St]	120	1			T54	2		T55	1		T56	2
auto[1]	auto[TransProgSt]	519	1			T54	6		T55	4		T56	6
auto[1]	auto[PostTransSt]	2486	1			T4	4		T17	22		T45	6
auto[1]	auto[ScrapSt]	37	1			T56	2		T57	1		T227	1
auto[1]	auto[EscalateSt]	1387975	1			T3	388		T14	98		T15	196
auto[1]	auto[InvalidSt]	6951	1			T3	4		T14	1		T15	2