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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.22 97.99 95.41 93.38 100.00 98.55 98.76 96.47


Total test records in report: 998
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T823 /workspace/coverage/default/4.lc_ctrl_jtag_priority.2476836087 Jul 01 12:29:40 PM PDT 24 Jul 01 12:29:43 PM PDT 24 274704953 ps
T824 /workspace/coverage/default/1.lc_ctrl_sec_token_digest.281110935 Jul 01 12:28:43 PM PDT 24 Jul 01 12:28:56 PM PDT 24 749048825 ps
T825 /workspace/coverage/default/47.lc_ctrl_sec_mubi.1125906910 Jul 01 12:35:00 PM PDT 24 Jul 01 12:35:09 PM PDT 24 260484459 ps
T826 /workspace/coverage/default/19.lc_ctrl_prog_failure.633686132 Jul 01 12:32:25 PM PDT 24 Jul 01 12:32:28 PM PDT 24 60955959 ps
T827 /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.709999079 Jul 01 12:31:47 PM PDT 24 Jul 01 12:31:51 PM PDT 24 198834725 ps
T828 /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.1926926712 Jul 01 12:27:59 PM PDT 24 Jul 01 12:29:23 PM PDT 24 2774100530 ps
T829 /workspace/coverage/default/35.lc_ctrl_sec_token_digest.371625142 Jul 01 12:34:01 PM PDT 24 Jul 01 12:34:14 PM PDT 24 526877782 ps
T830 /workspace/coverage/default/36.lc_ctrl_prog_failure.2140765653 Jul 01 12:33:59 PM PDT 24 Jul 01 12:34:04 PM PDT 24 218915102 ps
T831 /workspace/coverage/default/28.lc_ctrl_sec_token_mux.1043163334 Jul 01 12:33:18 PM PDT 24 Jul 01 12:33:27 PM PDT 24 1352632336 ps
T832 /workspace/coverage/default/6.lc_ctrl_jtag_priority.2548971331 Jul 01 12:30:29 PM PDT 24 Jul 01 12:30:33 PM PDT 24 614345605 ps
T833 /workspace/coverage/default/12.lc_ctrl_prog_failure.2808569774 Jul 01 12:31:21 PM PDT 24 Jul 01 12:31:24 PM PDT 24 116764096 ps
T834 /workspace/coverage/default/25.lc_ctrl_alert_test.226905679 Jul 01 12:33:07 PM PDT 24 Jul 01 12:33:08 PM PDT 24 93087738 ps
T835 /workspace/coverage/default/25.lc_ctrl_state_failure.2256776469 Jul 01 12:33:00 PM PDT 24 Jul 01 12:33:19 PM PDT 24 872667199 ps
T836 /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.1506987744 Jul 01 12:32:28 PM PDT 24 Jul 01 12:32:30 PM PDT 24 46091024 ps
T837 /workspace/coverage/default/13.lc_ctrl_state_post_trans.2094484677 Jul 01 12:31:27 PM PDT 24 Jul 01 12:31:36 PM PDT 24 71696390 ps
T838 /workspace/coverage/default/34.lc_ctrl_sec_token_mux.525589945 Jul 01 12:33:52 PM PDT 24 Jul 01 12:34:06 PM PDT 24 1115641595 ps
T839 /workspace/coverage/default/15.lc_ctrl_security_escalation.4032009627 Jul 01 12:31:48 PM PDT 24 Jul 01 12:32:01 PM PDT 24 628613484 ps
T840 /workspace/coverage/default/6.lc_ctrl_alert_test.2723937084 Jul 01 12:30:29 PM PDT 24 Jul 01 12:30:32 PM PDT 24 18114883 ps
T841 /workspace/coverage/default/35.lc_ctrl_state_post_trans.2353273428 Jul 01 12:33:53 PM PDT 24 Jul 01 12:33:58 PM PDT 24 50390762 ps
T842 /workspace/coverage/default/20.lc_ctrl_errors.2025309633 Jul 01 12:32:37 PM PDT 24 Jul 01 12:32:51 PM PDT 24 278111962 ps
T843 /workspace/coverage/default/3.lc_ctrl_state_post_trans.1054926432 Jul 01 12:29:13 PM PDT 24 Jul 01 12:29:17 PM PDT 24 399511517 ps
T844 /workspace/coverage/default/3.lc_ctrl_jtag_access.3503665562 Jul 01 12:29:23 PM PDT 24 Jul 01 12:29:26 PM PDT 24 53652956 ps
T845 /workspace/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.1453335780 Jul 01 12:33:42 PM PDT 24 Jul 01 12:41:36 PM PDT 24 24860649727 ps
T846 /workspace/coverage/default/4.lc_ctrl_stress_all.1284375918 Jul 01 12:29:46 PM PDT 24 Jul 01 12:30:33 PM PDT 24 4293185876 ps
T847 /workspace/coverage/default/1.lc_ctrl_sec_token_mux.417608883 Jul 01 12:28:42 PM PDT 24 Jul 01 12:28:59 PM PDT 24 2052889521 ps
T125 /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.3383663148 Jul 01 12:34:20 PM PDT 24 Jul 01 12:42:42 PM PDT 24 21461011171 ps
T187 /workspace/coverage/default/47.lc_ctrl_sec_token_digest.3937648103 Jul 01 12:35:03 PM PDT 24 Jul 01 12:35:12 PM PDT 24 395116592 ps
T188 /workspace/coverage/default/29.lc_ctrl_sec_mubi.441019042 Jul 01 12:33:31 PM PDT 24 Jul 01 12:33:49 PM PDT 24 2650949527 ps
T189 /workspace/coverage/default/5.lc_ctrl_sec_mubi.2839036007 Jul 01 12:29:55 PM PDT 24 Jul 01 12:30:14 PM PDT 24 697311339 ps
T190 /workspace/coverage/default/31.lc_ctrl_sec_token_digest.1541205104 Jul 01 12:33:35 PM PDT 24 Jul 01 12:33:52 PM PDT 24 825719890 ps
T191 /workspace/coverage/default/44.lc_ctrl_errors.81505320 Jul 01 12:34:46 PM PDT 24 Jul 01 12:34:59 PM PDT 24 566119978 ps
T192 /workspace/coverage/default/24.lc_ctrl_smoke.1296682237 Jul 01 12:32:53 PM PDT 24 Jul 01 12:32:57 PM PDT 24 94656103 ps
T193 /workspace/coverage/default/22.lc_ctrl_alert_test.558414472 Jul 01 12:32:52 PM PDT 24 Jul 01 12:32:53 PM PDT 24 23367870 ps
T194 /workspace/coverage/default/30.lc_ctrl_prog_failure.975830953 Jul 01 12:33:30 PM PDT 24 Jul 01 12:33:38 PM PDT 24 2257064447 ps
T195 /workspace/coverage/default/0.lc_ctrl_claim_transition_if.2284190351 Jul 01 12:27:58 PM PDT 24 Jul 01 12:27:59 PM PDT 24 16311443 ps
T848 /workspace/coverage/default/35.lc_ctrl_alert_test.805429265 Jul 01 12:33:58 PM PDT 24 Jul 01 12:34:00 PM PDT 24 13882513 ps
T849 /workspace/coverage/default/27.lc_ctrl_alert_test.2819284975 Jul 01 12:33:20 PM PDT 24 Jul 01 12:33:21 PM PDT 24 115374339 ps
T850 /workspace/coverage/default/12.lc_ctrl_security_escalation.351308812 Jul 01 12:31:21 PM PDT 24 Jul 01 12:31:32 PM PDT 24 2172667222 ps
T851 /workspace/coverage/default/41.lc_ctrl_alert_test.2284558863 Jul 01 12:34:30 PM PDT 24 Jul 01 12:34:31 PM PDT 24 41787709 ps
T852 /workspace/coverage/default/5.lc_ctrl_sec_token_mux.509853635 Jul 01 12:29:58 PM PDT 24 Jul 01 12:30:09 PM PDT 24 404561437 ps
T853 /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.1224912008 Jul 01 12:31:12 PM PDT 24 Jul 01 12:32:07 PM PDT 24 2220203984 ps
T854 /workspace/coverage/default/17.lc_ctrl_jtag_access.3824761800 Jul 01 12:32:07 PM PDT 24 Jul 01 12:32:09 PM PDT 24 476304781 ps
T855 /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.2314584554 Jul 01 12:32:03 PM PDT 24 Jul 01 12:32:11 PM PDT 24 1815742185 ps
T856 /workspace/coverage/default/19.lc_ctrl_sec_mubi.3240449808 Jul 01 12:32:30 PM PDT 24 Jul 01 12:32:41 PM PDT 24 369420671 ps
T857 /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.1920916730 Jul 01 12:34:25 PM PDT 24 Jul 01 12:34:28 PM PDT 24 17780896 ps
T858 /workspace/coverage/default/44.lc_ctrl_security_escalation.503693116 Jul 01 12:34:45 PM PDT 24 Jul 01 12:34:55 PM PDT 24 1512985780 ps
T196 /workspace/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.1457880259 Jul 01 12:30:01 PM PDT 24 Jul 01 12:38:54 PM PDT 24 13821464278 ps
T859 /workspace/coverage/default/2.lc_ctrl_jtag_priority.3183668060 Jul 01 12:28:58 PM PDT 24 Jul 01 12:29:08 PM PDT 24 1483508971 ps
T860 /workspace/coverage/default/30.lc_ctrl_alert_test.3234683380 Jul 01 12:33:33 PM PDT 24 Jul 01 12:33:35 PM PDT 24 14877178 ps
T861 /workspace/coverage/default/2.lc_ctrl_errors.3473596641 Jul 01 12:28:50 PM PDT 24 Jul 01 12:29:06 PM PDT 24 696737876 ps
T862 /workspace/coverage/default/17.lc_ctrl_prog_failure.1124105601 Jul 01 12:32:07 PM PDT 24 Jul 01 12:32:12 PM PDT 24 188120514 ps
T863 /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.1509545992 Jul 01 12:32:51 PM PDT 24 Jul 01 12:32:53 PM PDT 24 27679093 ps
T864 /workspace/coverage/default/44.lc_ctrl_prog_failure.807153496 Jul 01 12:34:44 PM PDT 24 Jul 01 12:34:48 PM PDT 24 984330158 ps
T78 /workspace/coverage/default/46.lc_ctrl_alert_test.1471520010 Jul 01 12:34:55 PM PDT 24 Jul 01 12:34:57 PM PDT 24 25367622 ps
T865 /workspace/coverage/default/10.lc_ctrl_state_failure.1558915658 Jul 01 12:31:03 PM PDT 24 Jul 01 12:31:32 PM PDT 24 1145703189 ps
T866 /workspace/coverage/default/36.lc_ctrl_alert_test.3570896371 Jul 01 12:34:05 PM PDT 24 Jul 01 12:34:08 PM PDT 24 39016693 ps
T867 /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.1226424337 Jul 01 12:30:21 PM PDT 24 Jul 01 12:30:27 PM PDT 24 1022039870 ps
T868 /workspace/coverage/default/23.lc_ctrl_security_escalation.3905789241 Jul 01 12:32:48 PM PDT 24 Jul 01 12:33:09 PM PDT 24 2642256844 ps
T869 /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.3616647708 Jul 01 12:32:17 PM PDT 24 Jul 01 12:32:19 PM PDT 24 233499410 ps
T870 /workspace/coverage/default/39.lc_ctrl_sec_token_digest.2997491034 Jul 01 12:34:21 PM PDT 24 Jul 01 12:34:38 PM PDT 24 2174408666 ps
T224 /workspace/coverage/default/5.lc_ctrl_claim_transition_if.3650727501 Jul 01 12:29:58 PM PDT 24 Jul 01 12:30:00 PM PDT 24 30407571 ps
T871 /workspace/coverage/default/44.lc_ctrl_stress_all.54393300 Jul 01 12:34:46 PM PDT 24 Jul 01 12:43:51 PM PDT 24 53456620465 ps
T872 /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.2290454876 Jul 01 12:32:19 PM PDT 24 Jul 01 12:33:06 PM PDT 24 5601857394 ps
T127 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1183206382 Jul 01 10:56:47 AM PDT 24 Jul 01 10:56:52 AM PDT 24 37010949 ps
T156 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.3685034661 Jul 01 10:56:49 AM PDT 24 Jul 01 10:56:57 AM PDT 24 270773416 ps
T122 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.357234358 Jul 01 10:55:23 AM PDT 24 Jul 01 10:55:25 AM PDT 24 52794066 ps
T119 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.695480104 Jul 01 10:56:47 AM PDT 24 Jul 01 10:56:55 AM PDT 24 307575266 ps
T133 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1150787088 Jul 01 10:56:46 AM PDT 24 Jul 01 10:56:50 AM PDT 24 27416362 ps
T120 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.4003171125 Jul 01 10:56:48 AM PDT 24 Jul 01 10:56:56 AM PDT 24 93628030 ps
T873 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1810818979 Jul 01 10:56:45 AM PDT 24 Jul 01 10:56:49 AM PDT 24 30614252 ps
T155 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3022536673 Jul 01 10:55:17 AM PDT 24 Jul 01 10:55:23 AM PDT 24 228448010 ps
T157 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1053655825 Jul 01 10:56:33 AM PDT 24 Jul 01 10:57:07 AM PDT 24 2309316346 ps
T173 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1942753626 Jul 01 10:56:45 AM PDT 24 Jul 01 10:56:48 AM PDT 24 100137319 ps
T121 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1548976074 Jul 01 10:56:49 AM PDT 24 Jul 01 10:56:59 AM PDT 24 319957890 ps
T128 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1504131201 Jul 01 10:56:47 AM PDT 24 Jul 01 10:56:53 AM PDT 24 94143504 ps
T123 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2692540188 Jul 01 10:56:46 AM PDT 24 Jul 01 10:56:53 AM PDT 24 97642102 ps
T152 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4003366871 Jul 01 10:56:45 AM PDT 24 Jul 01 10:56:52 AM PDT 24 117859904 ps
T153 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.4218566157 Jul 01 10:56:46 AM PDT 24 Jul 01 10:56:55 AM PDT 24 1305312583 ps
T874 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1414231107 Jul 01 10:56:53 AM PDT 24 Jul 01 10:56:59 AM PDT 24 35967709 ps
T126 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.306859626 Jul 01 10:56:47 AM PDT 24 Jul 01 10:56:56 AM PDT 24 114150368 ps
T875 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.3985510481 Jul 01 10:56:50 AM PDT 24 Jul 01 10:56:58 AM PDT 24 249439367 ps
T129 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3417430422 Jul 01 10:56:53 AM PDT 24 Jul 01 10:57:01 AM PDT 24 31169463 ps
T137 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.467448574 Jul 01 10:56:52 AM PDT 24 Jul 01 10:56:59 AM PDT 24 213715972 ps
T876 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.713859045 Jul 01 10:55:22 AM PDT 24 Jul 01 10:55:32 AM PDT 24 3445262628 ps
T877 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2372358959 Jul 01 10:56:48 AM PDT 24 Jul 01 10:56:55 AM PDT 24 109038032 ps
T878 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.640258412 Jul 01 10:56:32 AM PDT 24 Jul 01 10:56:34 AM PDT 24 156279300 ps
T131 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.4214061022 Jul 01 10:56:49 AM PDT 24 Jul 01 10:56:57 AM PDT 24 123007849 ps
T132 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1527817629 Jul 01 10:56:56 AM PDT 24 Jul 01 10:57:01 AM PDT 24 96754536 ps
T201 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2381652950 Jul 01 10:56:56 AM PDT 24 Jul 01 10:57:01 AM PDT 24 13773279 ps
T154 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.542951117 Jul 01 10:56:48 AM PDT 24 Jul 01 10:56:57 AM PDT 24 514502373 ps
T879 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.333153207 Jul 01 10:56:48 AM PDT 24 Jul 01 10:56:54 AM PDT 24 43377297 ps
T880 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1905953973 Jul 01 10:56:43 AM PDT 24 Jul 01 10:56:47 AM PDT 24 1006301510 ps
T141 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.4155735844 Jul 01 10:56:55 AM PDT 24 Jul 01 10:57:05 AM PDT 24 587577761 ps
T174 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3677749224 Jul 01 10:56:52 AM PDT 24 Jul 01 10:56:58 AM PDT 24 20781051 ps
T124 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2032206494 Jul 01 10:56:53 AM PDT 24 Jul 01 10:57:01 AM PDT 24 266046375 ps
T138 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.387965038 Jul 01 10:56:56 AM PDT 24 Jul 01 10:57:02 AM PDT 24 119899530 ps
T881 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.4235916467 Jul 01 10:55:30 AM PDT 24 Jul 01 10:55:31 AM PDT 24 1124780602 ps
T882 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.3023891668 Jul 01 10:55:24 AM PDT 24 Jul 01 10:55:26 AM PDT 24 37756948 ps
T213 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2783792690 Jul 01 10:56:57 AM PDT 24 Jul 01 10:57:01 AM PDT 24 57865880 ps
T214 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3577245807 Jul 01 10:56:46 AM PDT 24 Jul 01 10:56:51 AM PDT 24 22934735 ps
T202 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1377701888 Jul 01 10:56:53 AM PDT 24 Jul 01 10:56:59 AM PDT 24 14196454 ps
T883 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2115356214 Jul 01 10:56:45 AM PDT 24 Jul 01 10:56:50 AM PDT 24 250636151 ps
T884 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1535358472 Jul 01 10:56:45 AM PDT 24 Jul 01 10:56:50 AM PDT 24 242892456 ps
T885 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.469842917 Jul 01 10:56:47 AM PDT 24 Jul 01 10:56:54 AM PDT 24 62779307 ps
T215 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2602631194 Jul 01 10:56:48 AM PDT 24 Jul 01 10:56:54 AM PDT 24 16743470 ps
T140 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1847126732 Jul 01 10:56:47 AM PDT 24 Jul 01 10:56:55 AM PDT 24 541104824 ps
T886 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.830695700 Jul 01 10:56:47 AM PDT 24 Jul 01 10:56:54 AM PDT 24 961231579 ps
T887 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.4211871397 Jul 01 10:56:48 AM PDT 24 Jul 01 10:57:10 AM PDT 24 802672275 ps
T888 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3938160761 Jul 01 10:56:52 AM PDT 24 Jul 01 10:56:59 AM PDT 24 93979441 ps
T889 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3413044490 Jul 01 10:56:52 AM PDT 24 Jul 01 10:57:00 AM PDT 24 417755287 ps
T890 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.589845263 Jul 01 10:56:44 AM PDT 24 Jul 01 10:56:47 AM PDT 24 91751346 ps
T203 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3389397422 Jul 01 10:55:23 AM PDT 24 Jul 01 10:55:24 AM PDT 24 47042221 ps
T204 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.587703322 Jul 01 10:56:53 AM PDT 24 Jul 01 10:56:59 AM PDT 24 16968330 ps
T216 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2131204441 Jul 01 10:56:46 AM PDT 24 Jul 01 10:56:50 AM PDT 24 26206742 ps
T205 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1588615502 Jul 01 10:56:52 AM PDT 24 Jul 01 10:56:58 AM PDT 24 30186682 ps
T891 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3448560002 Jul 01 10:56:52 AM PDT 24 Jul 01 10:56:58 AM PDT 24 24394305 ps
T217 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.380695490 Jul 01 10:55:23 AM PDT 24 Jul 01 10:55:25 AM PDT 24 584812739 ps
T892 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1809439900 Jul 01 10:55:23 AM PDT 24 Jul 01 10:55:25 AM PDT 24 70656133 ps
T893 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.52865142 Jul 01 10:56:52 AM PDT 24 Jul 01 10:56:59 AM PDT 24 83825384 ps
T206 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1972387161 Jul 01 10:56:47 AM PDT 24 Jul 01 10:56:53 AM PDT 24 153935332 ps
T894 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1040455809 Jul 01 10:56:53 AM PDT 24 Jul 01 10:56:59 AM PDT 24 92938085 ps
T895 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.4286321077 Jul 01 10:56:45 AM PDT 24 Jul 01 10:56:50 AM PDT 24 312107938 ps
T130 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1127784353 Jul 01 10:56:45 AM PDT 24 Jul 01 10:56:50 AM PDT 24 240461936 ps
T896 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3632938948 Jul 01 10:56:52 AM PDT 24 Jul 01 10:56:58 AM PDT 24 52622791 ps
T897 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.737420798 Jul 01 10:56:50 AM PDT 24 Jul 01 10:57:03 AM PDT 24 5006856124 ps
T898 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1490149279 Jul 01 10:56:32 AM PDT 24 Jul 01 10:56:36 AM PDT 24 131272408 ps
T899 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3641781897 Jul 01 10:56:49 AM PDT 24 Jul 01 10:56:58 AM PDT 24 602745113 ps
T146 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.726716484 Jul 01 10:55:22 AM PDT 24 Jul 01 10:55:26 AM PDT 24 480196333 ps
T143 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3435298671 Jul 01 10:56:45 AM PDT 24 Jul 01 10:56:52 AM PDT 24 117674547 ps
T900 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2293111462 Jul 01 10:56:47 AM PDT 24 Jul 01 10:56:52 AM PDT 24 55525997 ps
T901 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.385249415 Jul 01 10:56:46 AM PDT 24 Jul 01 10:56:51 AM PDT 24 24753551 ps
T226 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3752358516 Jul 01 10:55:31 AM PDT 24 Jul 01 10:55:34 AM PDT 24 65849036 ps
T902 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1115246488 Jul 01 10:56:52 AM PDT 24 Jul 01 10:56:58 AM PDT 24 73664161 ps
T903 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.903963620 Jul 01 10:56:33 AM PDT 24 Jul 01 10:56:41 AM PDT 24 871140899 ps
T218 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.118615290 Jul 01 10:56:49 AM PDT 24 Jul 01 10:56:57 AM PDT 24 40199941 ps
T904 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2447545257 Jul 01 10:55:21 AM PDT 24 Jul 01 10:55:27 AM PDT 24 954379143 ps
T219 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3517231831 Jul 01 10:56:47 AM PDT 24 Jul 01 10:56:52 AM PDT 24 66338541 ps
T905 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.524315885 Jul 01 10:56:45 AM PDT 24 Jul 01 10:56:50 AM PDT 24 67124207 ps
T207 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2435688287 Jul 01 10:56:45 AM PDT 24 Jul 01 10:56:48 AM PDT 24 34311950 ps
T906 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3792166933 Jul 01 10:56:49 AM PDT 24 Jul 01 10:56:56 AM PDT 24 3203980109 ps
T147 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2023599602 Jul 01 10:56:50 AM PDT 24 Jul 01 10:56:57 AM PDT 24 73214024 ps
T907 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2765297218 Jul 01 10:56:49 AM PDT 24 Jul 01 10:56:59 AM PDT 24 78140593 ps
T151 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3424324839 Jul 01 10:56:45 AM PDT 24 Jul 01 10:56:49 AM PDT 24 59852341 ps
T908 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.847019260 Jul 01 10:56:52 AM PDT 24 Jul 01 10:56:58 AM PDT 24 66506122 ps
T909 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2270309984 Jul 01 10:56:45 AM PDT 24 Jul 01 10:56:49 AM PDT 24 222209565 ps
T910 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3455798716 Jul 01 10:56:43 AM PDT 24 Jul 01 10:56:45 AM PDT 24 38084486 ps
T911 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3499923762 Jul 01 10:55:29 AM PDT 24 Jul 01 10:55:32 AM PDT 24 94413127 ps
T912 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3545089991 Jul 01 10:56:50 AM PDT 24 Jul 01 10:56:57 AM PDT 24 221438255 ps
T913 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.72707335 Jul 01 10:56:53 AM PDT 24 Jul 01 10:56:59 AM PDT 24 26464678 ps
T914 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1187307966 Jul 01 10:55:20 AM PDT 24 Jul 01 10:55:21 AM PDT 24 256568051 ps
T915 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2983083076 Jul 01 10:56:31 AM PDT 24 Jul 01 10:56:33 AM PDT 24 249063026 ps
T916 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3146250222 Jul 01 10:56:46 AM PDT 24 Jul 01 10:56:51 AM PDT 24 156640163 ps
T917 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3082966312 Jul 01 10:56:44 AM PDT 24 Jul 01 10:56:48 AM PDT 24 889499784 ps
T918 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2545967138 Jul 01 10:56:47 AM PDT 24 Jul 01 10:56:53 AM PDT 24 61849420 ps
T919 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.681756240 Jul 01 10:56:33 AM PDT 24 Jul 01 10:56:35 AM PDT 24 20132711 ps
T920 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3826735609 Jul 01 10:56:44 AM PDT 24 Jul 01 10:56:57 AM PDT 24 2485501875 ps
T921 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1460059504 Jul 01 10:56:58 AM PDT 24 Jul 01 10:57:02 AM PDT 24 33812232 ps
T922 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1611637805 Jul 01 10:56:48 AM PDT 24 Jul 01 10:56:54 AM PDT 24 17112773 ps
T923 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.4183420321 Jul 01 10:55:15 AM PDT 24 Jul 01 10:55:21 AM PDT 24 706612769 ps
T924 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3064112396 Jul 01 10:56:52 AM PDT 24 Jul 01 10:56:58 AM PDT 24 102838002 ps
T925 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.532408438 Jul 01 10:55:30 AM PDT 24 Jul 01 10:55:31 AM PDT 24 12873178 ps
T208 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3746371957 Jul 01 10:56:44 AM PDT 24 Jul 01 10:56:47 AM PDT 24 11999093 ps
T926 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2075253586 Jul 01 10:56:33 AM PDT 24 Jul 01 10:56:35 AM PDT 24 27155790 ps
T927 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3974319897 Jul 01 10:56:33 AM PDT 24 Jul 01 10:56:35 AM PDT 24 20178498 ps
T928 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1981413787 Jul 01 10:55:23 AM PDT 24 Jul 01 10:55:29 AM PDT 24 207805017 ps
T929 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.4174719114 Jul 01 10:56:50 AM PDT 24 Jul 01 10:56:58 AM PDT 24 328125184 ps
T209 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1384730427 Jul 01 10:56:48 AM PDT 24 Jul 01 10:56:54 AM PDT 24 34064764 ps
T142 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1233329293 Jul 01 10:56:53 AM PDT 24 Jul 01 10:57:02 AM PDT 24 530464003 ps
T930 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2506583845 Jul 01 10:56:42 AM PDT 24 Jul 01 10:57:10 AM PDT 24 8513816882 ps
T136 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2871515664 Jul 01 10:56:48 AM PDT 24 Jul 01 10:56:55 AM PDT 24 231479069 ps
T210 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3950729592 Jul 01 10:56:44 AM PDT 24 Jul 01 10:56:47 AM PDT 24 75959378 ps
T931 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.38237531 Jul 01 10:56:53 AM PDT 24 Jul 01 10:56:59 AM PDT 24 143536465 ps
T932 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2636965516 Jul 01 10:56:50 AM PDT 24 Jul 01 10:56:57 AM PDT 24 29254022 ps
T145 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3855405150 Jul 01 10:56:45 AM PDT 24 Jul 01 10:56:50 AM PDT 24 162066412 ps
T933 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3440221455 Jul 01 10:56:45 AM PDT 24 Jul 01 10:56:51 AM PDT 24 58770925 ps
T934 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1262179126 Jul 01 10:56:44 AM PDT 24 Jul 01 10:56:46 AM PDT 24 26153107 ps
T935 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3849853732 Jul 01 10:56:46 AM PDT 24 Jul 01 10:56:51 AM PDT 24 57505698 ps
T139 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1922684184 Jul 01 10:56:50 AM PDT 24 Jul 01 10:56:58 AM PDT 24 187914317 ps
T936 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3169089191 Jul 01 10:56:49 AM PDT 24 Jul 01 10:56:56 AM PDT 24 15406667 ps
T937 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3307687627 Jul 01 10:56:50 AM PDT 24 Jul 01 10:56:57 AM PDT 24 17417298 ps
T938 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.970182501 Jul 01 10:56:52 AM PDT 24 Jul 01 10:56:58 AM PDT 24 38804563 ps
T939 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.341986188 Jul 01 10:55:17 AM PDT 24 Jul 01 10:55:21 AM PDT 24 992038197 ps
T940 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3384001045 Jul 01 10:56:45 AM PDT 24 Jul 01 10:56:49 AM PDT 24 23233074 ps
T941 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2509738488 Jul 01 10:56:46 AM PDT 24 Jul 01 10:56:50 AM PDT 24 39070202 ps
T942 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2396611688 Jul 01 10:56:46 AM PDT 24 Jul 01 10:56:50 AM PDT 24 254893059 ps
T943 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1482317959 Jul 01 10:56:47 AM PDT 24 Jul 01 10:56:54 AM PDT 24 526630210 ps
T944 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3131914756 Jul 01 10:56:49 AM PDT 24 Jul 01 10:56:58 AM PDT 24 88110292 ps
T945 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1000618000 Jul 01 10:56:49 AM PDT 24 Jul 01 10:56:57 AM PDT 24 182040560 ps
T946 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2295849533 Jul 01 10:56:50 AM PDT 24 Jul 01 10:57:02 AM PDT 24 3441068992 ps
T947 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1386509250 Jul 01 10:56:47 AM PDT 24 Jul 01 10:56:54 AM PDT 24 110263123 ps
T948 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2142571218 Jul 01 10:56:48 AM PDT 24 Jul 01 10:57:18 AM PDT 24 1110933737 ps
T949 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2496200999 Jul 01 10:55:24 AM PDT 24 Jul 01 10:55:26 AM PDT 24 169468628 ps
T950 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.3240001515 Jul 01 10:56:52 AM PDT 24 Jul 01 10:57:00 AM PDT 24 826913294 ps
T951 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3087250872 Jul 01 10:56:47 AM PDT 24 Jul 01 10:56:52 AM PDT 24 47195869 ps
T952 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.245517588 Jul 01 10:56:47 AM PDT 24 Jul 01 10:57:04 AM PDT 24 554680599 ps
T953 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.55083975 Jul 01 10:56:43 AM PDT 24 Jul 01 10:56:45 AM PDT 24 45080280 ps
T954 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1297797044 Jul 01 10:55:31 AM PDT 24 Jul 01 10:55:33 AM PDT 24 41551846 ps
T955 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2704447297 Jul 01 10:56:46 AM PDT 24 Jul 01 10:56:51 AM PDT 24 723126475 ps
T956 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.668622976 Jul 01 10:55:21 AM PDT 24 Jul 01 10:55:23 AM PDT 24 46824119 ps
T957 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1744331383 Jul 01 10:56:47 AM PDT 24 Jul 01 10:56:53 AM PDT 24 22371919 ps
T958 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.693107492 Jul 01 10:55:22 AM PDT 24 Jul 01 10:55:26 AM PDT 24 1241428526 ps
T959 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3918292144 Jul 01 10:56:47 AM PDT 24 Jul 01 10:56:53 AM PDT 24 110164927 ps
T960 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1786551101 Jul 01 10:56:45 AM PDT 24 Jul 01 10:56:48 AM PDT 24 12645979 ps
T150 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1656606277 Jul 01 10:56:50 AM PDT 24 Jul 01 10:56:58 AM PDT 24 250779550 ps
T961 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3456733623 Jul 01 10:56:45 AM PDT 24 Jul 01 10:56:48 AM PDT 24 66394330 ps
T962 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.887509680 Jul 01 10:56:53 AM PDT 24 Jul 01 10:56:59 AM PDT 24 67873162 ps
T963 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.611542241 Jul 01 10:56:49 AM PDT 24 Jul 01 10:56:58 AM PDT 24 281724409 ps
T964 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1229529142 Jul 01 10:55:24 AM PDT 24 Jul 01 10:55:26 AM PDT 24 82539339 ps
T965 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2546359648 Jul 01 10:56:49 AM PDT 24 Jul 01 10:56:56 AM PDT 24 36186356 ps
T966 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3069733295 Jul 01 10:56:48 AM PDT 24 Jul 01 10:56:54 AM PDT 24 262111461 ps
T967 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.4124739516 Jul 01 10:55:21 AM PDT 24 Jul 01 10:55:23 AM PDT 24 21011320 ps
T968 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.960045636 Jul 01 10:56:53 AM PDT 24 Jul 01 10:56:59 AM PDT 24 34846182 ps
T211 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1443868517 Jul 01 10:56:49 AM PDT 24 Jul 01 10:56:56 AM PDT 24 61340252 ps
T969 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2812323733 Jul 01 10:56:51 AM PDT 24 Jul 01 10:56:58 AM PDT 24 20957701 ps
T970 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1550125630 Jul 01 10:56:48 AM PDT 24 Jul 01 10:56:57 AM PDT 24 703512028 ps
T971 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.4030817864 Jul 01 10:56:44 AM PDT 24 Jul 01 10:56:50 AM PDT 24 1106856827 ps
T972 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3096625482 Jul 01 10:56:50 AM PDT 24 Jul 01 10:56:57 AM PDT 24 55528638 ps
T149 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.178365181 Jul 01 10:56:52 AM PDT 24 Jul 01 10:57:00 AM PDT 24 153795143 ps
T973 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.16045325 Jul 01 10:55:22 AM PDT 24 Jul 01 10:55:24 AM PDT 24 246797929 ps
T974 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.439526931 Jul 01 10:56:46 AM PDT 24 Jul 01 10:56:51 AM PDT 24 85174355 ps
T975 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.3207424690 Jul 01 10:56:45 AM PDT 24 Jul 01 10:57:27 AM PDT 24 4292186293 ps
T976 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.136008511 Jul 01 10:56:47 AM PDT 24 Jul 01 10:56:54 AM PDT 24 34759855 ps
T977 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2368632064 Jul 01 10:56:52 AM PDT 24 Jul 01 10:56:58 AM PDT 24 26654779 ps
T144 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.3497839958 Jul 01 10:56:50 AM PDT 24 Jul 01 10:56:58 AM PDT 24 153086723 ps
T212 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3031923829 Jul 01 10:56:45 AM PDT 24 Jul 01 10:56:49 AM PDT 24 97625702 ps
T978 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3971048030 Jul 01 10:56:52 AM PDT 24 Jul 01 10:56:58 AM PDT 24 55124182 ps
T979 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3087602214 Jul 01 10:56:48 AM PDT 24 Jul 01 10:56:55 AM PDT 24 131532023 ps
T980 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3077590268 Jul 01 10:56:49 AM PDT 24 Jul 01 10:56:55 AM PDT 24 108751154 ps
T981 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3877789779 Jul 01 10:56:51 AM PDT 24 Jul 01 10:56:59 AM PDT 24 668845233 ps
T982 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3795938119 Jul 01 10:56:49 AM PDT 24 Jul 01 10:56:55 AM PDT 24 68250279 ps
T983 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1282516533 Jul 01 10:56:33 AM PDT 24 Jul 01 10:56:35 AM PDT 24 26337426 ps
T134 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2109611894 Jul 01 10:56:53 AM PDT 24 Jul 01 10:57:00 AM PDT 24 366746330 ps
T984 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2739857754 Jul 01 10:56:46 AM PDT 24 Jul 01 10:56:52 AM PDT 24 543990385 ps
T985 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2641367552 Jul 01 10:56:44 AM PDT 24 Jul 01 10:56:45 AM PDT 24 19052926 ps
T986 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.4274260146 Jul 01 10:56:48 AM PDT 24 Jul 01 10:56:55 AM PDT 24 129721401 ps
T987 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3959534946 Jul 01 10:56:45 AM PDT 24 Jul 01 10:56:49 AM PDT 24 14825400 ps
T988 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3792333794 Jul 01 10:56:46 AM PDT 24 Jul 01 10:56:52 AM PDT 24 99335335 ps
T989 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2631202324 Jul 01 10:56:49 AM PDT 24 Jul 01 10:56:56 AM PDT 24 182030017 ps
T990 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3138852212 Jul 01 10:55:25 AM PDT 24 Jul 01 10:55:26 AM PDT 24 18713207 ps
T991 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.344139132 Jul 01 10:56:50 AM PDT 24 Jul 01 10:57:05 AM PDT 24 964849044 ps
T992 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.747790485 Jul 01 10:56:50 AM PDT 24 Jul 01 10:57:01 AM PDT 24 3196944706 ps
T993 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2927672601 Jul 01 10:56:46 AM PDT 24 Jul 01 10:56:52 AM PDT 24 108492269 ps
T994 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3035703057 Jul 01 10:56:52 AM PDT 24 Jul 01 10:56:58 AM PDT 24 485345365 ps
T995 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1210055947 Jul 01 10:55:21 AM PDT 24 Jul 01 10:55:23 AM PDT 24 56887947 ps
T996 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1272084770 Jul 01 10:56:52 AM PDT 24 Jul 01 10:56:59 AM PDT 24 80924406 ps
T148 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.75558049 Jul 01 10:56:53 AM PDT 24 Jul 01 10:57:00 AM PDT 24 237224432 ps
T997 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2742720612 Jul 01 10:56:53 AM PDT 24 Jul 01 10:56:59 AM PDT 24 96978966 ps
T998 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.4156700866 Jul 01 10:56:45 AM PDT 24 Jul 01 10:56:50 AM PDT 24 21557105 ps

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.2948213909
Short name T11
Test name
Test status
Simulation time 312358826 ps
CPU time 11.39 seconds
Started Jul 01 12:34:06 PM PDT 24
Finished Jul 01 12:34:19 PM PDT 24
Peak memory 218540 kb
Host smart-3b74087a-aad5-4151-b2b5-bde135c0f5ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948213909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
2948213909
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.668126131
Short name T4
Test name
Test status
Simulation time 11677681250 ps
CPU time 193.12 seconds
Started Jul 01 12:34:26 PM PDT 24
Finished Jul 01 12:37:40 PM PDT 24
Peak memory 251368 kb
Host smart-ecba57b6-562b-4891-8613-d1e1efaab2c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668126131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.668126131
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.1878885551
Short name T57
Test name
Test status
Simulation time 2501026910 ps
CPU time 11.91 seconds
Started Jul 01 12:29:50 PM PDT 24
Finished Jul 01 12:30:02 PM PDT 24
Peak memory 218748 kb
Host smart-1664764d-b655-4ba5-b140-980ad95cf2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878885551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.1878885551
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.4164617429
Short name T45
Test name
Test status
Simulation time 1293740809 ps
CPU time 11.21 seconds
Started Jul 01 12:34:41 PM PDT 24
Finished Jul 01 12:34:53 PM PDT 24
Peak memory 226372 kb
Host smart-de74e85f-aa91-4377-af28-f21e07bf9e42
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164617429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.4164617429
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.1980909968
Short name T93
Test name
Test status
Simulation time 43682681836 ps
CPU time 395.91 seconds
Started Jul 01 12:32:57 PM PDT 24
Finished Jul 01 12:39:34 PM PDT 24
Peak memory 317040 kb
Host smart-bbc4d6ea-b5a0-46df-9d09-52983765941e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1980909968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all_with_rand_reset.1980909968
Directory /workspace/24.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4003366871
Short name T152
Test name
Test status
Simulation time 117859904 ps
CPU time 3.73 seconds
Started Jul 01 10:56:45 AM PDT 24
Finished Jul 01 10:56:52 AM PDT 24
Peak memory 222568 kb
Host smart-1bde4e72-3496-4e0e-977e-ddd8eb3e214d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400336
6871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4003366871
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.460966890
Short name T40
Test name
Test status
Simulation time 29276389 ps
CPU time 0.78 seconds
Started Jul 01 12:32:43 PM PDT 24
Finished Jul 01 12:32:44 PM PDT 24
Peak memory 209140 kb
Host smart-a9d21ef3-2c82-4631-b647-467de968e2f5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460966890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ct
rl_volatile_unlock_smoke.460966890
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.546235423
Short name T118
Test name
Test status
Simulation time 565970487232 ps
CPU time 2342.03 seconds
Started Jul 01 12:28:42 PM PDT 24
Finished Jul 01 01:07:46 PM PDT 24
Peak memory 957600 kb
Host smart-71d8da58-20a2-4ce3-a95d-78fe2999a405
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=546235423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all_with_rand_reset.546235423
Directory /workspace/1.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.2264096039
Short name T59
Test name
Test status
Simulation time 111140917 ps
CPU time 22.76 seconds
Started Jul 01 12:29:25 PM PDT 24
Finished Jul 01 12:29:49 PM PDT 24
Peak memory 284552 kb
Host smart-f42e6c29-dcf0-4441-bcca-a50bf649b859
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264096039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.2264096039
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.1036828111
Short name T19
Test name
Test status
Simulation time 14603720584 ps
CPU time 83.59 seconds
Started Jul 01 12:31:16 PM PDT 24
Finished Jul 01 12:32:41 PM PDT 24
Peak memory 276180 kb
Host smart-91670861-3592-458a-96ec-25b239e64bb6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036828111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.1036828111
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2692540188
Short name T123
Test name
Test status
Simulation time 97642102 ps
CPU time 2.6 seconds
Started Jul 01 10:56:46 AM PDT 24
Finished Jul 01 10:56:53 AM PDT 24
Peak memory 222332 kb
Host smart-ff527f32-acac-4792-82c3-76e011995b68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692540188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.2692540188
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.2442040509
Short name T183
Test name
Test status
Simulation time 1330428335 ps
CPU time 15.69 seconds
Started Jul 01 12:34:03 PM PDT 24
Finished Jul 01 12:34:20 PM PDT 24
Peak memory 218632 kb
Host smart-aa4dd073-9006-4fdf-b922-ccee3764b47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442040509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.2442040509
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.626537123
Short name T23
Test name
Test status
Simulation time 3890208908 ps
CPU time 9.89 seconds
Started Jul 01 12:33:39 PM PDT 24
Finished Jul 01 12:33:50 PM PDT 24
Peak memory 218096 kb
Host smart-b9e065be-153f-4a96-809d-0552d1796a9e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626537123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.626537123
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.208216104
Short name T10
Test name
Test status
Simulation time 70240963 ps
CPU time 1.15 seconds
Started Jul 01 12:30:02 PM PDT 24
Finished Jul 01 12:30:04 PM PDT 24
Peak memory 209376 kb
Host smart-df227492-3652-47d2-81a1-bbb1119100f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208216104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.208216104
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.587703322
Short name T204
Test name
Test status
Simulation time 16968330 ps
CPU time 0.91 seconds
Started Jul 01 10:56:53 AM PDT 24
Finished Jul 01 10:56:59 AM PDT 24
Peak memory 208556 kb
Host smart-83d2d697-983f-4cf2-a968-884a9681250e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587703322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.587703322
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.3256089166
Short name T17
Test name
Test status
Simulation time 17715045043 ps
CPU time 293.31 seconds
Started Jul 01 12:31:56 PM PDT 24
Finished Jul 01 12:36:50 PM PDT 24
Peak memory 259572 kb
Host smart-c6645204-a2c6-40f3-9fd6-28f6e848ce96
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256089166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.3256089166
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3938160761
Short name T888
Test name
Test status
Simulation time 93979441 ps
CPU time 1.78 seconds
Started Jul 01 10:56:52 AM PDT 24
Finished Jul 01 10:56:59 AM PDT 24
Peak memory 217184 kb
Host smart-a52c51db-70e8-47c0-91fe-bc42a17ac86c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938160761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.3938160761
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.3603884718
Short name T58
Test name
Test status
Simulation time 271000015 ps
CPU time 6.71 seconds
Started Jul 01 12:33:35 PM PDT 24
Finished Jul 01 12:33:42 PM PDT 24
Peak memory 218604 kb
Host smart-ee0ee2ca-258b-4c37-8aba-7f0c7d6cf3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603884718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.3603884718
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.3748534337
Short name T43
Test name
Test status
Simulation time 266442302 ps
CPU time 12.49 seconds
Started Jul 01 12:33:07 PM PDT 24
Finished Jul 01 12:33:20 PM PDT 24
Peak memory 226464 kb
Host smart-6c27c201-d1e5-4876-b617-cb8cc20b8a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748534337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.3748534337
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1233329293
Short name T142
Test name
Test status
Simulation time 530464003 ps
CPU time 4.21 seconds
Started Jul 01 10:56:53 AM PDT 24
Finished Jul 01 10:57:02 AM PDT 24
Peak memory 217316 kb
Host smart-6a4cd075-926d-4910-9724-75fefcddd969
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233329293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.1233329293
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2109611894
Short name T134
Test name
Test status
Simulation time 366746330 ps
CPU time 1.95 seconds
Started Jul 01 10:56:53 AM PDT 24
Finished Jul 01 10:57:00 AM PDT 24
Peak memory 216780 kb
Host smart-4852e710-9970-46d5-8bd6-2f02441a2658
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109611894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.2109611894
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.3497839958
Short name T144
Test name
Test status
Simulation time 153086723 ps
CPU time 2.56 seconds
Started Jul 01 10:56:50 AM PDT 24
Finished Jul 01 10:56:58 AM PDT 24
Peak memory 221916 kb
Host smart-557e27d4-a432-4c4a-a0b6-8ed179e1f2e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497839958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.3497839958
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.380695490
Short name T217
Test name
Test status
Simulation time 584812739 ps
CPU time 1.2 seconds
Started Jul 01 10:55:23 AM PDT 24
Finished Jul 01 10:55:25 AM PDT 24
Peak memory 209128 kb
Host smart-4326368e-78f6-4845-adee-af1ee3c8ab7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380695490 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.380695490
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.588546947
Short name T98
Test name
Test status
Simulation time 14229212394 ps
CPU time 414.47 seconds
Started Jul 01 12:31:06 PM PDT 24
Finished Jul 01 12:38:01 PM PDT 24
Peak memory 480940 kb
Host smart-116bf26b-37da-445b-ae64-65381df28c5c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=588546947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.588546947
Directory /workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.1349430129
Short name T61
Test name
Test status
Simulation time 314860928 ps
CPU time 30.44 seconds
Started Jul 01 12:33:16 PM PDT 24
Finished Jul 01 12:33:47 PM PDT 24
Peak memory 251364 kb
Host smart-7342109e-3091-492a-a508-95266562e622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349430129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.1349430129
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.4286321077
Short name T895
Test name
Test status
Simulation time 312107938 ps
CPU time 3.06 seconds
Started Jul 01 10:56:45 AM PDT 24
Finished Jul 01 10:56:50 AM PDT 24
Peak memory 217212 kb
Host smart-b5f916e8-c43c-4ee3-8885-69a96f6fbbdd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286321077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.4286321077
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.387965038
Short name T138
Test name
Test status
Simulation time 119899530 ps
CPU time 2.05 seconds
Started Jul 01 10:56:56 AM PDT 24
Finished Jul 01 10:57:02 AM PDT 24
Peak memory 221756 kb
Host smart-0c2bf770-7fc3-47fb-bee0-dca5499a6784
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387965038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg_
err.387965038
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1847126732
Short name T140
Test name
Test status
Simulation time 541104824 ps
CPU time 3.04 seconds
Started Jul 01 10:56:47 AM PDT 24
Finished Jul 01 10:56:55 AM PDT 24
Peak memory 217252 kb
Host smart-e19d4f7d-b63c-450f-91ed-53a110024260
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847126732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.1847126732
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.2284190351
Short name T195
Test name
Test status
Simulation time 16311443 ps
CPU time 0.98 seconds
Started Jul 01 12:27:58 PM PDT 24
Finished Jul 01 12:27:59 PM PDT 24
Peak memory 209352 kb
Host smart-8455f41d-062c-45bb-8a66-95fa346af839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284190351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.2284190351
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.3627792239
Short name T274
Test name
Test status
Simulation time 279086310 ps
CPU time 10.64 seconds
Started Jul 01 12:32:10 PM PDT 24
Finished Jul 01 12:32:21 PM PDT 24
Peak memory 226440 kb
Host smart-fcc620e8-f5b3-41bf-8314-0346b4293bc1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627792239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.3627792239
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.2677172300
Short name T75
Test name
Test status
Simulation time 32076175 ps
CPU time 0.92 seconds
Started Jul 01 12:28:51 PM PDT 24
Finished Jul 01 12:28:53 PM PDT 24
Peak memory 209376 kb
Host smart-c412697c-94cc-4569-8710-b6050c7f89c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677172300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.2677172300
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.2930005390
Short name T225
Test name
Test status
Simulation time 14414343 ps
CPU time 0.84 seconds
Started Jul 01 12:29:13 PM PDT 24
Finished Jul 01 12:29:15 PM PDT 24
Peak memory 209088 kb
Host smart-f553b2a4-b211-4d8b-b656-3046f953490c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930005390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.2930005390
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.3650727501
Short name T224
Test name
Test status
Simulation time 30407571 ps
CPU time 0.83 seconds
Started Jul 01 12:29:58 PM PDT 24
Finished Jul 01 12:30:00 PM PDT 24
Peak memory 209224 kb
Host smart-14f8fee5-a30f-4056-8a62-8fc35e05f8ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650727501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.3650727501
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.1182067506
Short name T164
Test name
Test status
Simulation time 13138380 ps
CPU time 0.84 seconds
Started Jul 01 12:30:06 PM PDT 24
Finished Jul 01 12:30:07 PM PDT 24
Peak memory 209276 kb
Host smart-c46438c9-4722-4740-9c82-8a13136f6223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182067506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.1182067506
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.2994237911
Short name T18
Test name
Test status
Simulation time 346723164 ps
CPU time 10.57 seconds
Started Jul 01 12:28:00 PM PDT 24
Finished Jul 01 12:28:11 PM PDT 24
Peak memory 251232 kb
Host smart-758ab291-51d5-466b-809f-3e91b67ef9dd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994237911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.2994237911
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1656606277
Short name T150
Test name
Test status
Simulation time 250779550 ps
CPU time 2.48 seconds
Started Jul 01 10:56:50 AM PDT 24
Finished Jul 01 10:56:58 AM PDT 24
Peak memory 217208 kb
Host smart-0d86bf81-3674-4f39-9935-8ac137ce12ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656606277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.1656606277
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1127784353
Short name T130
Test name
Test status
Simulation time 240461936 ps
CPU time 1.95 seconds
Started Jul 01 10:56:45 AM PDT 24
Finished Jul 01 10:56:50 AM PDT 24
Peak memory 221200 kb
Host smart-f13637c5-b4a1-495b-99ff-b1bdc1e323e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127784353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.1127784353
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.178365181
Short name T149
Test name
Test status
Simulation time 153795143 ps
CPU time 2.5 seconds
Started Jul 01 10:56:52 AM PDT 24
Finished Jul 01 10:57:00 AM PDT 24
Peak memory 217220 kb
Host smart-82bddb0b-1a30-4ed0-83d9-e1f483547bf8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178365181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg_
err.178365181
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1922684184
Short name T139
Test name
Test status
Simulation time 187914317 ps
CPU time 2.73 seconds
Started Jul 01 10:56:50 AM PDT 24
Finished Jul 01 10:56:58 AM PDT 24
Peak memory 222128 kb
Host smart-cebc65f9-eebf-4362-8f4f-c2829342facd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922684184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.1922684184
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3855405150
Short name T145
Test name
Test status
Simulation time 162066412 ps
CPU time 2.15 seconds
Started Jul 01 10:56:45 AM PDT 24
Finished Jul 01 10:56:50 AM PDT 24
Peak memory 221504 kb
Host smart-df2641ca-3fd8-40f2-88e8-933c9530e157
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855405150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.3855405150
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.75558049
Short name T148
Test name
Test status
Simulation time 237224432 ps
CPU time 2.54 seconds
Started Jul 01 10:56:53 AM PDT 24
Finished Jul 01 10:57:00 AM PDT 24
Peak memory 216832 kb
Host smart-706a5182-7cae-4d96-afed-893c79a6488f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75558049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_er
r.75558049
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.1914045271
Short name T52
Test name
Test status
Simulation time 1713345660 ps
CPU time 13.67 seconds
Started Jul 01 12:30:12 PM PDT 24
Finished Jul 01 12:30:26 PM PDT 24
Peak memory 218592 kb
Host smart-c73a34df-5e8a-4709-8ba9-b3fa81b9b022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914045271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.1914045271
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.3901277654
Short name T12
Test name
Test status
Simulation time 49277766 ps
CPU time 2.58 seconds
Started Jul 01 12:31:55 PM PDT 24
Finished Jul 01 12:31:58 PM PDT 24
Peak memory 218020 kb
Host smart-f313b5e6-6e3e-4836-b012-db0b6379c2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901277654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.3901277654
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.2773787462
Short name T292
Test name
Test status
Simulation time 355241613 ps
CPU time 3.87 seconds
Started Jul 01 12:27:51 PM PDT 24
Finished Jul 01 12:27:55 PM PDT 24
Peak memory 222684 kb
Host smart-bf50c512-f673-4423-bff8-fe16a41d0712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773787462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.2773787462
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1229529142
Short name T964
Test name
Test status
Simulation time 82539339 ps
CPU time 1.25 seconds
Started Jul 01 10:55:24 AM PDT 24
Finished Jul 01 10:55:26 AM PDT 24
Peak memory 209036 kb
Host smart-e3000df0-8c54-474a-9abd-6172a4a56053
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229529142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.1229529142
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1809439900
Short name T892
Test name
Test status
Simulation time 70656133 ps
CPU time 1.14 seconds
Started Jul 01 10:55:23 AM PDT 24
Finished Jul 01 10:55:25 AM PDT 24
Peak memory 209016 kb
Host smart-32ea0d56-887b-4358-9c97-ba9851616fc5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809439900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.1809439900
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.3023891668
Short name T882
Test name
Test status
Simulation time 37756948 ps
CPU time 1.24 seconds
Started Jul 01 10:55:24 AM PDT 24
Finished Jul 01 10:55:26 AM PDT 24
Peak memory 217804 kb
Host smart-9b045a72-1b8f-4a9a-a640-230722ef90a1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023891668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.3023891668
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1210055947
Short name T995
Test name
Test status
Simulation time 56887947 ps
CPU time 1.17 seconds
Started Jul 01 10:55:21 AM PDT 24
Finished Jul 01 10:55:23 AM PDT 24
Peak memory 217264 kb
Host smart-c13990c3-f7e6-4458-9853-7f52e15b0e9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210055947 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.1210055947
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3389397422
Short name T203
Test name
Test status
Simulation time 47042221 ps
CPU time 0.98 seconds
Started Jul 01 10:55:23 AM PDT 24
Finished Jul 01 10:55:24 AM PDT 24
Peak memory 209068 kb
Host smart-f482e611-d7c9-4cd8-b627-c28da9546451
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389397422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.3389397422
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3138852212
Short name T990
Test name
Test status
Simulation time 18713207 ps
CPU time 1.06 seconds
Started Jul 01 10:55:25 AM PDT 24
Finished Jul 01 10:55:26 AM PDT 24
Peak memory 208388 kb
Host smart-5bbcea1d-2b60-4fa5-8589-4d9fcff41767
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138852212 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.3138852212
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3022536673
Short name T155
Test name
Test status
Simulation time 228448010 ps
CPU time 6.05 seconds
Started Jul 01 10:55:17 AM PDT 24
Finished Jul 01 10:55:23 AM PDT 24
Peak memory 208720 kb
Host smart-de6cba30-9776-4233-bc27-9f3bb8dc1654
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022536673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.3022536673
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.4183420321
Short name T923
Test name
Test status
Simulation time 706612769 ps
CPU time 4.78 seconds
Started Jul 01 10:55:15 AM PDT 24
Finished Jul 01 10:55:21 AM PDT 24
Peak memory 216744 kb
Host smart-c9e811ee-f8c2-4220-8604-bcabec2ca3b7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183420321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.4183420321
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.341986188
Short name T939
Test name
Test status
Simulation time 992038197 ps
CPU time 3.05 seconds
Started Jul 01 10:55:17 AM PDT 24
Finished Jul 01 10:55:21 AM PDT 24
Peak memory 217212 kb
Host smart-426200ac-2009-40b5-970a-6674e7c233ad
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341986188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.341986188
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.357234358
Short name T122
Test name
Test status
Simulation time 52794066 ps
CPU time 1.5 seconds
Started Jul 01 10:55:23 AM PDT 24
Finished Jul 01 10:55:25 AM PDT 24
Peak memory 218344 kb
Host smart-2c5ca658-3fd8-4850-a56b-befe0b3d4cf6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357234
358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.357234358
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1187307966
Short name T914
Test name
Test status
Simulation time 256568051 ps
CPU time 1.33 seconds
Started Jul 01 10:55:20 AM PDT 24
Finished Jul 01 10:55:21 AM PDT 24
Peak memory 209008 kb
Host smart-6ba6bf08-415b-410b-9350-ff9e08914a2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187307966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.1187307966
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.4124739516
Short name T967
Test name
Test status
Simulation time 21011320 ps
CPU time 1.23 seconds
Started Jul 01 10:55:21 AM PDT 24
Finished Jul 01 10:55:23 AM PDT 24
Peak memory 211116 kb
Host smart-af35f6e8-e042-4595-9d75-468936606291
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124739516 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.4124739516
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.668622976
Short name T956
Test name
Test status
Simulation time 46824119 ps
CPU time 1.06 seconds
Started Jul 01 10:55:21 AM PDT 24
Finished Jul 01 10:55:23 AM PDT 24
Peak memory 209072 kb
Host smart-9e839915-8f7d-43c6-99ff-bb47a2e7e58c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668622976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
same_csr_outstanding.668622976
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.693107492
Short name T958
Test name
Test status
Simulation time 1241428526 ps
CPU time 2.54 seconds
Started Jul 01 10:55:22 AM PDT 24
Finished Jul 01 10:55:26 AM PDT 24
Peak memory 217504 kb
Host smart-9d46a3d6-73ff-458e-a8dd-7ccef6e0fa84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693107492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.693107492
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.726716484
Short name T146
Test name
Test status
Simulation time 480196333 ps
CPU time 2.69 seconds
Started Jul 01 10:55:22 AM PDT 24
Finished Jul 01 10:55:26 AM PDT 24
Peak memory 217208 kb
Host smart-da571fa5-ef65-47c3-8e9d-b6318bab45bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726716484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_e
rr.726716484
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1282516533
Short name T983
Test name
Test status
Simulation time 26337426 ps
CPU time 1.07 seconds
Started Jul 01 10:56:33 AM PDT 24
Finished Jul 01 10:56:35 AM PDT 24
Peak memory 209056 kb
Host smart-4438ef8e-8748-4c1c-ba56-ffc85ae7b21c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282516533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.1282516533
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1490149279
Short name T898
Test name
Test status
Simulation time 131272408 ps
CPU time 2.67 seconds
Started Jul 01 10:56:32 AM PDT 24
Finished Jul 01 10:56:36 AM PDT 24
Peak memory 217240 kb
Host smart-78359335-b469-4ca5-bbbe-49c3352c91de
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490149279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.1490149279
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.532408438
Short name T925
Test name
Test status
Simulation time 12873178 ps
CPU time 1.05 seconds
Started Jul 01 10:55:30 AM PDT 24
Finished Jul 01 10:55:31 AM PDT 24
Peak memory 209668 kb
Host smart-333566e2-9731-48db-84eb-c3be347e33c3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532408438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_reset
.532408438
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3974319897
Short name T927
Test name
Test status
Simulation time 20178498 ps
CPU time 1.66 seconds
Started Jul 01 10:56:33 AM PDT 24
Finished Jul 01 10:56:35 AM PDT 24
Peak memory 218584 kb
Host smart-519262de-03c0-498b-be14-603865723ebf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974319897 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.3974319897
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1297797044
Short name T954
Test name
Test status
Simulation time 41551846 ps
CPU time 0.97 seconds
Started Jul 01 10:55:31 AM PDT 24
Finished Jul 01 10:55:33 AM PDT 24
Peak memory 209004 kb
Host smart-fbcb0bc6-8686-4a67-a717-0f3f893a379e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297797044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.1297797044
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.4235916467
Short name T881
Test name
Test status
Simulation time 1124780602 ps
CPU time 1.3 seconds
Started Jul 01 10:55:30 AM PDT 24
Finished Jul 01 10:55:31 AM PDT 24
Peak memory 208920 kb
Host smart-183472e5-1200-4035-b570-4602d4b877b8
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235916467 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.4235916467
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2447545257
Short name T904
Test name
Test status
Simulation time 954379143 ps
CPU time 5.63 seconds
Started Jul 01 10:55:21 AM PDT 24
Finished Jul 01 10:55:27 AM PDT 24
Peak memory 208704 kb
Host smart-32ab9f77-aa50-4a03-872a-7943464d8370
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447545257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.2447545257
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.713859045
Short name T876
Test name
Test status
Simulation time 3445262628 ps
CPU time 9.9 seconds
Started Jul 01 10:55:22 AM PDT 24
Finished Jul 01 10:55:32 AM PDT 24
Peak memory 208976 kb
Host smart-f2fd1d19-1b8a-4b96-a4cb-5b50f49829ba
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713859045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.713859045
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1981413787
Short name T928
Test name
Test status
Simulation time 207805017 ps
CPU time 5.13 seconds
Started Jul 01 10:55:23 AM PDT 24
Finished Jul 01 10:55:29 AM PDT 24
Peak memory 210644 kb
Host smart-4724ddfb-c4ae-4021-be85-2b1854b351a8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981413787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.1981413787
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2496200999
Short name T949
Test name
Test status
Simulation time 169468628 ps
CPU time 1.66 seconds
Started Jul 01 10:55:24 AM PDT 24
Finished Jul 01 10:55:26 AM PDT 24
Peak memory 218432 kb
Host smart-a091d48d-a8c4-45bd-985a-9e6f1094e5de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249620
0999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2496200999
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.16045325
Short name T973
Test name
Test status
Simulation time 246797929 ps
CPU time 1.26 seconds
Started Jul 01 10:55:22 AM PDT 24
Finished Jul 01 10:55:24 AM PDT 24
Peak memory 208884 kb
Host smart-06bf6eba-caab-458d-98a8-a5018fc39161
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16045325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test
+UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 1.lc_ctrl_jtag_csr_rw.16045325
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.681756240
Short name T919
Test name
Test status
Simulation time 20132711 ps
CPU time 1.53 seconds
Started Jul 01 10:56:33 AM PDT 24
Finished Jul 01 10:56:35 AM PDT 24
Peak memory 211360 kb
Host smart-62416c62-e4c9-4e2a-85e8-968efa9c7182
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681756240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
same_csr_outstanding.681756240
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3499923762
Short name T911
Test name
Test status
Simulation time 94413127 ps
CPU time 2.72 seconds
Started Jul 01 10:55:29 AM PDT 24
Finished Jul 01 10:55:32 AM PDT 24
Peak memory 217316 kb
Host smart-83bb8346-9c57-46fd-865b-2fbf97224358
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499923762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.3499923762
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3752358516
Short name T226
Test name
Test status
Simulation time 65849036 ps
CPU time 1.88 seconds
Started Jul 01 10:55:31 AM PDT 24
Finished Jul 01 10:55:34 AM PDT 24
Peak memory 221356 kb
Host smart-e689bb02-ed89-44e5-9903-e83d65028880
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752358516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.3752358516
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1040455809
Short name T894
Test name
Test status
Simulation time 92938085 ps
CPU time 1.25 seconds
Started Jul 01 10:56:53 AM PDT 24
Finished Jul 01 10:56:59 AM PDT 24
Peak memory 217400 kb
Host smart-c7b789a1-664e-4341-84ec-8b61df5cf5e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040455809 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.1040455809
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1611637805
Short name T922
Test name
Test status
Simulation time 17112773 ps
CPU time 0.92 seconds
Started Jul 01 10:56:48 AM PDT 24
Finished Jul 01 10:56:54 AM PDT 24
Peak memory 209048 kb
Host smart-24c75929-5a67-4d30-818d-f70834287a9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611637805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.1611637805
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3035703057
Short name T994
Test name
Test status
Simulation time 485345365 ps
CPU time 1.35 seconds
Started Jul 01 10:56:52 AM PDT 24
Finished Jul 01 10:56:58 AM PDT 24
Peak memory 211176 kb
Host smart-def65784-0d86-44dc-a628-e9731b636071
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035703057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.3035703057
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1548976074
Short name T121
Test name
Test status
Simulation time 319957890 ps
CPU time 4.22 seconds
Started Jul 01 10:56:49 AM PDT 24
Finished Jul 01 10:56:59 AM PDT 24
Peak memory 217328 kb
Host smart-0569bbae-555f-4521-bd7a-9690d897e538
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548976074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.1548976074
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.467448574
Short name T137
Test name
Test status
Simulation time 213715972 ps
CPU time 1.42 seconds
Started Jul 01 10:56:52 AM PDT 24
Finished Jul 01 10:56:59 AM PDT 24
Peak memory 217396 kb
Host smart-90437acb-a16a-41e2-80be-c11677bbf38e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467448574 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.467448574
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1272084770
Short name T996
Test name
Test status
Simulation time 80924406 ps
CPU time 1.94 seconds
Started Jul 01 10:56:52 AM PDT 24
Finished Jul 01 10:56:59 AM PDT 24
Peak memory 211196 kb
Host smart-b577a008-545d-4534-ac48-cc864186b434
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272084770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.1272084770
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2742720612
Short name T997
Test name
Test status
Simulation time 96978966 ps
CPU time 1.69 seconds
Started Jul 01 10:56:53 AM PDT 24
Finished Jul 01 10:56:59 AM PDT 24
Peak memory 218208 kb
Host smart-e2174d5e-ac6c-49fa-be5b-a2eaf2ae1bdf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742720612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.2742720612
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1744331383
Short name T957
Test name
Test status
Simulation time 22371919 ps
CPU time 1.61 seconds
Started Jul 01 10:56:47 AM PDT 24
Finished Jul 01 10:56:53 AM PDT 24
Peak memory 217424 kb
Host smart-6b42d54a-d005-4389-81f7-c5e8fe15dd87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744331383 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.1744331383
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1377701888
Short name T202
Test name
Test status
Simulation time 14196454 ps
CPU time 0.88 seconds
Started Jul 01 10:56:53 AM PDT 24
Finished Jul 01 10:56:59 AM PDT 24
Peak memory 209024 kb
Host smart-cba5b181-3e9c-4ad9-b6b9-0f2110a3442d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377701888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.1377701888
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2368632064
Short name T977
Test name
Test status
Simulation time 26654779 ps
CPU time 1.32 seconds
Started Jul 01 10:56:52 AM PDT 24
Finished Jul 01 10:56:58 AM PDT 24
Peak memory 209048 kb
Host smart-29a3f837-59a0-4efd-a23f-d62198339e4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368632064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.2368632064
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.4003171125
Short name T120
Test name
Test status
Simulation time 93628030 ps
CPU time 3.82 seconds
Started Jul 01 10:56:48 AM PDT 24
Finished Jul 01 10:56:56 AM PDT 24
Peak memory 217240 kb
Host smart-1745e542-34be-47f3-95ec-ef356ca7f367
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003171125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.4003171125
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1460059504
Short name T921
Test name
Test status
Simulation time 33812232 ps
CPU time 1.77 seconds
Started Jul 01 10:56:58 AM PDT 24
Finished Jul 01 10:57:02 AM PDT 24
Peak memory 218660 kb
Host smart-26687223-db0d-4665-a4e7-5d55ea084efb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460059504 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.1460059504
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3746371957
Short name T208
Test name
Test status
Simulation time 11999093 ps
CPU time 0.95 seconds
Started Jul 01 10:56:44 AM PDT 24
Finished Jul 01 10:56:47 AM PDT 24
Peak memory 208560 kb
Host smart-6b7a7023-b119-4fcd-a617-1c16b88509cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746371957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.3746371957
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3577245807
Short name T214
Test name
Test status
Simulation time 22934735 ps
CPU time 1.05 seconds
Started Jul 01 10:56:46 AM PDT 24
Finished Jul 01 10:56:51 AM PDT 24
Peak memory 217204 kb
Host smart-bcaa448a-b110-4022-9f8d-5a333b3e81e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577245807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.3577245807
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3440221455
Short name T933
Test name
Test status
Simulation time 58770925 ps
CPU time 2.69 seconds
Started Jul 01 10:56:45 AM PDT 24
Finished Jul 01 10:56:51 AM PDT 24
Peak memory 217268 kb
Host smart-97821a91-9e37-410f-b096-3bb4a52f2936
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440221455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.3440221455
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3435298671
Short name T143
Test name
Test status
Simulation time 117674547 ps
CPU time 4.32 seconds
Started Jul 01 10:56:45 AM PDT 24
Finished Jul 01 10:56:52 AM PDT 24
Peak memory 217388 kb
Host smart-4cc997e1-b1e1-44c8-9f2c-e08dd63d4c05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435298671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.3435298671
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3792333794
Short name T988
Test name
Test status
Simulation time 99335335 ps
CPU time 1.94 seconds
Started Jul 01 10:56:46 AM PDT 24
Finished Jul 01 10:56:52 AM PDT 24
Peak memory 217256 kb
Host smart-ade16bb0-2ea3-4d94-8af6-374145098deb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792333794 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.3792333794
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1183206382
Short name T127
Test name
Test status
Simulation time 37010949 ps
CPU time 0.96 seconds
Started Jul 01 10:56:47 AM PDT 24
Finished Jul 01 10:56:52 AM PDT 24
Peak memory 208384 kb
Host smart-d30d5edd-d375-4bbc-91cc-1f0cbf1ab45e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183206382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.1183206382
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3918292144
Short name T959
Test name
Test status
Simulation time 110164927 ps
CPU time 1.13 seconds
Started Jul 01 10:56:47 AM PDT 24
Finished Jul 01 10:56:53 AM PDT 24
Peak memory 217264 kb
Host smart-d34e9af8-fbac-45b5-8cb4-af532cb5cfe3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918292144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.3918292144
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3677749224
Short name T174
Test name
Test status
Simulation time 20781051 ps
CPU time 1.19 seconds
Started Jul 01 10:56:52 AM PDT 24
Finished Jul 01 10:56:58 AM PDT 24
Peak memory 217456 kb
Host smart-b37e550f-21a6-495a-b671-8b996236ebe0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677749224 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.3677749224
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3448560002
Short name T891
Test name
Test status
Simulation time 24394305 ps
CPU time 0.99 seconds
Started Jul 01 10:56:52 AM PDT 24
Finished Jul 01 10:56:58 AM PDT 24
Peak memory 209052 kb
Host smart-d4b2a961-dd59-43cd-8b42-e7048177dabd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448560002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.3448560002
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.38237531
Short name T931
Test name
Test status
Simulation time 143536465 ps
CPU time 1.71 seconds
Started Jul 01 10:56:53 AM PDT 24
Finished Jul 01 10:56:59 AM PDT 24
Peak memory 217236 kb
Host smart-1db207b0-41f3-47e1-9883-c87ea187c550
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38237531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_
same_csr_outstanding.38237531
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.4174719114
Short name T929
Test name
Test status
Simulation time 328125184 ps
CPU time 2.34 seconds
Started Jul 01 10:56:50 AM PDT 24
Finished Jul 01 10:56:58 AM PDT 24
Peak memory 217196 kb
Host smart-29998319-5f7e-4dc9-b396-ae7cf65f63d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174719114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.4174719114
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.72707335
Short name T913
Test name
Test status
Simulation time 26464678 ps
CPU time 1.28 seconds
Started Jul 01 10:56:53 AM PDT 24
Finished Jul 01 10:56:59 AM PDT 24
Peak memory 217320 kb
Host smart-563377ee-5db2-4e67-b4eb-28b455a45dbf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72707335 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.72707335
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.847019260
Short name T908
Test name
Test status
Simulation time 66506122 ps
CPU time 0.82 seconds
Started Jul 01 10:56:52 AM PDT 24
Finished Jul 01 10:56:58 AM PDT 24
Peak memory 208564 kb
Host smart-86b93c2b-7f6f-44ef-a5aa-0918e47ceaba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847019260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.847019260
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2812323733
Short name T969
Test name
Test status
Simulation time 20957701 ps
CPU time 1.43 seconds
Started Jul 01 10:56:51 AM PDT 24
Finished Jul 01 10:56:58 AM PDT 24
Peak memory 217268 kb
Host smart-5b8f5317-e35f-41b6-bb55-6d01b2b5bb6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812323733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.2812323733
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3632938948
Short name T896
Test name
Test status
Simulation time 52622791 ps
CPU time 1.89 seconds
Started Jul 01 10:56:52 AM PDT 24
Finished Jul 01 10:56:58 AM PDT 24
Peak memory 218204 kb
Host smart-819edb71-d6f4-4bc5-9414-b79fc43e43c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632938948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.3632938948
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2023599602
Short name T147
Test name
Test status
Simulation time 73214024 ps
CPU time 1.99 seconds
Started Jul 01 10:56:50 AM PDT 24
Finished Jul 01 10:56:57 AM PDT 24
Peak memory 217240 kb
Host smart-f55164d2-a6b7-48ec-9285-a78d6b04f9e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023599602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.2023599602
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.887509680
Short name T962
Test name
Test status
Simulation time 67873162 ps
CPU time 1.22 seconds
Started Jul 01 10:56:53 AM PDT 24
Finished Jul 01 10:56:59 AM PDT 24
Peak memory 217556 kb
Host smart-5933aef5-ff43-4ddc-ba4f-98ae4d91b3e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887509680 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.887509680
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1414231107
Short name T874
Test name
Test status
Simulation time 35967709 ps
CPU time 0.89 seconds
Started Jul 01 10:56:53 AM PDT 24
Finished Jul 01 10:56:59 AM PDT 24
Peak memory 208676 kb
Host smart-2dbd11e2-c1c0-43d6-ab1f-031a4fe421cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414231107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.1414231107
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.960045636
Short name T968
Test name
Test status
Simulation time 34846182 ps
CPU time 1.5 seconds
Started Jul 01 10:56:53 AM PDT 24
Finished Jul 01 10:56:59 AM PDT 24
Peak memory 208752 kb
Host smart-362f4179-0c7d-45f4-9771-b1fcbbb49c0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960045636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_same_csr_outstanding.960045636
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3413044490
Short name T889
Test name
Test status
Simulation time 417755287 ps
CPU time 3.01 seconds
Started Jul 01 10:56:52 AM PDT 24
Finished Jul 01 10:57:00 AM PDT 24
Peak memory 217264 kb
Host smart-f8ed5486-c0ff-4f1a-bad7-63b87737837b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413044490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.3413044490
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2032206494
Short name T124
Test name
Test status
Simulation time 266046375 ps
CPU time 3.12 seconds
Started Jul 01 10:56:53 AM PDT 24
Finished Jul 01 10:57:01 AM PDT 24
Peak memory 221964 kb
Host smart-186b6520-0790-4248-8efe-5296f5dd349c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032206494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.2032206494
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3971048030
Short name T978
Test name
Test status
Simulation time 55124182 ps
CPU time 1.35 seconds
Started Jul 01 10:56:52 AM PDT 24
Finished Jul 01 10:56:58 AM PDT 24
Peak memory 217392 kb
Host smart-88921063-547d-45ed-a78b-d6a901dea4bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971048030 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.3971048030
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1588615502
Short name T205
Test name
Test status
Simulation time 30186682 ps
CPU time 0.89 seconds
Started Jul 01 10:56:52 AM PDT 24
Finished Jul 01 10:56:58 AM PDT 24
Peak memory 209036 kb
Host smart-6718cdf3-ee74-4063-9ac1-0089c3217467
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588615502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.1588615502
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3064112396
Short name T924
Test name
Test status
Simulation time 102838002 ps
CPU time 1.12 seconds
Started Jul 01 10:56:52 AM PDT 24
Finished Jul 01 10:56:58 AM PDT 24
Peak memory 209036 kb
Host smart-11d2e3cc-22a7-4c9a-9182-f5165bcb634f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064112396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.3064112396
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3877789779
Short name T981
Test name
Test status
Simulation time 668845233 ps
CPU time 2.54 seconds
Started Jul 01 10:56:51 AM PDT 24
Finished Jul 01 10:56:59 AM PDT 24
Peak memory 218760 kb
Host smart-71bdb09a-5b97-4797-9e0e-7c04b93e749f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877789779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.3877789779
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1527817629
Short name T132
Test name
Test status
Simulation time 96754536 ps
CPU time 1.59 seconds
Started Jul 01 10:56:56 AM PDT 24
Finished Jul 01 10:57:01 AM PDT 24
Peak memory 217736 kb
Host smart-ca780659-ed8e-4de5-a0e6-e5fbecbd0cb0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527817629 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.1527817629
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2381652950
Short name T201
Test name
Test status
Simulation time 13773279 ps
CPU time 1.02 seconds
Started Jul 01 10:56:56 AM PDT 24
Finished Jul 01 10:57:01 AM PDT 24
Peak memory 209072 kb
Host smart-f97b8351-34e8-4708-ad00-5542c751adc5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381652950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.2381652950
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2783792690
Short name T213
Test name
Test status
Simulation time 57865880 ps
CPU time 1.18 seconds
Started Jul 01 10:56:57 AM PDT 24
Finished Jul 01 10:57:01 AM PDT 24
Peak memory 209040 kb
Host smart-224ca920-dc35-4204-bacb-a555b8e17b33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783792690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.2783792690
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.4155735844
Short name T141
Test name
Test status
Simulation time 587577761 ps
CPU time 5.84 seconds
Started Jul 01 10:56:55 AM PDT 24
Finished Jul 01 10:57:05 AM PDT 24
Peak memory 217176 kb
Host smart-84959dda-23a5-472f-b14a-9bd99e7cf036
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155735844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.4155735844
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3950729592
Short name T210
Test name
Test status
Simulation time 75959378 ps
CPU time 1.31 seconds
Started Jul 01 10:56:44 AM PDT 24
Finished Jul 01 10:56:47 AM PDT 24
Peak memory 209140 kb
Host smart-9a9f91a6-82c6-4071-a510-0dcd0b90b848
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950729592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.3950729592
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1810818979
Short name T873
Test name
Test status
Simulation time 30614252 ps
CPU time 1.88 seconds
Started Jul 01 10:56:45 AM PDT 24
Finished Jul 01 10:56:49 AM PDT 24
Peak memory 209152 kb
Host smart-21ae3538-ea16-4309-ad57-9a5ca2cc96cd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810818979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.1810818979
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3959534946
Short name T987
Test name
Test status
Simulation time 14825400 ps
CPU time 1.13 seconds
Started Jul 01 10:56:45 AM PDT 24
Finished Jul 01 10:56:49 AM PDT 24
Peak memory 217732 kb
Host smart-349bb742-effc-4845-b024-5c05c39fd437
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959534946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.3959534946
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2641367552
Short name T985
Test name
Test status
Simulation time 19052926 ps
CPU time 1.03 seconds
Started Jul 01 10:56:44 AM PDT 24
Finished Jul 01 10:56:45 AM PDT 24
Peak memory 217300 kb
Host smart-4939dabd-57e0-43b8-94c9-0c31c94283d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641367552 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.2641367552
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1786551101
Short name T960
Test name
Test status
Simulation time 12645979 ps
CPU time 1.02 seconds
Started Jul 01 10:56:45 AM PDT 24
Finished Jul 01 10:56:48 AM PDT 24
Peak memory 209000 kb
Host smart-bd4cac8f-5c8d-4234-ae97-4056927d3366
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786551101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.1786551101
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3384001045
Short name T940
Test name
Test status
Simulation time 23233074 ps
CPU time 0.87 seconds
Started Jul 01 10:56:45 AM PDT 24
Finished Jul 01 10:56:49 AM PDT 24
Peak memory 208780 kb
Host smart-0922713f-ab1b-4429-9c15-39b03dfe61c5
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384001045 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.3384001045
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.903963620
Short name T903
Test name
Test status
Simulation time 871140899 ps
CPU time 7.39 seconds
Started Jul 01 10:56:33 AM PDT 24
Finished Jul 01 10:56:41 AM PDT 24
Peak memory 208732 kb
Host smart-56f03613-effc-4bd7-94f3-69ab00e4d377
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903963620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.903963620
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1053655825
Short name T157
Test name
Test status
Simulation time 2309316346 ps
CPU time 32.83 seconds
Started Jul 01 10:56:33 AM PDT 24
Finished Jul 01 10:57:07 AM PDT 24
Peak memory 217020 kb
Host smart-73e1ceaa-001f-42ec-bdf1-e814ebecf3af
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053655825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.1053655825
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.640258412
Short name T878
Test name
Test status
Simulation time 156279300 ps
CPU time 1.96 seconds
Started Jul 01 10:56:32 AM PDT 24
Finished Jul 01 10:56:34 AM PDT 24
Peak memory 210620 kb
Host smart-946617ba-8e96-4598-90cb-57884c7eae3a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640258412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.640258412
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3082966312
Short name T917
Test name
Test status
Simulation time 889499784 ps
CPU time 3.22 seconds
Started Jul 01 10:56:44 AM PDT 24
Finished Jul 01 10:56:48 AM PDT 24
Peak memory 220144 kb
Host smart-a5aa72ca-caf7-43b9-be03-61e390672b2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308296
6312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3082966312
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2983083076
Short name T915
Test name
Test status
Simulation time 249063026 ps
CPU time 1.35 seconds
Started Jul 01 10:56:31 AM PDT 24
Finished Jul 01 10:56:33 AM PDT 24
Peak memory 208976 kb
Host smart-51bd2604-d3ea-4201-9a04-4668a8e1e690
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983083076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.2983083076
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2075253586
Short name T926
Test name
Test status
Simulation time 27155790 ps
CPU time 1.39 seconds
Started Jul 01 10:56:33 AM PDT 24
Finished Jul 01 10:56:35 AM PDT 24
Peak memory 217240 kb
Host smart-12b7b050-27eb-42e1-991c-e1a25dd75a37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075253586 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.2075253586
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.55083975
Short name T953
Test name
Test status
Simulation time 45080280 ps
CPU time 0.96 seconds
Started Jul 01 10:56:43 AM PDT 24
Finished Jul 01 10:56:45 AM PDT 24
Peak memory 209180 kb
Host smart-1a4001aa-2576-4283-9363-8eef225e2235
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55083975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_s
ame_csr_outstanding.55083975
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.589845263
Short name T890
Test name
Test status
Simulation time 91751346 ps
CPU time 2.43 seconds
Started Jul 01 10:56:44 AM PDT 24
Finished Jul 01 10:56:47 AM PDT 24
Peak memory 217264 kb
Host smart-cca41a0a-9b36-4da8-8925-c9cf6534707a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589845263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.589845263
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3424324839
Short name T151
Test name
Test status
Simulation time 59852341 ps
CPU time 2.72 seconds
Started Jul 01 10:56:45 AM PDT 24
Finished Jul 01 10:56:49 AM PDT 24
Peak memory 217232 kb
Host smart-67030fb7-8f1d-41b0-93e0-fe8a6f96fca7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424324839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.3424324839
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2509738488
Short name T941
Test name
Test status
Simulation time 39070202 ps
CPU time 1.3 seconds
Started Jul 01 10:56:46 AM PDT 24
Finished Jul 01 10:56:50 AM PDT 24
Peak memory 209028 kb
Host smart-9b8050b5-5466-4bfa-8903-97e5da975421
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509738488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.2509738488
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2270309984
Short name T909
Test name
Test status
Simulation time 222209565 ps
CPU time 2.08 seconds
Started Jul 01 10:56:45 AM PDT 24
Finished Jul 01 10:56:49 AM PDT 24
Peak memory 208872 kb
Host smart-80e9aba6-9e4d-4eb4-8f0b-98fbc545953b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270309984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.2270309984
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3031923829
Short name T212
Test name
Test status
Simulation time 97625702 ps
CPU time 0.97 seconds
Started Jul 01 10:56:45 AM PDT 24
Finished Jul 01 10:56:49 AM PDT 24
Peak memory 209348 kb
Host smart-94b9ff94-8006-4c80-8480-44652cd0f844
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031923829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.3031923829
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3456733623
Short name T961
Test name
Test status
Simulation time 66394330 ps
CPU time 1.24 seconds
Started Jul 01 10:56:45 AM PDT 24
Finished Jul 01 10:56:48 AM PDT 24
Peak memory 217616 kb
Host smart-98e65e67-0fed-4ec5-a6a9-31ad5f5b14f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456733623 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.3456733623
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2396611688
Short name T942
Test name
Test status
Simulation time 254893059 ps
CPU time 1.04 seconds
Started Jul 01 10:56:46 AM PDT 24
Finished Jul 01 10:56:50 AM PDT 24
Peak memory 208992 kb
Host smart-eb6d6c40-cbf8-48e1-bc52-eb647364b268
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396611688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.2396611688
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3849853732
Short name T935
Test name
Test status
Simulation time 57505698 ps
CPU time 0.88 seconds
Started Jul 01 10:56:46 AM PDT 24
Finished Jul 01 10:56:51 AM PDT 24
Peak memory 208864 kb
Host smart-53512523-ffd3-4569-bc74-69e8046aef2f
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849853732 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.3849853732
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1905953973
Short name T880
Test name
Test status
Simulation time 1006301510 ps
CPU time 3 seconds
Started Jul 01 10:56:43 AM PDT 24
Finished Jul 01 10:56:47 AM PDT 24
Peak memory 208820 kb
Host smart-e9c2eca2-f991-4bb4-a744-e41dceea71dd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905953973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.1905953973
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3826735609
Short name T920
Test name
Test status
Simulation time 2485501875 ps
CPU time 10.71 seconds
Started Jul 01 10:56:44 AM PDT 24
Finished Jul 01 10:56:57 AM PDT 24
Peak memory 208960 kb
Host smart-eaeba024-72bb-40c1-af11-f6f63479118d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826735609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.3826735609
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.524315885
Short name T905
Test name
Test status
Simulation time 67124207 ps
CPU time 1.5 seconds
Started Jul 01 10:56:45 AM PDT 24
Finished Jul 01 10:56:50 AM PDT 24
Peak memory 210364 kb
Host smart-f4f3bf93-d02c-4c83-9b9c-84601c0a988e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524315885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.524315885
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2115356214
Short name T883
Test name
Test status
Simulation time 250636151 ps
CPU time 1.62 seconds
Started Jul 01 10:56:45 AM PDT 24
Finished Jul 01 10:56:50 AM PDT 24
Peak memory 217304 kb
Host smart-fa9be447-a397-4ed5-8314-b3f89f95ccf6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211535
6214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2115356214
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.439526931
Short name T974
Test name
Test status
Simulation time 85174355 ps
CPU time 1.63 seconds
Started Jul 01 10:56:46 AM PDT 24
Finished Jul 01 10:56:51 AM PDT 24
Peak memory 217000 kb
Host smart-ef9ed6ff-3aef-4ff2-8c0f-9610170da05d
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439526931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.439526931
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1262179126
Short name T934
Test name
Test status
Simulation time 26153107 ps
CPU time 1.13 seconds
Started Jul 01 10:56:44 AM PDT 24
Finished Jul 01 10:56:46 AM PDT 24
Peak memory 209132 kb
Host smart-00f4febc-7207-45fa-9cf5-5b030d84e21f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262179126 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.1262179126
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1150787088
Short name T133
Test name
Test status
Simulation time 27416362 ps
CPU time 1.18 seconds
Started Jul 01 10:56:46 AM PDT 24
Finished Jul 01 10:56:50 AM PDT 24
Peak memory 209076 kb
Host smart-37c0472e-7464-4717-8650-c69cae2c6819
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150787088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.1150787088
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.469842917
Short name T885
Test name
Test status
Simulation time 62779307 ps
CPU time 2.66 seconds
Started Jul 01 10:56:47 AM PDT 24
Finished Jul 01 10:56:54 AM PDT 24
Peak memory 217164 kb
Host smart-d09d1a8c-0c2b-497a-9096-18293c343d76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469842917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.469842917
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1384730427
Short name T209
Test name
Test status
Simulation time 34064764 ps
CPU time 1.12 seconds
Started Jul 01 10:56:48 AM PDT 24
Finished Jul 01 10:56:54 AM PDT 24
Peak memory 209136 kb
Host smart-ec511c53-5835-4065-8191-8417f395ac63
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384730427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.1384730427
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.4274260146
Short name T986
Test name
Test status
Simulation time 129721401 ps
CPU time 2.56 seconds
Started Jul 01 10:56:48 AM PDT 24
Finished Jul 01 10:56:55 AM PDT 24
Peak memory 209080 kb
Host smart-9f8aa79c-8715-4918-a8b0-033899206d87
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274260146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.4274260146
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1972387161
Short name T206
Test name
Test status
Simulation time 153935332 ps
CPU time 1.3 seconds
Started Jul 01 10:56:47 AM PDT 24
Finished Jul 01 10:56:53 AM PDT 24
Peak memory 217392 kb
Host smart-87dbf67a-6919-4e34-b08f-8e4a602f8b36
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972387161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.1972387161
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.385249415
Short name T901
Test name
Test status
Simulation time 24753551 ps
CPU time 1.36 seconds
Started Jul 01 10:56:46 AM PDT 24
Finished Jul 01 10:56:51 AM PDT 24
Peak memory 220004 kb
Host smart-f46e5199-552d-49f0-97ab-0529c9dd5153
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385249415 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.385249415
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3087250872
Short name T951
Test name
Test status
Simulation time 47195869 ps
CPU time 0.97 seconds
Started Jul 01 10:56:47 AM PDT 24
Finished Jul 01 10:56:52 AM PDT 24
Peak memory 209044 kb
Host smart-12a8267c-ebb0-4196-97cc-c2a7bc3a6e42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087250872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.3087250872
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.333153207
Short name T879
Test name
Test status
Simulation time 43377297 ps
CPU time 1.58 seconds
Started Jul 01 10:56:48 AM PDT 24
Finished Jul 01 10:56:54 AM PDT 24
Peak memory 208448 kb
Host smart-b2f0715e-edfc-45ac-82f1-a163d1361786
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333153207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.lc_ctrl_jtag_alert_test.333153207
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.4218566157
Short name T153
Test name
Test status
Simulation time 1305312583 ps
CPU time 6.52 seconds
Started Jul 01 10:56:46 AM PDT 24
Finished Jul 01 10:56:55 AM PDT 24
Peak memory 208540 kb
Host smart-4b3f88b7-8cc3-4df4-8cf5-c4748512191d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218566157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.4218566157
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2506583845
Short name T930
Test name
Test status
Simulation time 8513816882 ps
CPU time 27.48 seconds
Started Jul 01 10:56:42 AM PDT 24
Finished Jul 01 10:57:10 AM PDT 24
Peak memory 217272 kb
Host smart-8446f187-ea90-4c20-9208-e2c28667c11c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506583845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.2506583845
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2927672601
Short name T993
Test name
Test status
Simulation time 108492269 ps
CPU time 3.12 seconds
Started Jul 01 10:56:46 AM PDT 24
Finished Jul 01 10:56:52 AM PDT 24
Peak memory 210660 kb
Host smart-5d430d8c-4985-4265-8350-442855622c04
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927672601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.2927672601
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.136008511
Short name T976
Test name
Test status
Simulation time 34759855 ps
CPU time 1.51 seconds
Started Jul 01 10:56:47 AM PDT 24
Finished Jul 01 10:56:54 AM PDT 24
Peak memory 209004 kb
Host smart-1c788023-72ba-4c5a-9b69-d3a4712b4c12
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136008511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.136008511
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2131204441
Short name T216
Test name
Test status
Simulation time 26206742 ps
CPU time 1.09 seconds
Started Jul 01 10:56:46 AM PDT 24
Finished Jul 01 10:56:50 AM PDT 24
Peak memory 209084 kb
Host smart-b03701e1-01e4-4812-abc7-a5622c4bfa0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131204441 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.2131204441
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1504131201
Short name T128
Test name
Test status
Simulation time 94143504 ps
CPU time 1.27 seconds
Started Jul 01 10:56:47 AM PDT 24
Finished Jul 01 10:56:53 AM PDT 24
Peak memory 209136 kb
Host smart-cb19e4f8-73ae-4f37-83ab-57efd40d85a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504131201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.1504131201
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.695480104
Short name T119
Test name
Test status
Simulation time 307575266 ps
CPU time 3.33 seconds
Started Jul 01 10:56:47 AM PDT 24
Finished Jul 01 10:56:55 AM PDT 24
Peak memory 217304 kb
Host smart-ddc3a312-87f0-40d9-892b-85addda4ef3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695480104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.695480104
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3096625482
Short name T972
Test name
Test status
Simulation time 55528638 ps
CPU time 1.19 seconds
Started Jul 01 10:56:50 AM PDT 24
Finished Jul 01 10:56:57 AM PDT 24
Peak memory 217328 kb
Host smart-c7f1c318-bb81-49a6-b627-c9914ae95b49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096625482 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.3096625482
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1443868517
Short name T211
Test name
Test status
Simulation time 61340252 ps
CPU time 1.1 seconds
Started Jul 01 10:56:49 AM PDT 24
Finished Jul 01 10:56:56 AM PDT 24
Peak memory 208800 kb
Host smart-9638c11a-586f-47e7-b402-6147eb9782d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443868517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.1443868517
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2372358959
Short name T877
Test name
Test status
Simulation time 109038032 ps
CPU time 1.31 seconds
Started Jul 01 10:56:48 AM PDT 24
Finished Jul 01 10:56:55 AM PDT 24
Peak memory 208916 kb
Host smart-6606a7ac-b3f9-447f-8bad-b3b5d9088eea
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372358959 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.2372358959
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.4211871397
Short name T887
Test name
Test status
Simulation time 802672275 ps
CPU time 17.74 seconds
Started Jul 01 10:56:48 AM PDT 24
Finished Jul 01 10:57:10 AM PDT 24
Peak memory 216860 kb
Host smart-53a10507-6fc1-4879-96b5-57748615ac21
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211871397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.4211871397
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.747790485
Short name T992
Test name
Test status
Simulation time 3196944706 ps
CPU time 5.93 seconds
Started Jul 01 10:56:50 AM PDT 24
Finished Jul 01 10:57:01 AM PDT 24
Peak memory 217012 kb
Host smart-ff273ff4-0bd0-4ffb-916f-9143f894fd06
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747790485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.747790485
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3641781897
Short name T899
Test name
Test status
Simulation time 602745113 ps
CPU time 2.83 seconds
Started Jul 01 10:56:49 AM PDT 24
Finished Jul 01 10:56:58 AM PDT 24
Peak memory 217100 kb
Host smart-9ee1f5ba-1590-4361-87d5-ff2af0cd8ba4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641781897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.3641781897
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.611542241
Short name T963
Test name
Test status
Simulation time 281724409 ps
CPU time 2.33 seconds
Started Jul 01 10:56:49 AM PDT 24
Finished Jul 01 10:56:58 AM PDT 24
Peak memory 217384 kb
Host smart-da1e3dd3-f485-4456-b731-809d5e81bf6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611542
241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.611542241
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2631202324
Short name T989
Test name
Test status
Simulation time 182030017 ps
CPU time 2.41 seconds
Started Jul 01 10:56:49 AM PDT 24
Finished Jul 01 10:56:56 AM PDT 24
Peak memory 208900 kb
Host smart-d1fa46c7-4529-4721-b5a4-883e72866f41
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631202324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.2631202324
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2546359648
Short name T965
Test name
Test status
Simulation time 36186356 ps
CPU time 1.51 seconds
Started Jul 01 10:56:49 AM PDT 24
Finished Jul 01 10:56:56 AM PDT 24
Peak memory 209012 kb
Host smart-e510bad6-918c-4a34-81e0-740148276802
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546359648 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.2546359648
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2636965516
Short name T932
Test name
Test status
Simulation time 29254022 ps
CPU time 1.46 seconds
Started Jul 01 10:56:50 AM PDT 24
Finished Jul 01 10:56:57 AM PDT 24
Peak memory 209064 kb
Host smart-a9eb6f7b-f8b9-4782-9b72-544f5ae491c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636965516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.2636965516
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1000618000
Short name T945
Test name
Test status
Simulation time 182040560 ps
CPU time 3.26 seconds
Started Jul 01 10:56:49 AM PDT 24
Finished Jul 01 10:56:57 AM PDT 24
Peak memory 217764 kb
Host smart-6291de98-3ff4-4426-8f79-528cdeeb5e6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000618000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.1000618000
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3417430422
Short name T129
Test name
Test status
Simulation time 31169463 ps
CPU time 2.44 seconds
Started Jul 01 10:56:53 AM PDT 24
Finished Jul 01 10:57:01 AM PDT 24
Peak memory 219484 kb
Host smart-acc8ae87-f821-453b-ae52-53611d8ffb44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417430422 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.3417430422
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.970182501
Short name T938
Test name
Test status
Simulation time 38804563 ps
CPU time 0.92 seconds
Started Jul 01 10:56:52 AM PDT 24
Finished Jul 01 10:56:58 AM PDT 24
Peak memory 209032 kb
Host smart-fc474561-16d8-4c4e-8337-587f992fa1f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970182501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.970182501
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1115246488
Short name T902
Test name
Test status
Simulation time 73664161 ps
CPU time 0.87 seconds
Started Jul 01 10:56:52 AM PDT 24
Finished Jul 01 10:56:58 AM PDT 24
Peak memory 208876 kb
Host smart-3824efb0-f2fa-4062-8efa-ef98db61aac0
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115246488 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.1115246488
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.737420798
Short name T897
Test name
Test status
Simulation time 5006856124 ps
CPU time 6.91 seconds
Started Jul 01 10:56:50 AM PDT 24
Finished Jul 01 10:57:03 AM PDT 24
Peak memory 217064 kb
Host smart-79bf887f-ead9-4647-993d-87c799dec8cd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737420798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.737420798
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.344139132
Short name T991
Test name
Test status
Simulation time 964849044 ps
CPU time 9.47 seconds
Started Jul 01 10:56:50 AM PDT 24
Finished Jul 01 10:57:05 AM PDT 24
Peak memory 208664 kb
Host smart-f8cc8a97-7caf-427a-a1b4-a8afcb901bce
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344139132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.344139132
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.3985510481
Short name T875
Test name
Test status
Simulation time 249439367 ps
CPU time 2.54 seconds
Started Jul 01 10:56:50 AM PDT 24
Finished Jul 01 10:56:58 AM PDT 24
Peak memory 210676 kb
Host smart-5456b8fd-6aa4-4c59-b766-f7781d05b03d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985510481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.3985510481
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3131914756
Short name T944
Test name
Test status
Simulation time 88110292 ps
CPU time 2.34 seconds
Started Jul 01 10:56:49 AM PDT 24
Finished Jul 01 10:56:58 AM PDT 24
Peak memory 218372 kb
Host smart-9f7a2266-29d2-457b-a3d2-a9a324405e0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313191
4756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3131914756
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3069733295
Short name T966
Test name
Test status
Simulation time 262111461 ps
CPU time 1.49 seconds
Started Jul 01 10:56:48 AM PDT 24
Finished Jul 01 10:56:54 AM PDT 24
Peak memory 208924 kb
Host smart-a8b88145-37d4-4ac1-8843-a609c31bcf90
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069733295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.3069733295
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3307687627
Short name T937
Test name
Test status
Simulation time 17417298 ps
CPU time 1.25 seconds
Started Jul 01 10:56:50 AM PDT 24
Finished Jul 01 10:56:57 AM PDT 24
Peak memory 209016 kb
Host smart-2250830c-b5e3-4d72-8895-4f5dc33e126d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307687627 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.3307687627
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3517231831
Short name T219
Test name
Test status
Simulation time 66338541 ps
CPU time 0.96 seconds
Started Jul 01 10:56:47 AM PDT 24
Finished Jul 01 10:56:52 AM PDT 24
Peak memory 209036 kb
Host smart-8759e0a0-c870-4190-bdde-99d472a45cf3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517231831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.3517231831
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.3240001515
Short name T950
Test name
Test status
Simulation time 826913294 ps
CPU time 3.01 seconds
Started Jul 01 10:56:52 AM PDT 24
Finished Jul 01 10:57:00 AM PDT 24
Peak memory 218228 kb
Host smart-4748c2cb-e3c8-4696-b3dd-5c9f9076b0dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240001515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.3240001515
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2293111462
Short name T900
Test name
Test status
Simulation time 55525997 ps
CPU time 0.94 seconds
Started Jul 01 10:56:47 AM PDT 24
Finished Jul 01 10:56:52 AM PDT 24
Peak memory 217340 kb
Host smart-c37b815a-53b0-45f1-9205-4cf5fbf59e35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293111462 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.2293111462
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2435688287
Short name T207
Test name
Test status
Simulation time 34311950 ps
CPU time 0.98 seconds
Started Jul 01 10:56:45 AM PDT 24
Finished Jul 01 10:56:48 AM PDT 24
Peak memory 209052 kb
Host smart-b740be25-dc10-40f7-ac26-976ad981b102
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435688287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.2435688287
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1535358472
Short name T884
Test name
Test status
Simulation time 242892456 ps
CPU time 1.64 seconds
Started Jul 01 10:56:45 AM PDT 24
Finished Jul 01 10:56:50 AM PDT 24
Peak memory 208924 kb
Host smart-d1f7ddd2-b23a-4a99-94e0-e2be401f3de9
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535358472 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.1535358472
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.4030817864
Short name T971
Test name
Test status
Simulation time 1106856827 ps
CPU time 4.53 seconds
Started Jul 01 10:56:44 AM PDT 24
Finished Jul 01 10:56:50 AM PDT 24
Peak memory 208908 kb
Host smart-ce2d456f-1f13-4a87-8f4d-40744168bfae
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030817864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.4030817864
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.3207424690
Short name T975
Test name
Test status
Simulation time 4292186293 ps
CPU time 39.62 seconds
Started Jul 01 10:56:45 AM PDT 24
Finished Jul 01 10:57:27 AM PDT 24
Peak memory 208980 kb
Host smart-c483ee90-b6da-4d86-b6a9-d72fb2180841
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207424690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.3207424690
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.52865142
Short name T893
Test name
Test status
Simulation time 83825384 ps
CPU time 1.65 seconds
Started Jul 01 10:56:52 AM PDT 24
Finished Jul 01 10:56:59 AM PDT 24
Peak memory 210580 kb
Host smart-45a74e8c-f568-434a-85f1-7c79e928b9cc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52865142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.52865142
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1482317959
Short name T943
Test name
Test status
Simulation time 526630210 ps
CPU time 2.03 seconds
Started Jul 01 10:56:47 AM PDT 24
Finished Jul 01 10:56:54 AM PDT 24
Peak memory 217392 kb
Host smart-a0edb77c-6ba7-40fe-8e34-514ef4572e76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148231
7959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1482317959
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3146250222
Short name T916
Test name
Test status
Simulation time 156640163 ps
CPU time 1.9 seconds
Started Jul 01 10:56:46 AM PDT 24
Finished Jul 01 10:56:51 AM PDT 24
Peak memory 208936 kb
Host smart-2d6b40bf-c891-4cc7-8fcc-314c24311225
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146250222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.3146250222
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.4156700866
Short name T998
Test name
Test status
Simulation time 21557105 ps
CPU time 1.32 seconds
Started Jul 01 10:56:45 AM PDT 24
Finished Jul 01 10:56:50 AM PDT 24
Peak memory 209060 kb
Host smart-c7849dd3-7b43-4048-ba93-11ed5995ffb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156700866 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.4156700866
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3455798716
Short name T910
Test name
Test status
Simulation time 38084486 ps
CPU time 1.71 seconds
Started Jul 01 10:56:43 AM PDT 24
Finished Jul 01 10:56:45 AM PDT 24
Peak memory 209028 kb
Host smart-294c9a7c-bc6d-4563-867d-0c91f34a1567
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455798716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.3455798716
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.306859626
Short name T126
Test name
Test status
Simulation time 114150368 ps
CPU time 4.33 seconds
Started Jul 01 10:56:47 AM PDT 24
Finished Jul 01 10:56:56 AM PDT 24
Peak memory 217372 kb
Host smart-bff6f3ee-2a34-4fdf-bc89-a0ceaaecfd65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306859626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.306859626
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1942753626
Short name T173
Test name
Test status
Simulation time 100137319 ps
CPU time 1.22 seconds
Started Jul 01 10:56:45 AM PDT 24
Finished Jul 01 10:56:48 AM PDT 24
Peak memory 218576 kb
Host smart-7d6ce4e7-7a77-457c-89ca-a88aad356976
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942753626 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.1942753626
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2602631194
Short name T215
Test name
Test status
Simulation time 16743470 ps
CPU time 0.93 seconds
Started Jul 01 10:56:48 AM PDT 24
Finished Jul 01 10:56:54 AM PDT 24
Peak memory 209044 kb
Host smart-3bb17492-5069-435c-a533-4689a5e2f580
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602631194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.2602631194
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1386509250
Short name T947
Test name
Test status
Simulation time 110263123 ps
CPU time 2.99 seconds
Started Jul 01 10:56:47 AM PDT 24
Finished Jul 01 10:56:54 AM PDT 24
Peak memory 208436 kb
Host smart-1962c70d-b72c-463d-ae95-16b84be80f30
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386509250 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.1386509250
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.830695700
Short name T886
Test name
Test status
Simulation time 961231579 ps
CPU time 3.13 seconds
Started Jul 01 10:56:47 AM PDT 24
Finished Jul 01 10:56:54 AM PDT 24
Peak memory 208868 kb
Host smart-441e6bb8-02e2-49a2-888b-149e87ba296d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830695700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.830695700
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.245517588
Short name T952
Test name
Test status
Simulation time 554680599 ps
CPU time 12.96 seconds
Started Jul 01 10:56:47 AM PDT 24
Finished Jul 01 10:57:04 AM PDT 24
Peak memory 208912 kb
Host smart-10a4d573-8838-454c-a12a-186dacce541a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245517588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.245517588
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2704447297
Short name T955
Test name
Test status
Simulation time 723126475 ps
CPU time 2.38 seconds
Started Jul 01 10:56:46 AM PDT 24
Finished Jul 01 10:56:51 AM PDT 24
Peak memory 217212 kb
Host smart-dd884910-19bc-4d69-9eeb-7079924f733e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704447297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.2704447297
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3792166933
Short name T906
Test name
Test status
Simulation time 3203980109 ps
CPU time 2.83 seconds
Started Jul 01 10:56:49 AM PDT 24
Finished Jul 01 10:56:56 AM PDT 24
Peak memory 217448 kb
Host smart-13759f7e-8c44-42c7-bf86-406dd8819560
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379216
6933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3792166933
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2739857754
Short name T984
Test name
Test status
Simulation time 543990385 ps
CPU time 1.91 seconds
Started Jul 01 10:56:46 AM PDT 24
Finished Jul 01 10:56:52 AM PDT 24
Peak memory 209004 kb
Host smart-cd939fa5-b7ad-45bc-84e2-35518554ff69
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739857754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.2739857754
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2545967138
Short name T918
Test name
Test status
Simulation time 61849420 ps
CPU time 1.16 seconds
Started Jul 01 10:56:47 AM PDT 24
Finished Jul 01 10:56:53 AM PDT 24
Peak memory 217288 kb
Host smart-880982af-249a-4159-bbfc-b8e49d05dfbe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545967138 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.2545967138
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3077590268
Short name T980
Test name
Test status
Simulation time 108751154 ps
CPU time 0.97 seconds
Started Jul 01 10:56:49 AM PDT 24
Finished Jul 01 10:56:55 AM PDT 24
Peak memory 208652 kb
Host smart-36b88050-f77a-430e-b773-dc92d46aff3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077590268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.3077590268
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.4214061022
Short name T131
Test name
Test status
Simulation time 123007849 ps
CPU time 3.22 seconds
Started Jul 01 10:56:49 AM PDT 24
Finished Jul 01 10:56:57 AM PDT 24
Peak memory 217096 kb
Host smart-e526e47b-0a27-4979-8ee9-45b815bd9688
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214061022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.4214061022
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2871515664
Short name T136
Test name
Test status
Simulation time 231479069 ps
CPU time 1.95 seconds
Started Jul 01 10:56:48 AM PDT 24
Finished Jul 01 10:56:55 AM PDT 24
Peak memory 221820 kb
Host smart-5f231cb7-363f-49bd-bb3b-d6f9be5fbf4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871515664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.2871515664
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3545089991
Short name T912
Test name
Test status
Simulation time 221438255 ps
CPU time 1.46 seconds
Started Jul 01 10:56:50 AM PDT 24
Finished Jul 01 10:56:57 AM PDT 24
Peak memory 218224 kb
Host smart-8494cf7a-ba71-4f17-8825-ac3b0db6ebe9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545089991 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.3545089991
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3169089191
Short name T936
Test name
Test status
Simulation time 15406667 ps
CPU time 0.88 seconds
Started Jul 01 10:56:49 AM PDT 24
Finished Jul 01 10:56:56 AM PDT 24
Peak memory 209044 kb
Host smart-0cc47fd3-bb06-4952-98da-89d505865f0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169089191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.3169089191
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.3685034661
Short name T156
Test name
Test status
Simulation time 270773416 ps
CPU time 1.9 seconds
Started Jul 01 10:56:49 AM PDT 24
Finished Jul 01 10:56:57 AM PDT 24
Peak memory 208888 kb
Host smart-fc244934-8cd8-4552-be43-1dc7fae55404
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685034661 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.3685034661
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2295849533
Short name T946
Test name
Test status
Simulation time 3441068992 ps
CPU time 6.84 seconds
Started Jul 01 10:56:50 AM PDT 24
Finished Jul 01 10:57:02 AM PDT 24
Peak memory 209064 kb
Host smart-cb63717b-89a1-4cfc-b8a8-e144be9b81af
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295849533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.2295849533
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2142571218
Short name T948
Test name
Test status
Simulation time 1110933737 ps
CPU time 24.7 seconds
Started Jul 01 10:56:48 AM PDT 24
Finished Jul 01 10:57:18 AM PDT 24
Peak memory 216872 kb
Host smart-5a62272b-09ba-4a53-ab9a-7b4153c8108c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142571218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.2142571218
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.542951117
Short name T154
Test name
Test status
Simulation time 514502373 ps
CPU time 3.18 seconds
Started Jul 01 10:56:48 AM PDT 24
Finished Jul 01 10:56:57 AM PDT 24
Peak memory 217208 kb
Host smart-436bf810-123a-4a88-900f-efc295a1238b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542951117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.542951117
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1550125630
Short name T970
Test name
Test status
Simulation time 703512028 ps
CPU time 3.16 seconds
Started Jul 01 10:56:48 AM PDT 24
Finished Jul 01 10:56:57 AM PDT 24
Peak memory 217452 kb
Host smart-c8d3a3e3-e8fc-432b-813a-9963aff8a5fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155012
5630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1550125630
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3087602214
Short name T979
Test name
Test status
Simulation time 131532023 ps
CPU time 2.24 seconds
Started Jul 01 10:56:48 AM PDT 24
Finished Jul 01 10:56:55 AM PDT 24
Peak memory 208980 kb
Host smart-83f04082-75ba-4271-8373-24d8c5f96472
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087602214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.3087602214
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3795938119
Short name T982
Test name
Test status
Simulation time 68250279 ps
CPU time 1.27 seconds
Started Jul 01 10:56:49 AM PDT 24
Finished Jul 01 10:56:55 AM PDT 24
Peak memory 209104 kb
Host smart-591a186e-f58e-421e-8006-87ce726ef2bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795938119 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.3795938119
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.118615290
Short name T218
Test name
Test status
Simulation time 40199941 ps
CPU time 1.45 seconds
Started Jul 01 10:56:49 AM PDT 24
Finished Jul 01 10:56:57 AM PDT 24
Peak memory 209064 kb
Host smart-fe6af5f6-6456-4ea7-b51f-132fbad6eafd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118615290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
same_csr_outstanding.118615290
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2765297218
Short name T907
Test name
Test status
Simulation time 78140593 ps
CPU time 3.18 seconds
Started Jul 01 10:56:49 AM PDT 24
Finished Jul 01 10:56:59 AM PDT 24
Peak memory 217212 kb
Host smart-b9bda138-0bd1-49a1-b6b2-0d46b853cfbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765297218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.2765297218
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.3880023063
Short name T518
Test name
Test status
Simulation time 59237622 ps
CPU time 1.16 seconds
Started Jul 01 12:28:25 PM PDT 24
Finished Jul 01 12:28:27 PM PDT 24
Peak memory 209344 kb
Host smart-72c9e6da-ad75-4fd3-91ed-c8a1c096638b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880023063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.3880023063
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.1344270053
Short name T666
Test name
Test status
Simulation time 1294216323 ps
CPU time 9.88 seconds
Started Jul 01 12:27:53 PM PDT 24
Finished Jul 01 12:28:04 PM PDT 24
Peak memory 226428 kb
Host smart-59ce74d2-0374-4204-b5a3-e53a9cbfebd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344270053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.1344270053
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.3362081768
Short name T661
Test name
Test status
Simulation time 3400351738 ps
CPU time 5.56 seconds
Started Jul 01 12:28:01 PM PDT 24
Finished Jul 01 12:28:07 PM PDT 24
Peak memory 218116 kb
Host smart-d3d2f280-68ad-4d9e-b92f-9bfd29f3868a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362081768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.3362081768
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.534497555
Short name T371
Test name
Test status
Simulation time 3605852086 ps
CPU time 35.44 seconds
Started Jul 01 12:27:59 PM PDT 24
Finished Jul 01 12:28:35 PM PDT 24
Peak memory 219832 kb
Host smart-f9ea4129-8359-43a1-a8a0-863c3b6ecee6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534497555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_err
ors.534497555
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.618492407
Short name T286
Test name
Test status
Simulation time 707804879 ps
CPU time 11.69 seconds
Started Jul 01 12:27:59 PM PDT 24
Finished Jul 01 12:28:11 PM PDT 24
Peak memory 218732 kb
Host smart-12e9e53a-7891-4ef2-bd12-bb25ad3eb690
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618492407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_
prog_failure.618492407
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.56774269
Short name T709
Test name
Test status
Simulation time 2894318890 ps
CPU time 18.08 seconds
Started Jul 01 12:28:04 PM PDT 24
Finished Jul 01 12:28:23 PM PDT 24
Peak memory 218024 kb
Host smart-034f36b5-d905-468c-af5a-eeb59e1c4242
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56774269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_r
egwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jt
ag_regwen_during_op.56774269
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.4291995533
Short name T710
Test name
Test status
Simulation time 553187168 ps
CPU time 3.84 seconds
Started Jul 01 12:27:59 PM PDT 24
Finished Jul 01 12:28:04 PM PDT 24
Peak memory 217996 kb
Host smart-2c010903-a952-4c4a-af3c-e4a774f3157c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291995533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
4291995533
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.1926926712
Short name T828
Test name
Test status
Simulation time 2774100530 ps
CPU time 83.45 seconds
Started Jul 01 12:27:59 PM PDT 24
Finished Jul 01 12:29:23 PM PDT 24
Peak memory 284080 kb
Host smart-1c74b2b5-b494-499d-8166-3f79ab701dc5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926926712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.1926926712
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.2142028434
Short name T586
Test name
Test status
Simulation time 136132604 ps
CPU time 6.28 seconds
Started Jul 01 12:27:50 PM PDT 24
Finished Jul 01 12:27:57 PM PDT 24
Peak memory 222796 kb
Host smart-bb4c40b0-17a2-4598-953b-5a475529e6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142028434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.2142028434
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.3715016693
Short name T750
Test name
Test status
Simulation time 1357365504 ps
CPU time 5.8 seconds
Started Jul 01 12:27:57 PM PDT 24
Finished Jul 01 12:28:03 PM PDT 24
Peak memory 218068 kb
Host smart-304e45c5-8107-4799-a27a-687893939fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715016693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.3715016693
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.3818487296
Short name T90
Test name
Test status
Simulation time 425587305 ps
CPU time 23.5 seconds
Started Jul 01 12:28:25 PM PDT 24
Finished Jul 01 12:28:49 PM PDT 24
Peak memory 267816 kb
Host smart-1b36de73-1e4c-4316-9330-26ddaa87ff6e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818487296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.3818487296
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.2998118565
Short name T606
Test name
Test status
Simulation time 1712116977 ps
CPU time 18.91 seconds
Started Jul 01 12:28:05 PM PDT 24
Finished Jul 01 12:28:24 PM PDT 24
Peak memory 226448 kb
Host smart-d9edf0cf-2a84-405e-ac79-90592c51b5bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998118565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.2998118565
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.4163380361
Short name T548
Test name
Test status
Simulation time 581482341 ps
CPU time 9.19 seconds
Started Jul 01 12:28:02 PM PDT 24
Finished Jul 01 12:28:12 PM PDT 24
Peak memory 218672 kb
Host smart-9efca2f9-6951-4685-b6fa-1799a9a276d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163380361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.4163380361
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.2880976439
Short name T443
Test name
Test status
Simulation time 1048154594 ps
CPU time 12.32 seconds
Started Jul 01 12:28:04 PM PDT 24
Finished Jul 01 12:28:17 PM PDT 24
Peak memory 218492 kb
Host smart-a461b82c-d70f-4302-9f6c-04324ee9c1c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880976439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.2
880976439
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.615865669
Short name T56
Test name
Test status
Simulation time 577036293 ps
CPU time 7.29 seconds
Started Jul 01 12:27:49 PM PDT 24
Finished Jul 01 12:27:57 PM PDT 24
Peak memory 225064 kb
Host smart-dc5b8841-5152-4344-a098-cd6138e01eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615865669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.615865669
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.2276960277
Short name T321
Test name
Test status
Simulation time 259119391 ps
CPU time 2.29 seconds
Started Jul 01 12:27:46 PM PDT 24
Finished Jul 01 12:27:49 PM PDT 24
Peak memory 214712 kb
Host smart-b9ce6a44-37e8-4f86-8789-74d3c61e012b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276960277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.2276960277
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.2471356744
Short name T689
Test name
Test status
Simulation time 3317334213 ps
CPU time 32.92 seconds
Started Jul 01 12:27:45 PM PDT 24
Finished Jul 01 12:28:19 PM PDT 24
Peak memory 251380 kb
Host smart-2ff978ec-d298-430c-8f71-9059d289dbac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471356744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.2471356744
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.2743291894
Short name T762
Test name
Test status
Simulation time 12597915746 ps
CPU time 187.83 seconds
Started Jul 01 12:28:09 PM PDT 24
Finished Jul 01 12:31:17 PM PDT 24
Peak memory 251364 kb
Host smart-60f96add-2b2c-440f-852f-96a8e9edef9e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743291894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.2743291894
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.3997482802
Short name T163
Test name
Test status
Simulation time 19640581280 ps
CPU time 536.29 seconds
Started Jul 01 12:28:15 PM PDT 24
Finished Jul 01 12:37:12 PM PDT 24
Peak memory 284228 kb
Host smart-61a90761-4550-43a7-949c-0d4e9457cc31
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3997482802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all_with_rand_reset.3997482802
Directory /workspace/0.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.3058002127
Short name T476
Test name
Test status
Simulation time 61781675 ps
CPU time 0.95 seconds
Started Jul 01 12:27:45 PM PDT 24
Finished Jul 01 12:27:46 PM PDT 24
Peak memory 209284 kb
Host smart-355c5d25-201a-485d-acf8-522f7946bd75
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058002127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.3058002127
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.1407025130
Short name T282
Test name
Test status
Simulation time 63075033 ps
CPU time 0.87 seconds
Started Jul 01 12:28:46 PM PDT 24
Finished Jul 01 12:28:48 PM PDT 24
Peak memory 209288 kb
Host smart-7ea347ec-3b7a-436d-be1a-baeafad6bba9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407025130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.1407025130
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.818332482
Short name T291
Test name
Test status
Simulation time 23827508 ps
CPU time 0.82 seconds
Started Jul 01 12:28:24 PM PDT 24
Finished Jul 01 12:28:25 PM PDT 24
Peak memory 208960 kb
Host smart-5f07eae3-a99b-41fe-8e9e-9376d296df06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818332482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.818332482
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.1399635157
Short name T313
Test name
Test status
Simulation time 462392741 ps
CPU time 13.21 seconds
Started Jul 01 12:28:24 PM PDT 24
Finished Jul 01 12:28:38 PM PDT 24
Peak memory 218532 kb
Host smart-86fe25cc-cefd-4109-a1ca-339212df22db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399635157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.1399635157
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.367155510
Short name T459
Test name
Test status
Simulation time 1495094611 ps
CPU time 5.47 seconds
Started Jul 01 12:28:36 PM PDT 24
Finished Jul 01 12:28:42 PM PDT 24
Peak memory 217568 kb
Host smart-faf64d1a-e0ef-4055-885b-9bfa93ca43bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367155510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.367155510
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.2058544960
Short name T387
Test name
Test status
Simulation time 2756999489 ps
CPU time 41.1 seconds
Started Jul 01 12:28:34 PM PDT 24
Finished Jul 01 12:29:16 PM PDT 24
Peak memory 219284 kb
Host smart-ec5666b0-e5e0-40af-8021-c98a0ce3ff1e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058544960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.2058544960
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.654023009
Short name T572
Test name
Test status
Simulation time 4412590913 ps
CPU time 11.55 seconds
Started Jul 01 12:28:41 PM PDT 24
Finished Jul 01 12:28:53 PM PDT 24
Peak memory 218168 kb
Host smart-65612d90-5965-4eb5-b40a-f62593b2c557
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654023009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.654023009
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.1874977515
Short name T457
Test name
Test status
Simulation time 64833256 ps
CPU time 2.76 seconds
Started Jul 01 12:28:29 PM PDT 24
Finished Jul 01 12:28:32 PM PDT 24
Peak memory 218536 kb
Host smart-93a6da25-5a13-454e-87af-177292fe64e7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874977515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.1874977515
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.446700963
Short name T76
Test name
Test status
Simulation time 1785597432 ps
CPU time 38.3 seconds
Started Jul 01 12:28:43 PM PDT 24
Finished Jul 01 12:29:22 PM PDT 24
Peak memory 217944 kb
Host smart-e1b0fc5d-174e-4bb2-95da-7c0be32852e1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446700963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_j
tag_regwen_during_op.446700963
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.1519922619
Short name T634
Test name
Test status
Simulation time 1028813473 ps
CPU time 7.18 seconds
Started Jul 01 12:28:30 PM PDT 24
Finished Jul 01 12:28:38 PM PDT 24
Peak memory 217972 kb
Host smart-166f3607-21a5-4885-9358-8c83b5de36b3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519922619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
1519922619
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.3944367242
Short name T683
Test name
Test status
Simulation time 7958044123 ps
CPU time 50.14 seconds
Started Jul 01 12:28:33 PM PDT 24
Finished Jul 01 12:29:23 PM PDT 24
Peak memory 267668 kb
Host smart-6d1696ff-67db-4ef5-8b2d-eacd2fa4979f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944367242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.3944367242
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.3348858338
Short name T740
Test name
Test status
Simulation time 2938345401 ps
CPU time 12.34 seconds
Started Jul 01 12:28:28 PM PDT 24
Finished Jul 01 12:28:40 PM PDT 24
Peak memory 251336 kb
Host smart-e2d98c40-cf21-49fb-a8f0-c5cf50e6a7ae
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348858338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.3348858338
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.489419662
Short name T641
Test name
Test status
Simulation time 67886801 ps
CPU time 3.56 seconds
Started Jul 01 12:28:24 PM PDT 24
Finished Jul 01 12:28:28 PM PDT 24
Peak memory 218596 kb
Host smart-34549114-4cb5-4dc8-a390-e6b499782ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489419662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.489419662
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.2181696445
Short name T333
Test name
Test status
Simulation time 1414192902 ps
CPU time 14.52 seconds
Started Jul 01 12:28:24 PM PDT 24
Finished Jul 01 12:28:39 PM PDT 24
Peak memory 218108 kb
Host smart-d320617a-74a1-4f01-b4a6-9894e70d5c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181696445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.2181696445
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.4290229175
Short name T108
Test name
Test status
Simulation time 276120332 ps
CPU time 24.19 seconds
Started Jul 01 12:28:44 PM PDT 24
Finished Jul 01 12:29:09 PM PDT 24
Peak memory 282240 kb
Host smart-b7e44a1c-7f67-425a-a7bb-dd0615944cfd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290229175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.4290229175
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.3349742981
Short name T424
Test name
Test status
Simulation time 1968813789 ps
CPU time 10.33 seconds
Started Jul 01 12:28:41 PM PDT 24
Finished Jul 01 12:28:51 PM PDT 24
Peak memory 226456 kb
Host smart-1f3ef4dd-4bc9-43e2-bac2-828fb8603db1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349742981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.3349742981
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.281110935
Short name T824
Test name
Test status
Simulation time 749048825 ps
CPU time 11.81 seconds
Started Jul 01 12:28:43 PM PDT 24
Finished Jul 01 12:28:56 PM PDT 24
Peak memory 218624 kb
Host smart-5d12f4ec-67c1-4d6c-a522-ce3cf646df4e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281110935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_dig
est.281110935
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.417608883
Short name T847
Test name
Test status
Simulation time 2052889521 ps
CPU time 16.1 seconds
Started Jul 01 12:28:42 PM PDT 24
Finished Jul 01 12:28:59 PM PDT 24
Peak memory 218564 kb
Host smart-bc8d7fc8-dc7c-46f2-af47-389d08e67bfb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417608883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.417608883
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.1665824286
Short name T551
Test name
Test status
Simulation time 257974296 ps
CPU time 10.74 seconds
Started Jul 01 12:28:26 PM PDT 24
Finished Jul 01 12:28:38 PM PDT 24
Peak memory 226416 kb
Host smart-a12826c3-f0f0-419e-a231-3869369460af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665824286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.1665824286
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.3972478410
Short name T624
Test name
Test status
Simulation time 28520791 ps
CPU time 1.76 seconds
Started Jul 01 12:28:20 PM PDT 24
Finished Jul 01 12:28:22 PM PDT 24
Peak memory 214328 kb
Host smart-6cbe5e56-f576-4575-b456-da5f4229e19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972478410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.3972478410
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.1693125790
Short name T714
Test name
Test status
Simulation time 1059492595 ps
CPU time 31.56 seconds
Started Jul 01 12:28:20 PM PDT 24
Finished Jul 01 12:28:52 PM PDT 24
Peak memory 251504 kb
Host smart-6d743805-e6bd-482d-8e5a-7bcfee2976f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693125790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.1693125790
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.3301004254
Short name T379
Test name
Test status
Simulation time 141130337 ps
CPU time 7.16 seconds
Started Jul 01 12:28:26 PM PDT 24
Finished Jul 01 12:28:34 PM PDT 24
Peak memory 251288 kb
Host smart-916685a4-16af-4ac4-909a-dd6b9aba31b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301004254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.3301004254
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.1943399202
Short name T305
Test name
Test status
Simulation time 2267925405 ps
CPU time 43.36 seconds
Started Jul 01 12:28:41 PM PDT 24
Finished Jul 01 12:29:25 PM PDT 24
Peak memory 251376 kb
Host smart-54914179-6673-4613-a28c-b5abfae1a4cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943399202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.1943399202
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1093825403
Short name T284
Test name
Test status
Simulation time 11044274 ps
CPU time 1.02 seconds
Started Jul 01 12:28:19 PM PDT 24
Finished Jul 01 12:28:20 PM PDT 24
Peak memory 212216 kb
Host smart-378dae77-f9a9-4936-831c-8fc6b5aa7355
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093825403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.1093825403
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.666623108
Short name T673
Test name
Test status
Simulation time 43502328 ps
CPU time 1.14 seconds
Started Jul 01 12:31:09 PM PDT 24
Finished Jul 01 12:31:11 PM PDT 24
Peak memory 209312 kb
Host smart-b1fecd21-a042-45ae-b66b-7d81dc9bd516
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666623108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.666623108
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.2802345545
Short name T307
Test name
Test status
Simulation time 1038931322 ps
CPU time 11.72 seconds
Started Jul 01 12:31:03 PM PDT 24
Finished Jul 01 12:31:16 PM PDT 24
Peak memory 226484 kb
Host smart-40c8614e-8d82-4a4d-9c05-e615618a66ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802345545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.2802345545
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.4283728385
Short name T412
Test name
Test status
Simulation time 148202516 ps
CPU time 2.47 seconds
Started Jul 01 12:31:07 PM PDT 24
Finished Jul 01 12:31:10 PM PDT 24
Peak memory 217452 kb
Host smart-142c6191-0ca2-4368-9665-6f0cabf4006c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283728385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.4283728385
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.1429547617
Short name T101
Test name
Test status
Simulation time 1001016703 ps
CPU time 18.96 seconds
Started Jul 01 12:31:11 PM PDT 24
Finished Jul 01 12:31:31 PM PDT 24
Peak memory 226060 kb
Host smart-caea2c11-3ded-4996-a9e8-20cf49d07e7d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429547617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.1429547617
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.2182874370
Short name T632
Test name
Test status
Simulation time 2032254638 ps
CPU time 9.45 seconds
Started Jul 01 12:31:06 PM PDT 24
Finished Jul 01 12:31:17 PM PDT 24
Peak memory 218580 kb
Host smart-db2d6401-cfd3-4c5a-ad3e-a360694a6044
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182874370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.2182874370
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.3363105146
Short name T520
Test name
Test status
Simulation time 834868105 ps
CPU time 8.03 seconds
Started Jul 01 12:31:03 PM PDT 24
Finished Jul 01 12:31:12 PM PDT 24
Peak memory 217996 kb
Host smart-ff619477-a739-47bb-8098-298dea1560de
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363105146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.3363105146
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.3360955325
Short name T30
Test name
Test status
Simulation time 6120097364 ps
CPU time 66.15 seconds
Started Jul 01 12:31:11 PM PDT 24
Finished Jul 01 12:32:18 PM PDT 24
Peak memory 267372 kb
Host smart-59125c9f-9320-4d54-a5f3-64bb3c6a1705
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360955325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.3360955325
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.2316479958
Short name T672
Test name
Test status
Simulation time 1469084498 ps
CPU time 13.05 seconds
Started Jul 01 12:31:08 PM PDT 24
Finished Jul 01 12:31:22 PM PDT 24
Peak memory 251264 kb
Host smart-83ca4288-e4aa-483a-8b30-c93f7bc610f9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316479958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.2316479958
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.2163084249
Short name T552
Test name
Test status
Simulation time 166591013 ps
CPU time 1.7 seconds
Started Jul 01 12:31:00 PM PDT 24
Finished Jul 01 12:31:03 PM PDT 24
Peak memory 222224 kb
Host smart-bc6f9638-6654-49b3-a5ea-833df718664a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163084249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.2163084249
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.1275994500
Short name T420
Test name
Test status
Simulation time 1229808145 ps
CPU time 10.44 seconds
Started Jul 01 12:31:07 PM PDT 24
Finished Jul 01 12:31:18 PM PDT 24
Peak memory 226440 kb
Host smart-1c627030-e731-4081-9cea-d124af597817
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275994500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.1275994500
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.1188985871
Short name T255
Test name
Test status
Simulation time 2062192852 ps
CPU time 13.46 seconds
Started Jul 01 12:31:08 PM PDT 24
Finished Jul 01 12:31:22 PM PDT 24
Peak memory 218600 kb
Host smart-0a35dc58-1346-45c2-93da-6fd7f2e99f56
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188985871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.1188985871
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.408955633
Short name T263
Test name
Test status
Simulation time 313202075 ps
CPU time 12.31 seconds
Started Jul 01 12:31:07 PM PDT 24
Finished Jul 01 12:31:20 PM PDT 24
Peak memory 218604 kb
Host smart-5c9ce461-c7c8-48a5-8136-6943214892d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408955633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.408955633
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.384224033
Short name T591
Test name
Test status
Simulation time 196273645 ps
CPU time 7.74 seconds
Started Jul 01 12:31:00 PM PDT 24
Finished Jul 01 12:31:09 PM PDT 24
Peak memory 224992 kb
Host smart-9d40ae19-5d7e-49b3-8807-165be8e31524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384224033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.384224033
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.3779665084
Short name T87
Test name
Test status
Simulation time 37646062 ps
CPU time 2.25 seconds
Started Jul 01 12:31:03 PM PDT 24
Finished Jul 01 12:31:07 PM PDT 24
Peak memory 214848 kb
Host smart-2954cea8-ed9c-4eaf-b8d7-355aac450dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779665084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.3779665084
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.1558915658
Short name T865
Test name
Test status
Simulation time 1145703189 ps
CPU time 27.95 seconds
Started Jul 01 12:31:03 PM PDT 24
Finished Jul 01 12:31:32 PM PDT 24
Peak memory 251340 kb
Host smart-461134a5-4f37-40c7-8c55-6991d0e46e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558915658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.1558915658
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.3509852105
Short name T344
Test name
Test status
Simulation time 189708947 ps
CPU time 8.33 seconds
Started Jul 01 12:31:01 PM PDT 24
Finished Jul 01 12:31:11 PM PDT 24
Peak memory 250932 kb
Host smart-36a74618-781e-4498-9ce6-7411978ee1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509852105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.3509852105
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.3830901321
Short name T760
Test name
Test status
Simulation time 2028699449 ps
CPU time 39.16 seconds
Started Jul 01 12:31:06 PM PDT 24
Finished Jul 01 12:31:46 PM PDT 24
Peak memory 251320 kb
Host smart-88e18dad-a4d8-4616-ac5b-07b4d7fcebc1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830901321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.3830901321
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.143344452
Short name T265
Test name
Test status
Simulation time 193078718 ps
CPU time 0.91 seconds
Started Jul 01 12:31:03 PM PDT 24
Finished Jul 01 12:31:04 PM PDT 24
Peak memory 212264 kb
Host smart-8c838390-8766-46a4-a17e-3dfcf2fc4dfd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143344452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ct
rl_volatile_unlock_smoke.143344452
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.2035850946
Short name T535
Test name
Test status
Simulation time 42068538 ps
CPU time 0.82 seconds
Started Jul 01 12:31:17 PM PDT 24
Finished Jul 01 12:31:18 PM PDT 24
Peak memory 209188 kb
Host smart-744238fe-474a-43f5-8d57-bb90ac47489e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035850946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.2035850946
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.2622694860
Short name T262
Test name
Test status
Simulation time 433279374 ps
CPU time 12.48 seconds
Started Jul 01 12:31:07 PM PDT 24
Finished Jul 01 12:31:20 PM PDT 24
Peak memory 226448 kb
Host smart-e3f96cf9-440a-4fb6-8e6f-d6b69f713f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622694860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.2622694860
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.3666580644
Short name T609
Test name
Test status
Simulation time 424715853 ps
CPU time 3.6 seconds
Started Jul 01 12:31:14 PM PDT 24
Finished Jul 01 12:31:18 PM PDT 24
Peak memory 217504 kb
Host smart-6fc37d4c-1bfe-428c-852f-ad2476bf7455
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666580644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.3666580644
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.1720291375
Short name T289
Test name
Test status
Simulation time 5183505807 ps
CPU time 39.99 seconds
Started Jul 01 12:31:13 PM PDT 24
Finished Jul 01 12:31:54 PM PDT 24
Peak memory 219656 kb
Host smart-3a4cb589-d8f3-4ee4-80d5-53ab22d0f306
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720291375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.1720291375
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.2439719123
Short name T759
Test name
Test status
Simulation time 276672577 ps
CPU time 5.27 seconds
Started Jul 01 12:31:12 PM PDT 24
Finished Jul 01 12:31:18 PM PDT 24
Peak memory 218464 kb
Host smart-b819b62b-12d4-417d-9aae-860b3a4da18c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439719123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.2439719123
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.2604870938
Short name T686
Test name
Test status
Simulation time 1431981993 ps
CPU time 5.59 seconds
Started Jul 01 12:31:15 PM PDT 24
Finished Jul 01 12:31:21 PM PDT 24
Peak memory 218040 kb
Host smart-6efeea7c-dfd6-455d-9477-a99fffae2e0b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604870938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.2604870938
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.1224912008
Short name T853
Test name
Test status
Simulation time 2220203984 ps
CPU time 54.41 seconds
Started Jul 01 12:31:12 PM PDT 24
Finished Jul 01 12:32:07 PM PDT 24
Peak memory 251208 kb
Host smart-920ffbb9-1609-4333-9191-9cf9b476571f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224912008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.1224912008
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.2482001767
Short name T165
Test name
Test status
Simulation time 577671568 ps
CPU time 21.31 seconds
Started Jul 01 12:31:12 PM PDT 24
Finished Jul 01 12:31:34 PM PDT 24
Peak memory 246500 kb
Host smart-ae07e7a0-5104-4792-9a58-d5a436f2ff77
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482001767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.2482001767
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.3189481435
Short name T481
Test name
Test status
Simulation time 439791072 ps
CPU time 3.16 seconds
Started Jul 01 12:31:08 PM PDT 24
Finished Jul 01 12:31:12 PM PDT 24
Peak memory 218480 kb
Host smart-a57c65d9-7d98-4568-9f22-4656dbef4d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189481435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.3189481435
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.392000788
Short name T478
Test name
Test status
Simulation time 1084734595 ps
CPU time 13.47 seconds
Started Jul 01 12:31:14 PM PDT 24
Finished Jul 01 12:31:28 PM PDT 24
Peak memory 226440 kb
Host smart-625ed8ee-bde1-4e6b-8ce3-6ed5bb93c2ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392000788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.392000788
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.1995775681
Short name T418
Test name
Test status
Simulation time 1315728493 ps
CPU time 7.33 seconds
Started Jul 01 12:31:18 PM PDT 24
Finished Jul 01 12:31:26 PM PDT 24
Peak memory 218644 kb
Host smart-9c442424-f061-446b-baa6-81c2014921ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995775681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.1995775681
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.1899750692
Short name T236
Test name
Test status
Simulation time 281995217 ps
CPU time 7.01 seconds
Started Jul 01 12:31:16 PM PDT 24
Finished Jul 01 12:31:24 PM PDT 24
Peak memory 226320 kb
Host smart-d18c5633-6853-47c2-a0ae-84806972b408
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899750692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
1899750692
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.910653870
Short name T411
Test name
Test status
Simulation time 314021964 ps
CPU time 11.99 seconds
Started Jul 01 12:31:12 PM PDT 24
Finished Jul 01 12:31:25 PM PDT 24
Peak memory 226348 kb
Host smart-af195f22-ccae-4200-a8ec-d6902d146781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910653870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.910653870
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.53117970
Short name T571
Test name
Test status
Simulation time 62759977 ps
CPU time 2.01 seconds
Started Jul 01 12:31:09 PM PDT 24
Finished Jul 01 12:31:13 PM PDT 24
Peak memory 214404 kb
Host smart-43d2aaa1-85da-4630-9eee-2f0912c1764b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53117970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.53117970
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.1637951209
Short name T605
Test name
Test status
Simulation time 260655091 ps
CPU time 22.96 seconds
Started Jul 01 12:31:10 PM PDT 24
Finished Jul 01 12:31:35 PM PDT 24
Peak memory 251264 kb
Host smart-a4c56f4a-1ef3-45a6-b003-630f25007c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637951209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.1637951209
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.3448171380
Short name T437
Test name
Test status
Simulation time 722043748 ps
CPU time 7.61 seconds
Started Jul 01 12:31:08 PM PDT 24
Finished Jul 01 12:31:17 PM PDT 24
Peak memory 245624 kb
Host smart-3778a4bc-f6e2-47f6-8095-3b84c96bbd7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448171380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.3448171380
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.624493270
Short name T258
Test name
Test status
Simulation time 21584644 ps
CPU time 0.78 seconds
Started Jul 01 12:31:09 PM PDT 24
Finished Jul 01 12:31:11 PM PDT 24
Peak memory 209352 kb
Host smart-b3c57c3d-33f4-48f6-926d-960309b22ca6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624493270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ct
rl_volatile_unlock_smoke.624493270
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.2989066900
Short name T818
Test name
Test status
Simulation time 33322007 ps
CPU time 0.89 seconds
Started Jul 01 12:31:30 PM PDT 24
Finished Jul 01 12:31:31 PM PDT 24
Peak memory 209412 kb
Host smart-a5ef402f-706a-44ef-ba5d-f2a2d922b999
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989066900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.2989066900
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.1603867552
Short name T753
Test name
Test status
Simulation time 2032454587 ps
CPU time 14.27 seconds
Started Jul 01 12:31:23 PM PDT 24
Finished Jul 01 12:31:37 PM PDT 24
Peak memory 226436 kb
Host smart-06c41382-b16e-4368-950d-dfc6ad8e8824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603867552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.1603867552
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.219788570
Short name T318
Test name
Test status
Simulation time 33761755 ps
CPU time 1.62 seconds
Started Jul 01 12:31:28 PM PDT 24
Finished Jul 01 12:31:31 PM PDT 24
Peak memory 217464 kb
Host smart-d8e118a7-c41d-4e80-9a96-8d940dfd875c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219788570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.219788570
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.4273002759
Short name T113
Test name
Test status
Simulation time 936847746 ps
CPU time 20.28 seconds
Started Jul 01 12:31:33 PM PDT 24
Finished Jul 01 12:31:54 PM PDT 24
Peak memory 218492 kb
Host smart-1b4c249c-6246-4700-85ec-9c542fa878ee
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273002759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.4273002759
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.3356884852
Short name T547
Test name
Test status
Simulation time 661744013 ps
CPU time 3.72 seconds
Started Jul 01 12:31:26 PM PDT 24
Finished Jul 01 12:31:31 PM PDT 24
Peak memory 218540 kb
Host smart-8b16c262-0983-4947-bac6-d8a81b73750d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356884852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.3356884852
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.2149008622
Short name T726
Test name
Test status
Simulation time 549261543 ps
CPU time 4.98 seconds
Started Jul 01 12:31:21 PM PDT 24
Finished Jul 01 12:31:27 PM PDT 24
Peak memory 217908 kb
Host smart-2fa42163-3668-48f2-bad7-4c201ba64934
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149008622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.2149008622
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.1118205147
Short name T643
Test name
Test status
Simulation time 3488184177 ps
CPU time 79.38 seconds
Started Jul 01 12:31:25 PM PDT 24
Finished Jul 01 12:32:44 PM PDT 24
Peak memory 267704 kb
Host smart-72086e80-b650-48cb-b213-c4b4ac391a71
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118205147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.1118205147
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.2127241086
Short name T434
Test name
Test status
Simulation time 763555046 ps
CPU time 23.62 seconds
Started Jul 01 12:31:29 PM PDT 24
Finished Jul 01 12:31:53 PM PDT 24
Peak memory 243028 kb
Host smart-450f9cc9-02c5-47c1-a2a0-0e10ec4474a0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127241086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.2127241086
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.2808569774
Short name T833
Test name
Test status
Simulation time 116764096 ps
CPU time 2.03 seconds
Started Jul 01 12:31:21 PM PDT 24
Finished Jul 01 12:31:24 PM PDT 24
Peak memory 222404 kb
Host smart-bc4d38d6-c416-4437-985f-886ddc3de040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808569774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.2808569774
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.2690255683
Short name T415
Test name
Test status
Simulation time 592955503 ps
CPU time 10.5 seconds
Started Jul 01 12:31:33 PM PDT 24
Finished Jul 01 12:31:44 PM PDT 24
Peak memory 226424 kb
Host smart-fe852ccc-ed7c-4daf-b15f-d26b99341d67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690255683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.2690255683
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.3923366099
Short name T480
Test name
Test status
Simulation time 632906333 ps
CPU time 13.38 seconds
Started Jul 01 12:31:27 PM PDT 24
Finished Jul 01 12:31:41 PM PDT 24
Peak memory 226380 kb
Host smart-bac8cd97-cf2b-4aa6-960e-51c3b7c1382f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923366099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.3923366099
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.2937549143
Short name T671
Test name
Test status
Simulation time 762061232 ps
CPU time 5.62 seconds
Started Jul 01 12:31:30 PM PDT 24
Finished Jul 01 12:31:36 PM PDT 24
Peak memory 218708 kb
Host smart-01a7fb02-45e7-479b-b4a6-c300f21c7e43
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937549143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
2937549143
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.351308812
Short name T850
Test name
Test status
Simulation time 2172667222 ps
CPU time 10.56 seconds
Started Jul 01 12:31:21 PM PDT 24
Finished Jul 01 12:31:32 PM PDT 24
Peak memory 226500 kb
Host smart-00f18d5f-7f21-4bb7-ba29-043d1be972d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351308812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.351308812
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.2765205667
Short name T257
Test name
Test status
Simulation time 227875667 ps
CPU time 2.4 seconds
Started Jul 01 12:31:17 PM PDT 24
Finished Jul 01 12:31:21 PM PDT 24
Peak memory 218040 kb
Host smart-2dd349dc-7827-4519-833c-5507ffb52b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765205667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.2765205667
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.2037214238
Short name T599
Test name
Test status
Simulation time 552209656 ps
CPU time 29.65 seconds
Started Jul 01 12:31:17 PM PDT 24
Finished Jul 01 12:31:47 PM PDT 24
Peak memory 251328 kb
Host smart-d5b8ef4c-2a39-4484-bfa6-073ab00afce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037214238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.2037214238
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.3500509991
Short name T811
Test name
Test status
Simulation time 1010509889 ps
CPU time 9.71 seconds
Started Jul 01 12:31:18 PM PDT 24
Finished Jul 01 12:31:29 PM PDT 24
Peak memory 251276 kb
Host smart-f3fabbd0-1f9d-43ac-90c3-f99db06b3142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500509991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.3500509991
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.2048257217
Short name T767
Test name
Test status
Simulation time 7401419357 ps
CPU time 42.15 seconds
Started Jul 01 12:31:27 PM PDT 24
Finished Jul 01 12:32:10 PM PDT 24
Peak memory 251348 kb
Host smart-a7d7df16-030b-4091-898a-3e095dd65622
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048257217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.2048257217
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.3520096226
Short name T47
Test name
Test status
Simulation time 40511608 ps
CPU time 1.04 seconds
Started Jul 01 12:31:20 PM PDT 24
Finished Jul 01 12:31:22 PM PDT 24
Peak memory 212320 kb
Host smart-3c3d353f-42c6-48e6-be85-4851091a7d7d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520096226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.3520096226
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.1789418340
Short name T627
Test name
Test status
Simulation time 65609204 ps
CPU time 0.97 seconds
Started Jul 01 12:31:38 PM PDT 24
Finished Jul 01 12:31:39 PM PDT 24
Peak memory 209204 kb
Host smart-571546e0-4f53-4bac-9139-e9198dc99790
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789418340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.1789418340
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.2194322787
Short name T351
Test name
Test status
Simulation time 537235072 ps
CPU time 23 seconds
Started Jul 01 12:31:33 PM PDT 24
Finished Jul 01 12:31:57 PM PDT 24
Peak memory 218548 kb
Host smart-05dd2e10-62a8-47f4-a5c2-c7f57c397a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194322787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.2194322787
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.3015187030
Short name T438
Test name
Test status
Simulation time 1378619517 ps
CPU time 8.97 seconds
Started Jul 01 12:31:33 PM PDT 24
Finished Jul 01 12:31:43 PM PDT 24
Peak memory 217516 kb
Host smart-25045b5a-8014-4abf-ad49-b88ab50ac516
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015187030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.3015187030
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.2984009437
Short name T421
Test name
Test status
Simulation time 2740032090 ps
CPU time 27.83 seconds
Started Jul 01 12:31:34 PM PDT 24
Finished Jul 01 12:32:02 PM PDT 24
Peak memory 219248 kb
Host smart-8be86d73-50da-405a-bb0a-0943aba099a3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984009437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.2984009437
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.1074761328
Short name T280
Test name
Test status
Simulation time 203632785 ps
CPU time 3.98 seconds
Started Jul 01 12:31:33 PM PDT 24
Finished Jul 01 12:31:38 PM PDT 24
Peak memory 223264 kb
Host smart-6eb5680b-6d66-4ce1-8d66-4740999d93ea
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074761328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.1074761328
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.3480747479
Short name T464
Test name
Test status
Simulation time 86789726 ps
CPU time 3.22 seconds
Started Jul 01 12:31:34 PM PDT 24
Finished Jul 01 12:31:38 PM PDT 24
Peak memory 217944 kb
Host smart-13a023da-cb0d-49b8-be84-291862afc5f0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480747479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.3480747479
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.2547003876
Short name T107
Test name
Test status
Simulation time 13028289951 ps
CPU time 55.25 seconds
Started Jul 01 12:31:33 PM PDT 24
Finished Jul 01 12:32:29 PM PDT 24
Peak memory 267776 kb
Host smart-5960bce8-90e5-4fe8-b51d-acbc7dee379d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547003876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.2547003876
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.3550498449
Short name T402
Test name
Test status
Simulation time 444397606 ps
CPU time 12.23 seconds
Started Jul 01 12:31:33 PM PDT 24
Finished Jul 01 12:31:46 PM PDT 24
Peak memory 247632 kb
Host smart-4e4db4c4-691c-4db3-921d-e59e73509dbe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550498449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.3550498449
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.747478299
Short name T798
Test name
Test status
Simulation time 112077403 ps
CPU time 2.16 seconds
Started Jul 01 12:31:28 PM PDT 24
Finished Jul 01 12:31:31 PM PDT 24
Peak memory 218632 kb
Host smart-7046d482-36a2-476d-b925-9b37d651246c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747478299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.747478299
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.1015816987
Short name T769
Test name
Test status
Simulation time 3723397807 ps
CPU time 10.46 seconds
Started Jul 01 12:31:34 PM PDT 24
Finished Jul 01 12:31:46 PM PDT 24
Peak memory 226492 kb
Host smart-6cf588d9-b202-4256-ab79-394a8615f922
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015816987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.1015816987
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.2148135881
Short name T395
Test name
Test status
Simulation time 1580197683 ps
CPU time 12.87 seconds
Started Jul 01 12:31:37 PM PDT 24
Finished Jul 01 12:31:50 PM PDT 24
Peak memory 218588 kb
Host smart-3d65e0c6-d92b-4617-a3a0-6f59b87d2d8f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148135881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.2148135881
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.3489198922
Short name T650
Test name
Test status
Simulation time 1214263522 ps
CPU time 12.83 seconds
Started Jul 01 12:31:39 PM PDT 24
Finished Jul 01 12:31:52 PM PDT 24
Peak memory 218584 kb
Host smart-fac4ac9c-d984-4733-af49-2b66146008ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489198922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
3489198922
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.3040917424
Short name T602
Test name
Test status
Simulation time 889174277 ps
CPU time 12.99 seconds
Started Jul 01 12:31:27 PM PDT 24
Finished Jul 01 12:31:41 PM PDT 24
Peak memory 218676 kb
Host smart-0960d971-1f68-48d4-a4bd-5dbf09b98a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040917424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.3040917424
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.2466438328
Short name T700
Test name
Test status
Simulation time 76709919 ps
CPU time 2.86 seconds
Started Jul 01 12:31:33 PM PDT 24
Finished Jul 01 12:31:37 PM PDT 24
Peak memory 218044 kb
Host smart-df8003ca-2805-43c2-8b3a-d68f33f3a411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466438328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.2466438328
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.678663840
Short name T696
Test name
Test status
Simulation time 403229351 ps
CPU time 23.68 seconds
Started Jul 01 12:31:30 PM PDT 24
Finished Jul 01 12:31:54 PM PDT 24
Peak memory 246564 kb
Host smart-ec81bfd2-c083-46b2-bbdb-4729fc82c827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678663840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.678663840
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.2094484677
Short name T837
Test name
Test status
Simulation time 71696390 ps
CPU time 8.41 seconds
Started Jul 01 12:31:27 PM PDT 24
Finished Jul 01 12:31:36 PM PDT 24
Peak memory 251324 kb
Host smart-38890a5e-109c-468c-98e8-951f960124fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094484677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.2094484677
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.557575592
Short name T653
Test name
Test status
Simulation time 3978340440 ps
CPU time 106.81 seconds
Started Jul 01 12:31:37 PM PDT 24
Finished Jul 01 12:33:25 PM PDT 24
Peak memory 276480 kb
Host smart-1c26827e-dad4-4c1f-b213-a7b7a85bf45e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557575592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.557575592
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.4187897094
Short name T186
Test name
Test status
Simulation time 21588758521 ps
CPU time 790.53 seconds
Started Jul 01 12:31:37 PM PDT 24
Finished Jul 01 12:44:48 PM PDT 24
Peak memory 497288 kb
Host smart-6046455d-652a-4adb-b6ae-df268a1e94a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4187897094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.4187897094
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.3699498419
Short name T248
Test name
Test status
Simulation time 58359489 ps
CPU time 0.7 seconds
Started Jul 01 12:31:27 PM PDT 24
Finished Jul 01 12:31:28 PM PDT 24
Peak memory 207388 kb
Host smart-fe5ed849-45f9-4a89-bab5-d0ed6602806b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699498419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.3699498419
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.3486251594
Short name T706
Test name
Test status
Simulation time 36343083 ps
CPU time 1.12 seconds
Started Jul 01 12:31:43 PM PDT 24
Finished Jul 01 12:31:45 PM PDT 24
Peak memory 209336 kb
Host smart-6a430323-834c-4039-b990-f5a54ff34b4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486251594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.3486251594
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.4099100186
Short name T184
Test name
Test status
Simulation time 587253363 ps
CPU time 13.83 seconds
Started Jul 01 12:31:46 PM PDT 24
Finished Jul 01 12:32:01 PM PDT 24
Peak memory 218636 kb
Host smart-243d0de6-f8f2-4f90-9f56-48d38b63f273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099100186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.4099100186
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.2224762295
Short name T704
Test name
Test status
Simulation time 2710133584 ps
CPU time 16.33 seconds
Started Jul 01 12:31:46 PM PDT 24
Finished Jul 01 12:32:04 PM PDT 24
Peak memory 218120 kb
Host smart-bf53759b-f1ee-4c1a-a1cf-865e7f4e0e05
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224762295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.2224762295
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.180500571
Short name T636
Test name
Test status
Simulation time 1886233272 ps
CPU time 30.47 seconds
Started Jul 01 12:31:42 PM PDT 24
Finished Jul 01 12:32:13 PM PDT 24
Peak memory 218592 kb
Host smart-f3eb9817-df91-40ef-9ba1-1e759457f276
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180500571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_er
rors.180500571
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.495475823
Short name T484
Test name
Test status
Simulation time 603404946 ps
CPU time 9.94 seconds
Started Jul 01 12:31:46 PM PDT 24
Finished Jul 01 12:31:58 PM PDT 24
Peak memory 223408 kb
Host smart-afae4dc2-3761-49b3-8719-7714cc3a4101
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495475823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag
_prog_failure.495475823
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.2935322260
Short name T83
Test name
Test status
Simulation time 249759298 ps
CPU time 4.42 seconds
Started Jul 01 12:31:46 PM PDT 24
Finished Jul 01 12:31:51 PM PDT 24
Peak memory 217992 kb
Host smart-80181d3e-862c-433e-8998-e8d67e928a6a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935322260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.2935322260
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.2477906239
Short name T708
Test name
Test status
Simulation time 2589268968 ps
CPU time 61.95 seconds
Started Jul 01 12:31:45 PM PDT 24
Finished Jul 01 12:32:48 PM PDT 24
Peak memory 277640 kb
Host smart-5ecfb1b7-453b-4d1a-b9f4-b3004f950e8e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477906239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.2477906239
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.2615483569
Short name T231
Test name
Test status
Simulation time 791221183 ps
CPU time 21.65 seconds
Started Jul 01 12:31:37 PM PDT 24
Finished Jul 01 12:31:59 PM PDT 24
Peak memory 251244 kb
Host smart-beb5d9b9-480b-4be0-8a49-6cdd23949528
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615483569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.2615483569
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.474463216
Short name T744
Test name
Test status
Simulation time 129713388 ps
CPU time 3.6 seconds
Started Jul 01 12:31:45 PM PDT 24
Finished Jul 01 12:31:50 PM PDT 24
Peak memory 223016 kb
Host smart-2fffd033-6248-4641-b593-df1a48ed4f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474463216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.474463216
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.2365619578
Short name T621
Test name
Test status
Simulation time 424382739 ps
CPU time 17.48 seconds
Started Jul 01 12:31:45 PM PDT 24
Finished Jul 01 12:32:03 PM PDT 24
Peak memory 226424 kb
Host smart-7492501e-ec2d-42f4-9394-ab97249aa442
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365619578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.2365619578
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.2449120853
Short name T350
Test name
Test status
Simulation time 909562279 ps
CPU time 13.94 seconds
Started Jul 01 12:31:43 PM PDT 24
Finished Jul 01 12:31:58 PM PDT 24
Peak memory 218652 kb
Host smart-65e5f8ee-3bd5-4a93-991b-4ba81184b55d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449120853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.2449120853
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.551611918
Short name T802
Test name
Test status
Simulation time 1115879359 ps
CPU time 11.57 seconds
Started Jul 01 12:31:42 PM PDT 24
Finished Jul 01 12:31:55 PM PDT 24
Peak memory 218512 kb
Host smart-a7078e82-e13a-4d90-821d-19118ec1c958
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551611918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.551611918
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.2889932451
Short name T755
Test name
Test status
Simulation time 636335776 ps
CPU time 7.5 seconds
Started Jul 01 12:31:45 PM PDT 24
Finished Jul 01 12:31:54 PM PDT 24
Peak memory 224856 kb
Host smart-267822ee-b3d1-40a6-862a-f5e99a554aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889932451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.2889932451
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.1906442776
Short name T541
Test name
Test status
Simulation time 747085859 ps
CPU time 10.08 seconds
Started Jul 01 12:31:46 PM PDT 24
Finished Jul 01 12:31:57 PM PDT 24
Peak memory 218064 kb
Host smart-a372bb44-1383-414b-a9f3-de621ec106f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906442776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.1906442776
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.2428398460
Short name T775
Test name
Test status
Simulation time 968692967 ps
CPU time 29.7 seconds
Started Jul 01 12:31:46 PM PDT 24
Finished Jul 01 12:32:17 PM PDT 24
Peak memory 245604 kb
Host smart-f98f712c-7f43-4196-9419-6bc25bfb5130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428398460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.2428398460
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.3106105865
Short name T104
Test name
Test status
Simulation time 67024924 ps
CPU time 8.34 seconds
Started Jul 01 12:31:45 PM PDT 24
Finished Jul 01 12:31:54 PM PDT 24
Peak memory 251256 kb
Host smart-611f559c-792e-4308-8f87-9a25e08fddb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106105865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.3106105865
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.1043502571
Short name T483
Test name
Test status
Simulation time 2527381155 ps
CPU time 7.27 seconds
Started Jul 01 12:31:44 PM PDT 24
Finished Jul 01 12:31:52 PM PDT 24
Peak memory 226508 kb
Host smart-eb9dc69f-3521-49de-b213-4a50a02f2218
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043502571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.1043502571
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.1934916698
Short name T32
Test name
Test status
Simulation time 13781588 ps
CPU time 0.77 seconds
Started Jul 01 12:31:40 PM PDT 24
Finished Jul 01 12:31:41 PM PDT 24
Peak memory 209036 kb
Host smart-3c651e8f-2285-4c72-9b0e-28a06ebf9ef9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934916698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.1934916698
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.3953853940
Short name T693
Test name
Test status
Simulation time 25860690 ps
CPU time 1.3 seconds
Started Jul 01 12:31:55 PM PDT 24
Finished Jul 01 12:31:57 PM PDT 24
Peak memory 209384 kb
Host smart-fa7233e1-28d6-477b-bf17-759cb3f8880d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953853940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.3953853940
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.2549286647
Short name T549
Test name
Test status
Simulation time 841286554 ps
CPU time 18.06 seconds
Started Jul 01 12:31:48 PM PDT 24
Finished Jul 01 12:32:07 PM PDT 24
Peak memory 226420 kb
Host smart-6b9b3a5d-7083-4ea5-a6d6-d7ac12630903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549286647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.2549286647
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.3290468631
Short name T8
Test name
Test status
Simulation time 313172523 ps
CPU time 9.13 seconds
Started Jul 01 12:31:53 PM PDT 24
Finished Jul 01 12:32:03 PM PDT 24
Peak memory 218084 kb
Host smart-f6c2ea1e-6176-4a24-9788-234f6b24a941
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290468631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.3290468631
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.2461816565
Short name T584
Test name
Test status
Simulation time 3021486771 ps
CPU time 23.39 seconds
Started Jul 01 12:31:48 PM PDT 24
Finished Jul 01 12:32:12 PM PDT 24
Peak memory 226452 kb
Host smart-45d3ddb4-5bea-41db-a345-898c0cb78d52
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461816565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.2461816565
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.709999079
Short name T827
Test name
Test status
Simulation time 198834725 ps
CPU time 2.7 seconds
Started Jul 01 12:31:47 PM PDT 24
Finished Jul 01 12:31:51 PM PDT 24
Peak memory 218584 kb
Host smart-118cec46-3d90-413c-a08b-140425bb9e2c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709999079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag
_prog_failure.709999079
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.673318554
Short name T628
Test name
Test status
Simulation time 1843948587 ps
CPU time 7.29 seconds
Started Jul 01 12:31:47 PM PDT 24
Finished Jul 01 12:31:56 PM PDT 24
Peak memory 217988 kb
Host smart-83fe974a-480f-4c45-96da-4cc3d2a85210
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673318554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke.
673318554
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.1499851075
Short name T707
Test name
Test status
Simulation time 4922557008 ps
CPU time 86.85 seconds
Started Jul 01 12:31:48 PM PDT 24
Finished Jul 01 12:33:17 PM PDT 24
Peak memory 278960 kb
Host smart-8f3d3523-cfaa-4cc9-b641-a6e6cf9871be
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499851075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.1499851075
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.3100661384
Short name T425
Test name
Test status
Simulation time 2253416980 ps
CPU time 18.71 seconds
Started Jul 01 12:31:47 PM PDT 24
Finished Jul 01 12:32:07 PM PDT 24
Peak memory 251328 kb
Host smart-28b87536-6d32-4548-b17e-4f2426c6852a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100661384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.3100661384
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.1442514321
Short name T728
Test name
Test status
Simulation time 444950175 ps
CPU time 3.4 seconds
Started Jul 01 12:31:47 PM PDT 24
Finished Jul 01 12:31:51 PM PDT 24
Peak memory 222848 kb
Host smart-54716c56-de4c-4da3-8b3f-3e4f6c475b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442514321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.1442514321
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.911578258
Short name T617
Test name
Test status
Simulation time 561623952 ps
CPU time 14.94 seconds
Started Jul 01 12:32:00 PM PDT 24
Finished Jul 01 12:32:15 PM PDT 24
Peak memory 226376 kb
Host smart-3a331a6b-b62e-4e44-aa4f-4487a499951e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911578258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.911578258
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.3254204653
Short name T723
Test name
Test status
Simulation time 280430480 ps
CPU time 10.21 seconds
Started Jul 01 12:31:54 PM PDT 24
Finished Jul 01 12:32:05 PM PDT 24
Peak memory 218620 kb
Host smart-617c57b5-af97-4ccc-af15-7929e41316f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254204653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.3254204653
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.3948069969
Short name T526
Test name
Test status
Simulation time 174575933 ps
CPU time 5.29 seconds
Started Jul 01 12:31:54 PM PDT 24
Finished Jul 01 12:32:00 PM PDT 24
Peak memory 224628 kb
Host smart-2a9f54b0-4a33-452f-b5b7-9161d4036ccd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948069969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
3948069969
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.4032009627
Short name T839
Test name
Test status
Simulation time 628613484 ps
CPU time 12.15 seconds
Started Jul 01 12:31:48 PM PDT 24
Finished Jul 01 12:32:01 PM PDT 24
Peak memory 226436 kb
Host smart-b5fd983f-2ead-4b10-8859-666467806a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032009627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.4032009627
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.1349615088
Short name T521
Test name
Test status
Simulation time 16425048 ps
CPU time 1.57 seconds
Started Jul 01 12:31:42 PM PDT 24
Finished Jul 01 12:31:45 PM PDT 24
Peak memory 213892 kb
Host smart-1d70ae80-519a-4469-bb73-b96808e0b06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349615088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.1349615088
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.665468844
Short name T299
Test name
Test status
Simulation time 1192543081 ps
CPU time 28.46 seconds
Started Jul 01 12:31:48 PM PDT 24
Finished Jul 01 12:32:18 PM PDT 24
Peak memory 251320 kb
Host smart-58120eef-7d2a-4f60-a6c3-25bbadd59271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665468844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.665468844
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.3013523559
Short name T245
Test name
Test status
Simulation time 266074019 ps
CPU time 6.84 seconds
Started Jul 01 12:31:49 PM PDT 24
Finished Jul 01 12:31:57 PM PDT 24
Peak memory 247184 kb
Host smart-2369856b-3430-434e-9bac-ea2f99287ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013523559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.3013523559
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.973027126
Short name T293
Test name
Test status
Simulation time 18202809 ps
CPU time 0.8 seconds
Started Jul 01 12:31:49 PM PDT 24
Finished Jul 01 12:31:51 PM PDT 24
Peak memory 209444 kb
Host smart-f8ea5b39-a353-4921-82b9-029089567869
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973027126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ct
rl_volatile_unlock_smoke.973027126
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.3023187722
Short name T91
Test name
Test status
Simulation time 18420815 ps
CPU time 1.03 seconds
Started Jul 01 12:32:02 PM PDT 24
Finished Jul 01 12:32:03 PM PDT 24
Peak memory 209340 kb
Host smart-709f86e9-59b9-4372-83e2-c19213efa203
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023187722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.3023187722
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.3295819632
Short name T684
Test name
Test status
Simulation time 3119997987 ps
CPU time 14.39 seconds
Started Jul 01 12:31:55 PM PDT 24
Finished Jul 01 12:32:11 PM PDT 24
Peak memory 219348 kb
Host smart-5ab920e6-8eb6-4d09-81f3-0ce4b330a4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295819632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.3295819632
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.2733592033
Short name T748
Test name
Test status
Simulation time 835652830 ps
CPU time 19.35 seconds
Started Jul 01 12:32:01 PM PDT 24
Finished Jul 01 12:32:21 PM PDT 24
Peak memory 217840 kb
Host smart-48d9aa9a-3a6c-4500-a313-75a4b4386712
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733592033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.2733592033
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.9222152
Short name T603
Test name
Test status
Simulation time 6017530329 ps
CPU time 26.39 seconds
Started Jul 01 12:32:00 PM PDT 24
Finished Jul 01 12:32:27 PM PDT 24
Peak memory 226556 kb
Host smart-3867a134-6318-4686-908e-d71314f97f9c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9222152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc
_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_erro
rs.9222152
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.2988462313
Short name T463
Test name
Test status
Simulation time 512967101 ps
CPU time 8.44 seconds
Started Jul 01 12:31:59 PM PDT 24
Finished Jul 01 12:32:08 PM PDT 24
Peak memory 218568 kb
Host smart-6cc63484-2840-4f10-88fe-f99b4bc6f2f3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988462313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.2988462313
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.3614281914
Short name T311
Test name
Test status
Simulation time 2989242962 ps
CPU time 6.18 seconds
Started Jul 01 12:31:59 PM PDT 24
Finished Jul 01 12:32:07 PM PDT 24
Peak memory 218048 kb
Host smart-709ac316-d894-42de-a477-ff285aab0b0f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614281914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.3614281914
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.1078497744
Short name T725
Test name
Test status
Simulation time 1935776120 ps
CPU time 43.56 seconds
Started Jul 01 12:32:00 PM PDT 24
Finished Jul 01 12:32:44 PM PDT 24
Peak memory 275784 kb
Host smart-bdd0bc7e-c43a-4634-9f00-47de5b604903
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078497744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.1078497744
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.1438608464
Short name T116
Test name
Test status
Simulation time 709054712 ps
CPU time 11.65 seconds
Started Jul 01 12:31:59 PM PDT 24
Finished Jul 01 12:32:11 PM PDT 24
Peak memory 243048 kb
Host smart-cac147da-4de8-43c7-944b-b477b70e529f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438608464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.1438608464
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.1908909183
Short name T389
Test name
Test status
Simulation time 174804540 ps
CPU time 1.53 seconds
Started Jul 01 12:31:55 PM PDT 24
Finished Jul 01 12:31:57 PM PDT 24
Peak memory 218616 kb
Host smart-ee686132-254c-4d4b-9e7a-585af0a26ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908909183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.1908909183
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.508628152
Short name T638
Test name
Test status
Simulation time 313666017 ps
CPU time 10.03 seconds
Started Jul 01 12:31:59 PM PDT 24
Finished Jul 01 12:32:09 PM PDT 24
Peak memory 226376 kb
Host smart-ea96e051-870a-409c-b4f1-ef5909f9ee83
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508628152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.508628152
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.669136496
Short name T447
Test name
Test status
Simulation time 336107648 ps
CPU time 14.35 seconds
Started Jul 01 12:32:01 PM PDT 24
Finished Jul 01 12:32:16 PM PDT 24
Peak memory 218592 kb
Host smart-5f852e22-055d-4d1a-8441-b68e85ef7958
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669136496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_di
gest.669136496
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.2326098704
Short name T276
Test name
Test status
Simulation time 988577907 ps
CPU time 20.44 seconds
Started Jul 01 12:31:59 PM PDT 24
Finished Jul 01 12:32:19 PM PDT 24
Peak memory 226420 kb
Host smart-ce676662-5768-4cc1-a07f-43f652fae97c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326098704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
2326098704
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.3009884593
Short name T789
Test name
Test status
Simulation time 282252072 ps
CPU time 9.55 seconds
Started Jul 01 12:31:53 PM PDT 24
Finished Jul 01 12:32:04 PM PDT 24
Peak memory 218772 kb
Host smart-743d73e6-a917-4e01-9fbb-5b0c74aa77ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009884593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.3009884593
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.1635436817
Short name T810
Test name
Test status
Simulation time 584220523 ps
CPU time 20.41 seconds
Started Jul 01 12:31:53 PM PDT 24
Finished Jul 01 12:32:14 PM PDT 24
Peak memory 251320 kb
Host smart-4829172f-fa87-4dc6-85b9-2dbe80bbc471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635436817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.1635436817
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.4016943883
Short name T569
Test name
Test status
Simulation time 594109758 ps
CPU time 10.16 seconds
Started Jul 01 12:31:55 PM PDT 24
Finished Jul 01 12:32:06 PM PDT 24
Peak memory 251352 kb
Host smart-b688fc4f-9c16-4d5d-954f-16cd7c3cf196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016943883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.4016943883
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.1643757801
Short name T490
Test name
Test status
Simulation time 12326809552 ps
CPU time 287.03 seconds
Started Jul 01 12:32:00 PM PDT 24
Finished Jul 01 12:36:48 PM PDT 24
Peak memory 422280 kb
Host smart-ee2c139e-1809-41c5-8496-dda931d6b08b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643757801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.1643757801
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.4039100686
Short name T398
Test name
Test status
Simulation time 25164930 ps
CPU time 0.78 seconds
Started Jul 01 12:31:59 PM PDT 24
Finished Jul 01 12:32:00 PM PDT 24
Peak memory 209204 kb
Host smart-e10e0ce5-743f-42b0-89be-896cc48d4c7d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039100686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.4039100686
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.2204383580
Short name T365
Test name
Test status
Simulation time 23697809 ps
CPU time 1.01 seconds
Started Jul 01 12:32:14 PM PDT 24
Finished Jul 01 12:32:16 PM PDT 24
Peak memory 209332 kb
Host smart-58dcf6bb-5aff-4627-bc80-ee944c0035ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204383580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.2204383580
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.2864182473
Short name T581
Test name
Test status
Simulation time 443838940 ps
CPU time 11.8 seconds
Started Jul 01 12:32:03 PM PDT 24
Finished Jul 01 12:32:16 PM PDT 24
Peak memory 218632 kb
Host smart-a55e552e-e442-48a5-87bb-78eca44dd15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864182473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.2864182473
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.3824761800
Short name T854
Test name
Test status
Simulation time 476304781 ps
CPU time 2.26 seconds
Started Jul 01 12:32:07 PM PDT 24
Finished Jul 01 12:32:09 PM PDT 24
Peak memory 217392 kb
Host smart-e3d26083-8e40-427d-9708-d4caa834d5a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824761800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.3824761800
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.25209528
Short name T324
Test name
Test status
Simulation time 4964753716 ps
CPU time 69.87 seconds
Started Jul 01 12:32:10 PM PDT 24
Finished Jul 01 12:33:21 PM PDT 24
Peak memory 219140 kb
Host smart-d3638c47-6d7b-4d19-91f7-9140a49ea312
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25209528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_l
c_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_err
ors.25209528
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.3406131563
Short name T687
Test name
Test status
Simulation time 157624112 ps
CPU time 3.27 seconds
Started Jul 01 12:32:11 PM PDT 24
Finished Jul 01 12:32:15 PM PDT 24
Peak memory 222156 kb
Host smart-d4f55302-8421-4e01-8820-a933a7eb6e7f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406131563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.3406131563
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.1290048191
Short name T85
Test name
Test status
Simulation time 1075077327 ps
CPU time 9.61 seconds
Started Jul 01 12:32:03 PM PDT 24
Finished Jul 01 12:32:14 PM PDT 24
Peak memory 217928 kb
Host smart-a36f6eb5-305a-4fa3-b9fe-6aac3812f00f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290048191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.1290048191
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.568419914
Short name T452
Test name
Test status
Simulation time 3512667667 ps
CPU time 32.81 seconds
Started Jul 01 12:32:04 PM PDT 24
Finished Jul 01 12:32:38 PM PDT 24
Peak memory 251256 kb
Host smart-3dda3167-2926-4be6-a539-b75487b6010e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568419914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_state_failure.568419914
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.2314584554
Short name T855
Test name
Test status
Simulation time 1815742185 ps
CPU time 7.82 seconds
Started Jul 01 12:32:03 PM PDT 24
Finished Jul 01 12:32:11 PM PDT 24
Peak memory 226644 kb
Host smart-a1902912-cde9-4149-acb3-a6720168c782
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314584554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.2314584554
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.1124105601
Short name T862
Test name
Test status
Simulation time 188120514 ps
CPU time 4.19 seconds
Started Jul 01 12:32:07 PM PDT 24
Finished Jul 01 12:32:12 PM PDT 24
Peak memory 222956 kb
Host smart-b91ee673-d84d-4275-a228-4bd18d9e6fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124105601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.1124105601
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.484758885
Short name T416
Test name
Test status
Simulation time 10800249405 ps
CPU time 16.55 seconds
Started Jul 01 12:32:11 PM PDT 24
Finished Jul 01 12:32:28 PM PDT 24
Peak memory 218700 kb
Host smart-c1c6279b-4dfc-4e13-ac07-9b9ef5499737
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484758885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_di
gest.484758885
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.585461519
Short name T819
Test name
Test status
Simulation time 525208152 ps
CPU time 9.83 seconds
Started Jul 01 12:32:09 PM PDT 24
Finished Jul 01 12:32:19 PM PDT 24
Peak memory 226384 kb
Host smart-312bea39-b797-4284-b726-3305b96f53f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585461519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.585461519
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.1937002398
Short name T462
Test name
Test status
Simulation time 1433375068 ps
CPU time 10.36 seconds
Started Jul 01 12:32:03 PM PDT 24
Finished Jul 01 12:32:14 PM PDT 24
Peak memory 226460 kb
Host smart-32c24fb7-7a3c-4a61-a7c3-789a0b025f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937002398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.1937002398
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.1201103046
Short name T494
Test name
Test status
Simulation time 47900186 ps
CPU time 2.08 seconds
Started Jul 01 12:32:04 PM PDT 24
Finished Jul 01 12:32:07 PM PDT 24
Peak memory 223904 kb
Host smart-74a374e1-d685-4db3-b2a6-5cab7c388d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201103046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.1201103046
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.3707827043
Short name T694
Test name
Test status
Simulation time 1224133099 ps
CPU time 29.74 seconds
Started Jul 01 12:32:07 PM PDT 24
Finished Jul 01 12:32:37 PM PDT 24
Peak memory 251428 kb
Host smart-e9383873-e71d-43fa-9b1f-3e87d7023c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707827043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.3707827043
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.1808898055
Short name T254
Test name
Test status
Simulation time 85017226 ps
CPU time 7.57 seconds
Started Jul 01 12:32:03 PM PDT 24
Finished Jul 01 12:32:12 PM PDT 24
Peak memory 251248 kb
Host smart-b6353bc8-802a-4a5e-9b74-99670914b19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808898055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.1808898055
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.3665930121
Short name T771
Test name
Test status
Simulation time 974129103 ps
CPU time 27.89 seconds
Started Jul 01 12:32:10 PM PDT 24
Finished Jul 01 12:32:38 PM PDT 24
Peak memory 226676 kb
Host smart-a7dd6b6b-cda8-42fb-bc7a-6c42a375b035
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665930121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.3665930121
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.107502391
Short name T69
Test name
Test status
Simulation time 28935047 ps
CPU time 1.03 seconds
Started Jul 01 12:32:07 PM PDT 24
Finished Jul 01 12:32:09 PM PDT 24
Peak memory 212244 kb
Host smart-a7326242-ee67-4a58-8b1d-16a76cba0a94
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107502391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ct
rl_volatile_unlock_smoke.107502391
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.1864489520
Short name T504
Test name
Test status
Simulation time 77624450 ps
CPU time 1.03 seconds
Started Jul 01 12:32:23 PM PDT 24
Finished Jul 01 12:32:25 PM PDT 24
Peak memory 209372 kb
Host smart-bf91abfa-a042-4b41-b292-99c1581fcc0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864489520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.1864489520
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.3154378989
Short name T453
Test name
Test status
Simulation time 461262498 ps
CPU time 13.16 seconds
Started Jul 01 12:32:17 PM PDT 24
Finished Jul 01 12:32:31 PM PDT 24
Peak memory 226336 kb
Host smart-f6255589-7d9a-4c0b-8817-5d1db62ebc71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154378989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.3154378989
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.1758118609
Short name T200
Test name
Test status
Simulation time 386258206 ps
CPU time 5.63 seconds
Started Jul 01 12:32:18 PM PDT 24
Finished Jul 01 12:32:24 PM PDT 24
Peak memory 217564 kb
Host smart-aee2746f-022d-4d6b-b8b8-5e36f642b0c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758118609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.1758118609
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.2624717704
Short name T392
Test name
Test status
Simulation time 2309822202 ps
CPU time 39.57 seconds
Started Jul 01 12:32:18 PM PDT 24
Finished Jul 01 12:32:59 PM PDT 24
Peak memory 226452 kb
Host smart-6dec9306-21d1-41d8-8a56-a50effd80ba2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624717704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.2624717704
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.3616647708
Short name T869
Test name
Test status
Simulation time 233499410 ps
CPU time 1.96 seconds
Started Jul 01 12:32:17 PM PDT 24
Finished Jul 01 12:32:19 PM PDT 24
Peak memory 218540 kb
Host smart-d9d52329-c336-4c00-92e7-16b317807fb0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616647708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.3616647708
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.1844303782
Short name T309
Test name
Test status
Simulation time 3369130873 ps
CPU time 5.43 seconds
Started Jul 01 12:32:20 PM PDT 24
Finished Jul 01 12:32:27 PM PDT 24
Peak memory 218028 kb
Host smart-5ba4c694-f25f-4c7e-91bc-bc7dadb8792e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844303782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.1844303782
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.2290454876
Short name T872
Test name
Test status
Simulation time 5601857394 ps
CPU time 46.88 seconds
Started Jul 01 12:32:19 PM PDT 24
Finished Jul 01 12:33:06 PM PDT 24
Peak memory 267944 kb
Host smart-ee4b9b4c-0f5f-40cd-9340-a0fbc52636a1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290454876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.2290454876
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.2521882145
Short name T489
Test name
Test status
Simulation time 249113411 ps
CPU time 10.16 seconds
Started Jul 01 12:32:21 PM PDT 24
Finished Jul 01 12:32:32 PM PDT 24
Peak memory 251228 kb
Host smart-e311161a-1c77-487a-98e4-f3217d896a78
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521882145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.2521882145
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.436507114
Short name T413
Test name
Test status
Simulation time 68019864 ps
CPU time 2.96 seconds
Started Jul 01 12:32:17 PM PDT 24
Finished Jul 01 12:32:21 PM PDT 24
Peak memory 218560 kb
Host smart-6ec74c02-c8ce-4fa2-8c64-3f1e1ca831c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436507114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.436507114
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.954859205
Short name T233
Test name
Test status
Simulation time 275912560 ps
CPU time 14.81 seconds
Started Jul 01 12:32:21 PM PDT 24
Finished Jul 01 12:32:37 PM PDT 24
Peak memory 226448 kb
Host smart-c2896c78-978a-4fd2-9408-bf4f9d05db07
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954859205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.954859205
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.539845876
Short name T772
Test name
Test status
Simulation time 542779720 ps
CPU time 12.68 seconds
Started Jul 01 12:32:18 PM PDT 24
Finished Jul 01 12:32:31 PM PDT 24
Peak memory 218508 kb
Host smart-27fdebf2-bf70-4e6d-9c38-87d314f9116b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539845876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_di
gest.539845876
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.1372201437
Short name T368
Test name
Test status
Simulation time 748573480 ps
CPU time 7.09 seconds
Started Jul 01 12:32:21 PM PDT 24
Finished Jul 01 12:32:29 PM PDT 24
Peak memory 218576 kb
Host smart-768fa5ba-9432-4aeb-8072-6226557ec795
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372201437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
1372201437
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.1738299091
Short name T550
Test name
Test status
Simulation time 511382064 ps
CPU time 6.44 seconds
Started Jul 01 12:32:17 PM PDT 24
Finished Jul 01 12:32:24 PM PDT 24
Peak memory 218900 kb
Host smart-c440c488-4ba6-4131-8f13-544343a8b251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738299091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.1738299091
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.2599990500
Short name T249
Test name
Test status
Simulation time 38873399 ps
CPU time 1.08 seconds
Started Jul 01 12:32:14 PM PDT 24
Finished Jul 01 12:32:15 PM PDT 24
Peak memory 212396 kb
Host smart-ac0a5a8f-b57b-431d-b551-c580e24eb77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599990500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.2599990500
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.3060222305
Short name T754
Test name
Test status
Simulation time 401807530 ps
CPU time 16.01 seconds
Started Jul 01 12:32:14 PM PDT 24
Finished Jul 01 12:32:31 PM PDT 24
Peak memory 251336 kb
Host smart-3c3b9497-4a03-4cb0-8ccd-dad33bed3048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060222305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.3060222305
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.1281833436
Short name T449
Test name
Test status
Simulation time 48730556 ps
CPU time 6.43 seconds
Started Jul 01 12:32:13 PM PDT 24
Finished Jul 01 12:32:20 PM PDT 24
Peak memory 247764 kb
Host smart-ffa51dae-d76a-4d33-8ec0-ba61ed228e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281833436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.1281833436
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.1742792798
Short name T486
Test name
Test status
Simulation time 18819324593 ps
CPU time 240.69 seconds
Started Jul 01 12:32:25 PM PDT 24
Finished Jul 01 12:36:26 PM PDT 24
Peak memory 422412 kb
Host smart-e1cad736-726a-4b75-ac92-45304ce5555d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742792798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.1742792798
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.3547475175
Short name T46
Test name
Test status
Simulation time 15000187 ps
CPU time 1.18 seconds
Started Jul 01 12:32:15 PM PDT 24
Finished Jul 01 12:32:17 PM PDT 24
Peak memory 218096 kb
Host smart-2343615e-039d-45d6-9c57-f534818f8ce3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547475175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.3547475175
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.3463705552
Short name T608
Test name
Test status
Simulation time 19790714 ps
CPU time 0.95 seconds
Started Jul 01 12:32:30 PM PDT 24
Finished Jul 01 12:32:31 PM PDT 24
Peak memory 209408 kb
Host smart-ac53fc82-c89a-47bf-8858-185318d3309d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463705552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.3463705552
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.3781698586
Short name T185
Test name
Test status
Simulation time 3007823244 ps
CPU time 11.9 seconds
Started Jul 01 12:32:28 PM PDT 24
Finished Jul 01 12:32:41 PM PDT 24
Peak memory 218720 kb
Host smart-fe524726-dced-4279-af45-541103ea0a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781698586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.3781698586
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.565132517
Short name T540
Test name
Test status
Simulation time 237317523 ps
CPU time 2.73 seconds
Started Jul 01 12:32:29 PM PDT 24
Finished Jul 01 12:32:33 PM PDT 24
Peak memory 217504 kb
Host smart-3a7e1daa-9f03-46e8-82a5-5e971092752c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565132517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.565132517
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.2593062498
Short name T470
Test name
Test status
Simulation time 1188231130 ps
CPU time 28.38 seconds
Started Jul 01 12:32:28 PM PDT 24
Finished Jul 01 12:32:58 PM PDT 24
Peak memory 226380 kb
Host smart-61daf062-9656-4078-9e85-53eb93966c27
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593062498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.2593062498
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.2327097195
Short name T348
Test name
Test status
Simulation time 4398681905 ps
CPU time 6.77 seconds
Started Jul 01 12:32:34 PM PDT 24
Finished Jul 01 12:32:41 PM PDT 24
Peak memory 218556 kb
Host smart-f754859d-6e73-489e-bf48-1371f5050424
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327097195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.2327097195
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.1524571770
Short name T68
Test name
Test status
Simulation time 2680198380 ps
CPU time 8.43 seconds
Started Jul 01 12:32:31 PM PDT 24
Finished Jul 01 12:32:40 PM PDT 24
Peak memory 218056 kb
Host smart-4819547d-1b12-4c09-bdb1-b47281fe0cfb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524571770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.1524571770
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.3946238064
Short name T384
Test name
Test status
Simulation time 2624815444 ps
CPU time 53.37 seconds
Started Jul 01 12:32:29 PM PDT 24
Finished Jul 01 12:33:23 PM PDT 24
Peak memory 267716 kb
Host smart-d7a5ffbc-a448-4816-9033-c5556d10f44c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946238064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.3946238064
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.1167557182
Short name T240
Test name
Test status
Simulation time 643068872 ps
CPU time 10.35 seconds
Started Jul 01 12:32:31 PM PDT 24
Finished Jul 01 12:32:42 PM PDT 24
Peak memory 223308 kb
Host smart-b1487ea3-69f2-4f60-ba9d-9694a35d0da7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167557182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.1167557182
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.633686132
Short name T826
Test name
Test status
Simulation time 60955959 ps
CPU time 2.53 seconds
Started Jul 01 12:32:25 PM PDT 24
Finished Jul 01 12:32:28 PM PDT 24
Peak memory 218696 kb
Host smart-698009a0-f54c-4eb9-a5e2-5b8b991946f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633686132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.633686132
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.3240449808
Short name T856
Test name
Test status
Simulation time 369420671 ps
CPU time 10.06 seconds
Started Jul 01 12:32:30 PM PDT 24
Finished Jul 01 12:32:41 PM PDT 24
Peak memory 226408 kb
Host smart-c072312b-0f1c-4481-93c2-5b6d57726672
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240449808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.3240449808
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.2368519051
Short name T776
Test name
Test status
Simulation time 354761434 ps
CPU time 11.92 seconds
Started Jul 01 12:32:35 PM PDT 24
Finished Jul 01 12:32:47 PM PDT 24
Peak memory 218528 kb
Host smart-5c4d95a6-6c5a-42ef-8392-473cb744c6f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368519051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.2368519051
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.341372906
Short name T733
Test name
Test status
Simulation time 478252580 ps
CPU time 9.58 seconds
Started Jul 01 12:32:29 PM PDT 24
Finished Jul 01 12:32:39 PM PDT 24
Peak memory 226396 kb
Host smart-48a8351c-5168-4e75-9921-208fd2b4de55
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341372906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.341372906
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.262778481
Short name T588
Test name
Test status
Simulation time 1305905610 ps
CPU time 9.95 seconds
Started Jul 01 12:32:30 PM PDT 24
Finished Jul 01 12:32:40 PM PDT 24
Peak memory 226432 kb
Host smart-95d16673-0195-4d1d-8ff9-b368f65ac60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262778481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.262778481
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.2034627677
Short name T327
Test name
Test status
Simulation time 282986335 ps
CPU time 2.09 seconds
Started Jul 01 12:32:24 PM PDT 24
Finished Jul 01 12:32:27 PM PDT 24
Peak memory 218080 kb
Host smart-588eeab9-dff8-4ab9-a90d-20fe4e34c01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034627677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.2034627677
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.2661544215
Short name T372
Test name
Test status
Simulation time 164361753 ps
CPU time 21.12 seconds
Started Jul 01 12:32:26 PM PDT 24
Finished Jul 01 12:32:47 PM PDT 24
Peak memory 251324 kb
Host smart-eeb892d2-b74b-42f9-a0f8-dcbf3b7345dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661544215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.2661544215
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.4249112109
Short name T273
Test name
Test status
Simulation time 81861253 ps
CPU time 3.73 seconds
Started Jul 01 12:32:28 PM PDT 24
Finished Jul 01 12:32:33 PM PDT 24
Peak memory 223044 kb
Host smart-d27e1daf-91f7-40ff-832c-0fb6007eae32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249112109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.4249112109
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.406666970
Short name T737
Test name
Test status
Simulation time 3217223315 ps
CPU time 36.46 seconds
Started Jul 01 12:32:29 PM PDT 24
Finished Jul 01 12:33:07 PM PDT 24
Peak memory 248116 kb
Host smart-93dfeabf-3913-40fa-a8a4-1903db49e70b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406666970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.406666970
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.78734101
Short name T97
Test name
Test status
Simulation time 29506591243 ps
CPU time 749.7 seconds
Started Jul 01 12:32:28 PM PDT 24
Finished Jul 01 12:44:59 PM PDT 24
Peak memory 480824 kb
Host smart-807a7a08-e0e0-4fe4-a8c8-ad17167f4731
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=78734101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.78734101
Directory /workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.4061455568
Short name T615
Test name
Test status
Simulation time 24349594 ps
CPU time 1.1 seconds
Started Jul 01 12:32:26 PM PDT 24
Finished Jul 01 12:32:28 PM PDT 24
Peak memory 212228 kb
Host smart-b617021e-52e0-4567-ac68-57b9436ed540
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061455568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.4061455568
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.2449795621
Short name T77
Test name
Test status
Simulation time 15542052 ps
CPU time 1.13 seconds
Started Jul 01 12:29:05 PM PDT 24
Finished Jul 01 12:29:06 PM PDT 24
Peak memory 209396 kb
Host smart-53a911e5-b741-4536-aea2-aa8e78d57999
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449795621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.2449795621
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.3473596641
Short name T861
Test name
Test status
Simulation time 696737876 ps
CPU time 14.12 seconds
Started Jul 01 12:28:50 PM PDT 24
Finished Jul 01 12:29:06 PM PDT 24
Peak memory 226424 kb
Host smart-6aa7a2b5-da29-46cc-86a1-aaf0ca439097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473596641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.3473596641
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.2873698431
Short name T99
Test name
Test status
Simulation time 643613219 ps
CPU time 8.18 seconds
Started Jul 01 12:28:59 PM PDT 24
Finished Jul 01 12:29:08 PM PDT 24
Peak memory 217608 kb
Host smart-88c533e6-21df-46ef-880f-52b9643b32fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873698431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.2873698431
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.120349171
Short name T645
Test name
Test status
Simulation time 1375825887 ps
CPU time 41.3 seconds
Started Jul 01 12:28:56 PM PDT 24
Finished Jul 01 12:29:37 PM PDT 24
Peak memory 218504 kb
Host smart-30d43909-4ae8-4528-91be-a5560e39795d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120349171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_err
ors.120349171
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.3183668060
Short name T859
Test name
Test status
Simulation time 1483508971 ps
CPU time 9.27 seconds
Started Jul 01 12:28:58 PM PDT 24
Finished Jul 01 12:29:08 PM PDT 24
Peak memory 217760 kb
Host smart-50ae81a0-cb37-49d1-a3dd-443350932996
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183668060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.3
183668060
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.3678383799
Short name T238
Test name
Test status
Simulation time 151580845 ps
CPU time 3.01 seconds
Started Jul 01 12:28:53 PM PDT 24
Finished Jul 01 12:28:57 PM PDT 24
Peak memory 221996 kb
Host smart-d3616321-3e69-48de-93ec-12cfe4fee362
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678383799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.3678383799
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.604952868
Short name T766
Test name
Test status
Simulation time 706726140 ps
CPU time 21.13 seconds
Started Jul 01 12:29:00 PM PDT 24
Finished Jul 01 12:29:22 PM PDT 24
Peak memory 217852 kb
Host smart-05f13ef9-0a69-49f8-80c2-87d6add2d799
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604952868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_regwen_during_op.604952868
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.884388459
Short name T790
Test name
Test status
Simulation time 1802327814 ps
CPU time 14.72 seconds
Started Jul 01 12:28:55 PM PDT 24
Finished Jul 01 12:29:10 PM PDT 24
Peak memory 217976 kb
Host smart-6813f5db-6afe-40ec-9d9c-2434f505268c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884388459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.884388459
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.4074547264
Short name T95
Test name
Test status
Simulation time 18082168416 ps
CPU time 80.48 seconds
Started Jul 01 12:28:53 PM PDT 24
Finished Jul 01 12:30:14 PM PDT 24
Peak memory 284132 kb
Host smart-9444812a-42b6-44b0-b643-bb31b7b2e399
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074547264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.4074547264
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.943279392
Short name T5
Test name
Test status
Simulation time 270619460 ps
CPU time 6.59 seconds
Started Jul 01 12:28:53 PM PDT 24
Finished Jul 01 12:29:00 PM PDT 24
Peak memory 223392 kb
Host smart-55da429e-e4ee-4c63-ad95-c0657536c0bf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943279392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_state_post_trans.943279392
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.812438099
Short name T495
Test name
Test status
Simulation time 125056734 ps
CPU time 3.14 seconds
Started Jul 01 12:28:45 PM PDT 24
Finished Jul 01 12:28:49 PM PDT 24
Peak memory 218624 kb
Host smart-c4cfdb44-ab22-40c0-aff0-9b6d506b0878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812438099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.812438099
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.2836521093
Short name T576
Test name
Test status
Simulation time 1354936573 ps
CPU time 8.74 seconds
Started Jul 01 12:28:50 PM PDT 24
Finished Jul 01 12:29:00 PM PDT 24
Peak memory 215116 kb
Host smart-91b62ee6-3961-4d75-a53d-1db05c074328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836521093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.2836521093
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.2708179753
Short name T109
Test name
Test status
Simulation time 211588206 ps
CPU time 41.9 seconds
Started Jul 01 12:29:03 PM PDT 24
Finished Jul 01 12:29:46 PM PDT 24
Peak memory 269768 kb
Host smart-0eb93a35-72db-4a68-a44d-500e9d177741
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708179753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.2708179753
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.3766179126
Short name T773
Test name
Test status
Simulation time 634498743 ps
CPU time 14.53 seconds
Started Jul 01 12:28:59 PM PDT 24
Finished Jul 01 12:29:14 PM PDT 24
Peak memory 226380 kb
Host smart-ba32d977-bfdd-4435-8457-11d8f9128da2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766179126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.3766179126
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.3871828242
Short name T430
Test name
Test status
Simulation time 2442653325 ps
CPU time 21.07 seconds
Started Jul 01 12:28:57 PM PDT 24
Finished Jul 01 12:29:19 PM PDT 24
Peak memory 219280 kb
Host smart-7a133894-631f-4490-b48a-406884870e23
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871828242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.3871828242
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.2673687876
Short name T246
Test name
Test status
Simulation time 1078132037 ps
CPU time 9.48 seconds
Started Jul 01 12:28:59 PM PDT 24
Finished Jul 01 12:29:09 PM PDT 24
Peak memory 226360 kb
Host smart-9d5bbd01-a8df-4f37-a433-c96292675bc8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673687876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.2
673687876
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.1839950418
Short name T731
Test name
Test status
Simulation time 615638994 ps
CPU time 12.36 seconds
Started Jul 01 12:28:51 PM PDT 24
Finished Jul 01 12:29:04 PM PDT 24
Peak memory 218656 kb
Host smart-0fbd2234-ab08-43ad-abab-b064c7af9bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839950418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.1839950418
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.1873660859
Short name T639
Test name
Test status
Simulation time 146173669 ps
CPU time 2.14 seconds
Started Jul 01 12:28:44 PM PDT 24
Finished Jul 01 12:28:47 PM PDT 24
Peak memory 218068 kb
Host smart-4d020d1f-2c53-4723-9a61-e7a84658f2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873660859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.1873660859
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.646777061
Short name T382
Test name
Test status
Simulation time 364837079 ps
CPU time 19.41 seconds
Started Jul 01 12:28:45 PM PDT 24
Finished Jul 01 12:29:06 PM PDT 24
Peak memory 246188 kb
Host smart-e54823d4-d1ea-4421-bb32-66c77c150ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646777061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.646777061
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.2314752990
Short name T250
Test name
Test status
Simulation time 297717298 ps
CPU time 10.31 seconds
Started Jul 01 12:28:45 PM PDT 24
Finished Jul 01 12:28:56 PM PDT 24
Peak memory 251196 kb
Host smart-69d25360-b48b-4174-9b3d-6e2f66784efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314752990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.2314752990
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.3117599828
Short name T448
Test name
Test status
Simulation time 66698890364 ps
CPU time 269.59 seconds
Started Jul 01 12:29:00 PM PDT 24
Finished Jul 01 12:33:31 PM PDT 24
Peak memory 283452 kb
Host smart-2b304db6-7f47-4e02-9961-441e44d0cff1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117599828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.3117599828
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.4262704438
Short name T159
Test name
Test status
Simulation time 16077455674 ps
CPU time 518.57 seconds
Started Jul 01 12:29:03 PM PDT 24
Finished Jul 01 12:37:43 PM PDT 24
Peak memory 287276 kb
Host smart-46d5b7b1-dfbb-4d62-a98b-6578e0aa1130
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4262704438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.4262704438
Directory /workspace/2.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.2483498850
Short name T718
Test name
Test status
Simulation time 23141748 ps
CPU time 0.93 seconds
Started Jul 01 12:28:47 PM PDT 24
Finished Jul 01 12:28:48 PM PDT 24
Peak memory 209260 kb
Host smart-1aab98d7-8f2d-42e7-a891-126b36e9bb00
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483498850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.2483498850
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.65356425
Short name T570
Test name
Test status
Simulation time 15002746 ps
CPU time 1.06 seconds
Started Jul 01 12:32:39 PM PDT 24
Finished Jul 01 12:32:41 PM PDT 24
Peak memory 209312 kb
Host smart-aff662a3-6b05-4f49-8d7a-1eda3aaacaf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65356425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.65356425
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.2025309633
Short name T842
Test name
Test status
Simulation time 278111962 ps
CPU time 13.22 seconds
Started Jul 01 12:32:37 PM PDT 24
Finished Jul 01 12:32:51 PM PDT 24
Peak memory 226384 kb
Host smart-3ff8b257-a78c-4c23-b4a1-cda019515e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025309633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.2025309633
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.3466429984
Short name T26
Test name
Test status
Simulation time 186612721 ps
CPU time 2.58 seconds
Started Jul 01 12:32:36 PM PDT 24
Finished Jul 01 12:32:39 PM PDT 24
Peak memory 217496 kb
Host smart-4c0f23d5-c60b-42b9-9254-06bb24abd079
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466429984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.3466429984
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.498106771
Short name T568
Test name
Test status
Simulation time 54468520 ps
CPU time 2.24 seconds
Started Jul 01 12:32:34 PM PDT 24
Finished Jul 01 12:32:37 PM PDT 24
Peak memory 218480 kb
Host smart-5312c3f3-d1aa-4e2d-bdd8-fbe089401fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498106771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.498106771
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.613769091
Short name T334
Test name
Test status
Simulation time 1028518526 ps
CPU time 11.39 seconds
Started Jul 01 12:32:37 PM PDT 24
Finished Jul 01 12:32:49 PM PDT 24
Peak memory 226408 kb
Host smart-4bdbd7ef-3365-4543-8792-c0e94f927cb0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613769091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.613769091
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.3745949327
Short name T503
Test name
Test status
Simulation time 409661964 ps
CPU time 15.15 seconds
Started Jul 01 12:32:35 PM PDT 24
Finished Jul 01 12:32:51 PM PDT 24
Peak memory 218684 kb
Host smart-768a92ac-b230-4ea9-a141-d7d32103b0bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745949327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.3745949327
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.3503863980
Short name T456
Test name
Test status
Simulation time 432817893 ps
CPU time 7.55 seconds
Started Jul 01 12:32:34 PM PDT 24
Finished Jul 01 12:32:42 PM PDT 24
Peak memory 226368 kb
Host smart-a4ba522d-721b-4f90-9180-4a09b972cd7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503863980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
3503863980
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.211512598
Short name T374
Test name
Test status
Simulation time 384852496 ps
CPU time 7.88 seconds
Started Jul 01 12:32:37 PM PDT 24
Finished Jul 01 12:32:45 PM PDT 24
Peak memory 225724 kb
Host smart-c6cf65cf-1194-4839-8f2c-ebef1462ed54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211512598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.211512598
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.2284796135
Short name T575
Test name
Test status
Simulation time 107213585 ps
CPU time 3.22 seconds
Started Jul 01 12:32:28 PM PDT 24
Finished Jul 01 12:32:32 PM PDT 24
Peak memory 214844 kb
Host smart-eb519a7d-cbcc-4929-9937-10fcc99409b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284796135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.2284796135
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.2276384090
Short name T574
Test name
Test status
Simulation time 176446017 ps
CPU time 21.78 seconds
Started Jul 01 12:32:33 PM PDT 24
Finished Jul 01 12:32:55 PM PDT 24
Peak memory 251312 kb
Host smart-5eb6e387-d10b-41dc-8ca0-079c750adb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276384090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.2276384090
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.2191663357
Short name T176
Test name
Test status
Simulation time 85612762 ps
CPU time 8.71 seconds
Started Jul 01 12:32:36 PM PDT 24
Finished Jul 01 12:32:45 PM PDT 24
Peak memory 251000 kb
Host smart-7c5117d3-c4ec-44b5-922f-a04e566bff0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191663357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.2191663357
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.4048857288
Short name T354
Test name
Test status
Simulation time 2408145431 ps
CPU time 79.29 seconds
Started Jul 01 12:32:37 PM PDT 24
Finished Jul 01 12:33:57 PM PDT 24
Peak memory 226468 kb
Host smart-09bd6722-65a8-47c0-a33c-fe526a403f47
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048857288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.4048857288
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.2398950447
Short name T172
Test name
Test status
Simulation time 55192843628 ps
CPU time 260.96 seconds
Started Jul 01 12:32:39 PM PDT 24
Finished Jul 01 12:37:00 PM PDT 24
Peak memory 267836 kb
Host smart-d39e22fb-7d61-4854-a188-4e896853476a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2398950447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all_with_rand_reset.2398950447
Directory /workspace/20.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.1506987744
Short name T836
Test name
Test status
Simulation time 46091024 ps
CPU time 0.79 seconds
Started Jul 01 12:32:28 PM PDT 24
Finished Jul 01 12:32:30 PM PDT 24
Peak memory 209216 kb
Host smart-28a7270e-4b2d-4330-b601-7470fda70bdb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506987744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.1506987744
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.763090904
Short name T178
Test name
Test status
Simulation time 29266689 ps
CPU time 1.04 seconds
Started Jul 01 12:32:40 PM PDT 24
Finished Jul 01 12:32:42 PM PDT 24
Peak memory 209452 kb
Host smart-37058986-7868-4c7f-aa70-e509312a33dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763090904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.763090904
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.3119153175
Short name T466
Test name
Test status
Simulation time 457437984 ps
CPU time 14.4 seconds
Started Jul 01 12:32:39 PM PDT 24
Finished Jul 01 12:32:54 PM PDT 24
Peak memory 218600 kb
Host smart-d79ab9e6-308c-418c-908f-41fab6d0d61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119153175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.3119153175
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.2009541921
Short name T797
Test name
Test status
Simulation time 1141674642 ps
CPU time 6 seconds
Started Jul 01 12:32:42 PM PDT 24
Finished Jul 01 12:32:49 PM PDT 24
Peak memory 217724 kb
Host smart-51092fed-a957-4314-9c0e-e43e049ba224
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009541921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.2009541921
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.3176431112
Short name T703
Test name
Test status
Simulation time 120441839 ps
CPU time 1.66 seconds
Started Jul 01 12:32:39 PM PDT 24
Finished Jul 01 12:32:41 PM PDT 24
Peak memory 222104 kb
Host smart-e0f34136-b09e-4699-b3ab-30abdea2e446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176431112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.3176431112
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.870893845
Short name T545
Test name
Test status
Simulation time 895142686 ps
CPU time 18.73 seconds
Started Jul 01 12:32:40 PM PDT 24
Finished Jul 01 12:33:00 PM PDT 24
Peak memory 226420 kb
Host smart-b7cc9db9-92d4-4eb1-b13c-df1fbc0e9d52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870893845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.870893845
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.2367705327
Short name T340
Test name
Test status
Simulation time 1674962540 ps
CPU time 15.45 seconds
Started Jul 01 12:32:41 PM PDT 24
Finished Jul 01 12:32:57 PM PDT 24
Peak memory 218672 kb
Host smart-936f6bbf-cce9-449f-9de9-adf617b8da73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367705327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.2367705327
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.1795157781
Short name T611
Test name
Test status
Simulation time 837336917 ps
CPU time 9.87 seconds
Started Jul 01 12:32:42 PM PDT 24
Finished Jul 01 12:32:53 PM PDT 24
Peak memory 218528 kb
Host smart-09d83125-5909-4d12-ae2a-4309c9367747
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795157781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
1795157781
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.1077156704
Short name T665
Test name
Test status
Simulation time 1378587267 ps
CPU time 11.79 seconds
Started Jul 01 12:32:41 PM PDT 24
Finished Jul 01 12:32:54 PM PDT 24
Peak memory 226420 kb
Host smart-a6be0c10-296b-440b-9835-f5351b225077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077156704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.1077156704
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.2172385533
Short name T82
Test name
Test status
Simulation time 182556205 ps
CPU time 1.34 seconds
Started Jul 01 12:32:41 PM PDT 24
Finished Jul 01 12:32:43 PM PDT 24
Peak memory 214164 kb
Host smart-ecbfaf70-9723-4314-be28-251fc63069d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172385533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.2172385533
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.2923868121
Short name T577
Test name
Test status
Simulation time 366715026 ps
CPU time 21.43 seconds
Started Jul 01 12:32:39 PM PDT 24
Finished Jul 01 12:33:00 PM PDT 24
Peak memory 251408 kb
Host smart-f7744efa-3ea7-47ae-80e6-6d148e41fb9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923868121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.2923868121
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.3537381228
Short name T764
Test name
Test status
Simulation time 317355893 ps
CPU time 7.92 seconds
Started Jul 01 12:32:41 PM PDT 24
Finished Jul 01 12:32:50 PM PDT 24
Peak memory 251312 kb
Host smart-066fc21c-b144-4018-8019-904bf035c563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537381228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.3537381228
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.342740755
Short name T761
Test name
Test status
Simulation time 4588099578 ps
CPU time 154.84 seconds
Started Jul 01 12:32:41 PM PDT 24
Finished Jul 01 12:35:17 PM PDT 24
Peak memory 280980 kb
Host smart-45018a87-d764-43ce-a786-4e100dff07a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342740755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.342740755
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.1077371534
Short name T746
Test name
Test status
Simulation time 126992863 ps
CPU time 0.91 seconds
Started Jul 01 12:32:40 PM PDT 24
Finished Jul 01 12:32:41 PM PDT 24
Peak memory 209240 kb
Host smart-e5f15cc0-53ce-4710-833e-e12639cd14dc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077371534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.1077371534
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.558414472
Short name T193
Test name
Test status
Simulation time 23367870 ps
CPU time 0.94 seconds
Started Jul 01 12:32:52 PM PDT 24
Finished Jul 01 12:32:53 PM PDT 24
Peak memory 209340 kb
Host smart-c4bb4d4d-7a8a-4fd5-8cd4-08d0c503a785
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558414472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.558414472
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.2883012916
Short name T346
Test name
Test status
Simulation time 2860970651 ps
CPU time 13.51 seconds
Started Jul 01 12:32:50 PM PDT 24
Finished Jul 01 12:33:04 PM PDT 24
Peak memory 219700 kb
Host smart-53f6cd1a-74f3-4f01-8b29-1d044f2b1851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883012916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.2883012916
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.76248915
Short name T817
Test name
Test status
Simulation time 234849823 ps
CPU time 2.22 seconds
Started Jul 01 12:32:45 PM PDT 24
Finished Jul 01 12:32:48 PM PDT 24
Peak memory 217428 kb
Host smart-f9510081-851c-4910-bc8e-8f259e57e71a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76248915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.76248915
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.1180077935
Short name T381
Test name
Test status
Simulation time 52685859 ps
CPU time 2.95 seconds
Started Jul 01 12:32:45 PM PDT 24
Finished Jul 01 12:32:48 PM PDT 24
Peak memory 218620 kb
Host smart-8a2856ed-2a2b-47b1-8c16-d33dbd86784b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180077935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.1180077935
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.1030668330
Short name T36
Test name
Test status
Simulation time 1924733143 ps
CPU time 12.69 seconds
Started Jul 01 12:32:43 PM PDT 24
Finished Jul 01 12:32:56 PM PDT 24
Peak memory 226424 kb
Host smart-fd392702-9cb5-489d-8a79-65c650fb1dd7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030668330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.1030668330
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.2940615290
Short name T820
Test name
Test status
Simulation time 415960761 ps
CPU time 11.6 seconds
Started Jul 01 12:32:44 PM PDT 24
Finished Jul 01 12:32:56 PM PDT 24
Peak memory 218612 kb
Host smart-caf1ca31-b8d1-49cd-aa0b-dad14f0d002d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940615290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.2940615290
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.1884512544
Short name T815
Test name
Test status
Simulation time 519614375 ps
CPU time 12.63 seconds
Started Jul 01 12:32:46 PM PDT 24
Finished Jul 01 12:32:59 PM PDT 24
Peak memory 218596 kb
Host smart-2a4e90c9-c70b-4e02-ad54-69143daff5c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884512544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
1884512544
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.4118201765
Short name T502
Test name
Test status
Simulation time 1057311846 ps
CPU time 7.78 seconds
Started Jul 01 12:32:44 PM PDT 24
Finished Jul 01 12:32:52 PM PDT 24
Peak memory 226412 kb
Host smart-1188bea7-d065-464c-b936-cf25ffa03c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118201765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.4118201765
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.2004970535
Short name T614
Test name
Test status
Simulation time 92141974 ps
CPU time 1.86 seconds
Started Jul 01 12:32:42 PM PDT 24
Finished Jul 01 12:32:45 PM PDT 24
Peak memory 214296 kb
Host smart-edb7a12d-b402-489d-9848-e7f9f5dfb97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004970535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.2004970535
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.1150466951
Short name T471
Test name
Test status
Simulation time 408484520 ps
CPU time 19.83 seconds
Started Jul 01 12:32:44 PM PDT 24
Finished Jul 01 12:33:05 PM PDT 24
Peak memory 251264 kb
Host smart-bf7a3e8d-b8cc-473a-a05d-0bd2a789227c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150466951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.1150466951
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.3909367351
Short name T410
Test name
Test status
Simulation time 144473097 ps
CPU time 7.71 seconds
Started Jul 01 12:32:45 PM PDT 24
Finished Jul 01 12:32:53 PM PDT 24
Peak memory 247212 kb
Host smart-54c934b6-33bd-4f2e-bf0e-084a462b9cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909367351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.3909367351
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.2745680240
Short name T96
Test name
Test status
Simulation time 3413869429 ps
CPU time 111.94 seconds
Started Jul 01 12:32:44 PM PDT 24
Finished Jul 01 12:34:37 PM PDT 24
Peak memory 267848 kb
Host smart-6371a628-5b5e-4c19-af34-6eb2a5ad0891
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745680240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.2745680240
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.2876535018
Short name T795
Test name
Test status
Simulation time 19136997 ps
CPU time 0.91 seconds
Started Jul 01 12:32:54 PM PDT 24
Finished Jul 01 12:32:56 PM PDT 24
Peak memory 209384 kb
Host smart-009e7e49-6f56-43d6-ab3e-59f2c1e69235
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876535018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.2876535018
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.4236763531
Short name T301
Test name
Test status
Simulation time 235928782 ps
CPU time 10.88 seconds
Started Jul 01 12:32:49 PM PDT 24
Finished Jul 01 12:33:00 PM PDT 24
Peak memory 226436 kb
Host smart-f4e15b06-c613-45dc-9aa7-009321244419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236763531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.4236763531
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.3076539903
Short name T793
Test name
Test status
Simulation time 1362746056 ps
CPU time 4.35 seconds
Started Jul 01 12:32:48 PM PDT 24
Finished Jul 01 12:32:52 PM PDT 24
Peak memory 217340 kb
Host smart-8a52d774-2fd7-4440-959a-259a1ad46e5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076539903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.3076539903
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.3188403754
Short name T404
Test name
Test status
Simulation time 111623571 ps
CPU time 2.34 seconds
Started Jul 01 12:32:49 PM PDT 24
Finished Jul 01 12:32:52 PM PDT 24
Peak memory 222648 kb
Host smart-0dfe4f24-fb9e-4639-9ecb-b888cad90b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188403754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.3188403754
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.3716706963
Short name T360
Test name
Test status
Simulation time 312559712 ps
CPU time 15.57 seconds
Started Jul 01 12:32:48 PM PDT 24
Finished Jul 01 12:33:04 PM PDT 24
Peak memory 219296 kb
Host smart-6667c5ef-9414-447a-98f9-bd5b04155b8a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716706963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.3716706963
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.3991191855
Short name T440
Test name
Test status
Simulation time 1485280874 ps
CPU time 11.25 seconds
Started Jul 01 12:32:51 PM PDT 24
Finished Jul 01 12:33:03 PM PDT 24
Peak memory 218588 kb
Host smart-529d9bd4-e2ca-42af-baa8-f101120893e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991191855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.3991191855
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.2683830108
Short name T44
Test name
Test status
Simulation time 338539720 ps
CPU time 11.14 seconds
Started Jul 01 12:32:47 PM PDT 24
Finished Jul 01 12:32:58 PM PDT 24
Peak memory 218680 kb
Host smart-2e9ed58f-9632-4041-bab6-ba07c57d62fd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683830108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
2683830108
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.3905789241
Short name T868
Test name
Test status
Simulation time 2642256844 ps
CPU time 20.81 seconds
Started Jul 01 12:32:48 PM PDT 24
Finished Jul 01 12:33:09 PM PDT 24
Peak memory 218700 kb
Host smart-eb692e5b-e455-4098-b34f-2453a75d48d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905789241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.3905789241
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.2901046328
Short name T523
Test name
Test status
Simulation time 90304303 ps
CPU time 5.59 seconds
Started Jul 01 12:32:49 PM PDT 24
Finished Jul 01 12:32:55 PM PDT 24
Peak memory 218160 kb
Host smart-399b3948-8132-4c17-85d9-0b386533ff19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901046328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.2901046328
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.4203668478
Short name T554
Test name
Test status
Simulation time 1131997031 ps
CPU time 29.86 seconds
Started Jul 01 12:32:50 PM PDT 24
Finished Jul 01 12:33:21 PM PDT 24
Peak memory 247772 kb
Host smart-d2e29485-2f9c-43c7-bdd0-3faa6f4c2350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203668478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.4203668478
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.2447173382
Short name T468
Test name
Test status
Simulation time 94440755 ps
CPU time 6.96 seconds
Started Jul 01 12:32:48 PM PDT 24
Finished Jul 01 12:32:56 PM PDT 24
Peak memory 247600 kb
Host smart-c7528fe2-d9a4-4815-b180-9917f85b50cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447173382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.2447173382
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.1895878289
Short name T514
Test name
Test status
Simulation time 6663875931 ps
CPU time 111.98 seconds
Started Jul 01 12:32:50 PM PDT 24
Finished Jul 01 12:34:43 PM PDT 24
Peak memory 268540 kb
Host smart-27414c9e-0000-4ba2-b186-598a1bb3457c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895878289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.1895878289
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.1509545992
Short name T863
Test name
Test status
Simulation time 27679093 ps
CPU time 1.59 seconds
Started Jul 01 12:32:51 PM PDT 24
Finished Jul 01 12:32:53 PM PDT 24
Peak memory 218056 kb
Host smart-d7b6fa23-8b24-4dfa-b01a-7c97aeba478b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509545992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.1509545992
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.2672814257
Short name T260
Test name
Test status
Simulation time 38536973 ps
CPU time 0.99 seconds
Started Jul 01 12:33:02 PM PDT 24
Finished Jul 01 12:33:03 PM PDT 24
Peak memory 209396 kb
Host smart-d9b0f177-7661-4418-9460-41e3e6c95cee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672814257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.2672814257
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.1792282030
Short name T711
Test name
Test status
Simulation time 905131720 ps
CPU time 16.96 seconds
Started Jul 01 12:32:54 PM PDT 24
Finished Jul 01 12:33:11 PM PDT 24
Peak memory 218692 kb
Host smart-f8fdc9b6-6d72-466c-a491-82415e06ce24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792282030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.1792282030
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.268056251
Short name T801
Test name
Test status
Simulation time 1841127111 ps
CPU time 6.1 seconds
Started Jul 01 12:32:56 PM PDT 24
Finished Jul 01 12:33:03 PM PDT 24
Peak memory 217576 kb
Host smart-d1bee076-4b59-4488-923f-60e0a3cc941b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268056251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.268056251
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.1633433209
Short name T616
Test name
Test status
Simulation time 27075440 ps
CPU time 2.05 seconds
Started Jul 01 12:32:53 PM PDT 24
Finished Jul 01 12:32:56 PM PDT 24
Peak memory 222436 kb
Host smart-39de01c7-5f87-4fa7-8284-d9a8b7456aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633433209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.1633433209
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.3187182791
Short name T593
Test name
Test status
Simulation time 1156405023 ps
CPU time 10.45 seconds
Started Jul 01 12:32:54 PM PDT 24
Finished Jul 01 12:33:05 PM PDT 24
Peak memory 226424 kb
Host smart-bf31a94a-d360-4b00-84b6-ca92919dd157
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187182791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.3187182791
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.538452442
Short name T698
Test name
Test status
Simulation time 303119713 ps
CPU time 12.29 seconds
Started Jul 01 12:32:59 PM PDT 24
Finished Jul 01 12:33:11 PM PDT 24
Peak memory 218532 kb
Host smart-7bbff039-2790-44db-babf-f159a8592723
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538452442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_di
gest.538452442
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.3875453898
Short name T269
Test name
Test status
Simulation time 681254906 ps
CPU time 8.08 seconds
Started Jul 01 12:33:02 PM PDT 24
Finished Jul 01 12:33:11 PM PDT 24
Peak memory 218600 kb
Host smart-78fc3980-9f17-4734-80fc-a8066e4cc107
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875453898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
3875453898
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.3874371739
Short name T670
Test name
Test status
Simulation time 234897587 ps
CPU time 7.22 seconds
Started Jul 01 12:32:55 PM PDT 24
Finished Jul 01 12:33:03 PM PDT 24
Peak memory 225056 kb
Host smart-61548073-c11b-43dd-8345-414b20523681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874371739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.3874371739
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.1296682237
Short name T192
Test name
Test status
Simulation time 94656103 ps
CPU time 3.3 seconds
Started Jul 01 12:32:53 PM PDT 24
Finished Jul 01 12:32:57 PM PDT 24
Peak memory 218056 kb
Host smart-99f5a005-cfb5-40fb-8361-6e464eba1705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296682237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.1296682237
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.711770224
Short name T561
Test name
Test status
Simulation time 381852811 ps
CPU time 24.34 seconds
Started Jul 01 12:32:52 PM PDT 24
Finished Jul 01 12:33:17 PM PDT 24
Peak memory 251352 kb
Host smart-6505b95f-03ca-40d3-80a1-00921a16ea2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711770224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.711770224
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.568046008
Short name T14
Test name
Test status
Simulation time 53353472 ps
CPU time 6.66 seconds
Started Jul 01 12:32:53 PM PDT 24
Finished Jul 01 12:33:00 PM PDT 24
Peak memory 247776 kb
Host smart-1fe63b1b-64bc-479d-836e-be7803598aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568046008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.568046008
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.3846319630
Short name T361
Test name
Test status
Simulation time 103749686209 ps
CPU time 131.97 seconds
Started Jul 01 12:32:59 PM PDT 24
Finished Jul 01 12:35:11 PM PDT 24
Peak memory 276052 kb
Host smart-c7aca2d9-368e-49a6-8306-3a4475c71cac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846319630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.3846319630
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.3855169387
Short name T559
Test name
Test status
Simulation time 45831926 ps
CPU time 0.79 seconds
Started Jul 01 12:32:54 PM PDT 24
Finished Jul 01 12:32:55 PM PDT 24
Peak memory 209140 kb
Host smart-bb08cc48-7c43-4fd4-914e-5e8e41d4bd48
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855169387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.3855169387
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.226905679
Short name T834
Test name
Test status
Simulation time 93087738 ps
CPU time 1 seconds
Started Jul 01 12:33:07 PM PDT 24
Finished Jul 01 12:33:08 PM PDT 24
Peak memory 209388 kb
Host smart-58e2a136-1815-4a42-a009-92f41d47cfbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226905679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.226905679
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.2120590161
Short name T485
Test name
Test status
Simulation time 3327927796 ps
CPU time 11.95 seconds
Started Jul 01 12:33:05 PM PDT 24
Finished Jul 01 12:33:18 PM PDT 24
Peak memory 219536 kb
Host smart-27027b51-7382-4ee1-8c4c-15f3e6f2827e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120590161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.2120590161
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.2405525248
Short name T595
Test name
Test status
Simulation time 1469447138 ps
CPU time 4.75 seconds
Started Jul 01 12:33:04 PM PDT 24
Finished Jul 01 12:33:10 PM PDT 24
Peak memory 217408 kb
Host smart-ab7699c5-6ffd-46aa-bd82-e9be57962ab2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405525248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.2405525248
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.1192576982
Short name T563
Test name
Test status
Simulation time 1959592181 ps
CPU time 4.92 seconds
Started Jul 01 12:33:04 PM PDT 24
Finished Jul 01 12:33:10 PM PDT 24
Peak memory 218608 kb
Host smart-449925eb-470a-431b-81df-cdb3a4d606ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192576982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.1192576982
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.2635742416
Short name T441
Test name
Test status
Simulation time 819531415 ps
CPU time 12.18 seconds
Started Jul 01 12:33:02 PM PDT 24
Finished Jul 01 12:33:15 PM PDT 24
Peak memory 226340 kb
Host smart-5dcb5d32-0648-47fc-b5c1-abaf9e9403f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635742416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.2635742416
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.2486758431
Short name T582
Test name
Test status
Simulation time 4418141191 ps
CPU time 12.33 seconds
Started Jul 01 12:33:07 PM PDT 24
Finished Jul 01 12:33:20 PM PDT 24
Peak memory 219412 kb
Host smart-8e821886-1833-49da-9f13-b9798e2c5e60
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486758431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.2486758431
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.3637099827
Short name T583
Test name
Test status
Simulation time 255760680 ps
CPU time 8.61 seconds
Started Jul 01 12:33:03 PM PDT 24
Finished Jul 01 12:33:13 PM PDT 24
Peak memory 226396 kb
Host smart-e38329e9-211f-41d6-86dd-e50a7f1ab8ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637099827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
3637099827
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.138008166
Short name T300
Test name
Test status
Simulation time 429525457 ps
CPU time 10.9 seconds
Started Jul 01 12:33:03 PM PDT 24
Finished Jul 01 12:33:15 PM PDT 24
Peak memory 218776 kb
Host smart-5684066c-c355-41f5-8ae0-726d7833bf1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138008166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.138008166
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.1483172481
Short name T84
Test name
Test status
Simulation time 359178041 ps
CPU time 8.42 seconds
Started Jul 01 12:33:00 PM PDT 24
Finished Jul 01 12:33:09 PM PDT 24
Peak memory 217916 kb
Host smart-4fae043b-a3c4-4090-8d5a-a95c134e66f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483172481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.1483172481
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.2256776469
Short name T835
Test name
Test status
Simulation time 872667199 ps
CPU time 18.47 seconds
Started Jul 01 12:33:00 PM PDT 24
Finished Jul 01 12:33:19 PM PDT 24
Peak memory 251324 kb
Host smart-4253e08b-0d22-47a1-8fe2-fafe599dfded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256776469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.2256776469
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.4143214813
Short name T816
Test name
Test status
Simulation time 156916328 ps
CPU time 4.9 seconds
Started Jul 01 12:33:05 PM PDT 24
Finished Jul 01 12:33:11 PM PDT 24
Peak memory 222748 kb
Host smart-e227ee27-0eaf-4499-9d21-b6bae8312bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143214813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.4143214813
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.337036826
Short name T735
Test name
Test status
Simulation time 10525844955 ps
CPU time 246.14 seconds
Started Jul 01 12:33:08 PM PDT 24
Finished Jul 01 12:37:15 PM PDT 24
Peak memory 284104 kb
Host smart-7cd2e434-77cf-4483-b64e-cd7bf50ce4a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337036826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.337036826
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.3826388803
Short name T436
Test name
Test status
Simulation time 12950431 ps
CPU time 0.79 seconds
Started Jul 01 12:32:58 PM PDT 24
Finished Jul 01 12:32:59 PM PDT 24
Peak memory 209188 kb
Host smart-f8e22721-5fd6-43ba-b06d-c5c68eb780c8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826388803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.3826388803
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.1887318496
Short name T763
Test name
Test status
Simulation time 12142932 ps
CPU time 1.01 seconds
Started Jul 01 12:33:14 PM PDT 24
Finished Jul 01 12:33:16 PM PDT 24
Peak memory 209356 kb
Host smart-4ddec1ac-f2d6-4534-b9b6-bab9fe0b0e9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887318496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.1887318496
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.1509275643
Short name T419
Test name
Test status
Simulation time 452274200 ps
CPU time 6.21 seconds
Started Jul 01 12:33:12 PM PDT 24
Finished Jul 01 12:33:19 PM PDT 24
Peak memory 217728 kb
Host smart-5f3ef477-065a-4e14-8cef-1422d54157e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509275643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.1509275643
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.3685149281
Short name T791
Test name
Test status
Simulation time 54837068 ps
CPU time 3.21 seconds
Started Jul 01 12:33:09 PM PDT 24
Finished Jul 01 12:33:13 PM PDT 24
Peak memory 218648 kb
Host smart-2c1a5a2e-113e-461e-bf03-1befdd27e31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685149281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.3685149281
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.3982163762
Short name T659
Test name
Test status
Simulation time 1582229855 ps
CPU time 9.6 seconds
Started Jul 01 12:33:13 PM PDT 24
Finished Jul 01 12:33:23 PM PDT 24
Peak memory 226400 kb
Host smart-dc2804cd-fa7d-45ea-8c05-0db476476fc8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982163762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.3982163762
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.366519270
Short name T454
Test name
Test status
Simulation time 283165655 ps
CPU time 11.29 seconds
Started Jul 01 12:33:15 PM PDT 24
Finished Jul 01 12:33:27 PM PDT 24
Peak memory 218592 kb
Host smart-62aa9659-b485-4658-b7b2-d83ce5bd8fbb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366519270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_di
gest.366519270
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.3227641633
Short name T432
Test name
Test status
Simulation time 572763866 ps
CPU time 13.23 seconds
Started Jul 01 12:33:18 PM PDT 24
Finished Jul 01 12:33:33 PM PDT 24
Peak memory 226336 kb
Host smart-aa463c8d-f458-494e-a54c-91eccbe65aab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227641633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
3227641633
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.2588010483
Short name T479
Test name
Test status
Simulation time 1118259661 ps
CPU time 16.58 seconds
Started Jul 01 12:33:08 PM PDT 24
Finished Jul 01 12:33:25 PM PDT 24
Peak memory 218732 kb
Host smart-d7f8a4b5-1bac-4e33-8959-e72d4d94786d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588010483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.2588010483
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.88340430
Short name T375
Test name
Test status
Simulation time 136529006 ps
CPU time 2.37 seconds
Started Jul 01 12:33:03 PM PDT 24
Finished Jul 01 12:33:06 PM PDT 24
Peak memory 218056 kb
Host smart-e86f21bc-3e42-46d4-87cf-c1c24c79bb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88340430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.88340430
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.3442077486
Short name T780
Test name
Test status
Simulation time 3856543014 ps
CPU time 35.62 seconds
Started Jul 01 12:33:08 PM PDT 24
Finished Jul 01 12:33:44 PM PDT 24
Peak memory 251380 kb
Host smart-5d6ec5bd-78d2-4811-94c1-6796794e1824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442077486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.3442077486
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.4286868137
Short name T442
Test name
Test status
Simulation time 122315435 ps
CPU time 6.27 seconds
Started Jul 01 12:33:09 PM PDT 24
Finished Jul 01 12:33:15 PM PDT 24
Peak memory 247376 kb
Host smart-da5e33ea-6879-43fb-9a53-f0748c3303cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286868137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.4286868137
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.642568975
Short name T439
Test name
Test status
Simulation time 32759629380 ps
CPU time 327.17 seconds
Started Jul 01 12:33:13 PM PDT 24
Finished Jul 01 12:38:41 PM PDT 24
Peak memory 277092 kb
Host smart-5166445d-605c-4c0f-a8b2-7d7b0b67115d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642568975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.642568975
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1575826742
Short name T48
Test name
Test status
Simulation time 19788739 ps
CPU time 0.81 seconds
Started Jul 01 12:33:10 PM PDT 24
Finished Jul 01 12:33:11 PM PDT 24
Peak memory 209036 kb
Host smart-3d9a3473-493a-407b-ab25-ce4bcbba27a7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575826742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.1575826742
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.2819284975
Short name T849
Test name
Test status
Simulation time 115374339 ps
CPU time 0.74 seconds
Started Jul 01 12:33:20 PM PDT 24
Finished Jul 01 12:33:21 PM PDT 24
Peak memory 209332 kb
Host smart-7d9d568c-186b-473b-bff8-79869f711b15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819284975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.2819284975
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.1166432198
Short name T264
Test name
Test status
Simulation time 240961383 ps
CPU time 8.07 seconds
Started Jul 01 12:33:13 PM PDT 24
Finished Jul 01 12:33:22 PM PDT 24
Peak memory 218624 kb
Host smart-37aa63f4-f2be-4bc5-97f4-d5752c4b45ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166432198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.1166432198
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.3896709368
Short name T598
Test name
Test status
Simulation time 66746459 ps
CPU time 1.26 seconds
Started Jul 01 12:33:12 PM PDT 24
Finished Jul 01 12:33:15 PM PDT 24
Peak memory 217424 kb
Host smart-4a6c93ed-8790-4b83-a9c8-336d4927f806
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896709368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.3896709368
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.2783424212
Short name T506
Test name
Test status
Simulation time 235080146 ps
CPU time 3.26 seconds
Started Jul 01 12:33:14 PM PDT 24
Finished Jul 01 12:33:18 PM PDT 24
Peak memory 218644 kb
Host smart-1277f510-8e31-43cc-a282-c2785f2596b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783424212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.2783424212
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.83436238
Short name T281
Test name
Test status
Simulation time 245475898 ps
CPU time 13.31 seconds
Started Jul 01 12:33:12 PM PDT 24
Finished Jul 01 12:33:26 PM PDT 24
Peak memory 226460 kb
Host smart-62dbe0c5-e5fe-4a3c-b72f-d677ec04cb43
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83436238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.83436238
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.1472484687
Short name T42
Test name
Test status
Simulation time 357234954 ps
CPU time 13.13 seconds
Started Jul 01 12:33:16 PM PDT 24
Finished Jul 01 12:33:31 PM PDT 24
Peak memory 218384 kb
Host smart-099fc142-3784-4298-91b1-cf6c5d36a009
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472484687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.1472484687
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.853203426
Short name T433
Test name
Test status
Simulation time 201524323 ps
CPU time 6.2 seconds
Started Jul 01 12:33:18 PM PDT 24
Finished Jul 01 12:33:25 PM PDT 24
Peak memory 218540 kb
Host smart-427c1fba-c3c8-4890-a12f-733d77dc6cd8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853203426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.853203426
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.2026209475
Short name T751
Test name
Test status
Simulation time 449001516 ps
CPU time 9.64 seconds
Started Jul 01 12:33:14 PM PDT 24
Finished Jul 01 12:33:25 PM PDT 24
Peak memory 218700 kb
Host smart-82148ba5-253a-4f30-abc6-0e5177e95bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026209475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.2026209475
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.1146772696
Short name T542
Test name
Test status
Simulation time 68059353 ps
CPU time 1.93 seconds
Started Jul 01 12:33:12 PM PDT 24
Finished Jul 01 12:33:15 PM PDT 24
Peak memory 214524 kb
Host smart-6a5d9ecc-e3b8-41ee-8762-cae5e0a8c703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146772696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.1146772696
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.3120714422
Short name T110
Test name
Test status
Simulation time 254333974 ps
CPU time 9.59 seconds
Started Jul 01 12:33:16 PM PDT 24
Finished Jul 01 12:33:27 PM PDT 24
Peak memory 251188 kb
Host smart-0536190c-10e2-4522-870e-df2c8aceebc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120714422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.3120714422
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.3567700662
Short name T21
Test name
Test status
Simulation time 22578127061 ps
CPU time 71.75 seconds
Started Jul 01 12:33:21 PM PDT 24
Finished Jul 01 12:34:34 PM PDT 24
Peak memory 248248 kb
Host smart-c7d42728-5dd6-40cd-abeb-bb94ce4dccf5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567700662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.3567700662
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.3401525708
Short name T681
Test name
Test status
Simulation time 16876287 ps
CPU time 1 seconds
Started Jul 01 12:33:14 PM PDT 24
Finished Jul 01 12:33:16 PM PDT 24
Peak memory 212252 kb
Host smart-ff8d29fb-cf60-4cde-b339-2be1c191bc83
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401525708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.3401525708
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.1936318446
Short name T477
Test name
Test status
Simulation time 42506860 ps
CPU time 0.86 seconds
Started Jul 01 12:33:25 PM PDT 24
Finished Jul 01 12:33:26 PM PDT 24
Peak memory 209180 kb
Host smart-66b07148-bda1-4974-b120-9b69f230ec7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936318446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.1936318446
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.183009182
Short name T234
Test name
Test status
Simulation time 711318610 ps
CPU time 14.91 seconds
Started Jul 01 12:33:17 PM PDT 24
Finished Jul 01 12:33:33 PM PDT 24
Peak memory 218636 kb
Host smart-570741ef-01f0-4f4c-b741-d3d02c3392b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183009182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.183009182
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.3606185628
Short name T734
Test name
Test status
Simulation time 3444194800 ps
CPU time 10.71 seconds
Started Jul 01 12:33:21 PM PDT 24
Finished Jul 01 12:33:33 PM PDT 24
Peak memory 218044 kb
Host smart-a38d67a2-f359-42ce-aef5-5d92857b4f59
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606185628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.3606185628
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.2004454457
Short name T242
Test name
Test status
Simulation time 42174675 ps
CPU time 2.5 seconds
Started Jul 01 12:33:19 PM PDT 24
Finished Jul 01 12:33:22 PM PDT 24
Peak memory 222552 kb
Host smart-79e505c6-7d61-4f2d-916c-f4597f6872b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004454457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.2004454457
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.3595226888
Short name T406
Test name
Test status
Simulation time 1007318420 ps
CPU time 10.51 seconds
Started Jul 01 12:33:20 PM PDT 24
Finished Jul 01 12:33:31 PM PDT 24
Peak memory 219260 kb
Host smart-66e0f3e8-57ba-434b-bed5-9f91fa2afad1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595226888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.3595226888
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.2237667304
Short name T285
Test name
Test status
Simulation time 307260810 ps
CPU time 9.06 seconds
Started Jul 01 12:33:26 PM PDT 24
Finished Jul 01 12:33:36 PM PDT 24
Peak memory 218584 kb
Host smart-c78cafda-bca1-4251-8aed-2327315e80aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237667304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.2237667304
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.1043163334
Short name T831
Test name
Test status
Simulation time 1352632336 ps
CPU time 8.26 seconds
Started Jul 01 12:33:18 PM PDT 24
Finished Jul 01 12:33:27 PM PDT 24
Peak memory 218516 kb
Host smart-5de673e1-b6ee-4eb0-b8ce-121b9246f002
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043163334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
1043163334
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.3074177229
Short name T229
Test name
Test status
Simulation time 2212562614 ps
CPU time 6.57 seconds
Started Jul 01 12:33:18 PM PDT 24
Finished Jul 01 12:33:25 PM PDT 24
Peak memory 218820 kb
Host smart-4bf75ab9-c13d-48a3-af25-7169cb5b90fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074177229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.3074177229
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.90288926
Short name T597
Test name
Test status
Simulation time 83724322 ps
CPU time 1.8 seconds
Started Jul 01 12:33:18 PM PDT 24
Finished Jul 01 12:33:21 PM PDT 24
Peak memory 223376 kb
Host smart-90fa71a7-e80a-469d-bd6d-195ef851fccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90288926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.90288926
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.1388338895
Short name T331
Test name
Test status
Simulation time 285518244 ps
CPU time 27.6 seconds
Started Jul 01 12:33:17 PM PDT 24
Finished Jul 01 12:33:45 PM PDT 24
Peak memory 251272 kb
Host smart-25d21e04-2975-415d-b5bb-a94ff19e857b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388338895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.1388338895
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.2224934208
Short name T758
Test name
Test status
Simulation time 82307767 ps
CPU time 8.78 seconds
Started Jul 01 12:33:21 PM PDT 24
Finished Jul 01 12:33:30 PM PDT 24
Peak memory 251304 kb
Host smart-55e8ebab-2e59-4f7e-85df-936a5ae70567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224934208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.2224934208
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.1605359219
Short name T562
Test name
Test status
Simulation time 2747835712 ps
CPU time 94.92 seconds
Started Jul 01 12:33:24 PM PDT 24
Finished Jul 01 12:35:00 PM PDT 24
Peak memory 267012 kb
Host smart-cec772fd-cade-439f-9c93-4a3da0d195f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605359219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.1605359219
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.1972500059
Short name T678
Test name
Test status
Simulation time 32436694 ps
CPU time 0.86 seconds
Started Jul 01 12:33:18 PM PDT 24
Finished Jul 01 12:33:20 PM PDT 24
Peak memory 209456 kb
Host smart-55d59e42-5c09-4d46-845c-7cba5c06de07
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972500059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.1972500059
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.1254347593
Short name T546
Test name
Test status
Simulation time 21492039 ps
CPU time 1.26 seconds
Started Jul 01 12:33:32 PM PDT 24
Finished Jul 01 12:33:34 PM PDT 24
Peak memory 209352 kb
Host smart-94287a84-b347-4d71-8fff-0d076a36642f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254347593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.1254347593
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.3512091565
Short name T319
Test name
Test status
Simulation time 364895198 ps
CPU time 16.79 seconds
Started Jul 01 12:33:23 PM PDT 24
Finished Jul 01 12:33:40 PM PDT 24
Peak memory 218628 kb
Host smart-ffac559d-8b7b-416b-95a9-1ab81495c2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512091565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.3512091565
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.1269557892
Short name T428
Test name
Test status
Simulation time 50447153 ps
CPU time 1.96 seconds
Started Jul 01 12:33:23 PM PDT 24
Finished Jul 01 12:33:26 PM PDT 24
Peak memory 217404 kb
Host smart-7b6358fb-6e3e-4a51-bedc-d9df43107d6e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269557892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.1269557892
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.3302105573
Short name T275
Test name
Test status
Simulation time 44707553 ps
CPU time 1.44 seconds
Started Jul 01 12:33:24 PM PDT 24
Finished Jul 01 12:33:26 PM PDT 24
Peak memory 222160 kb
Host smart-681c20d7-7dab-4f9c-84a8-ea3a27e6fad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302105573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.3302105573
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.441019042
Short name T188
Test name
Test status
Simulation time 2650949527 ps
CPU time 17.53 seconds
Started Jul 01 12:33:31 PM PDT 24
Finished Jul 01 12:33:49 PM PDT 24
Peak memory 219708 kb
Host smart-4583e3fa-8736-4f68-bbb5-5d02a45af292
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441019042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.441019042
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.2476398391
Short name T460
Test name
Test status
Simulation time 279311019 ps
CPU time 13.24 seconds
Started Jul 01 12:33:30 PM PDT 24
Finished Jul 01 12:33:44 PM PDT 24
Peak memory 218520 kb
Host smart-1456e4ba-a3b8-426a-8c56-139078382140
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476398391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.2476398391
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.2418128910
Short name T1
Test name
Test status
Simulation time 249465725 ps
CPU time 9.2 seconds
Started Jul 01 12:33:30 PM PDT 24
Finished Jul 01 12:33:40 PM PDT 24
Peak memory 218592 kb
Host smart-12dde092-69a7-4bde-ba72-01e3766f77fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418128910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
2418128910
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.826202490
Short name T620
Test name
Test status
Simulation time 2585372129 ps
CPU time 11.36 seconds
Started Jul 01 12:33:23 PM PDT 24
Finished Jul 01 12:33:35 PM PDT 24
Peak memory 226480 kb
Host smart-7c71cddf-0c64-4e09-8ac2-1361b10a2f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826202490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.826202490
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.3923861055
Short name T115
Test name
Test status
Simulation time 61294606 ps
CPU time 2.68 seconds
Started Jul 01 12:33:25 PM PDT 24
Finished Jul 01 12:33:29 PM PDT 24
Peak memory 214604 kb
Host smart-45b7d552-a689-4498-8475-f0244f3c36d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923861055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.3923861055
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.1125248286
Short name T16
Test name
Test status
Simulation time 215915912 ps
CPU time 19.2 seconds
Started Jul 01 12:33:27 PM PDT 24
Finished Jul 01 12:33:46 PM PDT 24
Peak memory 251260 kb
Host smart-c9e03911-4f4a-4696-879b-c8c8fc544cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125248286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.1125248286
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.1107780020
Short name T822
Test name
Test status
Simulation time 166690352 ps
CPU time 3.84 seconds
Started Jul 01 12:33:27 PM PDT 24
Finished Jul 01 12:33:32 PM PDT 24
Peak memory 226888 kb
Host smart-1161c50b-12ab-4121-bba8-95f597235f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107780020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.1107780020
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.2874565323
Short name T117
Test name
Test status
Simulation time 42125999793 ps
CPU time 109.67 seconds
Started Jul 01 12:33:31 PM PDT 24
Finished Jul 01 12:35:22 PM PDT 24
Peak memory 267704 kb
Host smart-41184af8-d89e-4c55-ba23-e95eed766f29
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874565323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.2874565323
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.3727809296
Short name T647
Test name
Test status
Simulation time 14835336 ps
CPU time 0.95 seconds
Started Jul 01 12:33:26 PM PDT 24
Finished Jul 01 12:33:27 PM PDT 24
Peak memory 212276 kb
Host smart-c7b16efc-f6b8-4d2d-b7bb-6b62eb4227a9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727809296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.3727809296
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.4252116546
Short name T182
Test name
Test status
Simulation time 17813257 ps
CPU time 1.09 seconds
Started Jul 01 12:29:29 PM PDT 24
Finished Jul 01 12:29:31 PM PDT 24
Peak memory 209384 kb
Host smart-060f38f3-c582-46c0-b586-b01865fdc581
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252116546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.4252116546
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.666979822
Short name T517
Test name
Test status
Simulation time 2740290368 ps
CPU time 16.53 seconds
Started Jul 01 12:29:15 PM PDT 24
Finished Jul 01 12:29:32 PM PDT 24
Peak memory 219360 kb
Host smart-481c178d-929e-4eaa-b879-4e7460f0ca03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666979822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.666979822
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.3503665562
Short name T844
Test name
Test status
Simulation time 53652956 ps
CPU time 1.47 seconds
Started Jul 01 12:29:23 PM PDT 24
Finished Jul 01 12:29:26 PM PDT 24
Peak memory 217424 kb
Host smart-a1feb95d-3160-455c-890a-f34880b89b3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503665562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.3503665562
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.1268863783
Short name T651
Test name
Test status
Simulation time 1694379459 ps
CPU time 23.17 seconds
Started Jul 01 12:29:20 PM PDT 24
Finished Jul 01 12:29:43 PM PDT 24
Peak memory 218556 kb
Host smart-d3d893a5-6a14-4b1d-92ae-fb9969e3e1cf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268863783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.1268863783
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.2453163828
Short name T53
Test name
Test status
Simulation time 730427637 ps
CPU time 8.22 seconds
Started Jul 01 12:29:24 PM PDT 24
Finished Jul 01 12:29:33 PM PDT 24
Peak memory 218044 kb
Host smart-62647ffa-d54e-41ee-8d6e-90c3bb7417ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453163828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.2
453163828
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.1405408028
Short name T786
Test name
Test status
Simulation time 2275380517 ps
CPU time 30.32 seconds
Started Jul 01 12:29:17 PM PDT 24
Finished Jul 01 12:29:48 PM PDT 24
Peak memory 220244 kb
Host smart-be667120-123d-4cb5-baf7-2170f3263e57
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405408028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.1405408028
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.2282647995
Short name T33
Test name
Test status
Simulation time 776922350 ps
CPU time 23.04 seconds
Started Jul 01 12:29:24 PM PDT 24
Finished Jul 01 12:29:48 PM PDT 24
Peak memory 217976 kb
Host smart-9c127ecd-9a12-465a-877b-c1ef1a512373
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282647995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.2282647995
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.1693662138
Short name T114
Test name
Test status
Simulation time 43450836 ps
CPU time 1.93 seconds
Started Jul 01 12:29:15 PM PDT 24
Finished Jul 01 12:29:18 PM PDT 24
Peak memory 217992 kb
Host smart-9ae7097c-70c3-444a-8d58-33ca58e14bca
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693662138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
1693662138
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.507956220
Short name T422
Test name
Test status
Simulation time 5884202876 ps
CPU time 34.17 seconds
Started Jul 01 12:29:21 PM PDT 24
Finished Jul 01 12:29:56 PM PDT 24
Peak memory 251252 kb
Host smart-f4ef4a1d-ec48-4b85-bca2-564b21f28d9a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507956220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_state_failure.507956220
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.1333022418
Short name T256
Test name
Test status
Simulation time 1586432248 ps
CPU time 8.45 seconds
Started Jul 01 12:29:21 PM PDT 24
Finished Jul 01 12:29:29 PM PDT 24
Peak memory 223580 kb
Host smart-98cddff5-7278-43bc-b9dc-3766176faf66
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333022418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.1333022418
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.1959553151
Short name T106
Test name
Test status
Simulation time 50828622 ps
CPU time 2.87 seconds
Started Jul 01 12:29:14 PM PDT 24
Finished Jul 01 12:29:18 PM PDT 24
Peak memory 218524 kb
Host smart-5cfdfa84-4742-431f-90b4-6566dd3893d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959553151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.1959553151
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.2693056620
Short name T70
Test name
Test status
Simulation time 844811858 ps
CPU time 9.36 seconds
Started Jul 01 12:29:14 PM PDT 24
Finished Jul 01 12:29:24 PM PDT 24
Peak memory 214740 kb
Host smart-63b39994-bbf6-444c-b181-1de515f85a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693056620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.2693056620
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.2613705792
Short name T782
Test name
Test status
Simulation time 298760285 ps
CPU time 9.98 seconds
Started Jul 01 12:29:26 PM PDT 24
Finished Jul 01 12:29:36 PM PDT 24
Peak memory 226544 kb
Host smart-7a6d9eb6-53c5-4d17-9e1c-3240510c280c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613705792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.2613705792
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.2551361861
Short name T266
Test name
Test status
Simulation time 1102233769 ps
CPU time 11.56 seconds
Started Jul 01 12:29:26 PM PDT 24
Finished Jul 01 12:29:38 PM PDT 24
Peak memory 218600 kb
Host smart-549b8cf4-9574-4fe6-af9b-e59eb6d24ced
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551361861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.2551361861
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.4155865473
Short name T752
Test name
Test status
Simulation time 1260552522 ps
CPU time 8.66 seconds
Started Jul 01 12:29:25 PM PDT 24
Finished Jul 01 12:29:34 PM PDT 24
Peak memory 226388 kb
Host smart-a1408232-eb8c-44b7-977b-56e620ef5561
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155865473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.4
155865473
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.1020601686
Short name T680
Test name
Test status
Simulation time 380455159 ps
CPU time 10.94 seconds
Started Jul 01 12:29:16 PM PDT 24
Finished Jul 01 12:29:28 PM PDT 24
Peak memory 226460 kb
Host smart-a9ec8f44-ebdd-4cc5-b7df-0072d0f1c610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020601686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.1020601686
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.1769346528
Short name T328
Test name
Test status
Simulation time 111612794 ps
CPU time 2.41 seconds
Started Jul 01 12:29:09 PM PDT 24
Finished Jul 01 12:29:12 PM PDT 24
Peak memory 214792 kb
Host smart-363a55e4-ebd2-42cf-baba-afb381fcce27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769346528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.1769346528
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.2374467645
Short name T729
Test name
Test status
Simulation time 328687880 ps
CPU time 23.81 seconds
Started Jul 01 12:29:09 PM PDT 24
Finished Jul 01 12:29:34 PM PDT 24
Peak memory 251308 kb
Host smart-eb1e7216-022b-4879-9d1d-39480eb12ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374467645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.2374467645
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.1054926432
Short name T843
Test name
Test status
Simulation time 399511517 ps
CPU time 2.92 seconds
Started Jul 01 12:29:13 PM PDT 24
Finished Jul 01 12:29:17 PM PDT 24
Peak memory 226596 kb
Host smart-a97782d9-930c-4fa9-bf9e-66a585d9da0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054926432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.1054926432
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.953008443
Short name T501
Test name
Test status
Simulation time 12723071102 ps
CPU time 118.2 seconds
Started Jul 01 12:29:24 PM PDT 24
Finished Jul 01 12:31:23 PM PDT 24
Peak memory 251440 kb
Host smart-6e545665-ba21-4407-b76f-deafd87fb91c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953008443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.953008443
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1334726535
Short name T560
Test name
Test status
Simulation time 38643111 ps
CPU time 0.75 seconds
Started Jul 01 12:29:09 PM PDT 24
Finished Jul 01 12:29:11 PM PDT 24
Peak memory 208996 kb
Host smart-0700d434-914e-44de-bbd6-991b09d9e983
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334726535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.1334726535
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.3234683380
Short name T860
Test name
Test status
Simulation time 14877178 ps
CPU time 0.93 seconds
Started Jul 01 12:33:33 PM PDT 24
Finished Jul 01 12:33:35 PM PDT 24
Peak memory 209364 kb
Host smart-f3568c83-f8b9-4fd7-add0-ce2f57db6bf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234683380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.3234683380
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.2586110425
Short name T253
Test name
Test status
Simulation time 1008776877 ps
CPU time 9.27 seconds
Started Jul 01 12:33:29 PM PDT 24
Finished Jul 01 12:33:39 PM PDT 24
Peak memory 218640 kb
Host smart-aa2dc951-55de-4ac3-b9fb-3bb62d1f3ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586110425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.2586110425
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.669031008
Short name T787
Test name
Test status
Simulation time 1151143377 ps
CPU time 6.72 seconds
Started Jul 01 12:33:31 PM PDT 24
Finished Jul 01 12:33:38 PM PDT 24
Peak memory 217736 kb
Host smart-53af4ca0-d004-4b97-86ef-c2a7ce0bced9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669031008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.669031008
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.975830953
Short name T194
Test name
Test status
Simulation time 2257064447 ps
CPU time 6.83 seconds
Started Jul 01 12:33:30 PM PDT 24
Finished Jul 01 12:33:38 PM PDT 24
Peak memory 218676 kb
Host smart-7a3630f2-a57d-4372-bdbf-d827b93db87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975830953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.975830953
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.3137176201
Short name T652
Test name
Test status
Simulation time 201189766 ps
CPU time 8.46 seconds
Started Jul 01 12:33:31 PM PDT 24
Finished Jul 01 12:33:40 PM PDT 24
Peak memory 218648 kb
Host smart-a8413d08-87c7-4e9a-a440-1f9be1f36813
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137176201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.3137176201
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.447100232
Short name T783
Test name
Test status
Simulation time 3097301414 ps
CPU time 20.7 seconds
Started Jul 01 12:33:32 PM PDT 24
Finished Jul 01 12:33:53 PM PDT 24
Peak memory 219200 kb
Host smart-93aaa88a-4067-4a0c-be95-54a1b08acab2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447100232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_di
gest.447100232
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.218032577
Short name T555
Test name
Test status
Simulation time 2807397486 ps
CPU time 12.49 seconds
Started Jul 01 12:33:31 PM PDT 24
Finished Jul 01 12:33:44 PM PDT 24
Peak memory 226348 kb
Host smart-c9b209c4-4d43-4290-ad58-8969aadef858
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218032577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.218032577
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.2971644075
Short name T228
Test name
Test status
Simulation time 281955318 ps
CPU time 12.35 seconds
Started Jul 01 12:33:28 PM PDT 24
Finished Jul 01 12:33:41 PM PDT 24
Peak memory 225704 kb
Host smart-18f74375-0f7e-484b-a469-b42e97b90c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971644075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.2971644075
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.2121098242
Short name T64
Test name
Test status
Simulation time 498385147 ps
CPU time 2.95 seconds
Started Jul 01 12:33:32 PM PDT 24
Finished Jul 01 12:33:36 PM PDT 24
Peak memory 218028 kb
Host smart-0c204e07-d85f-440b-a2a7-99f143b96b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121098242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.2121098242
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.1073591255
Short name T600
Test name
Test status
Simulation time 3587013151 ps
CPU time 32.27 seconds
Started Jul 01 12:33:29 PM PDT 24
Finished Jul 01 12:34:02 PM PDT 24
Peak memory 248700 kb
Host smart-17b23e72-98a7-473c-abb0-8a438e6c97ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073591255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.1073591255
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.1147828602
Short name T623
Test name
Test status
Simulation time 450352669 ps
CPU time 6.51 seconds
Started Jul 01 12:33:34 PM PDT 24
Finished Jul 01 12:33:41 PM PDT 24
Peak memory 251296 kb
Host smart-dcf1eccb-5a7b-48da-9a28-f7a2b932a261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147828602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.1147828602
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.300940831
Short name T472
Test name
Test status
Simulation time 17112616978 ps
CPU time 132.5 seconds
Started Jul 01 12:33:29 PM PDT 24
Finished Jul 01 12:35:42 PM PDT 24
Peak memory 287940 kb
Host smart-70618f33-0a71-4946-ae0f-b9e61dc0f0d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300940831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.300940831
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.606075447
Short name T94
Test name
Test status
Simulation time 23193275815 ps
CPU time 417.87 seconds
Started Jul 01 12:33:30 PM PDT 24
Finished Jul 01 12:40:28 PM PDT 24
Peak memory 317020 kb
Host smart-a12e841a-8e38-4b80-9dea-d76bd57d8c81
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=606075447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.606075447
Directory /workspace/30.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.3445491315
Short name T332
Test name
Test status
Simulation time 13380396 ps
CPU time 0.97 seconds
Started Jul 01 12:33:33 PM PDT 24
Finished Jul 01 12:33:34 PM PDT 24
Peak memory 212252 kb
Host smart-693553f9-30ab-4902-a78a-47c5ef45d64a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445491315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.3445491315
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.2827544906
Short name T663
Test name
Test status
Simulation time 23324151 ps
CPU time 1.06 seconds
Started Jul 01 12:33:40 PM PDT 24
Finished Jul 01 12:33:42 PM PDT 24
Peak memory 209392 kb
Host smart-93bc2905-0409-403f-9bd3-858113cd85d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827544906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.2827544906
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.842489306
Short name T252
Test name
Test status
Simulation time 1854123059 ps
CPU time 14.5 seconds
Started Jul 01 12:33:32 PM PDT 24
Finished Jul 01 12:33:48 PM PDT 24
Peak memory 218624 kb
Host smart-c59d8478-ca6a-449e-aea3-58f2b8e3dbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842489306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.842489306
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.4207300509
Short name T467
Test name
Test status
Simulation time 1360986099 ps
CPU time 4.48 seconds
Started Jul 01 12:33:34 PM PDT 24
Finished Jul 01 12:33:39 PM PDT 24
Peak memory 217408 kb
Host smart-8c6941c7-988b-4b11-8253-d489f2ab341e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207300509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.4207300509
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.3968585013
Short name T668
Test name
Test status
Simulation time 28900347 ps
CPU time 1.78 seconds
Started Jul 01 12:33:33 PM PDT 24
Finished Jul 01 12:33:35 PM PDT 24
Peak memory 222436 kb
Host smart-994430ad-bfe3-44e9-9539-318d43de0f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968585013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.3968585013
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.3059846447
Short name T604
Test name
Test status
Simulation time 430561325 ps
CPU time 19.77 seconds
Started Jul 01 12:33:34 PM PDT 24
Finished Jul 01 12:33:54 PM PDT 24
Peak memory 226464 kb
Host smart-37084707-8bfc-4818-8019-90b1f2b3d25d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059846447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.3059846447
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.1541205104
Short name T190
Test name
Test status
Simulation time 825719890 ps
CPU time 15.97 seconds
Started Jul 01 12:33:35 PM PDT 24
Finished Jul 01 12:33:52 PM PDT 24
Peak memory 218636 kb
Host smart-23e55c44-aa70-480e-992c-cc00250a6871
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541205104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.1541205104
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.2111140136
Short name T451
Test name
Test status
Simulation time 3162378122 ps
CPU time 15.22 seconds
Started Jul 01 12:33:32 PM PDT 24
Finished Jul 01 12:33:48 PM PDT 24
Peak memory 226220 kb
Host smart-f9a15b20-abdd-4c5b-a49e-0fd357e5310f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111140136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
2111140136
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.1617843640
Short name T685
Test name
Test status
Simulation time 43507572 ps
CPU time 2.99 seconds
Started Jul 01 12:33:27 PM PDT 24
Finished Jul 01 12:33:31 PM PDT 24
Peak memory 218164 kb
Host smart-92fce504-960f-4db2-832d-05edd3fcd2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617843640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.1617843640
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.2213702203
Short name T383
Test name
Test status
Simulation time 325484426 ps
CPU time 35.16 seconds
Started Jul 01 12:33:32 PM PDT 24
Finished Jul 01 12:34:08 PM PDT 24
Peak memory 251320 kb
Host smart-38cbdadd-db87-4e4d-a1e7-89f00179f89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213702203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.2213702203
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.1826997006
Short name T171
Test name
Test status
Simulation time 295930500 ps
CPU time 8.74 seconds
Started Jul 01 12:33:36 PM PDT 24
Finished Jul 01 12:33:45 PM PDT 24
Peak memory 251340 kb
Host smart-f632157b-cef9-4a42-91df-7b79f11b4978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826997006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.1826997006
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.1300322726
Short name T391
Test name
Test status
Simulation time 13376358594 ps
CPU time 271.85 seconds
Started Jul 01 12:33:38 PM PDT 24
Finished Jul 01 12:38:11 PM PDT 24
Peak memory 284168 kb
Host smart-933c9984-22dd-4a69-8c9b-54164fc08c13
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300322726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.1300322726
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.1453335780
Short name T845
Test name
Test status
Simulation time 24860649727 ps
CPU time 472.97 seconds
Started Jul 01 12:33:42 PM PDT 24
Finished Jul 01 12:41:36 PM PDT 24
Peak memory 284340 kb
Host smart-1fa2e488-40fb-4b6c-9b20-e5ed21ab536c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1453335780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all_with_rand_reset.1453335780
Directory /workspace/31.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.1076511629
Short name T358
Test name
Test status
Simulation time 14085216 ps
CPU time 0.84 seconds
Started Jul 01 12:33:34 PM PDT 24
Finished Jul 01 12:33:36 PM PDT 24
Peak memory 209232 kb
Host smart-519551f2-301e-4124-890a-bdaf60d6fe65
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076511629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.1076511629
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.1957286446
Short name T306
Test name
Test status
Simulation time 22458441 ps
CPU time 0.95 seconds
Started Jul 01 12:33:44 PM PDT 24
Finished Jul 01 12:33:46 PM PDT 24
Peak memory 209392 kb
Host smart-9d6c0895-6d10-4638-b3e2-a75cd02e9f53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957286446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.1957286446
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.2811136776
Short name T525
Test name
Test status
Simulation time 1257449526 ps
CPU time 24.19 seconds
Started Jul 01 12:33:39 PM PDT 24
Finished Jul 01 12:34:04 PM PDT 24
Peak memory 218656 kb
Host smart-d28d68e3-9b07-460f-95f8-f3804a08a961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811136776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.2811136776
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.3317161218
Short name T378
Test name
Test status
Simulation time 42847061 ps
CPU time 2.36 seconds
Started Jul 01 12:33:39 PM PDT 24
Finished Jul 01 12:33:42 PM PDT 24
Peak memory 222672 kb
Host smart-f0bc6917-49b0-46c0-bcba-2775227dab5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317161218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.3317161218
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.3188756387
Short name T675
Test name
Test status
Simulation time 524681855 ps
CPU time 15.04 seconds
Started Jul 01 12:33:39 PM PDT 24
Finished Jul 01 12:33:55 PM PDT 24
Peak memory 219148 kb
Host smart-d16b0465-545c-4d08-8b16-fd1e9f1ea13d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188756387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.3188756387
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.2330582949
Short name T345
Test name
Test status
Simulation time 825316219 ps
CPU time 22.01 seconds
Started Jul 01 12:33:38 PM PDT 24
Finished Jul 01 12:34:01 PM PDT 24
Peak memory 218540 kb
Host smart-7228c421-b43d-4ae4-918f-4fae973ee919
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330582949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.2330582949
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.1239707384
Short name T243
Test name
Test status
Simulation time 1391424428 ps
CPU time 9.77 seconds
Started Jul 01 12:33:40 PM PDT 24
Finished Jul 01 12:33:51 PM PDT 24
Peak memory 218536 kb
Host smart-43e6cc3e-11b9-4040-a2c0-27859d8158b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239707384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
1239707384
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.3894979834
Short name T60
Test name
Test status
Simulation time 273560343 ps
CPU time 7.27 seconds
Started Jul 01 12:33:39 PM PDT 24
Finished Jul 01 12:33:47 PM PDT 24
Peak memory 218688 kb
Host smart-718379c4-5630-4961-9e76-9cb617e17542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894979834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.3894979834
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.2491910623
Short name T259
Test name
Test status
Simulation time 40286656 ps
CPU time 1.78 seconds
Started Jul 01 12:33:40 PM PDT 24
Finished Jul 01 12:33:43 PM PDT 24
Peak memory 218080 kb
Host smart-a55751a2-9f44-460a-b49c-6fab17e66b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491910623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.2491910623
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.409790817
Short name T658
Test name
Test status
Simulation time 1011374840 ps
CPU time 30.88 seconds
Started Jul 01 12:33:39 PM PDT 24
Finished Jul 01 12:34:11 PM PDT 24
Peak memory 251316 kb
Host smart-33c56858-baa1-4cc4-aca9-c80da660e334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409790817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.409790817
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.257906710
Short name T322
Test name
Test status
Simulation time 207287987 ps
CPU time 8.34 seconds
Started Jul 01 12:33:40 PM PDT 24
Finished Jul 01 12:33:49 PM PDT 24
Peak memory 251340 kb
Host smart-37c9f321-03e5-4e5f-8930-ba27a2587528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257906710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.257906710
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.1964419589
Short name T366
Test name
Test status
Simulation time 17852275639 ps
CPU time 186.27 seconds
Started Jul 01 12:33:46 PM PDT 24
Finished Jul 01 12:36:53 PM PDT 24
Peak memory 273472 kb
Host smart-4c8bb679-876c-4dbb-92b2-bfc7a38c4365
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964419589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.1964419589
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.1286783312
Short name T492
Test name
Test status
Simulation time 17435236 ps
CPU time 0.78 seconds
Started Jul 01 12:33:43 PM PDT 24
Finished Jul 01 12:33:45 PM PDT 24
Peak memory 209212 kb
Host smart-e176746c-b82e-45c7-a68b-ecf68c0ea56b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286783312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.1286783312
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.803545648
Short name T656
Test name
Test status
Simulation time 17004517 ps
CPU time 1.1 seconds
Started Jul 01 12:33:48 PM PDT 24
Finished Jul 01 12:33:50 PM PDT 24
Peak memory 209384 kb
Host smart-8e99f168-12a7-418e-9e0e-cf69af2078fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803545648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.803545648
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.531070259
Short name T474
Test name
Test status
Simulation time 8879810932 ps
CPU time 18.17 seconds
Started Jul 01 12:33:46 PM PDT 24
Finished Jul 01 12:34:05 PM PDT 24
Peak memory 226516 kb
Host smart-a21ce715-2492-41d4-b3c9-2a520b1ef563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531070259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.531070259
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.3803773352
Short name T29
Test name
Test status
Simulation time 2920743235 ps
CPU time 8.06 seconds
Started Jul 01 12:33:47 PM PDT 24
Finished Jul 01 12:33:56 PM PDT 24
Peak memory 218120 kb
Host smart-66c813a6-b333-4ff7-8021-3719e605872a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803773352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.3803773352
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.1580922482
Short name T530
Test name
Test status
Simulation time 57225711 ps
CPU time 2.72 seconds
Started Jul 01 12:33:43 PM PDT 24
Finished Jul 01 12:33:47 PM PDT 24
Peak memory 218584 kb
Host smart-4c4357e7-c0d9-4c6c-9960-30a791536b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580922482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.1580922482
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.1811635079
Short name T302
Test name
Test status
Simulation time 621757757 ps
CPU time 9.63 seconds
Started Jul 01 12:33:42 PM PDT 24
Finished Jul 01 12:33:52 PM PDT 24
Peak memory 226444 kb
Host smart-a29bc5b7-3a45-4a06-9523-a2b8464e74b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811635079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.1811635079
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.652555396
Short name T531
Test name
Test status
Simulation time 3382506515 ps
CPU time 17.95 seconds
Started Jul 01 12:33:52 PM PDT 24
Finished Jul 01 12:34:11 PM PDT 24
Peak memory 219296 kb
Host smart-db0b2fcd-2206-482e-bba4-bc4761d7a9a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652555396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_di
gest.652555396
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.2533417091
Short name T538
Test name
Test status
Simulation time 229928567 ps
CPU time 9.68 seconds
Started Jul 01 12:33:48 PM PDT 24
Finished Jul 01 12:33:59 PM PDT 24
Peak memory 218536 kb
Host smart-5fa68e99-2652-43fc-ab72-3bd77c1f3c78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533417091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
2533417091
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.278415585
Short name T465
Test name
Test status
Simulation time 289275819 ps
CPU time 11.97 seconds
Started Jul 01 12:33:45 PM PDT 24
Finished Jul 01 12:33:58 PM PDT 24
Peak memory 225944 kb
Host smart-bc0b8cef-1911-4356-8dbb-cb0c92c8e681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278415585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.278415585
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.2796547143
Short name T388
Test name
Test status
Simulation time 36549290 ps
CPU time 2.3 seconds
Started Jul 01 12:33:46 PM PDT 24
Finished Jul 01 12:33:49 PM PDT 24
Peak memory 217996 kb
Host smart-2b9f3463-6f98-443e-9963-f2869567998a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796547143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.2796547143
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.1993479675
Short name T699
Test name
Test status
Simulation time 302088603 ps
CPU time 28.42 seconds
Started Jul 01 12:33:44 PM PDT 24
Finished Jul 01 12:34:13 PM PDT 24
Peak memory 251324 kb
Host smart-9e790e94-f8de-40f4-b401-a5f7db80f337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993479675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.1993479675
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.2717660846
Short name T646
Test name
Test status
Simulation time 73776469 ps
CPU time 6.34 seconds
Started Jul 01 12:33:44 PM PDT 24
Finished Jul 01 12:33:52 PM PDT 24
Peak memory 250824 kb
Host smart-68628c0c-d3ef-4724-b1a5-d2abe4c2135d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717660846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.2717660846
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.3120472412
Short name T674
Test name
Test status
Simulation time 21907715037 ps
CPU time 337.24 seconds
Started Jul 01 12:33:48 PM PDT 24
Finished Jul 01 12:39:26 PM PDT 24
Peak memory 284080 kb
Host smart-8dcf0360-f9dc-4d14-8999-33ec5ebf744f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120472412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.3120472412
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.391696669
Short name T51
Test name
Test status
Simulation time 100359640382 ps
CPU time 472.93 seconds
Started Jul 01 12:33:50 PM PDT 24
Finished Jul 01 12:41:44 PM PDT 24
Peak memory 418968 kb
Host smart-c1623a76-e5ae-476c-b0fa-152e17a3ac33
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=391696669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.391696669
Directory /workspace/33.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.1185610844
Short name T536
Test name
Test status
Simulation time 58089089 ps
CPU time 0.75 seconds
Started Jul 01 12:33:42 PM PDT 24
Finished Jul 01 12:33:44 PM PDT 24
Peak memory 209184 kb
Host smart-4b1d7fe7-ccfc-4a2e-8294-b70d9905c263
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185610844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.1185610844
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.1567453833
Short name T749
Test name
Test status
Simulation time 18483042 ps
CPU time 0.82 seconds
Started Jul 01 12:33:56 PM PDT 24
Finished Jul 01 12:33:58 PM PDT 24
Peak memory 209380 kb
Host smart-6d274fd8-75ec-474e-9fba-007e5f61d168
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567453833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.1567453833
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.2488767078
Short name T400
Test name
Test status
Simulation time 1157273123 ps
CPU time 9.99 seconds
Started Jul 01 12:33:48 PM PDT 24
Finished Jul 01 12:33:59 PM PDT 24
Peak memory 218692 kb
Host smart-72d58f14-c485-4b95-bdb6-9055fbf77017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488767078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.2488767078
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.411020995
Short name T613
Test name
Test status
Simulation time 372232417 ps
CPU time 5.6 seconds
Started Jul 01 12:33:52 PM PDT 24
Finished Jul 01 12:33:58 PM PDT 24
Peak memory 217636 kb
Host smart-996ca868-18fc-4ebd-b073-ec330aed93c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411020995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.411020995
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.1708952646
Short name T362
Test name
Test status
Simulation time 43079277 ps
CPU time 1.64 seconds
Started Jul 01 12:33:47 PM PDT 24
Finished Jul 01 12:33:50 PM PDT 24
Peak memory 222444 kb
Host smart-a8a18474-7af5-4c75-a63a-fcec15a17eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708952646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.1708952646
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.4091339777
Short name T507
Test name
Test status
Simulation time 442300516 ps
CPU time 14.92 seconds
Started Jul 01 12:33:53 PM PDT 24
Finished Jul 01 12:34:08 PM PDT 24
Peak memory 226460 kb
Host smart-c8f0333f-a2ed-4c6b-ad5a-2a3293925237
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091339777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.4091339777
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.3720011307
Short name T373
Test name
Test status
Simulation time 308256092 ps
CPU time 11.45 seconds
Started Jul 01 12:33:54 PM PDT 24
Finished Jul 01 12:34:06 PM PDT 24
Peak memory 218668 kb
Host smart-6506fd8b-8d74-4727-b80f-8ff93bf1b315
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720011307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.3720011307
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.525589945
Short name T838
Test name
Test status
Simulation time 1115641595 ps
CPU time 12.49 seconds
Started Jul 01 12:33:52 PM PDT 24
Finished Jul 01 12:34:06 PM PDT 24
Peak memory 218604 kb
Host smart-dd4eac46-456b-4ecc-b354-865976bc8f39
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525589945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.525589945
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.2206138856
Short name T105
Test name
Test status
Simulation time 2564317129 ps
CPU time 8.69 seconds
Started Jul 01 12:33:54 PM PDT 24
Finished Jul 01 12:34:04 PM PDT 24
Peak memory 218828 kb
Host smart-0325b95f-d19a-4573-a35c-86120bc3edcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206138856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.2206138856
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.1914704464
Short name T774
Test name
Test status
Simulation time 75394824 ps
CPU time 2.49 seconds
Started Jul 01 12:33:50 PM PDT 24
Finished Jul 01 12:33:53 PM PDT 24
Peak memory 214644 kb
Host smart-2d59505e-dcae-467b-94f7-8912d465be8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914704464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.1914704464
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.3748891510
Short name T268
Test name
Test status
Simulation time 354683683 ps
CPU time 30.84 seconds
Started Jul 01 12:33:50 PM PDT 24
Finished Jul 01 12:34:21 PM PDT 24
Peak memory 251320 kb
Host smart-fa7651be-7301-41f6-8b92-dccc9fd616ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748891510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.3748891510
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.3015809741
Short name T179
Test name
Test status
Simulation time 84741881 ps
CPU time 2.62 seconds
Started Jul 01 12:33:47 PM PDT 24
Finished Jul 01 12:33:51 PM PDT 24
Peak memory 222720 kb
Host smart-f989e55f-af08-4f60-af9c-640d66c09aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015809741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.3015809741
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.3012787739
Short name T65
Test name
Test status
Simulation time 49889715235 ps
CPU time 278.15 seconds
Started Jul 01 12:33:54 PM PDT 24
Finished Jul 01 12:38:33 PM PDT 24
Peak memory 284008 kb
Host smart-0f936ddb-9122-4f85-a14a-3cebbe0a1135
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012787739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.3012787739
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.172129103
Short name T667
Test name
Test status
Simulation time 27242566 ps
CPU time 1.09 seconds
Started Jul 01 12:33:50 PM PDT 24
Finished Jul 01 12:33:52 PM PDT 24
Peak memory 212256 kb
Host smart-106cc444-10d2-4535-aaa0-dbe5c6c0cecd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172129103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ct
rl_volatile_unlock_smoke.172129103
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.805429265
Short name T848
Test name
Test status
Simulation time 13882513 ps
CPU time 0.87 seconds
Started Jul 01 12:33:58 PM PDT 24
Finished Jul 01 12:34:00 PM PDT 24
Peak memory 209360 kb
Host smart-7518e522-0f69-4126-93fd-1d56a0f5ba30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805429265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.805429265
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.2224329553
Short name T49
Test name
Test status
Simulation time 401463276 ps
CPU time 13.44 seconds
Started Jul 01 12:33:54 PM PDT 24
Finished Jul 01 12:34:09 PM PDT 24
Peak memory 218560 kb
Host smart-8bac7533-edfe-4489-a39c-19a5ad05069b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224329553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.2224329553
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.2336888686
Short name T482
Test name
Test status
Simulation time 537943668 ps
CPU time 11.75 seconds
Started Jul 01 12:34:02 PM PDT 24
Finished Jul 01 12:34:15 PM PDT 24
Peak memory 217812 kb
Host smart-51c38cc7-9098-4bb3-92b8-941e8c726751
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336888686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.2336888686
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.3470539816
Short name T573
Test name
Test status
Simulation time 81180675 ps
CPU time 3.71 seconds
Started Jul 01 12:33:53 PM PDT 24
Finished Jul 01 12:33:58 PM PDT 24
Peak memory 218604 kb
Host smart-65378b1a-5b7e-4bb1-b2cf-337508bf41b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470539816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.3470539816
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.1006767624
Short name T745
Test name
Test status
Simulation time 1322580490 ps
CPU time 14.71 seconds
Started Jul 01 12:34:00 PM PDT 24
Finished Jul 01 12:34:15 PM PDT 24
Peak memory 219328 kb
Host smart-c5393dce-6c22-427c-a6d5-85432db7b54b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006767624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.1006767624
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.371625142
Short name T829
Test name
Test status
Simulation time 526877782 ps
CPU time 11.58 seconds
Started Jul 01 12:34:01 PM PDT 24
Finished Jul 01 12:34:14 PM PDT 24
Peak memory 218656 kb
Host smart-600292fa-7920-448f-9521-4a9ebe57f25a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371625142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_di
gest.371625142
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.306884517
Short name T777
Test name
Test status
Simulation time 177673142 ps
CPU time 6.03 seconds
Started Jul 01 12:33:58 PM PDT 24
Finished Jul 01 12:34:06 PM PDT 24
Peak memory 218580 kb
Host smart-57451661-7228-4dff-b753-4902e9f2345b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306884517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.306884517
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.191799350
Short name T54
Test name
Test status
Simulation time 366383653 ps
CPU time 13.05 seconds
Started Jul 01 12:34:01 PM PDT 24
Finished Jul 01 12:34:15 PM PDT 24
Peak memory 226448 kb
Host smart-04c97ddf-4226-4543-bdf9-12ad9ccb5977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191799350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.191799350
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.1249140346
Short name T170
Test name
Test status
Simulation time 182811588 ps
CPU time 2.2 seconds
Started Jul 01 12:33:57 PM PDT 24
Finished Jul 01 12:34:01 PM PDT 24
Peak memory 214720 kb
Host smart-c55a11b4-4f98-4dff-9aab-761c78064ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249140346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.1249140346
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.375863760
Short name T682
Test name
Test status
Simulation time 649769484 ps
CPU time 26.36 seconds
Started Jul 01 12:34:00 PM PDT 24
Finished Jul 01 12:34:27 PM PDT 24
Peak memory 251040 kb
Host smart-8ed0507e-eeaf-4b22-b16a-a9b1ef7c268d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375863760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.375863760
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.2353273428
Short name T841
Test name
Test status
Simulation time 50390762 ps
CPU time 3.2 seconds
Started Jul 01 12:33:53 PM PDT 24
Finished Jul 01 12:33:58 PM PDT 24
Peak memory 222832 kb
Host smart-f7a9776c-3034-4964-951b-abd044329004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353273428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.2353273428
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.1529634396
Short name T496
Test name
Test status
Simulation time 92083946210 ps
CPU time 264.81 seconds
Started Jul 01 12:34:00 PM PDT 24
Finished Jul 01 12:38:25 PM PDT 24
Peak memory 496876 kb
Host smart-eb007caa-a93b-468e-9cb2-b3b6bd9b8338
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529634396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.1529634396
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.1835093069
Short name T739
Test name
Test status
Simulation time 44336668459 ps
CPU time 226.25 seconds
Started Jul 01 12:34:03 PM PDT 24
Finished Jul 01 12:37:50 PM PDT 24
Peak memory 278652 kb
Host smart-37e761a6-aa54-4db7-af60-2dafc62512c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1835093069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.1835093069
Directory /workspace/35.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.1729218636
Short name T67
Test name
Test status
Simulation time 13538219 ps
CPU time 1 seconds
Started Jul 01 12:33:59 PM PDT 24
Finished Jul 01 12:34:02 PM PDT 24
Peak memory 212380 kb
Host smart-f4eb2ba1-a78d-4028-a6a6-d1b6145b9893
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729218636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.1729218636
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.3570896371
Short name T866
Test name
Test status
Simulation time 39016693 ps
CPU time 1.29 seconds
Started Jul 01 12:34:05 PM PDT 24
Finished Jul 01 12:34:08 PM PDT 24
Peak memory 209408 kb
Host smart-974ce05f-fe8b-44b0-b48d-d80c0a8a2391
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570896371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.3570896371
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.32481588
Short name T337
Test name
Test status
Simulation time 2032649032 ps
CPU time 14.68 seconds
Started Jul 01 12:34:01 PM PDT 24
Finished Jul 01 12:34:17 PM PDT 24
Peak memory 218620 kb
Host smart-cd485274-2aed-4a82-978d-588f6ea17f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32481588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.32481588
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.3416645118
Short name T369
Test name
Test status
Simulation time 145232012 ps
CPU time 2.4 seconds
Started Jul 01 12:34:06 PM PDT 24
Finished Jul 01 12:34:09 PM PDT 24
Peak memory 217300 kb
Host smart-e9a91a7d-e4ee-4bd2-b84e-fe4b899be4b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416645118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.3416645118
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.2140765653
Short name T830
Test name
Test status
Simulation time 218915102 ps
CPU time 3.27 seconds
Started Jul 01 12:33:59 PM PDT 24
Finished Jul 01 12:34:04 PM PDT 24
Peak memory 218612 kb
Host smart-5255a502-c3ed-446d-9263-50eb8e821c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140765653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.2140765653
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.2334691201
Short name T585
Test name
Test status
Simulation time 393535903 ps
CPU time 13.74 seconds
Started Jul 01 12:34:06 PM PDT 24
Finished Jul 01 12:34:21 PM PDT 24
Peak memory 226452 kb
Host smart-210262f4-1994-44f0-84ee-8d5e0d11a5c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334691201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.2334691201
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.3738060394
Short name T765
Test name
Test status
Simulation time 234891335 ps
CPU time 7.65 seconds
Started Jul 01 12:34:05 PM PDT 24
Finished Jul 01 12:34:13 PM PDT 24
Peak memory 218668 kb
Host smart-3bbf756a-440e-417e-a82d-2e44076e4633
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738060394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.3738060394
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.3483170369
Short name T741
Test name
Test status
Simulation time 175096405 ps
CPU time 2.67 seconds
Started Jul 01 12:34:02 PM PDT 24
Finished Jul 01 12:34:05 PM PDT 24
Peak memory 218052 kb
Host smart-183cb9ee-ae08-4307-9720-b640de500711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483170369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.3483170369
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.2410114314
Short name T423
Test name
Test status
Simulation time 1082694290 ps
CPU time 21.08 seconds
Started Jul 01 12:34:00 PM PDT 24
Finished Jul 01 12:34:22 PM PDT 24
Peak memory 251068 kb
Host smart-95ffd1a2-6774-4f13-91c3-8918bec74cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410114314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.2410114314
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.2303933901
Short name T713
Test name
Test status
Simulation time 68199803 ps
CPU time 7.64 seconds
Started Jul 01 12:34:01 PM PDT 24
Finished Jul 01 12:34:10 PM PDT 24
Peak memory 251332 kb
Host smart-f7e8505e-d7fa-44a9-9d79-6d0eb761ed97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303933901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.2303933901
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.1206068893
Short name T377
Test name
Test status
Simulation time 472448091 ps
CPU time 20.34 seconds
Started Jul 01 12:34:05 PM PDT 24
Finished Jul 01 12:34:26 PM PDT 24
Peak memory 219868 kb
Host smart-8be1b41c-a408-48f2-937c-3aec3b4d6bca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206068893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.1206068893
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.1345097287
Short name T308
Test name
Test status
Simulation time 42487942 ps
CPU time 1.09 seconds
Started Jul 01 12:34:01 PM PDT 24
Finished Jul 01 12:34:03 PM PDT 24
Peak memory 212224 kb
Host smart-30c3967b-ea26-4713-bf91-4c385be8fe98
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345097287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.1345097287
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.3636886266
Short name T648
Test name
Test status
Simulation time 67263713 ps
CPU time 1.02 seconds
Started Jul 01 12:34:11 PM PDT 24
Finished Jul 01 12:34:12 PM PDT 24
Peak memory 209428 kb
Host smart-b084491f-2d7b-4ee8-a330-ad622d14a776
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636886266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.3636886266
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.3176984327
Short name T590
Test name
Test status
Simulation time 615511479 ps
CPU time 14.7 seconds
Started Jul 01 12:34:05 PM PDT 24
Finished Jul 01 12:34:21 PM PDT 24
Peak memory 218620 kb
Host smart-ab40c313-2301-48bb-8e63-86c1af8b7a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176984327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.3176984327
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.333534208
Short name T27
Test name
Test status
Simulation time 6015470096 ps
CPU time 20.09 seconds
Started Jul 01 12:34:08 PM PDT 24
Finished Jul 01 12:34:29 PM PDT 24
Peak memory 217924 kb
Host smart-e07e830d-fc1d-41d2-a2a8-81e2dc667c45
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333534208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.333534208
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.3377866126
Short name T543
Test name
Test status
Simulation time 104678908 ps
CPU time 4.56 seconds
Started Jul 01 12:34:04 PM PDT 24
Finished Jul 01 12:34:09 PM PDT 24
Peak memory 218544 kb
Host smart-b6ef965c-a99e-467d-b9a9-86d8e1f19ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377866126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.3377866126
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.1330069286
Short name T732
Test name
Test status
Simulation time 377186722 ps
CPU time 13.64 seconds
Started Jul 01 12:34:10 PM PDT 24
Finished Jul 01 12:34:24 PM PDT 24
Peak memory 218656 kb
Host smart-4a7c7224-0b6e-4703-9327-6f8560383f67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330069286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.1330069286
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.468537612
Short name T512
Test name
Test status
Simulation time 414827457 ps
CPU time 10.02 seconds
Started Jul 01 12:34:11 PM PDT 24
Finished Jul 01 12:34:22 PM PDT 24
Peak memory 218540 kb
Host smart-871be9ba-4412-444f-ac90-325c444eeffc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468537612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_di
gest.468537612
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.2209582665
Short name T239
Test name
Test status
Simulation time 3229777730 ps
CPU time 9.36 seconds
Started Jul 01 12:34:09 PM PDT 24
Finished Jul 01 12:34:19 PM PDT 24
Peak memory 218608 kb
Host smart-1af45ea9-af03-43d5-a2ce-712f02e14be7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209582665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
2209582665
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.902901414
Short name T295
Test name
Test status
Simulation time 302794247 ps
CPU time 12.89 seconds
Started Jul 01 12:34:09 PM PDT 24
Finished Jul 01 12:34:22 PM PDT 24
Peak memory 226532 kb
Host smart-aa2e210a-58bd-45bc-9d30-6d01218b5fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902901414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.902901414
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.2496430170
Short name T736
Test name
Test status
Simulation time 64259015 ps
CPU time 1.3 seconds
Started Jul 01 12:34:04 PM PDT 24
Finished Jul 01 12:34:06 PM PDT 24
Peak memory 214116 kb
Host smart-b6f06eb6-bd9e-4f2c-a21d-d97db15ca77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496430170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.2496430170
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.3541746110
Short name T513
Test name
Test status
Simulation time 3310346142 ps
CPU time 28.5 seconds
Started Jul 01 12:34:03 PM PDT 24
Finished Jul 01 12:34:32 PM PDT 24
Peak memory 246772 kb
Host smart-3838c24f-347d-46e1-a657-faf7bdf04631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541746110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.3541746110
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.3125715372
Short name T635
Test name
Test status
Simulation time 81388871 ps
CPU time 7.79 seconds
Started Jul 01 12:34:03 PM PDT 24
Finished Jul 01 12:34:12 PM PDT 24
Peak memory 247432 kb
Host smart-64c6eceb-42a9-4da4-bb27-884abd5e7fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125715372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.3125715372
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.1602769234
Short name T657
Test name
Test status
Simulation time 33663645 ps
CPU time 0.78 seconds
Started Jul 01 12:34:05 PM PDT 24
Finished Jul 01 12:34:07 PM PDT 24
Peak memory 209252 kb
Host smart-93967401-60ae-424f-a286-e01aaaa990a4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602769234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.1602769234
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.222838531
Short name T74
Test name
Test status
Simulation time 17799163 ps
CPU time 1.17 seconds
Started Jul 01 12:34:14 PM PDT 24
Finished Jul 01 12:34:16 PM PDT 24
Peak memory 209372 kb
Host smart-d0ed9524-c459-4dcb-94ff-650f1d8b45c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222838531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.222838531
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.3598202081
Short name T244
Test name
Test status
Simulation time 2552289535 ps
CPU time 21.82 seconds
Started Jul 01 12:34:20 PM PDT 24
Finished Jul 01 12:34:43 PM PDT 24
Peak memory 226500 kb
Host smart-63f59ad5-af3e-458b-8128-4302621f0b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598202081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.3598202081
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.3260413616
Short name T7
Test name
Test status
Simulation time 664595469 ps
CPU time 15.98 seconds
Started Jul 01 12:34:16 PM PDT 24
Finished Jul 01 12:34:34 PM PDT 24
Peak memory 217796 kb
Host smart-f1001ca9-6dd5-4249-b09f-653ec4bff1fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260413616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.3260413616
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.2421537977
Short name T37
Test name
Test status
Simulation time 94784316 ps
CPU time 2.38 seconds
Started Jul 01 12:34:14 PM PDT 24
Finished Jul 01 12:34:18 PM PDT 24
Peak memory 222768 kb
Host smart-636fa936-8e41-46e6-b458-824baed94864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421537977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.2421537977
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.4286530373
Short name T537
Test name
Test status
Simulation time 867001114 ps
CPU time 14.77 seconds
Started Jul 01 12:34:13 PM PDT 24
Finished Jul 01 12:34:29 PM PDT 24
Peak memory 226408 kb
Host smart-d4fb6030-d886-405f-82cd-8b8f8f929739
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286530373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.4286530373
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.1624178914
Short name T111
Test name
Test status
Simulation time 1820338148 ps
CPU time 16.88 seconds
Started Jul 01 12:34:20 PM PDT 24
Finished Jul 01 12:34:38 PM PDT 24
Peak memory 218600 kb
Host smart-71f2ad55-1c99-4821-9d0a-49d8b9b69906
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624178914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.1624178914
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.2610394317
Short name T596
Test name
Test status
Simulation time 1898664330 ps
CPU time 9.1 seconds
Started Jul 01 12:34:21 PM PDT 24
Finished Jul 01 12:34:31 PM PDT 24
Peak memory 226380 kb
Host smart-a9d45f65-e13a-4e2c-9607-1fad422e6d53
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610394317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
2610394317
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.1483188374
Short name T522
Test name
Test status
Simulation time 1660940664 ps
CPU time 11.98 seconds
Started Jul 01 12:34:16 PM PDT 24
Finished Jul 01 12:34:30 PM PDT 24
Peak memory 218652 kb
Host smart-a3fd3a65-8d1b-43ad-8510-59b70f8bd08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483188374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.1483188374
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.1786312858
Short name T81
Test name
Test status
Simulation time 59343047 ps
CPU time 3.71 seconds
Started Jul 01 12:34:13 PM PDT 24
Finished Jul 01 12:34:18 PM PDT 24
Peak memory 218200 kb
Host smart-1ae4ffd8-dbd6-4ead-af09-610116f55be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786312858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.1786312858
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.3357339282
Short name T747
Test name
Test status
Simulation time 335879215 ps
CPU time 33.95 seconds
Started Jul 01 12:34:08 PM PDT 24
Finished Jul 01 12:34:43 PM PDT 24
Peak memory 249356 kb
Host smart-7a1f049d-9f84-411d-9447-9978a14d64fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357339282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.3357339282
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.41793261
Short name T230
Test name
Test status
Simulation time 61396189 ps
CPU time 9.16 seconds
Started Jul 01 12:34:13 PM PDT 24
Finished Jul 01 12:34:23 PM PDT 24
Peak memory 251340 kb
Host smart-903dcb33-c05e-4b0c-a453-202f32cb467d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41793261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.41793261
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.901479436
Short name T450
Test name
Test status
Simulation time 136977171188 ps
CPU time 208.71 seconds
Started Jul 01 12:34:17 PM PDT 24
Finished Jul 01 12:37:46 PM PDT 24
Peak memory 268972 kb
Host smart-8e94291c-e80c-4c60-ab18-b0dfc880b107
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901479436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.901479436
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.630787623
Short name T222
Test name
Test status
Simulation time 36093866652 ps
CPU time 525.33 seconds
Started Jul 01 12:34:25 PM PDT 24
Finished Jul 01 12:43:12 PM PDT 24
Peak memory 278488 kb
Host smart-f648e87d-6623-44a9-89e2-b443aff81b97
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=630787623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.630787623
Directory /workspace/38.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.4143325710
Short name T294
Test name
Test status
Simulation time 22522731 ps
CPU time 0.81 seconds
Started Jul 01 12:34:14 PM PDT 24
Finished Jul 01 12:34:15 PM PDT 24
Peak memory 209568 kb
Host smart-ddc73933-62f8-4196-b253-52266a4cbf69
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143325710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.4143325710
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.3486760012
Short name T784
Test name
Test status
Simulation time 12755550 ps
CPU time 0.84 seconds
Started Jul 01 12:34:18 PM PDT 24
Finished Jul 01 12:34:20 PM PDT 24
Peak memory 209188 kb
Host smart-0ff84894-4f11-4c14-b3aa-8bb3631f36bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486760012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.3486760012
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.974362352
Short name T414
Test name
Test status
Simulation time 258631836 ps
CPU time 11.33 seconds
Started Jul 01 12:34:21 PM PDT 24
Finished Jul 01 12:34:33 PM PDT 24
Peak memory 218628 kb
Host smart-f74ce63a-61dc-40d3-87bc-7250b02e607a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974362352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.974362352
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.4163841211
Short name T515
Test name
Test status
Simulation time 329053476 ps
CPU time 1.82 seconds
Started Jul 01 12:34:21 PM PDT 24
Finished Jul 01 12:34:24 PM PDT 24
Peak memory 217428 kb
Host smart-3a23befa-7ab8-4034-82b4-7e59cdc6153e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163841211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.4163841211
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.3884044056
Short name T296
Test name
Test status
Simulation time 253627243 ps
CPU time 2.51 seconds
Started Jul 01 12:34:21 PM PDT 24
Finished Jul 01 12:34:25 PM PDT 24
Peak memory 222592 kb
Host smart-20d8b950-ddc5-4dda-b446-8020098d7958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884044056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.3884044056
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.2111293248
Short name T564
Test name
Test status
Simulation time 839942621 ps
CPU time 14.27 seconds
Started Jul 01 12:34:17 PM PDT 24
Finished Jul 01 12:34:32 PM PDT 24
Peak memory 226420 kb
Host smart-b6b74773-f67d-4f34-8dba-ba8f7b8dba1a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111293248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.2111293248
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.2997491034
Short name T870
Test name
Test status
Simulation time 2174408666 ps
CPU time 15.79 seconds
Started Jul 01 12:34:21 PM PDT 24
Finished Jul 01 12:34:38 PM PDT 24
Peak memory 218668 kb
Host smart-baaa2359-c298-405b-8244-47d8e5717ba7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997491034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.2997491034
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.1045723178
Short name T702
Test name
Test status
Simulation time 232863795 ps
CPU time 9.3 seconds
Started Jul 01 12:34:20 PM PDT 24
Finished Jul 01 12:34:31 PM PDT 24
Peak memory 218584 kb
Host smart-6b9defd5-d53b-488c-9768-7197853a73e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045723178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
1045723178
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.1438915590
Short name T649
Test name
Test status
Simulation time 318794278 ps
CPU time 8.44 seconds
Started Jul 01 12:34:18 PM PDT 24
Finished Jul 01 12:34:27 PM PDT 24
Peak memory 218688 kb
Host smart-d7ed2a89-d5b7-4c8a-b5df-748eb1960078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438915590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.1438915590
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.3749823403
Short name T701
Test name
Test status
Simulation time 33436069 ps
CPU time 2.65 seconds
Started Jul 01 12:34:14 PM PDT 24
Finished Jul 01 12:34:18 PM PDT 24
Peak memory 214908 kb
Host smart-ba504422-293d-4017-8dfa-8ba333da7280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749823403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.3749823403
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.1020059463
Short name T317
Test name
Test status
Simulation time 613330953 ps
CPU time 28.4 seconds
Started Jul 01 12:34:19 PM PDT 24
Finished Jul 01 12:34:48 PM PDT 24
Peak memory 251316 kb
Host smart-cbbead83-7ff1-4e6e-9918-fdf6258a1416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020059463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.1020059463
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.2183805666
Short name T102
Test name
Test status
Simulation time 69565303 ps
CPU time 3.71 seconds
Started Jul 01 12:34:28 PM PDT 24
Finished Jul 01 12:34:32 PM PDT 24
Peak memory 222660 kb
Host smart-188a9895-6226-4abf-9502-5fcf45ec71d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183805666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.2183805666
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.2688509821
Short name T565
Test name
Test status
Simulation time 9257689697 ps
CPU time 184.08 seconds
Started Jul 01 12:34:21 PM PDT 24
Finished Jul 01 12:37:26 PM PDT 24
Peak memory 274788 kb
Host smart-c7baa672-6c5d-4394-b321-3b15589f400e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688509821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.2688509821
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.3383663148
Short name T125
Test name
Test status
Simulation time 21461011171 ps
CPU time 501.23 seconds
Started Jul 01 12:34:20 PM PDT 24
Finished Jul 01 12:42:42 PM PDT 24
Peak memory 421516 kb
Host smart-69db1933-69e5-40a0-93d6-ddbfcd437391
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3383663148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.3383663148
Directory /workspace/39.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.2763161505
Short name T181
Test name
Test status
Simulation time 27481807 ps
CPU time 0.82 seconds
Started Jul 01 12:34:19 PM PDT 24
Finished Jul 01 12:34:20 PM PDT 24
Peak memory 209232 kb
Host smart-d78cc2ad-8679-4a63-9f0a-f7024dd24c86
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763161505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.2763161505
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.2363361156
Short name T610
Test name
Test status
Simulation time 30586407 ps
CPU time 1.1 seconds
Started Jul 01 12:29:45 PM PDT 24
Finished Jul 01 12:29:47 PM PDT 24
Peak memory 209272 kb
Host smart-6aa6958f-ec61-4b56-bcbb-62dfeef5616d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363361156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.2363361156
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.3014943260
Short name T72
Test name
Test status
Simulation time 12251791 ps
CPU time 0.97 seconds
Started Jul 01 12:29:34 PM PDT 24
Finished Jul 01 12:29:35 PM PDT 24
Peak memory 209232 kb
Host smart-6160ca8d-7782-414e-9613-c41a29a23e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014943260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.3014943260
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.3034766813
Short name T660
Test name
Test status
Simulation time 685765457 ps
CPU time 24.28 seconds
Started Jul 01 12:29:29 PM PDT 24
Finished Jul 01 12:29:54 PM PDT 24
Peak memory 226408 kb
Host smart-0df18fbe-86a5-48c3-9549-e2918a57f5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034766813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.3034766813
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.3640796479
Short name T788
Test name
Test status
Simulation time 676019595 ps
CPU time 6.88 seconds
Started Jul 01 12:29:40 PM PDT 24
Finished Jul 01 12:29:48 PM PDT 24
Peak memory 217680 kb
Host smart-720838f2-5685-4ab6-92d3-95db1e7bcb7c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640796479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.3640796479
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.1054089869
Short name T566
Test name
Test status
Simulation time 3723209640 ps
CPU time 48.34 seconds
Started Jul 01 12:29:39 PM PDT 24
Finished Jul 01 12:30:28 PM PDT 24
Peak memory 219288 kb
Host smart-4ed7bf8e-9093-4ada-b0fd-ea84368760ae
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054089869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.1054089869
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.2476836087
Short name T823
Test name
Test status
Simulation time 274704953 ps
CPU time 2.2 seconds
Started Jul 01 12:29:40 PM PDT 24
Finished Jul 01 12:29:43 PM PDT 24
Peak memory 218156 kb
Host smart-578acb75-2766-4b27-9461-9961ca722ac9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476836087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.2
476836087
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.2999077623
Short name T721
Test name
Test status
Simulation time 149079382 ps
CPU time 3.52 seconds
Started Jul 01 12:29:38 PM PDT 24
Finished Jul 01 12:29:43 PM PDT 24
Peak memory 218664 kb
Host smart-23df6d19-d0f4-4125-91c3-47febaf9be77
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999077623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.2999077623
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.11884720
Short name T778
Test name
Test status
Simulation time 3752382022 ps
CPU time 23.68 seconds
Started Jul 01 12:29:39 PM PDT 24
Finished Jul 01 12:30:04 PM PDT 24
Peak memory 218064 kb
Host smart-1c8c66fb-cfe3-4810-87d2-9cf60e084d38
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11884720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_r
egwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jt
ag_regwen_during_op.11884720
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.880478665
Short name T446
Test name
Test status
Simulation time 14653949324 ps
CPU time 9.29 seconds
Started Jul 01 12:29:35 PM PDT 24
Finished Jul 01 12:29:45 PM PDT 24
Peak memory 218064 kb
Host smart-13dd7fef-80fd-49a5-8fa8-d9b445245bd5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880478665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.880478665
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.1338267324
Short name T288
Test name
Test status
Simulation time 2473806553 ps
CPU time 67.69 seconds
Started Jul 01 12:29:33 PM PDT 24
Finished Jul 01 12:30:41 PM PDT 24
Peak memory 267632 kb
Host smart-14ca3e24-f964-4301-9a5c-41fb35e04bfc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338267324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.1338267324
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.1312306895
Short name T417
Test name
Test status
Simulation time 6458139796 ps
CPU time 17.78 seconds
Started Jul 01 12:29:40 PM PDT 24
Finished Jul 01 12:29:59 PM PDT 24
Peak memory 238300 kb
Host smart-7763e71d-cb23-4dec-b6ab-9f6a4ca6b9d8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312306895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.1312306895
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.454867443
Short name T800
Test name
Test status
Simulation time 15245331 ps
CPU time 1.63 seconds
Started Jul 01 12:29:28 PM PDT 24
Finished Jul 01 12:29:30 PM PDT 24
Peak memory 222224 kb
Host smart-86130f5b-f7ee-4ce2-a4c0-dc274433ac2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454867443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.454867443
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.4168232531
Short name T806
Test name
Test status
Simulation time 255858459 ps
CPU time 6.65 seconds
Started Jul 01 12:29:36 PM PDT 24
Finished Jul 01 12:29:43 PM PDT 24
Peak memory 218048 kb
Host smart-213214a4-7a0e-4952-a861-3d234c59bfa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168232531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.4168232531
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.3040246098
Short name T89
Test name
Test status
Simulation time 113921288 ps
CPU time 24.24 seconds
Started Jul 01 12:29:45 PM PDT 24
Finished Jul 01 12:30:10 PM PDT 24
Peak memory 281812 kb
Host smart-28efe7cf-8768-418a-866e-6413f49aab7a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040246098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.3040246098
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.2408243270
Short name T283
Test name
Test status
Simulation time 265486878 ps
CPU time 10.28 seconds
Started Jul 01 12:29:43 PM PDT 24
Finished Jul 01 12:29:54 PM PDT 24
Peak memory 226436 kb
Host smart-d02c504f-223b-450e-bbb6-aff810b88783
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408243270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.2408243270
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.2126314074
Short name T341
Test name
Test status
Simulation time 949303945 ps
CPU time 7.78 seconds
Started Jul 01 12:29:44 PM PDT 24
Finished Jul 01 12:29:53 PM PDT 24
Peak memory 218584 kb
Host smart-d4e386ec-6bcb-4215-9ff0-d2120603c8c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126314074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.2126314074
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.2435145338
Short name T435
Test name
Test status
Simulation time 891008460 ps
CPU time 8.46 seconds
Started Jul 01 12:29:44 PM PDT 24
Finished Jul 01 12:29:54 PM PDT 24
Peak memory 218488 kb
Host smart-56d899a6-db74-4477-bab5-3b32561cf6a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435145338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.2
435145338
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.481517157
Short name T544
Test name
Test status
Simulation time 408707877 ps
CPU time 8.88 seconds
Started Jul 01 12:29:34 PM PDT 24
Finished Jul 01 12:29:43 PM PDT 24
Peak memory 226432 kb
Host smart-b40dc6da-bbe1-46c3-a9cb-2ae11b733cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481517157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.481517157
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.1114896769
Short name T177
Test name
Test status
Simulation time 104227245 ps
CPU time 3.33 seconds
Started Jul 01 12:29:28 PM PDT 24
Finished Jul 01 12:29:32 PM PDT 24
Peak memory 218240 kb
Host smart-f65aa7d1-9d6b-45c3-a035-3e674e17c488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114896769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.1114896769
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.755942810
Short name T310
Test name
Test status
Simulation time 906461487 ps
CPU time 21.02 seconds
Started Jul 01 12:29:30 PM PDT 24
Finished Jul 01 12:29:52 PM PDT 24
Peak memory 251316 kb
Host smart-6e138843-3008-4ea1-9b94-3a7b9c6779cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755942810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.755942810
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.2343027058
Short name T637
Test name
Test status
Simulation time 79006090 ps
CPU time 3.64 seconds
Started Jul 01 12:29:28 PM PDT 24
Finished Jul 01 12:29:33 PM PDT 24
Peak memory 223220 kb
Host smart-ac3aceb6-50b6-4cdd-9901-565d69f7f335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343027058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.2343027058
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.1284375918
Short name T846
Test name
Test status
Simulation time 4293185876 ps
CPU time 46.65 seconds
Started Jul 01 12:29:46 PM PDT 24
Finished Jul 01 12:30:33 PM PDT 24
Peak memory 226416 kb
Host smart-8a7e37d8-bcf5-4ea7-8881-23626910e6b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284375918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.1284375918
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.714013565
Short name T79
Test name
Test status
Simulation time 36207043 ps
CPU time 0.95 seconds
Started Jul 01 12:29:30 PM PDT 24
Finished Jul 01 12:29:32 PM PDT 24
Peak memory 218308 kb
Host smart-5ab9657a-7a06-48c3-92b5-57ceb2fbbc7a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714013565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctr
l_volatile_unlock_smoke.714013565
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.3560336489
Short name T92
Test name
Test status
Simulation time 57479886 ps
CPU time 0.97 seconds
Started Jul 01 12:34:24 PM PDT 24
Finished Jul 01 12:34:26 PM PDT 24
Peak memory 209340 kb
Host smart-f0c8890b-02db-4cdb-a801-0323c9a630f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560336489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.3560336489
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.1811547496
Short name T796
Test name
Test status
Simulation time 485436664 ps
CPU time 15.79 seconds
Started Jul 01 12:34:25 PM PDT 24
Finished Jul 01 12:34:42 PM PDT 24
Peak memory 218568 kb
Host smart-de0b39ed-2680-409f-86e9-f852f8c59f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811547496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.1811547496
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.2471235098
Short name T727
Test name
Test status
Simulation time 264627461 ps
CPU time 2.54 seconds
Started Jul 01 12:34:24 PM PDT 24
Finished Jul 01 12:34:27 PM PDT 24
Peak memory 217440 kb
Host smart-007c7a16-cc83-4427-bb45-16ca1c09d5b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471235098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.2471235098
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.3410988956
Short name T363
Test name
Test status
Simulation time 78686406 ps
CPU time 3.29 seconds
Started Jul 01 12:34:23 PM PDT 24
Finished Jul 01 12:34:27 PM PDT 24
Peak memory 218632 kb
Host smart-fce4d156-ff8b-4f2a-ac46-d45a639ae6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410988956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.3410988956
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.2715535718
Short name T500
Test name
Test status
Simulation time 746983519 ps
CPU time 28.94 seconds
Started Jul 01 12:34:24 PM PDT 24
Finished Jul 01 12:34:55 PM PDT 24
Peak memory 219296 kb
Host smart-7f0b2724-7a93-4fed-8d37-dd8c4871f614
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715535718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.2715535718
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.759036110
Short name T31
Test name
Test status
Simulation time 1013840953 ps
CPU time 15.31 seconds
Started Jul 01 12:34:23 PM PDT 24
Finished Jul 01 12:34:39 PM PDT 24
Peak memory 218616 kb
Host smart-abd35400-de36-4c41-a100-611c313d6d6c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759036110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_di
gest.759036110
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.1266552932
Short name T278
Test name
Test status
Simulation time 536437410 ps
CPU time 8.06 seconds
Started Jul 01 12:34:24 PM PDT 24
Finished Jul 01 12:34:34 PM PDT 24
Peak memory 218572 kb
Host smart-0ffdf1a3-b773-4cfb-ae58-24a0eb5ad40f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266552932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
1266552932
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.1289422489
Short name T691
Test name
Test status
Simulation time 381732946 ps
CPU time 12.61 seconds
Started Jul 01 12:34:24 PM PDT 24
Finished Jul 01 12:34:38 PM PDT 24
Peak memory 226412 kb
Host smart-739a3873-c508-4a40-a338-0bf4979f0e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289422489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.1289422489
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.4233761554
Short name T2
Test name
Test status
Simulation time 79037025 ps
CPU time 2.23 seconds
Started Jul 01 12:34:18 PM PDT 24
Finished Jul 01 12:34:21 PM PDT 24
Peak memory 217996 kb
Host smart-8dac552d-0c7d-4093-9117-5aadbad9f880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233761554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.4233761554
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.1942483954
Short name T488
Test name
Test status
Simulation time 225233938 ps
CPU time 25.25 seconds
Started Jul 01 12:34:18 PM PDT 24
Finished Jul 01 12:34:44 PM PDT 24
Peak memory 251236 kb
Host smart-d17d903b-c7da-4876-96d0-5dff5bb2d159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942483954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.1942483954
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.472200934
Short name T794
Test name
Test status
Simulation time 369948353 ps
CPU time 6.5 seconds
Started Jul 01 12:34:25 PM PDT 24
Finished Jul 01 12:34:33 PM PDT 24
Peak memory 251312 kb
Host smart-2cbc9975-0ad4-477c-a5cc-044f9dec9b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472200934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.472200934
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.3570646385
Short name T712
Test name
Test status
Simulation time 16333576 ps
CPU time 1.02 seconds
Started Jul 01 12:34:30 PM PDT 24
Finished Jul 01 12:34:32 PM PDT 24
Peak memory 212284 kb
Host smart-50f129ad-4d1f-4e60-a07c-8be4f47cee70
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570646385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.3570646385
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.2284558863
Short name T851
Test name
Test status
Simulation time 41787709 ps
CPU time 0.86 seconds
Started Jul 01 12:34:30 PM PDT 24
Finished Jul 01 12:34:31 PM PDT 24
Peak memory 209204 kb
Host smart-038afadc-c3ed-4c66-b4de-2a8fe26a815c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284558863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.2284558863
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.1088664359
Short name T343
Test name
Test status
Simulation time 719090158 ps
CPU time 13.72 seconds
Started Jul 01 12:34:31 PM PDT 24
Finished Jul 01 12:34:45 PM PDT 24
Peak memory 218656 kb
Host smart-7687a42d-926d-4d7a-8940-5c4faa050ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088664359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.1088664359
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.3061441294
Short name T25
Test name
Test status
Simulation time 482401847 ps
CPU time 3.41 seconds
Started Jul 01 12:34:31 PM PDT 24
Finished Jul 01 12:34:35 PM PDT 24
Peak memory 217508 kb
Host smart-480e1ad7-bd1f-4c76-b1e1-103d7699a4be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061441294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.3061441294
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.1738832372
Short name T533
Test name
Test status
Simulation time 141854553 ps
CPU time 3.82 seconds
Started Jul 01 12:34:25 PM PDT 24
Finished Jul 01 12:34:30 PM PDT 24
Peak memory 218536 kb
Host smart-68ee66c5-5dd0-4073-9c22-fa8a0684a091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738832372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.1738832372
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.2810962286
Short name T175
Test name
Test status
Simulation time 5688896363 ps
CPU time 16.7 seconds
Started Jul 01 12:34:29 PM PDT 24
Finished Jul 01 12:34:47 PM PDT 24
Peak memory 226604 kb
Host smart-81c73f08-070e-4148-85a3-7ad53617de3f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810962286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.2810962286
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.655814948
Short name T356
Test name
Test status
Simulation time 2008227103 ps
CPU time 10.31 seconds
Started Jul 01 12:34:29 PM PDT 24
Finished Jul 01 12:34:40 PM PDT 24
Peak memory 218608 kb
Host smart-246d24fa-2cd0-4679-a9ca-c05a5aa2af56
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655814948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_di
gest.655814948
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.701468946
Short name T715
Test name
Test status
Simulation time 2153270766 ps
CPU time 12.45 seconds
Started Jul 01 12:34:29 PM PDT 24
Finished Jul 01 12:34:42 PM PDT 24
Peak memory 218496 kb
Host smart-ab14ef19-05a1-4b90-91f9-70c16e736b49
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701468946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.701468946
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.810793025
Short name T227
Test name
Test status
Simulation time 639323236 ps
CPU time 8.53 seconds
Started Jul 01 12:34:33 PM PDT 24
Finished Jul 01 12:34:42 PM PDT 24
Peak memory 226452 kb
Host smart-6e7c799a-c81d-4f2a-a69d-3b2d082be52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810793025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.810793025
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.1970474477
Short name T642
Test name
Test status
Simulation time 75740670 ps
CPU time 1.83 seconds
Started Jul 01 12:34:28 PM PDT 24
Finished Jul 01 12:34:30 PM PDT 24
Peak memory 214620 kb
Host smart-6a0da2d9-9653-4e38-bb31-6a7a9d6d44d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970474477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.1970474477
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.2224407291
Short name T692
Test name
Test status
Simulation time 585501049 ps
CPU time 25.84 seconds
Started Jul 01 12:34:25 PM PDT 24
Finished Jul 01 12:34:52 PM PDT 24
Peak memory 251308 kb
Host smart-5d4abe49-9584-4919-9059-e6bc24c79a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224407291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.2224407291
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.1718034651
Short name T519
Test name
Test status
Simulation time 136159782 ps
CPU time 4.67 seconds
Started Jul 01 12:34:24 PM PDT 24
Finished Jul 01 12:34:30 PM PDT 24
Peak memory 222788 kb
Host smart-a5385388-3b0e-430f-b34c-b9f465851ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718034651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.1718034651
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.2787501964
Short name T498
Test name
Test status
Simulation time 31887951485 ps
CPU time 269.72 seconds
Started Jul 01 12:34:31 PM PDT 24
Finished Jul 01 12:39:02 PM PDT 24
Peak memory 283884 kb
Host smart-77eb44d2-56bd-4d9b-808c-3e7db0e95f7c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787501964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.2787501964
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.1920916730
Short name T857
Test name
Test status
Simulation time 17780896 ps
CPU time 1 seconds
Started Jul 01 12:34:25 PM PDT 24
Finished Jul 01 12:34:28 PM PDT 24
Peak memory 212192 kb
Host smart-5e5d7766-c8d8-4caa-9df1-6193d8bd5eab
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920916730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.1920916730
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.3978556043
Short name T475
Test name
Test status
Simulation time 16754000 ps
CPU time 1.1 seconds
Started Jul 01 12:34:36 PM PDT 24
Finished Jul 01 12:34:38 PM PDT 24
Peak memory 209352 kb
Host smart-bb3f2735-c751-495c-8e50-a31703d4c94c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978556043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.3978556043
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.2657651605
Short name T508
Test name
Test status
Simulation time 846422402 ps
CPU time 12.04 seconds
Started Jul 01 12:34:35 PM PDT 24
Finished Jul 01 12:34:48 PM PDT 24
Peak memory 218616 kb
Host smart-960efd5b-81b7-438b-89fc-c4c08e211c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657651605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.2657651605
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.440822585
Short name T396
Test name
Test status
Simulation time 552062804 ps
CPU time 13.46 seconds
Started Jul 01 12:34:36 PM PDT 24
Finished Jul 01 12:34:51 PM PDT 24
Peak memory 217748 kb
Host smart-c4529e8c-785e-4383-a640-38b4a7593556
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440822585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.440822585
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.2576878182
Short name T370
Test name
Test status
Simulation time 155835275 ps
CPU time 4.35 seconds
Started Jul 01 12:34:35 PM PDT 24
Finished Jul 01 12:34:41 PM PDT 24
Peak memory 223212 kb
Host smart-76a77eed-033e-4d8f-84e2-725a24ad80cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576878182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.2576878182
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.543828389
Short name T336
Test name
Test status
Simulation time 1283156133 ps
CPU time 10.26 seconds
Started Jul 01 12:34:35 PM PDT 24
Finished Jul 01 12:34:47 PM PDT 24
Peak memory 218504 kb
Host smart-a69a0b73-e7d3-44e4-b7de-a7784b75ea83
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543828389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_di
gest.543828389
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.890350586
Short name T364
Test name
Test status
Simulation time 551062390 ps
CPU time 10.93 seconds
Started Jul 01 12:34:35 PM PDT 24
Finished Jul 01 12:34:47 PM PDT 24
Peak memory 226392 kb
Host smart-59e1a8ed-54ac-4389-af89-9f574f4c516e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890350586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.890350586
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.2369717728
Short name T342
Test name
Test status
Simulation time 1524905245 ps
CPU time 10.84 seconds
Started Jul 01 12:34:37 PM PDT 24
Finished Jul 01 12:34:49 PM PDT 24
Peak memory 218752 kb
Host smart-5f8847c0-bbf0-49b8-b0ec-c93c5bb21666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369717728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.2369717728
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.826431255
Short name T534
Test name
Test status
Simulation time 27908338 ps
CPU time 2.16 seconds
Started Jul 01 12:34:29 PM PDT 24
Finished Jul 01 12:34:32 PM PDT 24
Peak memory 214760 kb
Host smart-cf33c241-541e-4b9a-8c7e-178eb603f7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826431255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.826431255
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.3877619354
Short name T261
Test name
Test status
Simulation time 3405504070 ps
CPU time 24.68 seconds
Started Jul 01 12:34:34 PM PDT 24
Finished Jul 01 12:35:00 PM PDT 24
Peak memory 251380 kb
Host smart-edb58d88-edbf-4789-9966-eea21193c98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877619354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.3877619354
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.1010949651
Short name T314
Test name
Test status
Simulation time 173339815 ps
CPU time 3.52 seconds
Started Jul 01 12:34:34 PM PDT 24
Finished Jul 01 12:34:39 PM PDT 24
Peak memory 218556 kb
Host smart-4fefccae-fe00-45eb-9218-72d639f10c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010949651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.1010949651
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.1388700485
Short name T719
Test name
Test status
Simulation time 3710696894 ps
CPU time 133.73 seconds
Started Jul 01 12:34:36 PM PDT 24
Finished Jul 01 12:36:51 PM PDT 24
Peak memory 274380 kb
Host smart-a1aa1edc-b462-47ed-978c-7af6f4308fb5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388700485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.1388700485
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.3023509699
Short name T527
Test name
Test status
Simulation time 17080153363 ps
CPU time 592.39 seconds
Started Jul 01 12:34:36 PM PDT 24
Finished Jul 01 12:44:29 PM PDT 24
Peak memory 311116 kb
Host smart-baee63f0-f875-403b-8ee9-944337314d25
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3023509699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.3023509699
Directory /workspace/42.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.2824485263
Short name T34
Test name
Test status
Simulation time 12864387 ps
CPU time 0.82 seconds
Started Jul 01 12:34:33 PM PDT 24
Finished Jul 01 12:34:35 PM PDT 24
Peak memory 209232 kb
Host smart-2a58d231-6092-4fda-a699-bb50942a294f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824485263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.2824485263
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.1164973950
Short name T380
Test name
Test status
Simulation time 31732918 ps
CPU time 1.13 seconds
Started Jul 01 12:34:42 PM PDT 24
Finished Jul 01 12:34:44 PM PDT 24
Peak memory 209308 kb
Host smart-9a1883fe-2af0-45d1-94cb-030f25c4db6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164973950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.1164973950
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.3106704063
Short name T353
Test name
Test status
Simulation time 231223908 ps
CPU time 11.81 seconds
Started Jul 01 12:34:40 PM PDT 24
Finished Jul 01 12:34:53 PM PDT 24
Peak memory 226408 kb
Host smart-18bcb7e4-be5d-4808-ba32-ce82b38c1269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106704063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.3106704063
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.1633579507
Short name T197
Test name
Test status
Simulation time 672736776 ps
CPU time 6.7 seconds
Started Jul 01 12:34:40 PM PDT 24
Finished Jul 01 12:34:48 PM PDT 24
Peak memory 217648 kb
Host smart-fb62517d-038b-4129-8709-fbf42c781d47
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633579507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.1633579507
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.3542347686
Short name T235
Test name
Test status
Simulation time 25936663 ps
CPU time 2.01 seconds
Started Jul 01 12:34:42 PM PDT 24
Finished Jul 01 12:34:45 PM PDT 24
Peak memory 222396 kb
Host smart-1bc1c37d-db92-4d3d-9d15-881593a411c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542347686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.3542347686
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.2520272978
Short name T287
Test name
Test status
Simulation time 2677299535 ps
CPU time 26.47 seconds
Started Jul 01 12:34:41 PM PDT 24
Finished Jul 01 12:35:08 PM PDT 24
Peak memory 219256 kb
Host smart-827f3b7c-bb9e-4e38-9e3b-0eef50cf6a07
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520272978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.2520272978
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.596453312
Short name T493
Test name
Test status
Simulation time 1083699445 ps
CPU time 7.69 seconds
Started Jul 01 12:34:49 PM PDT 24
Finished Jul 01 12:34:58 PM PDT 24
Peak memory 218648 kb
Host smart-88718d18-beec-4c12-ae0b-6c07f5115c3a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596453312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_di
gest.596453312
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.2364507720
Short name T814
Test name
Test status
Simulation time 2040828535 ps
CPU time 19.97 seconds
Started Jul 01 12:34:39 PM PDT 24
Finished Jul 01 12:35:00 PM PDT 24
Peak memory 218524 kb
Host smart-40f2cd11-2e83-4872-9c68-5354735196f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364507720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
2364507720
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.744722488
Short name T473
Test name
Test status
Simulation time 227183030 ps
CPU time 9.75 seconds
Started Jul 01 12:34:42 PM PDT 24
Finished Jul 01 12:34:53 PM PDT 24
Peak memory 218448 kb
Host smart-0528f07f-8e6e-45ab-8cfa-77b20418f566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744722488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.744722488
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.255303178
Short name T444
Test name
Test status
Simulation time 43630280 ps
CPU time 2.65 seconds
Started Jul 01 12:34:35 PM PDT 24
Finished Jul 01 12:34:39 PM PDT 24
Peak memory 215140 kb
Host smart-04f328d1-56e3-42ed-8175-d559b6b9b7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255303178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.255303178
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.4077368590
Short name T633
Test name
Test status
Simulation time 556402827 ps
CPU time 25.67 seconds
Started Jul 01 12:34:39 PM PDT 24
Finished Jul 01 12:35:07 PM PDT 24
Peak memory 251376 kb
Host smart-e25efa91-3315-4218-9efe-2af744782cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077368590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.4077368590
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.2960221416
Short name T385
Test name
Test status
Simulation time 78112839 ps
CPU time 7.37 seconds
Started Jul 01 12:34:40 PM PDT 24
Finished Jul 01 12:34:49 PM PDT 24
Peak memory 247284 kb
Host smart-5eb508e8-b0a7-46f2-84ad-921138aff9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960221416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.2960221416
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.1725288701
Short name T198
Test name
Test status
Simulation time 11665907752 ps
CPU time 184.03 seconds
Started Jul 01 12:34:50 PM PDT 24
Finished Jul 01 12:37:55 PM PDT 24
Peak memory 251376 kb
Host smart-3d499fe2-5b20-4e7b-8ed5-6757bb0326dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725288701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.1725288701
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.3825115660
Short name T161
Test name
Test status
Simulation time 95851122362 ps
CPU time 575.04 seconds
Started Jul 01 12:34:49 PM PDT 24
Finished Jul 01 12:44:25 PM PDT 24
Peak memory 333516 kb
Host smart-e8b11370-df6d-4988-a10e-eb17778913b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3825115660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.3825115660
Directory /workspace/43.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.393377447
Short name T359
Test name
Test status
Simulation time 38458712 ps
CPU time 0.92 seconds
Started Jul 01 12:34:39 PM PDT 24
Finished Jul 01 12:34:42 PM PDT 24
Peak memory 212320 kb
Host smart-618ee6d2-3cf3-44c3-aa12-7730df7fba0b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393377447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ct
rl_volatile_unlock_smoke.393377447
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.843361046
Short name T403
Test name
Test status
Simulation time 128169809 ps
CPU time 1.01 seconds
Started Jul 01 12:34:45 PM PDT 24
Finished Jul 01 12:34:46 PM PDT 24
Peak memory 209456 kb
Host smart-04d07530-5994-4528-9959-5360b34e9782
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843361046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.843361046
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.81505320
Short name T191
Test name
Test status
Simulation time 566119978 ps
CPU time 12.76 seconds
Started Jul 01 12:34:46 PM PDT 24
Finished Jul 01 12:34:59 PM PDT 24
Peak memory 218616 kb
Host smart-50fb77d6-4c3f-4586-bf63-768d04bf80ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81505320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.81505320
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.1797293656
Short name T352
Test name
Test status
Simulation time 81846506 ps
CPU time 2.72 seconds
Started Jul 01 12:34:48 PM PDT 24
Finished Jul 01 12:34:51 PM PDT 24
Peak memory 217436 kb
Host smart-08995297-4224-457b-9449-c53bdbab1e62
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797293656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.1797293656
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.807153496
Short name T864
Test name
Test status
Simulation time 984330158 ps
CPU time 3.68 seconds
Started Jul 01 12:34:44 PM PDT 24
Finished Jul 01 12:34:48 PM PDT 24
Peak memory 218588 kb
Host smart-3c3b9937-aca6-4eee-a3ca-b2ee254a9fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807153496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.807153496
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.967199809
Short name T813
Test name
Test status
Simulation time 210673467 ps
CPU time 8.09 seconds
Started Jul 01 12:34:44 PM PDT 24
Finished Jul 01 12:34:53 PM PDT 24
Peak memory 226364 kb
Host smart-1142ed7b-09f5-432f-8a3a-36571af6b21c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967199809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.967199809
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.2791247319
Short name T329
Test name
Test status
Simulation time 334707052 ps
CPU time 11.21 seconds
Started Jul 01 12:34:45 PM PDT 24
Finished Jul 01 12:34:57 PM PDT 24
Peak memory 218668 kb
Host smart-6d994e32-ff6a-4caa-817d-829e986c5caf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791247319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.2791247319
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.3516718276
Short name T644
Test name
Test status
Simulation time 1638854973 ps
CPU time 13.97 seconds
Started Jul 01 12:34:44 PM PDT 24
Finished Jul 01 12:34:59 PM PDT 24
Peak memory 218508 kb
Host smart-2e7c8666-a055-47f4-a771-957b7919dcff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516718276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
3516718276
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.503693116
Short name T858
Test name
Test status
Simulation time 1512985780 ps
CPU time 9.56 seconds
Started Jul 01 12:34:45 PM PDT 24
Finished Jul 01 12:34:55 PM PDT 24
Peak memory 218656 kb
Host smart-2652c737-ed2e-4018-bc80-60d71983fff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503693116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.503693116
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.1068199832
Short name T724
Test name
Test status
Simulation time 209514024 ps
CPU time 2.34 seconds
Started Jul 01 12:34:50 PM PDT 24
Finished Jul 01 12:34:53 PM PDT 24
Peak memory 214908 kb
Host smart-d3cf58ea-c3e7-48ac-8430-55a219bce510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068199832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.1068199832
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.239035280
Short name T279
Test name
Test status
Simulation time 302043875 ps
CPU time 33.41 seconds
Started Jul 01 12:34:43 PM PDT 24
Finished Jul 01 12:35:17 PM PDT 24
Peak memory 251248 kb
Host smart-9e7899f6-3f04-4257-949b-cd946c77ec3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239035280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.239035280
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.504366149
Short name T730
Test name
Test status
Simulation time 46421681 ps
CPU time 6.81 seconds
Started Jul 01 12:34:50 PM PDT 24
Finished Jul 01 12:34:57 PM PDT 24
Peak memory 251336 kb
Host smart-b1faed14-5f14-4dfb-a9bb-a05c29a12832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504366149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.504366149
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.54393300
Short name T871
Test name
Test status
Simulation time 53456620465 ps
CPU time 545.38 seconds
Started Jul 01 12:34:46 PM PDT 24
Finished Jul 01 12:43:51 PM PDT 24
Peak memory 303816 kb
Host smart-6b431536-c5a2-4d6f-82d3-7fd39e1dbc6b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54393300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.lc_ctrl_stress_all.54393300
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.824346942
Short name T162
Test name
Test status
Simulation time 63839267258 ps
CPU time 596.17 seconds
Started Jul 01 12:34:45 PM PDT 24
Finished Jul 01 12:44:42 PM PDT 24
Peak memory 284252 kb
Host smart-f81810c0-90f3-4cbc-bfb2-0de98be7e380
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=824346942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all_with_rand_reset.824346942
Directory /workspace/44.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.601515874
Short name T41
Test name
Test status
Simulation time 26291429 ps
CPU time 1.11 seconds
Started Jul 01 12:34:42 PM PDT 24
Finished Jul 01 12:34:44 PM PDT 24
Peak memory 212092 kb
Host smart-ef3cb034-d7c9-4196-9043-8668baa24a5b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601515874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ct
rl_volatile_unlock_smoke.601515874
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.1696244791
Short name T399
Test name
Test status
Simulation time 35062853 ps
CPU time 0.83 seconds
Started Jul 01 12:34:50 PM PDT 24
Finished Jul 01 12:34:52 PM PDT 24
Peak memory 209416 kb
Host smart-8a1826d9-c293-4fb8-a8a4-24e51d5b2c54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696244791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.1696244791
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.3036084915
Short name T497
Test name
Test status
Simulation time 325242481 ps
CPU time 11.29 seconds
Started Jul 01 12:34:50 PM PDT 24
Finished Jul 01 12:35:02 PM PDT 24
Peak memory 218652 kb
Host smart-1b48becb-8909-40b1-badb-1c18ab18873e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036084915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.3036084915
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.3870145554
Short name T742
Test name
Test status
Simulation time 682918535 ps
CPU time 4.34 seconds
Started Jul 01 12:34:49 PM PDT 24
Finished Jul 01 12:34:54 PM PDT 24
Peak memory 217696 kb
Host smart-2fbe6ef4-d140-4f49-bb51-764f72061f24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870145554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.3870145554
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.496975342
Short name T655
Test name
Test status
Simulation time 61465162 ps
CPU time 3.22 seconds
Started Jul 01 12:34:54 PM PDT 24
Finished Jul 01 12:34:58 PM PDT 24
Peak memory 218760 kb
Host smart-515181e1-7275-4f47-b6cd-e73419a547d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496975342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.496975342
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.518193716
Short name T312
Test name
Test status
Simulation time 1559780241 ps
CPU time 18.1 seconds
Started Jul 01 12:34:51 PM PDT 24
Finished Jul 01 12:35:10 PM PDT 24
Peak memory 226432 kb
Host smart-906c7d9c-9981-4ed7-935a-8f092404a364
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518193716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.518193716
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.1524873882
Short name T426
Test name
Test status
Simulation time 416420316 ps
CPU time 9.46 seconds
Started Jul 01 12:34:56 PM PDT 24
Finished Jul 01 12:35:06 PM PDT 24
Peak memory 218532 kb
Host smart-a3b22a5d-7918-4540-a297-ec07dcee9f05
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524873882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.1524873882
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.4040254415
Short name T529
Test name
Test status
Simulation time 560391657 ps
CPU time 7.69 seconds
Started Jul 01 12:34:55 PM PDT 24
Finished Jul 01 12:35:04 PM PDT 24
Peak memory 218516 kb
Host smart-091c9639-2ab6-4455-b6c8-d290d1ef7d38
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040254415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
4040254415
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.3862449710
Short name T55
Test name
Test status
Simulation time 272176180 ps
CPU time 7.05 seconds
Started Jul 01 12:34:50 PM PDT 24
Finished Jul 01 12:34:58 PM PDT 24
Peak memory 224888 kb
Host smart-9c56b6a1-d6f9-4070-bce9-7b549a7e7b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862449710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.3862449710
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.4262154740
Short name T594
Test name
Test status
Simulation time 56692233 ps
CPU time 2.31 seconds
Started Jul 01 12:34:55 PM PDT 24
Finished Jul 01 12:34:58 PM PDT 24
Peak memory 217704 kb
Host smart-44b52b91-b155-4b60-a84e-f069cb650f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262154740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.4262154740
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.2730609628
Short name T676
Test name
Test status
Simulation time 3157632756 ps
CPU time 32.66 seconds
Started Jul 01 12:34:51 PM PDT 24
Finished Jul 01 12:35:25 PM PDT 24
Peak memory 251400 kb
Host smart-df2be401-446f-403d-bb7a-203f0218ac63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730609628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.2730609628
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.203465212
Short name T716
Test name
Test status
Simulation time 81860027 ps
CPU time 7.29 seconds
Started Jul 01 12:34:55 PM PDT 24
Finished Jul 01 12:35:03 PM PDT 24
Peak memory 247284 kb
Host smart-5772bf6c-02f0-44f4-a324-37fffe95b3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203465212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.203465212
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.3531966840
Short name T619
Test name
Test status
Simulation time 10104458945 ps
CPU time 324.2 seconds
Started Jul 01 12:34:55 PM PDT 24
Finished Jul 01 12:40:20 PM PDT 24
Peak memory 284092 kb
Host smart-6db8ec41-0c12-4e7f-807c-42d17e86d771
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531966840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.3531966840
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1366103900
Short name T270
Test name
Test status
Simulation time 20964808 ps
CPU time 0.96 seconds
Started Jul 01 12:34:50 PM PDT 24
Finished Jul 01 12:34:52 PM PDT 24
Peak memory 212224 kb
Host smart-17743880-0c1e-4fd2-8b59-25e3e7bcf925
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366103900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.1366103900
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.1471520010
Short name T78
Test name
Test status
Simulation time 25367622 ps
CPU time 1.05 seconds
Started Jul 01 12:34:55 PM PDT 24
Finished Jul 01 12:34:57 PM PDT 24
Peak memory 209556 kb
Host smart-2965e997-6511-4e3a-a516-15562c34508c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471520010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.1471520010
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.2007454053
Short name T738
Test name
Test status
Simulation time 315212763 ps
CPU time 14.32 seconds
Started Jul 01 12:34:56 PM PDT 24
Finished Jul 01 12:35:11 PM PDT 24
Peak memory 218604 kb
Host smart-a655d12a-c09c-4ea3-96f4-cc7f3cc71bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007454053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.2007454053
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.3983481874
Short name T9
Test name
Test status
Simulation time 386231869 ps
CPU time 5.58 seconds
Started Jul 01 12:34:54 PM PDT 24
Finished Jul 01 12:35:01 PM PDT 24
Peak memory 217760 kb
Host smart-752dc6d9-bfcb-46c2-8931-f85f5f4a3c83
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983481874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.3983481874
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.3081462961
Short name T717
Test name
Test status
Simulation time 67943000 ps
CPU time 3.39 seconds
Started Jul 01 12:34:59 PM PDT 24
Finished Jul 01 12:35:03 PM PDT 24
Peak memory 223032 kb
Host smart-cf8d8b35-fdc5-4ea5-9874-96eb931cfe5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081462961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.3081462961
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.3191653945
Short name T408
Test name
Test status
Simulation time 2705131367 ps
CPU time 13.33 seconds
Started Jul 01 12:34:55 PM PDT 24
Finished Jul 01 12:35:09 PM PDT 24
Peak memory 219776 kb
Host smart-6075e27f-f0dd-4053-99fd-354f9a53a173
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191653945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.3191653945
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.2632186699
Short name T169
Test name
Test status
Simulation time 1874988884 ps
CPU time 10.7 seconds
Started Jul 01 12:34:54 PM PDT 24
Finished Jul 01 12:35:06 PM PDT 24
Peak memory 218592 kb
Host smart-8df4614a-47dc-418c-969e-bb001dae6032
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632186699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.2632186699
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.970571273
Short name T804
Test name
Test status
Simulation time 666289281 ps
CPU time 12.12 seconds
Started Jul 01 12:34:56 PM PDT 24
Finished Jul 01 12:35:09 PM PDT 24
Peak memory 218572 kb
Host smart-b991fa33-565e-48ee-8197-dba818dfe2bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970571273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.970571273
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.1837764841
Short name T458
Test name
Test status
Simulation time 448356997 ps
CPU time 9.97 seconds
Started Jul 01 12:34:53 PM PDT 24
Finished Jul 01 12:35:03 PM PDT 24
Peak memory 226436 kb
Host smart-8d5804fb-d8bc-4120-ac0d-34aea1a67c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837764841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.1837764841
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.3128991539
Short name T567
Test name
Test status
Simulation time 39082674 ps
CPU time 2.65 seconds
Started Jul 01 12:34:54 PM PDT 24
Finished Jul 01 12:34:57 PM PDT 24
Peak memory 218024 kb
Host smart-f5a26842-8747-4a1e-810e-e1c88108aab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128991539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.3128991539
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.3045795681
Short name T237
Test name
Test status
Simulation time 169904024 ps
CPU time 18.55 seconds
Started Jul 01 12:34:54 PM PDT 24
Finished Jul 01 12:35:14 PM PDT 24
Peak memory 251340 kb
Host smart-8f61d35d-11de-47b9-b85f-6593bae37066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045795681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.3045795681
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.2847621739
Short name T15
Test name
Test status
Simulation time 123019600 ps
CPU time 6.79 seconds
Started Jul 01 12:34:57 PM PDT 24
Finished Jul 01 12:35:05 PM PDT 24
Peak memory 247504 kb
Host smart-995b6f7e-5dd2-4f72-9087-8d0f491b98ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847621739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.2847621739
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.201427450
Short name T556
Test name
Test status
Simulation time 4040435257 ps
CPU time 81.83 seconds
Started Jul 01 12:34:53 PM PDT 24
Finished Jul 01 12:36:16 PM PDT 24
Peak memory 274740 kb
Host smart-e1bcfdac-34da-4562-b32e-a834c70b4e72
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201427450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.201427450
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.4248231943
Short name T335
Test name
Test status
Simulation time 52485431 ps
CPU time 0.92 seconds
Started Jul 01 12:34:54 PM PDT 24
Finished Jul 01 12:34:56 PM PDT 24
Peak memory 212260 kb
Host smart-85decd47-648f-419c-a303-f6ab1ee26aa8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248231943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.4248231943
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.2395923036
Short name T338
Test name
Test status
Simulation time 25803002 ps
CPU time 1.11 seconds
Started Jul 01 12:35:05 PM PDT 24
Finished Jul 01 12:35:06 PM PDT 24
Peak memory 209364 kb
Host smart-d35485c1-710f-4968-ba35-beaf5a939ddd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395923036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.2395923036
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.1188777194
Short name T539
Test name
Test status
Simulation time 240373443 ps
CPU time 11.25 seconds
Started Jul 01 12:34:58 PM PDT 24
Finished Jul 01 12:35:11 PM PDT 24
Peak memory 218540 kb
Host smart-3999937e-a6a6-4cae-8595-807d3ac1c995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188777194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.1188777194
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.282585496
Short name T367
Test name
Test status
Simulation time 1862988471 ps
CPU time 7.04 seconds
Started Jul 01 12:34:59 PM PDT 24
Finished Jul 01 12:35:07 PM PDT 24
Peak memory 217364 kb
Host smart-9a719eb8-3322-45f1-bb9b-2d5b047926fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282585496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.282585496
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.746970717
Short name T553
Test name
Test status
Simulation time 77053703 ps
CPU time 3.95 seconds
Started Jul 01 12:34:59 PM PDT 24
Finished Jul 01 12:35:04 PM PDT 24
Peak memory 218644 kb
Host smart-e862bc04-2626-4174-a42f-31e364c104f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746970717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.746970717
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.1125906910
Short name T825
Test name
Test status
Simulation time 260484459 ps
CPU time 8.82 seconds
Started Jul 01 12:35:00 PM PDT 24
Finished Jul 01 12:35:09 PM PDT 24
Peak memory 226424 kb
Host smart-12b4e47c-fe77-4048-8de1-215b1bc7389e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125906910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.1125906910
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.3937648103
Short name T187
Test name
Test status
Simulation time 395116592 ps
CPU time 7.93 seconds
Started Jul 01 12:35:03 PM PDT 24
Finished Jul 01 12:35:12 PM PDT 24
Peak memory 218468 kb
Host smart-2564a3ec-170b-42ef-acfe-5deda8eefa16
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937648103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.3937648103
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.1652438675
Short name T13
Test name
Test status
Simulation time 743155825 ps
CPU time 13.55 seconds
Started Jul 01 12:35:01 PM PDT 24
Finished Jul 01 12:35:15 PM PDT 24
Peak memory 226312 kb
Host smart-41c8363a-ec55-4ed3-9814-3033c1588f53
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652438675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
1652438675
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.83805718
Short name T669
Test name
Test status
Simulation time 599527705 ps
CPU time 10.52 seconds
Started Jul 01 12:35:01 PM PDT 24
Finished Jul 01 12:35:12 PM PDT 24
Peak memory 226360 kb
Host smart-56e81430-36c1-4c51-bf72-9febadc02c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83805718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.83805718
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.3216764638
Short name T809
Test name
Test status
Simulation time 75780070 ps
CPU time 2.55 seconds
Started Jul 01 12:34:59 PM PDT 24
Finished Jul 01 12:35:03 PM PDT 24
Peak memory 218064 kb
Host smart-8531048f-ddff-4800-a0dc-e5a93021c2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216764638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.3216764638
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.1931049352
Short name T558
Test name
Test status
Simulation time 979531311 ps
CPU time 29.84 seconds
Started Jul 01 12:35:01 PM PDT 24
Finished Jul 01 12:35:31 PM PDT 24
Peak memory 251260 kb
Host smart-1a54cfbb-d303-4397-b92a-1c72084829e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931049352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.1931049352
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.4249360995
Short name T427
Test name
Test status
Simulation time 214458527 ps
CPU time 7.19 seconds
Started Jul 01 12:35:02 PM PDT 24
Finished Jul 01 12:35:10 PM PDT 24
Peak memory 251280 kb
Host smart-64ff0522-e0c5-43f0-ad7e-206642af0a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249360995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.4249360995
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.1043394630
Short name T654
Test name
Test status
Simulation time 1583947111 ps
CPU time 45.93 seconds
Started Jul 01 12:35:04 PM PDT 24
Finished Jul 01 12:35:51 PM PDT 24
Peak memory 251288 kb
Host smart-b3b7a411-501a-40af-80db-2ee655cc61eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043394630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.1043394630
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.864826191
Short name T612
Test name
Test status
Simulation time 14712202 ps
CPU time 1.13 seconds
Started Jul 01 12:35:00 PM PDT 24
Finished Jul 01 12:35:02 PM PDT 24
Peak memory 212236 kb
Host smart-481ba0c2-5be5-4b8a-8931-4f52209f5831
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864826191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ct
rl_volatile_unlock_smoke.864826191
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.1014454485
Short name T516
Test name
Test status
Simulation time 168877730 ps
CPU time 0.92 seconds
Started Jul 01 12:35:14 PM PDT 24
Finished Jul 01 12:35:15 PM PDT 24
Peak memory 209396 kb
Host smart-2992259f-2931-4d43-8627-2f9939cbadf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014454485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.1014454485
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.1507911832
Short name T297
Test name
Test status
Simulation time 235566176 ps
CPU time 11.15 seconds
Started Jul 01 12:35:04 PM PDT 24
Finished Jul 01 12:35:16 PM PDT 24
Peak memory 226452 kb
Host smart-d720bce5-01d6-46aa-a325-c4b56961518a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507911832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.1507911832
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.3585133343
Short name T6
Test name
Test status
Simulation time 32719408 ps
CPU time 1.19 seconds
Started Jul 01 12:35:04 PM PDT 24
Finished Jul 01 12:35:06 PM PDT 24
Peak memory 217276 kb
Host smart-8ad59461-9d16-46e8-9140-40f621d0d936
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585133343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.3585133343
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.3860652304
Short name T66
Test name
Test status
Simulation time 43626143 ps
CPU time 1.73 seconds
Started Jul 01 12:35:04 PM PDT 24
Finished Jul 01 12:35:07 PM PDT 24
Peak memory 218536 kb
Host smart-092819a7-1bde-4e5c-99f8-ccf4cc667a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860652304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.3860652304
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.3335284364
Short name T62
Test name
Test status
Simulation time 732048590 ps
CPU time 20.16 seconds
Started Jul 01 12:35:09 PM PDT 24
Finished Jul 01 12:35:30 PM PDT 24
Peak memory 226452 kb
Host smart-397ca71e-8609-4519-8cb2-d20c01af0465
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335284364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.3335284364
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.1472924263
Short name T247
Test name
Test status
Simulation time 322314174 ps
CPU time 14.39 seconds
Started Jul 01 12:35:06 PM PDT 24
Finished Jul 01 12:35:21 PM PDT 24
Peak memory 218600 kb
Host smart-da9c9951-7785-4284-89af-b2a75e700e46
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472924263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.1472924263
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.1545601620
Short name T781
Test name
Test status
Simulation time 233687994 ps
CPU time 10.01 seconds
Started Jul 01 12:35:10 PM PDT 24
Finished Jul 01 12:35:20 PM PDT 24
Peak memory 226468 kb
Host smart-2971659e-15b5-4671-94aa-18dc9b8df21e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545601620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
1545601620
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.2421534309
Short name T803
Test name
Test status
Simulation time 2108717193 ps
CPU time 9.13 seconds
Started Jul 01 12:35:05 PM PDT 24
Finished Jul 01 12:35:15 PM PDT 24
Peak memory 218676 kb
Host smart-7521dcc4-d5e4-4242-b826-70cf751de99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421534309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.2421534309
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.1528842902
Short name T166
Test name
Test status
Simulation time 151469645 ps
CPU time 1.91 seconds
Started Jul 01 12:35:05 PM PDT 24
Finished Jul 01 12:35:08 PM PDT 24
Peak memory 214516 kb
Host smart-b0709caf-b0b7-4ac3-a0b4-0a802f3e2ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528842902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.1528842902
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.2960559828
Short name T505
Test name
Test status
Simulation time 607923658 ps
CPU time 18.51 seconds
Started Jul 01 12:35:04 PM PDT 24
Finished Jul 01 12:35:22 PM PDT 24
Peak memory 251264 kb
Host smart-b35e1847-2c1c-4e2d-b425-0f800e1b5531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960559828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.2960559828
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.1759235896
Short name T587
Test name
Test status
Simulation time 133056624 ps
CPU time 8.94 seconds
Started Jul 01 12:35:07 PM PDT 24
Finished Jul 01 12:35:17 PM PDT 24
Peak memory 251268 kb
Host smart-ce22448d-81f6-4cdc-9e47-7370a201a07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759235896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.1759235896
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.1306492538
Short name T325
Test name
Test status
Simulation time 8244862305 ps
CPU time 109.71 seconds
Started Jul 01 12:35:06 PM PDT 24
Finished Jul 01 12:36:56 PM PDT 24
Peak memory 248360 kb
Host smart-2d977b7d-4977-495e-bae0-57531a19e14d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306492538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.1306492538
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.73258648
Short name T607
Test name
Test status
Simulation time 19051804 ps
CPU time 0.98 seconds
Started Jul 01 12:35:09 PM PDT 24
Finished Jul 01 12:35:11 PM PDT 24
Peak memory 212260 kb
Host smart-577ad62b-87f6-4914-bc20-905614a788d9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73258648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctr
l_volatile_unlock_smoke.73258648
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.4039405859
Short name T272
Test name
Test status
Simulation time 11844266 ps
CPU time 0.99 seconds
Started Jul 01 12:35:15 PM PDT 24
Finished Jul 01 12:35:18 PM PDT 24
Peak memory 209324 kb
Host smart-362997cb-a26e-4e50-8a22-607690cc3811
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039405859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.4039405859
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.3097055299
Short name T347
Test name
Test status
Simulation time 236037694 ps
CPU time 8.59 seconds
Started Jul 01 12:35:12 PM PDT 24
Finished Jul 01 12:35:21 PM PDT 24
Peak memory 218656 kb
Host smart-3ef68bc7-733e-42a9-ab38-bc9466bbe0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097055299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.3097055299
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.2391154591
Short name T677
Test name
Test status
Simulation time 649558126 ps
CPU time 4.86 seconds
Started Jul 01 12:35:12 PM PDT 24
Finished Jul 01 12:35:17 PM PDT 24
Peak memory 217456 kb
Host smart-d31eb9b6-d54a-42e9-8892-0c3f34debfcb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391154591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.2391154591
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.651135836
Short name T705
Test name
Test status
Simulation time 1365470209 ps
CPU time 3.75 seconds
Started Jul 01 12:35:09 PM PDT 24
Finished Jul 01 12:35:14 PM PDT 24
Peak memory 218620 kb
Host smart-cc118f92-f1f8-4146-a4f5-943c5d41cd6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651135836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.651135836
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.4185297490
Short name T720
Test name
Test status
Simulation time 8355588440 ps
CPU time 18.53 seconds
Started Jul 01 12:35:12 PM PDT 24
Finished Jul 01 12:35:31 PM PDT 24
Peak memory 220056 kb
Host smart-7594d9c5-3861-4276-aaeb-52cffde69c27
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185297490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.4185297490
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.869848620
Short name T557
Test name
Test status
Simulation time 550265294 ps
CPU time 8.62 seconds
Started Jul 01 12:35:17 PM PDT 24
Finished Jul 01 12:35:26 PM PDT 24
Peak memory 218624 kb
Host smart-f97a18ae-6779-4029-9bca-7964dc92ae4b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869848620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_di
gest.869848620
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.721910121
Short name T662
Test name
Test status
Simulation time 1111746256 ps
CPU time 10.36 seconds
Started Jul 01 12:35:14 PM PDT 24
Finished Jul 01 12:35:25 PM PDT 24
Peak memory 218600 kb
Host smart-0731f1b7-32a9-42c0-9404-1d498b0c0a8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721910121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.721910121
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.3823168603
Short name T407
Test name
Test status
Simulation time 1268554685 ps
CPU time 8.42 seconds
Started Jul 01 12:35:09 PM PDT 24
Finished Jul 01 12:35:18 PM PDT 24
Peak memory 225816 kb
Host smart-472d9b93-cc30-479b-a0a5-b9e44de72dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823168603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.3823168603
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.966368966
Short name T63
Test name
Test status
Simulation time 363208317 ps
CPU time 10.53 seconds
Started Jul 01 12:35:10 PM PDT 24
Finished Jul 01 12:35:21 PM PDT 24
Peak memory 218056 kb
Host smart-28b2187d-5179-4f91-a751-7de2eba877a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966368966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.966368966
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.587003204
Short name T316
Test name
Test status
Simulation time 254258710 ps
CPU time 24.09 seconds
Started Jul 01 12:35:10 PM PDT 24
Finished Jul 01 12:35:35 PM PDT 24
Peak memory 251344 kb
Host smart-258ffac6-7f28-4118-8eb4-b81f8039d04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587003204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.587003204
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.1394382944
Short name T622
Test name
Test status
Simulation time 79759827 ps
CPU time 11.19 seconds
Started Jul 01 12:35:10 PM PDT 24
Finished Jul 01 12:35:22 PM PDT 24
Peak memory 251348 kb
Host smart-247c2158-5566-4d98-8b39-62b1021b266d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394382944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.1394382944
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.1513976926
Short name T664
Test name
Test status
Simulation time 7017361172 ps
CPU time 108.89 seconds
Started Jul 01 12:35:15 PM PDT 24
Finished Jul 01 12:37:05 PM PDT 24
Peak memory 226432 kb
Host smart-bfa22aff-72be-4875-9720-aea4c14b678c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513976926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.1513976926
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.3589180438
Short name T491
Test name
Test status
Simulation time 65295709 ps
CPU time 0.86 seconds
Started Jul 01 12:35:09 PM PDT 24
Finished Jul 01 12:35:11 PM PDT 24
Peak memory 209036 kb
Host smart-f2d91b87-2745-4217-9c72-16d361c90687
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589180438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.3589180438
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.2062813095
Short name T469
Test name
Test status
Simulation time 328446485 ps
CPU time 11.39 seconds
Started Jul 01 12:29:52 PM PDT 24
Finished Jul 01 12:30:04 PM PDT 24
Peak memory 226204 kb
Host smart-f5ccdc0d-0194-4b00-a0a7-56deeea159dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062813095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.2062813095
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.1533577922
Short name T429
Test name
Test status
Simulation time 418788981 ps
CPU time 2.8 seconds
Started Jul 01 12:29:55 PM PDT 24
Finished Jul 01 12:29:59 PM PDT 24
Peak memory 217272 kb
Host smart-2b646557-304d-40d6-9509-41c00f3ff44d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533577922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.1533577922
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.2035903702
Short name T799
Test name
Test status
Simulation time 8875870551 ps
CPU time 61.73 seconds
Started Jul 01 12:29:58 PM PDT 24
Finished Jul 01 12:31:00 PM PDT 24
Peak memory 219184 kb
Host smart-01e1a933-a30f-4777-8ba4-cc79c452a7ad
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035903702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.2035903702
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.3044178500
Short name T812
Test name
Test status
Simulation time 221909491 ps
CPU time 6.36 seconds
Started Jul 01 12:30:01 PM PDT 24
Finished Jul 01 12:30:07 PM PDT 24
Peak memory 218064 kb
Host smart-8de8055a-f546-4d53-bb48-4a4d3fa77e4d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044178500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.3
044178500
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.398594274
Short name T232
Test name
Test status
Simulation time 367827468 ps
CPU time 11.82 seconds
Started Jul 01 12:29:57 PM PDT 24
Finished Jul 01 12:30:09 PM PDT 24
Peak memory 218536 kb
Host smart-adba51ca-8296-49b3-930a-7b2ce05f1911
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398594274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_
prog_failure.398594274
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.2317221535
Short name T22
Test name
Test status
Simulation time 6010204732 ps
CPU time 20.08 seconds
Started Jul 01 12:29:55 PM PDT 24
Finished Jul 01 12:30:16 PM PDT 24
Peak memory 218032 kb
Host smart-c6151ecf-fe74-4301-9d1b-a7d1cd2de499
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317221535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.2317221535
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.1619360404
Short name T71
Test name
Test status
Simulation time 626508766 ps
CPU time 9.09 seconds
Started Jul 01 12:29:58 PM PDT 24
Finished Jul 01 12:30:08 PM PDT 24
Peak memory 217972 kb
Host smart-aae2d810-b370-49ab-8db5-29f3e886820e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619360404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
1619360404
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.1648157735
Short name T589
Test name
Test status
Simulation time 4209870835 ps
CPU time 42.75 seconds
Started Jul 01 12:29:55 PM PDT 24
Finished Jul 01 12:30:39 PM PDT 24
Peak memory 269064 kb
Host smart-c009ed27-d8a1-4fbc-b8bc-a6c6db20f3e1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648157735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.1648157735
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.481044886
Short name T386
Test name
Test status
Simulation time 4279029829 ps
CPU time 26.26 seconds
Started Jul 01 12:29:57 PM PDT 24
Finished Jul 01 12:30:24 PM PDT 24
Peak memory 251280 kb
Host smart-d5c15ed2-ed6f-430c-8419-8c95a49ef40f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481044886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_state_post_trans.481044886
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.1828269905
Short name T349
Test name
Test status
Simulation time 453207088 ps
CPU time 2.92 seconds
Started Jul 01 12:29:51 PM PDT 24
Finished Jul 01 12:29:55 PM PDT 24
Peak memory 222732 kb
Host smart-0cf198c5-6e21-4f13-a935-ed1d93dbd387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828269905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.1828269905
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.2685363217
Short name T220
Test name
Test status
Simulation time 4076632643 ps
CPU time 5.21 seconds
Started Jul 01 12:29:52 PM PDT 24
Finished Jul 01 12:29:58 PM PDT 24
Peak memory 218108 kb
Host smart-887bb985-2c96-4d4c-866b-1d1ddde7a446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685363217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.2685363217
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.2839036007
Short name T189
Test name
Test status
Simulation time 697311339 ps
CPU time 18.28 seconds
Started Jul 01 12:29:55 PM PDT 24
Finished Jul 01 12:30:14 PM PDT 24
Peak memory 226404 kb
Host smart-34fec888-6f0e-47a2-8641-649ff8fc7ef7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839036007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.2839036007
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.3225114543
Short name T690
Test name
Test status
Simulation time 406290680 ps
CPU time 8.5 seconds
Started Jul 01 12:30:08 PM PDT 24
Finished Jul 01 12:30:17 PM PDT 24
Peak memory 218556 kb
Host smart-9f9aa3f2-c09b-4934-b4be-2b06f35e789e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225114543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.3225114543
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.509853635
Short name T852
Test name
Test status
Simulation time 404561437 ps
CPU time 9.73 seconds
Started Jul 01 12:29:58 PM PDT 24
Finished Jul 01 12:30:09 PM PDT 24
Peak memory 218568 kb
Host smart-5316c118-d295-4f53-becb-a35e74a62eb3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509853635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.509853635
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.172243367
Short name T86
Test name
Test status
Simulation time 343924211 ps
CPU time 3.01 seconds
Started Jul 01 12:29:44 PM PDT 24
Finished Jul 01 12:29:48 PM PDT 24
Peak memory 218116 kb
Host smart-e388a1f8-1652-4e91-b098-0e01d2456eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172243367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.172243367
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.1563285296
Short name T330
Test name
Test status
Simulation time 674464836 ps
CPU time 21.14 seconds
Started Jul 01 12:29:51 PM PDT 24
Finished Jul 01 12:30:12 PM PDT 24
Peak memory 246428 kb
Host smart-f49e2b14-9ab3-46ee-9834-39d3b11c2258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563285296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.1563285296
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.2959426547
Short name T251
Test name
Test status
Simulation time 1680846340 ps
CPU time 3.49 seconds
Started Jul 01 12:29:57 PM PDT 24
Finished Jul 01 12:30:00 PM PDT 24
Peak memory 222652 kb
Host smart-e9c6f150-3ebe-42dc-981e-dbe7b785c9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959426547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.2959426547
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.4055183444
Short name T199
Test name
Test status
Simulation time 1722091676 ps
CPU time 43.64 seconds
Started Jul 01 12:30:01 PM PDT 24
Finished Jul 01 12:30:46 PM PDT 24
Peak memory 271028 kb
Host smart-49925c5f-fa20-4755-93bd-a4b7bdbf64d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055183444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.4055183444
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.1457880259
Short name T196
Test name
Test status
Simulation time 13821464278 ps
CPU time 532.59 seconds
Started Jul 01 12:30:01 PM PDT 24
Finished Jul 01 12:38:54 PM PDT 24
Peak memory 422436 kb
Host smart-517abf54-1dac-4b59-af52-4e64d98dc741
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1457880259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all_with_rand_reset.1457880259
Directory /workspace/5.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.3283154996
Short name T80
Test name
Test status
Simulation time 24254970 ps
CPU time 1.13 seconds
Started Jul 01 12:29:51 PM PDT 24
Finished Jul 01 12:29:53 PM PDT 24
Peak memory 218096 kb
Host smart-41d118b6-f0a2-4ed7-9e01-59ba16811f16
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283154996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.3283154996
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.2723937084
Short name T840
Test name
Test status
Simulation time 18114883 ps
CPU time 0.92 seconds
Started Jul 01 12:30:29 PM PDT 24
Finished Jul 01 12:30:32 PM PDT 24
Peak memory 209244 kb
Host smart-509b853c-4dfd-4986-bdf0-4ef64b594844
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723937084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.2723937084
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.3373675119
Short name T629
Test name
Test status
Simulation time 35055865 ps
CPU time 1.62 seconds
Started Jul 01 12:30:29 PM PDT 24
Finished Jul 01 12:30:32 PM PDT 24
Peak memory 217352 kb
Host smart-7c643395-f3c3-4c4e-9a80-7a34595f76fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373675119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.3373675119
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.4091040364
Short name T630
Test name
Test status
Simulation time 2341576900 ps
CPU time 35.12 seconds
Started Jul 01 12:30:29 PM PDT 24
Finished Jul 01 12:31:05 PM PDT 24
Peak memory 219264 kb
Host smart-629f8884-8aa1-4132-b007-60fd473919ae
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091040364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.4091040364
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.2548971331
Short name T832
Test name
Test status
Simulation time 614345605 ps
CPU time 4.01 seconds
Started Jul 01 12:30:29 PM PDT 24
Finished Jul 01 12:30:33 PM PDT 24
Peak memory 217748 kb
Host smart-9d25f687-b53e-4e0c-93ac-3a2441f25e89
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548971331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.2
548971331
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.2689491602
Short name T409
Test name
Test status
Simulation time 1040231563 ps
CPU time 7.05 seconds
Started Jul 01 12:30:11 PM PDT 24
Finished Jul 01 12:30:19 PM PDT 24
Peak memory 223268 kb
Host smart-99b9dc37-155f-43e6-b3d8-abf3c1174d53
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689491602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.2689491602
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.4257881098
Short name T640
Test name
Test status
Simulation time 4991842787 ps
CPU time 17.02 seconds
Started Jul 01 12:30:29 PM PDT 24
Finished Jul 01 12:30:48 PM PDT 24
Peak memory 217976 kb
Host smart-f0592c6c-095f-4a45-8f0d-4525a420590c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257881098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.4257881098
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.2876592795
Short name T524
Test name
Test status
Simulation time 417558362 ps
CPU time 6.74 seconds
Started Jul 01 12:30:07 PM PDT 24
Finished Jul 01 12:30:14 PM PDT 24
Peak memory 217996 kb
Host smart-8a7ee8c0-226d-4077-8113-7ae4db5c12c9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876592795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
2876592795
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.1929609053
Short name T35
Test name
Test status
Simulation time 2868234965 ps
CPU time 40.54 seconds
Started Jul 01 12:30:13 PM PDT 24
Finished Jul 01 12:30:54 PM PDT 24
Peak memory 275884 kb
Host smart-64abfb68-e089-4bce-9f44-04d96ab2bc91
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929609053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.1929609053
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.1352724912
Short name T355
Test name
Test status
Simulation time 1355035169 ps
CPU time 20 seconds
Started Jul 01 12:30:12 PM PDT 24
Finished Jul 01 12:30:32 PM PDT 24
Peak memory 226628 kb
Host smart-3783e646-ad5f-4c6b-9d55-9d0aa795d809
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352724912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.1352724912
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.1747256185
Short name T339
Test name
Test status
Simulation time 59668756 ps
CPU time 3.32 seconds
Started Jul 01 12:30:13 PM PDT 24
Finished Jul 01 12:30:17 PM PDT 24
Peak memory 218588 kb
Host smart-02357b96-99af-4803-9627-7bc452e3d615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747256185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.1747256185
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.1043236317
Short name T38
Test name
Test status
Simulation time 195863182 ps
CPU time 10.96 seconds
Started Jul 01 12:30:06 PM PDT 24
Finished Jul 01 12:30:18 PM PDT 24
Peak memory 214988 kb
Host smart-7ccb67b6-6d3f-482c-91b3-9154c92d628b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043236317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.1043236317
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.1802999897
Short name T326
Test name
Test status
Simulation time 1490549310 ps
CPU time 16.19 seconds
Started Jul 01 12:30:17 PM PDT 24
Finished Jul 01 12:30:34 PM PDT 24
Peak memory 226404 kb
Host smart-00414ebd-08ab-498a-aa8c-ef163237504f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802999897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.1802999897
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.3723906187
Short name T722
Test name
Test status
Simulation time 2329422558 ps
CPU time 10.09 seconds
Started Jul 01 12:30:17 PM PDT 24
Finished Jul 01 12:30:28 PM PDT 24
Peak memory 218608 kb
Host smart-ef257b86-6303-4757-9fa0-4f9fb0bb6fa8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723906187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.3723906187
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.2022471017
Short name T393
Test name
Test status
Simulation time 799069866 ps
CPU time 6.22 seconds
Started Jul 01 12:30:19 PM PDT 24
Finished Jul 01 12:30:25 PM PDT 24
Peak memory 218548 kb
Host smart-7fbff95d-b2f4-4705-8db2-cd9d27f89b2b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022471017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.2
022471017
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.3869096892
Short name T679
Test name
Test status
Simulation time 535785503 ps
CPU time 8.35 seconds
Started Jul 01 12:30:05 PM PDT 24
Finished Jul 01 12:30:13 PM PDT 24
Peak memory 226420 kb
Host smart-454a7a8e-2da1-41b5-b4fa-c0f6496f88df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869096892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.3869096892
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.3835740890
Short name T303
Test name
Test status
Simulation time 83892741 ps
CPU time 2.55 seconds
Started Jul 01 12:30:01 PM PDT 24
Finished Jul 01 12:30:04 PM PDT 24
Peak memory 214616 kb
Host smart-e89b010d-7892-4097-8293-01b938d73c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835740890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.3835740890
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.369713716
Short name T808
Test name
Test status
Simulation time 675177860 ps
CPU time 22.86 seconds
Started Jul 01 12:30:07 PM PDT 24
Finished Jul 01 12:30:30 PM PDT 24
Peak memory 251416 kb
Host smart-bad58e2c-6ed0-40b4-953a-828c0cf634e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369713716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.369713716
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.1535846581
Short name T697
Test name
Test status
Simulation time 312945725 ps
CPU time 7.34 seconds
Started Jul 01 12:30:05 PM PDT 24
Finished Jul 01 12:30:13 PM PDT 24
Peak memory 250896 kb
Host smart-86ca2ecb-e2fd-48fc-bb52-c762cad7547f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535846581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.1535846581
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.1108131935
Short name T618
Test name
Test status
Simulation time 16518577589 ps
CPU time 141.17 seconds
Started Jul 01 12:30:29 PM PDT 24
Finished Jul 01 12:32:52 PM PDT 24
Peak memory 259512 kb
Host smart-9585fd49-ec50-46e6-aa7a-bc9be5fca05d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108131935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.1108131935
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.2403628481
Short name T499
Test name
Test status
Simulation time 8055700220 ps
CPU time 236.52 seconds
Started Jul 01 12:30:29 PM PDT 24
Finished Jul 01 12:34:26 PM PDT 24
Peak memory 422340 kb
Host smart-2a55b102-0d98-4ce1-b83d-b955c0266311
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2403628481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.2403628481
Directory /workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.3907373337
Short name T39
Test name
Test status
Simulation time 14242742 ps
CPU time 0.91 seconds
Started Jul 01 12:30:06 PM PDT 24
Finished Jul 01 12:30:07 PM PDT 24
Peak memory 212268 kb
Host smart-bd098412-b0d7-4616-bfa6-0d7375aaa265
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907373337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.3907373337
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.2787971818
Short name T304
Test name
Test status
Simulation time 46167173 ps
CPU time 1.14 seconds
Started Jul 01 12:30:28 PM PDT 24
Finished Jul 01 12:30:30 PM PDT 24
Peak memory 209232 kb
Host smart-79e47a43-23ce-4ff2-b5b5-4fe3fc9141aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787971818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.2787971818
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.77390705
Short name T135
Test name
Test status
Simulation time 16540716 ps
CPU time 0.82 seconds
Started Jul 01 12:30:22 PM PDT 24
Finished Jul 01 12:30:24 PM PDT 24
Peak memory 209348 kb
Host smart-5decaf0c-d464-4260-90c5-5317b9e5a869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77390705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.77390705
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.1401740111
Short name T528
Test name
Test status
Simulation time 414171684 ps
CPU time 8 seconds
Started Jul 01 12:30:22 PM PDT 24
Finished Jul 01 12:30:31 PM PDT 24
Peak memory 218488 kb
Host smart-392a943f-58f0-4821-a3a7-263e47cf0927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401740111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.1401740111
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.786952881
Short name T24
Test name
Test status
Simulation time 297054066 ps
CPU time 2.37 seconds
Started Jul 01 12:30:22 PM PDT 24
Finished Jul 01 12:30:25 PM PDT 24
Peak memory 217488 kb
Host smart-969d1325-5583-4992-be9d-13e15d88a2f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786952881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.786952881
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.3858888506
Short name T445
Test name
Test status
Simulation time 1530958111 ps
CPU time 46.92 seconds
Started Jul 01 12:30:21 PM PDT 24
Finished Jul 01 12:31:08 PM PDT 24
Peak memory 218592 kb
Host smart-ad2f4f26-c7cd-4126-8cb6-1cd68d6304ca
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858888506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.3858888506
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.2637591847
Short name T167
Test name
Test status
Simulation time 285011905 ps
CPU time 4.29 seconds
Started Jul 01 12:30:28 PM PDT 24
Finished Jul 01 12:30:33 PM PDT 24
Peak memory 217824 kb
Host smart-cbd8be1d-9ed4-4fc1-97d9-2aaa4f89b1b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637591847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.2
637591847
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.1226424337
Short name T867
Test name
Test status
Simulation time 1022039870 ps
CPU time 5.12 seconds
Started Jul 01 12:30:21 PM PDT 24
Finished Jul 01 12:30:27 PM PDT 24
Peak memory 218584 kb
Host smart-fec19f2f-03e1-4a5d-9f60-604975a71d27
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226424337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.1226424337
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.1578416387
Short name T807
Test name
Test status
Simulation time 815468331 ps
CPU time 24.62 seconds
Started Jul 01 12:30:29 PM PDT 24
Finished Jul 01 12:30:54 PM PDT 24
Peak memory 217844 kb
Host smart-8d9d9b75-81f2-4d25-bdc3-e50fc2f1d64d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578416387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.1578416387
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.1302463782
Short name T73
Test name
Test status
Simulation time 62892068 ps
CPU time 2.44 seconds
Started Jul 01 12:30:23 PM PDT 24
Finished Jul 01 12:30:26 PM PDT 24
Peak memory 217992 kb
Host smart-d16560f9-d2e5-4e38-a9c9-e2fcd5a79b28
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302463782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
1302463782
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.2851496651
Short name T390
Test name
Test status
Simulation time 995678931 ps
CPU time 34.62 seconds
Started Jul 01 12:30:21 PM PDT 24
Finished Jul 01 12:30:56 PM PDT 24
Peak memory 251316 kb
Host smart-cc585925-3593-4e83-b0ca-e69d405a4f58
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851496651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.2851496651
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.1608704773
Short name T20
Test name
Test status
Simulation time 2102928179 ps
CPU time 16.73 seconds
Started Jul 01 12:30:23 PM PDT 24
Finished Jul 01 12:30:40 PM PDT 24
Peak memory 226616 kb
Host smart-870fdf90-558c-49a1-adb0-5d07d99af0d8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608704773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.1608704773
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.266596774
Short name T580
Test name
Test status
Simulation time 370137496 ps
CPU time 4.02 seconds
Started Jul 01 12:30:22 PM PDT 24
Finished Jul 01 12:30:27 PM PDT 24
Peak memory 218608 kb
Host smart-b5040caa-6761-46dc-9bbd-8bf70aaee5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266596774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.266596774
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.2667173721
Short name T487
Test name
Test status
Simulation time 838091415 ps
CPU time 10.65 seconds
Started Jul 01 12:30:24 PM PDT 24
Finished Jul 01 12:30:35 PM PDT 24
Peak memory 218048 kb
Host smart-75271678-c24a-4831-8d24-dc8e31b7e126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667173721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.2667173721
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.90252203
Short name T805
Test name
Test status
Simulation time 1412570278 ps
CPU time 9.76 seconds
Started Jul 01 12:30:26 PM PDT 24
Finished Jul 01 12:30:36 PM PDT 24
Peak memory 226352 kb
Host smart-88c0c5dd-6431-4bca-9c34-71083fbce037
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90252203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.90252203
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.525301028
Short name T779
Test name
Test status
Simulation time 1004716286 ps
CPU time 10.63 seconds
Started Jul 01 12:30:28 PM PDT 24
Finished Jul 01 12:30:39 PM PDT 24
Peak memory 218540 kb
Host smart-e3cb8f72-dbf9-4106-b82a-02e4fbb71fea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525301028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_dig
est.525301028
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.1031052801
Short name T626
Test name
Test status
Simulation time 1995491667 ps
CPU time 12.22 seconds
Started Jul 01 12:30:27 PM PDT 24
Finished Jul 01 12:30:39 PM PDT 24
Peak memory 218572 kb
Host smart-c72d1e6b-0c02-413e-9a02-ed0c048c9f88
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031052801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.1
031052801
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.3358306924
Short name T376
Test name
Test status
Simulation time 257407396 ps
CPU time 10.47 seconds
Started Jul 01 12:30:21 PM PDT 24
Finished Jul 01 12:30:32 PM PDT 24
Peak memory 226444 kb
Host smart-9dc11a8e-9b7b-4081-bf22-cafd1bd0182f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358306924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.3358306924
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.3080107422
Short name T578
Test name
Test status
Simulation time 86416385 ps
CPU time 2.99 seconds
Started Jul 01 12:30:29 PM PDT 24
Finished Jul 01 12:30:34 PM PDT 24
Peak memory 217980 kb
Host smart-6f03e01f-ca99-4a79-92bd-fed1a81831a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080107422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.3080107422
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.1253045633
Short name T168
Test name
Test status
Simulation time 361493294 ps
CPU time 23.95 seconds
Started Jul 01 12:30:16 PM PDT 24
Finished Jul 01 12:30:41 PM PDT 24
Peak memory 251396 kb
Host smart-9c92d8df-1adc-4331-bf3d-c729b106df59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253045633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.1253045633
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.2318819698
Short name T357
Test name
Test status
Simulation time 917240815 ps
CPU time 7.35 seconds
Started Jul 01 12:30:17 PM PDT 24
Finished Jul 01 12:30:25 PM PDT 24
Peak memory 251332 kb
Host smart-75848a65-18a7-4961-a9a7-25f07877ba35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318819698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.2318819698
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.2357749728
Short name T431
Test name
Test status
Simulation time 12888246887 ps
CPU time 119.99 seconds
Started Jul 01 12:30:28 PM PDT 24
Finished Jul 01 12:32:28 PM PDT 24
Peak memory 272688 kb
Host smart-97b027cd-9a42-4f37-8c58-c1f85b5503c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357749728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.2357749728
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.772507345
Short name T397
Test name
Test status
Simulation time 47034502 ps
CPU time 0.77 seconds
Started Jul 01 12:30:29 PM PDT 24
Finished Jul 01 12:30:31 PM PDT 24
Peak memory 209320 kb
Host smart-6dfa7f3c-88b5-49ff-967d-d24d8dd4ed5a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772507345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctr
l_volatile_unlock_smoke.772507345
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.1479071110
Short name T511
Test name
Test status
Simulation time 43149440 ps
CPU time 0.82 seconds
Started Jul 01 12:30:46 PM PDT 24
Finished Jul 01 12:30:48 PM PDT 24
Peak memory 209168 kb
Host smart-4cb0de2d-1969-404c-934a-087543cab889
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479071110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.1479071110
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.856071084
Short name T223
Test name
Test status
Simulation time 33396288 ps
CPU time 0.91 seconds
Started Jul 01 12:30:36 PM PDT 24
Finished Jul 01 12:30:37 PM PDT 24
Peak memory 209368 kb
Host smart-5dfda0e5-b696-413f-bd24-063da61c1416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856071084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.856071084
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.1827451786
Short name T320
Test name
Test status
Simulation time 1527498138 ps
CPU time 22.38 seconds
Started Jul 01 12:30:32 PM PDT 24
Finished Jul 01 12:30:55 PM PDT 24
Peak memory 218652 kb
Host smart-0a94dfa4-ce6c-4b88-81f1-eddd42de5ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827451786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.1827451786
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.1071212719
Short name T401
Test name
Test status
Simulation time 1262913893 ps
CPU time 9.74 seconds
Started Jul 01 12:30:41 PM PDT 24
Finished Jul 01 12:30:52 PM PDT 24
Peak memory 217780 kb
Host smart-aa085d9d-13e3-4b81-9d3c-18f3926324fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071212719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.1071212719
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.995848006
Short name T405
Test name
Test status
Simulation time 3412995352 ps
CPU time 52.17 seconds
Started Jul 01 12:30:36 PM PDT 24
Finished Jul 01 12:31:29 PM PDT 24
Peak memory 219356 kb
Host smart-d0e7d8d5-ef88-41d2-8d1e-deba2907dcb5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995848006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_err
ors.995848006
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.2611945389
Short name T756
Test name
Test status
Simulation time 6982570103 ps
CPU time 8.47 seconds
Started Jul 01 12:30:43 PM PDT 24
Finished Jul 01 12:30:52 PM PDT 24
Peak memory 218640 kb
Host smart-fd0d024d-3924-457c-98bb-1836abf6096a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611945389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.2611945389
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.2828582840
Short name T88
Test name
Test status
Simulation time 1032203784 ps
CPU time 13.43 seconds
Started Jul 01 12:30:41 PM PDT 24
Finished Jul 01 12:30:55 PM PDT 24
Peak memory 218076 kb
Host smart-1e8c2032-cf99-4e6f-9280-dde2c0e175f5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828582840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.2828582840
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.2808092197
Short name T743
Test name
Test status
Simulation time 476062730 ps
CPU time 3.63 seconds
Started Jul 01 12:30:36 PM PDT 24
Finished Jul 01 12:30:40 PM PDT 24
Peak memory 217988 kb
Host smart-1a673d7f-5624-4dfd-9fc1-8d0b0840594b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808092197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
2808092197
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.3470965828
Short name T267
Test name
Test status
Simulation time 17846516454 ps
CPU time 136.57 seconds
Started Jul 01 12:30:37 PM PDT 24
Finished Jul 01 12:32:54 PM PDT 24
Peak memory 284028 kb
Host smart-a96ed7a5-95eb-4d5d-8200-2f8712c5c8ab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470965828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.3470965828
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.1085233872
Short name T3
Test name
Test status
Simulation time 1237125963 ps
CPU time 20.61 seconds
Started Jul 01 12:30:37 PM PDT 24
Finished Jul 01 12:30:58 PM PDT 24
Peak memory 245720 kb
Host smart-89262b67-f66d-4cfd-a382-6be359fb464c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085233872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.1085233872
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.3400544231
Short name T277
Test name
Test status
Simulation time 211245437 ps
CPU time 1.84 seconds
Started Jul 01 12:30:31 PM PDT 24
Finished Jul 01 12:30:34 PM PDT 24
Peak memory 218636 kb
Host smart-dad50565-5c88-45eb-a97e-85f27255b9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400544231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.3400544231
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.3102563420
Short name T625
Test name
Test status
Simulation time 5388369555 ps
CPU time 10.7 seconds
Started Jul 01 12:30:40 PM PDT 24
Finished Jul 01 12:30:52 PM PDT 24
Peak memory 218268 kb
Host smart-5b08948e-74db-4e29-bc3d-73238dae2b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102563420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.3102563420
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.3360568439
Short name T631
Test name
Test status
Simulation time 1434216714 ps
CPU time 13.99 seconds
Started Jul 01 12:30:43 PM PDT 24
Finished Jul 01 12:30:58 PM PDT 24
Peak memory 226400 kb
Host smart-fa67996b-1836-43f3-b120-eb2b364873a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360568439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.3360568439
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.3683118088
Short name T510
Test name
Test status
Simulation time 741984499 ps
CPU time 10.71 seconds
Started Jul 01 12:30:43 PM PDT 24
Finished Jul 01 12:30:54 PM PDT 24
Peak memory 218576 kb
Host smart-2d8d0172-c429-417e-8373-003306b0b779
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683118088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.3683118088
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.3384780436
Short name T455
Test name
Test status
Simulation time 4962110250 ps
CPU time 15.7 seconds
Started Jul 01 12:30:41 PM PDT 24
Finished Jul 01 12:30:57 PM PDT 24
Peak memory 218548 kb
Host smart-b32275ee-9ef7-4f35-8483-fe6ca0adc32a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384780436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.3
384780436
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.949938311
Short name T601
Test name
Test status
Simulation time 211063794 ps
CPU time 8.96 seconds
Started Jul 01 12:30:31 PM PDT 24
Finished Jul 01 12:30:41 PM PDT 24
Peak memory 225772 kb
Host smart-65271860-f879-4036-8167-9841854b5c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949938311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.949938311
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.864282570
Short name T290
Test name
Test status
Simulation time 56252961 ps
CPU time 1.58 seconds
Started Jul 01 12:30:34 PM PDT 24
Finished Jul 01 12:30:36 PM PDT 24
Peak memory 218044 kb
Host smart-a523b398-cfa8-4bde-a5d5-f400ee30e0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864282570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.864282570
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.170954776
Short name T579
Test name
Test status
Simulation time 355629446 ps
CPU time 17.44 seconds
Started Jul 01 12:30:32 PM PDT 24
Finished Jul 01 12:30:51 PM PDT 24
Peak memory 251236 kb
Host smart-49704acf-55f0-4bf8-9bbd-0043195ccc9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170954776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.170954776
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.2096052647
Short name T180
Test name
Test status
Simulation time 446571232 ps
CPU time 7.39 seconds
Started Jul 01 12:30:32 PM PDT 24
Finished Jul 01 12:30:41 PM PDT 24
Peak memory 251308 kb
Host smart-495fc4e1-d92b-42b3-ae69-b0cb7ed0134b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096052647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.2096052647
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.2623246271
Short name T221
Test name
Test status
Simulation time 2110617708 ps
CPU time 78.88 seconds
Started Jul 01 12:30:43 PM PDT 24
Finished Jul 01 12:32:03 PM PDT 24
Peak memory 216520 kb
Host smart-d3787cf8-4530-4ea8-99f2-bd30141cf296
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623246271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.2623246271
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.3423032200
Short name T158
Test name
Test status
Simulation time 10160371671 ps
CPU time 357.8 seconds
Started Jul 01 12:30:41 PM PDT 24
Finished Jul 01 12:36:39 PM PDT 24
Peak memory 497412 kb
Host smart-3103b01f-4ec0-41d9-972b-3eeb810e0551
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3423032200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.3423032200
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.650810701
Short name T509
Test name
Test status
Simulation time 32945270 ps
CPU time 0.96 seconds
Started Jul 01 12:30:32 PM PDT 24
Finished Jul 01 12:30:34 PM PDT 24
Peak memory 212132 kb
Host smart-e90362d0-96fb-4c13-b6ba-9ab2b444434f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650810701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctr
l_volatile_unlock_smoke.650810701
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.4141344640
Short name T695
Test name
Test status
Simulation time 83540463 ps
CPU time 1.07 seconds
Started Jul 01 12:31:01 PM PDT 24
Finished Jul 01 12:31:03 PM PDT 24
Peak memory 209348 kb
Host smart-9d76910c-58dd-462f-88ef-5e90925de154
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141344640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.4141344640
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.386063655
Short name T394
Test name
Test status
Simulation time 10025155 ps
CPU time 0.91 seconds
Started Jul 01 12:30:51 PM PDT 24
Finished Jul 01 12:30:53 PM PDT 24
Peak memory 209376 kb
Host smart-996728f8-d7fd-4a44-9812-53de75a1d4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386063655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.386063655
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.1176329897
Short name T461
Test name
Test status
Simulation time 367069740 ps
CPU time 17.1 seconds
Started Jul 01 12:30:48 PM PDT 24
Finished Jul 01 12:31:05 PM PDT 24
Peak memory 226348 kb
Host smart-688a00d9-de4c-4462-b595-fca5c51c3ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176329897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.1176329897
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.3688705896
Short name T28
Test name
Test status
Simulation time 2521610008 ps
CPU time 12.03 seconds
Started Jul 01 12:30:50 PM PDT 24
Finished Jul 01 12:31:03 PM PDT 24
Peak memory 217972 kb
Host smart-8cdc0fec-d07c-4095-abcd-d17233fdfa36
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688705896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.3688705896
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.3285036549
Short name T298
Test name
Test status
Simulation time 4991399580 ps
CPU time 65.52 seconds
Started Jul 01 12:31:03 PM PDT 24
Finished Jul 01 12:32:09 PM PDT 24
Peak memory 219268 kb
Host smart-51408dd0-fcec-4921-b95c-261dd7d3e040
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285036549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.3285036549
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.4070849048
Short name T100
Test name
Test status
Simulation time 1359154762 ps
CPU time 4.67 seconds
Started Jul 01 12:30:53 PM PDT 24
Finished Jul 01 12:30:58 PM PDT 24
Peak memory 217980 kb
Host smart-7f0dc01b-5663-4250-88cb-76dffc3ea362
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070849048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.4
070849048
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.123545346
Short name T315
Test name
Test status
Simulation time 323851321 ps
CPU time 11.02 seconds
Started Jul 01 12:30:51 PM PDT 24
Finished Jul 01 12:31:02 PM PDT 24
Peak memory 218556 kb
Host smart-895b007e-974f-4574-965e-e42a76c858e0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123545346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_
prog_failure.123545346
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.2653068109
Short name T792
Test name
Test status
Simulation time 1162128053 ps
CPU time 20.19 seconds
Started Jul 01 12:30:59 PM PDT 24
Finished Jul 01 12:31:20 PM PDT 24
Peak memory 217972 kb
Host smart-160d70e7-e815-42e1-af66-3250e9b6ec41
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653068109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.2653068109
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.1314634158
Short name T103
Test name
Test status
Simulation time 355819597 ps
CPU time 6.87 seconds
Started Jul 01 12:30:54 PM PDT 24
Finished Jul 01 12:31:01 PM PDT 24
Peak memory 217972 kb
Host smart-a17f0f08-c552-4042-be9c-5da75b63f8b2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314634158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
1314634158
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.86295710
Short name T821
Test name
Test status
Simulation time 6780170537 ps
CPU time 43.14 seconds
Started Jul 01 12:30:53 PM PDT 24
Finished Jul 01 12:31:37 PM PDT 24
Peak memory 252388 kb
Host smart-35e9bd86-25bb-418d-8fe9-8fef9ae2d753
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86295710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_
state_failure.86295710
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.3641024817
Short name T532
Test name
Test status
Simulation time 842671400 ps
CPU time 11.44 seconds
Started Jul 01 12:30:53 PM PDT 24
Finished Jul 01 12:31:05 PM PDT 24
Peak memory 250528 kb
Host smart-13a8bc0d-ccf4-44b6-bdf1-c54758d949cc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641024817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.3641024817
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.3853891733
Short name T271
Test name
Test status
Simulation time 58202459 ps
CPU time 2.31 seconds
Started Jul 01 12:30:46 PM PDT 24
Finished Jul 01 12:30:50 PM PDT 24
Peak memory 218596 kb
Host smart-56ad6ce0-630b-4377-b9ba-14835915fa9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853891733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.3853891733
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.1545526072
Short name T768
Test name
Test status
Simulation time 405172308 ps
CPU time 12.48 seconds
Started Jul 01 12:30:48 PM PDT 24
Finished Jul 01 12:31:01 PM PDT 24
Peak memory 218096 kb
Host smart-f40489c6-2152-45f6-ab75-b961436d1c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545526072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.1545526072
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.542734080
Short name T50
Test name
Test status
Simulation time 1009874969 ps
CPU time 13.22 seconds
Started Jul 01 12:31:02 PM PDT 24
Finished Jul 01 12:31:16 PM PDT 24
Peak memory 218604 kb
Host smart-b4a629f9-6902-4d55-b4b0-bfb4cc5f2897
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542734080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.542734080
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.3367924928
Short name T112
Test name
Test status
Simulation time 887790774 ps
CPU time 8.17 seconds
Started Jul 01 12:31:01 PM PDT 24
Finished Jul 01 12:31:10 PM PDT 24
Peak memory 218616 kb
Host smart-0f5549a0-4a89-47c3-98bc-f209b97439f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367924928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.3367924928
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.3410445193
Short name T770
Test name
Test status
Simulation time 310244115 ps
CPU time 12.01 seconds
Started Jul 01 12:30:55 PM PDT 24
Finished Jul 01 12:31:07 PM PDT 24
Peak memory 218568 kb
Host smart-a9983b52-d122-41d1-9e2f-84fc266bba55
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410445193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.3
410445193
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.4284680739
Short name T688
Test name
Test status
Simulation time 2066816706 ps
CPU time 11.67 seconds
Started Jul 01 12:30:50 PM PDT 24
Finished Jul 01 12:31:02 PM PDT 24
Peak memory 226444 kb
Host smart-7402f095-7b56-4042-8dca-2505c45929b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284680739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.4284680739
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.1693503274
Short name T785
Test name
Test status
Simulation time 89084053 ps
CPU time 3.14 seconds
Started Jul 01 12:30:47 PM PDT 24
Finished Jul 01 12:30:51 PM PDT 24
Peak memory 215104 kb
Host smart-61be2ff1-ca11-45d6-8089-ce79779f5494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693503274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.1693503274
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.1334973682
Short name T757
Test name
Test status
Simulation time 1224229830 ps
CPU time 30.15 seconds
Started Jul 01 12:30:50 PM PDT 24
Finished Jul 01 12:31:20 PM PDT 24
Peak memory 251312 kb
Host smart-cb78c5d6-3465-437a-a303-739d10d59415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334973682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.1334973682
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.1318317894
Short name T592
Test name
Test status
Simulation time 184404813 ps
CPU time 3.61 seconds
Started Jul 01 12:30:50 PM PDT 24
Finished Jul 01 12:30:54 PM PDT 24
Peak memory 226760 kb
Host smart-5457eedb-aedd-4858-8cde-a65b68a3a5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318317894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.1318317894
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.2768785504
Short name T323
Test name
Test status
Simulation time 329637345 ps
CPU time 5.71 seconds
Started Jul 01 12:31:01 PM PDT 24
Finished Jul 01 12:31:08 PM PDT 24
Peak memory 226708 kb
Host smart-f30dcce8-c279-43b3-8ee6-d969e5425bdc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768785504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.2768785504
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.2158319218
Short name T160
Test name
Test status
Simulation time 23252323413 ps
CPU time 410.22 seconds
Started Jul 01 12:31:01 PM PDT 24
Finished Jul 01 12:37:52 PM PDT 24
Peak memory 309856 kb
Host smart-641d521a-551e-42b6-835e-e2bf63d3ba86
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2158319218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all_with_rand_reset.2158319218
Directory /workspace/9.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.1084727562
Short name T241
Test name
Test status
Simulation time 37699510 ps
CPU time 1.24 seconds
Started Jul 01 12:30:50 PM PDT 24
Finished Jul 01 12:30:51 PM PDT 24
Peak memory 212400 kb
Host smart-39bb9888-b8a7-4840-973d-aeb4957576e6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084727562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.1084727562
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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