Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50644 |
1 |
|
|
T1 |
59 |
|
T2 |
11 |
|
T3 |
16 |
auto[1] |
1758 |
1 |
|
|
T36 |
5 |
|
T37 |
33 |
|
T38 |
8 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51692 |
1 |
|
|
T1 |
59 |
|
T2 |
11 |
|
T3 |
16 |
auto[1] |
710 |
1 |
|
|
T9 |
17 |
|
T45 |
15 |
|
T40 |
15 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50498 |
1 |
|
|
T1 |
59 |
|
T2 |
10 |
|
T3 |
16 |
auto[1] |
1904 |
1 |
|
|
T2 |
1 |
|
T4 |
18 |
|
T70 |
1 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50576 |
1 |
|
|
T1 |
59 |
|
T2 |
11 |
|
T3 |
16 |
auto[1] |
1826 |
1 |
|
|
T4 |
5 |
|
T44 |
8 |
|
T31 |
8 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50562 |
1 |
|
|
T1 |
59 |
|
T2 |
11 |
|
T3 |
16 |
auto[1] |
1840 |
1 |
|
|
T4 |
9 |
|
T44 |
7 |
|
T30 |
1 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
47600 |
1 |
|
|
T1 |
59 |
|
T2 |
2 |
|
T3 |
16 |
no_err_inj |
4802 |
1 |
|
|
T2 |
9 |
|
T4 |
56 |
|
T5 |
8 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50601 |
1 |
|
|
T1 |
59 |
|
T2 |
11 |
|
T3 |
16 |
auto[1] |
1801 |
1 |
|
|
T36 |
10 |
|
T37 |
31 |
|
T38 |
6 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51650 |
1 |
|
|
T1 |
59 |
|
T2 |
11 |
|
T3 |
16 |
auto[1] |
752 |
1 |
|
|
T9 |
21 |
|
T45 |
11 |
|
T40 |
14 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
36930 |
1 |
|
|
T1 |
59 |
|
T3 |
16 |
|
T9 |
94 |
auto[1] |
15472 |
1 |
|
|
T2 |
11 |
|
T4 |
32 |
|
T5 |
8 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50505 |
1 |
|
|
T1 |
59 |
|
T2 |
10 |
|
T3 |
16 |
auto[1] |
1897 |
1 |
|
|
T2 |
1 |
|
T4 |
5 |
|
T44 |
17 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50573 |
1 |
|
|
T1 |
59 |
|
T2 |
11 |
|
T3 |
16 |
auto[1] |
1829 |
1 |
|
|
T4 |
9 |
|
T44 |
10 |
|
T15 |
1 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50560 |
1 |
|
|
T1 |
59 |
|
T2 |
11 |
|
T3 |
16 |
auto[1] |
1842 |
1 |
|
|
T4 |
6 |
|
T43 |
2 |
|
T44 |
8 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50651 |
1 |
|
|
T1 |
59 |
|
T2 |
11 |
|
T3 |
16 |
auto[1] |
1751 |
1 |
|
|
T36 |
13 |
|
T37 |
26 |
|
T38 |
8 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50289 |
1 |
|
|
T1 |
59 |
|
T2 |
11 |
|
T9 |
94 |
auto[1] |
2113 |
1 |
|
|
T3 |
16 |
|
T11 |
14 |
|
T16 |
17 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51641 |
1 |
|
|
T1 |
59 |
|
T2 |
11 |
|
T3 |
16 |
auto[1] |
761 |
1 |
|
|
T9 |
18 |
|
T45 |
10 |
|
T40 |
15 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51650 |
1 |
|
|
T1 |
59 |
|
T2 |
11 |
|
T3 |
16 |
auto[1] |
752 |
1 |
|
|
T9 |
18 |
|
T45 |
18 |
|
T40 |
22 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51658 |
1 |
|
|
T1 |
59 |
|
T2 |
11 |
|
T3 |
16 |
auto[1] |
744 |
1 |
|
|
T9 |
20 |
|
T45 |
11 |
|
T40 |
16 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49764 |
1 |
|
|
T1 |
59 |
|
T3 |
16 |
|
T9 |
94 |
auto[1] |
2638 |
1 |
|
|
T2 |
11 |
|
T4 |
23 |
|
T70 |
15 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48608 |
1 |
|
|
T2 |
11 |
|
T3 |
16 |
|
T9 |
94 |
auto[1] |
3794 |
1 |
|
|
T1 |
59 |
|
T10 |
79 |
|
T12 |
77 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50591 |
1 |
|
|
T1 |
59 |
|
T2 |
11 |
|
T3 |
16 |
auto[1] |
1811 |
1 |
|
|
T4 |
4 |
|
T70 |
1 |
|
T44 |
5 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50623 |
1 |
|
|
T1 |
59 |
|
T2 |
11 |
|
T3 |
16 |
auto[1] |
1779 |
1 |
|
|
T4 |
11 |
|
T44 |
10 |
|
T31 |
4 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50542 |
1 |
|
|
T1 |
59 |
|
T2 |
11 |
|
T3 |
16 |
auto[1] |
1860 |
1 |
|
|
T4 |
7 |
|
T70 |
2 |
|
T44 |
8 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50672 |
1 |
|
|
T1 |
59 |
|
T2 |
11 |
|
T3 |
16 |
auto[1] |
1730 |
1 |
|
|
T36 |
15 |
|
T37 |
38 |
|
T38 |
13 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46911 |
1 |
|
|
T1 |
59 |
|
T2 |
11 |
|
T3 |
16 |
auto[1] |
5491 |
1 |
|
|
T42 |
76 |
|
T36 |
9 |
|
T37 |
28 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48625 |
1 |
|
|
T1 |
59 |
|
T2 |
11 |
|
T3 |
16 |
auto[1] |
3777 |
1 |
|
|
T46 |
52 |
|
T56 |
51 |
|
T68 |
73 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52402 |
1 |
|
|
T1 |
59 |
|
T2 |
11 |
|
T3 |
16 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50643 |
1 |
|
|
T1 |
59 |
|
T2 |
11 |
|
T3 |
16 |
auto[1] |
1759 |
1 |
|
|
T36 |
7 |
|
T37 |
29 |
|
T38 |
7 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50735 |
1 |
|
|
T1 |
59 |
|
T2 |
11 |
|
T3 |
16 |
auto[1] |
1667 |
1 |
|
|
T36 |
13 |
|
T37 |
39 |
|
T38 |
6 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50750 |
1 |
|
|
T1 |
59 |
|
T2 |
11 |
|
T3 |
16 |
auto[1] |
1652 |
1 |
|
|
T36 |
7 |
|
T37 |
28 |
|
T38 |
4 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
46310 |
1 |
|
|
T1 |
59 |
|
T3 |
16 |
|
T9 |
94 |
auto[0] |
no_err_inj |
3454 |
1 |
|
|
T4 |
42 |
|
T5 |
8 |
|
T29 |
22 |
auto[1] |
err_inj |
1290 |
1 |
|
|
T2 |
2 |
|
T4 |
9 |
|
T70 |
4 |
auto[1] |
no_err_inj |
1348 |
1 |
|
|
T2 |
9 |
|
T4 |
14 |
|
T70 |
11 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48133 |
1 |
|
|
T1 |
59 |
|
T3 |
16 |
|
T9 |
94 |
auto[0] |
auto[1] |
1631 |
1 |
|
|
T4 |
9 |
|
T44 |
10 |
|
T31 |
4 |
auto[1] |
auto[0] |
2490 |
1 |
|
|
T2 |
11 |
|
T4 |
21 |
|
T70 |
15 |
auto[1] |
auto[1] |
148 |
1 |
|
|
T4 |
2 |
|
T39 |
1 |
|
T41 |
1 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48086 |
1 |
|
|
T1 |
59 |
|
T3 |
16 |
|
T9 |
94 |
auto[0] |
auto[1] |
1678 |
1 |
|
|
T4 |
7 |
|
T44 |
10 |
|
T31 |
8 |
auto[1] |
auto[0] |
2487 |
1 |
|
|
T2 |
11 |
|
T4 |
21 |
|
T70 |
15 |
auto[1] |
auto[1] |
151 |
1 |
|
|
T4 |
2 |
|
T15 |
1 |
|
T39 |
3 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48045 |
1 |
|
|
T1 |
59 |
|
T3 |
16 |
|
T9 |
94 |
auto[0] |
auto[1] |
1719 |
1 |
|
|
T4 |
7 |
|
T44 |
8 |
|
T31 |
4 |
auto[1] |
auto[0] |
2497 |
1 |
|
|
T2 |
11 |
|
T4 |
23 |
|
T70 |
13 |
auto[1] |
auto[1] |
141 |
1 |
|
|
T70 |
2 |
|
T15 |
2 |
|
T30 |
1 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48077 |
1 |
|
|
T1 |
59 |
|
T3 |
16 |
|
T9 |
94 |
auto[0] |
auto[1] |
1687 |
1 |
|
|
T4 |
5 |
|
T44 |
8 |
|
T31 |
8 |
auto[1] |
auto[0] |
2499 |
1 |
|
|
T2 |
11 |
|
T4 |
23 |
|
T70 |
15 |
auto[1] |
auto[1] |
139 |
1 |
|
|
T41 |
1 |
|
T218 |
1 |
|
T219 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48066 |
1 |
|
|
T1 |
59 |
|
T3 |
16 |
|
T9 |
94 |
auto[0] |
auto[1] |
1698 |
1 |
|
|
T4 |
8 |
|
T44 |
7 |
|
T31 |
9 |
auto[1] |
auto[0] |
2496 |
1 |
|
|
T2 |
11 |
|
T4 |
22 |
|
T70 |
15 |
auto[1] |
auto[1] |
142 |
1 |
|
|
T4 |
1 |
|
T30 |
1 |
|
T39 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
47981 |
1 |
|
|
T1 |
59 |
|
T3 |
16 |
|
T9 |
94 |
auto[0] |
auto[1] |
1783 |
1 |
|
|
T4 |
15 |
|
T44 |
4 |
|
T31 |
6 |
auto[1] |
auto[0] |
2517 |
1 |
|
|
T2 |
10 |
|
T4 |
20 |
|
T70 |
14 |
auto[1] |
auto[1] |
121 |
1 |
|
|
T2 |
1 |
|
T4 |
3 |
|
T70 |
1 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35806 |
1 |
|
|
T1 |
59 |
|
T3 |
16 |
|
T9 |
94 |
auto[0] |
auto[1] |
1124 |
1 |
|
|
T36 |
5 |
|
T37 |
21 |
|
T38 |
8 |
auto[1] |
auto[0] |
14838 |
1 |
|
|
T2 |
11 |
|
T4 |
32 |
|
T5 |
8 |
auto[1] |
auto[1] |
634 |
1 |
|
|
T37 |
12 |
|
T47 |
14 |
|
T48 |
9 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35792 |
1 |
|
|
T1 |
59 |
|
T3 |
16 |
|
T9 |
94 |
auto[0] |
auto[1] |
1138 |
1 |
|
|
T36 |
10 |
|
T37 |
15 |
|
T38 |
6 |
auto[1] |
auto[0] |
14809 |
1 |
|
|
T2 |
11 |
|
T4 |
32 |
|
T5 |
8 |
auto[1] |
auto[1] |
663 |
1 |
|
|
T37 |
16 |
|
T47 |
8 |
|
T48 |
13 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35716 |
1 |
|
|
T1 |
59 |
|
T9 |
94 |
|
T4 |
98 |
auto[0] |
auto[1] |
1214 |
1 |
|
|
T3 |
16 |
|
T11 |
14 |
|
T41 |
14 |
auto[1] |
auto[0] |
14573 |
1 |
|
|
T2 |
11 |
|
T4 |
32 |
|
T5 |
8 |
auto[1] |
auto[1] |
899 |
1 |
|
|
T16 |
17 |
|
T220 |
9 |
|
T221 |
9 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35831 |
1 |
|
|
T1 |
59 |
|
T3 |
16 |
|
T9 |
94 |
auto[0] |
auto[1] |
1099 |
1 |
|
|
T36 |
13 |
|
T37 |
15 |
|
T38 |
8 |
auto[1] |
auto[0] |
14820 |
1 |
|
|
T2 |
11 |
|
T4 |
32 |
|
T5 |
8 |
auto[1] |
auto[1] |
652 |
1 |
|
|
T37 |
11 |
|
T47 |
14 |
|
T48 |
11 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
32110 |
1 |
|
|
T1 |
59 |
|
T3 |
16 |
|
T9 |
94 |
auto[0] |
auto[1] |
4820 |
1 |
|
|
T42 |
76 |
|
T36 |
9 |
|
T37 |
11 |
auto[1] |
auto[0] |
14801 |
1 |
|
|
T2 |
11 |
|
T4 |
32 |
|
T5 |
8 |
auto[1] |
auto[1] |
671 |
1 |
|
|
T37 |
17 |
|
T47 |
13 |
|
T48 |
13 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35920 |
1 |
|
|
T1 |
59 |
|
T3 |
16 |
|
T9 |
94 |
auto[0] |
auto[1] |
1010 |
1 |
|
|
T4 |
11 |
|
T44 |
10 |
|
T32 |
8 |
auto[1] |
auto[0] |
14703 |
1 |
|
|
T2 |
11 |
|
T4 |
32 |
|
T5 |
8 |
auto[1] |
auto[1] |
769 |
1 |
|
|
T31 |
4 |
|
T39 |
1 |
|
T41 |
14 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35930 |
1 |
|
|
T1 |
59 |
|
T3 |
16 |
|
T9 |
94 |
auto[0] |
auto[1] |
1000 |
1 |
|
|
T4 |
4 |
|
T70 |
1 |
|
T44 |
5 |
auto[1] |
auto[0] |
14661 |
1 |
|
|
T2 |
11 |
|
T4 |
32 |
|
T5 |
8 |
auto[1] |
auto[1] |
811 |
1 |
|
|
T15 |
1 |
|
T31 |
9 |
|
T39 |
2 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35899 |
1 |
|
|
T1 |
59 |
|
T3 |
16 |
|
T9 |
94 |
auto[0] |
auto[1] |
1031 |
1 |
|
|
T4 |
9 |
|
T44 |
10 |
|
T32 |
7 |
auto[1] |
auto[0] |
14674 |
1 |
|
|
T2 |
11 |
|
T4 |
32 |
|
T5 |
8 |
auto[1] |
auto[1] |
798 |
1 |
|
|
T15 |
1 |
|
T31 |
8 |
|
T39 |
3 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35858 |
1 |
|
|
T1 |
59 |
|
T3 |
16 |
|
T9 |
94 |
auto[0] |
auto[1] |
1072 |
1 |
|
|
T4 |
5 |
|
T44 |
17 |
|
T30 |
1 |
auto[1] |
auto[0] |
14647 |
1 |
|
|
T2 |
10 |
|
T4 |
32 |
|
T5 |
8 |
auto[1] |
auto[1] |
825 |
1 |
|
|
T2 |
1 |
|
T31 |
5 |
|
T41 |
14 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35881 |
1 |
|
|
T1 |
59 |
|
T3 |
16 |
|
T9 |
94 |
auto[0] |
auto[1] |
1049 |
1 |
|
|
T4 |
5 |
|
T44 |
8 |
|
T32 |
10 |
auto[1] |
auto[0] |
14695 |
1 |
|
|
T2 |
11 |
|
T4 |
32 |
|
T5 |
8 |
auto[1] |
auto[1] |
777 |
1 |
|
|
T31 |
8 |
|
T41 |
18 |
|
T37 |
14 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35846 |
1 |
|
|
T1 |
59 |
|
T3 |
16 |
|
T9 |
94 |
auto[0] |
auto[1] |
1084 |
1 |
|
|
T4 |
18 |
|
T70 |
1 |
|
T43 |
1 |
auto[1] |
auto[0] |
14652 |
1 |
|
|
T2 |
10 |
|
T4 |
32 |
|
T5 |
8 |
auto[1] |
auto[1] |
820 |
1 |
|
|
T2 |
1 |
|
T15 |
2 |
|
T31 |
6 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35887 |
1 |
|
|
T1 |
59 |
|
T3 |
16 |
|
T9 |
94 |
auto[0] |
auto[1] |
1043 |
1 |
|
|
T36 |
7 |
|
T37 |
12 |
|
T38 |
4 |
auto[1] |
auto[0] |
14863 |
1 |
|
|
T2 |
11 |
|
T4 |
32 |
|
T5 |
8 |
auto[1] |
auto[1] |
609 |
1 |
|
|
T37 |
16 |
|
T47 |
15 |
|
T48 |
12 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35861 |
1 |
|
|
T1 |
59 |
|
T3 |
16 |
|
T9 |
94 |
auto[0] |
auto[1] |
1069 |
1 |
|
|
T36 |
13 |
|
T37 |
23 |
|
T38 |
6 |
auto[1] |
auto[0] |
14874 |
1 |
|
|
T2 |
11 |
|
T4 |
32 |
|
T5 |
8 |
auto[1] |
auto[1] |
598 |
1 |
|
|
T37 |
16 |
|
T47 |
14 |
|
T48 |
10 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35427 |
1 |
|
|
T1 |
59 |
|
T3 |
16 |
|
T9 |
94 |
auto[0] |
auto[1] |
1503 |
1 |
|
|
T4 |
23 |
|
T70 |
15 |
|
T43 |
11 |
auto[1] |
auto[0] |
14337 |
1 |
|
|
T4 |
32 |
|
T5 |
8 |
|
T16 |
17 |
auto[1] |
auto[1] |
1135 |
1 |
|
|
T2 |
11 |
|
T15 |
14 |
|
T39 |
13 |