Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

104011076

1

T1

16539

T2

31796

T3

6874

auto[1]

1376280

1

T1

7139

T2

98

T3

693

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

104009256

1

T1

16375

T2

31796

T3

6676

auto[1]

1378100

1

T1

7303

T2

98

T3

891

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7322322	1			T1	5561		T2	1020		T3	1561
auto[IdleSt]	22288170	1			T1	4855		T2	10999		T3	2159
auto[ClkMuxSt]	34650	1			T1	48		T2	9		T3	16
auto[CntIncrSt]	34385	1			T1	46		T2	9		T3	16
auto[CntProgSt]	2082500	1			T1	1279		T2	97		T3	293
auto[TransCheckSt]	27049	1			T1	28		T2	9		T9	59
auto[TokenHashSt]	39902780	1			T1	433		T2	209		T9	4158
auto[FlashRmaSt]	27845	1			T1	59		T2	19		T9	172
auto[TokenCheck0St]	12709	1			T1	21		T2	9		T9	50
auto[TokenCheck1St]	9368	1			T1	20		T2	9		T9	32
auto[TransProgSt]	622113	1			T1	58		T2	118		T9	60
auto[PostTransSt]	13074849	1			T1	5		T2	14744		T3	1230
auto[ScrapSt]	203753	1			T4	4414		T10	6		T13	6
auto[EscalateSt]	7030804	1			T1	11265		T2	2604		T3	2292
auto[InvalidSt]	12712157	1			T2	2039		T9	3568		T4	11036

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1902	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	12712157	1			T2	2039		T9	3568		T4	11036
EscalateSt	7030804	1			T1	11265		T2	2604		T3	2292
ScrapSt	203753	1			T4	4414		T10	6		T13	6
PostTransSt	13074849	1			T1	5		T2	14744		T3	1230
TransProgSt	622113	1			T1	58		T2	118		T9	60
TokenCheck1St	9368	1			T1	20		T2	9		T9	32
TokenCheck0St	12709	1			T1	21		T2	9		T9	50
FlashRmaSt	27845	1			T1	59		T2	19		T9	172
TokenHashSt	39902780	1			T1	433		T2	209		T9	4158
TransCheckSt	27049	1			T1	28		T2	9		T9	59
CntProgSt	2082500	1			T1	1279		T2	97		T3	293
CntIncrSt	34385	1			T1	46		T2	9		T3	16
ClkMuxSt	34650	1			T1	48		T2	9		T3	16
IdleSt	22288170	1			T1	4855		T2	10999		T3	2159
ResetSt	7322322	1			T1	5561		T2	1020		T3	1561
arcs[ResetSt=>IdleSt]	52672	1			T1	55		T2	12		T3	17
arcs[IdleSt=>ScrapSt]	291	1			T4	3		T10	2		T13	2
arcs[IdleSt=>ClkMuxSt]	34452	1			T1	48		T2	9		T3	16
arcs[ClkMuxSt=>CntIncrSt]	34385	1			T1	46		T2	9		T3	16
arcs[CntIncrSt=>PostTransSt]	1669	1			T36	13		T37	39		T38	6
arcs[CntIncrSt=>CntProgSt]	32643	1			T1	46		T2	9		T3	16
arcs[CntProgSt=>PostTransSt]	4553	1			T3	16		T9	17		T11	14
arcs[CntProgSt=>TransCheckSt]	27049	1			T1	28		T2	9		T9	59
arcs[TransCheckSt=>PostTransSt]	3488	1			T46	24		T36	7		T56	27
arcs[TransCheckSt=>TokenHashSt]	23418	1			T1	28		T2	9		T9	59
arcs[TokenHashSt=>PostTransSt]	9884	1			T9	9		T45	6		T46	11
arcs[TokenHashSt=>FlashRmaSt]	12796	1			T1	21		T2	9		T9	50
arcs[FlashRmaSt=>TokenCheck0St]	12709	1			T1	21		T2	9		T9	50
arcs[TokenCheck0St=>PostTransSt]	3299	1			T9	18		T45	9		T46	12
arcs[TokenCheck0St=>TokenCheck1St]	9368	1			T1	20		T2	9		T9	32
arcs[TokenCheck1St=>PostTransSt]	632	1			T9	1		T45	1		T46	5
arcs[TransProgSt=>PostTransSt]	7891	1			T1	2		T2	9		T9	31
arcs[IdleSt=>EscalateSt]	213	1			T1	6		T57	2		T58	12
arcs[ClkMuxSt=>EscalateSt]	67	1			T1	2		T12	3		T13	1
arcs[CntIncrSt=>EscalateSt]	73	1			T10	1		T12	1		T57	3
arcs[CntProgSt=>EscalateSt]	1041	1			T1	18		T10	6		T12	33
arcs[TransCheckSt=>EscalateSt]	143	1			T10	8		T13	5		T20	4
arcs[TokenHashSt=>EscalateSt]	738	1			T1	7		T10	31		T12	14
arcs[FlashRmaSt=>EscalateSt]	87	1			T10	1		T13	1		T20	1
arcs[TokenCheck0St=>EscalateSt]	42	1			T1	1		T13	1		T62	1
arcs[TokenCheck1St=>EscalateSt]	154	1			T1	1		T10	5		T12	3
arcs[TransProgSt=>EscalateSt]	691	1			T1	17		T10	14		T12	18
arcs[PostTransSt=>EscalateSt]	4814	1			T1	2		T3	16		T9	17
arcs[InvalidSt=>EscalateSt]	13654	1			T2	2		T9	18		T4	61

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7322155	1			T1	5557		T2	1020		T3	1561
auto[0]	auto[IdleSt]	22288032	1			T1	4853		T2	10999		T3	2159
auto[0]	auto[ClkMuxSt]	34602	1			T1	47		T2	9		T3	16
auto[0]	auto[CntIncrSt]	34341	1			T1	46		T2	9		T3	16
auto[0]	auto[CntProgSt]	2081779	1			T1	1268		T2	97		T3	293
auto[0]	auto[TransCheckSt]	26960	1			T1	28		T2	9		T9	59
auto[0]	auto[TokenHashSt]	39902304	1			T1	429		T2	209		T9	4158
auto[0]	auto[FlashRmaSt]	27784	1			T1	59		T2	19		T9	172
auto[0]	auto[TokenCheck0St]	12682	1			T1	20		T2	9		T9	50
auto[0]	auto[TokenCheck1St]	9276	1			T1	20		T2	9		T9	32
auto[0]	auto[TransProgSt]	621660	1			T1	46		T2	118		T9	60
auto[0]	auto[PostTransSt]	13072360	1			T1	3		T2	14744		T3	1223
auto[0]	auto[ScrapSt]	203709	1			T4	4414		T10	4		T13	5
auto[0]	auto[EscalateSt]	5666148	1			T1	4163		T2	2507		T3	1606
auto[0]	auto[InvalidSt]	12705382	1			T2	2038		T9	3555		T4	11007
auto[1]	auto[ResetSt]	167	1			T1	4		T10	1		T12	1
auto[1]	auto[IdleSt]	138	1			T1	2		T57	1		T58	9
auto[1]	auto[ClkMuxSt]	48	1			T1	1		T12	2		T13	1
auto[1]	auto[CntIncrSt]	44	1			T10	1		T57	1		T58	1
auto[1]	auto[CntProgSt]	721	1			T1	11		T10	6		T12	19
auto[1]	auto[TransCheckSt]	89	1			T10	8		T13	4		T20	2
auto[1]	auto[TokenHashSt]	476	1			T1	4		T10	21		T12	10
auto[1]	auto[FlashRmaSt]	61	1			T10	1		T13	1		T57	2
auto[1]	auto[TokenCheck0St]	27	1			T1	1		T13	1		T62	1
auto[1]	auto[TokenCheck1St]	92	1			T10	3		T12	2		T13	3
auto[1]	auto[TransProgSt]	453	1			T1	12		T10	9		T12	8
auto[1]	auto[PostTransSt]	2489	1			T1	2		T3	7		T9	11
auto[1]	auto[ScrapSt]	44	1			T10	2		T13	1		T20	2
auto[1]	auto[EscalateSt]	1364656	1			T1	7102		T2	97		T3	686
auto[1]	auto[InvalidSt]	6775	1			T2	1		T9	13		T4	29

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7322159	1			T1	5558		T2	1020		T3	1561
auto[0]	auto[IdleSt]	22288025	1			T1	4851		T2	10999		T3	2159
auto[0]	auto[ClkMuxSt]	34612	1			T1	47		T2	9		T3	16
auto[0]	auto[CntIncrSt]	34338	1			T1	46		T2	9		T3	16
auto[0]	auto[CntProgSt]	2081836	1			T1	1265		T2	97		T3	293
auto[0]	auto[TransCheckSt]	26954	1			T1	28		T2	9		T9	59
auto[0]	auto[TokenHashSt]	39902279	1			T1	427		T2	209		T9	4158
auto[0]	auto[FlashRmaSt]	27787	1			T1	59		T2	19		T9	172
auto[0]	auto[TokenCheck0St]	12677	1			T1	21		T2	9		T9	50
auto[0]	auto[TokenCheck1St]	9260	1			T1	19		T2	9		T9	32
auto[0]	auto[TransProgSt]	621641	1			T1	49		T2	118		T9	60
auto[0]	auto[PostTransSt]	13072438	1			T1	5		T2	14744		T3	1221
auto[0]	auto[ScrapSt]	203706	1			T4	4414		T10	6		T13	4
auto[0]	auto[EscalateSt]	5664364	1			T1	4000		T2	2507		T3	1410
auto[0]	auto[InvalidSt]	12705278	1			T2	2038		T9	3563		T4	11004
auto[1]	auto[ResetSt]	163	1			T1	3		T10	2		T12	2
auto[1]	auto[IdleSt]	145	1			T1	4		T57	1		T58	7
auto[1]	auto[ClkMuxSt]	38	1			T1	1		T12	2		T13	1
auto[1]	auto[CntIncrSt]	47	1			T10	1		T12	1		T57	3
auto[1]	auto[CntProgSt]	664	1			T1	14		T12	26		T13	21
auto[1]	auto[TransCheckSt]	95	1			T10	1		T13	4		T20	3
auto[1]	auto[TokenHashSt]	501	1			T1	6		T10	21		T12	10
auto[1]	auto[FlashRmaSt]	58	1			T20	1		T57	1		T62	1
auto[1]	auto[TokenCheck0St]	32	1			T62	1		T215	3		T216	1
auto[1]	auto[TokenCheck1St]	108	1			T1	1		T10	4		T12	2
auto[1]	auto[TransProgSt]	472	1			T1	9		T10	10		T12	14
auto[1]	auto[PostTransSt]	2411	1			T3	9		T9	6		T10	7
auto[1]	auto[ScrapSt]	47	1			T13	2		T20	1		T217	1
auto[1]	auto[EscalateSt]	1366440	1			T1	7265		T2	97		T3	882
auto[1]	auto[InvalidSt]	6879	1			T2	1		T9	5		T4	32