Unified Coverage Report :: Tests

Tests

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Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.93	97.99	95.77	93.38	97.67	98.55	99.00	96.11

Total test records in report: 1003

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html

T1001	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.428957173			Jul 01 04:57:27 PM PDT 24	Jul 01 04:57:38 PM PDT 24	420430371 ps
T1002	/workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.4128029754			Jul 01 04:57:47 PM PDT 24	Jul 01 04:57:58 PM PDT 24	79441951 ps
T1003	/workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3657466976			Jul 01 04:57:45 PM PDT 24	Jul 01 04:57:54 PM PDT 24	50629588 ps

Test location	/workspace/coverage/default/10.lc_ctrl_stress_all.2019404348
Short name	T4
Test name
Test status
Simulation time	5605062536 ps
CPU time	210.38 seconds
Started	Jul 01 06:45:03 PM PDT 24
Finished	Jul 01 06:48:35 PM PDT 24
Peak memory	251672 kb
Host	smart-25ac30ce-38d6-49b5-84c4-f8882f2c0975
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019404348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all.2019404348
Directory	/workspace/10.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/12.lc_ctrl_security_escalation.606327975
Short name	T13
Test name
Test status
Simulation time	1012616026 ps
CPU time	10.41 seconds
Started	Jul 01 06:45:21 PM PDT 24
Finished	Jul 01 06:45:35 PM PDT 24
Peak memory	226452 kb
Host	smart-4816083e-6505-4d42-9777-6e877fcc309c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=606327975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.606327975
Directory	/workspace/12.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.3034817173
Short name	T37
Test name
Test status
Simulation time	44209885058 ps
CPU time	357.72 seconds
Started	Jul 01 06:46:00 PM PDT 24
Finished	Jul 01 06:51:59 PM PDT 24
Peak memory	283864 kb
Host	smart-f933ae8e-7ac8-4b06-9119-d0a536d570e1
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3034817173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all_with_rand_reset.3034817173
Directory	/workspace/21.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/18.lc_ctrl_sec_mubi.2659231029
Short name	T9
Test name
Test status
Simulation time	1630017653 ps
CPU time	14.02 seconds
Started	Jul 01 06:45:43 PM PDT 24
Finished	Jul 01 06:46:02 PM PDT 24
Peak memory	226504 kb
Host	smart-2ba4f75f-1e86-4991-99c5-67927061156c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659231029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.2659231029
Directory	/workspace/18.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.2175967514
Short name	T52
Test name
Test status
Simulation time	8800331142 ps
CPU time	224.2 seconds
Started	Jul 01 06:44:18 PM PDT 24
Finished	Jul 01 06:48:06 PM PDT 24
Peak memory	268248 kb
Host	smart-a0b9e0aa-1dc3-45b5-90ae-2fef5b0c0270
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2175967514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all_with_rand_reset.2175967514
Directory	/workspace/5.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.3465233669
Short name	T28
Test name
Test status
Simulation time	59898081 ps
CPU time	0.9 seconds
Started	Jul 01 06:44:19 PM PDT 24
Finished	Jul 01 06:44:23 PM PDT 24
Peak memory	209292 kb
Host	smart-4f6521d5-7db7-42d1-9287-e9e8b76cb414
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465233669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct rl_volatile_unlock_smoke.3465233669
Directory	/workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/2.lc_ctrl_security_escalation.3370955308
Short name	T58
Test name
Test status
Simulation time	358072340 ps
CPU time	12.89 seconds
Started	Jul 01 06:43:51 PM PDT 24
Finished	Jul 01 06:44:06 PM PDT 24
Peak memory	226456 kb
Host	smart-4dcfcb99-0d9d-42ed-839a-d2f769f25c74
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3370955308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.3370955308
Directory	/workspace/2.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/0.lc_ctrl_sec_cm.768408991
Short name	T60
Test name
Test status
Simulation time	503126604 ps
CPU time	40.55 seconds
Started	Jul 01 06:43:28 PM PDT 24
Finished	Jul 01 06:44:10 PM PDT 24
Peak memory	270196 kb
Host	smart-28b02c5e-43ee-4429-bf2f-12f925460726
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768408991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.768408991
Directory	/workspace/0.lc_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/41.lc_ctrl_sec_token_mux.1386945464
Short name	T63
Test name
Test status
Simulation time	509994265 ps
CPU time	9.5 seconds
Started	Jul 01 06:47:01 PM PDT 24
Finished	Jul 01 06:47:14 PM PDT 24
Peak memory	218696 kb
Host	smart-ea58451a-b001-44e7-952c-800f71b8fb9f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386945464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux. 1386945464
Directory	/workspace/41.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3165424168
Short name	T123
Test name
Test status
Simulation time	289167049 ps
CPU time	3.26 seconds
Started	Jul 01 04:57:57 PM PDT 24
Finished	Jul 01 04:58:09 PM PDT 24
Peak memory	221916 kb
Host	smart-9dd1003d-da23-4bea-bf0f-7fddde86b2aa
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165424168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg _err.3165424168
Directory	/workspace/14.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/41.lc_ctrl_jtag_access.3217047482
Short name	T6
Test name
Test status
Simulation time	852327904 ps
CPU time	5.69 seconds
Started	Jul 01 06:47:01 PM PDT 24
Finished	Jul 01 06:47:10 PM PDT 24
Peak memory	217820 kb
Host	smart-a2c08c3a-46e3-4936-95e2-c77873a9611a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217047482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.3217047482
Directory	/workspace/41.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.530947308
Short name	T143
Test name
Test status
Simulation time	217469361 ps
CPU time	2.98 seconds
Started	Jul 01 04:57:43 PM PDT 24
Finished	Jul 01 04:57:54 PM PDT 24
Peak memory	223804 kb
Host	smart-d52becc6-a50d-4f03-8cbb-c74920edcd74
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530947 308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.530947308
Directory	/workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/default/41.lc_ctrl_alert_test.654266537
Short name	T92
Test name
Test status
Simulation time	227896715 ps
CPU time	0.86 seconds
Started	Jul 01 06:47:01 PM PDT 24
Finished	Jul 01 06:47:04 PM PDT 24
Peak memory	209400 kb
Host	smart-cfa98bb4-729b-4644-a445-dbef7312b455
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654266537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.654266537
Directory	/workspace/41.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.782535637
Short name	T94
Test name
Test status
Simulation time	20258548889 ps
CPU time	626.16 seconds
Started	Jul 01 06:46:13 PM PDT 24
Finished	Jul 01 06:56:41 PM PDT 24
Peak memory	422696 kb
Host	smart-7b234985-3ed3-4f5b-995c-26f2c3ca647f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=782535637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_stress_all_with_rand_reset.782535637
Directory	/workspace/25.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3027607747
Short name	T194
Test name
Test status
Simulation time	135967088 ps
CPU time	1.08 seconds
Started	Jul 01 04:57:29 PM PDT 24
Finished	Jul 01 04:57:36 PM PDT 24
Peak memory	209244 kb
Host	smart-3cc75811-afb9-4936-818d-c46ce99bb06b
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027607747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin g.3027607747
Directory	/workspace/2.lc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1465034308
Short name	T142
Test name
Test status
Simulation time	433200135 ps
CPU time	3.15 seconds
Started	Jul 01 04:57:32 PM PDT 24
Finished	Jul 01 04:57:44 PM PDT 24
Peak memory	217308 kb
Host	smart-892bbb36-d5a8-408a-a32d-ccee05baf16e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465034308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_ err.1465034308
Directory	/workspace/2.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/20.lc_ctrl_security_escalation.2869051287
Short name	T10
Test name
Test status
Simulation time	1651508528 ps
CPU time	10.9 seconds
Started	Jul 01 06:45:53 PM PDT 24
Finished	Jul 01 06:46:06 PM PDT 24
Peak memory	226464 kb
Host	smart-c65f87cf-d20d-40da-938d-500c2e0ff73d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2869051287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.2869051287
Directory	/workspace/20.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.4006475087
Short name	T129
Test name
Test status
Simulation time	28764265 ps
CPU time	1.22 seconds
Started	Jul 01 04:57:25 PM PDT 24
Finished	Jul 01 04:57:31 PM PDT 24
Peak memory	209008 kb
Host	smart-7d59fa7d-1e62-4a9a-b701-127fafa3f80b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006475087 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.4006475087
Directory	/workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1238055069
Short name	T135
Test name
Test status
Simulation time	110284915 ps
CPU time	2.9 seconds
Started	Jul 01 04:57:48 PM PDT 24
Finished	Jul 01 04:58:01 PM PDT 24
Peak memory	221992 kb
Host	smart-6f4a7cf6-ed7d-4d27-9c42-217436284c69
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238055069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg _err.1238055069
Directory	/workspace/11.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_errors.122501550
Short name	T529
Test name
Test status
Simulation time	2918877634 ps
CPU time	81.88 seconds
Started	Jul 01 06:43:21 PM PDT 24
Finished	Jul 01 06:44:45 PM PDT 24
Peak memory	226512 kb
Host	smart-ef0fc883-54e3-445f-b999-428196562592
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122501550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_err ors.122501550
Directory	/workspace/0.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.163891452
Short name	T133
Test name
Test status
Simulation time	269456679 ps
CPU time	3.28 seconds
Started	Jul 01 04:57:48 PM PDT 24
Finished	Jul 01 04:58:00 PM PDT 24
Peak memory	222116 kb
Host	smart-4a51bf07-4ee6-4e6f-86e7-52a61d5308a0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163891452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg_ err.163891452
Directory	/workspace/12.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.382163166
Short name	T924
Test name
Test status
Simulation time	571798482 ps
CPU time	2.81 seconds
Started	Jul 01 04:57:56 PM PDT 24
Finished	Jul 01 04:58:08 PM PDT 24
Peak memory	217680 kb
Host	smart-52f2dce4-15b1-4f9c-b82d-a1309f84edfd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382163166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.382163166
Directory	/workspace/14.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.1633080712
Short name	T119
Test name
Test status
Simulation time	17131070634 ps
CPU time	328.02 seconds
Started	Jul 01 06:46:24 PM PDT 24
Finished	Jul 01 06:51:55 PM PDT 24
Peak memory	284272 kb
Host	smart-e1e2cd95-0ff4-4273-86c0-ecf6e749c5ee
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1633080712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all_with_rand_reset.1633080712
Directory	/workspace/28.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.160240691
Short name	T889
Test name
Test status
Simulation time	92660498 ps
CPU time	1.77 seconds
Started	Jul 01 04:57:23 PM PDT 24
Finished	Jul 01 04:57:30 PM PDT 24
Peak memory	210528 kb
Host	smart-58eff211-7b95-4f7f-b5cb-ee8fcdb92174
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160240691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.160240691
Directory	/workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3616244336
Short name	T149
Test name
Test status
Simulation time	42872496 ps
CPU time	2.2 seconds
Started	Jul 01 04:57:48 PM PDT 24
Finished	Jul 01 04:58:00 PM PDT 24
Peak memory	221640 kb
Host	smart-f73d51df-18d6-4665-bd4e-f1df2e8b4e18
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616244336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_ err.3616244336
Directory	/workspace/5.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.3138640065
Short name	T146
Test name
Test status
Simulation time	527591725 ps
CPU time	3.04 seconds
Started	Jul 01 04:57:53 PM PDT 24
Finished	Jul 01 04:58:05 PM PDT 24
Peak memory	221760 kb
Host	smart-e83543d3-8f66-4426-955a-c0c99bd56360
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138640065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg _err.3138640065
Directory	/workspace/15.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.1069474670
Short name	T108
Test name
Test status
Simulation time	11000247873 ps
CPU time	301.2 seconds
Started	Jul 01 06:45:05 PM PDT 24
Finished	Jul 01 06:50:10 PM PDT 24
Peak memory	278464 kb
Host	smart-d80d5355-1988-4b1f-a4f6-036bf6b4d8f9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1069474670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.1069474670
Directory	/workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.3426216682
Short name	T97
Test name
Test status
Simulation time	33738216376 ps
CPU time	318.47 seconds
Started	Jul 01 06:45:32 PM PDT 24
Finished	Jul 01 06:50:52 PM PDT 24
Peak memory	309040 kb
Host	smart-d2704791-b21d-423d-aacb-93fc65a4dd67
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3426216682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all_with_rand_reset.3426216682
Directory	/workspace/15.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/23.lc_ctrl_state_failure.767547391
Short name	T44
Test name
Test status
Simulation time	222136014 ps
CPU time	19.93 seconds
Started	Jul 01 06:46:00 PM PDT 24
Finished	Jul 01 06:46:21 PM PDT 24
Peak memory	251500 kb
Host	smart-8f0c982a-4216-44c4-bfef-cee400e83bb8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=767547391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.767547391
Directory	/workspace/23.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/1.lc_ctrl_claim_transition_if.3257888464
Short name	T210
Test name
Test status
Simulation time	13728314 ps
CPU time	0.78 seconds
Started	Jul 01 06:43:45 PM PDT 24
Finished	Jul 01 06:43:47 PM PDT 24
Peak memory	209320 kb
Host	smart-fea2dcc2-e6c3-4f30-b99f-c97abcbe3d81
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3257888464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.3257888464
Directory	/workspace/1.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/1.lc_ctrl_security_escalation.2842065568
Short name	T216
Test name
Test status
Simulation time	2770077303 ps
CPU time	6.7 seconds
Started	Jul 01 06:43:50 PM PDT 24
Finished	Jul 01 06:43:58 PM PDT 24
Peak memory	225800 kb
Host	smart-743a0ef8-7d9a-47b7-9a3c-f4b0e56f5740
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2842065568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.2842065568
Directory	/workspace/1.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/2.lc_ctrl_claim_transition_if.4078970740
Short name	T213
Test name
Test status
Simulation time	12091831 ps
CPU time	1.04 seconds
Started	Jul 01 06:43:52 PM PDT 24
Finished	Jul 01 06:43:55 PM PDT 24
Peak memory	209464 kb
Host	smart-63b304e2-252f-46e9-bd5d-ecad34e7da63
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4078970740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.4078970740
Directory	/workspace/2.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/3.lc_ctrl_claim_transition_if.1237435778
Short name	T212
Test name
Test status
Simulation time	13923946 ps
CPU time	1.05 seconds
Started	Jul 01 06:44:00 PM PDT 24
Finished	Jul 01 06:44:02 PM PDT 24
Peak memory	209404 kb
Host	smart-502a4051-3292-4497-8d56-e1705839786d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1237435778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.1237435778
Directory	/workspace/3.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.4157768024
Short name	T151
Test name
Test status
Simulation time	449517638 ps
CPU time	3.06 seconds
Started	Jul 01 04:57:29 PM PDT 24
Finished	Jul 01 04:57:39 PM PDT 24
Peak memory	222052 kb
Host	smart-8716f328-03f5-4aba-b9f4-db7030f2bd91
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157768024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_ err.4157768024
Directory	/workspace/1.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.4077239718
Short name	T150
Test name
Test status
Simulation time	114598927 ps
CPU time	2.76 seconds
Started	Jul 01 04:58:06 PM PDT 24
Finished	Jul 01 04:58:13 PM PDT 24
Peak memory	217232 kb
Host	smart-3be09d38-84fa-4ff5-8c37-de259ee7fc42
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077239718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg _err.4077239718
Directory	/workspace/13.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2759183858
Short name	T141
Test name
Test status
Simulation time	299193631 ps
CPU time	2.06 seconds
Started	Jul 01 04:57:53 PM PDT 24
Finished	Jul 01 04:58:05 PM PDT 24
Peak memory	221644 kb
Host	smart-5d794ef7-9064-4170-99fd-15158c5977f3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759183858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg _err.2759183858
Directory	/workspace/16.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.418156817
Short name	T152
Test name
Test status
Simulation time	44227593 ps
CPU time	2.31 seconds
Started	Jul 01 04:57:55 PM PDT 24
Finished	Jul 01 04:58:07 PM PDT 24
Peak memory	222080 kb
Host	smart-6a0ac869-8981-415b-a0f6-b6eed51822ec
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418156817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg_ err.418156817
Directory	/workspace/18.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.133460945
Short name	T125
Test name
Test status
Simulation time	66382499 ps
CPU time	1.99 seconds
Started	Jul 01 04:57:54 PM PDT 24
Finished	Jul 01 04:58:05 PM PDT 24
Peak memory	221764 kb
Host	smart-ac1f203a-8f24-4622-a86a-16c6d4581185
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133460945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg_ err.133460945
Directory	/workspace/19.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/1.lc_ctrl_stress_all.3872500054
Short name	T53
Test name
Test status
Simulation time	3895657466 ps
CPU time	164.27 seconds
Started	Jul 01 06:43:44 PM PDT 24
Finished	Jul 01 06:46:30 PM PDT 24
Peak memory	273372 kb
Host	smart-9cd1edd4-f3aa-4ca7-93f9-0c54d467bf44
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872500054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all.3872500054
Directory	/workspace/1.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/12.lc_ctrl_errors.2647911078
Short name	T55
Test name
Test status
Simulation time	447057167 ps
CPU time	12.65 seconds
Started	Jul 01 06:45:19 PM PDT 24
Finished	Jul 01 06:45:36 PM PDT 24
Peak memory	218644 kb
Host	smart-c1509d53-b738-4a1e-b009-d80d651d7bce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2647911078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.2647911078
Directory	/workspace/12.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/15.lc_ctrl_state_post_trans.3849488678
Short name	T43
Test name
Test status
Simulation time	349811158 ps
CPU time	6.54 seconds
Started	Jul 01 06:45:28 PM PDT 24
Finished	Jul 01 06:45:37 PM PDT 24
Peak memory	251028 kb
Host	smart-d9ef78ce-9e28-49b7-9f4c-88c8afa43739
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3849488678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.3849488678
Directory	/workspace/15.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/0.lc_ctrl_errors.61050376
Short name	T36
Test name
Test status
Simulation time	1040277315 ps
CPU time	10.82 seconds
Started	Jul 01 06:43:20 PM PDT 24
Finished	Jul 01 06:43:32 PM PDT 24
Peak memory	218580 kb
Host	smart-32936d38-19e5-4f6f-8610-0b99cde00f6f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=61050376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.61050376
Directory	/workspace/0.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/13.lc_ctrl_jtag_state_failure.2300669810
Short name	T31
Test name
Test status
Simulation time	20138080956 ps
CPU time	43.59 seconds
Started	Jul 01 06:45:20 PM PDT 24
Finished	Jul 01 06:46:07 PM PDT 24
Peak memory	251316 kb
Host	smart-81872c3a-3e94-486b-b8bc-b66857bca761
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300669810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt ag_state_failure.2300669810
Directory	/workspace/13.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2942044121
Short name	T198
Test name
Test status
Simulation time	41145831 ps
CPU time	1.01 seconds
Started	Jul 01 04:57:37 PM PDT 24
Finished	Jul 01 04:57:46 PM PDT 24
Peak memory	209124 kb
Host	smart-e68510b6-155e-4114-89b6-8535de880cc7
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942044121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin g.2942044121
Directory	/workspace/0.lc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2748717351
Short name	T930
Test name
Test status
Simulation time	112256282 ps
CPU time	1.67 seconds
Started	Jul 01 04:57:36 PM PDT 24
Finished	Jul 01 04:57:46 PM PDT 24
Peak memory	208616 kb
Host	smart-8f165bbc-db9a-40aa-98dd-d34a3c0048d6
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748717351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas h.2748717351
Directory	/workspace/0.lc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1022155308
Short name	T943
Test name
Test status
Simulation time	21255245 ps
CPU time	1.27 seconds
Started	Jul 01 04:57:37 PM PDT 24
Finished	Jul 01 04:57:47 PM PDT 24
Peak memory	211316 kb
Host	smart-75b85c02-75bd-4c2d-b3cb-9f1cc93c78da
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022155308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese t.1022155308
Directory	/workspace/0.lc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1339641548
Short name	T938
Test name
Test status
Simulation time	57319980 ps
CPU time	1.08 seconds
Started	Jul 01 04:57:21 PM PDT 24
Finished	Jul 01 04:57:27 PM PDT 24
Peak memory	219100 kb
Host	smart-f8af3c31-ba49-47a6-8426-95bc213c7719
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339641548 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.1339641548
Directory	/workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2762391504
Short name	T188
Test name
Test status
Simulation time	18939730 ps
CPU time	1.1 seconds
Started	Jul 01 04:57:38 PM PDT 24
Finished	Jul 01 04:57:47 PM PDT 24
Peak memory	209072 kb
Host	smart-18e1145e-b51e-44b9-a830-48e13b1b372f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762391504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.2762391504
Directory	/workspace/0.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3014635290
Short name	T925
Test name
Test status
Simulation time	229479628 ps
CPU time	1.95 seconds
Started	Jul 01 04:57:23 PM PDT 24
Finished	Jul 01 04:57:29 PM PDT 24
Peak memory	208968 kb
Host	smart-17d44324-0737-4eb9-b7f5-9754be80d720
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014635290 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 0.lc_ctrl_jtag_alert_test.3014635290
Directory	/workspace/0.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3104371664
Short name	T900
Test name
Test status
Simulation time	441142204 ps
CPU time	10.35 seconds
Started	Jul 01 04:57:21 PM PDT 24
Finished	Jul 01 04:57:36 PM PDT 24
Peak memory	208792 kb
Host	smart-7c1607c1-8c30-4224-877d-161c63658857
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104371664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.3104371664
Directory	/workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2436508252
Short name	T921
Test name
Test status
Simulation time	6848529703 ps
CPU time	14.5 seconds
Started	Jul 01 04:57:22 PM PDT 24
Finished	Jul 01 04:57:41 PM PDT 24
Peak memory	208944 kb
Host	smart-9b837462-cf74-4a60-8142-419023fb2914
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436508252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.2436508252
Directory	/workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.928838266
Short name	T915
Test name
Test status
Simulation time	290863137 ps
CPU time	1.58 seconds
Started	Jul 01 04:57:24 PM PDT 24
Finished	Jul 01 04:57:31 PM PDT 24
Peak memory	217472 kb
Host	smart-152658a6-e4c7-47f8-9f1d-1e9a2f0ae5a7
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928838 266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.928838266
Directory	/workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.678524717
Short name	T893
Test name
Test status
Simulation time	44821462 ps
CPU time	1.74 seconds
Started	Jul 01 04:57:21 PM PDT 24
Finished	Jul 01 04:57:28 PM PDT 24
Peak memory	209056 kb
Host	smart-0844b419-cac2-4a0a-a238-fd16b06ae904
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678524717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_rw.678524717
Directory	/workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1644166706
Short name	T980
Test name
Test status
Simulation time	249493144 ps
CPU time	1.05 seconds
Started	Jul 01 04:57:46 PM PDT 24
Finished	Jul 01 04:57:56 PM PDT 24
Peak memory	209048 kb
Host	smart-e6a0d3a9-ba4e-4734-91c7-65b7148b5b07
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644166706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl _same_csr_outstanding.1644166706
Directory	/workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2954954722
Short name	T132
Test name
Test status
Simulation time	85837542 ps
CPU time	3.52 seconds
Started	Jul 01 04:57:32 PM PDT 24
Finished	Jul 01 04:57:44 PM PDT 24
Peak memory	217260 kb
Host	smart-a48a5f13-ad6a-407d-95bd-532f1253bd29
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954954722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.2954954722
Directory	/workspace/0.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.706720086
Short name	T148
Test name
Test status
Simulation time	56538709 ps
CPU time	2.57 seconds
Started	Jul 01 04:57:44 PM PDT 24
Finished	Jul 01 04:57:55 PM PDT 24
Peak memory	217276 kb
Host	smart-ed0af662-f870-4b97-888a-ac44fd532870
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706720086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_e rr.706720086
Directory	/workspace/0.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.39287539
Short name	T192
Test name
Test status
Simulation time	145491999 ps
CPU time	1.62 seconds
Started	Jul 01 04:57:31 PM PDT 24
Finished	Jul 01 04:57:40 PM PDT 24
Peak memory	209116 kb
Host	smart-cedd95ca-5dad-47c1-9f6c-60b93dee6892
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39287539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasing.39287539
Directory	/workspace/1.lc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3351623233
Short name	T947
Test name
Test status
Simulation time	46407077 ps
CPU time	1.33 seconds
Started	Jul 01 04:57:42 PM PDT 24
Finished	Jul 01 04:57:51 PM PDT 24
Peak memory	217048 kb
Host	smart-a15ea04d-d915-4013-8ffb-72979ce9cb8d
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351623233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas h.3351623233
Directory	/workspace/1.lc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.677992669
Short name	T941
Test name
Test status
Simulation time	38834488 ps
CPU time	1.32 seconds
Started	Jul 01 04:57:22 PM PDT 24
Finished	Jul 01 04:57:28 PM PDT 24
Peak memory	218952 kb
Host	smart-8741f88d-fc6c-4266-b18b-cdfa074d5d7e
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677992669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_reset .677992669
Directory	/workspace/1.lc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1863732800
Short name	T912
Test name
Test status
Simulation time	21686926 ps
CPU time	1.57 seconds
Started	Jul 01 04:57:28 PM PDT 24
Finished	Jul 01 04:57:37 PM PDT 24
Peak memory	219020 kb
Host	smart-f835a4ff-1325-4e87-986f-c389e9aee8c5
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863732800 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.1863732800
Directory	/workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.922086334
Short name	T201
Test name
Test status
Simulation time	59208488 ps
CPU time	0.89 seconds
Started	Jul 01 04:57:34 PM PDT 24
Finished	Jul 01 04:57:44 PM PDT 24
Peak memory	209120 kb
Host	smart-947d7e0a-5523-4497-aea1-ea2063e5c596
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922086334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.922086334
Directory	/workspace/1.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1210228123
Short name	T926
Test name
Test status
Simulation time	38585051 ps
CPU time	1.14 seconds
Started	Jul 01 04:57:23 PM PDT 24
Finished	Jul 01 04:57:29 PM PDT 24
Peak memory	208964 kb
Host	smart-b2294a93-2762-4d1e-ac35-45560af16c9c
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210228123 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 1.lc_ctrl_jtag_alert_test.1210228123
Directory	/workspace/1.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1600844478
Short name	T927
Test name
Test status
Simulation time	1885234562 ps
CPU time	4.82 seconds
Started	Jul 01 04:57:26 PM PDT 24
Finished	Jul 01 04:57:36 PM PDT 24
Peak memory	208768 kb
Host	smart-0abd0a87-53c1-4212-b183-1f931cc78a8e
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600844478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.1600844478
Directory	/workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1271590103
Short name	T991
Test name
Test status
Simulation time	3643161892 ps
CPU time	22.12 seconds
Started	Jul 01 04:57:31 PM PDT 24
Finished	Jul 01 04:58:02 PM PDT 24
Peak memory	208936 kb
Host	smart-2f76ddae-81d3-423b-be3f-6a2dc441b94b
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271590103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.1271590103
Directory	/workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.133190243
Short name	T981
Test name
Test status
Simulation time	218955139 ps
CPU time	3.27 seconds
Started	Jul 01 04:57:40 PM PDT 24
Finished	Jul 01 04:57:51 PM PDT 24
Peak memory	217212 kb
Host	smart-8bbf7456-a33b-4bfe-9dd6-0cd6d226eb0c
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133190243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.133190243
Directory	/workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3271833176
Short name	T897
Test name
Test status
Simulation time	125288105 ps
CPU time	1.46 seconds
Started	Jul 01 04:57:37 PM PDT 24
Finished	Jul 01 04:57:46 PM PDT 24
Peak memory	208984 kb
Host	smart-13676dbc-c6ba-45e5-9f2a-43200191db61
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271833176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_rw.3271833176
Directory	/workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.613158332
Short name	T979
Test name
Test status
Simulation time	21786035 ps
CPU time	1.41 seconds
Started	Jul 01 04:57:26 PM PDT 24
Finished	Jul 01 04:57:33 PM PDT 24
Peak memory	211340 kb
Host	smart-3d7c346a-2615-4455-9b00-98724c630ea8
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613158332 -assert nopostproc +UVM_TESTNAM E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.613158332
Directory	/workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2365189004
Short name	T987
Test name
Test status
Simulation time	41263766 ps
CPU time	1.5 seconds
Started	Jul 01 04:57:47 PM PDT 24
Finished	Jul 01 04:57:57 PM PDT 24
Peak memory	217348 kb
Host	smart-0ae97b95-57f9-4de3-9c59-5f8162bf0a16
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365189004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl _same_csr_outstanding.2365189004
Directory	/workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.952635664
Short name	T975
Test name
Test status
Simulation time	81798513 ps
CPU time	3.22 seconds
Started	Jul 01 04:57:26 PM PDT 24
Finished	Jul 01 04:57:34 PM PDT 24
Peak memory	217272 kb
Host	smart-64101391-e032-42c0-8b51-8e9be4d72f7e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952635664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.952635664
Directory	/workspace/1.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.86197035
Short name	T880
Test name
Test status
Simulation time	47583339 ps
CPU time	1.47 seconds
Started	Jul 01 04:57:44 PM PDT 24
Finished	Jul 01 04:57:54 PM PDT 24
Peak memory	217720 kb
Host	smart-6442a771-c39f-4831-bd57-babe6a24f65a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86197035 -assert nopostproc +UVM_TESTNAME=l c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.86197035
Directory	/workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.352755693
Short name	T906
Test name
Test status
Simulation time	70545938 ps
CPU time	0.93 seconds
Started	Jul 01 04:57:48 PM PDT 24
Finished	Jul 01 04:58:00 PM PDT 24
Peak memory	209112 kb
Host	smart-df4e6d60-5ef3-4cc3-8497-0194b92bd939
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352755693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.352755693
Directory	/workspace/10.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.1631233667
Short name	T959
Test name
Test status
Simulation time	18553137 ps
CPU time	1.33 seconds
Started	Jul 01 04:57:44 PM PDT 24
Finished	Jul 01 04:57:54 PM PDT 24
Peak memory	217324 kb
Host	smart-fd03b7e9-36a3-4edc-b4b8-abb8217fafd1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631233667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr l_same_csr_outstanding.1631233667
Directory	/workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.555996914
Short name	T963
Test name
Test status
Simulation time	191130257 ps
CPU time	2.58 seconds
Started	Jul 01 04:57:55 PM PDT 24
Finished	Jul 01 04:58:07 PM PDT 24
Peak memory	217468 kb
Host	smart-0b9fb656-d5e5-4911-9bd7-f298d7c41aea
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555996914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.555996914
Directory	/workspace/10.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3998103443
Short name	T144
Test name
Test status
Simulation time	216697322 ps
CPU time	2.18 seconds
Started	Jul 01 04:57:53 PM PDT 24
Finished	Jul 01 04:58:04 PM PDT 24
Peak memory	221768 kb
Host	smart-ccee55ee-80fe-45f0-8cf2-401220f828ee
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998103443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg _err.3998103443
Directory	/workspace/10.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3981264817
Short name	T919
Test name
Test status
Simulation time	31950619 ps
CPU time	1.25 seconds
Started	Jul 01 04:57:44 PM PDT 24
Finished	Jul 01 04:57:53 PM PDT 24
Peak memory	217400 kb
Host	smart-d098e619-bf88-4f3a-bcef-764cfff58f4e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981264817 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.3981264817
Directory	/workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1295553198
Short name	T905
Test name
Test status
Simulation time	14202183 ps
CPU time	0.89 seconds
Started	Jul 01 04:57:48 PM PDT 24
Finished	Jul 01 04:58:00 PM PDT 24
Peak memory	209124 kb
Host	smart-f8b530b7-28a0-4b21-887a-508c0152c193
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295553198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.1295553198
Directory	/workspace/11.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.4117780770
Short name	T982
Test name
Test status
Simulation time	30224255 ps
CPU time	1.08 seconds
Started	Jul 01 04:57:55 PM PDT 24
Finished	Jul 01 04:58:05 PM PDT 24
Peak memory	217468 kb
Host	smart-fd0e70e0-fabf-49b2-b247-0bc665f2af1f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117780770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr l_same_csr_outstanding.4117780770
Directory	/workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.671351634
Short name	T130
Test name
Test status
Simulation time	762805251 ps
CPU time	4.06 seconds
Started	Jul 01 04:57:53 PM PDT 24
Finished	Jul 01 04:58:07 PM PDT 24
Peak memory	217252 kb
Host	smart-b07944f3-7f46-4f8a-a7ef-aefe768e5b35
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671351634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.671351634
Directory	/workspace/11.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.421797937
Short name	T956
Test name
Test status
Simulation time	43470224 ps
CPU time	1.88 seconds
Started	Jul 01 04:57:55 PM PDT 24
Finished	Jul 01 04:58:07 PM PDT 24
Peak memory	225284 kb
Host	smart-1ed708eb-abc9-40f6-9848-b7ce24113827
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421797937 -assert nopostproc +UVM_TESTNAME= lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.421797937
Directory	/workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.4254499319
Short name	T204
Test name
Test status
Simulation time	15638100 ps
CPU time	0.92 seconds
Started	Jul 01 04:57:44 PM PDT 24
Finished	Jul 01 04:57:53 PM PDT 24
Peak memory	209120 kb
Host	smart-41ed58e5-b499-45fe-81f0-8a60b7887705
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254499319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.4254499319
Directory	/workspace/12.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3767522262
Short name	T202
Test name
Test status
Simulation time	56044379 ps
CPU time	1.06 seconds
Started	Jul 01 04:57:56 PM PDT 24
Finished	Jul 01 04:58:06 PM PDT 24
Peak memory	209128 kb
Host	smart-95fa7f17-6249-418a-a5bd-3a572ebe9213
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767522262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr l_same_csr_outstanding.3767522262
Directory	/workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.4128029754
Short name	T1002
Test name
Test status
Simulation time	79441951 ps
CPU time	2.25 seconds
Started	Jul 01 04:57:47 PM PDT 24
Finished	Jul 01 04:57:58 PM PDT 24
Peak memory	217272 kb
Host	smart-83de9942-afb0-4def-9945-8622642c61b2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128029754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.4128029754
Directory	/workspace/12.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3400088474
Short name	T928
Test name
Test status
Simulation time	21852830 ps
CPU time	1.4 seconds
Started	Jul 01 04:57:55 PM PDT 24
Finished	Jul 01 04:58:06 PM PDT 24
Peak memory	218760 kb
Host	smart-9276c91a-681b-49b4-8afc-72430f266515
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400088474 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.3400088474
Directory	/workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1960450699
Short name	T196
Test name
Test status
Simulation time	41245108 ps
CPU time	0.92 seconds
Started	Jul 01 04:57:57 PM PDT 24
Finished	Jul 01 04:58:06 PM PDT 24
Peak memory	209160 kb
Host	smart-fcf7cb13-aa68-4736-92c9-e9b9dbeead2f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960450699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.1960450699
Directory	/workspace/13.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3473639601
Short name	T203
Test name
Test status
Simulation time	23444878 ps
CPU time	1.26 seconds
Started	Jul 01 04:57:52 PM PDT 24
Finished	Jul 01 04:58:02 PM PDT 24
Peak memory	217320 kb
Host	smart-bf5be31e-9029-42dd-871a-efd4c1084caf
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473639601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr l_same_csr_outstanding.3473639601
Directory	/workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2137785910
Short name	T122
Test name
Test status
Simulation time	143083641 ps
CPU time	5.3 seconds
Started	Jul 01 04:57:53 PM PDT 24
Finished	Jul 01 04:58:09 PM PDT 24
Peak memory	217716 kb
Host	smart-eb0a73a6-9d51-4b26-ade5-28a78934fc9d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137785910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.2137785910
Directory	/workspace/13.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1590185030
Short name	T932
Test name
Test status
Simulation time	23214049 ps
CPU time	1.32 seconds
Started	Jul 01 04:57:58 PM PDT 24
Finished	Jul 01 04:58:07 PM PDT 24
Peak memory	217500 kb
Host	smart-c2ba3592-cde9-4137-9872-0ed7de6e0ad9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590185030 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.1590185030
Directory	/workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3990471490
Short name	T882
Test name
Test status
Simulation time	38189659 ps
CPU time	0.87 seconds
Started	Jul 01 04:58:05 PM PDT 24
Finished	Jul 01 04:58:11 PM PDT 24
Peak memory	209028 kb
Host	smart-b98b6e3f-6661-468d-a489-f1a9a65f915a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990471490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.3990471490
Directory	/workspace/14.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1874302548
Short name	T892
Test name
Test status
Simulation time	42347719 ps
CPU time	1.41 seconds
Started	Jul 01 04:57:53 PM PDT 24
Finished	Jul 01 04:58:05 PM PDT 24
Peak memory	217316 kb
Host	smart-dd003f5c-8d32-4fb7-8117-47fa4f9151fb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874302548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr l_same_csr_outstanding.1874302548
Directory	/workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3199730685
Short name	T914
Test name
Test status
Simulation time	86978972 ps
CPU time	1.34 seconds
Started	Jul 01 04:58:06 PM PDT 24
Finished	Jul 01 04:58:12 PM PDT 24
Peak memory	218668 kb
Host	smart-b1d01f11-025f-41f0-b462-a31ff5fb0878
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199730685 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.3199730685
Directory	/workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.546206641
Short name	T207
Test name
Test status
Simulation time	12224405 ps
CPU time	0.87 seconds
Started	Jul 01 04:57:53 PM PDT 24
Finished	Jul 01 04:58:04 PM PDT 24
Peak memory	209120 kb
Host	smart-18bdc161-b756-4825-b77a-861ed3614614
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546206641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.546206641
Directory	/workspace/15.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.4181488821
Short name	T957
Test name
Test status
Simulation time	90230877 ps
CPU time	1.37 seconds
Started	Jul 01 04:57:53 PM PDT 24
Finished	Jul 01 04:58:04 PM PDT 24
Peak memory	217312 kb
Host	smart-61667c8b-e660-4515-9d82-5bae5e71dfdc
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181488821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr l_same_csr_outstanding.4181488821
Directory	/workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.4284165359
Short name	T929
Test name
Test status
Simulation time	64914575 ps
CPU time	2.03 seconds
Started	Jul 01 04:57:54 PM PDT 24
Finished	Jul 01 04:58:05 PM PDT 24
Peak memory	217276 kb
Host	smart-706f4a25-6e4e-4828-8919-68832619090b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284165359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.4284165359
Directory	/workspace/15.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1215311494
Short name	T995
Test name
Test status
Simulation time	20234669 ps
CPU time	1.17 seconds
Started	Jul 01 04:57:53 PM PDT 24
Finished	Jul 01 04:58:04 PM PDT 24
Peak memory	217516 kb
Host	smart-6d2001fa-41ae-49de-8bde-ae1f09666e92
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215311494 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.1215311494
Directory	/workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1430847694
Short name	T903
Test name
Test status
Simulation time	24740658 ps
CPU time	0.99 seconds
Started	Jul 01 04:57:52 PM PDT 24
Finished	Jul 01 04:58:03 PM PDT 24
Peak memory	209116 kb
Host	smart-338a2869-8694-4214-8b9a-cd8dd23627d3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430847694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.1430847694
Directory	/workspace/16.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2428023170
Short name	T910
Test name
Test status
Simulation time	110729482 ps
CPU time	1.18 seconds
Started	Jul 01 04:57:56 PM PDT 24
Finished	Jul 01 04:58:06 PM PDT 24
Peak memory	209188 kb
Host	smart-269fc2aa-62a5-4bcb-8873-81b79ae5bf50
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428023170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr l_same_csr_outstanding.2428023170
Directory	/workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.404413313
Short name	T131
Test name
Test status
Simulation time	57447967 ps
CPU time	2.63 seconds
Started	Jul 01 04:57:54 PM PDT 24
Finished	Jul 01 04:58:07 PM PDT 24
Peak memory	209068 kb
Host	smart-5268f5dd-84a5-41f4-bfa2-f14c4a41e424
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404413313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.404413313
Directory	/workspace/16.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1813380898
Short name	T128
Test name
Test status
Simulation time	21603854 ps
CPU time	1.45 seconds
Started	Jul 01 04:57:52 PM PDT 24
Finished	Jul 01 04:58:03 PM PDT 24
Peak memory	217388 kb
Host	smart-0ad0b781-64db-48ff-8337-997ab12e4e9c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813380898 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.1813380898
Directory	/workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2216973111
Short name	T199
Test name
Test status
Simulation time	31928023 ps
CPU time	0.88 seconds
Started	Jul 01 04:57:53 PM PDT 24
Finished	Jul 01 04:58:04 PM PDT 24
Peak memory	209104 kb
Host	smart-9c4f841a-8e0b-469f-beaf-113a570fc0f6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216973111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.2216973111
Directory	/workspace/17.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3464296596
Short name	T994
Test name
Test status
Simulation time	129087812 ps
CPU time	1.4 seconds
Started	Jul 01 04:57:54 PM PDT 24
Finished	Jul 01 04:58:05 PM PDT 24
Peak memory	209112 kb
Host	smart-b00909e0-83f4-4529-ab02-65057fed11ff
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464296596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr l_same_csr_outstanding.3464296596
Directory	/workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3246108602
Short name	T124
Test name
Test status
Simulation time	39124263 ps
CPU time	3.08 seconds
Started	Jul 01 04:57:57 PM PDT 24
Finished	Jul 01 04:58:09 PM PDT 24
Peak memory	217684 kb
Host	smart-c9c99f68-ab29-400b-8ab3-022ca5573e7b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246108602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.3246108602
Directory	/workspace/17.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.131842617
Short name	T136
Test name
Test status
Simulation time	83622864 ps
CPU time	2.7 seconds
Started	Jul 01 04:57:56 PM PDT 24
Finished	Jul 01 04:58:08 PM PDT 24
Peak memory	217320 kb
Host	smart-fe20bbe3-c5f0-459b-a0bc-beaeb543aa91
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131842617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg_ err.131842617
Directory	/workspace/17.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2107041390
Short name	T973
Test name
Test status
Simulation time	113284654 ps
CPU time	1.38 seconds
Started	Jul 01 04:58:06 PM PDT 24
Finished	Jul 01 04:58:12 PM PDT 24
Peak memory	218928 kb
Host	smart-00b99ddc-0d46-4a84-a4bf-13fe12469d45
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107041390 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.2107041390
Directory	/workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.4028586130
Short name	T931
Test name
Test status
Simulation time	35498148 ps
CPU time	0.98 seconds
Started	Jul 01 04:57:54 PM PDT 24
Finished	Jul 01 04:58:05 PM PDT 24
Peak memory	209176 kb
Host	smart-36137b63-9420-4cfa-85a3-afe57d9c3c86
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028586130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.4028586130
Directory	/workspace/18.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2163970420
Short name	T894
Test name
Test status
Simulation time	27023939 ps
CPU time	1.01 seconds
Started	Jul 01 04:57:55 PM PDT 24
Finished	Jul 01 04:58:06 PM PDT 24
Peak memory	209164 kb
Host	smart-cae84f45-08d1-464d-ba6b-450302d5cbc1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163970420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr l_same_csr_outstanding.2163970420
Directory	/workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1384752109
Short name	T942
Test name
Test status
Simulation time	41608010 ps
CPU time	3.14 seconds
Started	Jul 01 04:58:05 PM PDT 24
Finished	Jul 01 04:58:14 PM PDT 24
Peak memory	217568 kb
Host	smart-59b51d11-63de-48b7-bb6a-01acfecccc62
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384752109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.1384752109
Directory	/workspace/18.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.4122702357
Short name	T886
Test name
Test status
Simulation time	53365208 ps
CPU time	1.64 seconds
Started	Jul 01 04:57:54 PM PDT 24
Finished	Jul 01 04:58:05 PM PDT 24
Peak memory	218824 kb
Host	smart-d51acd38-064e-4e3f-a658-cf02d63ffb51
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122702357 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.4122702357
Directory	/workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.920589579
Short name	T970
Test name
Test status
Simulation time	35420134 ps
CPU time	1.07 seconds
Started	Jul 01 04:57:56 PM PDT 24
Finished	Jul 01 04:58:06 PM PDT 24
Peak memory	209120 kb
Host	smart-e4b615b7-20ee-4042-8e3b-0819728ecafa
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920589579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.920589579
Directory	/workspace/19.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.176129311
Short name	T949
Test name
Test status
Simulation time	18010356 ps
CPU time	1.2 seconds
Started	Jul 01 04:58:06 PM PDT 24
Finished	Jul 01 04:58:12 PM PDT 24
Peak memory	208948 kb
Host	smart-652cf7b0-5e5b-448a-b0c5-a4eb10e6e8bd
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176129311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl _same_csr_outstanding.176129311
Directory	/workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.77824485
Short name	T954
Test name
Test status
Simulation time	62994490 ps
CPU time	2.36 seconds
Started	Jul 01 04:57:52 PM PDT 24
Finished	Jul 01 04:58:04 PM PDT 24
Peak memory	217272 kb
Host	smart-bc0d9a2f-6aaf-4824-8de6-dec584a44f67
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77824485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.77824485
Directory	/workspace/19.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1416488628
Short name	T999
Test name
Test status
Simulation time	37599590 ps
CPU time	1.14 seconds
Started	Jul 01 04:57:31 PM PDT 24
Finished	Jul 01 04:57:39 PM PDT 24
Peak memory	209144 kb
Host	smart-1a78be0f-41e2-461c-b2ba-3e408d693871
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416488628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas h.1416488628
Directory	/workspace/2.lc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1031661962
Short name	T197
Test name
Test status
Simulation time	18241661 ps
CPU time	1.03 seconds
Started	Jul 01 04:57:28 PM PDT 24
Finished	Jul 01 04:57:35 PM PDT 24
Peak memory	217656 kb
Host	smart-d47f2b08-31b4-48a8-aaf2-4c3e3a3bfff2
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031661962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese t.1031661962
Directory	/workspace/2.lc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3359944669
Short name	T989
Test name
Test status
Simulation time	32398310 ps
CPU time	1.7 seconds
Started	Jul 01 04:57:33 PM PDT 24
Finished	Jul 01 04:57:42 PM PDT 24
Peak memory	217432 kb
Host	smart-9b78a0a5-5900-4cd5-b389-9872fd81f81f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359944669 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.3359944669
Directory	/workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.197216663
Short name	T902
Test name
Test status
Simulation time	26547311 ps
CPU time	0.89 seconds
Started	Jul 01 04:57:31 PM PDT 24
Finished	Jul 01 04:57:40 PM PDT 24
Peak memory	209132 kb
Host	smart-e8c94e99-546c-4893-90eb-9efb1b632914
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197216663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.197216663
Directory	/workspace/2.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3599076389
Short name	T960
Test name
Test status
Simulation time	40821530 ps
CPU time	1.52 seconds
Started	Jul 01 04:57:41 PM PDT 24
Finished	Jul 01 04:57:50 PM PDT 24
Peak memory	208896 kb
Host	smart-d0ae8878-bef4-4076-afdb-6e40ca7a5f6d
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599076389 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 2.lc_ctrl_jtag_alert_test.3599076389
Directory	/workspace/2.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.428957173
Short name	T1001
Test name
Test status
Simulation time	420430371 ps
CPU time	5.45 seconds
Started	Jul 01 04:57:27 PM PDT 24
Finished	Jul 01 04:57:38 PM PDT 24
Peak memory	208336 kb
Host	smart-d646458c-6a46-4313-b0eb-b25576ef7204
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428957173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 2.lc_ctrl_jtag_csr_aliasing.428957173
Directory	/workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.4081305768
Short name	T944
Test name
Test status
Simulation time	702173654 ps
CPU time	4.21 seconds
Started	Jul 01 04:57:41 PM PDT 24
Finished	Jul 01 04:57:53 PM PDT 24
Peak memory	209052 kb
Host	smart-71ac3d2f-515e-4bd0-81c6-28f1591c719f
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081305768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.4081305768
Directory	/workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.1967845641
Short name	T884
Test name
Test status
Simulation time	902262259 ps
CPU time	1.91 seconds
Started	Jul 01 04:57:39 PM PDT 24
Finished	Jul 01 04:57:49 PM PDT 24
Peak memory	210528 kb
Host	smart-77201334-2695-4014-ab76-7e717364e5fd
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967845641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.1967845641
Directory	/workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1001126422
Short name	T901
Test name
Test status
Simulation time	207231021 ps
CPU time	2.34 seconds
Started	Jul 01 04:57:27 PM PDT 24
Finished	Jul 01 04:57:35 PM PDT 24
Peak memory	221272 kb
Host	smart-4bd3af74-fb12-4324-be4d-3caa5eea786b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100112 6422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1001126422
Directory	/workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1591561626
Short name	T157
Test name
Test status
Simulation time	52226053 ps
CPU time	1.89 seconds
Started	Jul 01 04:57:40 PM PDT 24
Finished	Jul 01 04:57:50 PM PDT 24
Peak memory	217088 kb
Host	smart-1a6d32cb-b03d-4e69-bd74-9b1ea8730382
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591561626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_rw.1591561626
Directory	/workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.719580720
Short name	T933
Test name
Test status
Simulation time	15839466 ps
CPU time	0.97 seconds
Started	Jul 01 04:57:32 PM PDT 24
Finished	Jul 01 04:57:41 PM PDT 24
Peak memory	208916 kb
Host	smart-0184ca00-6089-4a9b-90e3-b2a9479eb65c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719580720 -assert nopostproc +UVM_TESTNAM E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.719580720
Directory	/workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3429490653
Short name	T911
Test name
Test status
Simulation time	15883202 ps
CPU time	1.06 seconds
Started	Jul 01 04:57:28 PM PDT 24
Finished	Jul 01 04:57:36 PM PDT 24
Peak memory	208816 kb
Host	smart-b610cf5e-e7a4-4b33-abc6-9703d94708c1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429490653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl _same_csr_outstanding.3429490653
Directory	/workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2724619485
Short name	T907
Test name
Test status
Simulation time	36262636 ps
CPU time	2.23 seconds
Started	Jul 01 04:57:44 PM PDT 24
Finished	Jul 01 04:57:54 PM PDT 24
Peak memory	218184 kb
Host	smart-9ce99786-c9b6-49ac-9bcd-bad87e2a3fb9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724619485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.2724619485
Directory	/workspace/2.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2245867648
Short name	T189
Test name
Test status
Simulation time	45988702 ps
CPU time	1.04 seconds
Started	Jul 01 04:57:31 PM PDT 24
Finished	Jul 01 04:57:41 PM PDT 24
Peak memory	209136 kb
Host	smart-f12fb567-9ab8-471b-8ef0-a161ec07744b
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245867648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin g.2245867648
Directory	/workspace/3.lc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1341512506
Short name	T934
Test name
Test status
Simulation time	27773289 ps
CPU time	1.83 seconds
Started	Jul 01 04:57:41 PM PDT 24
Finished	Jul 01 04:57:50 PM PDT 24
Peak memory	209108 kb
Host	smart-6ed7b4a8-d22d-4c49-bfec-0649482144e0
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341512506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas h.1341512506
Directory	/workspace/3.lc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2494928242
Short name	T968
Test name
Test status
Simulation time	51037953 ps
CPU time	0.97 seconds
Started	Jul 01 04:57:40 PM PDT 24
Finished	Jul 01 04:57:48 PM PDT 24
Peak memory	209616 kb
Host	smart-7c1ff5ff-dbb5-4ca1-8f67-32a2d664f9b0
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494928242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese t.2494928242
Directory	/workspace/3.lc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.2238706271
Short name	T138
Test name
Test status
Simulation time	73868661 ps
CPU time	0.96 seconds
Started	Jul 01 04:57:31 PM PDT 24
Finished	Jul 01 04:57:39 PM PDT 24
Peak memory	217268 kb
Host	smart-98c68452-2e48-4779-b445-530c80570355
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238706271 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.2238706271
Directory	/workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.567410172
Short name	T193
Test name
Test status
Simulation time	30679113 ps
CPU time	0.97 seconds
Started	Jul 01 04:57:45 PM PDT 24
Finished	Jul 01 04:57:55 PM PDT 24
Peak memory	209064 kb
Host	smart-16349cd0-8e69-43ea-a493-30cd33cc7532
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567410172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.567410172
Directory	/workspace/3.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3091525725
Short name	T881
Test name
Test status
Simulation time	82386065 ps
CPU time	1.13 seconds
Started	Jul 01 04:57:28 PM PDT 24
Finished	Jul 01 04:57:36 PM PDT 24
Peak memory	208384 kb
Host	smart-48ea9a29-bea6-4f31-898e-9ee03f5c5c71
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091525725 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 3.lc_ctrl_jtag_alert_test.3091525725
Directory	/workspace/3.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3533037789
Short name	T913
Test name
Test status
Simulation time	1968331305 ps
CPU time	5.64 seconds
Started	Jul 01 04:57:46 PM PDT 24
Finished	Jul 01 04:58:00 PM PDT 24
Peak memory	208756 kb
Host	smart-ad6a03c5-c1ec-4f6e-bb68-0f4ca4cae576
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533037789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.3533037789
Directory	/workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.379535286
Short name	T940
Test name
Test status
Simulation time	7001782251 ps
CPU time	20.75 seconds
Started	Jul 01 04:57:28 PM PDT 24
Finished	Jul 01 04:57:55 PM PDT 24
Peak memory	217120 kb
Host	smart-71c50849-1f3d-494b-a4c5-33a14ae105dd
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379535286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.379535286
Directory	/workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1070640383
Short name	T952
Test name
Test status
Simulation time	454228833 ps
CPU time	2.14 seconds
Started	Jul 01 04:57:28 PM PDT 24
Finished	Jul 01 04:57:37 PM PDT 24
Peak memory	210764 kb
Host	smart-af157660-9f66-4c6b-b5fa-4fb9598b244f
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070640383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.1070640383
Directory	/workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2429217900
Short name	T986
Test name
Test status
Simulation time	103861531 ps
CPU time	1.92 seconds
Started	Jul 01 04:57:35 PM PDT 24
Finished	Jul 01 04:57:45 PM PDT 24
Peak memory	218480 kb
Host	smart-e1fc859f-2378-44b2-b798-af385149a788
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242921 7900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2429217900
Directory	/workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2856480411
Short name	T992
Test name
Test status
Simulation time	453280886 ps
CPU time	1.29 seconds
Started	Jul 01 04:57:38 PM PDT 24
Finished	Jul 01 04:57:47 PM PDT 24
Peak memory	208960 kb
Host	smart-8a521bca-6e3a-4948-9385-e89112548379
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856480411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_rw.2856480411
Directory	/workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3736137992
Short name	T974
Test name
Test status
Simulation time	76702914 ps
CPU time	1.32 seconds
Started	Jul 01 04:57:41 PM PDT 24
Finished	Jul 01 04:57:50 PM PDT 24
Peak memory	209188 kb
Host	smart-b9609c83-1f23-47f8-aa83-0da7d90df71d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736137992 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.3736137992
Directory	/workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1355304466
Short name	T951
Test name
Test status
Simulation time	31729827 ps
CPU time	1.15 seconds
Started	Jul 01 04:57:29 PM PDT 24
Finished	Jul 01 04:57:37 PM PDT 24
Peak memory	209136 kb
Host	smart-9de36f2a-fef4-4754-9b46-1e14e7bcf042
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355304466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl _same_csr_outstanding.1355304466
Directory	/workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1401209511
Short name	T978
Test name
Test status
Simulation time	313590910 ps
CPU time	2.67 seconds
Started	Jul 01 04:57:29 PM PDT 24
Finished	Jul 01 04:57:38 PM PDT 24
Peak memory	217348 kb
Host	smart-d945ceef-7b5e-4bdf-a175-964a32de9b97
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401209511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.1401209511
Directory	/workspace/3.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.74880178
Short name	T147
Test name
Test status
Simulation time	44605827 ps
CPU time	1.84 seconds
Started	Jul 01 04:57:28 PM PDT 24
Finished	Jul 01 04:57:36 PM PDT 24
Peak memory	221440 kb
Host	smart-b47b58fe-628c-4655-83cd-9e9e8eea9746
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74880178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_er r.74880178
Directory	/workspace/3.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.3147606878
Short name	T962
Test name
Test status
Simulation time	123167039 ps
CPU time	1.34 seconds
Started	Jul 01 04:57:47 PM PDT 24
Finished	Jul 01 04:57:58 PM PDT 24
Peak memory	209208 kb
Host	smart-5bf70c64-3783-4a36-90fd-96f5fbc8c041
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147606878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin g.3147606878
Directory	/workspace/4.lc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3457863848
Short name	T916
Test name
Test status
Simulation time	260284025 ps
CPU time	2.6 seconds
Started	Jul 01 04:57:36 PM PDT 24
Finished	Jul 01 04:57:47 PM PDT 24
Peak memory	209052 kb
Host	smart-8b633bfb-8a65-48fa-a306-11c58d4ed8c5
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457863848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas h.3457863848
Directory	/workspace/4.lc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3474585894
Short name	T937
Test name
Test status
Simulation time	88498792 ps
CPU time	1.04 seconds
Started	Jul 01 04:57:45 PM PDT 24
Finished	Jul 01 04:57:55 PM PDT 24
Peak memory	209120 kb
Host	smart-20fd98bf-b8b5-4a84-a3c7-3f0f446948e6
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474585894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese t.3474585894
Directory	/workspace/4.lc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.2944241455
Short name	T145
Test name
Test status
Simulation time	27405985 ps
CPU time	1.6 seconds
Started	Jul 01 04:57:45 PM PDT 24
Finished	Jul 01 04:57:56 PM PDT 24
Peak memory	217504 kb
Host	smart-40b5cfd6-1584-45a1-ae2c-db23ae27a320
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944241455 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.2944241455
Directory	/workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.4228780141
Short name	T195
Test name
Test status
Simulation time	14189409 ps
CPU time	1.09 seconds
Started	Jul 01 04:57:51 PM PDT 24
Finished	Jul 01 04:58:01 PM PDT 24
Peak memory	209104 kb
Host	smart-a064874f-d14f-49c5-b6bc-fc447d0cc8f7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228780141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.4228780141
Directory	/workspace/4.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1899044966
Short name	T985
Test name
Test status
Simulation time	123519989 ps
CPU time	1.61 seconds
Started	Jul 01 04:57:36 PM PDT 24
Finished	Jul 01 04:57:45 PM PDT 24
Peak memory	208940 kb
Host	smart-4eb2d57a-caec-44f3-880c-86dd6f766dc1
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899044966 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 4.lc_ctrl_jtag_alert_test.1899044966
Directory	/workspace/4.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1124826144
Short name	T966
Test name
Test status
Simulation time	1088000983 ps
CPU time	22.73 seconds
Started	Jul 01 04:57:36 PM PDT 24
Finished	Jul 01 04:58:07 PM PDT 24
Peak memory	208736 kb
Host	smart-8fb9907a-c144-441e-a30e-4d9807ae371f
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124826144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.1124826144
Directory	/workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.268786225
Short name	T939
Test name
Test status
Simulation time	1106663094 ps
CPU time	24.92 seconds
Started	Jul 01 04:57:39 PM PDT 24
Finished	Jul 01 04:58:12 PM PDT 24
Peak memory	216864 kb
Host	smart-e3534994-e9fa-48bf-9633-49ad9920e499
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268786225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.268786225
Directory	/workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2690318815
Short name	T988
Test name
Test status
Simulation time	653879437 ps
CPU time	2.37 seconds
Started	Jul 01 04:57:31 PM PDT 24
Finished	Jul 01 04:57:42 PM PDT 24
Peak memory	210492 kb
Host	smart-ecb47d78-4f69-479e-9917-2f7456f44366
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690318815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.2690318815
Directory	/workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1771079604
Short name	T984
Test name
Test status
Simulation time	75009024 ps
CPU time	2.46 seconds
Started	Jul 01 04:57:28 PM PDT 24
Finished	Jul 01 04:57:38 PM PDT 24
Peak memory	218108 kb
Host	smart-bc7ecda6-c486-40c5-85e9-09654d81c1f0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177107 9604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1771079604
Directory	/workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.969953722
Short name	T885
Test name
Test status
Simulation time	107945453 ps
CPU time	2.05 seconds
Started	Jul 01 04:57:31 PM PDT 24
Finished	Jul 01 04:57:42 PM PDT 24
Peak memory	217044 kb
Host	smart-e048f8e2-b0d7-465b-943e-17ddadb4d7d8
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969953722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_rw.969953722
Directory	/workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.4117245494
Short name	T890
Test name
Test status
Simulation time	38286714 ps
CPU time	1.9 seconds
Started	Jul 01 04:57:32 PM PDT 24
Finished	Jul 01 04:57:42 PM PDT 24
Peak memory	217324 kb
Host	smart-31a179a9-e2af-4f42-a30f-a89a6de01a93
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117245494 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.4117245494
Directory	/workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.584859252
Short name	T1000
Test name
Test status
Simulation time	17003191 ps
CPU time	1.19 seconds
Started	Jul 01 04:57:37 PM PDT 24
Finished	Jul 01 04:57:46 PM PDT 24
Peak memory	209076 kb
Host	smart-cd2a737b-7959-4951-8116-11b5053f0eb6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584859252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_ same_csr_outstanding.584859252
Directory	/workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.145312642
Short name	T998
Test name
Test status
Simulation time	392106307 ps
CPU time	2.32 seconds
Started	Jul 01 04:57:47 PM PDT 24
Finished	Jul 01 04:57:58 PM PDT 24
Peak memory	217308 kb
Host	smart-eca1b3bf-92b4-461c-8a81-643a3fd83b59
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145312642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.145312642
Directory	/workspace/4.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.4144979136
Short name	T140
Test name
Test status
Simulation time	958525538 ps
CPU time	2.76 seconds
Started	Jul 01 04:57:42 PM PDT 24
Finished	Jul 01 04:57:53 PM PDT 24
Peak memory	221856 kb
Host	smart-13be6300-02a4-4e7f-a3e8-6a7dc3fa9b3e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144979136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_ err.4144979136
Directory	/workspace/4.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3649128943
Short name	T888
Test name
Test status
Simulation time	250645620 ps
CPU time	1.76 seconds
Started	Jul 01 04:57:50 PM PDT 24
Finished	Jul 01 04:58:02 PM PDT 24
Peak memory	217452 kb
Host	smart-ad80830e-5f9d-424e-8e67-4e9b984630d1
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649128943 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.3649128943
Directory	/workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1199902543
Short name	T950
Test name
Test status
Simulation time	16497161 ps
CPU time	0.88 seconds
Started	Jul 01 04:57:46 PM PDT 24
Finished	Jul 01 04:57:56 PM PDT 24
Peak memory	209152 kb
Host	smart-881887b2-4aa9-47a7-8177-59370218d27f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199902543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.1199902543
Directory	/workspace/5.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.3969359318
Short name	T920
Test name
Test status
Simulation time	250034837 ps
CPU time	2.03 seconds
Started	Jul 01 04:57:36 PM PDT 24
Finished	Jul 01 04:57:47 PM PDT 24
Peak memory	208984 kb
Host	smart-7baa2b34-c932-47a6-b88b-2b4981b80fdc
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969359318 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 5.lc_ctrl_jtag_alert_test.3969359318
Directory	/workspace/5.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3346905268
Short name	T955
Test name
Test status
Simulation time	1592940181 ps
CPU time	5.15 seconds
Started	Jul 01 04:57:38 PM PDT 24
Finished	Jul 01 04:57:51 PM PDT 24
Peak memory	216948 kb
Host	smart-41cf06d3-b32a-4ca5-bd82-8cb7339eb3a4
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346905268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.3346905268
Directory	/workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2042990943
Short name	T946
Test name
Test status
Simulation time	4472162734 ps
CPU time	24.82 seconds
Started	Jul 01 04:57:37 PM PDT 24
Finished	Jul 01 04:58:10 PM PDT 24
Peak memory	209140 kb
Host	smart-18a9e970-47b3-4053-834e-ba2bcea4b02f
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042990943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.2042990943
Directory	/workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3912735080
Short name	T898
Test name
Test status
Simulation time	1821821485 ps
CPU time	1.81 seconds
Started	Jul 01 04:57:36 PM PDT 24
Finished	Jul 01 04:57:46 PM PDT 24
Peak memory	210500 kb
Host	smart-529a4726-6c7b-40ed-984b-3b470a2b4588
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912735080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.3912735080
Directory	/workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1712520832
Short name	T139
Test name
Test status
Simulation time	164020198 ps
CPU time	2.71 seconds
Started	Jul 01 04:57:46 PM PDT 24
Finished	Jul 01 04:57:57 PM PDT 24
Peak memory	217392 kb
Host	smart-c7bd9ec2-70ed-4393-b406-016098622942
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171252 0832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1712520832
Directory	/workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3212632651
Short name	T922
Test name
Test status
Simulation time	157912344 ps
CPU time	1.46 seconds
Started	Jul 01 04:57:48 PM PDT 24
Finished	Jul 01 04:57:59 PM PDT 24
Peak memory	217200 kb
Host	smart-96c536bb-c54e-4deb-9b55-55fca3dff603
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212632651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_rw.3212632651
Directory	/workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2102716784
Short name	T948
Test name
Test status
Simulation time	28673681 ps
CPU time	1.11 seconds
Started	Jul 01 04:57:36 PM PDT 24
Finished	Jul 01 04:57:45 PM PDT 24
Peak memory	209156 kb
Host	smart-180f2788-b564-4caa-9471-3da89810725d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102716784 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.2102716784
Directory	/workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2812023513
Short name	T200
Test name
Test status
Simulation time	19661127 ps
CPU time	0.96 seconds
Started	Jul 01 04:57:45 PM PDT 24
Finished	Jul 01 04:57:55 PM PDT 24
Peak memory	209100 kb
Host	smart-899d6723-35f9-4cf9-8961-231e0d977cf8
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812023513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl _same_csr_outstanding.2812023513
Directory	/workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2719702590
Short name	T969
Test name
Test status
Simulation time	125454408 ps
CPU time	2.11 seconds
Started	Jul 01 04:57:45 PM PDT 24
Finished	Jul 01 04:57:55 PM PDT 24
Peak memory	217464 kb
Host	smart-885c639b-60e0-47c4-ab89-6d216276f33d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719702590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.2719702590
Directory	/workspace/5.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.111484049
Short name	T181
Test name
Test status
Simulation time	49695078 ps
CPU time	0.99 seconds
Started	Jul 01 04:57:36 PM PDT 24
Finished	Jul 01 04:57:45 PM PDT 24
Peak memory	217464 kb
Host	smart-dd1ccff2-edcc-4e73-bcb8-85f386f2f27c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111484049 -assert nopostproc +UVM_TESTNAME= lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.111484049
Directory	/workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.2337851924
Short name	T171
Test name
Test status
Simulation time	63675961 ps
CPU time	1.15 seconds
Started	Jul 01 04:57:36 PM PDT 24
Finished	Jul 01 04:57:45 PM PDT 24
Peak memory	209092 kb
Host	smart-d673c8eb-9ed6-4c82-80c2-90e2ab7305d8
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337851924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.2337851924
Directory	/workspace/6.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1955030147
Short name	T158
Test name
Test status
Simulation time	17206007 ps
CPU time	0.94 seconds
Started	Jul 01 04:57:38 PM PDT 24
Finished	Jul 01 04:57:47 PM PDT 24
Peak memory	208956 kb
Host	smart-691aeddc-c67f-4abf-a0e9-975826edfbca
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955030147 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 6.lc_ctrl_jtag_alert_test.1955030147
Directory	/workspace/6.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3443039150
Short name	T977
Test name
Test status
Simulation time	1383117073 ps
CPU time	6.94 seconds
Started	Jul 01 04:57:43 PM PDT 24
Finished	Jul 01 04:57:58 PM PDT 24
Peak memory	208744 kb
Host	smart-a4c5a53d-d293-40e4-a686-3dad2ed6a70a
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443039150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.3443039150
Directory	/workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3042903360
Short name	T961
Test name
Test status
Simulation time	14669955129 ps
CPU time	10.8 seconds
Started	Jul 01 04:57:40 PM PDT 24
Finished	Jul 01 04:57:58 PM PDT 24
Peak memory	217116 kb
Host	smart-947aac21-c77b-4f58-885c-49b09400b9c5
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042903360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.3042903360
Directory	/workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1693528159
Short name	T156
Test name
Test status
Simulation time	283405160 ps
CPU time	1.36 seconds
Started	Jul 01 04:57:35 PM PDT 24
Finished	Jul 01 04:57:45 PM PDT 24
Peak memory	210612 kb
Host	smart-f558cc2f-b86e-41cd-ae66-3fa15a84e577
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693528159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.1693528159
Directory	/workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1901759192
Short name	T967
Test name
Test status
Simulation time	217446401 ps
CPU time	2.27 seconds
Started	Jul 01 04:57:42 PM PDT 24
Finished	Jul 01 04:57:52 PM PDT 24
Peak memory	221472 kb
Host	smart-a4c4c0f1-2975-4f68-a601-43cac774f2c3
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190175 9192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1901759192
Directory	/workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3719573893
Short name	T154
Test name
Test status
Simulation time	101345961 ps
CPU time	1.71 seconds
Started	Jul 01 04:57:35 PM PDT 24
Finished	Jul 01 04:57:45 PM PDT 24
Peak memory	208848 kb
Host	smart-ff8cfcee-6f0b-4ffa-af42-bbc489abac4c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719573893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_rw.3719573893
Directory	/workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.599370356
Short name	T997
Test name
Test status
Simulation time	47433240 ps
CPU time	1.13 seconds
Started	Jul 01 04:57:40 PM PDT 24
Finished	Jul 01 04:57:49 PM PDT 24
Peak memory	217428 kb
Host	smart-1df26b80-a1d1-41e1-bbea-047e762e4f8d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599370356 -assert nopostproc +UVM_TESTNAM E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.599370356
Directory	/workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.337823711
Short name	T936
Test name
Test status
Simulation time	28553328 ps
CPU time	1.09 seconds
Started	Jul 01 04:57:46 PM PDT 24
Finished	Jul 01 04:57:55 PM PDT 24
Peak memory	217276 kb
Host	smart-d557a444-7486-4d7d-9d2a-b2d7a11b765a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337823711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_ same_csr_outstanding.337823711
Directory	/workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.4143924766
Short name	T883
Test name
Test status
Simulation time	433241611 ps
CPU time	4.46 seconds
Started	Jul 01 04:57:44 PM PDT 24
Finished	Jul 01 04:57:57 PM PDT 24
Peak memory	217276 kb
Host	smart-b1022d74-56c7-4ae4-a131-1d9fbaf5c8b9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143924766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.4143924766
Directory	/workspace/6.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.869984851
Short name	T137
Test name
Test status
Simulation time	586627627 ps
CPU time	3.32 seconds
Started	Jul 01 04:57:45 PM PDT 24
Finished	Jul 01 04:57:58 PM PDT 24
Peak memory	217352 kb
Host	smart-1a627fc0-0a33-4494-8607-8abdeceaf079
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869984851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_e rr.869984851
Directory	/workspace/6.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3657466976
Short name	T1003
Test name
Test status
Simulation time	50629588 ps
CPU time	1.14 seconds
Started	Jul 01 04:57:45 PM PDT 24
Finished	Jul 01 04:57:54 PM PDT 24
Peak memory	217444 kb
Host	smart-7ecc7027-1041-49ea-b010-08cc784933be
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657466976 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.3657466976
Directory	/workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2626350357
Short name	T191
Test name
Test status
Simulation time	44429084 ps
CPU time	1.04 seconds
Started	Jul 01 04:57:48 PM PDT 24
Finished	Jul 01 04:57:58 PM PDT 24
Peak memory	209228 kb
Host	smart-137d1cfa-14cb-477f-85fc-ca19a9cdadd7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626350357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.2626350357
Directory	/workspace/7.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3573933849
Short name	T896
Test name
Test status
Simulation time	280606030 ps
CPU time	1.63 seconds
Started	Jul 01 04:57:36 PM PDT 24
Finished	Jul 01 04:57:46 PM PDT 24
Peak memory	208984 kb
Host	smart-a83ec262-a9fb-4d7e-97e5-a682e7a33d46
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573933849 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 7.lc_ctrl_jtag_alert_test.3573933849
Directory	/workspace/7.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3835401972
Short name	T965
Test name
Test status
Simulation time	3279188685 ps
CPU time	9.11 seconds
Started	Jul 01 04:57:37 PM PDT 24
Finished	Jul 01 04:57:54 PM PDT 24
Peak memory	209172 kb
Host	smart-f054521c-1898-4061-8612-f786a7a4cdbd
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835401972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.3835401972
Directory	/workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2266874877
Short name	T159
Test name
Test status
Simulation time	3188920904 ps
CPU time	6.73 seconds
Started	Jul 01 04:57:36 PM PDT 24
Finished	Jul 01 04:57:51 PM PDT 24
Peak memory	209144 kb
Host	smart-046374a6-8fd9-4aa0-aa2c-17719d293105
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266874877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.2266874877
Directory	/workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3005499075
Short name	T909
Test name
Test status
Simulation time	350271289 ps
CPU time	1.26 seconds
Started	Jul 01 04:57:35 PM PDT 24
Finished	Jul 01 04:57:44 PM PDT 24
Peak memory	210504 kb
Host	smart-adce2c1e-ebc6-47ee-b769-e5d5c517deb6
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005499075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.3005499075
Directory	/workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.28980188
Short name	T935
Test name
Test status
Simulation time	149687280 ps
CPU time	4.3 seconds
Started	Jul 01 04:57:37 PM PDT 24
Finished	Jul 01 04:57:49 PM PDT 24
Peak memory	217888 kb
Host	smart-139fc3a4-8307-4601-be55-374764210e73
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289801 88 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.28980188
Directory	/workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3049126379
Short name	T155
Test name
Test status
Simulation time	272679009 ps
CPU time	2.13 seconds
Started	Jul 01 04:57:36 PM PDT 24
Finished	Jul 01 04:57:46 PM PDT 24
Peak memory	209056 kb
Host	smart-7eee7316-15c0-4cf0-a6e1-44e5fa79828a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049126379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_rw.3049126379
Directory	/workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.345720162
Short name	T993
Test name
Test status
Simulation time	90024209 ps
CPU time	1.31 seconds
Started	Jul 01 04:57:50 PM PDT 24
Finished	Jul 01 04:58:01 PM PDT 24
Peak memory	209244 kb
Host	smart-ff604c08-ec6d-419c-849d-bfc7f5714a1a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345720162 -assert nopostproc +UVM_TESTNAM E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.345720162
Directory	/workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1339005308
Short name	T206
Test name
Test status
Simulation time	46527457 ps
CPU time	1.55 seconds
Started	Jul 01 04:57:47 PM PDT 24
Finished	Jul 01 04:57:57 PM PDT 24
Peak memory	217304 kb
Host	smart-ce2c8289-5b76-4632-9b4d-8d337e17863a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339005308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl _same_csr_outstanding.1339005308
Directory	/workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.591869677
Short name	T895
Test name
Test status
Simulation time	365276205 ps
CPU time	1.95 seconds
Started	Jul 01 04:57:49 PM PDT 24
Finished	Jul 01 04:58:01 PM PDT 24
Peak memory	217192 kb
Host	smart-91b5fcf7-0a55-441c-a544-3e7d90b5bbef
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591869677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.591869677
Directory	/workspace/7.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2841005953
Short name	T153
Test name
Test status
Simulation time	86375836 ps
CPU time	2.93 seconds
Started	Jul 01 04:57:45 PM PDT 24
Finished	Jul 01 04:57:57 PM PDT 24
Peak memory	221864 kb
Host	smart-8f3c3ab5-0e58-4800-b498-fc2e44247ae7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841005953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_ err.2841005953
Directory	/workspace/7.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.2213205086
Short name	T899
Test name
Test status
Simulation time	104878132 ps
CPU time	1.47 seconds
Started	Jul 01 04:57:55 PM PDT 24
Finished	Jul 01 04:58:06 PM PDT 24
Peak memory	218648 kb
Host	smart-7ccaaa83-ee10-4913-b02d-56bd05b666c6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213205086 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.2213205086
Directory	/workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1774687567
Short name	T190
Test name
Test status
Simulation time	17066658 ps
CPU time	0.97 seconds
Started	Jul 01 04:57:48 PM PDT 24
Finished	Jul 01 04:57:59 PM PDT 24
Peak memory	209076 kb
Host	smart-41026622-35b1-4ead-8c25-b78cca1fd04d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774687567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.1774687567
Directory	/workspace/8.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3386402339
Short name	T958
Test name
Test status
Simulation time	80677694 ps
CPU time	1.19 seconds
Started	Jul 01 04:57:55 PM PDT 24
Finished	Jul 01 04:58:05 PM PDT 24
Peak memory	208432 kb
Host	smart-cf1faad4-4ee7-446a-9757-c99d743554ac
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386402339 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 8.lc_ctrl_jtag_alert_test.3386402339
Directory	/workspace/8.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.4021851395
Short name	T983
Test name
Test status
Simulation time	1605195287 ps
CPU time	10.96 seconds
Started	Jul 01 04:57:44 PM PDT 24
Finished	Jul 01 04:58:03 PM PDT 24
Peak memory	208832 kb
Host	smart-f07c52a0-0166-4b6d-9927-63efe264bb9a
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021851395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.4021851395
Directory	/workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.738169481
Short name	T904
Test name
Test status
Simulation time	1518814466 ps
CPU time	20.32 seconds
Started	Jul 01 04:57:53 PM PDT 24
Finished	Jul 01 04:58:23 PM PDT 24
Peak memory	209060 kb
Host	smart-305cb948-31f7-49c8-9c3e-f970c1d30c31
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738169481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.738169481
Directory	/workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.4042057230
Short name	T953
Test name
Test status
Simulation time	347631034 ps
CPU time	1.45 seconds
Started	Jul 01 04:57:45 PM PDT 24
Finished	Jul 01 04:57:56 PM PDT 24
Peak memory	210136 kb
Host	smart-4ea89ee5-1cc5-47e9-a14f-781362adf727
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042057230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.4042057230
Directory	/workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3786656781
Short name	T918
Test name
Test status
Simulation time	469581071 ps
CPU time	2.03 seconds
Started	Jul 01 04:57:54 PM PDT 24
Finished	Jul 01 04:58:05 PM PDT 24
Peak memory	218532 kb
Host	smart-44bec0a2-fa19-4f03-bdf2-56a1a278d91f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378665 6781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3786656781
Directory	/workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2076564925
Short name	T887
Test name
Test status
Simulation time	138514532 ps
CPU time	1.06 seconds
Started	Jul 01 04:57:54 PM PDT 24
Finished	Jul 01 04:58:05 PM PDT 24
Peak memory	209036 kb
Host	smart-3bf6cf21-451f-4bbc-9702-f1d8cefdf1b1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076564925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_rw.2076564925
Directory	/workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1219575344
Short name	T908
Test name
Test status
Simulation time	22565553 ps
CPU time	1.23 seconds
Started	Jul 01 04:57:48 PM PDT 24
Finished	Jul 01 04:57:58 PM PDT 24
Peak memory	209232 kb
Host	smart-889c9cd1-3fcf-4f91-8a5d-24184cbaacbb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219575344 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.1219575344
Directory	/workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.2479419197
Short name	T205
Test name
Test status
Simulation time	38972547 ps
CPU time	1.3 seconds
Started	Jul 01 04:57:47 PM PDT 24
Finished	Jul 01 04:57:58 PM PDT 24
Peak memory	211284 kb
Host	smart-9cd2c4a5-d2c7-4caf-b4ae-f2e0e2ca1f46
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479419197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl _same_csr_outstanding.2479419197
Directory	/workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.769770748
Short name	T990
Test name
Test status
Simulation time	656119876 ps
CPU time	5.73 seconds
Started	Jul 01 04:57:48 PM PDT 24
Finished	Jul 01 04:58:03 PM PDT 24
Peak memory	217268 kb
Host	smart-7e361bb1-4816-48c0-ad62-41e7b943c8e0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769770748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.769770748
Directory	/workspace/8.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.955048119
Short name	T126
Test name
Test status
Simulation time	111933480 ps
CPU time	4.14 seconds
Started	Jul 01 04:57:44 PM PDT 24
Finished	Jul 01 04:57:57 PM PDT 24
Peak memory	217324 kb
Host	smart-c0989f6f-da0e-4337-9f0f-d12b605d7034
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955048119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_e rr.955048119
Directory	/workspace/8.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2407130585
Short name	T972
Test name
Test status
Simulation time	37398420 ps
CPU time	1.53 seconds
Started	Jul 01 04:57:54 PM PDT 24
Finished	Jul 01 04:58:05 PM PDT 24
Peak memory	219196 kb
Host	smart-d1cec912-9626-4725-8ea0-9afa18ceee11
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407130585 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.2407130585
Directory	/workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3721042744
Short name	T879
Test name
Test status
Simulation time	15759056 ps
CPU time	1.12 seconds
Started	Jul 01 04:57:45 PM PDT 24
Finished	Jul 01 04:57:54 PM PDT 24
Peak memory	208912 kb
Host	smart-c01fdf63-a63f-447b-b543-a19dcef91cdc
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721042744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.3721042744
Directory	/workspace/9.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.3462825919
Short name	T891
Test name
Test status
Simulation time	30624041 ps
CPU time	1.4 seconds
Started	Jul 01 04:57:52 PM PDT 24
Finished	Jul 01 04:58:03 PM PDT 24
Peak memory	208960 kb
Host	smart-952749c0-0206-4f1d-b56e-43a4e483f987
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462825919 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 9.lc_ctrl_jtag_alert_test.3462825919
Directory	/workspace/9.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.234123522
Short name	T971
Test name
Test status
Simulation time	2295766024 ps
CPU time	13.45 seconds
Started	Jul 01 04:57:51 PM PDT 24
Finished	Jul 01 04:58:14 PM PDT 24
Peak memory	216964 kb
Host	smart-dd195966-3167-4671-8e89-f3aedb1ce5a9
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234123522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 9.lc_ctrl_jtag_csr_aliasing.234123522
Directory	/workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1458912206
Short name	T964
Test name
Test status
Simulation time	768480606 ps
CPU time	10.23 seconds
Started	Jul 01 04:57:48 PM PDT 24
Finished	Jul 01 04:58:08 PM PDT 24
Peak memory	209040 kb
Host	smart-db12e274-f233-4bf2-878b-b5a3318e2998
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458912206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.1458912206
Directory	/workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.156913979
Short name	T923
Test name
Test status
Simulation time	692271306 ps
CPU time	2.61 seconds
Started	Jul 01 04:57:54 PM PDT 24
Finished	Jul 01 04:58:06 PM PDT 24
Peak memory	217248 kb
Host	smart-2306b007-6fdd-4cb5-b351-c0d4f4062e00
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156913979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.156913979
Directory	/workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3526776400
Short name	T917
Test name
Test status
Simulation time	631731419 ps
CPU time	1.32 seconds
Started	Jul 01 04:57:44 PM PDT 24
Finished	Jul 01 04:57:54 PM PDT 24
Peak memory	217528 kb
Host	smart-9c51e42c-eb97-4937-a4a6-318999d37e4d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352677 6400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3526776400
Directory	/workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2660310110
Short name	T945
Test name
Test status
Simulation time	81719954 ps
CPU time	2.56 seconds
Started	Jul 01 04:57:43 PM PDT 24
Finished	Jul 01 04:57:53 PM PDT 24
Peak memory	209060 kb
Host	smart-4072c422-1fe5-4ff1-b74c-f4c9f7773032
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660310110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_rw.2660310110
Directory	/workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2904939877
Short name	T134
Test name
Test status
Simulation time	49284306 ps
CPU time	1.18 seconds
Started	Jul 01 04:57:53 PM PDT 24
Finished	Jul 01 04:58:04 PM PDT 24
Peak memory	217404 kb
Host	smart-101960c2-20d5-40a1-91ae-2030d93861ce
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904939877 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.2904939877
Directory	/workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.1605409910
Short name	T976
Test name
Test status
Simulation time	85087679 ps
CPU time	1.56 seconds
Started	Jul 01 04:57:50 PM PDT 24
Finished	Jul 01 04:58:01 PM PDT 24
Peak memory	217404 kb
Host	smart-dfe2639d-f10e-48ef-ad81-152ea19d10d1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605409910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl _same_csr_outstanding.1605409910
Directory	/workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3026222861
Short name	T996
Test name
Test status
Simulation time	130763614 ps
CPU time	5.04 seconds
Started	Jul 01 04:57:47 PM PDT 24
Finished	Jul 01 04:58:02 PM PDT 24
Peak memory	217264 kb
Host	smart-83c53fd0-258d-4835-9d80-6db155552370
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026222861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.3026222861
Directory	/workspace/9.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.584820336
Short name	T214
Test name
Test status
Simulation time	122931624 ps
CPU time	2.86 seconds
Started	Jul 01 04:57:50 PM PDT 24
Finished	Jul 01 04:58:02 PM PDT 24
Peak memory	217360 kb
Host	smart-880399bc-fb75-49df-a46f-f81b7a35d710
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584820336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_e rr.584820336
Directory	/workspace/9.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/0.lc_ctrl_alert_test.2615844460
Short name	T804
Test name
Test status
Simulation time	18205488 ps
CPU time	1.13 seconds
Started	Jul 01 06:43:29 PM PDT 24
Finished	Jul 01 06:43:32 PM PDT 24
Peak memory	209380 kb
Host	smart-6debcc3c-48d2-47da-9d5b-2f26008b17a7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615844460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.2615844460
Directory	/workspace/0.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/0.lc_ctrl_claim_transition_if.4020809686
Short name	T814
Test name
Test status
Simulation time	37162874 ps
CPU time	0.81 seconds
Started	Jul 01 06:43:23 PM PDT 24
Finished	Jul 01 06:43:25 PM PDT 24
Peak memory	209284 kb
Host	smart-7028dfd7-48d2-4bc3-ad83-33a1d8a14d45
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4020809686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.4020809686
Directory	/workspace/0.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_access.3901763660
Short name	T455
Test name
Test status
Simulation time	263346628 ps
CPU time	6.3 seconds
Started	Jul 01 06:43:21 PM PDT 24
Finished	Jul 01 06:43:30 PM PDT 24
Peak memory	217548 kb
Host	smart-13cbbbba-ce7c-4f27-adf4-a2bc1abc6db9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901763660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.3901763660
Directory	/workspace/0.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_priority.1758299113
Short name	T185
Test name
Test status
Simulation time	760377425 ps
CPU time	4.1 seconds
Started	Jul 01 06:43:21 PM PDT 24
Finished	Jul 01 06:43:27 PM PDT 24
Peak memory	217936 kb
Host	smart-4d615482-874a-49ef-99c6-ef9bb44aef4d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758299113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.1 758299113
Directory	/workspace/0.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.1552089840
Short name	T306
Test name
Test status
Simulation time	1185034085 ps
CPU time	9.19 seconds
Started	Jul 01 06:43:21 PM PDT 24
Finished	Jul 01 06:43:32 PM PDT 24
Peak memory	218644 kb
Host	smart-af5ef304-3cb8-4a11-bf6c-a9bbf8058471
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552089840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag _prog_failure.1552089840
Directory	/workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.582524678
Short name	T345
Test name
Test status
Simulation time	1055720190 ps
CPU time	32.24 seconds
Started	Jul 01 06:43:28 PM PDT 24
Finished	Jul 01 06:44:01 PM PDT 24
Peak memory	218016 kb
Host	smart-6bd30d4d-04ff-403d-9093-cab0f1ac6879
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582524678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j tag_regwen_during_op.582524678
Directory	/workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_smoke.4203729207
Short name	T490
Test name
Test status
Simulation time	1009229633 ps
CPU time	7.76 seconds
Started	Jul 01 06:43:20 PM PDT 24
Finished	Jul 01 06:43:29 PM PDT 24
Peak memory	218064 kb
Host	smart-b16c6314-db24-4449-a3d4-648da1decfd8
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203729207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke. 4203729207
Directory	/workspace/0.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_state_failure.2004790397
Short name	T756
Test name
Test status
Simulation time	3773051447 ps
CPU time	32.18 seconds
Started	Jul 01 06:43:21 PM PDT 24
Finished	Jul 01 06:43:54 PM PDT 24
Peak memory	251440 kb
Host	smart-c4b9ac4a-9152-4e06-baad-76fffd303dde
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004790397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta g_state_failure.2004790397
Directory	/workspace/0.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.2301050993
Short name	T406
Test name
Test status
Simulation time	858106036 ps
CPU time	24.75 seconds
Started	Jul 01 06:43:22 PM PDT 24
Finished	Jul 01 06:43:49 PM PDT 24
Peak memory	226440 kb
Host	smart-f0fcab65-dbc0-423f-a685-d2ac2071f4ce
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301050993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_ jtag_state_post_trans.2301050993
Directory	/workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/0.lc_ctrl_prog_failure.3346882211
Short name	T325
Test name
Test status
Simulation time	56145354 ps
CPU time	3.29 seconds
Started	Jul 01 06:43:20 PM PDT 24
Finished	Jul 01 06:43:24 PM PDT 24
Peak memory	218632 kb
Host	smart-31f70443-a2fa-4972-8715-cc8b8ba44a5d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3346882211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.3346882211
Directory	/workspace/0.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/0.lc_ctrl_regwen_during_op.2975018595
Short name	T642
Test name
Test status
Simulation time	920082540 ps
CPU time	12.96 seconds
Started	Jul 01 06:43:19 PM PDT 24
Finished	Jul 01 06:43:33 PM PDT 24
Peak memory	215012 kb
Host	smart-029bf589-7770-4afa-8e5a-b34dc0dd411a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2975018595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.2975018595
Directory	/workspace/0.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/0.lc_ctrl_sec_mubi.2878738588
Short name	T280
Test name
Test status
Simulation time	184599270 ps
CPU time	9.56 seconds
Started	Jul 01 06:43:29 PM PDT 24
Finished	Jul 01 06:43:40 PM PDT 24
Peak memory	226532 kb
Host	smart-790f0134-5024-426e-b3b8-5b04151cd273
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878738588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.2878738588
Directory	/workspace/0.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/0.lc_ctrl_sec_token_digest.4093710387
Short name	T489
Test name
Test status
Simulation time	572081989 ps
CPU time	13.17 seconds
Started	Jul 01 06:43:29 PM PDT 24
Finished	Jul 01 06:43:44 PM PDT 24
Peak memory	218608 kb
Host	smart-7847d548-3387-4281-b62b-65d1fef4bb9b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093710387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di gest.4093710387
Directory	/workspace/0.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/0.lc_ctrl_sec_token_mux.4238743757
Short name	T761
Test name
Test status
Simulation time	1413531775 ps
CPU time	8.6 seconds
Started	Jul 01 06:43:27 PM PDT 24
Finished	Jul 01 06:43:37 PM PDT 24
Peak memory	218600 kb
Host	smart-def0dde5-0b4a-4743-a300-7683bedf8022
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238743757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.4 238743757
Directory	/workspace/0.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/0.lc_ctrl_security_escalation.3299674148
Short name	T785
Test name
Test status
Simulation time	921090130 ps
CPU time	10.94 seconds
Started	Jul 01 06:43:21 PM PDT 24
Finished	Jul 01 06:43:34 PM PDT 24
Peak memory	226420 kb
Host	smart-093bba3a-e17b-4849-a82d-c1e9536ab860
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3299674148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.3299674148
Directory	/workspace/0.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/0.lc_ctrl_smoke.691343473
Short name	T541
Test name
Test status
Simulation time	141163755 ps
CPU time	2.53 seconds
Started	Jul 01 06:43:25 PM PDT 24
Finished	Jul 01 06:43:28 PM PDT 24
Peak memory	214676 kb
Host	smart-2b8986cd-b3fc-487f-910d-5edf7fbffff9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=691343473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.691343473
Directory	/workspace/0.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/0.lc_ctrl_state_failure.2685988119
Short name	T719
Test name
Test status
Simulation time	394595174 ps
CPU time	20.27 seconds
Started	Jul 01 06:43:21 PM PDT 24
Finished	Jul 01 06:43:43 PM PDT 24
Peak memory	251348 kb
Host	smart-20fac6eb-82e4-4dcd-85b8-0ee5e07fb1ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2685988119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.2685988119
Directory	/workspace/0.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/0.lc_ctrl_state_post_trans.3458368719
Short name	T253
Test name
Test status
Simulation time	64407561 ps
CPU time	8.12 seconds
Started	Jul 01 06:43:21 PM PDT 24
Finished	Jul 01 06:43:30 PM PDT 24
Peak memory	251384 kb
Host	smart-9b16f37c-c675-44d8-a4e9-d4498c6380eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3458368719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.3458368719
Directory	/workspace/0.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/0.lc_ctrl_stress_all.2561440899
Short name	T725
Test name
Test status
Simulation time	23327909704 ps
CPU time	118.5 seconds
Started	Jul 01 06:43:27 PM PDT 24
Finished	Jul 01 06:45:27 PM PDT 24
Peak memory	314836 kb
Host	smart-41bb762d-2702-447d-8ba4-8214266300b3
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561440899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all.2561440899
Directory	/workspace/0.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.3918368996
Short name	T356
Test name
Test status
Simulation time	38847546 ps
CPU time	0.79 seconds
Started	Jul 01 06:43:22 PM PDT 24
Finished	Jul 01 06:43:25 PM PDT 24
Peak memory	209192 kb
Host	smart-ae1af3a8-652b-43dc-9627-f35acebd2002
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918368996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct rl_volatile_unlock_smoke.3918368996
Directory	/workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/1.lc_ctrl_alert_test.3649525250
Short name	T788
Test name
Test status
Simulation time	25599212 ps
CPU time	0.89 seconds
Started	Jul 01 06:43:46 PM PDT 24
Finished	Jul 01 06:43:48 PM PDT 24
Peak memory	209420 kb
Host	smart-6c1c9122-7c76-4cb1-bfcc-a54f197f0e5d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649525250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.3649525250
Directory	/workspace/1.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/1.lc_ctrl_errors.2914409207
Short name	T106
Test name
Test status
Simulation time	1062278230 ps
CPU time	12.96 seconds
Started	Jul 01 06:43:44 PM PDT 24
Finished	Jul 01 06:43:58 PM PDT 24
Peak memory	218636 kb
Host	smart-0812e499-08fc-4338-b0aa-d55f60277f7d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2914409207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.2914409207
Directory	/workspace/1.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_access.1279138642
Short name	T616
Test name
Test status
Simulation time	4930239017 ps
CPU time	10.88 seconds
Started	Jul 01 06:43:42 PM PDT 24
Finished	Jul 01 06:43:54 PM PDT 24
Peak memory	218104 kb
Host	smart-c580079d-e6a0-4cee-a00d-11a437cb8d3c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279138642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.1279138642
Directory	/workspace/1.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_errors.4151432277
Short name	T358
Test name
Test status
Simulation time	3968042090 ps
CPU time	103.64 seconds
Started	Jul 01 06:43:44 PM PDT 24
Finished	Jul 01 06:45:28 PM PDT 24
Peak memory	219528 kb
Host	smart-00755693-0f7f-4fed-8938-1e959e1b42a2
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151432277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er rors.4151432277
Directory	/workspace/1.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_priority.3759946408
Short name	T14
Test name
Test status
Simulation time	3810044882 ps
CPU time	23.09 seconds
Started	Jul 01 06:43:44 PM PDT 24
Finished	Jul 01 06:44:09 PM PDT 24
Peak memory	218316 kb
Host	smart-23bd556c-49b5-48c1-bd89-2276ecbd0ede
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759946408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.3 759946408
Directory	/workspace/1.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.414193609
Short name	T390
Test name
Test status
Simulation time	415110132 ps
CPU time	7.23 seconds
Started	Jul 01 06:43:44 PM PDT 24
Finished	Jul 01 06:43:52 PM PDT 24
Peak memory	218496 kb
Host	smart-a79af720-6a75-4dce-96e0-2ad7b0e34db5
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414193609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_ prog_failure.414193609
Directory	/workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.1941730173
Short name	T349
Test name
Test status
Simulation time	4733544019 ps
CPU time	34.84 seconds
Started	Jul 01 06:43:45 PM PDT 24
Finished	Jul 01 06:44:22 PM PDT 24
Peak memory	218048 kb
Host	smart-0e8791c2-0af8-47f6-b1e5-b38362da3ee4
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941730173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_ jtag_regwen_during_op.1941730173
Directory	/workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_smoke.774284175
Short name	T295
Test name
Test status
Simulation time	152825856 ps
CPU time	2.83 seconds
Started	Jul 01 06:43:44 PM PDT 24
Finished	Jul 01 06:43:49 PM PDT 24
Peak memory	218012 kb
Host	smart-3d6456ad-3596-488c-b404-4ca1f03e7ed4
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774284175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.774284175
Directory	/workspace/1.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_state_failure.1923222602
Short name	T466
Test name
Test status
Simulation time	13468900082 ps
CPU time	57.08 seconds
Started	Jul 01 06:43:44 PM PDT 24
Finished	Jul 01 06:44:43 PM PDT 24
Peak memory	282764 kb
Host	smart-91260511-bfd2-4784-8dc0-10cdfe000b3f
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923222602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta g_state_failure.1923222602
Directory	/workspace/1.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.824799127
Short name	T278
Test name
Test status
Simulation time	671487552 ps
CPU time	23.07 seconds
Started	Jul 01 06:43:46 PM PDT 24
Finished	Jul 01 06:44:11 PM PDT 24
Peak memory	248204 kb
Host	smart-d492479e-05b5-415d-819d-c0a97c9c5f13
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824799127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_j tag_state_post_trans.824799127
Directory	/workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/1.lc_ctrl_prog_failure.1100310052
Short name	T520
Test name
Test status
Simulation time	350188078 ps
CPU time	2.94 seconds
Started	Jul 01 06:43:28 PM PDT 24
Finished	Jul 01 06:43:32 PM PDT 24
Peak memory	218628 kb
Host	smart-6efc73f8-6ecc-4cc2-abde-63e51c0cf0cc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1100310052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.1100310052
Directory	/workspace/1.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/1.lc_ctrl_regwen_during_op.3238006639
Short name	T208
Test name
Test status
Simulation time	307710720 ps
CPU time	18.27 seconds
Started	Jul 01 06:43:43 PM PDT 24
Finished	Jul 01 06:44:03 PM PDT 24
Peak memory	218092 kb
Host	smart-0aaef418-7226-487c-ab3b-981bad1e12e9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3238006639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.3238006639
Directory	/workspace/1.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/1.lc_ctrl_sec_cm.4035919504
Short name	T91
Test name
Test status
Simulation time	403435972 ps
CPU time	21.79 seconds
Started	Jul 01 06:43:42 PM PDT 24
Finished	Jul 01 06:44:05 PM PDT 24
Peak memory	280948 kb
Host	smart-29edd8c8-e0ae-4f9d-8732-cb338fa62391
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035919504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.4035919504
Directory	/workspace/1.lc_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/1.lc_ctrl_sec_mubi.2794562628
Short name	T508
Test name
Test status
Simulation time	1597409127 ps
CPU time	11.75 seconds
Started	Jul 01 06:43:43 PM PDT 24
Finished	Jul 01 06:43:56 PM PDT 24
Peak memory	219376 kb
Host	smart-829f5f16-6f90-4bc7-ba6d-4c17cf355783
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794562628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.2794562628
Directory	/workspace/1.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/1.lc_ctrl_sec_token_digest.1780100940
Short name	T563
Test name
Test status
Simulation time	1451082947 ps
CPU time	14.38 seconds
Started	Jul 01 06:43:43 PM PDT 24
Finished	Jul 01 06:43:59 PM PDT 24
Peak memory	218680 kb
Host	smart-3e2f62a4-5d58-40cf-937a-bb97295ef5e2
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780100940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di gest.1780100940
Directory	/workspace/1.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/1.lc_ctrl_sec_token_mux.1108298089
Short name	T728
Test name
Test status
Simulation time	4104552397 ps
CPU time	11.34 seconds
Started	Jul 01 06:43:44 PM PDT 24
Finished	Jul 01 06:43:57 PM PDT 24
Peak memory	226420 kb
Host	smart-eb30c5a9-9398-4392-a490-f4f6aeb508d4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108298089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.1 108298089
Directory	/workspace/1.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/1.lc_ctrl_smoke.1707059869
Short name	T457
Test name
Test status
Simulation time	100079100 ps
CPU time	2.02 seconds
Started	Jul 01 06:43:23 PM PDT 24
Finished	Jul 01 06:43:27 PM PDT 24
Peak memory	214596 kb
Host	smart-6f91f119-fe8d-4d20-a185-e406b2e89605
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1707059869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.1707059869
Directory	/workspace/1.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/1.lc_ctrl_state_failure.1742602579
Short name	T477
Test name
Test status
Simulation time	1509322834 ps
CPU time	29.68 seconds
Started	Jul 01 06:43:28 PM PDT 24
Finished	Jul 01 06:43:59 PM PDT 24
Peak memory	251340 kb
Host	smart-144410c2-967e-427f-94e5-b371ac4e9a80
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1742602579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.1742602579
Directory	/workspace/1.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/1.lc_ctrl_state_post_trans.1920150785
Short name	T385
Test name
Test status
Simulation time	1257880898 ps
CPU time	2.74 seconds
Started	Jul 01 06:43:27 PM PDT 24
Finished	Jul 01 06:43:31 PM PDT 24
Peak memory	222596 kb
Host	smart-caa10315-802e-44ab-a582-e64c2196f3fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1920150785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.1920150785
Directory	/workspace/1.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.2797390529
Short name	T781
Test name
Test status
Simulation time	30969816468 ps
CPU time	1025.66 seconds
Started	Jul 01 06:43:46 PM PDT 24
Finished	Jul 01 07:00:53 PM PDT 24
Peak memory	277848 kb
Host	smart-10b745b3-86a0-4c87-9c60-fc78f2013ed0
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2797390529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all_with_rand_reset.2797390529
Directory	/workspace/1.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.3999678883
Short name	T593
Test name
Test status
Simulation time	42346138 ps
CPU time	0.88 seconds
Started	Jul 01 06:43:29 PM PDT 24
Finished	Jul 01 06:43:32 PM PDT 24
Peak memory	212224 kb
Host	smart-8fdbff50-5e68-4026-b4ba-8f0b985e9142
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999678883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct rl_volatile_unlock_smoke.3999678883
Directory	/workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/10.lc_ctrl_alert_test.463174084
Short name	T323
Test name
Test status
Simulation time	35787748 ps
CPU time	0.95 seconds
Started	Jul 01 06:45:05 PM PDT 24
Finished	Jul 01 06:45:09 PM PDT 24
Peak memory	209512 kb
Host	smart-ad60beba-de8c-4e0b-b86c-6349ec37a4bf
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463174084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.463174084
Directory	/workspace/10.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/10.lc_ctrl_errors.964485799
Short name	T226
Test name
Test status
Simulation time	295679190 ps
CPU time	10.97 seconds
Started	Jul 01 06:45:05 PM PDT 24
Finished	Jul 01 06:45:19 PM PDT 24
Peak memory	218636 kb
Host	smart-54d352fa-9a7d-4592-94cc-30ad62a967d3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=964485799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.964485799
Directory	/workspace/10.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/10.lc_ctrl_jtag_access.4000777310
Short name	T657
Test name
Test status
Simulation time	6783294901 ps
CPU time	6.44 seconds
Started	Jul 01 06:45:04 PM PDT 24
Finished	Jul 01 06:45:13 PM PDT 24
Peak memory	218100 kb
Host	smart-c9db2bfe-4fc8-477a-9d99-32a32f4141ec
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000777310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.4000777310
Directory	/workspace/10.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/10.lc_ctrl_jtag_errors.664708782
Short name	T726
Test name
Test status
Simulation time	2172547827 ps
CPU time	20.46 seconds
Started	Jul 01 06:45:03 PM PDT 24
Finished	Jul 01 06:45:25 PM PDT 24
Peak memory	226568 kb
Host	smart-160a4b04-c1d4-4135-a8f4-517065066f6c
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664708782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_er rors.664708782
Directory	/workspace/10.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.3383696589
Short name	T450
Test name
Test status
Simulation time	761578196 ps
CPU time	10.42 seconds
Started	Jul 01 06:45:03 PM PDT 24
Finished	Jul 01 06:45:16 PM PDT 24
Peak memory	218660 kb
Host	smart-c7da01dd-f109-4557-afe6-0d3ac3d8b3fb
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383696589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta g_prog_failure.3383696589
Directory	/workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/10.lc_ctrl_jtag_smoke.2094639593
Short name	T172
Test name
Test status
Simulation time	117884418 ps
CPU time	4.18 seconds
Started	Jul 01 06:45:02 PM PDT 24
Finished	Jul 01 06:45:07 PM PDT 24
Peak memory	217992 kb
Host	smart-aff2f786-190c-4f36-beaa-4a52d1217a53
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094639593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke .2094639593
Directory	/workspace/10.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/10.lc_ctrl_jtag_state_failure.3853558482
Short name	T867
Test name
Test status
Simulation time	3129134316 ps
CPU time	50.13 seconds
Started	Jul 01 06:45:03 PM PDT 24
Finished	Jul 01 06:45:55 PM PDT 24
Peak memory	268744 kb
Host	smart-eae5a4e2-aa18-4831-9156-1cdb5edd3186
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853558482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt ag_state_failure.3853558482
Directory	/workspace/10.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.3825985594
Short name	T760
Test name
Test status
Simulation time	1308039386 ps
CPU time	30.52 seconds
Started	Jul 01 06:45:04 PM PDT 24
Finished	Jul 01 06:45:37 PM PDT 24
Peak memory	246576 kb
Host	smart-dc8dcc69-2ef4-4122-8941-d20fb1d7a611
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825985594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl _jtag_state_post_trans.3825985594
Directory	/workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/10.lc_ctrl_prog_failure.1495854195
Short name	T338
Test name
Test status
Simulation time	56361379 ps
CPU time	2.88 seconds
Started	Jul 01 06:45:03 PM PDT 24
Finished	Jul 01 06:45:08 PM PDT 24
Peak memory	218632 kb
Host	smart-39b12ecf-2613-44ac-a7a4-752e480518fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1495854195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.1495854195
Directory	/workspace/10.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/10.lc_ctrl_sec_mubi.679470717
Short name	T311
Test name
Test status
Simulation time	2496082799 ps
CPU time	24.64 seconds
Started	Jul 01 06:45:04 PM PDT 24
Finished	Jul 01 06:45:31 PM PDT 24
Peak memory	226512 kb
Host	smart-8290ad4a-0cb8-443c-a8e6-fce06ef42bd6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679470717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.679470717
Directory	/workspace/10.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/10.lc_ctrl_sec_token_digest.593040053
Short name	T765
Test name
Test status
Simulation time	537475118 ps
CPU time	9.12 seconds
Started	Jul 01 06:45:06 PM PDT 24
Finished	Jul 01 06:45:18 PM PDT 24
Peak memory	218760 kb
Host	smart-4fb32a07-4a37-412f-b873-0fd9607570a1
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593040053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_di gest.593040053
Directory	/workspace/10.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/10.lc_ctrl_sec_token_mux.2163796524
Short name	T399
Test name
Test status
Simulation time	2128676551 ps
CPU time	18.23 seconds
Started	Jul 01 06:45:04 PM PDT 24
Finished	Jul 01 06:45:26 PM PDT 24
Peak memory	226408 kb
Host	smart-891e6547-f1a6-41d3-97ea-abe3dfeceea2
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163796524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux. 2163796524
Directory	/workspace/10.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/10.lc_ctrl_security_escalation.1278757095
Short name	T441
Test name
Test status
Simulation time	295765146 ps
CPU time	9.93 seconds
Started	Jul 01 06:45:03 PM PDT 24
Finished	Jul 01 06:45:14 PM PDT 24
Peak memory	218760 kb
Host	smart-677ec5c0-2195-44ce-8015-845581115edc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1278757095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.1278757095
Directory	/workspace/10.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/10.lc_ctrl_smoke.1694523033
Short name	T83
Test name
Test status
Simulation time	19155140 ps
CPU time	1.62 seconds
Started	Jul 01 06:45:04 PM PDT 24
Finished	Jul 01 06:45:07 PM PDT 24
Peak memory	214088 kb
Host	smart-025413c6-ee9a-418c-9bf9-1c5a93fe4de4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1694523033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.1694523033
Directory	/workspace/10.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/10.lc_ctrl_state_failure.3325840487
Short name	T547
Test name
Test status
Simulation time	369044607 ps
CPU time	28.89 seconds
Started	Jul 01 06:45:02 PM PDT 24
Finished	Jul 01 06:45:33 PM PDT 24
Peak memory	251348 kb
Host	smart-2acc37fd-5ad7-455d-9ea4-74e5e86cdb57
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3325840487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.3325840487
Directory	/workspace/10.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/10.lc_ctrl_state_post_trans.3946994313
Short name	T249
Test name
Test status
Simulation time	93039031 ps
CPU time	8.55 seconds
Started	Jul 01 06:45:03 PM PDT 24
Finished	Jul 01 06:45:14 PM PDT 24
Peak memory	251388 kb
Host	smart-ade3e9d0-2ae0-4adc-a0f6-cb5507c962f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3946994313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.3946994313
Directory	/workspace/10.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.3689069535
Short name	T445
Test name
Test status
Simulation time	36066490 ps
CPU time	1.16 seconds
Started	Jul 01 06:45:04 PM PDT 24
Finished	Jul 01 06:45:08 PM PDT 24
Peak memory	218208 kb
Host	smart-d1e04f78-d281-4a48-b6b1-bb5584725e81
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689069535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c trl_volatile_unlock_smoke.3689069535
Directory	/workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/11.lc_ctrl_alert_test.3042605105
Short name	T859
Test name
Test status
Simulation time	16993023 ps
CPU time	0.89 seconds
Started	Jul 01 06:45:19 PM PDT 24
Finished	Jul 01 06:45:23 PM PDT 24
Peak memory	209452 kb
Host	smart-92521e7d-f673-46a1-87ee-2ae95dbf7179
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042605105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.3042605105
Directory	/workspace/11.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/11.lc_ctrl_errors.3865699570
Short name	T691
Test name
Test status
Simulation time	2194049125 ps
CPU time	14.74 seconds
Started	Jul 01 06:45:03 PM PDT 24
Finished	Jul 01 06:45:20 PM PDT 24
Peak memory	218680 kb
Host	smart-1318b1b1-6df1-462c-913c-725fe431ef81
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3865699570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.3865699570
Directory	/workspace/11.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/11.lc_ctrl_jtag_access.4242416872
Short name	T511
Test name
Test status
Simulation time	299858032 ps
CPU time	2.36 seconds
Started	Jul 01 06:45:20 PM PDT 24
Finished	Jul 01 06:45:26 PM PDT 24
Peak memory	217524 kb
Host	smart-01254c18-b345-48d6-b708-d1a803c0674d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242416872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.4242416872
Directory	/workspace/11.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/11.lc_ctrl_jtag_errors.3538753173
Short name	T611
Test name
Test status
Simulation time	4791194977 ps
CPU time	36.31 seconds
Started	Jul 01 06:45:19 PM PDT 24
Finished	Jul 01 06:45:58 PM PDT 24
Peak memory	219292 kb
Host	smart-42ab732e-4622-4bf7-9937-94f0c383118e
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538753173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e rrors.3538753173
Directory	/workspace/11.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.78182730
Short name	T560
Test name
Test status
Simulation time	256195909 ps
CPU time	2.22 seconds
Started	Jul 01 06:45:04 PM PDT 24
Finished	Jul 01 06:45:08 PM PDT 24
Peak memory	218620 kb
Host	smart-bd088f31-740b-4ce2-9fcb-d2d9331570bf
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78182730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_ prog_failure.78182730
Directory	/workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/11.lc_ctrl_jtag_smoke.3934716105
Short name	T544
Test name
Test status
Simulation time	321428654 ps
CPU time	8.47 seconds
Started	Jul 01 06:45:06 PM PDT 24
Finished	Jul 01 06:45:17 PM PDT 24
Peak memory	217984 kb
Host	smart-a3f0883c-96de-4740-b769-645c1a61fc04
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934716105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke .3934716105
Directory	/workspace/11.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/11.lc_ctrl_jtag_state_failure.1279658914
Short name	T569
Test name
Test status
Simulation time	20032443734 ps
CPU time	59.09 seconds
Started	Jul 01 06:45:04 PM PDT 24
Finished	Jul 01 06:46:05 PM PDT 24
Peak memory	284076 kb
Host	smart-ca70fe6e-de12-427e-b1c9-6dec5c8ef69a
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279658914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt ag_state_failure.1279658914
Directory	/workspace/11.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.2701878260
Short name	T289
Test name
Test status
Simulation time	3657153847 ps
CPU time	20.31 seconds
Started	Jul 01 06:45:05 PM PDT 24
Finished	Jul 01 06:45:28 PM PDT 24
Peak memory	247268 kb
Host	smart-0317dba1-9ef3-4710-b65c-be8f623a56f6
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701878260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl _jtag_state_post_trans.2701878260
Directory	/workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/11.lc_ctrl_prog_failure.3834073042
Short name	T437
Test name
Test status
Simulation time	99392319 ps
CPU time	3.74 seconds
Started	Jul 01 06:45:06 PM PDT 24
Finished	Jul 01 06:45:13 PM PDT 24
Peak memory	218632 kb
Host	smart-82f3bd95-1ee7-421d-a02e-2bf8b1e7d7ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3834073042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.3834073042
Directory	/workspace/11.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/11.lc_ctrl_sec_mubi.4205072065
Short name	T400
Test name
Test status
Simulation time	220109210 ps
CPU time	11.55 seconds
Started	Jul 01 06:45:20 PM PDT 24
Finished	Jul 01 06:45:35 PM PDT 24
Peak memory	218756 kb
Host	smart-ef7adfc1-8884-43c4-9cf0-6426a127e14b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205072065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.4205072065
Directory	/workspace/11.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/11.lc_ctrl_sec_token_digest.3397458251
Short name	T413
Test name
Test status
Simulation time	5872343097 ps
CPU time	14.57 seconds
Started	Jul 01 06:45:16 PM PDT 24
Finished	Jul 01 06:45:32 PM PDT 24
Peak memory	218676 kb
Host	smart-ebe0a2fb-284e-4678-9129-71aea7639ac9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397458251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d igest.3397458251
Directory	/workspace/11.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/11.lc_ctrl_sec_token_mux.3288563374
Short name	T662
Test name
Test status
Simulation time	283966152 ps
CPU time	8.63 seconds
Started	Jul 01 06:45:18 PM PDT 24
Finished	Jul 01 06:45:28 PM PDT 24
Peak memory	218648 kb
Host	smart-0d32172f-7a56-4fc0-a958-6a4b3f4af6f9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288563374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux. 3288563374
Directory	/workspace/11.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/11.lc_ctrl_security_escalation.2870758896
Short name	T473
Test name
Test status
Simulation time	710928827 ps
CPU time	6.52 seconds
Started	Jul 01 06:45:06 PM PDT 24
Finished	Jul 01 06:45:16 PM PDT 24
Peak memory	218760 kb
Host	smart-199ed4cb-1925-4f66-af9b-01fe7884c381
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2870758896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.2870758896
Directory	/workspace/11.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/11.lc_ctrl_smoke.2218088352
Short name	T378
Test name
Test status
Simulation time	229784397 ps
CPU time	1.04 seconds
Started	Jul 01 06:45:03 PM PDT 24
Finished	Jul 01 06:45:06 PM PDT 24
Peak memory	212556 kb
Host	smart-924f1f19-830a-42c1-aacd-f16ec248f155
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2218088352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.2218088352
Directory	/workspace/11.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/11.lc_ctrl_state_failure.1924539668
Short name	T518
Test name
Test status
Simulation time	315905096 ps
CPU time	18.71 seconds
Started	Jul 01 06:45:04 PM PDT 24
Finished	Jul 01 06:45:26 PM PDT 24
Peak memory	251420 kb
Host	smart-61b8b096-cbbb-4321-b00d-15431db5040e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1924539668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.1924539668
Directory	/workspace/11.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/11.lc_ctrl_state_post_trans.3316096305
Short name	T618
Test name
Test status
Simulation time	526770706 ps
CPU time	6.6 seconds
Started	Jul 01 06:45:04 PM PDT 24
Finished	Jul 01 06:45:13 PM PDT 24
Peak memory	250912 kb
Host	smart-0968b571-541a-4843-aea3-f105c52c0f1e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3316096305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.3316096305
Directory	/workspace/11.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/11.lc_ctrl_stress_all.1179662315
Short name	T831
Test name
Test status
Simulation time	10174803509 ps
CPU time	75.47 seconds
Started	Jul 01 06:45:20 PM PDT 24
Finished	Jul 01 06:46:39 PM PDT 24
Peak memory	251380 kb
Host	smart-06e2fa7f-9d3a-4818-b114-e760187ad8fa
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179662315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all.1179662315
Directory	/workspace/11.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.857225667
Short name	T160
Test name
Test status
Simulation time	20932975977 ps
CPU time	785.84 seconds
Started	Jul 01 06:45:18 PM PDT 24
Finished	Jul 01 06:58:27 PM PDT 24
Peak memory	497280 kb
Host	smart-73a5542b-4dd8-40bb-b920-a32543642314
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=857225667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all_with_rand_reset.857225667
Directory	/workspace/11.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.4049790427
Short name	T442
Test name
Test status
Simulation time	51657436 ps
CPU time	1.1 seconds
Started	Jul 01 06:45:05 PM PDT 24
Finished	Jul 01 06:45:09 PM PDT 24
Peak memory	213368 kb
Host	smart-2997e661-1cd8-45ba-b29c-a69fbfc706b7
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049790427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c trl_volatile_unlock_smoke.4049790427
Directory	/workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/12.lc_ctrl_alert_test.26974128
Short name	T558
Test name
Test status
Simulation time	13160783 ps
CPU time	0.86 seconds
Started	Jul 01 06:45:18 PM PDT 24
Finished	Jul 01 06:45:20 PM PDT 24
Peak memory	209304 kb
Host	smart-31e5cf19-c54c-4262-9b9f-4e18fe271cf8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26974128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.26974128
Directory	/workspace/12.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/12.lc_ctrl_jtag_access.387597127
Short name	T25
Test name
Test status
Simulation time	209042116 ps
CPU time	6.09 seconds
Started	Jul 01 06:45:18 PM PDT 24
Finished	Jul 01 06:45:27 PM PDT 24
Peak memory	217988 kb
Host	smart-08238b67-8449-4826-a0d8-d57dc39ce98d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387597127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.387597127
Directory	/workspace/12.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/12.lc_ctrl_jtag_errors.589666551
Short name	T49
Test name
Test status
Simulation time	4266112321 ps
CPU time	109.34 seconds
Started	Jul 01 06:45:18 PM PDT 24
Finished	Jul 01 06:47:09 PM PDT 24
Peak memory	220688 kb
Host	smart-3be0a417-ab90-4c04-bb53-f00a1a93ef65
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589666551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_er rors.589666551
Directory	/workspace/12.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.4247544981
Short name	T16
Test name
Test status
Simulation time	2527647194 ps
CPU time	10.66 seconds
Started	Jul 01 06:45:19 PM PDT 24
Finished	Jul 01 06:45:33 PM PDT 24
Peak memory	218752 kb
Host	smart-d95fd40a-1b58-41d3-b33d-b2614db9fbd9
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247544981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta g_prog_failure.4247544981
Directory	/workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/12.lc_ctrl_jtag_smoke.1240305229
Short name	T19
Test name
Test status
Simulation time	3597991060 ps
CPU time	15.28 seconds
Started	Jul 01 06:45:18 PM PDT 24
Finished	Jul 01 06:45:35 PM PDT 24
Peak memory	218160 kb
Host	smart-257a84b6-9070-473c-8f82-abde798481a0
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240305229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke .1240305229
Directory	/workspace/12.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/12.lc_ctrl_jtag_state_failure.662538832
Short name	T401
Test name
Test status
Simulation time	2124760626 ps
CPU time	38.3 seconds
Started	Jul 01 06:45:21 PM PDT 24
Finished	Jul 01 06:46:02 PM PDT 24
Peak memory	252292 kb
Host	smart-578b7b56-6eb6-46ac-b9d7-f0571ab99fbb
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662538832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta g_state_failure.662538832
Directory	/workspace/12.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.3862673827
Short name	T380
Test name
Test status
Simulation time	2372942396 ps
CPU time	19.29 seconds
Started	Jul 01 06:45:20 PM PDT 24
Finished	Jul 01 06:45:43 PM PDT 24
Peak memory	249360 kb
Host	smart-d028ebe6-c684-4af4-b2b8-6c527ec485a7
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862673827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl _jtag_state_post_trans.3862673827
Directory	/workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/12.lc_ctrl_prog_failure.473011498
Short name	T540
Test name
Test status
Simulation time	155554701 ps
CPU time	1.53 seconds
Started	Jul 01 06:45:18 PM PDT 24
Finished	Jul 01 06:45:22 PM PDT 24
Peak memory	222400 kb
Host	smart-858391e8-5416-48d0-b411-ff67189db1d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=473011498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.473011498
Directory	/workspace/12.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/12.lc_ctrl_sec_mubi.3295348993
Short name	T644
Test name
Test status
Simulation time	313839123 ps
CPU time	11.55 seconds
Started	Jul 01 06:45:19 PM PDT 24
Finished	Jul 01 06:45:34 PM PDT 24
Peak memory	226556 kb
Host	smart-d7512bc0-31c1-4dc9-bf59-e16c4e98b008
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295348993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.3295348993
Directory	/workspace/12.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/12.lc_ctrl_sec_token_digest.1665308451
Short name	T824
Test name
Test status
Simulation time	2865352710 ps
CPU time	18.19 seconds
Started	Jul 01 06:45:10 PM PDT 24
Finished	Jul 01 06:45:29 PM PDT 24
Peak memory	219300 kb
Host	smart-4b89f3a9-14da-47b8-a75f-1621776f4160
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665308451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d igest.1665308451
Directory	/workspace/12.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/12.lc_ctrl_sec_token_mux.1110362326
Short name	T750
Test name
Test status
Simulation time	649471499 ps
CPU time	10.74 seconds
Started	Jul 01 06:45:19 PM PDT 24
Finished	Jul 01 06:45:33 PM PDT 24
Peak memory	218656 kb
Host	smart-ecda4b2c-6f3c-4ca0-991a-025b7a160de9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110362326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux. 1110362326
Directory	/workspace/12.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/12.lc_ctrl_smoke.2136315722
Short name	T242
Test name
Test status
Simulation time	157027052 ps
CPU time	3.61 seconds
Started	Jul 01 06:45:19 PM PDT 24
Finished	Jul 01 06:45:25 PM PDT 24
Peak memory	218248 kb
Host	smart-512b7494-e6e6-4311-8de9-fbc81f3fc3a5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2136315722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.2136315722
Directory	/workspace/12.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/12.lc_ctrl_state_failure.2448696517
Short name	T556
Test name
Test status
Simulation time	4509759683 ps
CPU time	31.12 seconds
Started	Jul 01 06:45:19 PM PDT 24
Finished	Jul 01 06:45:53 PM PDT 24
Peak memory	248680 kb
Host	smart-33150f3e-5f69-4f37-bf8d-9b25335b7481
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2448696517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.2448696517
Directory	/workspace/12.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/12.lc_ctrl_state_post_trans.1593971367
Short name	T421
Test name
Test status
Simulation time	155832765 ps
CPU time	5.93 seconds
Started	Jul 01 06:45:20 PM PDT 24
Finished	Jul 01 06:45:30 PM PDT 24
Peak memory	247192 kb
Host	smart-6056eda8-9272-411d-a1a5-d7cc0165b72e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1593971367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.1593971367
Directory	/workspace/12.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/12.lc_ctrl_stress_all.2887168163
Short name	T724
Test name
Test status
Simulation time	9491171236 ps
CPU time	177.85 seconds
Started	Jul 01 06:45:19 PM PDT 24
Finished	Jul 01 06:48:20 PM PDT 24
Peak memory	281908 kb
Host	smart-77ad2971-732e-4b88-8582-4e5112e26a01
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887168163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all.2887168163
Directory	/workspace/12.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.958553317
Short name	T86
Test name
Test status
Simulation time	16994054 ps
CPU time	0.95 seconds
Started	Jul 01 06:45:20 PM PDT 24
Finished	Jul 01 06:45:25 PM PDT 24
Peak memory	212292 kb
Host	smart-37632290-261d-4111-a665-975c7aa423d7
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958553317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ct rl_volatile_unlock_smoke.958553317
Directory	/workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/13.lc_ctrl_alert_test.2799893587
Short name	T440
Test name
Test status
Simulation time	23101958 ps
CPU time	1 seconds
Started	Jul 01 06:45:19 PM PDT 24
Finished	Jul 01 06:45:22 PM PDT 24
Peak memory	209644 kb
Host	smart-e3273e16-3aa9-438e-8532-30c6f01fcf38
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799893587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.2799893587
Directory	/workspace/13.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/13.lc_ctrl_errors.2013130614
Short name	T38
Test name
Test status
Simulation time	3152263579 ps
CPU time	10.8 seconds
Started	Jul 01 06:45:16 PM PDT 24
Finished	Jul 01 06:45:29 PM PDT 24
Peak memory	218744 kb
Host	smart-9e746412-8f66-4651-bd82-37efca8584b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2013130614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.2013130614
Directory	/workspace/13.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/13.lc_ctrl_jtag_access.1424815847
Short name	T647
Test name
Test status
Simulation time	268468646 ps
CPU time	6.55 seconds
Started	Jul 01 06:45:20 PM PDT 24
Finished	Jul 01 06:45:30 PM PDT 24
Peak memory	217596 kb
Host	smart-7df9e582-8b4b-4d40-a936-5204a3c906e0
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424815847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.1424815847
Directory	/workspace/13.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/13.lc_ctrl_jtag_errors.2586047071
Short name	T533
Test name
Test status
Simulation time	9708732336 ps
CPU time	40.84 seconds
Started	Jul 01 06:45:19 PM PDT 24
Finished	Jul 01 06:46:03 PM PDT 24
Peak memory	219060 kb
Host	smart-b73d1ee4-6b06-4414-a7af-c044d87aa9fb
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586047071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e rrors.2586047071
Directory	/workspace/13.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.1594072045
Short name	T221
Test name
Test status
Simulation time	1006717518 ps
CPU time	8.18 seconds
Started	Jul 01 06:45:23 PM PDT 24
Finished	Jul 01 06:45:33 PM PDT 24
Peak memory	223408 kb
Host	smart-57d68dc0-6a35-43e3-abc3-5143a012ae44
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594072045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta g_prog_failure.1594072045
Directory	/workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/13.lc_ctrl_jtag_smoke.2890798331
Short name	T318
Test name
Test status
Simulation time	173116840 ps
CPU time	3.34 seconds
Started	Jul 01 06:45:15 PM PDT 24
Finished	Jul 01 06:45:20 PM PDT 24
Peak memory	218056 kb
Host	smart-7d62126f-6260-451e-a249-0ac1b7825a46
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890798331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke .2890798331
Directory	/workspace/13.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.3288638529
Short name	T673
Test name
Test status
Simulation time	6228159649 ps
CPU time	19.51 seconds
Started	Jul 01 06:45:22 PM PDT 24
Finished	Jul 01 06:45:45 PM PDT 24
Peak memory	251312 kb
Host	smart-269287cf-ad57-4674-9f09-ca063879bce7
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288638529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl _jtag_state_post_trans.3288638529
Directory	/workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/13.lc_ctrl_prog_failure.3748840460
Short name	T550
Test name
Test status
Simulation time	650777198 ps
CPU time	2.41 seconds
Started	Jul 01 06:45:18 PM PDT 24
Finished	Jul 01 06:45:22 PM PDT 24
Peak memory	218716 kb
Host	smart-9a42139f-9b8f-43ce-99f4-989177e90127
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3748840460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.3748840460
Directory	/workspace/13.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/13.lc_ctrl_sec_mubi.3928320585
Short name	T381
Test name
Test status
Simulation time	1209607029 ps
CPU time	14.6 seconds
Started	Jul 01 06:45:20 PM PDT 24
Finished	Jul 01 06:45:38 PM PDT 24
Peak memory	219304 kb
Host	smart-23ab8a32-eb5d-4ee3-ad9f-2669a8890753
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928320585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.3928320585
Directory	/workspace/13.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/13.lc_ctrl_sec_token_digest.2746682898
Short name	T436
Test name
Test status
Simulation time	1093889664 ps
CPU time	11.47 seconds
Started	Jul 01 06:45:19 PM PDT 24
Finished	Jul 01 06:45:34 PM PDT 24
Peak memory	218628 kb
Host	smart-0f41a496-3cec-406b-931e-6935c2063bd3
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746682898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d igest.2746682898
Directory	/workspace/13.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/13.lc_ctrl_sec_token_mux.3529434054
Short name	T285
Test name
Test status
Simulation time	466496769 ps
CPU time	11.21 seconds
Started	Jul 01 06:45:20 PM PDT 24
Finished	Jul 01 06:45:35 PM PDT 24
Peak memory	218568 kb
Host	smart-e89ff62e-ac87-4765-9e97-4a694ebd66d6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529434054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux. 3529434054
Directory	/workspace/13.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/13.lc_ctrl_security_escalation.1636481833
Short name	T420
Test name
Test status
Simulation time	462798967 ps
CPU time	8.07 seconds
Started	Jul 01 06:45:39 PM PDT 24
Finished	Jul 01 06:45:49 PM PDT 24
Peak memory	226448 kb
Host	smart-217bc519-79bb-459e-8a20-150f163668c4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1636481833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.1636481833
Directory	/workspace/13.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/13.lc_ctrl_smoke.2104588726
Short name	T418
Test name
Test status
Simulation time	92824917 ps
CPU time	2 seconds
Started	Jul 01 06:45:18 PM PDT 24
Finished	Jul 01 06:45:23 PM PDT 24
Peak memory	214708 kb
Host	smart-beaefe46-6d86-4650-8968-e02c1b92c78a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2104588726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.2104588726
Directory	/workspace/13.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/13.lc_ctrl_state_failure.2768250946
Short name	T793
Test name
Test status
Simulation time	1251494538 ps
CPU time	32.13 seconds
Started	Jul 01 06:45:18 PM PDT 24
Finished	Jul 01 06:45:52 PM PDT 24
Peak memory	251348 kb
Host	smart-e24ea710-1c9c-434a-9ba6-240a2113c298
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2768250946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.2768250946
Directory	/workspace/13.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/13.lc_ctrl_state_post_trans.478357876
Short name	T848
Test name
Test status
Simulation time	925091195 ps
CPU time	3.47 seconds
Started	Jul 01 06:45:19 PM PDT 24
Finished	Jul 01 06:45:26 PM PDT 24
Peak memory	222692 kb
Host	smart-6e50c82f-16ce-44aa-900e-f9c3091d9276
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=478357876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.478357876
Directory	/workspace/13.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/13.lc_ctrl_stress_all.4006653498
Short name	T730
Test name
Test status
Simulation time	36503920912 ps
CPU time	284.37 seconds
Started	Jul 01 06:45:19 PM PDT 24
Finished	Jul 01 06:50:06 PM PDT 24
Peak memory	267876 kb
Host	smart-7708d2a6-8a56-4a35-b735-5fe290383392
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006653498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all.4006653498
Directory	/workspace/13.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.543630477
Short name	T847
Test name
Test status
Simulation time	13833141 ps
CPU time	1.14 seconds
Started	Jul 01 06:45:18 PM PDT 24
Finished	Jul 01 06:45:22 PM PDT 24
Peak memory	212264 kb
Host	smart-40905e42-b8df-412e-8b23-46a8ce088285
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543630477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ct rl_volatile_unlock_smoke.543630477
Directory	/workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/14.lc_ctrl_alert_test.4272007865
Short name	T74
Test name
Test status
Simulation time	45574556 ps
CPU time	0.99 seconds
Started	Jul 01 06:45:30 PM PDT 24
Finished	Jul 01 06:45:33 PM PDT 24
Peak memory	209324 kb
Host	smart-4d73d04a-8e0f-43fe-9c4b-1dd3c592772f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272007865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.4272007865
Directory	/workspace/14.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/14.lc_ctrl_errors.3508365760
Short name	T590
Test name
Test status
Simulation time	2021184270 ps
CPU time	13.85 seconds
Started	Jul 01 06:45:18 PM PDT 24
Finished	Jul 01 06:45:34 PM PDT 24
Peak memory	218756 kb
Host	smart-ab86290d-cce5-4442-a368-4bd4acda7a91
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3508365760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.3508365760
Directory	/workspace/14.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/14.lc_ctrl_jtag_access.4055951297
Short name	T386
Test name
Test status
Simulation time	2679355424 ps
CPU time	11.03 seconds
Started	Jul 01 06:45:27 PM PDT 24
Finished	Jul 01 06:45:41 PM PDT 24
Peak memory	218120 kb
Host	smart-12122cd3-af4b-429f-b21b-38c7ee71bede
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055951297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.4055951297
Directory	/workspace/14.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/14.lc_ctrl_jtag_errors.433029915
Short name	T48
Test name
Test status
Simulation time	2735037139 ps
CPU time	77.73 seconds
Started	Jul 01 06:45:27 PM PDT 24
Finished	Jul 01 06:46:48 PM PDT 24
Peak memory	218652 kb
Host	smart-0a46faa2-6c4d-480b-96f6-a2b96841f205
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433029915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_er rors.433029915
Directory	/workspace/14.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.286130958
Short name	T316
Test name
Test status
Simulation time	1117275571 ps
CPU time	7.63 seconds
Started	Jul 01 06:45:28 PM PDT 24
Finished	Jul 01 06:45:38 PM PDT 24
Peak memory	218576 kb
Host	smart-4b4f4a5a-37b3-45c0-b062-55420e0bd6c8
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286130958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag _prog_failure.286130958
Directory	/workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/14.lc_ctrl_jtag_smoke.1838522841
Short name	T260
Test name
Test status
Simulation time	677860377 ps
CPU time	6.23 seconds
Started	Jul 01 06:45:28 PM PDT 24
Finished	Jul 01 06:45:37 PM PDT 24
Peak memory	218100 kb
Host	smart-a3dd7d30-f7e1-4557-8e50-1a8b8369e8fa
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838522841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke .1838522841
Directory	/workspace/14.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/14.lc_ctrl_jtag_state_failure.549237686
Short name	T484
Test name
Test status
Simulation time	2294151652 ps
CPU time	50.38 seconds
Started	Jul 01 06:45:33 PM PDT 24
Finished	Jul 01 06:46:26 PM PDT 24
Peak memory	267832 kb
Host	smart-606baa35-b3ac-455e-8ac7-308d920ae2e5
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549237686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta g_state_failure.549237686
Directory	/workspace/14.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.3093311938
Short name	T830
Test name
Test status
Simulation time	552454357 ps
CPU time	21.78 seconds
Started	Jul 01 06:45:45 PM PDT 24
Finished	Jul 01 06:46:12 PM PDT 24
Peak memory	243220 kb
Host	smart-3ac17dc3-68af-4f60-9d4c-43f86f6a3bff
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093311938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl _jtag_state_post_trans.3093311938
Directory	/workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/14.lc_ctrl_prog_failure.574359563
Short name	T676
Test name
Test status
Simulation time	238548615 ps
CPU time	2.48 seconds
Started	Jul 01 06:45:19 PM PDT 24
Finished	Jul 01 06:45:25 PM PDT 24
Peak memory	218580 kb
Host	smart-529fca9b-37ed-4736-b35e-0cf7fa8b135c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=574359563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.574359563
Directory	/workspace/14.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/14.lc_ctrl_sec_mubi.3912318817
Short name	T751
Test name
Test status
Simulation time	1865276354 ps
CPU time	13.02 seconds
Started	Jul 01 06:45:28 PM PDT 24
Finished	Jul 01 06:45:43 PM PDT 24
Peak memory	219408 kb
Host	smart-8dad4e5c-ae07-4fee-88e1-4b7ee2cf1227
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912318817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.3912318817
Directory	/workspace/14.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/14.lc_ctrl_sec_token_digest.2858820283
Short name	T405
Test name
Test status
Simulation time	481991453 ps
CPU time	9.58 seconds
Started	Jul 01 06:45:30 PM PDT 24
Finished	Jul 01 06:45:42 PM PDT 24
Peak memory	218664 kb
Host	smart-43226ffd-48e0-4cb9-a6f1-8b3598e38be1
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858820283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d igest.2858820283
Directory	/workspace/14.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/14.lc_ctrl_sec_token_mux.2490630790
Short name	T458
Test name
Test status
Simulation time	541025596 ps
CPU time	9.54 seconds
Started	Jul 01 06:45:26 PM PDT 24
Finished	Jul 01 06:45:38 PM PDT 24
Peak memory	226456 kb
Host	smart-dc8f8e82-7ae6-4585-bff7-601aeef5b02a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490630790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux. 2490630790
Directory	/workspace/14.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/14.lc_ctrl_security_escalation.13203578
Short name	T609
Test name
Test status
Simulation time	428758289 ps
CPU time	15.69 seconds
Started	Jul 01 06:45:29 PM PDT 24
Finished	Jul 01 06:45:47 PM PDT 24
Peak memory	226428 kb
Host	smart-f6f5c52b-673c-451a-8010-408b69ffa4cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=13203578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.13203578
Directory	/workspace/14.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/14.lc_ctrl_smoke.1677852024
Short name	T828
Test name
Test status
Simulation time	197037104 ps
CPU time	2.64 seconds
Started	Jul 01 06:45:20 PM PDT 24
Finished	Jul 01 06:45:26 PM PDT 24
Peak memory	218072 kb
Host	smart-82854693-3a4d-4f62-8d19-560804e7f75b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1677852024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.1677852024
Directory	/workspace/14.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/14.lc_ctrl_state_failure.2340660176
Short name	T710
Test name
Test status
Simulation time	1756330708 ps
CPU time	28.25 seconds
Started	Jul 01 06:45:23 PM PDT 24
Finished	Jul 01 06:45:54 PM PDT 24
Peak memory	251296 kb
Host	smart-33b5f292-6074-4a1d-927b-eaa95b2ecd7c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2340660176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.2340660176
Directory	/workspace/14.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/14.lc_ctrl_state_post_trans.3425798263
Short name	T659
Test name
Test status
Simulation time	362012555 ps
CPU time	8.82 seconds
Started	Jul 01 06:45:20 PM PDT 24
Finished	Jul 01 06:45:32 PM PDT 24
Peak memory	251404 kb
Host	smart-a81bf827-e22c-4f51-beca-744818fefa2e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3425798263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.3425798263
Directory	/workspace/14.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/14.lc_ctrl_stress_all.1251690509
Short name	T638
Test name
Test status
Simulation time	66741388127 ps
CPU time	444.25 seconds
Started	Jul 01 06:45:32 PM PDT 24
Finished	Jul 01 06:52:59 PM PDT 24
Peak memory	348128 kb
Host	smart-fbc54db0-ed3e-4831-a0a0-1ac2e7741ac4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251690509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all.1251690509
Directory	/workspace/14.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.4259576050
Short name	T182
Test name
Test status
Simulation time	25154521765 ps
CPU time	867.77 seconds
Started	Jul 01 06:45:27 PM PDT 24
Finished	Jul 01 06:59:57 PM PDT 24
Peak memory	300820 kb
Host	smart-5452aa62-66d5-4cb2-9c18-3a7adcc1e487
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=4259576050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all_with_rand_reset.4259576050
Directory	/workspace/14.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.2543830798
Short name	T698
Test name
Test status
Simulation time	82342507 ps
CPU time	0.98 seconds
Started	Jul 01 06:45:19 PM PDT 24
Finished	Jul 01 06:45:23 PM PDT 24
Peak memory	212356 kb
Host	smart-2c3f7e4a-c021-42c1-bcdb-a6ceb0d0511b
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543830798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c trl_volatile_unlock_smoke.2543830798
Directory	/workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/15.lc_ctrl_alert_test.3234030806
Short name	T93
Test name
Test status
Simulation time	49381019 ps
CPU time	0.84 seconds
Started	Jul 01 06:45:30 PM PDT 24
Finished	Jul 01 06:45:33 PM PDT 24
Peak memory	209252 kb
Host	smart-c92fa479-ee1d-4fed-ab57-17f6738f5228
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234030806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.3234030806
Directory	/workspace/15.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/15.lc_ctrl_errors.2492045635
Short name	T404
Test name
Test status
Simulation time	572445447 ps
CPU time	14.63 seconds
Started	Jul 01 06:45:45 PM PDT 24
Finished	Jul 01 06:46:05 PM PDT 24
Peak memory	226480 kb
Host	smart-e1fbcf69-d463-44c4-a63d-435796145fc3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2492045635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.2492045635
Directory	/workspace/15.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/15.lc_ctrl_jtag_access.629561638
Short name	T27
Test name
Test status
Simulation time	362169034 ps
CPU time	4.15 seconds
Started	Jul 01 06:45:43 PM PDT 24
Finished	Jul 01 06:45:52 PM PDT 24
Peak memory	217584 kb
Host	smart-4747a824-bace-4897-9772-c1011655b523
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629561638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.629561638
Directory	/workspace/15.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/15.lc_ctrl_jtag_errors.109941248
Short name	T872
Test name
Test status
Simulation time	2185159162 ps
CPU time	27.68 seconds
Started	Jul 01 06:45:29 PM PDT 24
Finished	Jul 01 06:45:59 PM PDT 24
Peak memory	218716 kb
Host	smart-7c5ab699-827e-44dc-ba47-5b765104bae5
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109941248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_er rors.109941248
Directory	/workspace/15.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.1233398917
Short name	T522
Test name
Test status
Simulation time	2343415378 ps
CPU time	16.4 seconds
Started	Jul 01 06:45:28 PM PDT 24
Finished	Jul 01 06:45:47 PM PDT 24
Peak memory	218636 kb
Host	smart-8971c68b-bbd6-42ef-9caf-428da2477d5e
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233398917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta g_prog_failure.1233398917
Directory	/workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/15.lc_ctrl_jtag_smoke.2106880185
Short name	T89
Test name
Test status
Simulation time	299300636 ps
CPU time	8.57 seconds
Started	Jul 01 06:45:27 PM PDT 24
Finished	Jul 01 06:45:38 PM PDT 24
Peak memory	217996 kb
Host	smart-607b1c47-5f32-4d91-8549-8a3194f4caf8
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106880185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke .2106880185
Directory	/workspace/15.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/15.lc_ctrl_jtag_state_failure.1809072286
Short name	T621
Test name
Test status
Simulation time	7979117551 ps
CPU time	49.37 seconds
Started	Jul 01 06:45:32 PM PDT 24
Finished	Jul 01 06:46:24 PM PDT 24
Peak memory	269156 kb
Host	smart-8deb04d7-9fb9-493c-9639-99f2dca8db81
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809072286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt ag_state_failure.1809072286
Directory	/workspace/15.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.3905496454
Short name	T15
Test name
Test status
Simulation time	848979983 ps
CPU time	18.18 seconds
Started	Jul 01 06:45:27 PM PDT 24
Finished	Jul 01 06:45:48 PM PDT 24
Peak memory	251332 kb
Host	smart-4bd80557-600c-4de1-90bf-bdf37b3b5ef5
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905496454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl _jtag_state_post_trans.3905496454
Directory	/workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/15.lc_ctrl_prog_failure.1402263549
Short name	T11
Test name
Test status
Simulation time	94898328 ps
CPU time	2.9 seconds
Started	Jul 01 06:45:33 PM PDT 24
Finished	Jul 01 06:45:38 PM PDT 24
Peak memory	222708 kb
Host	smart-1a108698-8404-47f1-a5ac-60ba46e03dcf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1402263549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.1402263549
Directory	/workspace/15.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/15.lc_ctrl_sec_mubi.1575203547
Short name	T335
Test name
Test status
Simulation time	676942308 ps
CPU time	15.47 seconds
Started	Jul 01 06:45:28 PM PDT 24
Finished	Jul 01 06:45:47 PM PDT 24
Peak memory	226472 kb
Host	smart-c0391a25-fdb2-4469-b6a3-b7a118477b9c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575203547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.1575203547
Directory	/workspace/15.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/15.lc_ctrl_sec_token_digest.331970085
Short name	T826
Test name
Test status
Simulation time	477619150 ps
CPU time	9.94 seconds
Started	Jul 01 06:45:33 PM PDT 24
Finished	Jul 01 06:45:45 PM PDT 24
Peak memory	218796 kb
Host	smart-a2155481-c43b-485e-89e3-58512e83fe8b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331970085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_di gest.331970085
Directory	/workspace/15.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/15.lc_ctrl_sec_token_mux.3936522575
Short name	T433
Test name
Test status
Simulation time	222371725 ps
CPU time	6.17 seconds
Started	Jul 01 06:45:33 PM PDT 24
Finished	Jul 01 06:45:42 PM PDT 24
Peak memory	218712 kb
Host	smart-74c02eb0-9cb1-411c-8644-de43a5b31f1f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936522575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux. 3936522575
Directory	/workspace/15.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/15.lc_ctrl_security_escalation.3526208462
Short name	T808
Test name
Test status
Simulation time	187138419 ps
CPU time	6.21 seconds
Started	Jul 01 06:45:45 PM PDT 24
Finished	Jul 01 06:45:56 PM PDT 24
Peak memory	218648 kb
Host	smart-a42df575-e7dc-48f5-aa78-84e084fa2571
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3526208462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.3526208462
Directory	/workspace/15.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/15.lc_ctrl_smoke.3964906878
Short name	T549
Test name
Test status
Simulation time	79173107 ps
CPU time	3.06 seconds
Started	Jul 01 06:45:27 PM PDT 24
Finished	Jul 01 06:45:32 PM PDT 24
Peak memory	214948 kb
Host	smart-6b3de0ba-3458-478a-af98-c98de2b7f501
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3964906878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.3964906878
Directory	/workspace/15.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/15.lc_ctrl_state_failure.4249864412
Short name	T537
Test name
Test status
Simulation time	170112962 ps
CPU time	24.85 seconds
Started	Jul 01 06:45:27 PM PDT 24
Finished	Jul 01 06:45:55 PM PDT 24
Peak memory	251340 kb
Host	smart-6758afb4-f002-4a64-8403-76c75c732df5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4249864412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.4249864412
Directory	/workspace/15.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/15.lc_ctrl_stress_all.1659145417
Short name	T414
Test name
Test status
Simulation time	3987496988 ps
CPU time	43.11 seconds
Started	Jul 01 06:45:26 PM PDT 24
Finished	Jul 01 06:46:11 PM PDT 24
Peak memory	251720 kb
Host	smart-dbca07d1-7321-470c-8056-593a22ac2876
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659145417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all.1659145417
Directory	/workspace/15.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.3190893326
Short name	T102
Test name
Test status
Simulation time	98248899 ps
CPU time	1.95 seconds
Started	Jul 01 06:45:28 PM PDT 24
Finished	Jul 01 06:45:32 PM PDT 24
Peak memory	218140 kb
Host	smart-4ecd1dcd-aff2-4e14-bfd3-d402d66f8217
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190893326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c trl_volatile_unlock_smoke.3190893326
Directory	/workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/16.lc_ctrl_alert_test.2139002119
Short name	T362
Test name
Test status
Simulation time	116073931 ps
CPU time	1.37 seconds
Started	Jul 01 06:45:35 PM PDT 24
Finished	Jul 01 06:45:38 PM PDT 24
Peak memory	209496 kb
Host	smart-9e0624a5-e4a7-44be-9dd3-505ba7410290
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139002119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.2139002119
Directory	/workspace/16.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/16.lc_ctrl_errors.3114125714
Short name	T685
Test name
Test status
Simulation time	1765895252 ps
CPU time	14.84 seconds
Started	Jul 01 06:45:30 PM PDT 24
Finished	Jul 01 06:45:47 PM PDT 24
Peak memory	218688 kb
Host	smart-7ee7fa2e-1d15-4e60-8c59-a1e22ed81f06
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3114125714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.3114125714
Directory	/workspace/16.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/16.lc_ctrl_jtag_access.3891652060
Short name	T379
Test name
Test status
Simulation time	342990560 ps
CPU time	2.82 seconds
Started	Jul 01 06:45:28 PM PDT 24
Finished	Jul 01 06:45:33 PM PDT 24
Peak memory	217448 kb
Host	smart-a0903e9a-7690-4de3-b7da-9ec17a1971f5
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891652060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.3891652060
Directory	/workspace/16.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/16.lc_ctrl_jtag_errors.256160621
Short name	T315
Test name
Test status
Simulation time	3403360487 ps
CPU time	53.76 seconds
Started	Jul 01 06:45:43 PM PDT 24
Finished	Jul 01 06:46:41 PM PDT 24
Peak memory	219436 kb
Host	smart-8dc77dad-1eef-40b3-9adc-cca7794ab324
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256160621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_er rors.256160621
Directory	/workspace/16.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1121178736
Short name	T220
Test name
Test status
Simulation time	474652403 ps
CPU time	13.41 seconds
Started	Jul 01 06:45:45 PM PDT 24
Finished	Jul 01 06:46:03 PM PDT 24
Peak memory	218720 kb
Host	smart-32984a80-a158-4391-9644-b6b42ff2971b
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121178736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta g_prog_failure.1121178736
Directory	/workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/16.lc_ctrl_jtag_smoke.3281599018
Short name	T485
Test name
Test status
Simulation time	1995352078 ps
CPU time	6.25 seconds
Started	Jul 01 06:45:32 PM PDT 24
Finished	Jul 01 06:45:40 PM PDT 24
Peak memory	218176 kb
Host	smart-276b99ad-048f-4e39-95c2-5692a3e545c4
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281599018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke .3281599018
Directory	/workspace/16.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/16.lc_ctrl_jtag_state_failure.3417493092
Short name	T534
Test name
Test status
Simulation time	4150702206 ps
CPU time	78.77 seconds
Started	Jul 01 06:45:45 PM PDT 24
Finished	Jul 01 06:47:08 PM PDT 24
Peak memory	284192 kb
Host	smart-c5d252cd-5ddd-4bb7-9d34-91adeedcdead
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417493092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt ag_state_failure.3417493092
Directory	/workspace/16.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.1107548761
Short name	T2
Test name
Test status
Simulation time	741758930 ps
CPU time	15.18 seconds
Started	Jul 01 06:45:45 PM PDT 24
Finished	Jul 01 06:46:05 PM PDT 24
Peak memory	251360 kb
Host	smart-9d1f2e48-3513-4c9a-9e67-e531a04ea306
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107548761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl _jtag_state_post_trans.1107548761
Directory	/workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/16.lc_ctrl_prog_failure.2832221087
Short name	T235
Test name
Test status
Simulation time	81187545 ps
CPU time	2.1 seconds
Started	Jul 01 06:45:43 PM PDT 24
Finished	Jul 01 06:45:50 PM PDT 24
Peak memory	218768 kb
Host	smart-1c121ee3-325a-4686-b6e2-2f2ac3277a3b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2832221087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.2832221087
Directory	/workspace/16.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/16.lc_ctrl_sec_mubi.2262603231
Short name	T301
Test name
Test status
Simulation time	433827851 ps
CPU time	13.91 seconds
Started	Jul 01 06:45:31 PM PDT 24
Finished	Jul 01 06:45:47 PM PDT 24
Peak memory	226504 kb
Host	smart-31a1680e-b582-4413-a520-a3e4a366d87a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262603231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.2262603231
Directory	/workspace/16.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/16.lc_ctrl_sec_token_digest.2173094960
Short name	T607
Test name
Test status
Simulation time	1489451599 ps
CPU time	10.31 seconds
Started	Jul 01 06:45:30 PM PDT 24
Finished	Jul 01 06:45:42 PM PDT 24
Peak memory	218676 kb
Host	smart-035e3718-6ea0-4751-884f-c54c17410f9d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173094960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d igest.2173094960
Directory	/workspace/16.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/16.lc_ctrl_sec_token_mux.4145863612
Short name	T395
Test name
Test status
Simulation time	1057160975 ps
CPU time	16.52 seconds
Started	Jul 01 06:45:33 PM PDT 24
Finished	Jul 01 06:45:52 PM PDT 24
Peak memory	218712 kb
Host	smart-c503dce1-c906-4636-8b1f-7bbcdc512c92
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145863612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux. 4145863612
Directory	/workspace/16.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/16.lc_ctrl_security_escalation.2697468801
Short name	T479
Test name
Test status
Simulation time	548904548 ps
CPU time	12.91 seconds
Started	Jul 01 06:45:26 PM PDT 24
Finished	Jul 01 06:45:41 PM PDT 24
Peak memory	226520 kb
Host	smart-8d4cf731-eb7d-49f8-95ae-70c6ae7a6fb4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2697468801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.2697468801
Directory	/workspace/16.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/16.lc_ctrl_smoke.330387760
Short name	T683
Test name
Test status
Simulation time	35387363 ps
CPU time	1.7 seconds
Started	Jul 01 06:45:27 PM PDT 24
Finished	Jul 01 06:45:31 PM PDT 24
Peak memory	214436 kb
Host	smart-08f97cad-254a-4371-a002-09a4aed9d824
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=330387760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.330387760
Directory	/workspace/16.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/16.lc_ctrl_state_failure.786720719
Short name	T592
Test name
Test status
Simulation time	166436612 ps
CPU time	21.74 seconds
Started	Jul 01 06:45:30 PM PDT 24
Finished	Jul 01 06:45:54 PM PDT 24
Peak memory	251412 kb
Host	smart-029c6a93-0b10-4efb-bcae-6d3af23f2c55
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=786720719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.786720719
Directory	/workspace/16.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/16.lc_ctrl_state_post_trans.769607635
Short name	T238
Test name
Test status
Simulation time	550089285 ps
CPU time	5.91 seconds
Started	Jul 01 06:45:28 PM PDT 24
Finished	Jul 01 06:45:36 PM PDT 24
Peak memory	247348 kb
Host	smart-39d20e07-67b0-43c2-94a3-487b2cba0f87
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=769607635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.769607635
Directory	/workspace/16.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/16.lc_ctrl_stress_all.1293942893
Short name	T164
Test name
Test status
Simulation time	27590622595 ps
CPU time	128.91 seconds
Started	Jul 01 06:45:37 PM PDT 24
Finished	Jul 01 06:47:48 PM PDT 24
Peak memory	284076 kb
Host	smart-96b1cf9c-c818-4f24-a273-7a687a2dabf3
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293942893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all.1293942893
Directory	/workspace/16.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.2850473050
Short name	T118
Test name
Test status
Simulation time	21218512252 ps
CPU time	693.87 seconds
Started	Jul 01 06:45:34 PM PDT 24
Finished	Jul 01 06:57:09 PM PDT 24
Peak memory	268004 kb
Host	smart-1179654b-3d68-4b67-aef4-bb759f7ab836
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2850473050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all_with_rand_reset.2850473050
Directory	/workspace/16.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.758708437
Short name	T596
Test name
Test status
Simulation time	17486453 ps
CPU time	1.06 seconds
Started	Jul 01 06:45:27 PM PDT 24
Finished	Jul 01 06:45:31 PM PDT 24
Peak memory	218044 kb
Host	smart-b9da066e-4c6a-43c9-ae3d-5a2a7fdc50ea
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758708437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ct rl_volatile_unlock_smoke.758708437
Directory	/workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/17.lc_ctrl_alert_test.4280784114
Short name	T476
Test name
Test status
Simulation time	17961350 ps
CPU time	0.91 seconds
Started	Jul 01 06:45:37 PM PDT 24
Finished	Jul 01 06:45:40 PM PDT 24
Peak memory	209384 kb
Host	smart-d36337b2-d96d-4c9c-b2a4-086de6a3611b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280784114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.4280784114
Directory	/workspace/17.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/17.lc_ctrl_errors.1681170181
Short name	T850
Test name
Test status
Simulation time	310625919 ps
CPU time	10.74 seconds
Started	Jul 01 06:45:40 PM PDT 24
Finished	Jul 01 06:45:53 PM PDT 24
Peak memory	218700 kb
Host	smart-6e6f2305-7bfd-4d44-95a3-4f12196b5eb6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1681170181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.1681170181
Directory	/workspace/17.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/17.lc_ctrl_jtag_access.529149942
Short name	T17
Test name
Test status
Simulation time	88958675 ps
CPU time	2.77 seconds
Started	Jul 01 06:45:34 PM PDT 24
Finished	Jul 01 06:45:38 PM PDT 24
Peak memory	217932 kb
Host	smart-7ca3fae0-f0af-4807-ac3a-e8173c77e585
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529149942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.529149942
Directory	/workspace/17.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/17.lc_ctrl_jtag_errors.3605179138
Short name	T454
Test name
Test status
Simulation time	2999575696 ps
CPU time	82.42 seconds
Started	Jul 01 06:45:37 PM PDT 24
Finished	Jul 01 06:47:02 PM PDT 24
Peak memory	219644 kb
Host	smart-acccc67d-0225-40a7-bf67-1e32b2b41662
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605179138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e rrors.3605179138
Directory	/workspace/17.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.2139439514
Short name	T251
Test name
Test status
Simulation time	348369143 ps
CPU time	5.51 seconds
Started	Jul 01 06:45:33 PM PDT 24
Finished	Jul 01 06:45:41 PM PDT 24
Peak memory	223372 kb
Host	smart-22eaae93-e3bb-480d-800d-b1e15636e527
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139439514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta g_prog_failure.2139439514
Directory	/workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/17.lc_ctrl_jtag_smoke.3307742470
Short name	T799
Test name
Test status
Simulation time	748465740 ps
CPU time	6.18 seconds
Started	Jul 01 06:45:36 PM PDT 24
Finished	Jul 01 06:45:44 PM PDT 24
Peak memory	217996 kb
Host	smart-20406eed-f38a-4269-90da-f325cd60cbaa
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307742470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke .3307742470
Directory	/workspace/17.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/17.lc_ctrl_jtag_state_failure.1182058685
Short name	T652
Test name
Test status
Simulation time	3408879705 ps
CPU time	31.73 seconds
Started	Jul 01 06:45:36 PM PDT 24
Finished	Jul 01 06:46:09 PM PDT 24
Peak memory	251336 kb
Host	smart-c11235a5-bc0c-410b-8219-6985556db0bf
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182058685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt ag_state_failure.1182058685
Directory	/workspace/17.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.882839027
Short name	T711
Test name
Test status
Simulation time	1824422802 ps
CPU time	12.23 seconds
Started	Jul 01 06:45:40 PM PDT 24
Finished	Jul 01 06:45:55 PM PDT 24
Peak memory	251228 kb
Host	smart-de3662cd-ec1b-4006-8c2b-979ffefcb846
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882839027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_ jtag_state_post_trans.882839027
Directory	/workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/17.lc_ctrl_prog_failure.2998812729
Short name	T800
Test name
Test status
Simulation time	112146700 ps
CPU time	1.97 seconds
Started	Jul 01 06:45:36 PM PDT 24
Finished	Jul 01 06:45:40 PM PDT 24
Peak memory	218756 kb
Host	smart-c6cbb568-c746-4ff3-882e-edcc0bfa76dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2998812729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.2998812729
Directory	/workspace/17.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/17.lc_ctrl_sec_mubi.2435756172
Short name	T328
Test name
Test status
Simulation time	1467441395 ps
CPU time	15.26 seconds
Started	Jul 01 06:45:41 PM PDT 24
Finished	Jul 01 06:45:59 PM PDT 24
Peak memory	220388 kb
Host	smart-6f65228f-033b-4019-a7f4-46a47a46585c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435756172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.2435756172
Directory	/workspace/17.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/17.lc_ctrl_sec_token_digest.2809867390
Short name	T669
Test name
Test status
Simulation time	1059709165 ps
CPU time	10.42 seconds
Started	Jul 01 06:45:35 PM PDT 24
Finished	Jul 01 06:45:47 PM PDT 24
Peak memory	218584 kb
Host	smart-9e8fb85f-98af-42f3-ac88-cf4c0b0f1206
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809867390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d igest.2809867390
Directory	/workspace/17.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/17.lc_ctrl_sec_token_mux.3515138035
Short name	T572
Test name
Test status
Simulation time	273555316 ps
CPU time	10.67 seconds
Started	Jul 01 06:45:39 PM PDT 24
Finished	Jul 01 06:45:52 PM PDT 24
Peak memory	218568 kb
Host	smart-137282a0-a0a7-439a-8eda-fe95ce935349
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515138035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux. 3515138035
Directory	/workspace/17.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/17.lc_ctrl_security_escalation.3437458908
Short name	T587
Test name
Test status
Simulation time	419579671 ps
CPU time	8.32 seconds
Started	Jul 01 06:45:41 PM PDT 24
Finished	Jul 01 06:45:52 PM PDT 24
Peak memory	225432 kb
Host	smart-bab878ad-1b4a-4f0a-96cf-d95270b3d1ce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3437458908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.3437458908
Directory	/workspace/17.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/17.lc_ctrl_smoke.2750338022
Short name	T456
Test name
Test status
Simulation time	52347820 ps
CPU time	3.14 seconds
Started	Jul 01 06:45:40 PM PDT 24
Finished	Jul 01 06:45:46 PM PDT 24
Peak memory	215532 kb
Host	smart-9b166ac4-4429-48ff-af94-bbf4f88d80d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2750338022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.2750338022
Directory	/workspace/17.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/17.lc_ctrl_state_failure.3823330935
Short name	T567
Test name
Test status
Simulation time	888332051 ps
CPU time	28.61 seconds
Started	Jul 01 06:45:34 PM PDT 24
Finished	Jul 01 06:46:05 PM PDT 24
Peak memory	251504 kb
Host	smart-674e3819-1fc0-4c9c-894d-3fb75b5edd49
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3823330935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.3823330935
Directory	/workspace/17.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/17.lc_ctrl_state_post_trans.3038974477
Short name	T837
Test name
Test status
Simulation time	570111851 ps
CPU time	6.63 seconds
Started	Jul 01 06:45:34 PM PDT 24
Finished	Jul 01 06:45:42 PM PDT 24
Peak memory	247704 kb
Host	smart-1922d862-004c-41ac-a308-3defd1e2370b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3038974477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.3038974477
Directory	/workspace/17.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/17.lc_ctrl_stress_all.2462301694
Short name	T293
Test name
Test status
Simulation time	12998001733 ps
CPU time	356.79 seconds
Started	Jul 01 06:45:41 PM PDT 24
Finished	Jul 01 06:51:40 PM PDT 24
Peak memory	243248 kb
Host	smart-b5065b9d-20bd-4709-b33b-8a89905db21b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462301694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all.2462301694
Directory	/workspace/17.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.4108233072
Short name	T393
Test name
Test status
Simulation time	49417513 ps
CPU time	0.95 seconds
Started	Jul 01 06:45:37 PM PDT 24
Finished	Jul 01 06:45:40 PM PDT 24
Peak memory	209372 kb
Host	smart-1d1da36d-61a0-4830-9a67-f53d69cf8072
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108233072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c trl_volatile_unlock_smoke.4108233072
Directory	/workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/18.lc_ctrl_alert_test.1002300045
Short name	T656
Test name
Test status
Simulation time	39586123 ps
CPU time	1.59 seconds
Started	Jul 01 06:45:43 PM PDT 24
Finished	Jul 01 06:45:49 PM PDT 24
Peak memory	209456 kb
Host	smart-dc6753b2-376d-4e18-99e8-56a0364a0a60
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002300045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.1002300045
Directory	/workspace/18.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/18.lc_ctrl_errors.3574484593
Short name	T852
Test name
Test status
Simulation time	3278899281 ps
CPU time	9.7 seconds
Started	Jul 01 06:45:44 PM PDT 24
Finished	Jul 01 06:45:58 PM PDT 24
Peak memory	219580 kb
Host	smart-e6c058dd-c61f-4730-a807-797aa6a7319f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3574484593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.3574484593
Directory	/workspace/18.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/18.lc_ctrl_jtag_access.2511494821
Short name	T757
Test name
Test status
Simulation time	5266303421 ps
CPU time	4.31 seconds
Started	Jul 01 06:45:43 PM PDT 24
Finished	Jul 01 06:45:52 PM PDT 24
Peak memory	218216 kb
Host	smart-0043cdc8-e2fa-4bec-a400-2281d5b48a4b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511494821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.2511494821
Directory	/workspace/18.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/18.lc_ctrl_jtag_errors.2215914410
Short name	T256
Test name
Test status
Simulation time	3191633632 ps
CPU time	44.68 seconds
Started	Jul 01 06:45:44 PM PDT 24
Finished	Jul 01 06:46:33 PM PDT 24
Peak memory	218932 kb
Host	smart-a4a90794-29a7-4c11-b5b9-5d64b9f4cb9a
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215914410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e rrors.2215914410
Directory	/workspace/18.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.1908022891
Short name	T465
Test name
Test status
Simulation time	3103405058 ps
CPU time	6.29 seconds
Started	Jul 01 06:45:44 PM PDT 24
Finished	Jul 01 06:45:55 PM PDT 24
Peak memory	223972 kb
Host	smart-fa3e0107-0461-4ba6-9258-1ee1a90178fe
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908022891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta g_prog_failure.1908022891
Directory	/workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/18.lc_ctrl_jtag_smoke.2292239145
Short name	T822
Test name
Test status
Simulation time	403522155 ps
CPU time	4.59 seconds
Started	Jul 01 06:45:44 PM PDT 24
Finished	Jul 01 06:45:53 PM PDT 24
Peak memory	218204 kb
Host	smart-63253708-c424-4fbe-9ce0-bde1c8864165
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292239145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke .2292239145
Directory	/workspace/18.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/18.lc_ctrl_jtag_state_failure.3713345630
Short name	T798
Test name
Test status
Simulation time	3389356764 ps
CPU time	61.09 seconds
Started	Jul 01 06:45:45 PM PDT 24
Finished	Jul 01 06:46:51 PM PDT 24
Peak memory	284064 kb
Host	smart-1b35151b-4220-4cfb-b171-cee2a085e503
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713345630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt ag_state_failure.3713345630
Directory	/workspace/18.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.2745509230
Short name	T509
Test name
Test status
Simulation time	471627762 ps
CPU time	12.41 seconds
Started	Jul 01 06:45:45 PM PDT 24
Finished	Jul 01 06:46:02 PM PDT 24
Peak memory	248036 kb
Host	smart-03b50c6b-417b-4ded-a408-5f03f34adfc9
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745509230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl _jtag_state_post_trans.2745509230
Directory	/workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/18.lc_ctrl_prog_failure.1967089959
Short name	T585
Test name
Test status
Simulation time	453155942 ps
CPU time	3.33 seconds
Started	Jul 01 06:45:44 PM PDT 24
Finished	Jul 01 06:45:52 PM PDT 24
Peak memory	223052 kb
Host	smart-3e873d0c-1208-4d62-b449-376bd8803eed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1967089959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.1967089959
Directory	/workspace/18.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/18.lc_ctrl_sec_token_digest.3449902485
Short name	T510
Test name
Test status
Simulation time	513418365 ps
CPU time	10.58 seconds
Started	Jul 01 06:45:43 PM PDT 24
Finished	Jul 01 06:45:59 PM PDT 24
Peak memory	218688 kb
Host	smart-819e13db-715b-4af6-accf-4f5561530bc6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449902485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d igest.3449902485
Directory	/workspace/18.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/18.lc_ctrl_sec_token_mux.991311904
Short name	T167
Test name
Test status
Simulation time	1286879722 ps
CPU time	8.71 seconds
Started	Jul 01 06:45:45 PM PDT 24
Finished	Jul 01 06:45:58 PM PDT 24
Peak memory	218632 kb
Host	smart-56cf4240-a91a-4293-9cef-44f965b6b8ff
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991311904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.991311904
Directory	/workspace/18.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/18.lc_ctrl_security_escalation.3082696056
Short name	T496
Test name
Test status
Simulation time	221116679 ps
CPU time	6.83 seconds
Started	Jul 01 06:45:44 PM PDT 24
Finished	Jul 01 06:45:55 PM PDT 24
Peak memory	224656 kb
Host	smart-6dd4b59c-62ab-4e3f-acbb-e4a4d48c4a3c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3082696056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.3082696056
Directory	/workspace/18.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/18.lc_ctrl_smoke.93578318
Short name	T501
Test name
Test status
Simulation time	257959279 ps
CPU time	7.49 seconds
Started	Jul 01 06:45:40 PM PDT 24
Finished	Jul 01 06:45:49 PM PDT 24
Peak memory	218072 kb
Host	smart-5f296296-ac77-4412-b4bf-da31291c9bb6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=93578318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.93578318
Directory	/workspace/18.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/18.lc_ctrl_state_failure.888552789
Short name	T865
Test name
Test status
Simulation time	446075916 ps
CPU time	20.48 seconds
Started	Jul 01 06:45:36 PM PDT 24
Finished	Jul 01 06:45:58 PM PDT 24
Peak memory	251516 kb
Host	smart-9db21089-2161-464e-8042-20242c97957c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=888552789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.888552789
Directory	/workspace/18.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/18.lc_ctrl_state_post_trans.865685967
Short name	T758
Test name
Test status
Simulation time	268028893 ps
CPU time	8.14 seconds
Started	Jul 01 06:45:35 PM PDT 24
Finished	Jul 01 06:45:45 PM PDT 24
Peak memory	251320 kb
Host	smart-444fe8ab-93cf-44f9-88df-05c1d379be5e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=865685967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.865685967
Directory	/workspace/18.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/18.lc_ctrl_stress_all.782741738
Short name	T494
Test name
Test status
Simulation time	5136408445 ps
CPU time	210.2 seconds
Started	Jul 01 06:45:44 PM PDT 24
Finished	Jul 01 06:49:19 PM PDT 24
Peak memory	276200 kb
Host	smart-b8fccd1a-58c1-4469-8749-77946ffce5ab
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782741738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all.782741738
Directory	/workspace/18.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.3429490704
Short name	T162
Test name
Test status
Simulation time	81976404710 ps
CPU time	734.2 seconds
Started	Jul 01 06:45:43 PM PDT 24
Finished	Jul 01 06:58:02 PM PDT 24
Peak memory	464468 kb
Host	smart-48834a4f-2259-4bd8-8d89-00de8edc9149
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3429490704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.3429490704
Directory	/workspace/18.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.2761840010
Short name	T766
Test name
Test status
Simulation time	25105431 ps
CPU time	0.92 seconds
Started	Jul 01 06:45:36 PM PDT 24
Finished	Jul 01 06:45:38 PM PDT 24
Peak memory	209496 kb
Host	smart-4d4e8eb0-b342-40f3-9beb-a79c19e23511
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761840010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c trl_volatile_unlock_smoke.2761840010
Directory	/workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/19.lc_ctrl_alert_test.1954947742
Short name	T314
Test name
Test status
Simulation time	23504561 ps
CPU time	1.17 seconds
Started	Jul 01 06:45:53 PM PDT 24
Finished	Jul 01 06:45:57 PM PDT 24
Peak memory	209516 kb
Host	smart-286fe896-febd-48d3-ab2b-64e061a9e89d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954947742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.1954947742
Directory	/workspace/19.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/19.lc_ctrl_errors.391578980
Short name	T475
Test name
Test status
Simulation time	331629146 ps
CPU time	7.43 seconds
Started	Jul 01 06:45:44 PM PDT 24
Finished	Jul 01 06:45:56 PM PDT 24
Peak memory	218636 kb
Host	smart-2389fb56-fcb9-4802-9585-c05d4a4c83d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=391578980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.391578980
Directory	/workspace/19.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/19.lc_ctrl_jtag_access.3639237623
Short name	T680
Test name
Test status
Simulation time	352586581 ps
CPU time	5.44 seconds
Started	Jul 01 06:45:52 PM PDT 24
Finished	Jul 01 06:46:01 PM PDT 24
Peak memory	217664 kb
Host	smart-33b1563e-8854-4714-bfae-cfe64d60e072
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639237623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.3639237623
Directory	/workspace/19.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/19.lc_ctrl_jtag_errors.1695790234
Short name	T694
Test name
Test status
Simulation time	2230063556 ps
CPU time	20.32 seconds
Started	Jul 01 06:45:50 PM PDT 24
Finished	Jul 01 06:46:12 PM PDT 24
Peak memory	226432 kb
Host	smart-bde915e6-c548-4645-bbd0-d721ec227080
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695790234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e rrors.1695790234
Directory	/workspace/19.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.2640133736
Short name	T825
Test name
Test status
Simulation time	1108898326 ps
CPU time	4.63 seconds
Started	Jul 01 06:45:52 PM PDT 24
Finished	Jul 01 06:46:00 PM PDT 24
Peak memory	222216 kb
Host	smart-9d131e92-37de-47cd-b83c-1357e52aa020
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640133736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta g_prog_failure.2640133736
Directory	/workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/19.lc_ctrl_jtag_smoke.1064891472
Short name	T111
Test name
Test status
Simulation time	3502455986 ps
CPU time	20.25 seconds
Started	Jul 01 06:45:44 PM PDT 24
Finished	Jul 01 06:46:09 PM PDT 24
Peak memory	218156 kb
Host	smart-b394adb8-dad2-45b9-8d9e-89495eae9fec
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064891472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke .1064891472
Directory	/workspace/19.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/19.lc_ctrl_jtag_state_failure.3860100999
Short name	T351
Test name
Test status
Simulation time	2182745596 ps
CPU time	45.45 seconds
Started	Jul 01 06:45:43 PM PDT 24
Finished	Jul 01 06:46:32 PM PDT 24
Peak memory	268088 kb
Host	smart-381f9b15-be8b-40d8-977f-b134578a347e
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860100999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt ag_state_failure.3860100999
Directory	/workspace/19.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.323775302
Short name	T39
Test name
Test status
Simulation time	584698093 ps
CPU time	17.24 seconds
Started	Jul 01 06:45:46 PM PDT 24
Finished	Jul 01 06:46:07 PM PDT 24
Peak memory	251216 kb
Host	smart-d28fc287-ad54-40be-bc94-967997a2ed77
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323775302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_ jtag_state_post_trans.323775302
Directory	/workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/19.lc_ctrl_prog_failure.2454577202
Short name	T792
Test name
Test status
Simulation time	322198602 ps
CPU time	3.1 seconds
Started	Jul 01 06:45:43 PM PDT 24
Finished	Jul 01 06:45:51 PM PDT 24
Peak memory	222992 kb
Host	smart-395da053-f580-42e6-85e4-1ecc78844b29
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2454577202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.2454577202
Directory	/workspace/19.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/19.lc_ctrl_sec_mubi.556098575
Short name	T373
Test name
Test status
Simulation time	7010050460 ps
CPU time	13.34 seconds
Started	Jul 01 06:45:52 PM PDT 24
Finished	Jul 01 06:46:08 PM PDT 24
Peak memory	226564 kb
Host	smart-c02987c3-c180-4ef4-94ae-e3fda1b78771
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556098575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.556098575
Directory	/workspace/19.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/19.lc_ctrl_sec_token_digest.2231068011
Short name	T797
Test name
Test status
Simulation time	951979341 ps
CPU time	8.9 seconds
Started	Jul 01 06:45:53 PM PDT 24
Finished	Jul 01 06:46:05 PM PDT 24
Peak memory	218668 kb
Host	smart-25eef039-1446-4bcc-b57e-136d55c06f81
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231068011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d igest.2231068011
Directory	/workspace/19.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/19.lc_ctrl_sec_token_mux.2867486950
Short name	T849
Test name
Test status
Simulation time	1118932603 ps
CPU time	12.17 seconds
Started	Jul 01 06:45:52 PM PDT 24
Finished	Jul 01 06:46:07 PM PDT 24
Peak memory	226408 kb
Host	smart-f6e7b453-8dc6-4cd7-b6f4-8b3eb50bd074
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867486950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux. 2867486950
Directory	/workspace/19.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/19.lc_ctrl_security_escalation.2914335481
Short name	T471
Test name
Test status
Simulation time	2818188567 ps
CPU time	9.41 seconds
Started	Jul 01 06:45:45 PM PDT 24
Finished	Jul 01 06:45:59 PM PDT 24
Peak memory	226580 kb
Host	smart-696121a4-f9ab-4437-8c4a-afaef822ad10
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2914335481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.2914335481
Directory	/workspace/19.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/19.lc_ctrl_smoke.2017957949
Short name	T84
Test name
Test status
Simulation time	28686002 ps
CPU time	1.16 seconds
Started	Jul 01 06:45:45 PM PDT 24
Finished	Jul 01 06:45:51 PM PDT 24
Peak memory	214128 kb
Host	smart-b5787925-7fab-4dc6-a746-54c504aee64f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2017957949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.2017957949
Directory	/workspace/19.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/19.lc_ctrl_state_failure.2512064246
Short name	T177
Test name
Test status
Simulation time	1343973400 ps
CPU time	35.21 seconds
Started	Jul 01 06:45:43 PM PDT 24
Finished	Jul 01 06:46:23 PM PDT 24
Peak memory	251288 kb
Host	smart-e5af5fcd-962c-41da-8d71-6c52a8bfdf09
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2512064246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.2512064246
Directory	/workspace/19.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/19.lc_ctrl_state_post_trans.2635264798
Short name	T329
Test name
Test status
Simulation time	589401986 ps
CPU time	9.8 seconds
Started	Jul 01 06:45:44 PM PDT 24
Finished	Jul 01 06:45:58 PM PDT 24
Peak memory	247264 kb
Host	smart-2530c6c9-4162-4c45-a1fb-aa4d593046a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2635264798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.2635264798
Directory	/workspace/19.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/19.lc_ctrl_stress_all.365838906
Short name	T354
Test name
Test status
Simulation time	7812344799 ps
CPU time	123.15 seconds
Started	Jul 01 06:45:53 PM PDT 24
Finished	Jul 01 06:47:59 PM PDT 24
Peak memory	260032 kb
Host	smart-569b615b-98e7-4b8e-8bf2-220b7a1febf4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365838906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all.365838906
Directory	/workspace/19.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.3921911452
Short name	T566
Test name
Test status
Simulation time	14289354 ps
CPU time	1.1 seconds
Started	Jul 01 06:45:44 PM PDT 24
Finished	Jul 01 06:45:50 PM PDT 24
Peak memory	212216 kb
Host	smart-17f6fc86-494f-4553-8567-4e5aef8f6055
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921911452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c trl_volatile_unlock_smoke.3921911452
Directory	/workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/2.lc_ctrl_alert_test.3959799171
Short name	T495
Test name
Test status
Simulation time	53201397 ps
CPU time	0.88 seconds
Started	Jul 01 06:44:01 PM PDT 24
Finished	Jul 01 06:44:03 PM PDT 24
Peak memory	209188 kb
Host	smart-77ad53db-2b62-40b2-b6b2-2d05b9ff1943
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959799171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.3959799171
Directory	/workspace/2.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/2.lc_ctrl_errors.11462816
Short name	T816
Test name
Test status
Simulation time	636356260 ps
CPU time	7.74 seconds
Started	Jul 01 06:43:54 PM PDT 24
Finished	Jul 01 06:44:03 PM PDT 24
Peak memory	218640 kb
Host	smart-d74fa7da-1304-4d2e-9125-999dfdb98286
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=11462816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.11462816
Directory	/workspace/2.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_access.901423478
Short name	T857
Test name
Test status
Simulation time	755164086 ps
CPU time	10.35 seconds
Started	Jul 01 06:43:54 PM PDT 24
Finished	Jul 01 06:44:06 PM PDT 24
Peak memory	218100 kb
Host	smart-f76fb40a-33ad-4d87-99c5-1dc963d7c57d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901423478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.901423478
Directory	/workspace/2.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_errors.3508179885
Short name	T116
Test name
Test status
Simulation time	16574802991 ps
CPU time	53.82 seconds
Started	Jul 01 06:43:53 PM PDT 24
Finished	Jul 01 06:44:49 PM PDT 24
Peak memory	226440 kb
Host	smart-47fac34a-c65c-439e-a972-e65b380189b7
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508179885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er rors.3508179885
Directory	/workspace/2.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_priority.3990384839
Short name	T526
Test name
Test status
Simulation time	1037531019 ps
CPU time	6.06 seconds
Started	Jul 01 06:43:52 PM PDT 24
Finished	Jul 01 06:43:59 PM PDT 24
Peak memory	218104 kb
Host	smart-a96555c1-69c2-4c53-bc14-f7c0cb34cc8e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990384839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.3 990384839
Directory	/workspace/2.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.2688166735
Short name	T603
Test name
Test status
Simulation time	373212476 ps
CPU time	8.06 seconds
Started	Jul 01 06:43:52 PM PDT 24
Finished	Jul 01 06:44:02 PM PDT 24
Peak memory	218584 kb
Host	smart-8f7bf550-339d-46ee-8df7-68edcb52dbfd
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688166735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag _prog_failure.2688166735
Directory	/workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.1288757139
Short name	T223
Test name
Test status
Simulation time	1209506725 ps
CPU time	19.13 seconds
Started	Jul 01 06:43:53 PM PDT 24
Finished	Jul 01 06:44:13 PM PDT 24
Peak memory	218096 kb
Host	smart-a3950d5c-1c9f-44e3-a1f8-1aa32a680af2
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288757139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_ jtag_regwen_during_op.1288757139
Directory	/workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_smoke.668474772
Short name	T795
Test name
Test status
Simulation time	1473465323 ps
CPU time	17.3 seconds
Started	Jul 01 06:43:54 PM PDT 24
Finished	Jul 01 06:44:13 PM PDT 24
Peak memory	218124 kb
Host	smart-2bcc9596-0360-4539-be9f-36b05a5854a6
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668474772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.668474772
Directory	/workspace/2.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_state_failure.3738876143
Short name	T864
Test name
Test status
Simulation time	5617634824 ps
CPU time	40.93 seconds
Started	Jul 01 06:43:54 PM PDT 24
Finished	Jul 01 06:44:36 PM PDT 24
Peak memory	251528 kb
Host	smart-b8165b83-c377-44b2-9b8b-69be6478e13e
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738876143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta g_state_failure.3738876143
Directory	/workspace/2.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.1464141722
Short name	T246
Test name
Test status
Simulation time	667396242 ps
CPU time	13.84 seconds
Started	Jul 01 06:43:52 PM PDT 24
Finished	Jul 01 06:44:08 PM PDT 24
Peak memory	246800 kb
Host	smart-786c0919-f8a7-4543-9932-f4aa979f4f9b
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464141722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_ jtag_state_post_trans.1464141722
Directory	/workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/2.lc_ctrl_prog_failure.1865891962
Short name	T845
Test name
Test status
Simulation time	64906063 ps
CPU time	1.86 seconds
Started	Jul 01 06:43:53 PM PDT 24
Finished	Jul 01 06:43:57 PM PDT 24
Peak memory	218732 kb
Host	smart-8bd5e611-d6f3-4c24-93ce-58fcb77a775e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1865891962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.1865891962
Directory	/workspace/2.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/2.lc_ctrl_regwen_during_op.1589503569
Short name	T636
Test name
Test status
Simulation time	405698906 ps
CPU time	5.23 seconds
Started	Jul 01 06:43:52 PM PDT 24
Finished	Jul 01 06:43:59 PM PDT 24
Peak memory	218044 kb
Host	smart-b266a4ba-466d-4e18-b3b2-1352edfe7533
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1589503569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.1589503569
Directory	/workspace/2.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/2.lc_ctrl_sec_cm.3081624550
Short name	T117
Test name
Test status
Simulation time	417003954 ps
CPU time	23.77 seconds
Started	Jul 01 06:43:58 PM PDT 24
Finished	Jul 01 06:44:23 PM PDT 24
Peak memory	281736 kb
Host	smart-e4c16da7-f652-4ab5-9fbe-f64cecf552b6
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081624550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.3081624550
Directory	/workspace/2.lc_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/2.lc_ctrl_sec_mubi.700984155
Short name	T273
Test name
Test status
Simulation time	2074765369 ps
CPU time	16.72 seconds
Started	Jul 01 06:43:51 PM PDT 24
Finished	Jul 01 06:44:09 PM PDT 24
Peak memory	226464 kb
Host	smart-d01f875f-6b43-4332-b1a2-a4de4480c793
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700984155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.700984155
Directory	/workspace/2.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/2.lc_ctrl_sec_token_digest.163205770
Short name	T763
Test name
Test status
Simulation time	3197243216 ps
CPU time	10.88 seconds
Started	Jul 01 06:43:51 PM PDT 24
Finished	Jul 01 06:44:03 PM PDT 24
Peak memory	218668 kb
Host	smart-34dc609b-3658-47f9-9f6c-37245ef646e7
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163205770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_dig est.163205770
Directory	/workspace/2.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/2.lc_ctrl_sec_token_mux.232416475
Short name	T56
Test name
Test status
Simulation time	791158587 ps
CPU time	6 seconds
Started	Jul 01 06:43:53 PM PDT 24
Finished	Jul 01 06:44:01 PM PDT 24
Peak memory	218708 kb
Host	smart-9b4e3473-0225-421f-84e3-93f5e36a1402
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232416475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.232416475
Directory	/workspace/2.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/2.lc_ctrl_smoke.4223100699
Short name	T309
Test name
Test status
Simulation time	85143375 ps
CPU time	1.31 seconds
Started	Jul 01 06:43:50 PM PDT 24
Finished	Jul 01 06:43:53 PM PDT 24
Peak memory	214248 kb
Host	smart-da362448-189b-4d1e-8945-9b0828f546fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4223100699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.4223100699
Directory	/workspace/2.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/2.lc_ctrl_state_failure.3354783568
Short name	T279
Test name
Test status
Simulation time	837864920 ps
CPU time	20.4 seconds
Started	Jul 01 06:43:50 PM PDT 24
Finished	Jul 01 06:44:12 PM PDT 24
Peak memory	251352 kb
Host	smart-87febf1d-271c-47ac-8ae2-a4cb5d363af3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3354783568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.3354783568
Directory	/workspace/2.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/2.lc_ctrl_state_post_trans.2356126989
Short name	T878
Test name
Test status
Simulation time	192520213 ps
CPU time	6.27 seconds
Started	Jul 01 06:43:53 PM PDT 24
Finished	Jul 01 06:44:01 PM PDT 24
Peak memory	250908 kb
Host	smart-8991e5ed-b298-4d84-b84a-232a7b18c4b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2356126989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.2356126989
Directory	/workspace/2.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/2.lc_ctrl_stress_all.3385867051
Short name	T624
Test name
Test status
Simulation time	2003042138 ps
CPU time	59.12 seconds
Started	Jul 01 06:43:53 PM PDT 24
Finished	Jul 01 06:44:53 PM PDT 24
Peak memory	226348 kb
Host	smart-40a28ca6-8053-4415-a2f4-c98186b86f45
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385867051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all.3385867051
Directory	/workspace/2.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.209216830
Short name	T304
Test name
Test status
Simulation time	13711100 ps
CPU time	0.96 seconds
Started	Jul 01 06:43:46 PM PDT 24
Finished	Jul 01 06:43:48 PM PDT 24
Peak memory	212336 kb
Host	smart-aad1dcbd-a076-43cf-be4b-aa998decbba0
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209216830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctr l_volatile_unlock_smoke.209216830
Directory	/workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/20.lc_ctrl_alert_test.1939197312
Short name	T275
Test name
Test status
Simulation time	68638800 ps
CPU time	1.13 seconds
Started	Jul 01 06:45:50 PM PDT 24
Finished	Jul 01 06:45:54 PM PDT 24
Peak memory	209552 kb
Host	smart-656ba7f3-ab00-4755-bb89-dc8497c514f5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939197312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.1939197312
Directory	/workspace/20.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/20.lc_ctrl_errors.1413567443
Short name	T443
Test name
Test status
Simulation time	310836629 ps
CPU time	11.1 seconds
Started	Jul 01 06:45:52 PM PDT 24
Finished	Jul 01 06:46:06 PM PDT 24
Peak memory	226448 kb
Host	smart-592fe8a2-ebf5-41c6-a42f-c9fd4f73a3f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1413567443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.1413567443
Directory	/workspace/20.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/20.lc_ctrl_jtag_access.1408368793
Short name	T21
Test name
Test status
Simulation time	482246400 ps
CPU time	6.62 seconds
Started	Jul 01 06:45:53 PM PDT 24
Finished	Jul 01 06:46:03 PM PDT 24
Peak memory	217632 kb
Host	smart-6e651278-8781-4e23-9b8e-98a11f32ced2
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408368793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.1408368793
Directory	/workspace/20.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/20.lc_ctrl_prog_failure.4271164829
Short name	T874
Test name
Test status
Simulation time	80300090 ps
CPU time	1.56 seconds
Started	Jul 01 06:45:53 PM PDT 24
Finished	Jul 01 06:45:57 PM PDT 24
Peak memory	218784 kb
Host	smart-da6a5f32-325f-4a98-b7e5-959b2a3af055
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4271164829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.4271164829
Directory	/workspace/20.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/20.lc_ctrl_sec_mubi.106255609
Short name	T492
Test name
Test status
Simulation time	1509402627 ps
CPU time	12.07 seconds
Started	Jul 01 06:45:52 PM PDT 24
Finished	Jul 01 06:46:07 PM PDT 24
Peak memory	226568 kb
Host	smart-7f55d355-1dde-4350-a826-e70edf49cea0
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106255609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.106255609
Directory	/workspace/20.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/20.lc_ctrl_sec_token_digest.3569609554
Short name	T65
Test name
Test status
Simulation time	936346890 ps
CPU time	9.72 seconds
Started	Jul 01 06:45:54 PM PDT 24
Finished	Jul 01 06:46:06 PM PDT 24
Peak memory	218672 kb
Host	smart-9b01ec75-5a19-4565-9973-2a99ae024e27
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569609554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d igest.3569609554
Directory	/workspace/20.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/20.lc_ctrl_sec_token_mux.1865096586
Short name	T606
Test name
Test status
Simulation time	966811095 ps
CPU time	15.05 seconds
Started	Jul 01 06:46:00 PM PDT 24
Finished	Jul 01 06:46:16 PM PDT 24
Peak memory	218772 kb
Host	smart-5a4e8d52-97c1-4f9c-8279-fb8a3e289a84
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865096586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux. 1865096586
Directory	/workspace/20.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/20.lc_ctrl_smoke.3562254509
Short name	T366
Test name
Test status
Simulation time	455523585 ps
CPU time	7.46 seconds
Started	Jul 01 06:45:51 PM PDT 24
Finished	Jul 01 06:46:00 PM PDT 24
Peak memory	218184 kb
Host	smart-515f1297-d26c-414a-8315-1981b74c58f7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3562254509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.3562254509
Directory	/workspace/20.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/20.lc_ctrl_state_failure.4282825702
Short name	T614
Test name
Test status
Simulation time	373801653 ps
CPU time	22.15 seconds
Started	Jul 01 06:45:51 PM PDT 24
Finished	Jul 01 06:46:17 PM PDT 24
Peak memory	251460 kb
Host	smart-c2a1bc48-bc40-44d8-bdc6-4ddff48e0677
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4282825702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.4282825702
Directory	/workspace/20.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/20.lc_ctrl_state_post_trans.1817482778
Short name	T773
Test name
Test status
Simulation time	635377845 ps
CPU time	2.86 seconds
Started	Jul 01 06:45:51 PM PDT 24
Finished	Jul 01 06:45:56 PM PDT 24
Peak memory	226748 kb
Host	smart-6278cc0b-583c-412c-8461-37c630da9ecd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1817482778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.1817482778
Directory	/workspace/20.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/20.lc_ctrl_stress_all.3853934279
Short name	T769
Test name
Test status
Simulation time	31446023426 ps
CPU time	147.64 seconds
Started	Jul 01 06:46:00 PM PDT 24
Finished	Jul 01 06:48:30 PM PDT 24
Peak memory	273420 kb
Host	smart-3ca09e01-3f0e-45a3-a12f-c06150e3dcbd
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853934279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all.3853934279
Directory	/workspace/20.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.4054821494
Short name	T690
Test name
Test status
Simulation time	12192814 ps
CPU time	0.81 seconds
Started	Jul 01 06:45:51 PM PDT 24
Finished	Jul 01 06:45:54 PM PDT 24
Peak memory	209304 kb
Host	smart-cc86d342-0400-4dc8-9f02-0508cfed42a4
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054821494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c trl_volatile_unlock_smoke.4054821494
Directory	/workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/21.lc_ctrl_alert_test.2334394866
Short name	T431
Test name
Test status
Simulation time	91705017 ps
CPU time	1.27 seconds
Started	Jul 01 06:46:00 PM PDT 24
Finished	Jul 01 06:46:02 PM PDT 24
Peak memory	209372 kb
Host	smart-6e865501-88a0-4356-8d8c-8dfcfaea9a8a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334394866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.2334394866
Directory	/workspace/21.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/21.lc_ctrl_errors.3347080195
Short name	T115
Test name
Test status
Simulation time	2645658260 ps
CPU time	14.12 seconds
Started	Jul 01 06:45:59 PM PDT 24
Finished	Jul 01 06:46:14 PM PDT 24
Peak memory	218896 kb
Host	smart-c7b407ba-cb42-4f97-9040-ff733414da50
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3347080195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.3347080195
Directory	/workspace/21.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/21.lc_ctrl_jtag_access.2178374959
Short name	T352
Test name
Test status
Simulation time	959143559 ps
CPU time	6.92 seconds
Started	Jul 01 06:45:54 PM PDT 24
Finished	Jul 01 06:46:03 PM PDT 24
Peak memory	217792 kb
Host	smart-1091188a-ccf4-4a47-8ee1-5d0a5721f32a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178374959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.2178374959
Directory	/workspace/21.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/21.lc_ctrl_prog_failure.1217421860
Short name	T276
Test name
Test status
Simulation time	132904377 ps
CPU time	2.78 seconds
Started	Jul 01 06:45:59 PM PDT 24
Finished	Jul 01 06:46:03 PM PDT 24
Peak memory	222992 kb
Host	smart-300dc0d2-9d4a-4850-8884-fe0936b0980d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1217421860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.1217421860
Directory	/workspace/21.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/21.lc_ctrl_sec_mubi.3094139202
Short name	T268
Test name
Test status
Simulation time	1466507042 ps
CPU time	15.67 seconds
Started	Jul 01 06:45:52 PM PDT 24
Finished	Jul 01 06:46:10 PM PDT 24
Peak memory	226608 kb
Host	smart-c62e6014-474a-437d-97c2-2a43b8b40b60
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094139202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.3094139202
Directory	/workspace/21.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/21.lc_ctrl_sec_token_digest.3822637422
Short name	T434
Test name
Test status
Simulation time	1949222260 ps
CPU time	17.1 seconds
Started	Jul 01 06:45:53 PM PDT 24
Finished	Jul 01 06:46:13 PM PDT 24
Peak memory	218600 kb
Host	smart-c1347096-63bd-4c73-95e1-d8d1af550634
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822637422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d igest.3822637422
Directory	/workspace/21.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/21.lc_ctrl_sec_token_mux.2483690753
Short name	T692
Test name
Test status
Simulation time	346007677 ps
CPU time	12.05 seconds
Started	Jul 01 06:45:52 PM PDT 24
Finished	Jul 01 06:46:07 PM PDT 24
Peak memory	218600 kb
Host	smart-5020ff6a-e880-4230-a446-cd8c6aea402f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483690753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux. 2483690753
Directory	/workspace/21.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/21.lc_ctrl_security_escalation.3766293104
Short name	T504
Test name
Test status
Simulation time	323262675 ps
CPU time	7.97 seconds
Started	Jul 01 06:45:53 PM PDT 24
Finished	Jul 01 06:46:04 PM PDT 24
Peak memory	225468 kb
Host	smart-f6b9c4d7-7f15-4fd6-a7fe-fd726be71867
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3766293104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.3766293104
Directory	/workspace/21.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/21.lc_ctrl_smoke.71454286
Short name	T811
Test name
Test status
Simulation time	231364041 ps
CPU time	2.52 seconds
Started	Jul 01 06:45:52 PM PDT 24
Finished	Jul 01 06:45:58 PM PDT 24
Peak memory	215024 kb
Host	smart-a5876ea3-95b0-4fa4-bb6e-08e131a584fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=71454286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.71454286
Directory	/workspace/21.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/21.lc_ctrl_state_failure.2290879468
Short name	T175
Test name
Test status
Simulation time	1725740607 ps
CPU time	37.22 seconds
Started	Jul 01 06:45:59 PM PDT 24
Finished	Jul 01 06:46:38 PM PDT 24
Peak memory	251520 kb
Host	smart-c87d0186-a82b-40dd-aec7-f4b57108866b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2290879468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.2290879468
Directory	/workspace/21.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/21.lc_ctrl_state_post_trans.3685022318
Short name	T290
Test name
Test status
Simulation time	569907291 ps
CPU time	3.33 seconds
Started	Jul 01 06:45:52 PM PDT 24
Finished	Jul 01 06:45:59 PM PDT 24
Peak memory	226740 kb
Host	smart-dcda5511-2769-416d-b5c4-d9037d23f645
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3685022318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.3685022318
Directory	/workspace/21.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/21.lc_ctrl_stress_all.2651454613
Short name	T480
Test name
Test status
Simulation time	5169527254 ps
CPU time	51.43 seconds
Started	Jul 01 06:45:54 PM PDT 24
Finished	Jul 01 06:46:48 PM PDT 24
Peak memory	251304 kb
Host	smart-fd2d6534-5ef9-4e96-bc2f-5d1c7ffb1e83
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651454613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all.2651454613
Directory	/workspace/21.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.1091676542
Short name	T487
Test name
Test status
Simulation time	33859792 ps
CPU time	0.81 seconds
Started	Jul 01 06:45:59 PM PDT 24
Finished	Jul 01 06:46:00 PM PDT 24
Peak memory	209452 kb
Host	smart-a28db6e6-7125-4172-9ae1-eae853431be8
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091676542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c trl_volatile_unlock_smoke.1091676542
Directory	/workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/22.lc_ctrl_alert_test.3951425791
Short name	T75
Test name
Test status
Simulation time	26975086 ps
CPU time	1.06 seconds
Started	Jul 01 06:45:59 PM PDT 24
Finished	Jul 01 06:46:00 PM PDT 24
Peak memory	209532 kb
Host	smart-fbe5c451-2d4f-4f68-a4b7-39e564926c72
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951425791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.3951425791
Directory	/workspace/22.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/22.lc_ctrl_errors.648110346
Short name	T51
Test name
Test status
Simulation time	558382315 ps
CPU time	11.11 seconds
Started	Jul 01 06:46:01 PM PDT 24
Finished	Jul 01 06:46:14 PM PDT 24
Peak memory	226448 kb
Host	smart-b3b057ba-b77b-4149-9ede-59e3307de981
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=648110346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.648110346
Directory	/workspace/22.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/22.lc_ctrl_jtag_access.739356753
Short name	T574
Test name
Test status
Simulation time	739755713 ps
CPU time	9.99 seconds
Started	Jul 01 06:46:02 PM PDT 24
Finished	Jul 01 06:46:14 PM PDT 24
Peak memory	217844 kb
Host	smart-3c5a38d5-7fc8-45b4-b30a-2be27077dafe
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739356753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.739356753
Directory	/workspace/22.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/22.lc_ctrl_prog_failure.2840694635
Short name	T679
Test name
Test status
Simulation time	184266721 ps
CPU time	2.37 seconds
Started	Jul 01 06:46:01 PM PDT 24
Finished	Jul 01 06:46:06 PM PDT 24
Peak memory	222712 kb
Host	smart-52090d02-e6de-40c3-8d75-cb3aae6ec281
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2840694635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.2840694635
Directory	/workspace/22.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/22.lc_ctrl_sec_mubi.1762166864
Short name	T259
Test name
Test status
Simulation time	6529082388 ps
CPU time	12.19 seconds
Started	Jul 01 06:45:59 PM PDT 24
Finished	Jul 01 06:46:12 PM PDT 24
Peak memory	226556 kb
Host	smart-a62f0689-5ceb-4372-b60c-c6ced280562b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762166864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.1762166864
Directory	/workspace/22.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/22.lc_ctrl_sec_token_digest.1241736835
Short name	T575
Test name
Test status
Simulation time	399086486 ps
CPU time	14.23 seconds
Started	Jul 01 06:46:08 PM PDT 24
Finished	Jul 01 06:46:23 PM PDT 24
Peak memory	218584 kb
Host	smart-01dd2e8a-34c9-47a4-a458-1e3fe31447b3
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241736835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d igest.1241736835
Directory	/workspace/22.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/22.lc_ctrl_sec_token_mux.4266072907
Short name	T46
Test name
Test status
Simulation time	1256265720 ps
CPU time	7.86 seconds
Started	Jul 01 06:46:02 PM PDT 24
Finished	Jul 01 06:46:12 PM PDT 24
Peak memory	218636 kb
Host	smart-134a4baf-8189-4353-be91-a45bb023e1f1
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266072907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux. 4266072907
Directory	/workspace/22.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/22.lc_ctrl_security_escalation.4037694421
Short name	T740
Test name
Test status
Simulation time	400948680 ps
CPU time	13.78 seconds
Started	Jul 01 06:46:07 PM PDT 24
Finished	Jul 01 06:46:22 PM PDT 24
Peak memory	226448 kb
Host	smart-5a9e1b1a-1d12-4467-91f3-eddae0c371b3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4037694421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.4037694421
Directory	/workspace/22.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/22.lc_ctrl_smoke.1703114768
Short name	T447
Test name
Test status
Simulation time	172175726 ps
CPU time	2.1 seconds
Started	Jul 01 06:46:00 PM PDT 24
Finished	Jul 01 06:46:03 PM PDT 24
Peak memory	214656 kb
Host	smart-fe712fee-5424-4152-bb20-6008cd1f2aa6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1703114768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.1703114768
Directory	/workspace/22.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/22.lc_ctrl_state_failure.3953124167
Short name	T310
Test name
Test status
Simulation time	204262206 ps
CPU time	27.04 seconds
Started	Jul 01 06:46:09 PM PDT 24
Finished	Jul 01 06:46:37 PM PDT 24
Peak memory	251344 kb
Host	smart-675e0d8e-b675-41e4-b77e-00c69f196659
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3953124167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.3953124167
Directory	/workspace/22.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/22.lc_ctrl_state_post_trans.4276907723
Short name	T681
Test name
Test status
Simulation time	316250195 ps
CPU time	7.63 seconds
Started	Jul 01 06:46:01 PM PDT 24
Finished	Jul 01 06:46:11 PM PDT 24
Peak memory	251344 kb
Host	smart-b83e9b6a-b5d3-415c-bf5e-60237ebcbbb4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4276907723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.4276907723
Directory	/workspace/22.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/22.lc_ctrl_stress_all.3893014671
Short name	T67
Test name
Test status
Simulation time	21901497017 ps
CPU time	140.33 seconds
Started	Jul 01 06:46:01 PM PDT 24
Finished	Jul 01 06:48:24 PM PDT 24
Peak memory	223632 kb
Host	smart-9d1a8f11-94b2-4122-822a-3e77f21af901
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893014671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all.3893014671
Directory	/workspace/22.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2658359964
Short name	T774
Test name
Test status
Simulation time	65054630 ps
CPU time	0.98 seconds
Started	Jul 01 06:46:00 PM PDT 24
Finished	Jul 01 06:46:02 PM PDT 24
Peak memory	218136 kb
Host	smart-fe9309b5-b9fe-40a5-a8ae-16035c1ee49e
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658359964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c trl_volatile_unlock_smoke.2658359964
Directory	/workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/23.lc_ctrl_alert_test.1192592127
Short name	T287
Test name
Test status
Simulation time	25016786 ps
CPU time	1.28 seconds
Started	Jul 01 06:46:09 PM PDT 24
Finished	Jul 01 06:46:12 PM PDT 24
Peak memory	209372 kb
Host	smart-e17a7650-7453-479b-964e-2f3d6b2cf104
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192592127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.1192592127
Directory	/workspace/23.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/23.lc_ctrl_errors.3207438900
Short name	T796
Test name
Test status
Simulation time	314055337 ps
CPU time	14.69 seconds
Started	Jul 01 06:46:07 PM PDT 24
Finished	Jul 01 06:46:23 PM PDT 24
Peak memory	218748 kb
Host	smart-cfa24490-c199-4259-823a-b8c547fa42a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3207438900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.3207438900
Directory	/workspace/23.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/23.lc_ctrl_jtag_access.422329223
Short name	T23
Test name
Test status
Simulation time	449462835 ps
CPU time	9.36 seconds
Started	Jul 01 06:46:16 PM PDT 24
Finished	Jul 01 06:46:31 PM PDT 24
Peak memory	217740 kb
Host	smart-c7edd51e-d7a0-438d-ab39-8af8813d2c87
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422329223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.422329223
Directory	/workspace/23.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/23.lc_ctrl_prog_failure.506678496
Short name	T855
Test name
Test status
Simulation time	186255242 ps
CPU time	2.54 seconds
Started	Jul 01 06:46:09 PM PDT 24
Finished	Jul 01 06:46:14 PM PDT 24
Peak memory	222884 kb
Host	smart-6e028ce2-69fe-47f1-8e17-ca5630a47bbe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=506678496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.506678496
Directory	/workspace/23.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/23.lc_ctrl_sec_mubi.260027512
Short name	T294
Test name
Test status
Simulation time	975758397 ps
CPU time	11.21 seconds
Started	Jul 01 06:46:14 PM PDT 24
Finished	Jul 01 06:46:27 PM PDT 24
Peak memory	218760 kb
Host	smart-4a2e6ee7-efcd-4232-9a49-3407d89c1840
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260027512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.260027512
Directory	/workspace/23.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/23.lc_ctrl_sec_token_digest.1604296823
Short name	T851
Test name
Test status
Simulation time	260150344 ps
CPU time	8.09 seconds
Started	Jul 01 06:46:08 PM PDT 24
Finished	Jul 01 06:46:18 PM PDT 24
Peak memory	218620 kb
Host	smart-45af56f2-141f-498b-a240-a16e46439312
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604296823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d igest.1604296823
Directory	/workspace/23.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/23.lc_ctrl_sec_token_mux.2170529869
Short name	T355
Test name
Test status
Simulation time	394930750 ps
CPU time	13.8 seconds
Started	Jul 01 06:46:10 PM PDT 24
Finished	Jul 01 06:46:26 PM PDT 24
Peak memory	218644 kb
Host	smart-89cb66f5-44c7-40c1-808a-210ad12da1c4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170529869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux. 2170529869
Directory	/workspace/23.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/23.lc_ctrl_security_escalation.4133756882
Short name	T836
Test name
Test status
Simulation time	833658370 ps
CPU time	10.38 seconds
Started	Jul 01 06:46:09 PM PDT 24
Finished	Jul 01 06:46:22 PM PDT 24
Peak memory	226448 kb
Host	smart-f6c07611-0998-4fde-8a93-80baaef77ab8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4133756882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.4133756882
Directory	/workspace/23.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/23.lc_ctrl_smoke.3693870565
Short name	T79
Test name
Test status
Simulation time	43476424 ps
CPU time	2.42 seconds
Started	Jul 01 06:46:07 PM PDT 24
Finished	Jul 01 06:46:11 PM PDT 24
Peak memory	218076 kb
Host	smart-347dd0d6-0c2a-4a60-b45d-425f67630339
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3693870565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.3693870565
Directory	/workspace/23.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/23.lc_ctrl_state_post_trans.4079516744
Short name	T411
Test name
Test status
Simulation time	220071107 ps
CPU time	6.03 seconds
Started	Jul 01 06:46:07 PM PDT 24
Finished	Jul 01 06:46:14 PM PDT 24
Peak memory	247248 kb
Host	smart-5198fd6d-bbe6-4680-97df-f634e01b665f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4079516744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.4079516744
Directory	/workspace/23.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/23.lc_ctrl_stress_all.2168654675
Short name	T95
Test name
Test status
Simulation time	3275534895 ps
CPU time	15.51 seconds
Started	Jul 01 06:46:12 PM PDT 24
Finished	Jul 01 06:46:29 PM PDT 24
Peak memory	219960 kb
Host	smart-2193ebc3-ccff-4c98-9235-315f773115d6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168654675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all.2168654675
Directory	/workspace/23.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3055582183
Short name	T525
Test name
Test status
Simulation time	43001284 ps
CPU time	1.08 seconds
Started	Jul 01 06:46:00 PM PDT 24
Finished	Jul 01 06:46:04 PM PDT 24
Peak memory	212496 kb
Host	smart-815d19a3-a0a6-4b64-aef6-66153bf932ff
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055582183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c trl_volatile_unlock_smoke.3055582183
Directory	/workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/24.lc_ctrl_alert_test.1173131090
Short name	T708
Test name
Test status
Simulation time	16106959 ps
CPU time	0.93 seconds
Started	Jul 01 06:46:07 PM PDT 24
Finished	Jul 01 06:46:09 PM PDT 24
Peak memory	209476 kb
Host	smart-f288cb72-5ad6-478b-8177-0f224506b097
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173131090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.1173131090
Directory	/workspace/24.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/24.lc_ctrl_errors.437466936
Short name	T648
Test name
Test status
Simulation time	1502687683 ps
CPU time	11.69 seconds
Started	Jul 01 06:46:06 PM PDT 24
Finished	Jul 01 06:46:18 PM PDT 24
Peak memory	218760 kb
Host	smart-10171ae6-9168-4c0b-aebc-53184f3895f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=437466936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.437466936
Directory	/workspace/24.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/24.lc_ctrl_jtag_access.3288716270
Short name	T7
Test name
Test status
Simulation time	2382200780 ps
CPU time	7.46 seconds
Started	Jul 01 06:46:08 PM PDT 24
Finished	Jul 01 06:46:16 PM PDT 24
Peak memory	218196 kb
Host	smart-b584caf1-6256-4351-b050-c77c58287163
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288716270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.3288716270
Directory	/workspace/24.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/24.lc_ctrl_prog_failure.2565318412
Short name	T297
Test name
Test status
Simulation time	92275905 ps
CPU time	4.25 seconds
Started	Jul 01 06:46:12 PM PDT 24
Finished	Jul 01 06:46:18 PM PDT 24
Peak memory	218748 kb
Host	smart-f4ec8fa2-6e8c-40f7-acb4-ca07353c7b84
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2565318412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.2565318412
Directory	/workspace/24.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/24.lc_ctrl_sec_mubi.4058892209
Short name	T248
Test name
Test status
Simulation time	1274793474 ps
CPU time	9.87 seconds
Started	Jul 01 06:46:14 PM PDT 24
Finished	Jul 01 06:46:26 PM PDT 24
Peak memory	226604 kb
Host	smart-aed2d71b-9cc4-448c-b943-b05696b1eef9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058892209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.4058892209
Directory	/workspace/24.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/24.lc_ctrl_sec_token_digest.793609904
Short name	T225
Test name
Test status
Simulation time	779782075 ps
CPU time	8.86 seconds
Started	Jul 01 06:46:16 PM PDT 24
Finished	Jul 01 06:46:29 PM PDT 24
Peak memory	218668 kb
Host	smart-64374520-eb32-4f74-ac71-2c1ce5fdd439
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793609904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_di gest.793609904
Directory	/workspace/24.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/24.lc_ctrl_sec_token_mux.653117255
Short name	T527
Test name
Test status
Simulation time	807358186 ps
CPU time	7.04 seconds
Started	Jul 01 06:46:09 PM PDT 24
Finished	Jul 01 06:46:18 PM PDT 24
Peak memory	226368 kb
Host	smart-fafa08b2-fa02-4741-bb5c-75b18bd0cd07
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653117255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.653117255
Directory	/workspace/24.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/24.lc_ctrl_security_escalation.1513502056
Short name	T807
Test name
Test status
Simulation time	1435623785 ps
CPU time	8.6 seconds
Started	Jul 01 06:46:14 PM PDT 24
Finished	Jul 01 06:46:24 PM PDT 24
Peak memory	225236 kb
Host	smart-81ca16c0-7766-4307-8cab-746ca864f1f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1513502056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.1513502056
Directory	/workspace/24.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/24.lc_ctrl_smoke.966207968
Short name	T66
Test name
Test status
Simulation time	69016446 ps
CPU time	2.51 seconds
Started	Jul 01 06:46:13 PM PDT 24
Finished	Jul 01 06:46:18 PM PDT 24
Peak memory	215140 kb
Host	smart-a9c138d3-dd9b-428a-8e55-99c8bcf8327d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=966207968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.966207968
Directory	/workspace/24.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/24.lc_ctrl_state_failure.799751915
Short name	T224
Test name
Test status
Simulation time	437040348 ps
CPU time	21.33 seconds
Started	Jul 01 06:46:12 PM PDT 24
Finished	Jul 01 06:46:35 PM PDT 24
Peak memory	251324 kb
Host	smart-ee4b39f3-54dd-4b9d-8aa1-e9ab90a3908f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=799751915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.799751915
Directory	/workspace/24.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/24.lc_ctrl_state_post_trans.2077472642
Short name	T557
Test name
Test status
Simulation time	242507150 ps
CPU time	6.96 seconds
Started	Jul 01 06:46:09 PM PDT 24
Finished	Jul 01 06:46:17 PM PDT 24
Peak memory	247096 kb
Host	smart-43cf9291-3ae1-4165-9b18-bc8b0eb12439
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2077472642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.2077472642
Directory	/workspace/24.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/24.lc_ctrl_stress_all.70513984
Short name	T284
Test name
Test status
Simulation time	141157047162 ps
CPU time	193.25 seconds
Started	Jul 01 06:46:07 PM PDT 24
Finished	Jul 01 06:49:22 PM PDT 24
Peak memory	333352 kb
Host	smart-44f8508c-4782-4b85-90f5-dfbf67dc1dfc
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70513984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 4.lc_ctrl_stress_all.70513984
Directory	/workspace/24.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.872689196
Short name	T336
Test name
Test status
Simulation time	12937110 ps
CPU time	1.08 seconds
Started	Jul 01 06:46:09 PM PDT 24
Finished	Jul 01 06:46:12 PM PDT 24
Peak memory	218084 kb
Host	smart-242a9934-cfb7-4cef-a431-88e890e53dd3
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872689196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ct rl_volatile_unlock_smoke.872689196
Directory	/workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/25.lc_ctrl_alert_test.1858272771
Short name	T317
Test name
Test status
Simulation time	58702021 ps
CPU time	0.91 seconds
Started	Jul 01 06:46:15 PM PDT 24
Finished	Jul 01 06:46:20 PM PDT 24
Peak memory	209380 kb
Host	smart-475fbc8c-f79f-40d3-adba-2a87353bf60e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858272771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.1858272771
Directory	/workspace/25.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/25.lc_ctrl_errors.1129278544
Short name	T844
Test name
Test status
Simulation time	952685675 ps
CPU time	9.79 seconds
Started	Jul 01 06:46:16 PM PDT 24
Finished	Jul 01 06:46:31 PM PDT 24
Peak memory	218636 kb
Host	smart-d49f05fe-9032-4f2e-812f-6e2485c99318
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1129278544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.1129278544
Directory	/workspace/25.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/25.lc_ctrl_jtag_access.4157754456
Short name	T237
Test name
Test status
Simulation time	636228498 ps
CPU time	1.46 seconds
Started	Jul 01 06:46:17 PM PDT 24
Finished	Jul 01 06:46:23 PM PDT 24
Peak memory	217140 kb
Host	smart-b1046930-cfbb-448d-9fe0-e986e19e79a2
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157754456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.4157754456
Directory	/workspace/25.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/25.lc_ctrl_prog_failure.2406620699
Short name	T786
Test name
Test status
Simulation time	52417809 ps
CPU time	2.17 seconds
Started	Jul 01 06:46:16 PM PDT 24
Finished	Jul 01 06:46:23 PM PDT 24
Peak memory	218632 kb
Host	smart-69bd9827-7270-4007-868a-523e79648812
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2406620699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.2406620699
Directory	/workspace/25.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/25.lc_ctrl_sec_mubi.3290830728
Short name	T869
Test name
Test status
Simulation time	457190277 ps
CPU time	14.52 seconds
Started	Jul 01 06:46:17 PM PDT 24
Finished	Jul 01 06:46:36 PM PDT 24
Peak memory	226448 kb
Host	smart-bacd2752-5b1e-4457-8ccd-acc6a0fe8c1a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290830728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.3290830728
Directory	/workspace/25.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/25.lc_ctrl_sec_token_digest.236754961
Short name	T481
Test name
Test status
Simulation time	674395901 ps
CPU time	15.28 seconds
Started	Jul 01 06:46:18 PM PDT 24
Finished	Jul 01 06:46:38 PM PDT 24
Peak memory	218668 kb
Host	smart-b2dcc790-df2f-4723-9532-c45b35375480
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236754961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_di gest.236754961
Directory	/workspace/25.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/25.lc_ctrl_sec_token_mux.1390226756
Short name	T720
Test name
Test status
Simulation time	246899317 ps
CPU time	10.9 seconds
Started	Jul 01 06:46:16 PM PDT 24
Finished	Jul 01 06:46:32 PM PDT 24
Peak memory	218644 kb
Host	smart-7d516af4-dd4c-42a9-bc5a-8b394788f062
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390226756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux. 1390226756
Directory	/workspace/25.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/25.lc_ctrl_security_escalation.2835371290
Short name	T513
Test name
Test status
Simulation time	1146891041 ps
CPU time	8.62 seconds
Started	Jul 01 06:46:18 PM PDT 24
Finished	Jul 01 06:46:31 PM PDT 24
Peak memory	226436 kb
Host	smart-d0724fca-671d-49ee-8f8d-95c2d2e9968b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2835371290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.2835371290
Directory	/workspace/25.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/25.lc_ctrl_smoke.648249191
Short name	T277
Test name
Test status
Simulation time	107259103 ps
CPU time	2.23 seconds
Started	Jul 01 06:46:10 PM PDT 24
Finished	Jul 01 06:46:14 PM PDT 24
Peak memory	214636 kb
Host	smart-7774851c-3612-4be3-87f9-4936a947c076
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=648249191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.648249191
Directory	/workspace/25.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/25.lc_ctrl_state_failure.3329850975
Short name	T486
Test name
Test status
Simulation time	639945353 ps
CPU time	33.31 seconds
Started	Jul 01 06:46:14 PM PDT 24
Finished	Jul 01 06:46:50 PM PDT 24
Peak memory	251536 kb
Host	smart-f70f0081-f844-4f0d-ac38-ec9f931cbc8d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3329850975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.3329850975
Directory	/workspace/25.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/25.lc_ctrl_state_post_trans.3821248703
Short name	T671
Test name
Test status
Simulation time	304754619 ps
CPU time	7.33 seconds
Started	Jul 01 06:46:09 PM PDT 24
Finished	Jul 01 06:46:18 PM PDT 24
Peak memory	247176 kb
Host	smart-13f99c7a-5a4f-460e-aaba-1df21622f360
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3821248703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.3821248703
Directory	/workspace/25.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/25.lc_ctrl_stress_all.2832986732
Short name	T753
Test name
Test status
Simulation time	23789217909 ps
CPU time	228.02 seconds
Started	Jul 01 06:46:18 PM PDT 24
Finished	Jul 01 06:50:11 PM PDT 24
Peak memory	251440 kb
Host	smart-128ada2c-efd7-412f-af11-e84fe38bd647
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832986732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_stress_all.2832986732
Directory	/workspace/25.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.3479063033
Short name	T706
Test name
Test status
Simulation time	24545511 ps
CPU time	0.79 seconds
Started	Jul 01 06:46:05 PM PDT 24
Finished	Jul 01 06:46:07 PM PDT 24
Peak memory	209424 kb
Host	smart-5ebcc2f5-0018-4248-8d0f-bed73444571e
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479063033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c trl_volatile_unlock_smoke.3479063033
Directory	/workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/26.lc_ctrl_alert_test.414602499
Short name	T713
Test name
Test status
Simulation time	44019618 ps
CPU time	0.84 seconds
Started	Jul 01 06:46:16 PM PDT 24
Finished	Jul 01 06:46:22 PM PDT 24
Peak memory	209208 kb
Host	smart-d558d525-b9a2-43ab-9ca4-c688981aadd6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414602499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.414602499
Directory	/workspace/26.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/26.lc_ctrl_errors.4030676349
Short name	T296
Test name
Test status
Simulation time	1334359771 ps
CPU time	19.65 seconds
Started	Jul 01 06:46:14 PM PDT 24
Finished	Jul 01 06:46:36 PM PDT 24
Peak memory	218644 kb
Host	smart-3e938d4c-526d-4ff3-84e7-2876c6c78c34
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4030676349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.4030676349
Directory	/workspace/26.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/26.lc_ctrl_jtag_access.666093351
Short name	T877
Test name
Test status
Simulation time	430148113 ps
CPU time	5.37 seconds
Started	Jul 01 06:46:20 PM PDT 24
Finished	Jul 01 06:46:30 PM PDT 24
Peak memory	217832 kb
Host	smart-721ac892-bd16-4e51-bbcc-0873e0c0ba21
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666093351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.666093351
Directory	/workspace/26.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/26.lc_ctrl_prog_failure.3151026228
Short name	T422
Test name
Test status
Simulation time	94619499 ps
CPU time	2.62 seconds
Started	Jul 01 06:46:13 PM PDT 24
Finished	Jul 01 06:46:18 PM PDT 24
Peak memory	218712 kb
Host	smart-93edaf61-d457-4956-9e6a-ce31445e9bec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3151026228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.3151026228
Directory	/workspace/26.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/26.lc_ctrl_sec_mubi.2291510058
Short name	T40
Test name
Test status
Simulation time	683312719 ps
CPU time	25.76 seconds
Started	Jul 01 06:46:17 PM PDT 24
Finished	Jul 01 06:46:48 PM PDT 24
Peak memory	226528 kb
Host	smart-1c5d7f76-d5e5-4cc2-bebf-14560e170be7
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291510058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.2291510058
Directory	/workspace/26.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/26.lc_ctrl_sec_token_digest.4289365653
Short name	T435
Test name
Test status
Simulation time	880786937 ps
CPU time	11.66 seconds
Started	Jul 01 06:46:17 PM PDT 24
Finished	Jul 01 06:46:33 PM PDT 24
Peak memory	218396 kb
Host	smart-50b54dab-597d-497a-b29d-797f4584b41d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289365653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d igest.4289365653
Directory	/workspace/26.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/26.lc_ctrl_sec_token_mux.2289704083
Short name	T491
Test name
Test status
Simulation time	901311774 ps
CPU time	8.7 seconds
Started	Jul 01 06:46:15 PM PDT 24
Finished	Jul 01 06:46:29 PM PDT 24
Peak memory	218588 kb
Host	smart-caa5d1ba-905b-4294-a136-d8bcc77e698e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289704083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux. 2289704083
Directory	/workspace/26.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/26.lc_ctrl_security_escalation.141496677
Short name	T215
Test name
Test status
Simulation time	1006251465 ps
CPU time	7.39 seconds
Started	Jul 01 06:46:17 PM PDT 24
Finished	Jul 01 06:46:30 PM PDT 24
Peak memory	226396 kb
Host	smart-3381e02e-56f7-48db-981e-0b8f4107218f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=141496677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.141496677
Directory	/workspace/26.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/26.lc_ctrl_smoke.10920396
Short name	T674
Test name
Test status
Simulation time	736106218 ps
CPU time	4.82 seconds
Started	Jul 01 06:46:14 PM PDT 24
Finished	Jul 01 06:46:23 PM PDT 24
Peak memory	218092 kb
Host	smart-862954c5-a82d-47cb-b3f6-3d1476a6378e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=10920396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.10920396
Directory	/workspace/26.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/26.lc_ctrl_state_failure.4068508779
Short name	T803
Test name
Test status
Simulation time	3121178070 ps
CPU time	34.2 seconds
Started	Jul 01 06:46:19 PM PDT 24
Finished	Jul 01 06:46:58 PM PDT 24
Peak memory	251504 kb
Host	smart-cea20ab2-2d4d-490a-bddd-ea8ceba72fa6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4068508779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.4068508779
Directory	/workspace/26.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/26.lc_ctrl_state_post_trans.2137007082
Short name	T790
Test name
Test status
Simulation time	195939014 ps
CPU time	6.26 seconds
Started	Jul 01 06:46:19 PM PDT 24
Finished	Jul 01 06:46:30 PM PDT 24
Peak memory	250888 kb
Host	smart-c5ec17aa-27e9-4115-aab7-0c9455247b19
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2137007082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.2137007082
Directory	/workspace/26.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/26.lc_ctrl_stress_all.64467222
Short name	T87
Test name
Test status
Simulation time	23883967062 ps
CPU time	203.75 seconds
Started	Jul 01 06:46:18 PM PDT 24
Finished	Jul 01 06:49:46 PM PDT 24
Peak memory	283284 kb
Host	smart-eb8e7fc0-1f18-42dc-8b10-150250b4d1d3
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64467222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 6.lc_ctrl_stress_all.64467222
Directory	/workspace/26.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.1301961280
Short name	T127
Test name
Test status
Simulation time	22581136773 ps
CPU time	831.2 seconds
Started	Jul 01 06:46:18 PM PDT 24
Finished	Jul 01 07:00:14 PM PDT 24
Peak memory	275956 kb
Host	smart-a53283f1-ed69-4ec1-a270-67833725e34a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1301961280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all_with_rand_reset.1301961280
Directory	/workspace/26.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.348676685
Short name	T374
Test name
Test status
Simulation time	15396024 ps
CPU time	0.93 seconds
Started	Jul 01 06:46:14 PM PDT 24
Finished	Jul 01 06:46:18 PM PDT 24
Peak memory	212280 kb
Host	smart-98cac8f3-5719-48b1-9c75-3f2c25afd417
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348676685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ct rl_volatile_unlock_smoke.348676685
Directory	/workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/27.lc_ctrl_alert_test.781383572
Short name	T449
Test name
Test status
Simulation time	18985363 ps
CPU time	0.91 seconds
Started	Jul 01 06:46:16 PM PDT 24
Finished	Jul 01 06:46:22 PM PDT 24
Peak memory	209516 kb
Host	smart-96ce6cee-9224-4a63-9444-87e2f5c773a0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781383572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.781383572
Directory	/workspace/27.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/27.lc_ctrl_errors.2098589185
Short name	T568
Test name
Test status
Simulation time	270897878 ps
CPU time	10.64 seconds
Started	Jul 01 06:46:15 PM PDT 24
Finished	Jul 01 06:46:30 PM PDT 24
Peak memory	218712 kb
Host	smart-83acd4c6-e2a5-4a20-873f-bc49a09a3c89
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2098589185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.2098589185
Directory	/workspace/27.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/27.lc_ctrl_jtag_access.894310475
Short name	T26
Test name
Test status
Simulation time	1291705536 ps
CPU time	16.66 seconds
Started	Jul 01 06:46:17 PM PDT 24
Finished	Jul 01 06:46:39 PM PDT 24
Peak memory	217684 kb
Host	smart-fbea8125-171b-4276-8e51-7202dd4b39ab
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894310475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.894310475
Directory	/workspace/27.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/27.lc_ctrl_prog_failure.559814699
Short name	T245
Test name
Test status
Simulation time	127903342 ps
CPU time	1.85 seconds
Started	Jul 01 06:46:16 PM PDT 24
Finished	Jul 01 06:46:23 PM PDT 24
Peak memory	222580 kb
Host	smart-ff75985e-41eb-40e5-ae96-02f7f1a40068
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=559814699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.559814699
Directory	/workspace/27.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/27.lc_ctrl_sec_mubi.3961188016
Short name	T360
Test name
Test status
Simulation time	548763504 ps
CPU time	14.62 seconds
Started	Jul 01 06:46:16 PM PDT 24
Finished	Jul 01 06:46:35 PM PDT 24
Peak memory	219304 kb
Host	smart-d22a059b-06a5-4e66-9944-49c3909c7101
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961188016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.3961188016
Directory	/workspace/27.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/27.lc_ctrl_sec_token_digest.3848448824
Short name	T498
Test name
Test status
Simulation time	1153505271 ps
CPU time	8.43 seconds
Started	Jul 01 06:46:15 PM PDT 24
Finished	Jul 01 06:46:28 PM PDT 24
Peak memory	226368 kb
Host	smart-89e2ad23-c6dd-4163-8d09-dacc6000f821
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848448824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d igest.3848448824
Directory	/workspace/27.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/27.lc_ctrl_sec_token_mux.3565128154
Short name	T580
Test name
Test status
Simulation time	812649676 ps
CPU time	8.81 seconds
Started	Jul 01 06:46:19 PM PDT 24
Finished	Jul 01 06:46:32 PM PDT 24
Peak memory	218696 kb
Host	smart-c3e63504-b58f-42f2-9d8e-f6fdfc1131a6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565128154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux. 3565128154
Directory	/workspace/27.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/27.lc_ctrl_security_escalation.1831968339
Short name	T57
Test name
Test status
Simulation time	584692498 ps
CPU time	11.38 seconds
Started	Jul 01 06:46:14 PM PDT 24
Finished	Jul 01 06:46:28 PM PDT 24
Peak memory	225572 kb
Host	smart-e7afa974-e35c-44c5-8b0c-a51f013a48db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1831968339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.1831968339
Directory	/workspace/27.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/27.lc_ctrl_smoke.547927406
Short name	T666
Test name
Test status
Simulation time	36828945 ps
CPU time	2.36 seconds
Started	Jul 01 06:46:14 PM PDT 24
Finished	Jul 01 06:46:18 PM PDT 24
Peak memory	218176 kb
Host	smart-7c2f909c-0efb-45fd-8ed2-815cd1f5b6ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=547927406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.547927406
Directory	/workspace/27.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/27.lc_ctrl_state_failure.2772085845
Short name	T472
Test name
Test status
Simulation time	308082337 ps
CPU time	27.12 seconds
Started	Jul 01 06:46:16 PM PDT 24
Finished	Jul 01 06:46:48 PM PDT 24
Peak memory	251344 kb
Host	smart-e5dfe59a-1bba-4a77-83a8-74cad5fa0ac6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2772085845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.2772085845
Directory	/workspace/27.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/27.lc_ctrl_state_post_trans.4277810419
Short name	T721
Test name
Test status
Simulation time	439231699 ps
CPU time	6.85 seconds
Started	Jul 01 06:46:15 PM PDT 24
Finished	Jul 01 06:46:26 PM PDT 24
Peak memory	247248 kb
Host	smart-6283f3c7-cf2f-4e66-8e07-5514766e2f9d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4277810419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.4277810419
Directory	/workspace/27.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/27.lc_ctrl_stress_all.2692502800
Short name	T240
Test name
Test status
Simulation time	4534681853 ps
CPU time	51.44 seconds
Started	Jul 01 06:46:17 PM PDT 24
Finished	Jul 01 06:47:14 PM PDT 24
Peak memory	246576 kb
Host	smart-c7052791-4ffe-4378-8dab-5e62821d7046
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692502800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all.2692502800
Directory	/workspace/27.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.63161330
Short name	T209
Test name
Test status
Simulation time	257061206010 ps
CPU time	537.5 seconds
Started	Jul 01 06:46:15 PM PDT 24
Finished	Jul 01 06:55:17 PM PDT 24
Peak memory	513720 kb
Host	smart-fc135f2b-575d-4233-a507-c87cd070c50b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=63161330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all_with_rand_reset.63161330
Directory	/workspace/27.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.960171451
Short name	T35
Test name
Test status
Simulation time	20967847 ps
CPU time	0.92 seconds
Started	Jul 01 06:46:16 PM PDT 24
Finished	Jul 01 06:46:22 PM PDT 24
Peak memory	209300 kb
Host	smart-3ce1e480-4387-4209-aac4-df991f58153e
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960171451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ct rl_volatile_unlock_smoke.960171451
Directory	/workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/28.lc_ctrl_alert_test.2243445231
Short name	T321
Test name
Test status
Simulation time	85581110 ps
CPU time	1.17 seconds
Started	Jul 01 06:46:24 PM PDT 24
Finished	Jul 01 06:46:28 PM PDT 24
Peak memory	209432 kb
Host	smart-a10b6896-1076-428b-b405-b95ed35ebfde
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243445231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.2243445231
Directory	/workspace/28.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/28.lc_ctrl_errors.967372487
Short name	T649
Test name
Test status
Simulation time	253215908 ps
CPU time	12.7 seconds
Started	Jul 01 06:46:23 PM PDT 24
Finished	Jul 01 06:46:38 PM PDT 24
Peak memory	218716 kb
Host	smart-7365393f-f3b0-4f15-ba33-5bf49069f2a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=967372487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.967372487
Directory	/workspace/28.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/28.lc_ctrl_jtag_access.233085952
Short name	T664
Test name
Test status
Simulation time	156585409 ps
CPU time	1.09 seconds
Started	Jul 01 06:46:23 PM PDT 24
Finished	Jul 01 06:46:27 PM PDT 24
Peak memory	217424 kb
Host	smart-42e9dec5-0157-4c7a-b37c-40954db33561
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233085952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.233085952
Directory	/workspace/28.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/28.lc_ctrl_prog_failure.1999361057
Short name	T632
Test name
Test status
Simulation time	32200617 ps
CPU time	2.36 seconds
Started	Jul 01 06:46:25 PM PDT 24
Finished	Jul 01 06:46:31 PM PDT 24
Peak memory	222608 kb
Host	smart-034237ab-dbfc-4605-bc20-743f67f661ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1999361057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.1999361057
Directory	/workspace/28.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/28.lc_ctrl_sec_mubi.3764883536
Short name	T45
Test name
Test status
Simulation time	2533380243 ps
CPU time	11.96 seconds
Started	Jul 01 06:46:23 PM PDT 24
Finished	Jul 01 06:46:38 PM PDT 24
Peak memory	226536 kb
Host	smart-f95e2f8d-3b12-4ec2-9969-9769d972f92d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764883536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.3764883536
Directory	/workspace/28.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/28.lc_ctrl_sec_token_digest.1169733094
Short name	T594
Test name
Test status
Simulation time	1013898778 ps
CPU time	9.81 seconds
Started	Jul 01 06:46:26 PM PDT 24
Finished	Jul 01 06:46:39 PM PDT 24
Peak memory	218728 kb
Host	smart-b1a941a9-8d43-470e-a564-e85aae3b04dd
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169733094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d igest.1169733094
Directory	/workspace/28.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/28.lc_ctrl_sec_token_mux.570171840
Short name	T417
Test name
Test status
Simulation time	295784398 ps
CPU time	5.11 seconds
Started	Jul 01 06:46:22 PM PDT 24
Finished	Jul 01 06:46:30 PM PDT 24
Peak memory	225352 kb
Host	smart-538d5a16-9577-4e57-b991-a2254b94fa93
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570171840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.570171840
Directory	/workspace/28.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/28.lc_ctrl_security_escalation.2831006517
Short name	T655
Test name
Test status
Simulation time	762943990 ps
CPU time	11.01 seconds
Started	Jul 01 06:46:22 PM PDT 24
Finished	Jul 01 06:46:36 PM PDT 24
Peak memory	226548 kb
Host	smart-6ffa5e03-7f43-47ad-a07a-c54a0355b0ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2831006517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.2831006517
Directory	/workspace/28.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/28.lc_ctrl_smoke.1129580233
Short name	T552
Test name
Test status
Simulation time	121382805 ps
CPU time	3.5 seconds
Started	Jul 01 06:46:19 PM PDT 24
Finished	Jul 01 06:46:26 PM PDT 24
Peak memory	226316 kb
Host	smart-e1a0bb6e-a039-4ef7-9cf9-72e18c1198bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1129580233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.1129580233
Directory	/workspace/28.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/28.lc_ctrl_state_failure.278917953
Short name	T327
Test name
Test status
Simulation time	3833726539 ps
CPU time	28.14 seconds
Started	Jul 01 06:46:23 PM PDT 24
Finished	Jul 01 06:46:53 PM PDT 24
Peak memory	251468 kb
Host	smart-0262d51e-e569-45ba-a27a-2423a3aca6ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=278917953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.278917953
Directory	/workspace/28.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/28.lc_ctrl_state_post_trans.3685748372
Short name	T635
Test name
Test status
Simulation time	89526477 ps
CPU time	10.17 seconds
Started	Jul 01 06:46:26 PM PDT 24
Finished	Jul 01 06:46:40 PM PDT 24
Peak memory	251392 kb
Host	smart-f2374c95-291e-42cd-b840-67bd482e8375
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3685748372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.3685748372
Directory	/workspace/28.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/28.lc_ctrl_stress_all.2315642183
Short name	T553
Test name
Test status
Simulation time	28167481077 ps
CPU time	285.13 seconds
Started	Jul 01 06:46:23 PM PDT 24
Finished	Jul 01 06:51:11 PM PDT 24
Peak memory	284064 kb
Host	smart-daebc173-f652-4441-9993-7a55a01fd017
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315642183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all.2315642183
Directory	/workspace/28.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.2808704600
Short name	T815
Test name
Test status
Simulation time	18752006 ps
CPU time	0.8 seconds
Started	Jul 01 06:46:16 PM PDT 24
Finished	Jul 01 06:46:22 PM PDT 24
Peak memory	209320 kb
Host	smart-5252054f-2bba-49ca-aaba-8e0818ea7fa2
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808704600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c trl_volatile_unlock_smoke.2808704600
Directory	/workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/29.lc_ctrl_alert_test.1212330315
Short name	T536
Test name
Test status
Simulation time	313351373 ps
CPU time	0.96 seconds
Started	Jul 01 06:46:22 PM PDT 24
Finished	Jul 01 06:46:26 PM PDT 24
Peak memory	209452 kb
Host	smart-230f559c-d729-4b9f-8782-4573fdfa0548
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212330315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.1212330315
Directory	/workspace/29.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/29.lc_ctrl_errors.2981388055
Short name	T339
Test name
Test status
Simulation time	354977984 ps
CPU time	15.93 seconds
Started	Jul 01 06:46:23 PM PDT 24
Finished	Jul 01 06:46:42 PM PDT 24
Peak memory	218576 kb
Host	smart-c6b79ded-bced-4846-b8f0-f9f9091690ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2981388055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.2981388055
Directory	/workspace/29.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/29.lc_ctrl_jtag_access.574949761
Short name	T805
Test name
Test status
Simulation time	3720069640 ps
CPU time	4.46 seconds
Started	Jul 01 06:46:25 PM PDT 24
Finished	Jul 01 06:46:32 PM PDT 24
Peak memory	218148 kb
Host	smart-389712be-600e-4853-9b3f-1ddc2a5b6e24
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574949761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.574949761
Directory	/workspace/29.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/29.lc_ctrl_prog_failure.2738564978
Short name	T3
Test name
Test status
Simulation time	840913814 ps
CPU time	4 seconds
Started	Jul 01 06:46:23 PM PDT 24
Finished	Jul 01 06:46:30 PM PDT 24
Peak memory	222760 kb
Host	smart-b93752a0-9aa5-47f3-b52c-9f14f7c37ed2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2738564978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.2738564978
Directory	/workspace/29.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/29.lc_ctrl_sec_mubi.3285567557
Short name	T736
Test name
Test status
Simulation time	883917953 ps
CPU time	14.52 seconds
Started	Jul 01 06:46:27 PM PDT 24
Finished	Jul 01 06:46:46 PM PDT 24
Peak memory	219296 kb
Host	smart-b43205c9-a711-49ab-a5ba-f292f976ae6b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285567557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.3285567557
Directory	/workspace/29.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/29.lc_ctrl_sec_token_digest.2422011415
Short name	T42
Test name
Test status
Simulation time	1084323809 ps
CPU time	13.68 seconds
Started	Jul 01 06:46:26 PM PDT 24
Finished	Jul 01 06:46:43 PM PDT 24
Peak memory	218796 kb
Host	smart-4d771c45-4c58-4802-8cb9-b28b050aedb6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422011415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d igest.2422011415
Directory	/workspace/29.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/29.lc_ctrl_sec_token_mux.3311163544
Short name	T502
Test name
Test status
Simulation time	324063700 ps
CPU time	11.97 seconds
Started	Jul 01 06:46:24 PM PDT 24
Finished	Jul 01 06:46:39 PM PDT 24
Peak memory	226360 kb
Host	smart-a31ffa49-96cf-4261-9f7e-cc9130a944c5
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311163544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux. 3311163544
Directory	/workspace/29.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/29.lc_ctrl_security_escalation.1430035552
Short name	T625
Test name
Test status
Simulation time	526353019 ps
CPU time	10.61 seconds
Started	Jul 01 06:46:22 PM PDT 24
Finished	Jul 01 06:46:36 PM PDT 24
Peak memory	218768 kb
Host	smart-ebaf5ea2-b98a-41f5-8d4f-a2b6345b57be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1430035552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.1430035552
Directory	/workspace/29.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/29.lc_ctrl_smoke.1617881052
Short name	T752
Test name
Test status
Simulation time	128580656 ps
CPU time	1.85 seconds
Started	Jul 01 06:46:26 PM PDT 24
Finished	Jul 01 06:46:32 PM PDT 24
Peak memory	214648 kb
Host	smart-56156242-20c5-442f-bc21-3c5ff94cdcd1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1617881052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.1617881052
Directory	/workspace/29.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/29.lc_ctrl_state_failure.2887064561
Short name	T392
Test name
Test status
Simulation time	698919325 ps
CPU time	20.44 seconds
Started	Jul 01 06:46:24 PM PDT 24
Finished	Jul 01 06:46:47 PM PDT 24
Peak memory	251312 kb
Host	smart-e9932bcb-dea2-4e50-9f99-6e28bc397434
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2887064561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.2887064561
Directory	/workspace/29.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/29.lc_ctrl_state_post_trans.3281535849
Short name	T695
Test name
Test status
Simulation time	53998846 ps
CPU time	7.4 seconds
Started	Jul 01 06:46:27 PM PDT 24
Finished	Jul 01 06:46:38 PM PDT 24
Peak memory	251392 kb
Host	smart-5fcaf1a6-b5af-44cb-807a-c4e08920e396
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3281535849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.3281535849
Directory	/workspace/29.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/29.lc_ctrl_stress_all.4145054670
Short name	T627
Test name
Test status
Simulation time	4085650254 ps
CPU time	172.38 seconds
Started	Jul 01 06:46:22 PM PDT 24
Finished	Jul 01 06:49:17 PM PDT 24
Peak memory	284120 kb
Host	smart-41eddf0d-6ea7-46c8-8713-24ace0f56a75
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145054670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all.4145054670
Directory	/workspace/29.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.3805187877
Short name	T34
Test name
Test status
Simulation time	13965385 ps
CPU time	0.79 seconds
Started	Jul 01 06:46:25 PM PDT 24
Finished	Jul 01 06:46:30 PM PDT 24
Peak memory	209208 kb
Host	smart-9aea9e22-001b-40be-b3cc-cfb6e2e68d15
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805187877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c trl_volatile_unlock_smoke.3805187877
Directory	/workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/3.lc_ctrl_alert_test.3725531836
Short name	T579
Test name
Test status
Simulation time	28950627 ps
CPU time	0.84 seconds
Started	Jul 01 06:44:15 PM PDT 24
Finished	Jul 01 06:44:18 PM PDT 24
Peak memory	209412 kb
Host	smart-c3e68887-fcae-49a0-bc0b-ba87703acca6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725531836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.3725531836
Directory	/workspace/3.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/3.lc_ctrl_errors.3925218063
Short name	T370
Test name
Test status
Simulation time	228059116 ps
CPU time	11.54 seconds
Started	Jul 01 06:43:59 PM PDT 24
Finished	Jul 01 06:44:12 PM PDT 24
Peak memory	218700 kb
Host	smart-c7329ba0-6af9-4044-9923-3159abdf1f55
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3925218063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.3925218063
Directory	/workspace/3.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_access.3901348102
Short name	T702
Test name
Test status
Simulation time	3185261079 ps
CPU time	6.88 seconds
Started	Jul 01 06:44:10 PM PDT 24
Finished	Jul 01 06:44:20 PM PDT 24
Peak memory	218152 kb
Host	smart-d7728052-3874-4526-a5e6-1d619d738b35
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901348102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.3901348102
Directory	/workspace/3.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_errors.1009437815
Short name	T47
Test name
Test status
Simulation time	18852689733 ps
CPU time	124.9 seconds
Started	Jul 01 06:44:00 PM PDT 24
Finished	Jul 01 06:46:06 PM PDT 24
Peak memory	226428 kb
Host	smart-afaadd57-a73c-4967-a003-b33d4571a12f
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009437815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er rors.1009437815
Directory	/workspace/3.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_priority.3942004686
Short name	T103
Test name
Test status
Simulation time	917352093 ps
CPU time	3.14 seconds
Started	Jul 01 06:44:10 PM PDT 24
Finished	Jul 01 06:44:16 PM PDT 24
Peak memory	217820 kb
Host	smart-657033cf-9133-4410-af07-3bdfdac63335
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942004686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.3 942004686
Directory	/workspace/3.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.3816618882
Short name	T432
Test name
Test status
Simulation time	767165562 ps
CPU time	10.97 seconds
Started	Jul 01 06:44:03 PM PDT 24
Finished	Jul 01 06:44:15 PM PDT 24
Peak memory	225616 kb
Host	smart-096f31cc-70a8-4ecf-ab25-dbd55d3c1752
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816618882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag _prog_failure.3816618882
Directory	/workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1134178309
Short name	T76
Test name
Test status
Simulation time	822459785 ps
CPU time	12.99 seconds
Started	Jul 01 06:44:13 PM PDT 24
Finished	Jul 01 06:44:27 PM PDT 24
Peak memory	217948 kb
Host	smart-5a29eb23-b51e-4f26-8cd3-c65787411647
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134178309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_ jtag_regwen_during_op.1134178309
Directory	/workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_smoke.104538079
Short name	T331
Test name
Test status
Simulation time	850396364 ps
CPU time	5.71 seconds
Started	Jul 01 06:44:01 PM PDT 24
Finished	Jul 01 06:44:08 PM PDT 24
Peak memory	218116 kb
Host	smart-e58b5334-bfd7-4ab7-803a-7fbdbbf79989
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104538079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.104538079
Directory	/workspace/3.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_state_failure.4132349432
Short name	T467
Test name
Test status
Simulation time	4240944401 ps
CPU time	48.11 seconds
Started	Jul 01 06:44:02 PM PDT 24
Finished	Jul 01 06:44:51 PM PDT 24
Peak memory	267720 kb
Host	smart-fb2a3bb5-a679-4238-9e63-8f5f89c85c8b
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132349432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta g_state_failure.4132349432
Directory	/workspace/3.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.80089996
Short name	T468
Test name
Test status
Simulation time	1720215773 ps
CPU time	15.83 seconds
Started	Jul 01 06:43:59 PM PDT 24
Finished	Jul 01 06:44:16 PM PDT 24
Peak memory	249276 kb
Host	smart-d59675a7-6610-40dc-86a0-f216aa1af04b
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80089996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s tate_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jt ag_state_post_trans.80089996
Directory	/workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/3.lc_ctrl_prog_failure.3338617604
Short name	T532
Test name
Test status
Simulation time	150352879 ps
CPU time	3.33 seconds
Started	Jul 01 06:44:01 PM PDT 24
Finished	Jul 01 06:44:05 PM PDT 24
Peak memory	223044 kb
Host	smart-c483f355-f041-4f3a-8fb5-cc82215c512c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3338617604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.3338617604
Directory	/workspace/3.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/3.lc_ctrl_regwen_during_op.616111732
Short name	T875
Test name
Test status
Simulation time	790911157 ps
CPU time	14.12 seconds
Started	Jul 01 06:43:59 PM PDT 24
Finished	Jul 01 06:44:14 PM PDT 24
Peak memory	218060 kb
Host	smart-efdb08fa-7a0e-43bd-9b37-f033b2342a9b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=616111732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.616111732
Directory	/workspace/3.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/3.lc_ctrl_sec_cm.1684796468
Short name	T61
Test name
Test status
Simulation time	1023033110 ps
CPU time	26.55 seconds
Started	Jul 01 06:44:09 PM PDT 24
Finished	Jul 01 06:44:38 PM PDT 24
Peak memory	268944 kb
Host	smart-8accdb09-0928-4ba2-9f9a-16932cd5756f
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684796468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.1684796468
Directory	/workspace/3.lc_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/3.lc_ctrl_sec_mubi.3545926129
Short name	T464
Test name
Test status
Simulation time	2909290521 ps
CPU time	18.3 seconds
Started	Jul 01 06:44:15 PM PDT 24
Finished	Jul 01 06:44:35 PM PDT 24
Peak memory	226500 kb
Host	smart-b4ba9c04-3f1d-493f-9033-c1ad65eb16b2
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545926129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.3545926129
Directory	/workspace/3.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/3.lc_ctrl_sec_token_digest.297784429
Short name	T545
Test name
Test status
Simulation time	391231162 ps
CPU time	10.81 seconds
Started	Jul 01 06:44:09 PM PDT 24
Finished	Jul 01 06:44:21 PM PDT 24
Peak memory	218668 kb
Host	smart-2d9ee9f4-13ed-4eec-aec0-6c48aca4b64b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297784429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_dig est.297784429
Directory	/workspace/3.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/3.lc_ctrl_sec_token_mux.3808910897
Short name	T727
Test name
Test status
Simulation time	2240776565 ps
CPU time	7.93 seconds
Started	Jul 01 06:44:10 PM PDT 24
Finished	Jul 01 06:44:21 PM PDT 24
Peak memory	225556 kb
Host	smart-e9e3eed3-260c-4947-9da5-e4921772222a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808910897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.3 808910897
Directory	/workspace/3.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/3.lc_ctrl_security_escalation.642437780
Short name	T732
Test name
Test status
Simulation time	1571604996 ps
CPU time	10.58 seconds
Started	Jul 01 06:43:59 PM PDT 24
Finished	Jul 01 06:44:11 PM PDT 24
Peak memory	226524 kb
Host	smart-c21d5da3-310d-4f42-9ff8-fb6ac172ac3e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=642437780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.642437780
Directory	/workspace/3.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/3.lc_ctrl_smoke.3505204839
Short name	T110
Test name
Test status
Simulation time	103210628 ps
CPU time	3.05 seconds
Started	Jul 01 06:43:58 PM PDT 24
Finished	Jul 01 06:44:03 PM PDT 24
Peak memory	218072 kb
Host	smart-de5de65e-4242-40a1-ae67-cacc6bda8b58
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3505204839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.3505204839
Directory	/workspace/3.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/3.lc_ctrl_state_failure.2544412329
Short name	T32
Test name
Test status
Simulation time	1771997763 ps
CPU time	28.48 seconds
Started	Jul 01 06:44:01 PM PDT 24
Finished	Jul 01 06:44:31 PM PDT 24
Peak memory	251300 kb
Host	smart-d857f3ca-897a-4f7d-a839-ff4dcb600b0a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2544412329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.2544412329
Directory	/workspace/3.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/3.lc_ctrl_state_post_trans.140316100
Short name	T488
Test name
Test status
Simulation time	73734261 ps
CPU time	4.04 seconds
Started	Jul 01 06:43:59 PM PDT 24
Finished	Jul 01 06:44:04 PM PDT 24
Peak memory	222580 kb
Host	smart-449b446c-a1c9-4c9d-8800-e2f25681659b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=140316100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.140316100
Directory	/workspace/3.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/3.lc_ctrl_stress_all.1483606341
Short name	T608
Test name
Test status
Simulation time	86077397870 ps
CPU time	120.35 seconds
Started	Jul 01 06:44:09 PM PDT 24
Finished	Jul 01 06:46:12 PM PDT 24
Peak memory	278824 kb
Host	smart-b9c2b270-bfe7-49a2-8fee-677a0774a311
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483606341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all.1483606341
Directory	/workspace/3.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.3077391143
Short name	T542
Test name
Test status
Simulation time	39155577 ps
CPU time	0.81 seconds
Started	Jul 01 06:44:03 PM PDT 24
Finished	Jul 01 06:44:05 PM PDT 24
Peak memory	209232 kb
Host	smart-29026ab8-5b75-48cb-9f49-4cdfcdc1a2fe
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077391143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct rl_volatile_unlock_smoke.3077391143
Directory	/workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/30.lc_ctrl_alert_test.2715792169
Short name	T651
Test name
Test status
Simulation time	67979193 ps
CPU time	0.9 seconds
Started	Jul 01 06:46:33 PM PDT 24
Finished	Jul 01 06:46:40 PM PDT 24
Peak memory	209480 kb
Host	smart-ce98dede-110c-4057-9029-6e9d67d1ed42
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715792169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.2715792169
Directory	/workspace/30.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/30.lc_ctrl_errors.879563929
Short name	T634
Test name
Test status
Simulation time	1120536850 ps
CPU time	11.37 seconds
Started	Jul 01 06:46:30 PM PDT 24
Finished	Jul 01 06:46:44 PM PDT 24
Peak memory	218704 kb
Host	smart-b8e15d9a-fbef-4de3-a7b3-8968b172805c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=879563929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.879563929
Directory	/workspace/30.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/30.lc_ctrl_jtag_access.647901979
Short name	T584
Test name
Test status
Simulation time	695062873 ps
CPU time	4.36 seconds
Started	Jul 01 06:46:29 PM PDT 24
Finished	Jul 01 06:46:37 PM PDT 24
Peak memory	217812 kb
Host	smart-7eef8e61-b560-4551-bb0a-b6bef580ba84
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647901979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.647901979
Directory	/workspace/30.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/30.lc_ctrl_prog_failure.261331989
Short name	T646
Test name
Test status
Simulation time	66772605 ps
CPU time	3.4 seconds
Started	Jul 01 06:46:29 PM PDT 24
Finished	Jul 01 06:46:36 PM PDT 24
Peak memory	218752 kb
Host	smart-835a3b59-a605-421d-af6b-018bff0590d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=261331989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.261331989
Directory	/workspace/30.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/30.lc_ctrl_sec_mubi.3955317504
Short name	T424
Test name
Test status
Simulation time	388188863 ps
CPU time	10.23 seconds
Started	Jul 01 06:46:33 PM PDT 24
Finished	Jul 01 06:46:48 PM PDT 24
Peak memory	218872 kb
Host	smart-42a2043e-c15b-4257-aaff-5af6af84733f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955317504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.3955317504
Directory	/workspace/30.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/30.lc_ctrl_sec_token_digest.3498220814
Short name	T448
Test name
Test status
Simulation time	2359159977 ps
CPU time	13.76 seconds
Started	Jul 01 06:46:33 PM PDT 24
Finished	Jul 01 06:46:53 PM PDT 24
Peak memory	218712 kb
Host	smart-e053c2c5-4e18-454d-be04-c7ad8522d31e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498220814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d igest.3498220814
Directory	/workspace/30.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/30.lc_ctrl_sec_token_mux.3507059253
Short name	T444
Test name
Test status
Simulation time	604527742 ps
CPU time	7.94 seconds
Started	Jul 01 06:46:32 PM PDT 24
Finished	Jul 01 06:46:43 PM PDT 24
Peak memory	218580 kb
Host	smart-c59c2429-2abd-4302-992b-bd431533b29c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507059253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux. 3507059253
Directory	/workspace/30.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/30.lc_ctrl_security_escalation.2830616187
Short name	T376
Test name
Test status
Simulation time	479633194 ps
CPU time	10.47 seconds
Started	Jul 01 06:46:31 PM PDT 24
Finished	Jul 01 06:46:45 PM PDT 24
Peak memory	226524 kb
Host	smart-bd842595-46e5-4670-9f88-c4780ef83975
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2830616187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.2830616187
Directory	/workspace/30.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/30.lc_ctrl_smoke.1326468525
Short name	T718
Test name
Test status
Simulation time	200947624 ps
CPU time	2.38 seconds
Started	Jul 01 06:46:31 PM PDT 24
Finished	Jul 01 06:46:36 PM PDT 24
Peak memory	215020 kb
Host	smart-84d16a2a-08cd-48cc-83dd-14123d1c3e20
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1326468525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.1326468525
Directory	/workspace/30.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/30.lc_ctrl_state_failure.4145484159
Short name	T262
Test name
Test status
Simulation time	278945830 ps
CPU time	32.56 seconds
Started	Jul 01 06:46:33 PM PDT 24
Finished	Jul 01 06:47:12 PM PDT 24
Peak memory	246756 kb
Host	smart-dc56eab7-3068-4fd4-b450-16abfb532491
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4145484159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.4145484159
Directory	/workspace/30.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/30.lc_ctrl_state_post_trans.677421792
Short name	T120
Test name
Test status
Simulation time	245842883 ps
CPU time	8.23 seconds
Started	Jul 01 06:46:33 PM PDT 24
Finished	Jul 01 06:46:47 PM PDT 24
Peak memory	251476 kb
Host	smart-2af3b27e-e47d-4c0a-94a2-ea93172849aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=677421792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.677421792
Directory	/workspace/30.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/30.lc_ctrl_stress_all.309900016
Short name	T371
Test name
Test status
Simulation time	9614741678 ps
CPU time	300.52 seconds
Started	Jul 01 06:46:30 PM PDT 24
Finished	Jul 01 06:51:34 PM PDT 24
Peak memory	277228 kb
Host	smart-c6bc792a-dfee-418a-bb6e-86fa377c3d2c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309900016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all.309900016
Directory	/workspace/30.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.2969590562
Short name	T88
Test name
Test status
Simulation time	24778990 ps
CPU time	0.92 seconds
Started	Jul 01 06:46:33 PM PDT 24
Finished	Jul 01 06:46:41 PM PDT 24
Peak memory	212428 kb
Host	smart-4cfbb713-fa19-4e31-b3cb-d3d5e36605a1
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969590562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c trl_volatile_unlock_smoke.2969590562
Directory	/workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/31.lc_ctrl_alert_test.1605205077
Short name	T577
Test name
Test status
Simulation time	298620721 ps
CPU time	1.29 seconds
Started	Jul 01 06:46:29 PM PDT 24
Finished	Jul 01 06:46:34 PM PDT 24
Peak memory	209448 kb
Host	smart-f73a255b-046e-43de-ba89-dcd1d77f5cdc
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605205077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.1605205077
Directory	/workspace/31.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/31.lc_ctrl_errors.3392389758
Short name	T515
Test name
Test status
Simulation time	645607430 ps
CPU time	28 seconds
Started	Jul 01 06:46:31 PM PDT 24
Finished	Jul 01 06:47:02 PM PDT 24
Peak memory	218616 kb
Host	smart-68a73af9-2e04-4b0b-8414-5590575b28b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3392389758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.3392389758
Directory	/workspace/31.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/31.lc_ctrl_jtag_access.2662036502
Short name	T474
Test name
Test status
Simulation time	2938501156 ps
CPU time	8.72 seconds
Started	Jul 01 06:46:31 PM PDT 24
Finished	Jul 01 06:46:43 PM PDT 24
Peak memory	218056 kb
Host	smart-2d2b78a3-c086-4fbe-880c-0da92f7c5dfb
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662036502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.2662036502
Directory	/workspace/31.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/31.lc_ctrl_prog_failure.2745130578
Short name	T700
Test name
Test status
Simulation time	288230775 ps
CPU time	3.66 seconds
Started	Jul 01 06:46:33 PM PDT 24
Finished	Jul 01 06:46:43 PM PDT 24
Peak memory	218760 kb
Host	smart-04951850-2e56-4a54-b45d-2389d7fae3e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2745130578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.2745130578
Directory	/workspace/31.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/31.lc_ctrl_sec_mubi.106152260
Short name	T812
Test name
Test status
Simulation time	370934076 ps
CPU time	11.8 seconds
Started	Jul 01 06:46:31 PM PDT 24
Finished	Jul 01 06:46:46 PM PDT 24
Peak memory	225996 kb
Host	smart-e174f446-b01e-4829-8b91-29aebf25e609
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106152260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.106152260
Directory	/workspace/31.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/31.lc_ctrl_sec_token_digest.1652551125
Short name	T367
Test name
Test status
Simulation time	876755906 ps
CPU time	11.55 seconds
Started	Jul 01 06:46:31 PM PDT 24
Finished	Jul 01 06:46:47 PM PDT 24
Peak memory	218688 kb
Host	smart-adb18218-38d8-4aff-8045-787f76e1e394
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652551125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d igest.1652551125
Directory	/workspace/31.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/31.lc_ctrl_sec_token_mux.3916298949
Short name	T612
Test name
Test status
Simulation time	1073973089 ps
CPU time	8.24 seconds
Started	Jul 01 06:46:30 PM PDT 24
Finished	Jul 01 06:46:41 PM PDT 24
Peak memory	218588 kb
Host	smart-2d67083e-1d3c-483e-8405-a39e73bbe0fb
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916298949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux. 3916298949
Directory	/workspace/31.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/31.lc_ctrl_security_escalation.3048690602
Short name	T539
Test name
Test status
Simulation time	800983095 ps
CPU time	10.32 seconds
Started	Jul 01 06:46:33 PM PDT 24
Finished	Jul 01 06:46:49 PM PDT 24
Peak memory	226108 kb
Host	smart-599a370d-ad03-479c-86e3-1fb3e381d036
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3048690602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.3048690602
Directory	/workspace/31.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/31.lc_ctrl_smoke.2812084855
Short name	T687
Test name
Test status
Simulation time	104453367 ps
CPU time	1.8 seconds
Started	Jul 01 06:46:33 PM PDT 24
Finished	Jul 01 06:46:42 PM PDT 24
Peak memory	218204 kb
Host	smart-99f6c67a-b243-4a42-8706-44a7562c91f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2812084855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.2812084855
Directory	/workspace/31.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/31.lc_ctrl_state_failure.3674477335
Short name	T516
Test name
Test status
Simulation time	690359097 ps
CPU time	21.58 seconds
Started	Jul 01 06:46:31 PM PDT 24
Finished	Jul 01 06:46:56 PM PDT 24
Peak memory	251396 kb
Host	smart-b702133e-3b82-42b4-84d6-569cfbebef2d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3674477335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.3674477335
Directory	/workspace/31.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/31.lc_ctrl_state_post_trans.2578303576
Short name	T383
Test name
Test status
Simulation time	94156719 ps
CPU time	8.88 seconds
Started	Jul 01 06:46:33 PM PDT 24
Finished	Jul 01 06:46:49 PM PDT 24
Peak memory	251284 kb
Host	smart-93c53c94-9673-4e4c-ba5b-caaf2d480529
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2578303576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.2578303576
Directory	/workspace/31.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/31.lc_ctrl_stress_all.2566021974
Short name	T576
Test name
Test status
Simulation time	8241241024 ps
CPU time	144.09 seconds
Started	Jul 01 06:46:32 PM PDT 24
Finished	Jul 01 06:49:00 PM PDT 24
Peak memory	220204 kb
Host	smart-97a7be4f-adca-40d1-8912-25490902b022
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566021974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all.2566021974
Directory	/workspace/31.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.1038209747
Short name	T81
Test name
Test status
Simulation time	14735585936 ps
CPU time	289.25 seconds
Started	Jul 01 06:46:30 PM PDT 24
Finished	Jul 01 06:51:23 PM PDT 24
Peak memory	278744 kb
Host	smart-edbfc608-c313-4f62-b2c2-564ba6dcda6b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1038209747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all_with_rand_reset.1038209747
Directory	/workspace/31.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.4255649997
Short name	T776
Test name
Test status
Simulation time	26319793 ps
CPU time	0.95 seconds
Started	Jul 01 06:46:31 PM PDT 24
Finished	Jul 01 06:46:35 PM PDT 24
Peak memory	212232 kb
Host	smart-a5c42e7e-1f8a-44d9-989c-c805a156b1cf
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255649997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c trl_volatile_unlock_smoke.4255649997
Directory	/workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/32.lc_ctrl_alert_test.163211825
Short name	T344
Test name
Test status
Simulation time	19089503 ps
CPU time	1.18 seconds
Started	Jul 01 06:46:38 PM PDT 24
Finished	Jul 01 06:46:45 PM PDT 24
Peak memory	209520 kb
Host	smart-7ebc83cf-9224-426c-8bb3-d8d8f4bba7a4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163211825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.163211825
Directory	/workspace/32.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/32.lc_ctrl_errors.565248180
Short name	T387
Test name
Test status
Simulation time	230606318 ps
CPU time	9.91 seconds
Started	Jul 01 06:46:31 PM PDT 24
Finished	Jul 01 06:46:45 PM PDT 24
Peak memory	218640 kb
Host	smart-856e7ca5-7079-4d42-8a1a-2889ab4fec9b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=565248180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.565248180
Directory	/workspace/32.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/32.lc_ctrl_jtag_access.292893502
Short name	T853
Test name
Test status
Simulation time	1186121602 ps
CPU time	4.26 seconds
Started	Jul 01 06:46:33 PM PDT 24
Finished	Jul 01 06:46:44 PM PDT 24
Peak memory	217488 kb
Host	smart-cace6d20-607e-4faa-a2da-929ad51178ae
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292893502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.292893502
Directory	/workspace/32.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/32.lc_ctrl_prog_failure.1172119910
Short name	T678
Test name
Test status
Simulation time	79256470 ps
CPU time	3.79 seconds
Started	Jul 01 06:46:31 PM PDT 24
Finished	Jul 01 06:46:38 PM PDT 24
Peak memory	222820 kb
Host	smart-d0788732-2a8b-45d1-b8f7-e9cbe2c16b5b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1172119910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.1172119910
Directory	/workspace/32.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/32.lc_ctrl_sec_mubi.1136278968
Short name	T755
Test name
Test status
Simulation time	796869361 ps
CPU time	8.42 seconds
Started	Jul 01 06:46:33 PM PDT 24
Finished	Jul 01 06:46:46 PM PDT 24
Peak memory	218656 kb
Host	smart-9728d6f4-9d4f-424d-a023-e1d9b22e95e7
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136278968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.1136278968
Directory	/workspace/32.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/32.lc_ctrl_sec_token_digest.181152651
Short name	T809
Test name
Test status
Simulation time	1700639348 ps
CPU time	12.13 seconds
Started	Jul 01 06:46:39 PM PDT 24
Finished	Jul 01 06:46:56 PM PDT 24
Peak memory	218576 kb
Host	smart-47b7e28f-f593-46f0-9d92-0f2de7b9be26
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181152651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_di gest.181152651
Directory	/workspace/32.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/32.lc_ctrl_sec_token_mux.1057719931
Short name	T64
Test name
Test status
Simulation time	2946785407 ps
CPU time	8.96 seconds
Started	Jul 01 06:46:40 PM PDT 24
Finished	Jul 01 06:46:54 PM PDT 24
Peak memory	218652 kb
Host	smart-c4bc46c0-c95d-4748-b2d4-4bb64523b103
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057719931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux. 1057719931
Directory	/workspace/32.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/32.lc_ctrl_security_escalation.1327140384
Short name	T639
Test name
Test status
Simulation time	456593195 ps
CPU time	15.07 seconds
Started	Jul 01 06:46:29 PM PDT 24
Finished	Jul 01 06:46:48 PM PDT 24
Peak memory	226436 kb
Host	smart-bc9ebe89-3cdc-4759-945f-5a280407e0aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1327140384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.1327140384
Directory	/workspace/32.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/32.lc_ctrl_smoke.2714113512
Short name	T762
Test name
Test status
Simulation time	132798126 ps
CPU time	2.51 seconds
Started	Jul 01 06:46:33 PM PDT 24
Finished	Jul 01 06:46:42 PM PDT 24
Peak memory	215056 kb
Host	smart-82441819-d344-4f1f-a534-3f59a62eed23
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2714113512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.2714113512
Directory	/workspace/32.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/32.lc_ctrl_state_failure.1704708122
Short name	T548
Test name
Test status
Simulation time	196344992 ps
CPU time	19.66 seconds
Started	Jul 01 06:46:29 PM PDT 24
Finished	Jul 01 06:46:52 PM PDT 24
Peak memory	251420 kb
Host	smart-78edda2e-3d42-4f30-9566-29fb5af7be3e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1704708122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.1704708122
Directory	/workspace/32.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/32.lc_ctrl_state_post_trans.839091963
Short name	T554
Test name
Test status
Simulation time	100185469 ps
CPU time	3.5 seconds
Started	Jul 01 06:46:29 PM PDT 24
Finished	Jul 01 06:46:36 PM PDT 24
Peak memory	218708 kb
Host	smart-e6cf88a4-44d8-4376-8dfd-fa6094b7ac54
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=839091963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.839091963
Directory	/workspace/32.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/32.lc_ctrl_stress_all.2159994594
Short name	T282
Test name
Test status
Simulation time	63541138991 ps
CPU time	472.48 seconds
Started	Jul 01 06:46:42 PM PDT 24
Finished	Jul 01 06:54:39 PM PDT 24
Peak memory	283228 kb
Host	smart-59be7643-c9cc-4686-8db5-c5ecfa93600b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159994594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all.2159994594
Directory	/workspace/32.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.3562602348
Short name	T546
Test name
Test status
Simulation time	24872389 ps
CPU time	0.81 seconds
Started	Jul 01 06:46:31 PM PDT 24
Finished	Jul 01 06:46:36 PM PDT 24
Peak memory	209436 kb
Host	smart-374886dd-b7d4-4788-9149-17aff3d6bd04
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562602348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c trl_volatile_unlock_smoke.3562602348
Directory	/workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/33.lc_ctrl_alert_test.2141743534
Short name	T551
Test name
Test status
Simulation time	14501280 ps
CPU time	1.02 seconds
Started	Jul 01 06:46:39 PM PDT 24
Finished	Jul 01 06:46:45 PM PDT 24
Peak memory	209440 kb
Host	smart-3d60c183-f987-40a0-b6a7-4b4055593bf8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141743534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.2141743534
Directory	/workspace/33.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/33.lc_ctrl_errors.474587779
Short name	T232
Test name
Test status
Simulation time	349094738 ps
CPU time	16.74 seconds
Started	Jul 01 06:46:44 PM PDT 24
Finished	Jul 01 06:47:04 PM PDT 24
Peak memory	218632 kb
Host	smart-b4a5d36e-5d62-4cf5-bc27-67306b7ed873
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=474587779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.474587779
Directory	/workspace/33.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/33.lc_ctrl_jtag_access.2599143057
Short name	T637
Test name
Test status
Simulation time	148206905 ps
CPU time	4.71 seconds
Started	Jul 01 06:46:38 PM PDT 24
Finished	Jul 01 06:46:48 PM PDT 24
Peak memory	217496 kb
Host	smart-10597a1d-ad0a-4dd6-8538-869e653e86d8
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599143057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.2599143057
Directory	/workspace/33.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/33.lc_ctrl_prog_failure.1510907471
Short name	T233
Test name
Test status
Simulation time	565306277 ps
CPU time	4.32 seconds
Started	Jul 01 06:46:41 PM PDT 24
Finished	Jul 01 06:46:50 PM PDT 24
Peak memory	222920 kb
Host	smart-844ce70c-c3bc-4737-9811-80367902e27e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1510907471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.1510907471
Directory	/workspace/33.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/33.lc_ctrl_sec_mubi.2111689369
Short name	T863
Test name
Test status
Simulation time	1050825904 ps
CPU time	9.94 seconds
Started	Jul 01 06:46:41 PM PDT 24
Finished	Jul 01 06:46:55 PM PDT 24
Peak memory	218756 kb
Host	smart-2a9c5a2c-a394-4170-a361-e80208e0df1f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111689369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.2111689369
Directory	/workspace/33.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/33.lc_ctrl_sec_token_digest.1366954983
Short name	T100
Test name
Test status
Simulation time	6335864976 ps
CPU time	12.96 seconds
Started	Jul 01 06:46:37 PM PDT 24
Finished	Jul 01 06:46:56 PM PDT 24
Peak memory	218668 kb
Host	smart-a83b60d4-e128-4f4b-94e4-4fea8dd1df91
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366954983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d igest.1366954983
Directory	/workspace/33.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/33.lc_ctrl_sec_token_mux.1545225328
Short name	T775
Test name
Test status
Simulation time	2202119462 ps
CPU time	7.65 seconds
Started	Jul 01 06:46:40 PM PDT 24
Finished	Jul 01 06:46:52 PM PDT 24
Peak memory	218652 kb
Host	smart-3c2902ec-13a7-495a-9cf8-7be70a501207
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545225328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux. 1545225328
Directory	/workspace/33.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/33.lc_ctrl_security_escalation.2053670815
Short name	T62
Test name
Test status
Simulation time	312545143 ps
CPU time	12.67 seconds
Started	Jul 01 06:46:40 PM PDT 24
Finished	Jul 01 06:46:57 PM PDT 24
Peak memory	218768 kb
Host	smart-25da7dd0-1b63-458c-ab65-7f04c03bbad1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2053670815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.2053670815
Directory	/workspace/33.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/33.lc_ctrl_smoke.1382624834
Short name	T813
Test name
Test status
Simulation time	98691080 ps
CPU time	1.73 seconds
Started	Jul 01 06:46:37 PM PDT 24
Finished	Jul 01 06:46:45 PM PDT 24
Peak memory	218184 kb
Host	smart-44563096-6595-444f-aa2a-5c1420f692cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1382624834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.1382624834
Directory	/workspace/33.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/33.lc_ctrl_state_failure.1414063980
Short name	T265
Test name
Test status
Simulation time	250840962 ps
CPU time	36.05 seconds
Started	Jul 01 06:46:39 PM PDT 24
Finished	Jul 01 06:47:20 PM PDT 24
Peak memory	251412 kb
Host	smart-882adcef-dbee-4648-99dd-7417cf8a06c4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1414063980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.1414063980
Directory	/workspace/33.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/33.lc_ctrl_state_post_trans.2305647929
Short name	T482
Test name
Test status
Simulation time	358003839 ps
CPU time	3.16 seconds
Started	Jul 01 06:46:40 PM PDT 24
Finished	Jul 01 06:46:48 PM PDT 24
Peak memory	221432 kb
Host	smart-083baac1-7ad2-45a7-b2b3-510ea473a318
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2305647929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.2305647929
Directory	/workspace/33.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/33.lc_ctrl_stress_all.815040990
Short name	T524
Test name
Test status
Simulation time	15873743029 ps
CPU time	157.29 seconds
Started	Jul 01 06:46:39 PM PDT 24
Finished	Jul 01 06:49:21 PM PDT 24
Peak memory	276296 kb
Host	smart-4d7464c6-894e-4989-9018-560830fff22c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815040990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all.815040990
Directory	/workspace/33.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.2069548809
Short name	T98
Test name
Test status
Simulation time	21987268207 ps
CPU time	479.09 seconds
Started	Jul 01 06:46:37 PM PDT 24
Finished	Jul 01 06:54:43 PM PDT 24
Peak memory	333524 kb
Host	smart-ee217707-4c09-4197-80d5-9c47f8ef9839
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2069548809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.2069548809
Directory	/workspace/33.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.3000877508
Short name	T369
Test name
Test status
Simulation time	11112498 ps
CPU time	0.93 seconds
Started	Jul 01 06:46:39 PM PDT 24
Finished	Jul 01 06:46:45 PM PDT 24
Peak memory	209492 kb
Host	smart-1acb2081-3409-44b8-8f7d-b57a63f0807b
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000877508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c trl_volatile_unlock_smoke.3000877508
Directory	/workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/34.lc_ctrl_alert_test.241789972
Short name	T600
Test name
Test status
Simulation time	147989775 ps
CPU time	1.09 seconds
Started	Jul 01 06:46:45 PM PDT 24
Finished	Jul 01 06:46:50 PM PDT 24
Peak memory	209388 kb
Host	smart-e4ec0c6a-0d6e-4a63-a054-7734672fd2b5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241789972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.241789972
Directory	/workspace/34.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/34.lc_ctrl_errors.1600655905
Short name	T165
Test name
Test status
Simulation time	995849287 ps
CPU time	10.95 seconds
Started	Jul 01 06:46:36 PM PDT 24
Finished	Jul 01 06:46:53 PM PDT 24
Peak memory	218644 kb
Host	smart-0fc26ee0-0b78-4dfb-8d35-28ef36b69805
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1600655905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.1600655905
Directory	/workspace/34.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/34.lc_ctrl_jtag_access.1688492587
Short name	T631
Test name
Test status
Simulation time	1398160258 ps
CPU time	8.93 seconds
Started	Jul 01 06:46:44 PM PDT 24
Finished	Jul 01 06:46:56 PM PDT 24
Peak memory	217396 kb
Host	smart-b4881c00-4379-4a6b-81c5-26f85ba565dc
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688492587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.1688492587
Directory	/workspace/34.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/34.lc_ctrl_prog_failure.1084642179
Short name	T672
Test name
Test status
Simulation time	65039209 ps
CPU time	3.5 seconds
Started	Jul 01 06:46:40 PM PDT 24
Finished	Jul 01 06:46:49 PM PDT 24
Peak memory	222980 kb
Host	smart-49f7feba-8cc0-4f03-b721-3e49b7599874
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1084642179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.1084642179
Directory	/workspace/34.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/34.lc_ctrl_sec_mubi.135625201
Short name	T856
Test name
Test status
Simulation time	1039200052 ps
CPU time	13 seconds
Started	Jul 01 06:46:38 PM PDT 24
Finished	Jul 01 06:46:57 PM PDT 24
Peak memory	219376 kb
Host	smart-84ec6d31-7c2b-4ad1-ae1f-0334209d3709
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135625201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.135625201
Directory	/workspace/34.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/34.lc_ctrl_sec_token_digest.4143386218
Short name	T841
Test name
Test status
Simulation time	999195336 ps
CPU time	8.35 seconds
Started	Jul 01 06:46:39 PM PDT 24
Finished	Jul 01 06:46:52 PM PDT 24
Peak memory	218680 kb
Host	smart-949027c5-7f23-4561-9ff5-9bcf4923dc9c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143386218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d igest.4143386218
Directory	/workspace/34.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/34.lc_ctrl_sec_token_mux.92623384
Short name	T675
Test name
Test status
Simulation time	1253460452 ps
CPU time	9.87 seconds
Started	Jul 01 06:46:38 PM PDT 24
Finished	Jul 01 06:46:54 PM PDT 24
Peak memory	226388 kb
Host	smart-dea7988e-278a-4fbd-91e4-7cc0f4bd1e24
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92623384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.92623384
Directory	/workspace/34.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/34.lc_ctrl_security_escalation.1038285142
Short name	T12
Test name
Test status
Simulation time	2481850395 ps
CPU time	8.9 seconds
Started	Jul 01 06:46:40 PM PDT 24
Finished	Jul 01 06:46:53 PM PDT 24
Peak memory	226504 kb
Host	smart-59c00b89-7e33-4b14-941d-e33b9c93efee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1038285142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.1038285142
Directory	/workspace/34.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/34.lc_ctrl_smoke.511298012
Short name	T101
Test name
Test status
Simulation time	30660094 ps
CPU time	1.99 seconds
Started	Jul 01 06:46:38 PM PDT 24
Finished	Jul 01 06:46:46 PM PDT 24
Peak memory	218092 kb
Host	smart-4c395839-0397-42c7-809f-7484cc46d589
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=511298012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.511298012
Directory	/workspace/34.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/34.lc_ctrl_state_failure.701965388
Short name	T701
Test name
Test status
Simulation time	617179466 ps
CPU time	32.39 seconds
Started	Jul 01 06:46:44 PM PDT 24
Finished	Jul 01 06:47:20 PM PDT 24
Peak memory	251068 kb
Host	smart-8785ca10-e97e-4532-91f6-f79f98bc084d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=701965388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.701965388
Directory	/workspace/34.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/34.lc_ctrl_state_post_trans.334291556
Short name	T218
Test name
Test status
Simulation time	59145734 ps
CPU time	6.19 seconds
Started	Jul 01 06:46:41 PM PDT 24
Finished	Jul 01 06:46:52 PM PDT 24
Peak memory	250860 kb
Host	smart-0f733d3f-6b73-4622-8f3b-0a5053f9cdf2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=334291556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.334291556
Directory	/workspace/34.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/34.lc_ctrl_stress_all.2301088469
Short name	T787
Test name
Test status
Simulation time	40746621304 ps
CPU time	77.44 seconds
Started	Jul 01 06:46:46 PM PDT 24
Finished	Jul 01 06:48:06 PM PDT 24
Peak memory	282012 kb
Host	smart-eeaa318d-2c88-4522-b1d2-b8e820378a69
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301088469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all.2301088469
Directory	/workspace/34.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.2082888244
Short name	T784
Test name
Test status
Simulation time	98972706716 ps
CPU time	1006.4 seconds
Started	Jul 01 06:46:45 PM PDT 24
Finished	Jul 01 07:03:35 PM PDT 24
Peak memory	497280 kb
Host	smart-3f64421a-53ce-4c98-9b30-8ed49fae8256
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2082888244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.2082888244
Directory	/workspace/34.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.3290672328
Short name	T802
Test name
Test status
Simulation time	13583337 ps
CPU time	1.07 seconds
Started	Jul 01 06:46:39 PM PDT 24
Finished	Jul 01 06:46:45 PM PDT 24
Peak memory	212272 kb
Host	smart-fed1876b-ceb7-4118-8fab-af2846b2c6be
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290672328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c trl_volatile_unlock_smoke.3290672328
Directory	/workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/35.lc_ctrl_alert_test.2862282371
Short name	T299
Test name
Test status
Simulation time	40591350 ps
CPU time	0.96 seconds
Started	Jul 01 06:46:47 PM PDT 24
Finished	Jul 01 06:46:51 PM PDT 24
Peak memory	209528 kb
Host	smart-a6409a09-d32a-44d5-ab77-3019874a9fb9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862282371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.2862282371
Directory	/workspace/35.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/35.lc_ctrl_errors.1220240176
Short name	T412
Test name
Test status
Simulation time	1053784609 ps
CPU time	8.68 seconds
Started	Jul 01 06:46:45 PM PDT 24
Finished	Jul 01 06:46:57 PM PDT 24
Peak memory	226448 kb
Host	smart-a85f5f63-bcd5-4b2f-ab51-69be988a32db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1220240176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.1220240176
Directory	/workspace/35.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/35.lc_ctrl_jtag_access.1328687004
Short name	T705
Test name
Test status
Simulation time	2571271568 ps
CPU time	16.51 seconds
Started	Jul 01 06:46:47 PM PDT 24
Finished	Jul 01 06:47:07 PM PDT 24
Peak memory	218056 kb
Host	smart-0f384dd9-45fb-4aea-a582-72713aedf77f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328687004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.1328687004
Directory	/workspace/35.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/35.lc_ctrl_prog_failure.1397472783
Short name	T562
Test name
Test status
Simulation time	85265100 ps
CPU time	4.03 seconds
Started	Jul 01 06:46:47 PM PDT 24
Finished	Jul 01 06:46:54 PM PDT 24
Peak memory	222888 kb
Host	smart-cf616f7e-25ac-47a4-bfa9-70fffd496bb3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1397472783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.1397472783
Directory	/workspace/35.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/35.lc_ctrl_sec_mubi.2765725919
Short name	T50
Test name
Test status
Simulation time	423736880 ps
CPU time	18.21 seconds
Started	Jul 01 06:46:48 PM PDT 24
Finished	Jul 01 06:47:09 PM PDT 24
Peak memory	226608 kb
Host	smart-b1e8ce27-a35d-4486-a458-fc27d4bbf505
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765725919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.2765725919
Directory	/workspace/35.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/35.lc_ctrl_sec_token_digest.2595022751
Short name	T794
Test name
Test status
Simulation time	1037714803 ps
CPU time	11.02 seconds
Started	Jul 01 06:46:50 PM PDT 24
Finished	Jul 01 06:47:03 PM PDT 24
Peak memory	218724 kb
Host	smart-c5c23848-1f23-49e0-9c8b-0ddbf694f571
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595022751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d igest.2595022751
Directory	/workspace/35.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/35.lc_ctrl_sec_token_mux.842998963
Short name	T833
Test name
Test status
Simulation time	674360020 ps
CPU time	12.68 seconds
Started	Jul 01 06:46:46 PM PDT 24
Finished	Jul 01 06:47:02 PM PDT 24
Peak memory	218660 kb
Host	smart-427517c4-bf57-43a3-a5be-a49b5f29a4e9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842998963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.842998963
Directory	/workspace/35.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/35.lc_ctrl_security_escalation.3527385733
Short name	T1
Test name
Test status
Simulation time	493302297 ps
CPU time	9.52 seconds
Started	Jul 01 06:46:52 PM PDT 24
Finished	Jul 01 06:47:03 PM PDT 24
Peak memory	226512 kb
Host	smart-3cc74b74-3ad8-4d57-b6c7-8752f4f4f308
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3527385733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.3527385733
Directory	/workspace/35.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/35.lc_ctrl_smoke.45698205
Short name	T742
Test name
Test status
Simulation time	69839359 ps
CPU time	2.31 seconds
Started	Jul 01 06:46:52 PM PDT 24
Finished	Jul 01 06:46:55 PM PDT 24
Peak memory	218144 kb
Host	smart-44548253-5a81-49dc-9083-d70fcbe01f3f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=45698205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.45698205
Directory	/workspace/35.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/35.lc_ctrl_state_failure.4186807659
Short name	T451
Test name
Test status
Simulation time	226112160 ps
CPU time	24.23 seconds
Started	Jul 01 06:46:48 PM PDT 24
Finished	Jul 01 06:47:15 PM PDT 24
Peak memory	251372 kb
Host	smart-652c7e1b-e471-4554-b432-adaaa46f62c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4186807659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.4186807659
Directory	/workspace/35.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/35.lc_ctrl_state_post_trans.989931938
Short name	T521
Test name
Test status
Simulation time	88391498 ps
CPU time	8.21 seconds
Started	Jul 01 06:46:46 PM PDT 24
Finished	Jul 01 06:46:57 PM PDT 24
Peak memory	251408 kb
Host	smart-e4e5c4ed-407e-4a42-b93d-746e03e799ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=989931938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.989931938
Directory	/workspace/35.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/35.lc_ctrl_stress_all.4108878105
Short name	T723
Test name
Test status
Simulation time	14681517375 ps
CPU time	162.58 seconds
Started	Jul 01 06:46:46 PM PDT 24
Finished	Jul 01 06:49:32 PM PDT 24
Peak memory	284176 kb
Host	smart-ff4abcbb-76e6-4cc1-adcc-17b64500bb77
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108878105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all.4108878105
Directory	/workspace/35.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.751894707
Short name	T601
Test name
Test status
Simulation time	13232182 ps
CPU time	0.95 seconds
Started	Jul 01 06:46:45 PM PDT 24
Finished	Jul 01 06:46:49 PM PDT 24
Peak memory	212252 kb
Host	smart-0177565d-258f-4168-b78b-525e86f49fad
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751894707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ct rl_volatile_unlock_smoke.751894707
Directory	/workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/36.lc_ctrl_alert_test.1165237257
Short name	T499
Test name
Test status
Simulation time	78701423 ps
CPU time	0.93 seconds
Started	Jul 01 06:46:50 PM PDT 24
Finished	Jul 01 06:46:53 PM PDT 24
Peak memory	209516 kb
Host	smart-846c874c-d408-4b66-bc00-90070aae39d4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165237257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.1165237257
Directory	/workspace/36.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/36.lc_ctrl_errors.388633338
Short name	T266
Test name
Test status
Simulation time	264495121 ps
CPU time	9.24 seconds
Started	Jul 01 06:46:51 PM PDT 24
Finished	Jul 01 06:47:02 PM PDT 24
Peak memory	226584 kb
Host	smart-5c0e37f2-36e2-4333-96d5-47723b3ea2c4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=388633338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.388633338
Directory	/workspace/36.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/36.lc_ctrl_jtag_access.2867700641
Short name	T415
Test name
Test status
Simulation time	3844786315 ps
CPU time	6.98 seconds
Started	Jul 01 06:46:51 PM PDT 24
Finished	Jul 01 06:47:00 PM PDT 24
Peak memory	218200 kb
Host	smart-f1d8e630-c3ae-4072-916c-2f99cf902e9d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867700641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.2867700641
Directory	/workspace/36.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/36.lc_ctrl_prog_failure.932773945
Short name	T746
Test name
Test status
Simulation time	286196394 ps
CPU time	2.34 seconds
Started	Jul 01 06:46:46 PM PDT 24
Finished	Jul 01 06:46:51 PM PDT 24
Peak memory	218724 kb
Host	smart-e667dc1c-a32d-43f7-b7b8-d3ed054b0ec8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=932773945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.932773945
Directory	/workspace/36.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/36.lc_ctrl_sec_mubi.1501568710
Short name	T827
Test name
Test status
Simulation time	311930357 ps
CPU time	12.99 seconds
Started	Jul 01 06:46:44 PM PDT 24
Finished	Jul 01 06:47:01 PM PDT 24
Peak memory	226556 kb
Host	smart-4b53d235-fdd3-4be0-92dd-75e1731c7c3d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501568710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.1501568710
Directory	/workspace/36.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/36.lc_ctrl_sec_token_digest.2384072650
Short name	T243
Test name
Test status
Simulation time	535704989 ps
CPU time	9.13 seconds
Started	Jul 01 06:46:52 PM PDT 24
Finished	Jul 01 06:47:03 PM PDT 24
Peak memory	218744 kb
Host	smart-13800363-c4f8-4c8e-bfff-cba21f82000d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384072650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d igest.2384072650
Directory	/workspace/36.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/36.lc_ctrl_sec_token_mux.3002673948
Short name	T819
Test name
Test status
Simulation time	822697756 ps
CPU time	6.55 seconds
Started	Jul 01 06:46:47 PM PDT 24
Finished	Jul 01 06:46:57 PM PDT 24
Peak memory	226348 kb
Host	smart-d72330aa-be7d-411f-bdcc-bf9ebb09f949
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002673948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux. 3002673948
Directory	/workspace/36.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/36.lc_ctrl_security_escalation.856734428
Short name	T319
Test name
Test status
Simulation time	256343277 ps
CPU time	8.85 seconds
Started	Jul 01 06:46:46 PM PDT 24
Finished	Jul 01 06:46:59 PM PDT 24
Peak memory	226452 kb
Host	smart-60d98f21-05b5-4e61-aa6e-c0bc74880369
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=856734428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.856734428
Directory	/workspace/36.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/36.lc_ctrl_smoke.1319769240
Short name	T254
Test name
Test status
Simulation time	44009953 ps
CPU time	1.86 seconds
Started	Jul 01 06:46:46 PM PDT 24
Finished	Jul 01 06:46:51 PM PDT 24
Peak memory	218148 kb
Host	smart-0442d1bd-4bf3-4fcd-bd8c-a2558aa5b387
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1319769240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.1319769240
Directory	/workspace/36.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/36.lc_ctrl_state_failure.561757013
Short name	T778
Test name
Test status
Simulation time	308927380 ps
CPU time	30.16 seconds
Started	Jul 01 06:46:48 PM PDT 24
Finished	Jul 01 06:47:21 PM PDT 24
Peak memory	251412 kb
Host	smart-0f23eebf-7d0c-4220-adc5-1f8a50749afd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=561757013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.561757013
Directory	/workspace/36.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/36.lc_ctrl_state_post_trans.1804895406
Short name	T30
Test name
Test status
Simulation time	77262961 ps
CPU time	8.25 seconds
Started	Jul 01 06:46:45 PM PDT 24
Finished	Jul 01 06:46:57 PM PDT 24
Peak memory	251344 kb
Host	smart-e33e81a1-23e3-4337-8bb3-e226ce813251
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1804895406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.1804895406
Directory	/workspace/36.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/36.lc_ctrl_stress_all.2565212543
Short name	T586
Test name
Test status
Simulation time	546216035 ps
CPU time	6.23 seconds
Started	Jul 01 06:46:47 PM PDT 24
Finished	Jul 01 06:46:56 PM PDT 24
Peak memory	225128 kb
Host	smart-aeef48c6-2148-4ae4-ba59-7dc05cd1ef82
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565212543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all.2565212543
Directory	/workspace/36.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.3094672578
Short name	T85
Test name
Test status
Simulation time	14058248 ps
CPU time	1.11 seconds
Started	Jul 01 06:46:51 PM PDT 24
Finished	Jul 01 06:46:54 PM PDT 24
Peak memory	212324 kb
Host	smart-5ff08b8c-c5cc-497c-853d-e2f06be5b277
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094672578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c trl_volatile_unlock_smoke.3094672578
Directory	/workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/37.lc_ctrl_alert_test.1099448236
Short name	T168
Test name
Test status
Simulation time	31655591 ps
CPU time	1.41 seconds
Started	Jul 01 06:46:52 PM PDT 24
Finished	Jul 01 06:46:55 PM PDT 24
Peak memory	209468 kb
Host	smart-9aea81ea-f2b9-403a-80c3-45960213b91d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099448236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.1099448236
Directory	/workspace/37.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/37.lc_ctrl_errors.3823486887
Short name	T286
Test name
Test status
Simulation time	1190525739 ps
CPU time	9.36 seconds
Started	Jul 01 06:47:01 PM PDT 24
Finished	Jul 01 06:47:13 PM PDT 24
Peak memory	226576 kb
Host	smart-0de40aa2-6ad3-4c6f-8ea1-dc84c5a06e1c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3823486887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.3823486887
Directory	/workspace/37.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/37.lc_ctrl_jtag_access.1745839990
Short name	T8
Test name
Test status
Simulation time	3059881238 ps
CPU time	5.52 seconds
Started	Jul 01 06:46:53 PM PDT 24
Finished	Jul 01 06:47:00 PM PDT 24
Peak memory	218204 kb
Host	smart-9167b51d-2393-4b83-af26-e5a7672d9687
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745839990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.1745839990
Directory	/workspace/37.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/37.lc_ctrl_prog_failure.2194590190
Short name	T598
Test name
Test status
Simulation time	130429403 ps
CPU time	2.23 seconds
Started	Jul 01 06:46:55 PM PDT 24
Finished	Jul 01 06:47:00 PM PDT 24
Peak memory	222812 kb
Host	smart-749a0d87-d7eb-4742-abc5-1030af82dc49
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2194590190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.2194590190
Directory	/workspace/37.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/37.lc_ctrl_sec_mubi.3973551414
Short name	T689
Test name
Test status
Simulation time	1348067866 ps
CPU time	10.34 seconds
Started	Jul 01 06:46:55 PM PDT 24
Finished	Jul 01 06:47:08 PM PDT 24
Peak memory	226448 kb
Host	smart-1f8c0595-8982-4218-a805-a278acd0c2f5
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973551414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.3973551414
Directory	/workspace/37.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/37.lc_ctrl_sec_token_digest.3105213229
Short name	T743
Test name
Test status
Simulation time	308282719 ps
CPU time	12.52 seconds
Started	Jul 01 06:46:54 PM PDT 24
Finished	Jul 01 06:47:09 PM PDT 24
Peak memory	218624 kb
Host	smart-56ac743c-dbe1-4cbd-a9bb-3b8d3aeacbfe
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105213229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d igest.3105213229
Directory	/workspace/37.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/37.lc_ctrl_sec_token_mux.1351763458
Short name	T394
Test name
Test status
Simulation time	625852410 ps
CPU time	10.16 seconds
Started	Jul 01 06:46:53 PM PDT 24
Finished	Jul 01 06:47:05 PM PDT 24
Peak memory	218660 kb
Host	smart-fb626083-1976-4f89-979c-4eb7104b7161
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351763458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux. 1351763458
Directory	/workspace/37.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/37.lc_ctrl_security_escalation.4232976555
Short name	T749
Test name
Test status
Simulation time	2729812843 ps
CPU time	7.61 seconds
Started	Jul 01 06:46:55 PM PDT 24
Finished	Jul 01 06:47:05 PM PDT 24
Peak memory	226020 kb
Host	smart-702419ba-06e7-4875-a917-fa4eec8c4e76
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4232976555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.4232976555
Directory	/workspace/37.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/37.lc_ctrl_smoke.4072056730
Short name	T688
Test name
Test status
Simulation time	87008045 ps
CPU time	2.2 seconds
Started	Jul 01 06:46:46 PM PDT 24
Finished	Jul 01 06:46:52 PM PDT 24
Peak memory	214868 kb
Host	smart-60db04ec-df90-469e-81f5-e31458cdabcc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4072056730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.4072056730
Directory	/workspace/37.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/37.lc_ctrl_state_failure.3363805208
Short name	T772
Test name
Test status
Simulation time	198738043 ps
CPU time	16.41 seconds
Started	Jul 01 06:46:47 PM PDT 24
Finished	Jul 01 06:47:07 PM PDT 24
Peak memory	251416 kb
Host	smart-eac91a02-2116-4abf-a8c2-d3124d24f942
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3363805208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.3363805208
Directory	/workspace/37.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/37.lc_ctrl_state_post_trans.1455284405
Short name	T684
Test name
Test status
Simulation time	150239917 ps
CPU time	7.72 seconds
Started	Jul 01 06:46:45 PM PDT 24
Finished	Jul 01 06:46:56 PM PDT 24
Peak memory	244140 kb
Host	smart-214f843e-86f9-4635-be34-2c452a18162d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1455284405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.1455284405
Directory	/workspace/37.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/37.lc_ctrl_stress_all.1130059848
Short name	T29
Test name
Test status
Simulation time	170836284 ps
CPU time	5.37 seconds
Started	Jul 01 06:46:55 PM PDT 24
Finished	Jul 01 06:47:03 PM PDT 24
Peak memory	218408 kb
Host	smart-04f29856-9798-4d3b-902e-77fbf97a32a5
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130059848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all.1130059848
Directory	/workspace/37.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.4172084189
Short name	T170
Test name
Test status
Simulation time	135270035980 ps
CPU time	290.71 seconds
Started	Jul 01 06:46:59 PM PDT 24
Finished	Jul 01 06:51:51 PM PDT 24
Peak memory	268104 kb
Host	smart-e688065b-30f0-4672-938b-43e6870fac16
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=4172084189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.4172084189
Directory	/workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.1336928553
Short name	T535
Test name
Test status
Simulation time	62313145 ps
CPU time	0.87 seconds
Started	Jul 01 06:46:46 PM PDT 24
Finished	Jul 01 06:46:50 PM PDT 24
Peak memory	209408 kb
Host	smart-558c7313-ad9a-4496-a92f-638767c7d7c0
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336928553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c trl_volatile_unlock_smoke.1336928553
Directory	/workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/38.lc_ctrl_alert_test.2589937699
Short name	T555
Test name
Test status
Simulation time	25851102 ps
CPU time	0.97 seconds
Started	Jul 01 06:46:55 PM PDT 24
Finished	Jul 01 06:46:59 PM PDT 24
Peak memory	209200 kb
Host	smart-df50f381-f1bb-4346-a888-1cb3f1bbfafa
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589937699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.2589937699
Directory	/workspace/38.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/38.lc_ctrl_errors.679852042
Short name	T768
Test name
Test status
Simulation time	1094770034 ps
CPU time	12.46 seconds
Started	Jul 01 06:46:53 PM PDT 24
Finished	Jul 01 06:47:08 PM PDT 24
Peak memory	218568 kb
Host	smart-30eaaf2d-fc8d-4746-94d7-73f6206db26f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=679852042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.679852042
Directory	/workspace/38.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/38.lc_ctrl_jtag_access.1892921984
Short name	T372
Test name
Test status
Simulation time	1341332379 ps
CPU time	8.17 seconds
Started	Jul 01 06:46:52 PM PDT 24
Finished	Jul 01 06:47:02 PM PDT 24
Peak memory	217552 kb
Host	smart-95dd3a3e-a24e-486f-a791-b06b9a4813d1
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892921984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.1892921984
Directory	/workspace/38.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/38.lc_ctrl_prog_failure.3865359882
Short name	T303
Test name
Test status
Simulation time	154262984 ps
CPU time	3.18 seconds
Started	Jul 01 06:46:59 PM PDT 24
Finished	Jul 01 06:47:02 PM PDT 24
Peak memory	218660 kb
Host	smart-668f8843-87d4-4ef4-8098-2871647b8c3c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3865359882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.3865359882
Directory	/workspace/38.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/38.lc_ctrl_sec_mubi.3418560576
Short name	T426
Test name
Test status
Simulation time	1363123746 ps
CPU time	16.3 seconds
Started	Jul 01 06:46:56 PM PDT 24
Finished	Jul 01 06:47:15 PM PDT 24
Peak memory	226572 kb
Host	smart-7d7d15c7-6d28-4ee7-902d-a9a51a53a7ec
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418560576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.3418560576
Directory	/workspace/38.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/38.lc_ctrl_sec_token_digest.303779767
Short name	T368
Test name
Test status
Simulation time	1748606784 ps
CPU time	15.88 seconds
Started	Jul 01 06:46:54 PM PDT 24
Finished	Jul 01 06:47:13 PM PDT 24
Peak memory	218680 kb
Host	smart-b4a2d46b-df0c-4276-9dc6-f0cfee0fb9a3
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303779767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_di gest.303779767
Directory	/workspace/38.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/38.lc_ctrl_sec_token_mux.829831599
Short name	T645
Test name
Test status
Simulation time	791802510 ps
CPU time	25.56 seconds
Started	Jul 01 06:46:53 PM PDT 24
Finished	Jul 01 06:47:21 PM PDT 24
Peak memory	218588 kb
Host	smart-58dda938-0810-4275-8832-838a610addbf
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829831599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.829831599
Directory	/workspace/38.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/38.lc_ctrl_security_escalation.2826589748
Short name	T305
Test name
Test status
Simulation time	1271753252 ps
CPU time	12.43 seconds
Started	Jul 01 06:46:55 PM PDT 24
Finished	Jul 01 06:47:10 PM PDT 24
Peak memory	226436 kb
Host	smart-14ee101b-ae64-434f-b399-8011c0ff458c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2826589748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.2826589748
Directory	/workspace/38.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/38.lc_ctrl_smoke.2146430666
Short name	T227
Test name
Test status
Simulation time	67240690 ps
CPU time	2.31 seconds
Started	Jul 01 06:46:54 PM PDT 24
Finished	Jul 01 06:46:59 PM PDT 24
Peak memory	218192 kb
Host	smart-2e27b97d-1f0e-4783-979d-56191b364d8e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2146430666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.2146430666
Directory	/workspace/38.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/38.lc_ctrl_state_failure.1272204472
Short name	T780
Test name
Test status
Simulation time	166330235 ps
CPU time	15.91 seconds
Started	Jul 01 06:46:54 PM PDT 24
Finished	Jul 01 06:47:12 PM PDT 24
Peak memory	245112 kb
Host	smart-c80792c9-7044-4ab3-8417-2f41ba672ce3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1272204472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.1272204472
Directory	/workspace/38.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/38.lc_ctrl_state_post_trans.1832530155
Short name	T589
Test name
Test status
Simulation time	98575339 ps
CPU time	6.24 seconds
Started	Jul 01 06:46:54 PM PDT 24
Finished	Jul 01 06:47:03 PM PDT 24
Peak memory	246672 kb
Host	smart-0c9b5a47-ab85-4d10-b455-d084b5ea02a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1832530155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.1832530155
Directory	/workspace/38.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/38.lc_ctrl_stress_all.2982457125
Short name	T41
Test name
Test status
Simulation time	18893255494 ps
CPU time	198.11 seconds
Started	Jul 01 06:47:01 PM PDT 24
Finished	Jul 01 06:50:21 PM PDT 24
Peak memory	272784 kb
Host	smart-90e6546d-d81b-4d54-ba67-ee8a464f9438
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982457125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all.2982457125
Directory	/workspace/38.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.364403591
Short name	T588
Test name
Test status
Simulation time	13031849 ps
CPU time	0.96 seconds
Started	Jul 01 06:46:53 PM PDT 24
Finished	Jul 01 06:46:56 PM PDT 24
Peak memory	209328 kb
Host	smart-ed1b081e-72e8-4619-9211-9117f4e96268
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364403591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ct rl_volatile_unlock_smoke.364403591
Directory	/workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/39.lc_ctrl_alert_test.4219936401
Short name	T461
Test name
Test status
Simulation time	49359261 ps
CPU time	1.08 seconds
Started	Jul 01 06:46:54 PM PDT 24
Finished	Jul 01 06:46:58 PM PDT 24
Peak memory	209532 kb
Host	smart-6cf06c43-800c-4556-91f9-5687a7ad9872
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219936401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.4219936401
Directory	/workspace/39.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/39.lc_ctrl_errors.2051648573
Short name	T538
Test name
Test status
Simulation time	469138740 ps
CPU time	6.81 seconds
Started	Jul 01 06:46:55 PM PDT 24
Finished	Jul 01 06:47:05 PM PDT 24
Peak memory	218760 kb
Host	smart-0003c3c1-1776-457b-a9e6-22a8f5f77a68
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2051648573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.2051648573
Directory	/workspace/39.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/39.lc_ctrl_jtag_access.919164508
Short name	T543
Test name
Test status
Simulation time	168333879 ps
CPU time	4.73 seconds
Started	Jul 01 06:46:53 PM PDT 24
Finished	Jul 01 06:47:00 PM PDT 24
Peak memory	217460 kb
Host	smart-279d9983-2feb-4833-b5a6-05ea4407b2d0
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919164508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.919164508
Directory	/workspace/39.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/39.lc_ctrl_prog_failure.347234899
Short name	T234
Test name
Test status
Simulation time	19586559 ps
CPU time	1.8 seconds
Started	Jul 01 06:46:52 PM PDT 24
Finished	Jul 01 06:46:56 PM PDT 24
Peak memory	222428 kb
Host	smart-2dc768fe-629f-4962-ab20-a5143533f5f0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=347234899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.347234899
Directory	/workspace/39.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/39.lc_ctrl_sec_mubi.4089956400
Short name	T871
Test name
Test status
Simulation time	2352564458 ps
CPU time	25.9 seconds
Started	Jul 01 06:46:56 PM PDT 24
Finished	Jul 01 06:47:24 PM PDT 24
Peak memory	220596 kb
Host	smart-0e1a9539-8e6a-4449-ab29-74d9b0a4c6ff
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089956400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.4089956400
Directory	/workspace/39.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/39.lc_ctrl_sec_token_digest.2401736898
Short name	T423
Test name
Test status
Simulation time	466380877 ps
CPU time	7.64 seconds
Started	Jul 01 06:46:55 PM PDT 24
Finished	Jul 01 06:47:05 PM PDT 24
Peak memory	218612 kb
Host	smart-f5da7895-35b5-42ab-85a5-0cbe2d30eae2
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401736898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d igest.2401736898
Directory	/workspace/39.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/39.lc_ctrl_sec_token_mux.3517315762
Short name	T68
Test name
Test status
Simulation time	281289291 ps
CPU time	10.8 seconds
Started	Jul 01 06:47:00 PM PDT 24
Finished	Jul 01 06:47:12 PM PDT 24
Peak memory	218708 kb
Host	smart-0c35b2ec-d03b-406f-9926-1db1cde3186c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517315762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux. 3517315762
Directory	/workspace/39.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/39.lc_ctrl_security_escalation.3877577280
Short name	T745
Test name
Test status
Simulation time	1240792145 ps
CPU time	10.03 seconds
Started	Jul 01 06:46:55 PM PDT 24
Finished	Jul 01 06:47:07 PM PDT 24
Peak memory	218844 kb
Host	smart-1ecd6783-8b05-4eaa-85a7-c599ec8b18e9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3877577280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.3877577280
Directory	/workspace/39.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/39.lc_ctrl_smoke.908164563
Short name	T854
Test name
Test status
Simulation time	147804115 ps
CPU time	2.24 seconds
Started	Jul 01 06:46:53 PM PDT 24
Finished	Jul 01 06:46:57 PM PDT 24
Peak memory	218072 kb
Host	smart-64e77420-a736-4023-b7b5-37e1cbb67411
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=908164563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.908164563
Directory	/workspace/39.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/39.lc_ctrl_state_failure.4084145912
Short name	T505
Test name
Test status
Simulation time	532169642 ps
CPU time	33.22 seconds
Started	Jul 01 06:46:55 PM PDT 24
Finished	Jul 01 06:47:31 PM PDT 24
Peak memory	251436 kb
Host	smart-e9777362-4b19-4ae6-a2bd-a2d3fa101cf0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4084145912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.4084145912
Directory	/workspace/39.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/39.lc_ctrl_state_post_trans.4020816922
Short name	T741
Test name
Test status
Simulation time	94948457 ps
CPU time	6.86 seconds
Started	Jul 01 06:46:59 PM PDT 24
Finished	Jul 01 06:47:06 PM PDT 24
Peak memory	247340 kb
Host	smart-0626a5f7-d8ed-4239-b5d0-0f1949f1ef34
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4020816922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.4020816922
Directory	/workspace/39.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/39.lc_ctrl_stress_all.2716671643
Short name	T860
Test name
Test status
Simulation time	211921134 ps
CPU time	10.6 seconds
Started	Jul 01 06:46:56 PM PDT 24
Finished	Jul 01 06:47:09 PM PDT 24
Peak memory	251612 kb
Host	smart-1ac16539-48cf-4833-baea-9bc0d3b2390e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716671643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all.2716671643
Directory	/workspace/39.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.2429704404
Short name	T169
Test name
Test status
Simulation time	159791083430 ps
CPU time	1877.31 seconds
Started	Jul 01 06:46:53 PM PDT 24
Finished	Jul 01 07:18:12 PM PDT 24
Peak memory	954408 kb
Host	smart-ad19a6dc-395a-4b71-b5d8-f36c48317035
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2429704404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.2429704404
Directory	/workspace/39.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.1703622726
Short name	T843
Test name
Test status
Simulation time	183872490 ps
CPU time	0.97 seconds
Started	Jul 01 06:47:01 PM PDT 24
Finished	Jul 01 06:47:04 PM PDT 24
Peak memory	212396 kb
Host	smart-2c59b0a7-5c55-4622-a9f9-d5a09e6acbaf
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703622726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c trl_volatile_unlock_smoke.1703622726
Directory	/workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/4.lc_ctrl_alert_test.2505331452
Short name	T595
Test name
Test status
Simulation time	19854340 ps
CPU time	0.96 seconds
Started	Jul 01 06:44:11 PM PDT 24
Finished	Jul 01 06:44:15 PM PDT 24
Peak memory	209524 kb
Host	smart-3509bca8-012b-4977-ae76-6d4d4f0b6667
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505331452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.2505331452
Directory	/workspace/4.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/4.lc_ctrl_claim_transition_if.1545526907
Short name	T617
Test name
Test status
Simulation time	11378425 ps
CPU time	0.82 seconds
Started	Jul 01 06:44:09 PM PDT 24
Finished	Jul 01 06:44:12 PM PDT 24
Peak memory	209164 kb
Host	smart-d1afa69d-2b1e-4c56-9ec0-75545295ebb9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1545526907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.1545526907
Directory	/workspace/4.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/4.lc_ctrl_errors.2260358918
Short name	T573
Test name
Test status
Simulation time	390436159 ps
CPU time	17.37 seconds
Started	Jul 01 06:44:12 PM PDT 24
Finished	Jul 01 06:44:31 PM PDT 24
Peak memory	226508 kb
Host	smart-4333b806-c922-4226-908b-53cdeebc551d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2260358918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.2260358918
Directory	/workspace/4.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_access.773651296
Short name	T619
Test name
Test status
Simulation time	112333012 ps
CPU time	1.09 seconds
Started	Jul 01 06:44:09 PM PDT 24
Finished	Jul 01 06:44:12 PM PDT 24
Peak memory	217468 kb
Host	smart-6a2e482e-f676-46c6-9e8d-3d228242e454
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773651296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.773651296
Directory	/workspace/4.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_errors.2026462103
Short name	T271
Test name
Test status
Simulation time	6867077186 ps
CPU time	49.31 seconds
Started	Jul 01 06:44:12 PM PDT 24
Finished	Jul 01 06:45:03 PM PDT 24
Peak memory	219432 kb
Host	smart-0541f44c-afa1-4064-8772-c1824ff6894a
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026462103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er rors.2026462103
Directory	/workspace/4.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_priority.17848509
Short name	T187
Test name
Test status
Simulation time	894156623 ps
CPU time	10.45 seconds
Started	Jul 01 06:44:10 PM PDT 24
Finished	Jul 01 06:44:24 PM PDT 24
Peak memory	217952 kb
Host	smart-936c0d4f-d96b-406f-851b-54974e290a33
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17848509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.17848509
Directory	/workspace/4.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.3239974166
Short name	T416
Test name
Test status
Simulation time	453956045 ps
CPU time	7.26 seconds
Started	Jul 01 06:44:10 PM PDT 24
Finished	Jul 01 06:44:20 PM PDT 24
Peak memory	218576 kb
Host	smart-2c1b86a6-f034-41f2-bdb9-15a77efd3a2b
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239974166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag _prog_failure.3239974166
Directory	/workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.1726066872
Short name	T236
Test name
Test status
Simulation time	1594099785 ps
CPU time	12.58 seconds
Started	Jul 01 06:44:10 PM PDT 24
Finished	Jul 01 06:44:25 PM PDT 24
Peak memory	218108 kb
Host	smart-faec97c6-565c-487d-a9e0-5671a22a68d7
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726066872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_ jtag_regwen_during_op.1726066872
Directory	/workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_smoke.2433899593
Short name	T620
Test name
Test status
Simulation time	137812542 ps
CPU time	4.66 seconds
Started	Jul 01 06:44:08 PM PDT 24
Finished	Jul 01 06:44:15 PM PDT 24
Peak memory	218100 kb
Host	smart-1f6a9d39-2d87-443f-bdca-6783e5156b6e
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433899593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke. 2433899593
Directory	/workspace/4.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_state_failure.3351160727
Short name	T350
Test name
Test status
Simulation time	1323660505 ps
CPU time	41.26 seconds
Started	Jul 01 06:44:11 PM PDT 24
Finished	Jul 01 06:44:55 PM PDT 24
Peak memory	276136 kb
Host	smart-1448888f-8034-4a6d-86a1-c77be2e920d2
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351160727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta g_state_failure.3351160727
Directory	/workspace/4.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.4022518843
Short name	T565
Test name
Test status
Simulation time	2720958322 ps
CPU time	9.94 seconds
Started	Jul 01 06:44:14 PM PDT 24
Finished	Jul 01 06:44:26 PM PDT 24
Peak memory	226700 kb
Host	smart-190e824b-e61e-4adf-8b74-729c2c0daff2
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022518843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_ jtag_state_post_trans.4022518843
Directory	/workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/4.lc_ctrl_prog_failure.664178843
Short name	T660
Test name
Test status
Simulation time	125437654 ps
CPU time	2.83 seconds
Started	Jul 01 06:44:16 PM PDT 24
Finished	Jul 01 06:44:21 PM PDT 24
Peak memory	223200 kb
Host	smart-b22e1df7-ee42-4e51-b446-a84a4234ea0f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=664178843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.664178843
Directory	/workspace/4.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/4.lc_ctrl_regwen_during_op.3845307495
Short name	T722
Test name
Test status
Simulation time	428330102 ps
CPU time	16.78 seconds
Started	Jul 01 06:44:09 PM PDT 24
Finished	Jul 01 06:44:29 PM PDT 24
Peak memory	218236 kb
Host	smart-1b0a9e67-1f20-4211-ac10-e957d860017b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3845307495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.3845307495
Directory	/workspace/4.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/4.lc_ctrl_sec_cm.487019828
Short name	T59
Test name
Test status
Simulation time	1160435340 ps
CPU time	35.23 seconds
Started	Jul 01 06:44:10 PM PDT 24
Finished	Jul 01 06:44:48 PM PDT 24
Peak memory	269952 kb
Host	smart-5a5e49fe-649e-415f-982a-90f825bef195
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487019828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.487019828
Directory	/workspace/4.lc_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/4.lc_ctrl_sec_mubi.2349303376
Short name	T670
Test name
Test status
Simulation time	412585633 ps
CPU time	19.49 seconds
Started	Jul 01 06:44:09 PM PDT 24
Finished	Jul 01 06:44:31 PM PDT 24
Peak memory	226604 kb
Host	smart-83df7b23-7416-4006-8258-3978edbdcbbe
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349303376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.2349303376
Directory	/workspace/4.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/4.lc_ctrl_sec_token_digest.672681967
Short name	T228
Test name
Test status
Simulation time	1709724896 ps
CPU time	8.28 seconds
Started	Jul 01 06:44:10 PM PDT 24
Finished	Jul 01 06:44:21 PM PDT 24
Peak memory	218720 kb
Host	smart-ae200495-be76-4ef4-9708-fb7ee47038a5
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672681967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_dig est.672681967
Directory	/workspace/4.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/4.lc_ctrl_sec_token_mux.3867030288
Short name	T320
Test name
Test status
Simulation time	1222975103 ps
CPU time	9.33 seconds
Started	Jul 01 06:44:10 PM PDT 24
Finished	Jul 01 06:44:22 PM PDT 24
Peak memory	218584 kb
Host	smart-714a03b5-4023-45b3-9bf1-8fd71ef94e46
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867030288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.3 867030288
Directory	/workspace/4.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/4.lc_ctrl_security_escalation.98218655
Short name	T759
Test name
Test status
Simulation time	940620835 ps
CPU time	10.94 seconds
Started	Jul 01 06:44:11 PM PDT 24
Finished	Jul 01 06:44:25 PM PDT 24
Peak memory	226528 kb
Host	smart-02cd7e14-2236-44aa-829e-b5c1aa84db4e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=98218655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.98218655
Directory	/workspace/4.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/4.lc_ctrl_smoke.4231077098
Short name	T114
Test name
Test status
Simulation time	83929148 ps
CPU time	2.63 seconds
Started	Jul 01 06:44:10 PM PDT 24
Finished	Jul 01 06:44:15 PM PDT 24
Peak memory	214800 kb
Host	smart-48b72361-cbdf-40ac-8aee-20831788b60a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4231077098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.4231077098
Directory	/workspace/4.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/4.lc_ctrl_state_failure.1409090664
Short name	T397
Test name
Test status
Simulation time	5194763481 ps
CPU time	29.57 seconds
Started	Jul 01 06:44:09 PM PDT 24
Finished	Jul 01 06:44:41 PM PDT 24
Peak memory	251516 kb
Host	smart-e9c2c474-7d73-445d-8065-e9a84219726c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1409090664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.1409090664
Directory	/workspace/4.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/4.lc_ctrl_state_post_trans.2628213018
Short name	T817
Test name
Test status
Simulation time	217944931 ps
CPU time	7.95 seconds
Started	Jul 01 06:44:09 PM PDT 24
Finished	Jul 01 06:44:20 PM PDT 24
Peak memory	251408 kb
Host	smart-4e9957e9-50c5-42b6-997a-6b50fd7bba73
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2628213018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.2628213018
Directory	/workspace/4.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/4.lc_ctrl_stress_all.1048625879
Short name	T54
Test name
Test status
Simulation time	3141656378 ps
CPU time	62.17 seconds
Started	Jul 01 06:44:09 PM PDT 24
Finished	Jul 01 06:45:14 PM PDT 24
Peak memory	250760 kb
Host	smart-a6f16c49-a04f-478c-ab89-ab166e8e6514
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048625879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all.1048625879
Directory	/workspace/4.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.3065014072
Short name	T712
Test name
Test status
Simulation time	33823944666 ps
CPU time	226.34 seconds
Started	Jul 01 06:44:09 PM PDT 24
Finished	Jul 01 06:47:58 PM PDT 24
Peak memory	422288 kb
Host	smart-146e35ca-de65-4eb2-b6a4-cc4788e1268d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3065014072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.3065014072
Directory	/workspace/4.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.2504724543
Short name	T667
Test name
Test status
Simulation time	22514234 ps
CPU time	0.9 seconds
Started	Jul 01 06:44:10 PM PDT 24
Finished	Jul 01 06:44:14 PM PDT 24
Peak memory	212192 kb
Host	smart-9e780de4-ca90-4172-a373-1675d57f2a7b
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504724543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct rl_volatile_unlock_smoke.2504724543
Directory	/workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/40.lc_ctrl_alert_test.1483741248
Short name	T341
Test name
Test status
Simulation time	19144445 ps
CPU time	1.17 seconds
Started	Jul 01 06:47:03 PM PDT 24
Finished	Jul 01 06:47:06 PM PDT 24
Peak memory	209516 kb
Host	smart-870b64d0-2017-4123-9f00-ce5755336be8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483741248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.1483741248
Directory	/workspace/40.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/40.lc_ctrl_errors.3355899342
Short name	T391
Test name
Test status
Simulation time	2651995201 ps
CPU time	9.43 seconds
Started	Jul 01 06:47:01 PM PDT 24
Finished	Jul 01 06:47:13 PM PDT 24
Peak memory	219364 kb
Host	smart-1aff303f-6412-4f7e-9ff2-34f35373d1d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3355899342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.3355899342
Directory	/workspace/40.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/40.lc_ctrl_jtag_access.1765067369
Short name	T22
Test name
Test status
Simulation time	1914450067 ps
CPU time	11.82 seconds
Started	Jul 01 06:47:03 PM PDT 24
Finished	Jul 01 06:47:17 PM PDT 24
Peak memory	217460 kb
Host	smart-6060726f-c3ac-4b27-be65-2fd914e195e9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765067369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.1765067369
Directory	/workspace/40.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/40.lc_ctrl_prog_failure.1154630835
Short name	T838
Test name
Test status
Simulation time	64569035 ps
CPU time	2.74 seconds
Started	Jul 01 06:47:02 PM PDT 24
Finished	Jul 01 06:47:07 PM PDT 24
Peak memory	218684 kb
Host	smart-e62320b0-1631-4cbe-963d-959560530314
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1154630835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.1154630835
Directory	/workspace/40.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/40.lc_ctrl_sec_mubi.3428944363
Short name	T308
Test name
Test status
Simulation time	2320106880 ps
CPU time	22.36 seconds
Started	Jul 01 06:47:01 PM PDT 24
Finished	Jul 01 06:47:26 PM PDT 24
Peak memory	226532 kb
Host	smart-e09380b9-a33e-4270-a841-ef1f63e3e431
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428944363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.3428944363
Directory	/workspace/40.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/40.lc_ctrl_sec_token_digest.2334117282
Short name	T398
Test name
Test status
Simulation time	767001213 ps
CPU time	15.8 seconds
Started	Jul 01 06:47:02 PM PDT 24
Finished	Jul 01 06:47:20 PM PDT 24
Peak memory	218664 kb
Host	smart-ada7e26c-b8a3-412b-bf2c-693c2550e109
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334117282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d igest.2334117282
Directory	/workspace/40.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/40.lc_ctrl_sec_token_mux.3650775406
Short name	T396
Test name
Test status
Simulation time	1219472597 ps
CPU time	10.92 seconds
Started	Jul 01 06:47:02 PM PDT 24
Finished	Jul 01 06:47:16 PM PDT 24
Peak memory	218540 kb
Host	smart-09e60a09-a104-4f32-9637-f2a5b62b4a44
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650775406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux. 3650775406
Directory	/workspace/40.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/40.lc_ctrl_security_escalation.1594662119
Short name	T388
Test name
Test status
Simulation time	455788445 ps
CPU time	13.46 seconds
Started	Jul 01 06:46:59 PM PDT 24
Finished	Jul 01 06:47:14 PM PDT 24
Peak memory	225888 kb
Host	smart-3d86b23f-1ac7-43e3-b911-9491867704dd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1594662119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.1594662119
Directory	/workspace/40.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/40.lc_ctrl_smoke.4120947030
Short name	T810
Test name
Test status
Simulation time	118777468 ps
CPU time	3.95 seconds
Started	Jul 01 06:46:55 PM PDT 24
Finished	Jul 01 06:47:02 PM PDT 24
Peak memory	218148 kb
Host	smart-685d1cd9-32a2-4634-bd8f-244e85981b82
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4120947030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.4120947030
Directory	/workspace/40.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/40.lc_ctrl_state_failure.2400704227
Short name	T868
Test name
Test status
Simulation time	185969515 ps
CPU time	21.28 seconds
Started	Jul 01 06:47:01 PM PDT 24
Finished	Jul 01 06:47:25 PM PDT 24
Peak memory	251376 kb
Host	smart-29567afc-fcaa-478e-a931-b5b3570fabf4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2400704227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.2400704227
Directory	/workspace/40.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/40.lc_ctrl_state_post_trans.1329003353
Short name	T686
Test name
Test status
Simulation time	49942747 ps
CPU time	7.27 seconds
Started	Jul 01 06:47:02 PM PDT 24
Finished	Jul 01 06:47:11 PM PDT 24
Peak memory	251400 kb
Host	smart-a7ca5466-3b0c-4903-8610-40c36fac1f67
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1329003353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.1329003353
Directory	/workspace/40.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/40.lc_ctrl_stress_all.457270923
Short name	T365
Test name
Test status
Simulation time	5909473715 ps
CPU time	264.56 seconds
Started	Jul 01 06:47:03 PM PDT 24
Finished	Jul 01 06:51:30 PM PDT 24
Peak memory	251520 kb
Host	smart-1a2437fb-5aba-46b2-a342-afbe1030584f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457270923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all.457270923
Directory	/workspace/40.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.1317922098
Short name	T161
Test name
Test status
Simulation time	18432250659 ps
CPU time	437.91 seconds
Started	Jul 01 06:47:02 PM PDT 24
Finished	Jul 01 06:54:22 PM PDT 24
Peak memory	300672 kb
Host	smart-e7f82676-8319-4077-85a0-e4b7224a9af0
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1317922098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all_with_rand_reset.1317922098
Directory	/workspace/40.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.2740649663
Short name	T623
Test name
Test status
Simulation time	34737931 ps
CPU time	0.82 seconds
Started	Jul 01 06:47:01 PM PDT 24
Finished	Jul 01 06:47:03 PM PDT 24
Peak memory	209176 kb
Host	smart-2a4b495e-8c83-4f0b-a717-fed3e1aaef92
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740649663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c trl_volatile_unlock_smoke.2740649663
Directory	/workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/41.lc_ctrl_errors.2829881789
Short name	T107
Test name
Test status
Simulation time	2329328687 ps
CPU time	16.89 seconds
Started	Jul 01 06:47:01 PM PDT 24
Finished	Jul 01 06:47:20 PM PDT 24
Peak memory	226512 kb
Host	smart-f0fd1198-1d9b-402f-84e1-b226436f75dd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2829881789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.2829881789
Directory	/workspace/41.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/41.lc_ctrl_prog_failure.888707007
Short name	T334
Test name
Test status
Simulation time	148343998 ps
CPU time	2.27 seconds
Started	Jul 01 06:46:59 PM PDT 24
Finished	Jul 01 06:47:03 PM PDT 24
Peak memory	222744 kb
Host	smart-dd9d405a-3a79-453c-bd24-0f04a255d59c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=888707007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.888707007
Directory	/workspace/41.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/41.lc_ctrl_sec_mubi.2527487211
Short name	T470
Test name
Test status
Simulation time	1262318651 ps
CPU time	8.94 seconds
Started	Jul 01 06:47:00 PM PDT 24
Finished	Jul 01 06:47:10 PM PDT 24
Peak memory	226188 kb
Host	smart-f0922485-5177-4274-825f-7dad0af10b9a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527487211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.2527487211
Directory	/workspace/41.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/41.lc_ctrl_sec_token_digest.2617899425
Short name	T272
Test name
Test status
Simulation time	433551036 ps
CPU time	8.62 seconds
Started	Jul 01 06:46:59 PM PDT 24
Finished	Jul 01 06:47:09 PM PDT 24
Peak memory	218760 kb
Host	smart-1f0df4eb-907c-488c-83dc-7cf5970985fa
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617899425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d igest.2617899425
Directory	/workspace/41.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/41.lc_ctrl_security_escalation.9344854
Short name	T346
Test name
Test status
Simulation time	2324162560 ps
CPU time	16.42 seconds
Started	Jul 01 06:47:02 PM PDT 24
Finished	Jul 01 06:47:21 PM PDT 24
Peak memory	226520 kb
Host	smart-49ec8cbb-539f-4d6a-a9e4-cabb2fdacb06
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=9344854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.9344854
Directory	/workspace/41.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/41.lc_ctrl_smoke.3110215256
Short name	T109
Test name
Test status
Simulation time	247278011 ps
CPU time	5.89 seconds
Started	Jul 01 06:47:01 PM PDT 24
Finished	Jul 01 06:47:09 PM PDT 24
Peak memory	218048 kb
Host	smart-4476a8eb-fb19-4756-a987-a130891cc3d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3110215256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.3110215256
Directory	/workspace/41.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/41.lc_ctrl_state_failure.1450040704
Short name	T643
Test name
Test status
Simulation time	301872765 ps
CPU time	24.95 seconds
Started	Jul 01 06:47:04 PM PDT 24
Finished	Jul 01 06:47:31 PM PDT 24
Peak memory	251320 kb
Host	smart-14565514-6d9b-45f7-a576-d88141c0fd58
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1450040704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.1450040704
Directory	/workspace/41.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/41.lc_ctrl_state_post_trans.2438115510
Short name	T839
Test name
Test status
Simulation time	90131440 ps
CPU time	7.91 seconds
Started	Jul 01 06:47:01 PM PDT 24
Finished	Jul 01 06:47:10 PM PDT 24
Peak memory	250908 kb
Host	smart-02cd41fc-48cc-41ba-8b09-dd4b71b611a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2438115510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.2438115510
Directory	/workspace/41.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/41.lc_ctrl_stress_all.3055450724
Short name	T658
Test name
Test status
Simulation time	3516335386 ps
CPU time	105.57 seconds
Started	Jul 01 06:47:01 PM PDT 24
Finished	Jul 01 06:48:49 PM PDT 24
Peak memory	251048 kb
Host	smart-8f6603bb-4a18-4ad5-ab3c-d73ab71edee8
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055450724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all.3055450724
Directory	/workspace/41.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.1796439536
Short name	T222
Test name
Test status
Simulation time	36328480 ps
CPU time	0.81 seconds
Started	Jul 01 06:47:00 PM PDT 24
Finished	Jul 01 06:47:01 PM PDT 24
Peak memory	208560 kb
Host	smart-bb23b1f4-1ed7-4690-bdd8-c68ba70a32d2
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796439536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c trl_volatile_unlock_smoke.1796439536
Directory	/workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/42.lc_ctrl_alert_test.1843259179
Short name	T707
Test name
Test status
Simulation time	72436323 ps
CPU time	0.93 seconds
Started	Jul 01 06:47:09 PM PDT 24
Finished	Jul 01 06:47:11 PM PDT 24
Peak memory	209460 kb
Host	smart-580a007a-b13b-45af-b59c-53f9181c72d7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843259179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.1843259179
Directory	/workspace/42.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/42.lc_ctrl_errors.1302906156
Short name	T861
Test name
Test status
Simulation time	2789044103 ps
CPU time	14.28 seconds
Started	Jul 01 06:47:10 PM PDT 24
Finished	Jul 01 06:47:30 PM PDT 24
Peak memory	226496 kb
Host	smart-e0f1c287-1a2c-4df6-ae10-9ca13dcb6bf1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1302906156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.1302906156
Directory	/workspace/42.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/42.lc_ctrl_jtag_access.161735457
Short name	T166
Test name
Test status
Simulation time	86777412 ps
CPU time	1.18 seconds
Started	Jul 01 06:47:15 PM PDT 24
Finished	Jul 01 06:47:20 PM PDT 24
Peak memory	217352 kb
Host	smart-4f5c81ab-8564-432e-8f10-865da6852ac4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161735457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.161735457
Directory	/workspace/42.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/42.lc_ctrl_prog_failure.4072890737
Short name	T578
Test name
Test status
Simulation time	93086488 ps
CPU time	4.33 seconds
Started	Jul 01 06:47:15 PM PDT 24
Finished	Jul 01 06:47:23 PM PDT 24
Peak memory	218692 kb
Host	smart-2ada7901-4505-4d73-8ef8-944ad6991852
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4072890737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.4072890737
Directory	/workspace/42.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/42.lc_ctrl_sec_mubi.3308879662
Short name	T377
Test name
Test status
Simulation time	400145489 ps
CPU time	13.98 seconds
Started	Jul 01 06:47:10 PM PDT 24
Finished	Jul 01 06:47:30 PM PDT 24
Peak memory	226452 kb
Host	smart-cad1efbb-eb28-4cfd-ae48-1d5c238046b9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308879662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.3308879662
Directory	/workspace/42.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/42.lc_ctrl_sec_token_digest.411879878
Short name	T469
Test name
Test status
Simulation time	1200920161 ps
CPU time	11.64 seconds
Started	Jul 01 06:47:10 PM PDT 24
Finished	Jul 01 06:47:29 PM PDT 24
Peak memory	218568 kb
Host	smart-a0a33249-4a27-43de-9179-05cb3d859b06
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411879878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_di gest.411879878
Directory	/workspace/42.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/42.lc_ctrl_sec_token_mux.3548940805
Short name	T419
Test name
Test status
Simulation time	380584951 ps
CPU time	8.86 seconds
Started	Jul 01 06:47:12 PM PDT 24
Finished	Jul 01 06:47:26 PM PDT 24
Peak memory	218640 kb
Host	smart-e3e6ef63-d3f0-4ecf-a34c-0c783199d279
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548940805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux. 3548940805
Directory	/workspace/42.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/42.lc_ctrl_security_escalation.3232191357
Short name	T735
Test name
Test status
Simulation time	252103125 ps
CPU time	9.62 seconds
Started	Jul 01 06:47:14 PM PDT 24
Finished	Jul 01 06:47:28 PM PDT 24
Peak memory	225748 kb
Host	smart-66ee19f0-005f-4242-add0-86d4aadf7e30
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3232191357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.3232191357
Directory	/workspace/42.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/42.lc_ctrl_smoke.382217916
Short name	T77
Test name
Test status
Simulation time	19317945 ps
CPU time	0.97 seconds
Started	Jul 01 06:47:02 PM PDT 24
Finished	Jul 01 06:47:06 PM PDT 24
Peak memory	209468 kb
Host	smart-a6f94483-3cd9-4f57-97ec-d5b005609363
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=382217916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.382217916
Directory	/workspace/42.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/42.lc_ctrl_state_failure.2465524197
Short name	T425
Test name
Test status
Simulation time	609630588 ps
CPU time	29.62 seconds
Started	Jul 01 06:47:13 PM PDT 24
Finished	Jul 01 06:47:48 PM PDT 24
Peak memory	251344 kb
Host	smart-ea1c73ca-ac7d-4673-be62-a4ae5ba0b5b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2465524197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.2465524197
Directory	/workspace/42.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/42.lc_ctrl_state_post_trans.1629334827
Short name	T703
Test name
Test status
Simulation time	93074627 ps
CPU time	8.5 seconds
Started	Jul 01 06:47:10 PM PDT 24
Finished	Jul 01 06:47:24 PM PDT 24
Peak memory	251324 kb
Host	smart-cf391f38-736c-406e-ad39-24cb3cb1d184
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1629334827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.1629334827
Directory	/workspace/42.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/42.lc_ctrl_stress_all.857763169
Short name	T682
Test name
Test status
Simulation time	7835132613 ps
CPU time	122.13 seconds
Started	Jul 01 06:47:13 PM PDT 24
Finished	Jul 01 06:49:20 PM PDT 24
Peak memory	283180 kb
Host	smart-06fe87ad-cbbe-4cab-a81c-532d73b3c1f7
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857763169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all.857763169
Directory	/workspace/42.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.2823059875
Short name	T104
Test name
Test status
Simulation time	13934662 ps
CPU time	1.02 seconds
Started	Jul 01 06:47:11 PM PDT 24
Finished	Jul 01 06:47:18 PM PDT 24
Peak memory	209428 kb
Host	smart-fa8a289d-caae-4b97-89e4-8c3decf28f6b
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823059875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c trl_volatile_unlock_smoke.2823059875
Directory	/workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/43.lc_ctrl_alert_test.3317144065
Short name	T462
Test name
Test status
Simulation time	25024621 ps
CPU time	1.28 seconds
Started	Jul 01 06:47:08 PM PDT 24
Finished	Jul 01 06:47:10 PM PDT 24
Peak memory	209556 kb
Host	smart-c3c98258-3476-4cb7-858d-d567974796f1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317144065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.3317144065
Directory	/workspace/43.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/43.lc_ctrl_errors.1093986284
Short name	T478
Test name
Test status
Simulation time	2650196078 ps
CPU time	15.68 seconds
Started	Jul 01 06:47:10 PM PDT 24
Finished	Jul 01 06:47:32 PM PDT 24
Peak memory	218780 kb
Host	smart-1f917d9f-c107-4f1c-bc81-42053acad6c1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1093986284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.1093986284
Directory	/workspace/43.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/43.lc_ctrl_jtag_access.247923029
Short name	T24
Test name
Test status
Simulation time	1468454351 ps
CPU time	10.28 seconds
Started	Jul 01 06:47:11 PM PDT 24
Finished	Jul 01 06:47:28 PM PDT 24
Peak memory	217672 kb
Host	smart-2d2357da-d24a-495f-9337-f562373a9a99
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247923029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.247923029
Directory	/workspace/43.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/43.lc_ctrl_prog_failure.1526768367
Short name	T748
Test name
Test status
Simulation time	508004151 ps
CPU time	2.41 seconds
Started	Jul 01 06:47:13 PM PDT 24
Finished	Jul 01 06:47:20 PM PDT 24
Peak memory	218584 kb
Host	smart-cb1cdb4a-a39a-4f1e-beab-49515b3e056b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1526768367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.1526768367
Directory	/workspace/43.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/43.lc_ctrl_sec_mubi.2906866571
Short name	T834
Test name
Test status
Simulation time	252290767 ps
CPU time	9.6 seconds
Started	Jul 01 06:47:08 PM PDT 24
Finished	Jul 01 06:47:19 PM PDT 24
Peak memory	226452 kb
Host	smart-27022524-6a0c-49f0-93db-95072a41f161
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906866571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.2906866571
Directory	/workspace/43.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/43.lc_ctrl_sec_token_digest.1282586371
Short name	T581
Test name
Test status
Simulation time	1359954844 ps
CPU time	15.51 seconds
Started	Jul 01 06:47:15 PM PDT 24
Finished	Jul 01 06:47:34 PM PDT 24
Peak memory	218664 kb
Host	smart-3078eb78-a400-442b-9b70-77ca0e0e3a7e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282586371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d igest.1282586371
Directory	/workspace/43.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/43.lc_ctrl_sec_token_mux.540335721
Short name	T696
Test name
Test status
Simulation time	3408248622 ps
CPU time	15.52 seconds
Started	Jul 01 06:47:10 PM PDT 24
Finished	Jul 01 06:47:31 PM PDT 24
Peak memory	226440 kb
Host	smart-423d6f06-cbf7-461e-9205-75c2cf3e5479
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540335721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.540335721
Directory	/workspace/43.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/43.lc_ctrl_security_escalation.2053912285
Short name	T313
Test name
Test status
Simulation time	1878852374 ps
CPU time	9.4 seconds
Started	Jul 01 06:47:09 PM PDT 24
Finished	Jul 01 06:47:21 PM PDT 24
Peak memory	225408 kb
Host	smart-a0ed8e88-d22a-4c3b-b36c-8704787824db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2053912285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.2053912285
Directory	/workspace/43.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/43.lc_ctrl_smoke.777412553
Short name	T337
Test name
Test status
Simulation time	109211391 ps
CPU time	3.87 seconds
Started	Jul 01 06:47:08 PM PDT 24
Finished	Jul 01 06:47:12 PM PDT 24
Peak memory	218140 kb
Host	smart-c21a75be-74eb-4bec-9c42-0cc98da11971
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=777412553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.777412553
Directory	/workspace/43.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/43.lc_ctrl_state_failure.1013881232
Short name	T408
Test name
Test status
Simulation time	256089684 ps
CPU time	24.97 seconds
Started	Jul 01 06:47:12 PM PDT 24
Finished	Jul 01 06:47:42 PM PDT 24
Peak memory	251448 kb
Host	smart-4a2f7d13-aa73-422e-8c99-45162e1d1eaf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1013881232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.1013881232
Directory	/workspace/43.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/43.lc_ctrl_state_post_trans.3358053343
Short name	T738
Test name
Test status
Simulation time	804436855 ps
CPU time	9.37 seconds
Started	Jul 01 06:47:11 PM PDT 24
Finished	Jul 01 06:47:27 PM PDT 24
Peak memory	251420 kb
Host	smart-bc9d760a-af21-4f1d-adac-ac056802a2e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3358053343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.3358053343
Directory	/workspace/43.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/43.lc_ctrl_stress_all.2457623100
Short name	T438
Test name
Test status
Simulation time	20333548308 ps
CPU time	45.82 seconds
Started	Jul 01 06:47:11 PM PDT 24
Finished	Jul 01 06:48:03 PM PDT 24
Peak memory	271868 kb
Host	smart-2bab6061-2a7e-4a9b-8348-650d661de5f6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457623100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all.2457623100
Directory	/workspace/43.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.3190502688
Short name	T121
Test name
Test status
Simulation time	16389235865 ps
CPU time	288.44 seconds
Started	Jul 01 06:47:14 PM PDT 24
Finished	Jul 01 06:52:07 PM PDT 24
Peak memory	317024 kb
Host	smart-da61ad26-8aa7-43fe-832d-4b1cee8ab1bb
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3190502688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.3190502688
Directory	/workspace/43.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.1617080449
Short name	T530
Test name
Test status
Simulation time	47244415 ps
CPU time	0.88 seconds
Started	Jul 01 06:47:10 PM PDT 24
Finished	Jul 01 06:47:18 PM PDT 24
Peak memory	212412 kb
Host	smart-46429768-ad4e-427f-a67a-08c794b58ff2
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617080449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c trl_volatile_unlock_smoke.1617080449
Directory	/workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/44.lc_ctrl_alert_test.3211883407
Short name	T80
Test name
Test status
Simulation time	17596235 ps
CPU time	1.19 seconds
Started	Jul 01 06:47:19 PM PDT 24
Finished	Jul 01 06:47:23 PM PDT 24
Peak memory	209332 kb
Host	smart-1920d23b-5913-4d15-a41d-ea919c2fbbc5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211883407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.3211883407
Directory	/workspace/44.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/44.lc_ctrl_errors.361938205
Short name	T523
Test name
Test status
Simulation time	290614465 ps
CPU time	13.98 seconds
Started	Jul 01 06:47:22 PM PDT 24
Finished	Jul 01 06:47:37 PM PDT 24
Peak memory	226456 kb
Host	smart-22ea034d-000c-4537-9894-3098fa43cb92
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=361938205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.361938205
Directory	/workspace/44.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/44.lc_ctrl_jtag_access.1168008760
Short name	T870
Test name
Test status
Simulation time	604470909 ps
CPU time	8.16 seconds
Started	Jul 01 06:47:18 PM PDT 24
Finished	Jul 01 06:47:29 PM PDT 24
Peak memory	217680 kb
Host	smart-62f998ba-fa0d-428d-b3da-8ac6dca49f3e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168008760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.1168008760
Directory	/workspace/44.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/44.lc_ctrl_prog_failure.729572514
Short name	T858
Test name
Test status
Simulation time	19546087 ps
CPU time	1.64 seconds
Started	Jul 01 06:47:19 PM PDT 24
Finished	Jul 01 06:47:23 PM PDT 24
Peak memory	218620 kb
Host	smart-b1bfc424-76c7-49d0-8b3d-f9e875dc803f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=729572514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.729572514
Directory	/workspace/44.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/44.lc_ctrl_sec_mubi.2332693954
Short name	T668
Test name
Test status
Simulation time	294703070 ps
CPU time	12.87 seconds
Started	Jul 01 06:47:18 PM PDT 24
Finished	Jul 01 06:47:33 PM PDT 24
Peak memory	226456 kb
Host	smart-2bc7ce58-d075-4c7c-81a2-3ff21edc10ec
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332693954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.2332693954
Directory	/workspace/44.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/44.lc_ctrl_sec_token_digest.2425289607
Short name	T597
Test name
Test status
Simulation time	480997123 ps
CPU time	11.35 seconds
Started	Jul 01 06:47:19 PM PDT 24
Finished	Jul 01 06:47:33 PM PDT 24
Peak memory	218608 kb
Host	smart-470429fc-5e43-4521-9271-a2497739c4ef
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425289607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d igest.2425289607
Directory	/workspace/44.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/44.lc_ctrl_sec_token_mux.158035217
Short name	T179
Test name
Test status
Simulation time	684973228 ps
CPU time	12.15 seconds
Started	Jul 01 06:47:22 PM PDT 24
Finished	Jul 01 06:47:36 PM PDT 24
Peak memory	218576 kb
Host	smart-d063148a-1e02-4fc6-babc-e2f7d43a3f46
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158035217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.158035217
Directory	/workspace/44.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/44.lc_ctrl_security_escalation.2075860890
Short name	T326
Test name
Test status
Simulation time	276186429 ps
CPU time	10.88 seconds
Started	Jul 01 06:47:18 PM PDT 24
Finished	Jul 01 06:47:31 PM PDT 24
Peak memory	218772 kb
Host	smart-1ba64b2a-0c44-4f15-8d06-aafc1f167cf5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2075860890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.2075860890
Directory	/workspace/44.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/44.lc_ctrl_smoke.1535118835
Short name	T402
Test name
Test status
Simulation time	35979553 ps
CPU time	1.48 seconds
Started	Jul 01 06:47:09 PM PDT 24
Finished	Jul 01 06:47:16 PM PDT 24
Peak memory	214232 kb
Host	smart-26424e75-876f-4726-9a28-dd6c00926fb2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1535118835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.1535118835
Directory	/workspace/44.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/44.lc_ctrl_state_failure.3636729511
Short name	T263
Test name
Test status
Simulation time	370009656 ps
CPU time	39.85 seconds
Started	Jul 01 06:47:13 PM PDT 24
Finished	Jul 01 06:47:58 PM PDT 24
Peak memory	251332 kb
Host	smart-55d1801b-ae84-409d-8236-43b74e60207e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3636729511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.3636729511
Directory	/workspace/44.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/44.lc_ctrl_state_post_trans.3137217889
Short name	T528
Test name
Test status
Simulation time	211008861 ps
CPU time	7.73 seconds
Started	Jul 01 06:47:17 PM PDT 24
Finished	Jul 01 06:47:27 PM PDT 24
Peak memory	251256 kb
Host	smart-d8a156ec-4d93-4ecb-800a-4be67862f22c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3137217889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.3137217889
Directory	/workspace/44.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/44.lc_ctrl_stress_all.997257290
Short name	T90
Test name
Test status
Simulation time	2982216855 ps
CPU time	17.99 seconds
Started	Jul 01 06:47:25 PM PDT 24
Finished	Jul 01 06:47:44 PM PDT 24
Peak memory	226516 kb
Host	smart-06a9329e-aef3-4129-89d0-808cd3110c4b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997257290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all.997257290
Directory	/workspace/44.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.2914457080
Short name	T363
Test name
Test status
Simulation time	72392251 ps
CPU time	0.82 seconds
Started	Jul 01 06:47:15 PM PDT 24
Finished	Jul 01 06:47:20 PM PDT 24
Peak memory	212216 kb
Host	smart-322993cf-58cd-45c6-9e2d-27ba184acee4
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914457080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c trl_volatile_unlock_smoke.2914457080
Directory	/workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/45.lc_ctrl_alert_test.1015408019
Short name	T283
Test name
Test status
Simulation time	57933276 ps
CPU time	0.86 seconds
Started	Jul 01 06:47:23 PM PDT 24
Finished	Jul 01 06:47:25 PM PDT 24
Peak memory	209376 kb
Host	smart-1f290a18-2767-4a8f-81c5-2fcd96eb451b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015408019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.1015408019
Directory	/workspace/45.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/45.lc_ctrl_errors.1764175672
Short name	T446
Test name
Test status
Simulation time	1288808307 ps
CPU time	14.65 seconds
Started	Jul 01 06:47:17 PM PDT 24
Finished	Jul 01 06:47:35 PM PDT 24
Peak memory	218640 kb
Host	smart-f3c2891d-0629-4c9c-b9de-501885b98765
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1764175672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.1764175672
Directory	/workspace/45.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/45.lc_ctrl_jtag_access.1202106487
Short name	T709
Test name
Test status
Simulation time	2166784832 ps
CPU time	5.77 seconds
Started	Jul 01 06:47:17 PM PDT 24
Finished	Jul 01 06:47:25 PM PDT 24
Peak memory	217500 kb
Host	smart-e56087be-ec39-45db-9d9d-527fba69a532
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202106487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.1202106487
Directory	/workspace/45.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/45.lc_ctrl_prog_failure.2686926969
Short name	T503
Test name
Test status
Simulation time	79312145 ps
CPU time	2.28 seconds
Started	Jul 01 06:47:18 PM PDT 24
Finished	Jul 01 06:47:23 PM PDT 24
Peak memory	218644 kb
Host	smart-b96ca265-e828-4163-af2b-7126ed0cf924
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2686926969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.2686926969
Directory	/workspace/45.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/45.lc_ctrl_sec_mubi.4187196472
Short name	T506
Test name
Test status
Simulation time	1657514044 ps
CPU time	16.45 seconds
Started	Jul 01 06:47:18 PM PDT 24
Finished	Jul 01 06:47:37 PM PDT 24
Peak memory	226556 kb
Host	smart-b0e8f097-6af3-44dc-b9ab-82d22920f48d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187196472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.4187196472
Directory	/workspace/45.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/45.lc_ctrl_sec_token_digest.3180510799
Short name	T591
Test name
Test status
Simulation time	2238768445 ps
CPU time	10.19 seconds
Started	Jul 01 06:47:17 PM PDT 24
Finished	Jul 01 06:47:30 PM PDT 24
Peak memory	218732 kb
Host	smart-7de43d1d-d625-47b7-a8b3-c866802afc89
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180510799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d igest.3180510799
Directory	/workspace/45.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/45.lc_ctrl_sec_token_mux.4043222789
Short name	T364
Test name
Test status
Simulation time	623091088 ps
CPU time	8.16 seconds
Started	Jul 01 06:47:20 PM PDT 24
Finished	Jul 01 06:47:30 PM PDT 24
Peak memory	218664 kb
Host	smart-5ea0a18b-6bcb-45ea-a0ab-26a704416824
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043222789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux. 4043222789
Directory	/workspace/45.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/45.lc_ctrl_security_escalation.2741441216
Short name	T764
Test name
Test status
Simulation time	264231409 ps
CPU time	7.2 seconds
Started	Jul 01 06:47:24 PM PDT 24
Finished	Jul 01 06:47:32 PM PDT 24
Peak memory	226448 kb
Host	smart-70bc9c76-da8b-45f2-8415-8ce90b5bc814
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2741441216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.2741441216
Directory	/workspace/45.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/45.lc_ctrl_smoke.677866157
Short name	T640
Test name
Test status
Simulation time	46716120 ps
CPU time	3.05 seconds
Started	Jul 01 06:47:18 PM PDT 24
Finished	Jul 01 06:47:24 PM PDT 24
Peak memory	214916 kb
Host	smart-db8aeb81-3ca0-44ed-97c1-57cbdfaf4fd9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=677866157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.677866157
Directory	/workspace/45.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/45.lc_ctrl_state_failure.135190102
Short name	T497
Test name
Test status
Simulation time	254507773 ps
CPU time	23.14 seconds
Started	Jul 01 06:47:18 PM PDT 24
Finished	Jul 01 06:47:44 PM PDT 24
Peak memory	251352 kb
Host	smart-2a1ab269-35ce-445d-98ac-f1aab4667505
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=135190102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.135190102
Directory	/workspace/45.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/45.lc_ctrl_state_post_trans.526037502
Short name	T641
Test name
Test status
Simulation time	468812645 ps
CPU time	7.13 seconds
Started	Jul 01 06:47:20 PM PDT 24
Finished	Jul 01 06:47:29 PM PDT 24
Peak memory	247684 kb
Host	smart-8ed2c294-4c62-4057-90f2-122f0258ea03
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=526037502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.526037502
Directory	/workspace/45.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/45.lc_ctrl_stress_all.4184372428
Short name	T770
Test name
Test status
Simulation time	3622096233 ps
CPU time	156.11 seconds
Started	Jul 01 06:47:24 PM PDT 24
Finished	Jul 01 06:50:01 PM PDT 24
Peak memory	267768 kb
Host	smart-eff74c7b-8ffc-4895-a8f5-26d8a08f5e1b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184372428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all.4184372428
Directory	/workspace/45.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.3246317693
Short name	T33
Test name
Test status
Simulation time	42996967 ps
CPU time	1.08 seconds
Started	Jul 01 06:47:19 PM PDT 24
Finished	Jul 01 06:47:22 PM PDT 24
Peak memory	212404 kb
Host	smart-1144abc2-c7f9-4bbe-a66b-8aea8102527a
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246317693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c trl_volatile_unlock_smoke.3246317693
Directory	/workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/46.lc_ctrl_alert_test.3961553790
Short name	T661
Test name
Test status
Simulation time	55680687 ps
CPU time	1.01 seconds
Started	Jul 01 06:47:25 PM PDT 24
Finished	Jul 01 06:47:27 PM PDT 24
Peak memory	209448 kb
Host	smart-f936a545-296d-4827-bfc1-f820c166014c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961553790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.3961553790
Directory	/workspace/46.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/46.lc_ctrl_errors.1804014224
Short name	T429
Test name
Test status
Simulation time	2240687902 ps
CPU time	15.53 seconds
Started	Jul 01 06:47:20 PM PDT 24
Finished	Jul 01 06:47:38 PM PDT 24
Peak memory	226644 kb
Host	smart-aa51a881-e17f-486a-9408-96019e902b84
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1804014224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.1804014224
Directory	/workspace/46.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/46.lc_ctrl_jtag_access.267748990
Short name	T343
Test name
Test status
Simulation time	3113858147 ps
CPU time	7.55 seconds
Started	Jul 01 06:47:17 PM PDT 24
Finished	Jul 01 06:47:27 PM PDT 24
Peak memory	217952 kb
Host	smart-ce43458e-cb26-46e9-9243-2f12165a8693
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267748990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.267748990
Directory	/workspace/46.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/46.lc_ctrl_prog_failure.3772779890
Short name	T493
Test name
Test status
Simulation time	43292466 ps
CPU time	2.3 seconds
Started	Jul 01 06:47:19 PM PDT 24
Finished	Jul 01 06:47:24 PM PDT 24
Peak memory	218656 kb
Host	smart-69eefc67-c8b4-4a6c-800f-4f41d744c7d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3772779890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.3772779890
Directory	/workspace/46.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/46.lc_ctrl_sec_mubi.1314026771
Short name	T330
Test name
Test status
Simulation time	687087311 ps
CPU time	11.83 seconds
Started	Jul 01 06:47:17 PM PDT 24
Finished	Jul 01 06:47:32 PM PDT 24
Peak memory	219148 kb
Host	smart-481e3031-b9c4-4379-a15e-55f9a310afd8
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314026771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.1314026771
Directory	/workspace/46.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/46.lc_ctrl_sec_token_digest.601468690
Short name	T823
Test name
Test status
Simulation time	532432288 ps
CPU time	13.73 seconds
Started	Jul 01 06:47:28 PM PDT 24
Finished	Jul 01 06:47:46 PM PDT 24
Peak memory	218628 kb
Host	smart-8f76f515-a6ce-4d37-91d0-daddb75a50eb
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601468690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_di gest.601468690
Directory	/workspace/46.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/46.lc_ctrl_sec_token_mux.986030018
Short name	T599
Test name
Test status
Simulation time	1571317958 ps
CPU time	17.23 seconds
Started	Jul 01 06:47:30 PM PDT 24
Finished	Jul 01 06:47:50 PM PDT 24
Peak memory	218580 kb
Host	smart-cffab9cc-919c-4e89-ba5d-8539b18af8f8
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986030018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.986030018
Directory	/workspace/46.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/46.lc_ctrl_security_escalation.3566133626
Short name	T832
Test name
Test status
Simulation time	1674134766 ps
CPU time	10.22 seconds
Started	Jul 01 06:47:24 PM PDT 24
Finished	Jul 01 06:47:36 PM PDT 24
Peak memory	226444 kb
Host	smart-b466f959-bc36-4b77-9871-6977d236483e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3566133626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.3566133626
Directory	/workspace/46.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/46.lc_ctrl_smoke.1392691205
Short name	T357
Test name
Test status
Simulation time	32392891 ps
CPU time	1.62 seconds
Started	Jul 01 06:47:23 PM PDT 24
Finished	Jul 01 06:47:25 PM PDT 24
Peak memory	218072 kb
Host	smart-26fe1a7f-1a88-4aa0-abbf-8f23e685ac5d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1392691205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.1392691205
Directory	/workspace/46.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/46.lc_ctrl_state_failure.1445256490
Short name	T453
Test name
Test status
Simulation time	605864619 ps
CPU time	21.83 seconds
Started	Jul 01 06:47:21 PM PDT 24
Finished	Jul 01 06:47:44 PM PDT 24
Peak memory	248040 kb
Host	smart-c863a531-55cf-48c0-9b9d-d072b5e3b45e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1445256490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.1445256490
Directory	/workspace/46.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/46.lc_ctrl_state_post_trans.3150317637
Short name	T70
Test name
Test status
Simulation time	1971171141 ps
CPU time	11.34 seconds
Started	Jul 01 06:47:20 PM PDT 24
Finished	Jul 01 06:47:33 PM PDT 24
Peak memory	251336 kb
Host	smart-c4c1537a-95b1-4565-87c1-8bfc75b3f20d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3150317637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.3150317637
Directory	/workspace/46.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/46.lc_ctrl_stress_all.1993292704
Short name	T96
Test name
Test status
Simulation time	3134107596 ps
CPU time	88.74 seconds
Started	Jul 01 06:47:28 PM PDT 24
Finished	Jul 01 06:48:59 PM PDT 24
Peak memory	278088 kb
Host	smart-2d59fef8-3467-4fbc-a761-43945e73bc57
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993292704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all.1993292704
Directory	/workspace/46.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.2444905643
Short name	T663
Test name
Test status
Simulation time	42973063 ps
CPU time	0.94 seconds
Started	Jul 01 06:47:20 PM PDT 24
Finished	Jul 01 06:47:23 PM PDT 24
Peak memory	209284 kb
Host	smart-67512eec-82bd-4f65-8ab3-36d2b643888e
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444905643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c trl_volatile_unlock_smoke.2444905643
Directory	/workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/47.lc_ctrl_alert_test.3050884007
Short name	T105
Test name
Test status
Simulation time	193578389 ps
CPU time	1.03 seconds
Started	Jul 01 06:47:28 PM PDT 24
Finished	Jul 01 06:47:32 PM PDT 24
Peak memory	209360 kb
Host	smart-db5d5d18-ebf5-48c6-9d63-0e9a92508ff6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050884007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.3050884007
Directory	/workspace/47.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/47.lc_ctrl_errors.2213680642
Short name	T375
Test name
Test status
Simulation time	588656723 ps
CPU time	11.68 seconds
Started	Jul 01 06:47:32 PM PDT 24
Finished	Jul 01 06:47:46 PM PDT 24
Peak memory	226588 kb
Host	smart-b4bfa190-c2cf-44c5-8a62-116f8c6a660b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2213680642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.2213680642
Directory	/workspace/47.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/47.lc_ctrl_jtag_access.4258058595
Short name	T460
Test name
Test status
Simulation time	13992755019 ps
CPU time	20.1 seconds
Started	Jul 01 06:47:27 PM PDT 24
Finished	Jul 01 06:47:50 PM PDT 24
Peak memory	218192 kb
Host	smart-d592cd14-b01f-47e6-b84b-c391f72fcade
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258058595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.4258058595
Directory	/workspace/47.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/47.lc_ctrl_prog_failure.2264310459
Short name	T767
Test name
Test status
Simulation time	195454697 ps
CPU time	3.23 seconds
Started	Jul 01 06:47:32 PM PDT 24
Finished	Jul 01 06:47:38 PM PDT 24
Peak memory	218768 kb
Host	smart-6a3ef27d-3854-4a1a-b628-58f5991b9b9a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2264310459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.2264310459
Directory	/workspace/47.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/47.lc_ctrl_sec_mubi.1263504748
Short name	T483
Test name
Test status
Simulation time	200333067 ps
CPU time	10.18 seconds
Started	Jul 01 06:47:26 PM PDT 24
Finished	Jul 01 06:47:38 PM PDT 24
Peak memory	218732 kb
Host	smart-492763d4-376b-4552-9db2-b6be52263c27
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263504748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.1263504748
Directory	/workspace/47.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/47.lc_ctrl_sec_token_digest.2339848616
Short name	T602
Test name
Test status
Simulation time	219765353 ps
CPU time	8.56 seconds
Started	Jul 01 06:47:26 PM PDT 24
Finished	Jul 01 06:47:36 PM PDT 24
Peak memory	218684 kb
Host	smart-6b82fe71-5b97-4c8d-8f3e-9f748cb1b823
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339848616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d igest.2339848616
Directory	/workspace/47.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/47.lc_ctrl_sec_token_mux.4033421078
Short name	T582
Test name
Test status
Simulation time	555451950 ps
CPU time	9.52 seconds
Started	Jul 01 06:47:30 PM PDT 24
Finished	Jul 01 06:47:43 PM PDT 24
Peak memory	218640 kb
Host	smart-bd2c9e69-4341-4718-8b38-38e3926576b1
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033421078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux. 4033421078
Directory	/workspace/47.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/47.lc_ctrl_security_escalation.1300720133
Short name	T605
Test name
Test status
Simulation time	1178447059 ps
CPU time	7.77 seconds
Started	Jul 01 06:47:28 PM PDT 24
Finished	Jul 01 06:47:39 PM PDT 24
Peak memory	226436 kb
Host	smart-64554973-76d5-4f93-b4c4-6d47008df2c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1300720133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.1300720133
Directory	/workspace/47.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/47.lc_ctrl_smoke.508715177
Short name	T292
Test name
Test status
Simulation time	182181596 ps
CPU time	2.58 seconds
Started	Jul 01 06:47:28 PM PDT 24
Finished	Jul 01 06:47:35 PM PDT 24
Peak memory	218260 kb
Host	smart-dad5d0b2-3834-4e8a-b659-d74cc04be2c1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=508715177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.508715177
Directory	/workspace/47.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/47.lc_ctrl_state_failure.3310379342
Short name	T312
Test name
Test status
Simulation time	289026787 ps
CPU time	26.99 seconds
Started	Jul 01 06:47:27 PM PDT 24
Finished	Jul 01 06:47:57 PM PDT 24
Peak memory	245956 kb
Host	smart-d51d5841-42a8-43d9-b80e-bb900fd3c539
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3310379342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.3310379342
Directory	/workspace/47.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/47.lc_ctrl_state_post_trans.3241416078
Short name	T699
Test name
Test status
Simulation time	633662559 ps
CPU time	6.21 seconds
Started	Jul 01 06:47:28 PM PDT 24
Finished	Jul 01 06:47:38 PM PDT 24
Peak memory	243132 kb
Host	smart-fec0a637-1d36-40f5-807c-f4b72f72cf34
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3241416078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.3241416078
Directory	/workspace/47.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/47.lc_ctrl_stress_all.3831537300
Short name	T630
Test name
Test status
Simulation time	47838315845 ps
CPU time	190.15 seconds
Started	Jul 01 06:47:26 PM PDT 24
Finished	Jul 01 06:50:38 PM PDT 24
Peak memory	279208 kb
Host	smart-98914e9f-02a7-43b4-912d-a348b646a9be
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831537300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all.3831537300
Directory	/workspace/47.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.3265678428
Short name	T715
Test name
Test status
Simulation time	53777945 ps
CPU time	0.93 seconds
Started	Jul 01 06:47:28 PM PDT 24
Finished	Jul 01 06:47:31 PM PDT 24
Peak memory	212308 kb
Host	smart-f9f18877-82a2-421a-b371-4e744d01667e
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265678428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c trl_volatile_unlock_smoke.3265678428
Directory	/workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/48.lc_ctrl_alert_test.1231227799
Short name	T633
Test name
Test status
Simulation time	85727839 ps
CPU time	1.24 seconds
Started	Jul 01 06:47:30 PM PDT 24
Finished	Jul 01 06:47:34 PM PDT 24
Peak memory	209528 kb
Host	smart-7528db1f-7d13-4bdd-bc2d-2ce6692c4179
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231227799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.1231227799
Directory	/workspace/48.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/48.lc_ctrl_errors.3795195620
Short name	T291
Test name
Test status
Simulation time	1567161137 ps
CPU time	17.14 seconds
Started	Jul 01 06:47:32 PM PDT 24
Finished	Jul 01 06:47:51 PM PDT 24
Peak memory	218776 kb
Host	smart-860532f7-686b-45ca-97fc-340dd2342ce4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3795195620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.3795195620
Directory	/workspace/48.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/48.lc_ctrl_jtag_access.1555572239
Short name	T288
Test name
Test status
Simulation time	635689134 ps
CPU time	1.96 seconds
Started	Jul 01 06:47:28 PM PDT 24
Finished	Jul 01 06:47:34 PM PDT 24
Peak memory	217416 kb
Host	smart-c39b1f2f-8852-4fe9-b35d-9f33b4f0e9f4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555572239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.1555572239
Directory	/workspace/48.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/48.lc_ctrl_prog_failure.3982586876
Short name	T340
Test name
Test status
Simulation time	18970695 ps
CPU time	1.63 seconds
Started	Jul 01 06:47:30 PM PDT 24
Finished	Jul 01 06:47:34 PM PDT 24
Peak memory	218708 kb
Host	smart-0296b142-ea3f-44dc-9e34-a4b04b58bf2e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3982586876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.3982586876
Directory	/workspace/48.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/48.lc_ctrl_sec_mubi.3260183839
Short name	T747
Test name
Test status
Simulation time	361122937 ps
CPU time	15.9 seconds
Started	Jul 01 06:47:32 PM PDT 24
Finished	Jul 01 06:47:51 PM PDT 24
Peak memory	220444 kb
Host	smart-51665d66-1c54-4b13-b122-f9f4abe6537d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260183839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.3260183839
Directory	/workspace/48.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/48.lc_ctrl_sec_token_digest.1871305092
Short name	T174
Test name
Test status
Simulation time	2817366271 ps
CPU time	17.62 seconds
Started	Jul 01 06:47:28 PM PDT 24
Finished	Jul 01 06:47:48 PM PDT 24
Peak memory	219300 kb
Host	smart-f7790e36-5329-46fc-a73b-12de92ac6978
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871305092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d igest.1871305092
Directory	/workspace/48.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/48.lc_ctrl_sec_token_mux.1626298308
Short name	T500
Test name
Test status
Simulation time	443707784 ps
CPU time	6.03 seconds
Started	Jul 01 06:47:30 PM PDT 24
Finished	Jul 01 06:47:39 PM PDT 24
Peak memory	224956 kb
Host	smart-ca525084-8366-47b5-9d94-153dd5743f86
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626298308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux. 1626298308
Directory	/workspace/48.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/48.lc_ctrl_security_escalation.712615189
Short name	T389
Test name
Test status
Simulation time	176747615 ps
CPU time	5.87 seconds
Started	Jul 01 06:47:28 PM PDT 24
Finished	Jul 01 06:47:38 PM PDT 24
Peak memory	225124 kb
Host	smart-5704f9d4-54b2-45e2-a30b-58120617b20f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=712615189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.712615189
Directory	/workspace/48.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/48.lc_ctrl_smoke.3229510874
Short name	T72
Test name
Test status
Simulation time	208860164 ps
CPU time	2.4 seconds
Started	Jul 01 06:47:26 PM PDT 24
Finished	Jul 01 06:47:30 PM PDT 24
Peak memory	215116 kb
Host	smart-63555854-a1a7-4301-976f-d8e98cdf76b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3229510874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.3229510874
Directory	/workspace/48.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/48.lc_ctrl_state_failure.1303633930
Short name	T452
Test name
Test status
Simulation time	1839454540 ps
CPU time	23.31 seconds
Started	Jul 01 06:47:30 PM PDT 24
Finished	Jul 01 06:47:56 PM PDT 24
Peak memory	251384 kb
Host	smart-ef5cf3c1-b816-42ab-be23-52c57aaaefa8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1303633930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.1303633930
Directory	/workspace/48.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/48.lc_ctrl_state_post_trans.2855760020
Short name	T704
Test name
Test status
Simulation time	102680985 ps
CPU time	9.62 seconds
Started	Jul 01 06:47:29 PM PDT 24
Finished	Jul 01 06:47:42 PM PDT 24
Peak memory	251416 kb
Host	smart-671dea19-4f2f-4e7b-8cf5-9e4adda9a84f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2855760020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.2855760020
Directory	/workspace/48.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/48.lc_ctrl_stress_all.734177886
Short name	T247
Test name
Test status
Simulation time	14872599229 ps
CPU time	58.59 seconds
Started	Jul 01 06:47:28 PM PDT 24
Finished	Jul 01 06:48:31 PM PDT 24
Peak memory	251476 kb
Host	smart-a31a8499-4e1c-4cde-8be1-c622e30997c0
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734177886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all.734177886
Directory	/workspace/48.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.890524101
Short name	T613
Test name
Test status
Simulation time	74475485 ps
CPU time	0.94 seconds
Started	Jul 01 06:47:26 PM PDT 24
Finished	Jul 01 06:47:29 PM PDT 24
Peak memory	212192 kb
Host	smart-28d28ee3-8f7b-4242-9c82-9eb9284935a1
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890524101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ct rl_volatile_unlock_smoke.890524101
Directory	/workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/49.lc_ctrl_alert_test.803717112
Short name	T353
Test name
Test status
Simulation time	18580461 ps
CPU time	1.12 seconds
Started	Jul 01 06:47:36 PM PDT 24
Finished	Jul 01 06:47:40 PM PDT 24
Peak memory	209524 kb
Host	smart-7203374d-8b9d-4be8-b3e9-c780bbb914e8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803717112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.803717112
Directory	/workspace/49.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/49.lc_ctrl_errors.3329450608
Short name	T777
Test name
Test status
Simulation time	601923507 ps
CPU time	14.67 seconds
Started	Jul 01 06:47:28 PM PDT 24
Finished	Jul 01 06:47:45 PM PDT 24
Peak memory	226452 kb
Host	smart-14f26557-7828-4059-ac55-d7519d522273
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3329450608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.3329450608
Directory	/workspace/49.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/49.lc_ctrl_jtag_access.3160418852
Short name	T178
Test name
Test status
Simulation time	130568256 ps
CPU time	4.22 seconds
Started	Jul 01 06:47:29 PM PDT 24
Finished	Jul 01 06:47:37 PM PDT 24
Peak memory	217556 kb
Host	smart-f9f800ff-f89c-480d-95ea-949969fcafaa
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160418852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.3160418852
Directory	/workspace/49.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/49.lc_ctrl_prog_failure.2786499767
Short name	T348
Test name
Test status
Simulation time	102688712 ps
CPU time	2.08 seconds
Started	Jul 01 06:47:30 PM PDT 24
Finished	Jul 01 06:47:35 PM PDT 24
Peak memory	218704 kb
Host	smart-b65aa6cc-970b-4188-a1e3-6fe094ec5fde
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2786499767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.2786499767
Directory	/workspace/49.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/49.lc_ctrl_sec_mubi.1218519550
Short name	T771
Test name
Test status
Simulation time	393711052 ps
CPU time	11.67 seconds
Started	Jul 01 06:47:32 PM PDT 24
Finished	Jul 01 06:47:46 PM PDT 24
Peak memory	226524 kb
Host	smart-df3147b5-4e46-4231-be89-e91777180b0e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218519550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.1218519550
Directory	/workspace/49.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/49.lc_ctrl_sec_token_digest.3335114203
Short name	T783
Test name
Test status
Simulation time	595513913 ps
CPU time	12.37 seconds
Started	Jul 01 06:47:29 PM PDT 24
Finished	Jul 01 06:47:45 PM PDT 24
Peak memory	218652 kb
Host	smart-98cf886a-fddf-4798-88f3-edf9883f434f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335114203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d igest.3335114203
Directory	/workspace/49.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/49.lc_ctrl_sec_token_mux.1123913474
Short name	T693
Test name
Test status
Simulation time	1505145781 ps
CPU time	8.9 seconds
Started	Jul 01 06:47:28 PM PDT 24
Finished	Jul 01 06:47:39 PM PDT 24
Peak memory	218596 kb
Host	smart-374c1d53-83a7-4923-8e18-dcf2ee992d29
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123913474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux. 1123913474
Directory	/workspace/49.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/49.lc_ctrl_security_escalation.1527436468
Short name	T112
Test name
Test status
Simulation time	307749120 ps
CPU time	11.67 seconds
Started	Jul 01 06:47:30 PM PDT 24
Finished	Jul 01 06:47:45 PM PDT 24
Peak memory	218636 kb
Host	smart-c915e824-0f49-4e7f-925b-8dfbba61f632
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1527436468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.1527436468
Directory	/workspace/49.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/49.lc_ctrl_smoke.3000685724
Short name	T835
Test name
Test status
Simulation time	49071609 ps
CPU time	1.85 seconds
Started	Jul 01 06:47:26 PM PDT 24
Finished	Jul 01 06:47:29 PM PDT 24
Peak memory	218176 kb
Host	smart-7e3d99b1-836c-4cb6-818b-0c8f8006325f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3000685724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.3000685724
Directory	/workspace/49.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/49.lc_ctrl_state_failure.1591322496
Short name	T564
Test name
Test status
Simulation time	529821971 ps
CPU time	27.82 seconds
Started	Jul 01 06:47:26 PM PDT 24
Finished	Jul 01 06:47:55 PM PDT 24
Peak memory	251400 kb
Host	smart-09b536b8-9b75-4852-9b7e-bf6cadb62ac7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1591322496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.1591322496
Directory	/workspace/49.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/49.lc_ctrl_state_post_trans.3076713370
Short name	T173
Test name
Test status
Simulation time	42466132 ps
CPU time	2.54 seconds
Started	Jul 01 06:47:32 PM PDT 24
Finished	Jul 01 06:47:38 PM PDT 24
Peak memory	218632 kb
Host	smart-c816d3ee-5608-48ba-9aa4-8b4798ff9f29
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3076713370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.3076713370
Directory	/workspace/49.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/49.lc_ctrl_stress_all.3032349545
Short name	T806
Test name
Test status
Simulation time	7605512065 ps
CPU time	145.73 seconds
Started	Jul 01 06:47:32 PM PDT 24
Finished	Jul 01 06:50:01 PM PDT 24
Peak memory	249212 kb
Host	smart-4ffcca09-3c75-41ff-b591-1ba72fae2c62
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032349545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all.3032349545
Directory	/workspace/49.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.510230809
Short name	T731
Test name
Test status
Simulation time	50450426 ps
CPU time	0.91 seconds
Started	Jul 01 06:47:29 PM PDT 24
Finished	Jul 01 06:47:33 PM PDT 24
Peak memory	212344 kb
Host	smart-09462998-cf60-46a3-8ddd-bae782248536
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510230809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ct rl_volatile_unlock_smoke.510230809
Directory	/workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/5.lc_ctrl_alert_test.3329397284
Short name	T300
Test name
Test status
Simulation time	85791833 ps
CPU time	0.92 seconds
Started	Jul 01 06:44:19 PM PDT 24
Finished	Jul 01 06:44:24 PM PDT 24
Peak memory	209140 kb
Host	smart-436cb0bf-0bd9-4cc0-ab11-8e106ddf1176
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329397284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.3329397284
Directory	/workspace/5.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/5.lc_ctrl_claim_transition_if.780583399
Short name	T829
Test name
Test status
Simulation time	34741632 ps
CPU time	0.88 seconds
Started	Jul 01 06:44:19 PM PDT 24
Finished	Jul 01 06:44:24 PM PDT 24
Peak memory	209440 kb
Host	smart-24c9f63a-1c53-4778-a1ca-5f80e7c3a8bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=780583399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.780583399
Directory	/workspace/5.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/5.lc_ctrl_errors.1804729532
Short name	T229
Test name
Test status
Simulation time	1140868653 ps
CPU time	12.44 seconds
Started	Jul 01 06:44:19 PM PDT 24
Finished	Jul 01 06:44:35 PM PDT 24
Peak memory	218644 kb
Host	smart-a506ebf2-f0f4-425f-966f-72aaa21e4676
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1804729532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.1804729532
Directory	/workspace/5.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_access.840076371
Short name	T665
Test name
Test status
Simulation time	246808093 ps
CPU time	1.61 seconds
Started	Jul 01 06:44:17 PM PDT 24
Finished	Jul 01 06:44:21 PM PDT 24
Peak memory	217608 kb
Host	smart-b4c861eb-8786-4c77-ac7b-74a715329a36
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840076371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.840076371
Directory	/workspace/5.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_errors.2371455728
Short name	T241
Test name
Test status
Simulation time	10867218062 ps
CPU time	55.57 seconds
Started	Jul 01 06:44:17 PM PDT 24
Finished	Jul 01 06:45:14 PM PDT 24
Peak memory	219360 kb
Host	smart-be656b09-5978-47f3-b20b-4bb068812224
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371455728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er rors.2371455728
Directory	/workspace/5.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_priority.3811322249
Short name	T733
Test name
Test status
Simulation time	543134621 ps
CPU time	7.37 seconds
Started	Jul 01 06:44:18 PM PDT 24
Finished	Jul 01 06:44:30 PM PDT 24
Peak memory	218232 kb
Host	smart-ef82a917-9888-4cec-90f8-36128929db82
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811322249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.3 811322249
Directory	/workspace/5.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.556423591
Short name	T250
Test name
Test status
Simulation time	743921780 ps
CPU time	3.2 seconds
Started	Jul 01 06:44:17 PM PDT 24
Finished	Jul 01 06:44:23 PM PDT 24
Peak memory	218580 kb
Host	smart-e0d2b246-6044-49be-9999-762e8a97b3f9
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556423591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_ prog_failure.556423591
Directory	/workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.1100811011
Short name	T512
Test name
Test status
Simulation time	781013025 ps
CPU time	16.87 seconds
Started	Jul 01 06:44:19 PM PDT 24
Finished	Jul 01 06:44:40 PM PDT 24
Peak memory	218084 kb
Host	smart-914114ee-db0b-4622-b595-75d141cc70f2
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100811011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_ jtag_regwen_during_op.1100811011
Directory	/workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_smoke.221588309
Short name	T69
Test name
Test status
Simulation time	247937641 ps
CPU time	4.69 seconds
Started	Jul 01 06:44:18 PM PDT 24
Finished	Jul 01 06:44:26 PM PDT 24
Peak memory	218044 kb
Host	smart-68a9c5af-7062-4b41-8928-d3e0d6f0bea9
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221588309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.221588309
Directory	/workspace/5.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_state_failure.1192425935
Short name	T729
Test name
Test status
Simulation time	2931792140 ps
CPU time	36.49 seconds
Started	Jul 01 06:44:18 PM PDT 24
Finished	Jul 01 06:44:59 PM PDT 24
Peak memory	276952 kb
Host	smart-e5f3c80b-a8f5-49fd-abfb-bdf120d9fe77
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192425935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta g_state_failure.1192425935
Directory	/workspace/5.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.1678531383
Short name	T333
Test name
Test status
Simulation time	1284136171 ps
CPU time	10.07 seconds
Started	Jul 01 06:44:18 PM PDT 24
Finished	Jul 01 06:44:31 PM PDT 24
Peak memory	224048 kb
Host	smart-674b1769-0d30-4db8-bfc0-9e3d4f2e6bb5
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678531383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_ jtag_state_post_trans.1678531383
Directory	/workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/5.lc_ctrl_prog_failure.2634236924
Short name	T629
Test name
Test status
Simulation time	65634144 ps
CPU time	1.5 seconds
Started	Jul 01 06:44:18 PM PDT 24
Finished	Jul 01 06:44:23 PM PDT 24
Peak memory	218744 kb
Host	smart-90a53da3-7eae-4009-a5bf-5ea21945183e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2634236924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.2634236924
Directory	/workspace/5.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/5.lc_ctrl_regwen_during_op.2794451662
Short name	T78
Test name
Test status
Simulation time	425597097 ps
CPU time	22.02 seconds
Started	Jul 01 06:44:18 PM PDT 24
Finished	Jul 01 06:44:44 PM PDT 24
Peak memory	218220 kb
Host	smart-4db7b04e-b0a6-4ed3-8c0e-27ca7f90c6c8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2794451662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.2794451662
Directory	/workspace/5.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/5.lc_ctrl_sec_mubi.642711767
Short name	T409
Test name
Test status
Simulation time	251693881 ps
CPU time	13 seconds
Started	Jul 01 06:44:18 PM PDT 24
Finished	Jul 01 06:44:34 PM PDT 24
Peak memory	226456 kb
Host	smart-b42c258c-f103-4a97-8fb4-92545ded6309
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642711767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.642711767
Directory	/workspace/5.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/5.lc_ctrl_sec_token_digest.2529575732
Short name	T615
Test name
Test status
Simulation time	379729923 ps
CPU time	6.87 seconds
Started	Jul 01 06:44:17 PM PDT 24
Finished	Jul 01 06:44:26 PM PDT 24
Peak memory	218828 kb
Host	smart-cb627dc3-8da9-462c-b525-21af17e46de4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529575732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di gest.2529575732
Directory	/workspace/5.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/5.lc_ctrl_sec_token_mux.2158004445
Short name	T113
Test name
Test status
Simulation time	1362970638 ps
CPU time	9.01 seconds
Started	Jul 01 06:44:19 PM PDT 24
Finished	Jul 01 06:44:32 PM PDT 24
Peak memory	218356 kb
Host	smart-30935daf-aeb0-49b7-8c0f-5c9c5392fd55
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158004445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.2 158004445
Directory	/workspace/5.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/5.lc_ctrl_security_escalation.75273954
Short name	T20
Test name
Test status
Simulation time	436650047 ps
CPU time	8.72 seconds
Started	Jul 01 06:44:18 PM PDT 24
Finished	Jul 01 06:44:30 PM PDT 24
Peak memory	225572 kb
Host	smart-5dce894d-2c3c-4306-b6a4-0ae291fa9146
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=75273954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.75273954
Directory	/workspace/5.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/5.lc_ctrl_smoke.2080447159
Short name	T307
Test name
Test status
Simulation time	199254978 ps
CPU time	3.22 seconds
Started	Jul 01 06:44:08 PM PDT 24
Finished	Jul 01 06:44:12 PM PDT 24
Peak memory	215008 kb
Host	smart-e6dc994d-2253-43e3-8974-9abd61890acf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2080447159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.2080447159
Directory	/workspace/5.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/5.lc_ctrl_state_failure.274102195
Short name	T239
Test name
Test status
Simulation time	703147928 ps
CPU time	24.47 seconds
Started	Jul 01 06:44:18 PM PDT 24
Finished	Jul 01 06:44:46 PM PDT 24
Peak memory	251456 kb
Host	smart-6658f045-4683-42fe-b8c0-4e11640f908d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=274102195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.274102195
Directory	/workspace/5.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/5.lc_ctrl_state_post_trans.729626506
Short name	T298
Test name
Test status
Simulation time	164053840 ps
CPU time	6.52 seconds
Started	Jul 01 06:44:18 PM PDT 24
Finished	Jul 01 06:44:28 PM PDT 24
Peak memory	250740 kb
Host	smart-f0de8585-4e89-4c56-ad4d-eb338e08fc92
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=729626506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.729626506
Directory	/workspace/5.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/5.lc_ctrl_stress_all.1975576597
Short name	T322
Test name
Test status
Simulation time	12903035157 ps
CPU time	416.34 seconds
Started	Jul 01 06:44:18 PM PDT 24
Finished	Jul 01 06:51:18 PM PDT 24
Peak memory	280968 kb
Host	smart-940a7c5b-3a82-472c-bb1b-9ff805ddff9a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975576597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all.1975576597
Directory	/workspace/5.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.3566945701
Short name	T734
Test name
Test status
Simulation time	13762728 ps
CPU time	1.01 seconds
Started	Jul 01 06:44:12 PM PDT 24
Finished	Jul 01 06:44:15 PM PDT 24
Peak memory	212232 kb
Host	smart-dab7403f-cb9d-4768-b82f-565015022089
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566945701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct rl_volatile_unlock_smoke.3566945701
Directory	/workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/6.lc_ctrl_alert_test.4181118897
Short name	T244
Test name
Test status
Simulation time	46692866 ps
CPU time	1.08 seconds
Started	Jul 01 06:44:29 PM PDT 24
Finished	Jul 01 06:44:32 PM PDT 24
Peak memory	209548 kb
Host	smart-e592042a-7d39-4025-b471-e7fa15b30aa4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181118897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.4181118897
Directory	/workspace/6.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/6.lc_ctrl_claim_transition_if.3172695506
Short name	T231
Test name
Test status
Simulation time	30268288 ps
CPU time	0.88 seconds
Started	Jul 01 06:44:27 PM PDT 24
Finished	Jul 01 06:44:28 PM PDT 24
Peak memory	209336 kb
Host	smart-d54628d3-d00c-45d7-bd1f-a6d11336094e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3172695506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.3172695506
Directory	/workspace/6.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/6.lc_ctrl_errors.2719497122
Short name	T714
Test name
Test status
Simulation time	290939079 ps
CPU time	8.92 seconds
Started	Jul 01 06:44:17 PM PDT 24
Finished	Jul 01 06:44:29 PM PDT 24
Peak memory	218616 kb
Host	smart-919bd7e6-b541-4b3d-8568-c3cb3aedd26c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2719497122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.2719497122
Directory	/workspace/6.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_access.2928891160
Short name	T428
Test name
Test status
Simulation time	1380777981 ps
CPU time	4.2 seconds
Started	Jul 01 06:44:29 PM PDT 24
Finished	Jul 01 06:44:35 PM PDT 24
Peak memory	217468 kb
Host	smart-515c5712-5e70-4058-bc56-09e8ee8c31cc
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928891160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.2928891160
Directory	/workspace/6.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_errors.1652158360
Short name	T324
Test name
Test status
Simulation time	1384312483 ps
CPU time	24.54 seconds
Started	Jul 01 06:44:29 PM PDT 24
Finished	Jul 01 06:44:56 PM PDT 24
Peak memory	226444 kb
Host	smart-88341a83-f634-46eb-a4ae-f54ce059e5b3
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652158360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er rors.1652158360
Directory	/workspace/6.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_priority.2160225975
Short name	T73
Test name
Test status
Simulation time	2677560335 ps
CPU time	7.5 seconds
Started	Jul 01 06:44:29 PM PDT 24
Finished	Jul 01 06:44:38 PM PDT 24
Peak memory	218272 kb
Host	smart-7e6a0978-4b6e-458d-a931-d283716f49ab
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160225975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.2 160225975
Directory	/workspace/6.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.715489839
Short name	T654
Test name
Test status
Simulation time	203084609 ps
CPU time	6.42 seconds
Started	Jul 01 06:44:28 PM PDT 24
Finished	Jul 01 06:44:36 PM PDT 24
Peak memory	218576 kb
Host	smart-903f9ad9-7c33-4e55-937e-a82887fdbed3
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715489839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_ prog_failure.715489839
Directory	/workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.1358958965
Short name	T18
Test name
Test status
Simulation time	1230216925 ps
CPU time	19.61 seconds
Started	Jul 01 06:44:29 PM PDT 24
Finished	Jul 01 06:44:51 PM PDT 24
Peak memory	218064 kb
Host	smart-a5abb740-7696-4781-a15e-558ca2469986
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358958965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_ jtag_regwen_during_op.1358958965
Directory	/workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_smoke.2785014433
Short name	T427
Test name
Test status
Simulation time	1343616219 ps
CPU time	3.97 seconds
Started	Jul 01 06:44:29 PM PDT 24
Finished	Jul 01 06:44:35 PM PDT 24
Peak memory	218096 kb
Host	smart-b290306e-e68d-441b-882e-cbfaeff7fec9
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785014433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke. 2785014433
Directory	/workspace/6.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_state_failure.83351106
Short name	T347
Test name
Test status
Simulation time	15500699675 ps
CPU time	40.74 seconds
Started	Jul 01 06:44:27 PM PDT 24
Finished	Jul 01 06:45:10 PM PDT 24
Peak memory	275928 kb
Host	smart-c18dd596-26dd-49c7-b03e-57c16db7199b
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83351106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_ state_failure.83351106
Directory	/workspace/6.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.3353287877
Short name	T754
Test name
Test status
Simulation time	454492321 ps
CPU time	19.58 seconds
Started	Jul 01 06:44:31 PM PDT 24
Finished	Jul 01 06:44:52 PM PDT 24
Peak memory	251324 kb
Host	smart-d8087072-7d92-4c54-a37c-c9ebe7ed81fa
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353287877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_ jtag_state_post_trans.3353287877
Directory	/workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/6.lc_ctrl_prog_failure.107230038
Short name	T818
Test name
Test status
Simulation time	58050078 ps
CPU time	3.07 seconds
Started	Jul 01 06:44:18 PM PDT 24
Finished	Jul 01 06:44:25 PM PDT 24
Peak memory	218692 kb
Host	smart-7ef0c8bb-4bc4-4c28-a214-a7fb04dcfa59
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=107230038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.107230038
Directory	/workspace/6.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/6.lc_ctrl_regwen_during_op.730143738
Short name	T252
Test name
Test status
Simulation time	1327286037 ps
CPU time	10.63 seconds
Started	Jul 01 06:44:29 PM PDT 24
Finished	Jul 01 06:44:42 PM PDT 24
Peak memory	218052 kb
Host	smart-63ce5d06-7f73-4bcc-bc18-cd5c03fd81f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=730143738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.730143738
Directory	/workspace/6.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/6.lc_ctrl_sec_mubi.4140914403
Short name	T821
Test name
Test status
Simulation time	330955586 ps
CPU time	14.7 seconds
Started	Jul 01 06:44:28 PM PDT 24
Finished	Jul 01 06:44:45 PM PDT 24
Peak memory	226532 kb
Host	smart-88253874-c433-4428-abf7-68863b0e1da4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140914403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.4140914403
Directory	/workspace/6.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/6.lc_ctrl_sec_token_digest.1104508723
Short name	T176
Test name
Test status
Simulation time	932570521 ps
CPU time	7.69 seconds
Started	Jul 01 06:44:30 PM PDT 24
Finished	Jul 01 06:44:40 PM PDT 24
Peak memory	218676 kb
Host	smart-24643f24-9318-4ab8-929b-5df3e6d41241
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104508723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di gest.1104508723
Directory	/workspace/6.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/6.lc_ctrl_sec_token_mux.2356359037
Short name	T744
Test name
Test status
Simulation time	1789299216 ps
CPU time	12.84 seconds
Started	Jul 01 06:44:29 PM PDT 24
Finished	Jul 01 06:44:44 PM PDT 24
Peak memory	218700 kb
Host	smart-7268be4c-688d-4155-8a78-c962d60fa2d9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356359037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.2 356359037
Directory	/workspace/6.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/6.lc_ctrl_security_escalation.3172456198
Short name	T571
Test name
Test status
Simulation time	725683442 ps
CPU time	13.88 seconds
Started	Jul 01 06:44:18 PM PDT 24
Finished	Jul 01 06:44:35 PM PDT 24
Peak memory	226560 kb
Host	smart-978c8992-236a-4cc5-ad84-91444640ab19
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3172456198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.3172456198
Directory	/workspace/6.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/6.lc_ctrl_smoke.2803458692
Short name	T258
Test name
Test status
Simulation time	56198517 ps
CPU time	1.48 seconds
Started	Jul 01 06:44:17 PM PDT 24
Finished	Jul 01 06:44:21 PM PDT 24
Peak memory	214356 kb
Host	smart-99a0000a-c570-478d-813b-6f6a5ed507ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2803458692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.2803458692
Directory	/workspace/6.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/6.lc_ctrl_state_failure.1982879122
Short name	T801
Test name
Test status
Simulation time	2743043003 ps
CPU time	31.79 seconds
Started	Jul 01 06:44:17 PM PDT 24
Finished	Jul 01 06:44:52 PM PDT 24
Peak memory	251400 kb
Host	smart-a5ee3171-8e2b-4826-b7d2-06edc2a13c6c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1982879122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.1982879122
Directory	/workspace/6.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/6.lc_ctrl_state_post_trans.479613969
Short name	T570
Test name
Test status
Simulation time	786418822 ps
CPU time	6.89 seconds
Started	Jul 01 06:44:18 PM PDT 24
Finished	Jul 01 06:44:28 PM PDT 24
Peak memory	247268 kb
Host	smart-3d430100-5abc-493f-9efd-70e62f42e10d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=479613969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.479613969
Directory	/workspace/6.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/6.lc_ctrl_stress_all.1191582650
Short name	T430
Test name
Test status
Simulation time	27324318984 ps
CPU time	130.9 seconds
Started	Jul 01 06:44:28 PM PDT 24
Finished	Jul 01 06:46:40 PM PDT 24
Peak memory	315972 kb
Host	smart-9d2a3d06-ea7d-4df1-b24b-c13bed25c544
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191582650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all.1191582650
Directory	/workspace/6.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.3552035627
Short name	T180
Test name
Test status
Simulation time	17246443498 ps
CPU time	422.49 seconds
Started	Jul 01 06:44:29 PM PDT 24
Finished	Jul 01 06:51:34 PM PDT 24
Peak memory	267980 kb
Host	smart-eb28d7bc-ed4f-4876-b553-0a6f7e5e6af7
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3552035627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.3552035627
Directory	/workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/7.lc_ctrl_alert_test.1118062206
Short name	T779
Test name
Test status
Simulation time	18621578 ps
CPU time	1.18 seconds
Started	Jul 01 06:44:42 PM PDT 24
Finished	Jul 01 06:44:45 PM PDT 24
Peak memory	209392 kb
Host	smart-3eca614b-c275-4a7c-a4f7-6e4da879efb4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118062206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.1118062206
Directory	/workspace/7.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/7.lc_ctrl_claim_transition_if.4174971986
Short name	T876
Test name
Test status
Simulation time	39572338 ps
CPU time	0.81 seconds
Started	Jul 01 06:44:30 PM PDT 24
Finished	Jul 01 06:44:33 PM PDT 24
Peak memory	209436 kb
Host	smart-20526c16-544b-4c4b-b95e-28cfc8e317df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4174971986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.4174971986
Directory	/workspace/7.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/7.lc_ctrl_errors.2630244717
Short name	T517
Test name
Test status
Simulation time	616028188 ps
CPU time	16.59 seconds
Started	Jul 01 06:44:27 PM PDT 24
Finished	Jul 01 06:44:44 PM PDT 24
Peak memory	218648 kb
Host	smart-8c9b6c01-ab54-468f-97b3-77247cd6f0ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2630244717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.2630244717
Directory	/workspace/7.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_access.2453834108
Short name	T610
Test name
Test status
Simulation time	233707599 ps
CPU time	1.43 seconds
Started	Jul 01 06:44:39 PM PDT 24
Finished	Jul 01 06:44:44 PM PDT 24
Peak memory	217592 kb
Host	smart-1e423cd2-6415-4de3-8be6-1a11ad1548a9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453834108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.2453834108
Directory	/workspace/7.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_errors.4239185983
Short name	T439
Test name
Test status
Simulation time	1810110200 ps
CPU time	57.86 seconds
Started	Jul 01 06:44:39 PM PDT 24
Finished	Jul 01 06:45:40 PM PDT 24
Peak memory	219296 kb
Host	smart-5371311c-e7ac-45da-a17e-9f0321b6ef0d
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239185983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er rors.4239185983
Directory	/workspace/7.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_priority.3178143840
Short name	T183
Test name
Test status
Simulation time	1290213397 ps
CPU time	28.29 seconds
Started	Jul 01 06:44:37 PM PDT 24
Finished	Jul 01 06:45:08 PM PDT 24
Peak memory	217956 kb
Host	smart-944c83e7-418d-4a20-ab9b-14082d27c2bb
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178143840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.3 178143840
Directory	/workspace/7.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.69410442
Short name	T519
Test name
Test status
Simulation time	2830366585 ps
CPU time	20.69 seconds
Started	Jul 01 06:44:38 PM PDT 24
Finished	Jul 01 06:45:01 PM PDT 24
Peak memory	218820 kb
Host	smart-322db251-89bb-4eda-a642-07d1d932e074
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69410442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_p rog_failure.69410442
Directory	/workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.1977524248
Short name	T789
Test name
Test status
Simulation time	1417170351 ps
CPU time	25.47 seconds
Started	Jul 01 06:44:35 PM PDT 24
Finished	Jul 01 06:45:01 PM PDT 24
Peak memory	217988 kb
Host	smart-250a45ec-937f-4d81-ab5a-ee8448716305
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977524248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_ jtag_regwen_during_op.1977524248
Directory	/workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_smoke.1713404484
Short name	T677
Test name
Test status
Simulation time	164243405 ps
CPU time	3.06 seconds
Started	Jul 01 06:44:31 PM PDT 24
Finished	Jul 01 06:44:36 PM PDT 24
Peak memory	218060 kb
Host	smart-c83d5851-a2b1-4fd4-bb20-d76d8ad4bb6c
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713404484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke. 1713404484
Directory	/workspace/7.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_state_failure.1255405206
Short name	T507
Test name
Test status
Simulation time	9064523279 ps
CPU time	64.43 seconds
Started	Jul 01 06:44:28 PM PDT 24
Finished	Jul 01 06:45:34 PM PDT 24
Peak memory	276120 kb
Host	smart-771af013-0ba7-4677-8719-5702e8123118
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255405206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta g_state_failure.1255405206
Directory	/workspace/7.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.479196729
Short name	T463
Test name
Test status
Simulation time	245153767 ps
CPU time	13.89 seconds
Started	Jul 01 06:44:40 PM PDT 24
Finished	Jul 01 06:44:56 PM PDT 24
Peak memory	251448 kb
Host	smart-3c899a26-8b21-4bd0-b68f-c113f50b1f5b
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479196729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j tag_state_post_trans.479196729
Directory	/workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/7.lc_ctrl_prog_failure.471181291
Short name	T361
Test name
Test status
Simulation time	48640093 ps
CPU time	2.95 seconds
Started	Jul 01 06:44:30 PM PDT 24
Finished	Jul 01 06:44:35 PM PDT 24
Peak memory	218560 kb
Host	smart-f64a4fdb-cf09-4730-8868-560d7477d5e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=471181291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.471181291
Directory	/workspace/7.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/7.lc_ctrl_regwen_during_op.819129312
Short name	T184
Test name
Test status
Simulation time	1595439514 ps
CPU time	17.93 seconds
Started	Jul 01 06:44:28 PM PDT 24
Finished	Jul 01 06:44:48 PM PDT 24
Peak memory	214652 kb
Host	smart-289f817a-3d26-40e0-a12a-11b60a763797
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=819129312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.819129312
Directory	/workspace/7.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/7.lc_ctrl_sec_mubi.880732892
Short name	T302
Test name
Test status
Simulation time	1287216509 ps
CPU time	15.61 seconds
Started	Jul 01 06:44:41 PM PDT 24
Finished	Jul 01 06:44:59 PM PDT 24
Peak memory	226456 kb
Host	smart-0d53bbaf-bbff-4010-8126-cbf352bb89d6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880732892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.880732892
Directory	/workspace/7.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/7.lc_ctrl_sec_token_digest.4030743944
Short name	T264
Test name
Test status
Simulation time	500103972 ps
CPU time	12 seconds
Started	Jul 01 06:44:42 PM PDT 24
Finished	Jul 01 06:44:56 PM PDT 24
Peak memory	226376 kb
Host	smart-7c18cbad-2a81-488e-8bf3-eb5b7421bf29
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030743944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di gest.4030743944
Directory	/workspace/7.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/7.lc_ctrl_sec_token_mux.2477682781
Short name	T559
Test name
Test status
Simulation time	944358790 ps
CPU time	7.16 seconds
Started	Jul 01 06:44:38 PM PDT 24
Finished	Jul 01 06:44:47 PM PDT 24
Peak memory	218592 kb
Host	smart-6d09117f-1a74-4503-ae01-cac97911ff6f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477682781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.2 477682781
Directory	/workspace/7.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/7.lc_ctrl_security_escalation.597118941
Short name	T217
Test name
Test status
Simulation time	953327933 ps
CPU time	9.56 seconds
Started	Jul 01 06:44:29 PM PDT 24
Finished	Jul 01 06:44:41 PM PDT 24
Peak memory	226516 kb
Host	smart-671fcaae-7930-48b9-8855-c8883ed77a12
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=597118941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.597118941
Directory	/workspace/7.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/7.lc_ctrl_smoke.3106874683
Short name	T840
Test name
Test status
Simulation time	31410660 ps
CPU time	1.33 seconds
Started	Jul 01 06:44:29 PM PDT 24
Finished	Jul 01 06:44:32 PM PDT 24
Peak memory	218072 kb
Host	smart-3913c548-fa21-4ab2-8c9e-61ac5c953c3e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3106874683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.3106874683
Directory	/workspace/7.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/7.lc_ctrl_state_failure.2324318540
Short name	T99
Test name
Test status
Simulation time	508987425 ps
CPU time	27.48 seconds
Started	Jul 01 06:44:27 PM PDT 24
Finished	Jul 01 06:44:57 PM PDT 24
Peak memory	251320 kb
Host	smart-1ed97dd1-19c7-40f9-abad-18dc1940703d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2324318540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.2324318540
Directory	/workspace/7.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/7.lc_ctrl_state_post_trans.2017890187
Short name	T697
Test name
Test status
Simulation time	750843900 ps
CPU time	8.68 seconds
Started	Jul 01 06:44:26 PM PDT 24
Finished	Jul 01 06:44:36 PM PDT 24
Peak memory	251336 kb
Host	smart-e6375b5c-5c30-46e2-9901-3031cfc14ce8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2017890187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.2017890187
Directory	/workspace/7.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/7.lc_ctrl_stress_all.2104582313
Short name	T626
Test name
Test status
Simulation time	19652284193 ps
CPU time	253.42 seconds
Started	Jul 01 06:44:37 PM PDT 24
Finished	Jul 01 06:48:53 PM PDT 24
Peak memory	497024 kb
Host	smart-f18e42ed-6da9-4943-ade6-1642d6d14d5e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104582313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all.2104582313
Directory	/workspace/7.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.2078414655
Short name	T163
Test name
Test status
Simulation time	93921296635 ps
CPU time	396.97 seconds
Started	Jul 01 06:44:40 PM PDT 24
Finished	Jul 01 06:51:20 PM PDT 24
Peak memory	421152 kb
Host	smart-425bdd03-6385-4b3c-b23d-2501ed2cea8c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2078414655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all_with_rand_reset.2078414655
Directory	/workspace/7.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.4232508682
Short name	T82
Test name
Test status
Simulation time	51461549 ps
CPU time	1.02 seconds
Started	Jul 01 06:44:30 PM PDT 24
Finished	Jul 01 06:44:33 PM PDT 24
Peak memory	218024 kb
Host	smart-235e1482-cc96-4085-9d2e-335a432c4f72
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232508682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct rl_volatile_unlock_smoke.4232508682
Directory	/workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/8.lc_ctrl_alert_test.4062753527
Short name	T269
Test name
Test status
Simulation time	47444157 ps
CPU time	1.41 seconds
Started	Jul 01 06:44:52 PM PDT 24
Finished	Jul 01 06:44:54 PM PDT 24
Peak memory	209372 kb
Host	smart-d48bcf95-1cd5-4a1f-be92-edd0393326f2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062753527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.4062753527
Directory	/workspace/8.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/8.lc_ctrl_claim_transition_if.3778795321
Short name	T410
Test name
Test status
Simulation time	19902332 ps
CPU time	0.88 seconds
Started	Jul 01 06:44:40 PM PDT 24
Finished	Jul 01 06:44:44 PM PDT 24
Peak memory	209176 kb
Host	smart-48a8f3d0-abd9-4d3a-b06d-a35f0ec40eb1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3778795321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.3778795321
Directory	/workspace/8.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/8.lc_ctrl_errors.2612150770
Short name	T255
Test name
Test status
Simulation time	634643398 ps
CPU time	16.48 seconds
Started	Jul 01 06:44:39 PM PDT 24
Finished	Jul 01 06:44:58 PM PDT 24
Peak memory	218648 kb
Host	smart-e1068687-2daf-4781-9c8e-976b51797250
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2612150770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.2612150770
Directory	/workspace/8.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_access.1038726632
Short name	T186
Test name
Test status
Simulation time	5621864462 ps
CPU time	8.13 seconds
Started	Jul 01 06:44:55 PM PDT 24
Finished	Jul 01 06:45:05 PM PDT 24
Peak memory	218096 kb
Host	smart-589940c6-c09a-4f08-a3a2-947fb5d0975d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038726632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.1038726632
Directory	/workspace/8.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_errors.4179480592
Short name	T281
Test name
Test status
Simulation time	19545403828 ps
CPU time	117.25 seconds
Started	Jul 01 06:44:57 PM PDT 24
Finished	Jul 01 06:46:55 PM PDT 24
Peak memory	219288 kb
Host	smart-e77d01bf-b3d7-4ce3-8da3-2788ab95b524
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179480592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er rors.4179480592
Directory	/workspace/8.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_priority.429768002
Short name	T862
Test name
Test status
Simulation time	1337953898 ps
CPU time	3.93 seconds
Started	Jul 01 06:44:54 PM PDT 24
Finished	Jul 01 06:44:59 PM PDT 24
Peak memory	217776 kb
Host	smart-6ef40e0a-5935-425b-aa4c-855ae1aa2aec
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429768002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.429768002
Directory	/workspace/8.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.2563294113
Short name	T270
Test name
Test status
Simulation time	2576321976 ps
CPU time	10.22 seconds
Started	Jul 01 06:44:55 PM PDT 24
Finished	Jul 01 06:45:07 PM PDT 24
Peak memory	226056 kb
Host	smart-19a2238c-7296-4daf-9d2e-fa185627aff0
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563294113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag _prog_failure.2563294113
Directory	/workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.138193790
Short name	T561
Test name
Test status
Simulation time	921410604 ps
CPU time	27.68 seconds
Started	Jul 01 06:44:53 PM PDT 24
Finished	Jul 01 06:45:23 PM PDT 24
Peak memory	218240 kb
Host	smart-63a7df6e-99ec-4d52-a135-f83a7e540b9a
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138193790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_j tag_regwen_during_op.138193790
Directory	/workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_smoke.3870758641
Short name	T5
Test name
Test status
Simulation time	400218282 ps
CPU time	3.89 seconds
Started	Jul 01 06:44:39 PM PDT 24
Finished	Jul 01 06:44:46 PM PDT 24
Peak memory	218100 kb
Host	smart-a0dc2bc1-3017-4ca4-90cb-dfe30bf03dcf
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870758641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke. 3870758641
Directory	/workspace/8.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_state_failure.1589963086
Short name	T267
Test name
Test status
Simulation time	41738938423 ps
CPU time	84.07 seconds
Started	Jul 01 06:44:50 PM PDT 24
Finished	Jul 01 06:46:15 PM PDT 24
Peak memory	277140 kb
Host	smart-5595fdbe-612f-447d-94e3-7ac80e8d48d8
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589963086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta g_state_failure.1589963086
Directory	/workspace/8.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.3605427696
Short name	T219
Test name
Test status
Simulation time	401643851 ps
CPU time	13.18 seconds
Started	Jul 01 06:44:49 PM PDT 24
Finished	Jul 01 06:45:04 PM PDT 24
Peak memory	226704 kb
Host	smart-7bff418e-db62-4798-abc1-c66a426b2e1b
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605427696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_ jtag_state_post_trans.3605427696
Directory	/workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/8.lc_ctrl_prog_failure.1215071473
Short name	T846
Test name
Test status
Simulation time	20687316 ps
CPU time	1.86 seconds
Started	Jul 01 06:44:37 PM PDT 24
Finished	Jul 01 06:44:41 PM PDT 24
Peak memory	218628 kb
Host	smart-04403205-7af2-4485-b838-ccc3709e67aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1215071473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.1215071473
Directory	/workspace/8.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/8.lc_ctrl_regwen_during_op.1964111572
Short name	T650
Test name
Test status
Simulation time	1023525299 ps
CPU time	7.56 seconds
Started	Jul 01 06:44:40 PM PDT 24
Finished	Jul 01 06:44:50 PM PDT 24
Peak memory	218052 kb
Host	smart-01288a70-9bc9-4964-9b90-ec90056c8470
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1964111572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.1964111572
Directory	/workspace/8.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/8.lc_ctrl_sec_mubi.3696394134
Short name	T274
Test name
Test status
Simulation time	261566539 ps
CPU time	9.53 seconds
Started	Jul 01 06:44:57 PM PDT 24
Finished	Jul 01 06:45:08 PM PDT 24
Peak memory	226572 kb
Host	smart-8918a471-0675-4742-8a07-2882598639ac
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696394134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.3696394134
Directory	/workspace/8.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/8.lc_ctrl_sec_token_digest.3963331210
Short name	T604
Test name
Test status
Simulation time	2100513132 ps
CPU time	12.89 seconds
Started	Jul 01 06:44:50 PM PDT 24
Finished	Jul 01 06:45:05 PM PDT 24
Peak memory	218604 kb
Host	smart-411de2b4-bc8c-4c3e-ac87-338d1fe25e34
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963331210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di gest.3963331210
Directory	/workspace/8.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/8.lc_ctrl_sec_token_mux.1476092567
Short name	T359
Test name
Test status
Simulation time	368677878 ps
CPU time	13.01 seconds
Started	Jul 01 06:44:57 PM PDT 24
Finished	Jul 01 06:45:11 PM PDT 24
Peak memory	218716 kb
Host	smart-2b6fcd7d-4719-4531-80aa-8f3d5454d5d9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476092567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.1 476092567
Directory	/workspace/8.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/8.lc_ctrl_security_escalation.219338735
Short name	T717
Test name
Test status
Simulation time	704728793 ps
CPU time	12.79 seconds
Started	Jul 01 06:44:39 PM PDT 24
Finished	Jul 01 06:44:54 PM PDT 24
Peak memory	226460 kb
Host	smart-2f54fed8-99d1-4ef4-907b-f52888e2b8b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=219338735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.219338735
Directory	/workspace/8.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/8.lc_ctrl_smoke.4084743419
Short name	T71
Test name
Test status
Simulation time	64149271 ps
CPU time	1.22 seconds
Started	Jul 01 06:44:37 PM PDT 24
Finished	Jul 01 06:44:41 PM PDT 24
Peak memory	218192 kb
Host	smart-e3e866b2-3753-4b86-85de-c9e21e58471e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4084743419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.4084743419
Directory	/workspace/8.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/8.lc_ctrl_state_failure.90928127
Short name	T531
Test name
Test status
Simulation time	1470307323 ps
CPU time	35.43 seconds
Started	Jul 01 06:44:41 PM PDT 24
Finished	Jul 01 06:45:19 PM PDT 24
Peak memory	251432 kb
Host	smart-1e230530-af19-4bd3-a522-0ed8961e8c0f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=90928127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.90928127
Directory	/workspace/8.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/8.lc_ctrl_state_post_trans.2591853151
Short name	T230
Test name
Test status
Simulation time	133654652 ps
CPU time	3.79 seconds
Started	Jul 01 06:44:41 PM PDT 24
Finished	Jul 01 06:44:47 PM PDT 24
Peak memory	226824 kb
Host	smart-92794f6d-c131-473d-b1c2-8f80493f9f64
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2591853151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.2591853151
Directory	/workspace/8.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/8.lc_ctrl_stress_all.517170926
Short name	T622
Test name
Test status
Simulation time	67617343339 ps
CPU time	586.75 seconds
Started	Jul 01 06:44:52 PM PDT 24
Finished	Jul 01 06:54:40 PM PDT 24
Peak memory	270180 kb
Host	smart-17581e34-128e-46c1-9a6a-d49b91adaa8b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517170926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all.517170926
Directory	/workspace/8.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.41950389
Short name	T866
Test name
Test status
Simulation time	86442760 ps
CPU time	0.77 seconds
Started	Jul 01 06:44:39 PM PDT 24
Finished	Jul 01 06:44:42 PM PDT 24
Peak memory	209116 kb
Host	smart-8f035cc3-a422-4914-9caf-114529103ec3
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41950389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl _volatile_unlock_smoke.41950389
Directory	/workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/9.lc_ctrl_alert_test.2375380250
Short name	T384
Test name
Test status
Simulation time	22768969 ps
CPU time	0.84 seconds
Started	Jul 01 06:45:03 PM PDT 24
Finished	Jul 01 06:45:06 PM PDT 24
Peak memory	209252 kb
Host	smart-515a809e-790c-4fb3-82ee-fa462bf82d5b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375380250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.2375380250
Directory	/workspace/9.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/9.lc_ctrl_claim_transition_if.1600135401
Short name	T211
Test name
Test status
Simulation time	11094332 ps
CPU time	0.95 seconds
Started	Jul 01 06:44:54 PM PDT 24
Finished	Jul 01 06:44:56 PM PDT 24
Peak memory	209464 kb
Host	smart-26f1d343-67f1-44f4-a5ac-2d93a219f6ce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1600135401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.1600135401
Directory	/workspace/9.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/9.lc_ctrl_errors.871250386
Short name	T628
Test name
Test status
Simulation time	881127227 ps
CPU time	21.42 seconds
Started	Jul 01 06:44:49 PM PDT 24
Finished	Jul 01 06:45:12 PM PDT 24
Peak memory	226568 kb
Host	smart-7a256849-dc1d-4da7-9ac5-0b07cc365754
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=871250386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.871250386
Directory	/workspace/9.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_access.706924992
Short name	T403
Test name
Test status
Simulation time	7085505456 ps
CPU time	5.17 seconds
Started	Jul 01 06:44:49 PM PDT 24
Finished	Jul 01 06:44:56 PM PDT 24
Peak memory	218172 kb
Host	smart-3f9f2b59-46bb-4eb1-98f6-48497da4522c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706924992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.706924992
Directory	/workspace/9.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_errors.4209109069
Short name	T739
Test name
Test status
Simulation time	19393292753 ps
CPU time	56.91 seconds
Started	Jul 01 06:44:49 PM PDT 24
Finished	Jul 01 06:45:48 PM PDT 24
Peak memory	226504 kb
Host	smart-4185d742-f561-47dc-8bf5-eea2e45fd29d
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209109069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er rors.4209109069
Directory	/workspace/9.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_priority.2056927014
Short name	T583
Test name
Test status
Simulation time	995184612 ps
CPU time	4.83 seconds
Started	Jul 01 06:44:49 PM PDT 24
Finished	Jul 01 06:44:55 PM PDT 24
Peak memory	218008 kb
Host	smart-671b755e-f474-4d94-83fe-a0a4709292cc
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056927014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.2 056927014
Directory	/workspace/9.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.1238809865
Short name	T737
Test name
Test status
Simulation time	462696457 ps
CPU time	7.88 seconds
Started	Jul 01 06:44:56 PM PDT 24
Finished	Jul 01 06:45:05 PM PDT 24
Peak memory	218664 kb
Host	smart-e2fa93bf-3211-4fd9-8ec8-0cfc1756ef15
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238809865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag _prog_failure.1238809865
Directory	/workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.2379350265
Short name	T332
Test name
Test status
Simulation time	5672780583 ps
CPU time	22.34 seconds
Started	Jul 01 06:44:54 PM PDT 24
Finished	Jul 01 06:45:18 PM PDT 24
Peak memory	218124 kb
Host	smart-99d842e2-179c-43c5-99a2-aea1d22d2d4f
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379350265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_ jtag_regwen_during_op.2379350265
Directory	/workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_smoke.1695604175
Short name	T842
Test name
Test status
Simulation time	127363582 ps
CPU time	2.16 seconds
Started	Jul 01 06:44:49 PM PDT 24
Finished	Jul 01 06:44:53 PM PDT 24
Peak memory	218000 kb
Host	smart-4db94f07-4f45-40ad-8074-a17ff71f89be
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695604175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke. 1695604175
Directory	/workspace/9.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_state_failure.2370002778
Short name	T653
Test name
Test status
Simulation time	6602801964 ps
CPU time	78.29 seconds
Started	Jul 01 06:44:49 PM PDT 24
Finished	Jul 01 06:46:08 PM PDT 24
Peak memory	268212 kb
Host	smart-f90c2db1-7fb9-4d7d-bb1e-110650c88f4e
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370002778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta g_state_failure.2370002778
Directory	/workspace/9.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.1373569945
Short name	T716
Test name
Test status
Simulation time	751169011 ps
CPU time	13.12 seconds
Started	Jul 01 06:44:54 PM PDT 24
Finished	Jul 01 06:45:09 PM PDT 24
Peak memory	223764 kb
Host	smart-69207f41-491d-46b8-a4f7-af405bf30ab0
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373569945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_ jtag_state_post_trans.1373569945
Directory	/workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/9.lc_ctrl_prog_failure.3756459535
Short name	T407
Test name
Test status
Simulation time	85537991 ps
CPU time	3.15 seconds
Started	Jul 01 06:44:53 PM PDT 24
Finished	Jul 01 06:44:57 PM PDT 24
Peak memory	218824 kb
Host	smart-83a9193e-7da5-4c72-a4e6-c39a22e3ad61
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3756459535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.3756459535
Directory	/workspace/9.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/9.lc_ctrl_regwen_during_op.3122699929
Short name	T873
Test name
Test status
Simulation time	1375817982 ps
CPU time	12.6 seconds
Started	Jul 01 06:44:49 PM PDT 24
Finished	Jul 01 06:45:03 PM PDT 24
Peak memory	223584 kb
Host	smart-38245a32-3ace-4388-80ff-cdeff9e51955
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3122699929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.3122699929
Directory	/workspace/9.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/9.lc_ctrl_sec_mubi.488402119
Short name	T459
Test name
Test status
Simulation time	185949079 ps
CPU time	8.2 seconds
Started	Jul 01 06:44:56 PM PDT 24
Finished	Jul 01 06:45:06 PM PDT 24
Peak memory	226396 kb
Host	smart-97980440-51f7-4075-968d-90df3e06ceed
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488402119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.488402119
Directory	/workspace/9.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/9.lc_ctrl_sec_token_digest.3488305380
Short name	T342
Test name
Test status
Simulation time	382533896 ps
CPU time	13.48 seconds
Started	Jul 01 06:44:56 PM PDT 24
Finished	Jul 01 06:45:11 PM PDT 24
Peak memory	218600 kb
Host	smart-9fb0a87a-3e79-470f-8eda-f373643212ac
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488305380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di gest.3488305380
Directory	/workspace/9.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/9.lc_ctrl_sec_token_mux.3384929189
Short name	T782
Test name
Test status
Simulation time	1274741858 ps
CPU time	12.21 seconds
Started	Jul 01 06:44:58 PM PDT 24
Finished	Jul 01 06:45:11 PM PDT 24
Peak memory	226380 kb
Host	smart-89d74bd8-7a0b-42c8-820a-6fac8bef3107
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384929189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.3 384929189
Directory	/workspace/9.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/9.lc_ctrl_security_escalation.4247747579
Short name	T514
Test name
Test status
Simulation time	569984530 ps
CPU time	12.93 seconds
Started	Jul 01 06:44:55 PM PDT 24
Finished	Jul 01 06:45:09 PM PDT 24
Peak memory	226444 kb
Host	smart-c93c4706-70f4-4937-8c6a-e288eff01b5b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4247747579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.4247747579
Directory	/workspace/9.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/9.lc_ctrl_smoke.3751158945
Short name	T382
Test name
Test status
Simulation time	14677640 ps
CPU time	1.45 seconds
Started	Jul 01 06:44:49 PM PDT 24
Finished	Jul 01 06:44:52 PM PDT 24
Peak memory	214276 kb
Host	smart-78e87804-f2f6-44b6-a2dd-9dddb8f0c021
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3751158945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.3751158945
Directory	/workspace/9.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/9.lc_ctrl_state_failure.1210694151
Short name	T261
Test name
Test status
Simulation time	779441549 ps
CPU time	16.46 seconds
Started	Jul 01 06:44:49 PM PDT 24
Finished	Jul 01 06:45:07 PM PDT 24
Peak memory	251312 kb
Host	smart-7982b4d7-896a-415a-a883-79d1288d03f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1210694151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.1210694151
Directory	/workspace/9.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/9.lc_ctrl_state_post_trans.2203337841
Short name	T257
Test name
Test status
Simulation time	342043593 ps
CPU time	3.97 seconds
Started	Jul 01 06:44:55 PM PDT 24
Finished	Jul 01 06:45:01 PM PDT 24
Peak memory	226764 kb
Host	smart-d4d42a91-34bd-4a2a-a4b0-03ce38c1ddfc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2203337841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.2203337841
Directory	/workspace/9.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/9.lc_ctrl_stress_all.1080096105
Short name	T820
Test name
Test status
Simulation time	3732239551 ps
CPU time	24.91 seconds
Started	Jul 01 06:44:52 PM PDT 24
Finished	Jul 01 06:45:17 PM PDT 24
Peak memory	251376 kb
Host	smart-2d01d16f-9449-4572-8a21-c44497662a38
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080096105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all.1080096105
Directory	/workspace/9.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.902478252
Short name	T791
Test name
Test status
Simulation time	35629717 ps
CPU time	0.8 seconds
Started	Jul 01 06:44:49 PM PDT 24
Finished	Jul 01 06:44:51 PM PDT 24
Peak memory	209092 kb
Host	smart-d9c44df2-3813-4ffb-95b8-1a69f54535d6
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902478252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctr l_volatile_unlock_smoke.902478252
Directory	/workspace/9.lc_ctrl_volatile_unlock_smoke/latest

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