Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

95461104

1

T1

186857

T2

1300

T3

53242

auto[1]

1398395

1

T1

297

T4

693

T10

495

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

95468442

1

T1

186263

T2

1300

T3

53242

auto[1]

1391057

1

T1

891

T4

1584

T10

297

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7036182	1			T1	8417		T2	90		T3	8578
auto[IdleSt]	20565988	1			T1	96323		T2	1210		T3	7928
auto[ClkMuxSt]	35259	1			T1	80		T3	97		T4	40
auto[CntIncrSt]	34911	1			T1	80		T3	97		T4	40
auto[CntProgSt]	1805032	1			T1	131		T3	15728		T4	5969
auto[TransCheckSt]	26912	1			T1	61		T3	97		T4	28
auto[TokenHashSt]	35862404	1			T1	951		T3	5385		T4	1676
auto[FlashRmaSt]	34156	1			T1	66		T3	137		T4	106
auto[TokenCheck0St]	12555	1			T1	18		T3	49		T4	26
auto[TokenCheck1St]	9384	1			T1	12		T3	24		T4	19
auto[TransProgSt]	576548	1			T1	19		T4	3298		T10	8
auto[PostTransSt]	12047596	1			T1	75019		T3	15122		T4	6504
auto[ScrapSt]	418220	1			T12	6		T14	318		T6	1120
auto[EscalateSt]	6739642	1			T1	5977		T4	3365		T10	1443
auto[InvalidSt]	11652769	1			T4	2333		T10	605		T11	727

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1941	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	11652769	1			T4	2333		T10	605		T11	727
EscalateSt	6739642	1			T1	5977		T4	3365		T10	1443
ScrapSt	418220	1			T12	6		T14	318		T6	1120
PostTransSt	12047596	1			T1	75019		T3	15122		T4	6504
TransProgSt	576548	1			T1	19		T4	3298		T10	8
TokenCheck1St	9384	1			T1	12		T3	24		T4	19
TokenCheck0St	12555	1			T1	18		T3	49		T4	26
FlashRmaSt	34156	1			T1	66		T3	137		T4	106
TokenHashSt	35862404	1			T1	951		T3	5385		T4	1676
TransCheckSt	26912	1			T1	61		T3	97		T4	28
CntProgSt	1805032	1			T1	131		T3	15728		T4	5969
CntIncrSt	34911	1			T1	80		T3	97		T4	40
ClkMuxSt	35259	1			T1	80		T3	97		T4	40
IdleSt	20565988	1			T1	96323		T2	1210		T3	7928
ResetSt	7036182	1			T1	8417		T2	90		T3	8578
arcs[ResetSt=>IdleSt]	53410	1			T1	81		T2	1		T3	98
arcs[IdleSt=>ScrapSt]	293	1			T12	2		T14	3		T6	1
arcs[IdleSt=>ClkMuxSt]	34965	1			T1	80		T3	97		T4	40
arcs[ClkMuxSt=>CntIncrSt]	34911	1			T1	80		T3	97		T4	40
arcs[CntIncrSt=>PostTransSt]	1829	1			T1	10		T5	7		T47	5
arcs[CntIncrSt=>CntProgSt]	33012	1			T1	70		T3	97		T4	40
arcs[CntProgSt=>PostTransSt]	4839	1			T1	9		T4	12		T18	13
arcs[CntProgSt=>TransCheckSt]	26912	1			T1	61		T3	97		T4	28
arcs[TransCheckSt=>PostTransSt]	3807	1			T1	15		T3	40		T5	9
arcs[TransCheckSt=>TokenHashSt]	23027	1			T1	46		T3	57		T4	28
arcs[TokenHashSt=>PostTransSt]	9799	1			T1	28		T3	8		T4	2
arcs[TokenHashSt=>FlashRmaSt]	12655	1			T1	18		T3	49		T4	26
arcs[FlashRmaSt=>TokenCheck0St]	12555	1			T1	18		T3	49		T4	26
arcs[TokenCheck0St=>PostTransSt]	3143	1			T1	6		T3	25		T4	7
arcs[TokenCheck0St=>TokenCheck1St]	9384	1			T1	12		T3	24		T4	19
arcs[TokenCheck1St=>PostTransSt]	616	1			T1	1		T3	24		T4	1
arcs[TransProgSt=>PostTransSt]	7765	1			T1	11		T4	18		T10	4
arcs[IdleSt=>EscalateSt]	242	1			T65	7		T40	11		T41	6
arcs[ClkMuxSt=>EscalateSt]	54	1			T12	1		T65	1		T40	1
arcs[CntIncrSt=>EscalateSt]	70	1			T12	2		T66	2		T67	2
arcs[CntProgSt=>EscalateSt]	1261	1			T12	17		T65	28		T40	9
arcs[TransCheckSt=>EscalateSt]	78	1			T12	7		T40	4		T69	9
arcs[TokenHashSt=>EscalateSt]	573	1			T12	30		T65	7		T40	17
arcs[FlashRmaSt=>EscalateSt]	100	1			T12	3		T65	1		T40	2
arcs[TokenCheck0St=>EscalateSt]	28	1			T65	1		T41	1		T66	2
arcs[TokenCheck1St=>EscalateSt]	165	1			T12	2		T65	4		T40	6
arcs[TransProgSt=>EscalateSt]	838	1			T12	11		T65	22		T40	9
arcs[PostTransSt=>EscalateSt]	5022	1			T1	12		T4	12		T12	8
arcs[InvalidSt=>EscalateSt]	13727	1			T4	11		T10	8		T11	4

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7036006	1			T1	8417		T2	90		T3	8578
auto[0]	auto[IdleSt]	20565831	1			T1	96323		T2	1210		T3	7928
auto[0]	auto[ClkMuxSt]	35218	1			T1	80		T3	97		T4	40
auto[0]	auto[CntIncrSt]	34872	1			T1	80		T3	97		T4	40
auto[0]	auto[CntProgSt]	1804195	1			T1	131		T3	15728		T4	5969
auto[0]	auto[TransCheckSt]	26849	1			T1	61		T3	97		T4	28
auto[0]	auto[TokenHashSt]	35862013	1			T1	951		T3	5385		T4	1676
auto[0]	auto[FlashRmaSt]	34086	1			T1	66		T3	137		T4	106
auto[0]	auto[TokenCheck0St]	12534	1			T1	18		T3	49		T4	26
auto[0]	auto[TokenCheck1St]	9275	1			T1	12		T3	24		T4	19
auto[0]	auto[TransProgSt]	575981	1			T1	19		T4	3298		T10	8
auto[0]	auto[PostTransSt]	12045118	1			T1	75016		T3	15122		T4	6500
auto[0]	auto[ScrapSt]	418177	1			T12	6		T14	318		T6	1120
auto[0]	auto[EscalateSt]	5353106	1			T1	5683		T4	2679		T10	953
auto[0]	auto[InvalidSt]	11645902	1			T4	2330		T10	600		T11	725
auto[1]	auto[ResetSt]	176	1			T12	4		T65	4		T40	5
auto[1]	auto[IdleSt]	157	1			T65	6		T40	6		T41	4
auto[1]	auto[ClkMuxSt]	41	1			T12	1		T69	1		T66	1
auto[1]	auto[CntIncrSt]	39	1			T12	2		T67	2		T191	2
auto[1]	auto[CntProgSt]	837	1			T12	10		T65	21		T40	8
auto[1]	auto[TransCheckSt]	63	1			T12	7		T40	4		T69	6
auto[1]	auto[TokenHashSt]	391	1			T12	22		T65	6		T40	13
auto[1]	auto[FlashRmaSt]	70	1			T12	3		T40	1		T67	1
auto[1]	auto[TokenCheck0St]	21	1			T65	1		T41	1		T66	2
auto[1]	auto[TokenCheck1St]	109	1			T12	2		T65	3		T40	4
auto[1]	auto[TransProgSt]	567	1			T12	8		T65	16		T40	7
auto[1]	auto[PostTransSt]	2478	1			T1	3		T4	4		T12	5
auto[1]	auto[ScrapSt]	43	1			T65	1		T40	1		T66	1
auto[1]	auto[EscalateSt]	1386536	1			T1	294		T4	686		T10	490
auto[1]	auto[InvalidSt]	6867	1			T4	3		T10	5		T11	2

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7036014	1			T1	8417		T2	90		T3	8578
auto[0]	auto[IdleSt]	20565830	1			T1	96323		T2	1210		T3	7928
auto[0]	auto[ClkMuxSt]	35223	1			T1	80		T3	97		T4	40
auto[0]	auto[CntIncrSt]	34864	1			T1	80		T3	97		T4	40
auto[0]	auto[CntProgSt]	1804214	1			T1	131		T3	15728		T4	5969
auto[0]	auto[TransCheckSt]	26864	1			T1	61		T3	97		T4	28
auto[0]	auto[TokenHashSt]	35862026	1			T1	951		T3	5385		T4	1676
auto[0]	auto[FlashRmaSt]	34092	1			T1	66		T3	137		T4	106
auto[0]	auto[TokenCheck0St]	12536	1			T1	18		T3	49		T4	26
auto[0]	auto[TokenCheck1St]	9275	1			T1	12		T3	24		T4	19
auto[0]	auto[TransProgSt]	576006	1			T1	19		T4	3298		T10	8
auto[0]	auto[PostTransSt]	12045007	1			T1	75010		T3	15122		T4	6496
auto[0]	auto[ScrapSt]	418180	1			T12	4		T14	318		T6	1120
auto[0]	auto[EscalateSt]	5360461	1			T1	5095		T4	1797		T10	1149
auto[0]	auto[InvalidSt]	11645909	1			T4	2325		T10	602		T11	725
auto[1]	auto[ResetSt]	168	1			T12	6		T65	7		T40	4
auto[1]	auto[IdleSt]	158	1			T65	3		T40	8		T41	2
auto[1]	auto[ClkMuxSt]	36	1			T65	1		T40	1		T66	1
auto[1]	auto[CntIncrSt]	47	1			T12	1		T66	2		T67	1
auto[1]	auto[CntProgSt]	818	1			T12	11		T65	13		T40	5
auto[1]	auto[TransCheckSt]	48	1			T12	3		T40	4		T69	6
auto[1]	auto[TokenHashSt]	378	1			T12	21		T65	5		T40	14
auto[1]	auto[FlashRmaSt]	64	1			T12	1		T65	1		T40	2
auto[1]	auto[TokenCheck0St]	19	1			T65	1		T41	1		T66	2
auto[1]	auto[TokenCheck1St]	109	1			T12	1		T65	1		T40	4
auto[1]	auto[TransProgSt]	542	1			T12	9		T65	15		T40	9
auto[1]	auto[PostTransSt]	2589	1			T1	9		T4	8		T12	4
auto[1]	auto[ScrapSt]	40	1			T12	2		T40	1		T66	2
auto[1]	auto[EscalateSt]	1379181	1			T1	882		T4	1568		T10	294
auto[1]	auto[InvalidSt]	6860	1			T4	8		T10	3		T11	2