Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.98 97.99 96.22 93.38 97.67 98.55 98.76 96.29


Total test records in report: 994
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
T811 /workspace/coverage/default/25.lc_ctrl_security_escalation.2656735214 Jul 02 09:41:28 AM PDT 24 Jul 02 09:41:40 AM PDT 24 410204872 ps
T812 /workspace/coverage/default/21.lc_ctrl_state_post_trans.2559522086 Jul 02 09:41:21 AM PDT 24 Jul 02 09:41:32 AM PDT 24 236592672 ps
T813 /workspace/coverage/default/31.lc_ctrl_security_escalation.480714411 Jul 02 09:41:44 AM PDT 24 Jul 02 09:41:56 AM PDT 24 1590257419 ps
T814 /workspace/coverage/default/42.lc_ctrl_sec_token_digest.1362038087 Jul 02 09:42:12 AM PDT 24 Jul 02 09:42:24 AM PDT 24 3134095769 ps
T815 /workspace/coverage/default/23.lc_ctrl_smoke.3726679619 Jul 02 09:41:21 AM PDT 24 Jul 02 09:41:26 AM PDT 24 64038814 ps
T816 /workspace/coverage/default/30.lc_ctrl_prog_failure.1693766957 Jul 02 09:41:40 AM PDT 24 Jul 02 09:41:43 AM PDT 24 29633948 ps
T817 /workspace/coverage/default/9.lc_ctrl_regwen_during_op.3154205449 Jul 02 09:40:32 AM PDT 24 Jul 02 09:40:48 AM PDT 24 988931632 ps
T818 /workspace/coverage/default/3.lc_ctrl_sec_mubi.1743333862 Jul 02 09:40:16 AM PDT 24 Jul 02 09:40:29 AM PDT 24 210202295 ps
T819 /workspace/coverage/default/38.lc_ctrl_prog_failure.2780064558 Jul 02 09:42:02 AM PDT 24 Jul 02 09:42:05 AM PDT 24 186801822 ps
T820 /workspace/coverage/default/38.lc_ctrl_security_escalation.431718215 Jul 02 09:42:02 AM PDT 24 Jul 02 09:42:17 AM PDT 24 675212367 ps
T821 /workspace/coverage/default/3.lc_ctrl_sec_token_mux.3989343561 Jul 02 09:40:08 AM PDT 24 Jul 02 09:40:17 AM PDT 24 901097392 ps
T822 /workspace/coverage/default/45.lc_ctrl_prog_failure.2407711879 Jul 02 09:42:12 AM PDT 24 Jul 02 09:42:15 AM PDT 24 56162709 ps
T823 /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.567289982 Jul 02 09:40:50 AM PDT 24 Jul 02 09:41:07 AM PDT 24 559096135 ps
T824 /workspace/coverage/default/29.lc_ctrl_state_post_trans.646006632 Jul 02 09:41:36 AM PDT 24 Jul 02 09:41:43 AM PDT 24 317683712 ps
T825 /workspace/coverage/default/25.lc_ctrl_sec_token_digest.3954641136 Jul 02 09:41:30 AM PDT 24 Jul 02 09:41:38 AM PDT 24 494293654 ps
T826 /workspace/coverage/default/37.lc_ctrl_state_failure.3238701413 Jul 02 09:42:01 AM PDT 24 Jul 02 09:42:23 AM PDT 24 230254538 ps
T827 /workspace/coverage/default/17.lc_ctrl_security_escalation.736757518 Jul 02 09:41:07 AM PDT 24 Jul 02 09:41:21 AM PDT 24 1424447670 ps
T828 /workspace/coverage/default/46.lc_ctrl_sec_token_digest.989575583 Jul 02 09:42:19 AM PDT 24 Jul 02 09:42:33 AM PDT 24 1747215623 ps
T829 /workspace/coverage/default/23.lc_ctrl_sec_mubi.3069008758 Jul 02 09:41:24 AM PDT 24 Jul 02 09:41:36 AM PDT 24 287988297 ps
T830 /workspace/coverage/default/5.lc_ctrl_sec_token_mux.3835886403 Jul 02 09:40:19 AM PDT 24 Jul 02 09:40:32 AM PDT 24 2313844863 ps
T831 /workspace/coverage/default/39.lc_ctrl_sec_token_digest.205693912 Jul 02 09:42:14 AM PDT 24 Jul 02 09:42:23 AM PDT 24 428180564 ps
T116 /workspace/coverage/default/22.lc_ctrl_stress_all.3523618861 Jul 02 09:41:20 AM PDT 24 Jul 02 09:46:09 AM PDT 24 8732802746 ps
T832 /workspace/coverage/default/46.lc_ctrl_state_failure.247319150 Jul 02 09:42:15 AM PDT 24 Jul 02 09:42:48 AM PDT 24 1941300607 ps
T833 /workspace/coverage/default/11.lc_ctrl_jtag_access.2772662391 Jul 02 09:40:45 AM PDT 24 Jul 02 09:40:53 AM PDT 24 395488857 ps
T834 /workspace/coverage/default/47.lc_ctrl_state_post_trans.3824328213 Jul 02 09:42:17 AM PDT 24 Jul 02 09:42:24 AM PDT 24 331118170 ps
T835 /workspace/coverage/default/17.lc_ctrl_smoke.1619632024 Jul 02 09:41:02 AM PDT 24 Jul 02 09:41:05 AM PDT 24 48502513 ps
T836 /workspace/coverage/default/23.lc_ctrl_sec_token_mux.181631085 Jul 02 09:41:25 AM PDT 24 Jul 02 09:41:36 AM PDT 24 627850987 ps
T837 /workspace/coverage/default/10.lc_ctrl_alert_test.738350440 Jul 02 09:40:45 AM PDT 24 Jul 02 09:40:48 AM PDT 24 24036603 ps
T838 /workspace/coverage/default/44.lc_ctrl_sec_token_digest.2084252738 Jul 02 09:42:11 AM PDT 24 Jul 02 09:42:26 AM PDT 24 784712211 ps
T839 /workspace/coverage/default/36.lc_ctrl_alert_test.3736264908 Jul 02 09:41:59 AM PDT 24 Jul 02 09:42:00 AM PDT 24 20382260 ps
T840 /workspace/coverage/default/6.lc_ctrl_smoke.3207816671 Jul 02 09:40:20 AM PDT 24 Jul 02 09:40:25 AM PDT 24 41326766 ps
T841 /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.3236958358 Jul 02 09:40:43 AM PDT 24 Jul 02 09:40:48 AM PDT 24 2022736848 ps
T842 /workspace/coverage/default/12.lc_ctrl_security_escalation.393693871 Jul 02 09:40:50 AM PDT 24 Jul 02 09:41:04 AM PDT 24 766573597 ps
T843 /workspace/coverage/default/38.lc_ctrl_alert_test.188691773 Jul 02 09:42:02 AM PDT 24 Jul 02 09:42:04 AM PDT 24 22497763 ps
T844 /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.971422310 Jul 02 09:41:15 AM PDT 24 Jul 02 09:43:32 AM PDT 24 55982776178 ps
T845 /workspace/coverage/default/5.lc_ctrl_errors.4177330690 Jul 02 09:40:16 AM PDT 24 Jul 02 09:40:31 AM PDT 24 327903278 ps
T846 /workspace/coverage/default/22.lc_ctrl_errors.2748149037 Jul 02 09:41:22 AM PDT 24 Jul 02 09:41:33 AM PDT 24 1361346061 ps
T847 /workspace/coverage/default/40.lc_ctrl_state_failure.1448728531 Jul 02 09:42:06 AM PDT 24 Jul 02 09:42:31 AM PDT 24 1542151908 ps
T848 /workspace/coverage/default/32.lc_ctrl_sec_mubi.3595423415 Jul 02 09:41:45 AM PDT 24 Jul 02 09:41:53 AM PDT 24 230238061 ps
T849 /workspace/coverage/default/15.lc_ctrl_state_post_trans.1312222292 Jul 02 09:40:58 AM PDT 24 Jul 02 09:41:06 AM PDT 24 682678495 ps
T850 /workspace/coverage/default/14.lc_ctrl_security_escalation.2139303617 Jul 02 09:41:00 AM PDT 24 Jul 02 09:41:07 AM PDT 24 272691932 ps
T851 /workspace/coverage/default/21.lc_ctrl_state_failure.852776246 Jul 02 09:41:17 AM PDT 24 Jul 02 09:41:44 AM PDT 24 585477745 ps
T852 /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.1613703778 Jul 02 09:41:03 AM PDT 24 Jul 02 09:42:13 AM PDT 24 3621815173 ps
T853 /workspace/coverage/default/45.lc_ctrl_sec_token_digest.590695271 Jul 02 09:42:14 AM PDT 24 Jul 02 09:42:30 AM PDT 24 1645360079 ps
T854 /workspace/coverage/default/2.lc_ctrl_alert_test.3414975907 Jul 02 09:40:06 AM PDT 24 Jul 02 09:40:07 AM PDT 24 48884349 ps
T855 /workspace/coverage/default/0.lc_ctrl_regwen_during_op.3869774207 Jul 02 09:40:09 AM PDT 24 Jul 02 09:40:21 AM PDT 24 1053535797 ps
T856 /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.2377342072 Jul 02 09:40:30 AM PDT 24 Jul 02 09:40:44 AM PDT 24 1105959645 ps
T857 /workspace/coverage/default/7.lc_ctrl_jtag_access.90688509 Jul 02 09:40:25 AM PDT 24 Jul 02 09:40:38 AM PDT 24 3241009869 ps
T858 /workspace/coverage/default/9.lc_ctrl_state_failure.1933143939 Jul 02 09:40:33 AM PDT 24 Jul 02 09:41:02 AM PDT 24 842889103 ps
T859 /workspace/coverage/default/42.lc_ctrl_sec_mubi.203288730 Jul 02 09:42:22 AM PDT 24 Jul 02 09:42:40 AM PDT 24 328749297 ps
T860 /workspace/coverage/default/10.lc_ctrl_sec_token_mux.2863396094 Jul 02 09:40:42 AM PDT 24 Jul 02 09:40:51 AM PDT 24 231984571 ps
T861 /workspace/coverage/default/8.lc_ctrl_sec_token_digest.2276830997 Jul 02 09:40:29 AM PDT 24 Jul 02 09:40:40 AM PDT 24 503089064 ps
T862 /workspace/coverage/default/26.lc_ctrl_state_post_trans.1307374173 Jul 02 09:41:27 AM PDT 24 Jul 02 09:41:36 AM PDT 24 295177072 ps
T863 /workspace/coverage/default/20.lc_ctrl_state_failure.1320901288 Jul 02 09:41:17 AM PDT 24 Jul 02 09:41:47 AM PDT 24 271942260 ps
T864 /workspace/coverage/default/12.lc_ctrl_jtag_access.3415784830 Jul 02 09:40:49 AM PDT 24 Jul 02 09:40:55 AM PDT 24 813488429 ps
T865 /workspace/coverage/default/47.lc_ctrl_state_failure.3100854576 Jul 02 09:42:19 AM PDT 24 Jul 02 09:42:52 AM PDT 24 1245091837 ps
T866 /workspace/coverage/default/0.lc_ctrl_smoke.530198442 Jul 02 09:39:58 AM PDT 24 Jul 02 09:40:01 AM PDT 24 104204051 ps
T867 /workspace/coverage/default/2.lc_ctrl_security_escalation.3926850964 Jul 02 09:40:06 AM PDT 24 Jul 02 09:40:19 AM PDT 24 367297303 ps
T868 /workspace/coverage/default/12.lc_ctrl_state_failure.1223464721 Jul 02 09:40:52 AM PDT 24 Jul 02 09:41:14 AM PDT 24 598690760 ps
T121 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.80277457 Jul 02 09:05:47 AM PDT 24 Jul 02 09:05:54 AM PDT 24 220095391 ps
T129 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.467443994 Jul 02 09:05:50 AM PDT 24 Jul 02 09:06:10 AM PDT 24 593457028 ps
T134 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1600089382 Jul 02 09:05:34 AM PDT 24 Jul 02 09:05:36 AM PDT 24 59985344 ps
T122 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2247195388 Jul 02 09:05:47 AM PDT 24 Jul 02 09:05:54 AM PDT 24 562909292 ps
T130 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1359292478 Jul 02 09:05:52 AM PDT 24 Jul 02 09:05:59 AM PDT 24 18120385 ps
T155 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3160320354 Jul 02 09:05:37 AM PDT 24 Jul 02 09:05:53 AM PDT 24 2756002953 ps
T158 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.963514079 Jul 02 09:05:47 AM PDT 24 Jul 02 09:05:52 AM PDT 24 1364753130 ps
T123 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1013405659 Jul 02 09:05:59 AM PDT 24 Jul 02 09:06:05 AM PDT 24 161944386 ps
T220 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.782091873 Jul 02 09:05:41 AM PDT 24 Jul 02 09:05:43 AM PDT 24 23860960 ps
T126 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1259634436 Jul 02 09:05:25 AM PDT 24 Jul 02 09:05:28 AM PDT 24 86536543 ps
T127 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.243921852 Jul 02 09:06:03 AM PDT 24 Jul 02 09:06:08 AM PDT 24 68407179 ps
T165 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3303835217 Jul 02 09:05:44 AM PDT 24 Jul 02 09:05:46 AM PDT 24 186854563 ps
T178 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.281070393 Jul 02 09:05:46 AM PDT 24 Jul 02 09:05:50 AM PDT 24 51738842 ps
T869 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3572128929 Jul 02 09:05:44 AM PDT 24 Jul 02 09:05:46 AM PDT 24 39099702 ps
T221 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2502200725 Jul 02 09:05:45 AM PDT 24 Jul 02 09:05:49 AM PDT 24 20928426 ps
T157 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1047895695 Jul 02 09:05:50 AM PDT 24 Jul 02 09:06:00 AM PDT 24 801136372 ps
T179 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.386169558 Jul 02 09:05:51 AM PDT 24 Jul 02 09:05:58 AM PDT 24 15516590 ps
T229 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.4072727752 Jul 02 09:05:39 AM PDT 24 Jul 02 09:05:55 AM PDT 24 8870680178 ps
T156 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.2407217583 Jul 02 09:05:39 AM PDT 24 Jul 02 09:05:42 AM PDT 24 99602673 ps
T166 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2433393261 Jul 02 09:05:46 AM PDT 24 Jul 02 09:05:50 AM PDT 24 82032465 ps
T870 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3522560829 Jul 02 09:05:38 AM PDT 24 Jul 02 09:05:40 AM PDT 24 1169248760 ps
T871 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.272467601 Jul 02 09:06:02 AM PDT 24 Jul 02 09:06:08 AM PDT 24 344556084 ps
T872 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1000387108 Jul 02 09:05:30 AM PDT 24 Jul 02 09:05:32 AM PDT 24 18996873 ps
T873 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1172490236 Jul 02 09:05:21 AM PDT 24 Jul 02 09:05:40 AM PDT 24 700728050 ps
T190 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1675514006 Jul 02 09:05:46 AM PDT 24 Jul 02 09:05:50 AM PDT 24 189784910 ps
T874 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2574183314 Jul 02 09:05:52 AM PDT 24 Jul 02 09:06:08 AM PDT 24 487440982 ps
T222 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.905897382 Jul 02 09:05:46 AM PDT 24 Jul 02 09:05:49 AM PDT 24 84446872 ps
T875 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.631329027 Jul 02 09:05:21 AM PDT 24 Jul 02 09:05:22 AM PDT 24 45045624 ps
T876 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2142135228 Jul 02 09:05:36 AM PDT 24 Jul 02 09:05:46 AM PDT 24 1788897074 ps
T167 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.4136572968 Jul 02 09:05:52 AM PDT 24 Jul 02 09:05:59 AM PDT 24 20717352 ps
T223 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2092938731 Jul 02 09:05:47 AM PDT 24 Jul 02 09:05:51 AM PDT 24 16497373 ps
T877 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2713168117 Jul 02 09:05:34 AM PDT 24 Jul 02 09:05:36 AM PDT 24 75897631 ps
T878 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.556433846 Jul 02 09:05:23 AM PDT 24 Jul 02 09:05:26 AM PDT 24 32469050 ps
T879 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2217534590 Jul 02 09:05:29 AM PDT 24 Jul 02 09:05:30 AM PDT 24 14085917 ps
T168 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1718919264 Jul 02 09:05:48 AM PDT 24 Jul 02 09:05:53 AM PDT 24 16709206 ps
T224 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3737353718 Jul 02 09:06:03 AM PDT 24 Jul 02 09:06:06 AM PDT 24 41620221 ps
T128 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.934228897 Jul 02 09:05:46 AM PDT 24 Jul 02 09:05:52 AM PDT 24 63436476 ps
T199 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3044914004 Jul 02 09:05:44 AM PDT 24 Jul 02 09:05:51 AM PDT 24 1371786458 ps
T880 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1166219381 Jul 02 09:05:30 AM PDT 24 Jul 02 09:05:31 AM PDT 24 19848422 ps
T881 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.226919753 Jul 02 09:05:25 AM PDT 24 Jul 02 09:05:27 AM PDT 24 45773382 ps
T132 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4181562005 Jul 02 09:05:18 AM PDT 24 Jul 02 09:05:22 AM PDT 24 1819029609 ps
T148 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3776831993 Jul 02 09:05:45 AM PDT 24 Jul 02 09:05:48 AM PDT 24 52119464 ps
T225 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.3195159541 Jul 02 09:05:46 AM PDT 24 Jul 02 09:05:51 AM PDT 24 43359845 ps
T882 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1848972124 Jul 02 09:05:49 AM PDT 24 Jul 02 09:05:56 AM PDT 24 71896835 ps
T133 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.98404544 Jul 02 09:05:25 AM PDT 24 Jul 02 09:05:28 AM PDT 24 137228579 ps
T883 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.345957692 Jul 02 09:05:22 AM PDT 24 Jul 02 09:05:24 AM PDT 24 26241098 ps
T884 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3988675635 Jul 02 09:05:46 AM PDT 24 Jul 02 09:05:49 AM PDT 24 17658117 ps
T226 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1984465222 Jul 02 09:05:51 AM PDT 24 Jul 02 09:05:58 AM PDT 24 32182516 ps
T885 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1893531047 Jul 02 09:05:23 AM PDT 24 Jul 02 09:05:26 AM PDT 24 16025666 ps
T886 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3423350121 Jul 02 09:05:35 AM PDT 24 Jul 02 09:05:51 AM PDT 24 2767901880 ps
T887 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3852675424 Jul 02 09:05:41 AM PDT 24 Jul 02 09:05:51 AM PDT 24 3698246473 ps
T227 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.251978984 Jul 02 09:05:46 AM PDT 24 Jul 02 09:05:49 AM PDT 24 16918176 ps
T888 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3595499058 Jul 02 09:05:27 AM PDT 24 Jul 02 09:05:30 AM PDT 24 87163841 ps
T212 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2389613420 Jul 02 09:05:36 AM PDT 24 Jul 02 09:05:39 AM PDT 24 27356689 ps
T889 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2709079404 Jul 02 09:05:46 AM PDT 24 Jul 02 09:05:51 AM PDT 24 58510287 ps
T213 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1110039118 Jul 02 09:05:49 AM PDT 24 Jul 02 09:05:57 AM PDT 24 99961545 ps
T890 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.389285765 Jul 02 09:05:47 AM PDT 24 Jul 02 09:05:52 AM PDT 24 106256343 ps
T891 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3769770155 Jul 02 09:05:52 AM PDT 24 Jul 02 09:05:59 AM PDT 24 86753316 ps
T137 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.756298307 Jul 02 09:05:41 AM PDT 24 Jul 02 09:05:48 AM PDT 24 171416897 ps
T142 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1750371582 Jul 02 09:05:22 AM PDT 24 Jul 02 09:05:28 AM PDT 24 428381376 ps
T153 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.33023763 Jul 02 09:05:28 AM PDT 24 Jul 02 09:05:33 AM PDT 24 193675721 ps
T892 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.243367989 Jul 02 09:05:27 AM PDT 24 Jul 02 09:05:30 AM PDT 24 30919734 ps
T893 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.576616505 Jul 02 09:05:24 AM PDT 24 Jul 02 09:05:28 AM PDT 24 804404623 ps
T894 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2257719202 Jul 02 09:05:47 AM PDT 24 Jul 02 09:05:52 AM PDT 24 71916874 ps
T895 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2571598996 Jul 02 09:05:21 AM PDT 24 Jul 02 09:05:23 AM PDT 24 36352018 ps
T896 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1338696733 Jul 02 09:05:35 AM PDT 24 Jul 02 09:05:37 AM PDT 24 43411795 ps
T897 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.2189098057 Jul 02 09:05:42 AM PDT 24 Jul 02 09:05:46 AM PDT 24 47789943 ps
T898 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2701854659 Jul 02 09:05:58 AM PDT 24 Jul 02 09:06:03 AM PDT 24 74260088 ps
T899 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.1879584224 Jul 02 09:05:51 AM PDT 24 Jul 02 09:05:59 AM PDT 24 372366156 ps
T900 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3051204082 Jul 02 09:05:49 AM PDT 24 Jul 02 09:05:56 AM PDT 24 147634677 ps
T901 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.67121182 Jul 02 09:05:32 AM PDT 24 Jul 02 09:05:34 AM PDT 24 143760255 ps
T902 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2056914845 Jul 02 09:05:41 AM PDT 24 Jul 02 09:05:49 AM PDT 24 6597199593 ps
T903 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3305206274 Jul 02 09:05:39 AM PDT 24 Jul 02 09:05:41 AM PDT 24 158439637 ps
T904 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2669455443 Jul 02 09:05:46 AM PDT 24 Jul 02 09:05:53 AM PDT 24 390182125 ps
T905 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.819077831 Jul 02 09:05:33 AM PDT 24 Jul 02 09:05:39 AM PDT 24 1890579036 ps
T906 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1362260976 Jul 02 09:05:48 AM PDT 24 Jul 02 09:05:53 AM PDT 24 20565886 ps
T907 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.249289068 Jul 02 09:05:39 AM PDT 24 Jul 02 09:05:41 AM PDT 24 55708225 ps
T908 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1961702945 Jul 02 09:05:29 AM PDT 24 Jul 02 09:05:31 AM PDT 24 265478221 ps
T909 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3699429151 Jul 02 09:05:23 AM PDT 24 Jul 02 09:05:27 AM PDT 24 187769707 ps
T910 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.447407802 Jul 02 09:05:49 AM PDT 24 Jul 02 09:05:57 AM PDT 24 143308661 ps
T911 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3384523899 Jul 02 09:05:21 AM PDT 24 Jul 02 09:05:25 AM PDT 24 100925330 ps
T912 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.4290596911 Jul 02 09:05:47 AM PDT 24 Jul 02 09:05:51 AM PDT 24 45109661 ps
T214 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1697807358 Jul 02 09:05:27 AM PDT 24 Jul 02 09:05:29 AM PDT 24 14499487 ps
T135 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2901644555 Jul 02 09:05:46 AM PDT 24 Jul 02 09:05:53 AM PDT 24 182238420 ps
T913 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.4030160200 Jul 02 09:05:34 AM PDT 24 Jul 02 09:05:36 AM PDT 24 40137630 ps
T914 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.4158838091 Jul 02 09:05:46 AM PDT 24 Jul 02 09:05:50 AM PDT 24 102000310 ps
T915 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3702586007 Jul 02 09:05:49 AM PDT 24 Jul 02 09:05:55 AM PDT 24 35133331 ps
T143 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2974967845 Jul 02 09:05:51 AM PDT 24 Jul 02 09:05:59 AM PDT 24 270557482 ps
T916 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2029351526 Jul 02 09:05:41 AM PDT 24 Jul 02 09:05:43 AM PDT 24 29148915 ps
T917 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1304054581 Jul 02 09:05:17 AM PDT 24 Jul 02 09:05:22 AM PDT 24 121961630 ps
T151 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1939049706 Jul 02 09:05:51 AM PDT 24 Jul 02 09:05:59 AM PDT 24 389395394 ps
T918 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.948530250 Jul 02 09:05:52 AM PDT 24 Jul 02 09:05:59 AM PDT 24 43298873 ps
T919 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1991840850 Jul 02 09:05:48 AM PDT 24 Jul 02 09:05:53 AM PDT 24 11364815 ps
T215 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.145923323 Jul 02 09:05:25 AM PDT 24 Jul 02 09:05:28 AM PDT 24 267564551 ps
T920 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1378679694 Jul 02 09:05:49 AM PDT 24 Jul 02 09:05:58 AM PDT 24 203926114 ps
T921 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1450072735 Jul 02 09:05:54 AM PDT 24 Jul 02 09:06:01 AM PDT 24 61408079 ps
T922 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.593805457 Jul 02 09:05:46 AM PDT 24 Jul 02 09:05:50 AM PDT 24 20925649 ps
T923 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1144178125 Jul 02 09:05:37 AM PDT 24 Jul 02 09:05:41 AM PDT 24 89109607 ps
T924 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.1436045565 Jul 02 09:05:47 AM PDT 24 Jul 02 09:05:53 AM PDT 24 32400641 ps
T146 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.4043973137 Jul 02 09:05:51 AM PDT 24 Jul 02 09:06:00 AM PDT 24 1014378268 ps
T925 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.33895853 Jul 02 09:05:46 AM PDT 24 Jul 02 09:05:50 AM PDT 24 16791160 ps
T926 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.710868613 Jul 02 09:05:47 AM PDT 24 Jul 02 09:05:53 AM PDT 24 95019828 ps
T927 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.835977726 Jul 02 09:05:28 AM PDT 24 Jul 02 09:05:30 AM PDT 24 16310844 ps
T928 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.606727133 Jul 02 09:05:47 AM PDT 24 Jul 02 09:05:52 AM PDT 24 46464301 ps
T144 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2716334786 Jul 02 09:05:21 AM PDT 24 Jul 02 09:05:26 AM PDT 24 82127770 ps
T929 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1223006862 Jul 02 09:05:51 AM PDT 24 Jul 02 09:06:01 AM PDT 24 419984565 ps
T930 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1685309447 Jul 02 09:05:39 AM PDT 24 Jul 02 09:05:41 AM PDT 24 77422806 ps
T931 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3494859292 Jul 02 09:05:47 AM PDT 24 Jul 02 09:05:52 AM PDT 24 67469264 ps
T932 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.4281904289 Jul 02 09:05:50 AM PDT 24 Jul 02 09:06:23 AM PDT 24 4906845430 ps
T933 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1241914244 Jul 02 09:05:49 AM PDT 24 Jul 02 09:05:57 AM PDT 24 694545944 ps
T145 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2863708695 Jul 02 09:05:46 AM PDT 24 Jul 02 09:05:52 AM PDT 24 498832210 ps
T934 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.1147996572 Jul 02 09:05:48 AM PDT 24 Jul 02 09:05:55 AM PDT 24 136258011 ps
T935 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3837562436 Jul 02 09:05:50 AM PDT 24 Jul 02 09:05:57 AM PDT 24 91914361 ps
T936 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.502158465 Jul 02 09:05:33 AM PDT 24 Jul 02 09:05:35 AM PDT 24 47272890 ps
T937 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4017897645 Jul 02 09:05:37 AM PDT 24 Jul 02 09:05:41 AM PDT 24 79062381 ps
T938 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3163553554 Jul 02 09:05:21 AM PDT 24 Jul 02 09:05:27 AM PDT 24 744653167 ps
T149 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3347117899 Jul 02 09:05:47 AM PDT 24 Jul 02 09:05:53 AM PDT 24 120608604 ps
T219 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3339411945 Jul 02 09:05:21 AM PDT 24 Jul 02 09:05:24 AM PDT 24 95891081 ps
T939 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.538234033 Jul 02 09:05:53 AM PDT 24 Jul 02 09:05:59 AM PDT 24 24817685 ps
T147 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.4133118923 Jul 02 09:05:37 AM PDT 24 Jul 02 09:05:40 AM PDT 24 76586864 ps
T940 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3667969736 Jul 02 09:05:48 AM PDT 24 Jul 02 09:05:54 AM PDT 24 108964493 ps
T941 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2799197913 Jul 02 09:05:58 AM PDT 24 Jul 02 09:06:04 AM PDT 24 203576557 ps
T942 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.192876079 Jul 02 09:05:47 AM PDT 24 Jul 02 09:05:53 AM PDT 24 215432897 ps
T943 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3835586752 Jul 02 09:05:36 AM PDT 24 Jul 02 09:05:38 AM PDT 24 46993141 ps
T140 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.290821250 Jul 02 09:05:46 AM PDT 24 Jul 02 09:05:51 AM PDT 24 47875506 ps
T944 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.609612341 Jul 02 09:05:45 AM PDT 24 Jul 02 09:05:51 AM PDT 24 371768844 ps
T216 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2030845373 Jul 02 09:05:43 AM PDT 24 Jul 02 09:05:45 AM PDT 24 15276401 ps
T217 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1521481235 Jul 02 09:05:26 AM PDT 24 Jul 02 09:05:28 AM PDT 24 37752406 ps
T154 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2798127381 Jul 02 09:05:37 AM PDT 24 Jul 02 09:05:40 AM PDT 24 241559250 ps
T945 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2967502051 Jul 02 09:05:22 AM PDT 24 Jul 02 09:05:24 AM PDT 24 80316723 ps
T946 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3439278174 Jul 02 09:05:52 AM PDT 24 Jul 02 09:06:00 AM PDT 24 88460569 ps
T152 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3309960659 Jul 02 09:05:53 AM PDT 24 Jul 02 09:06:01 AM PDT 24 195583980 ps
T136 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2970043969 Jul 02 09:05:45 AM PDT 24 Jul 02 09:05:50 AM PDT 24 311771185 ps
T947 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.278506712 Jul 02 09:05:51 AM PDT 24 Jul 02 09:05:58 AM PDT 24 18956315 ps
T948 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1442839877 Jul 02 09:05:46 AM PDT 24 Jul 02 09:05:51 AM PDT 24 48215521 ps
T949 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2133879064 Jul 02 09:05:21 AM PDT 24 Jul 02 09:05:24 AM PDT 24 42415885 ps
T950 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2100923927 Jul 02 09:05:26 AM PDT 24 Jul 02 09:05:28 AM PDT 24 36634264 ps
T951 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1635637911 Jul 02 09:05:27 AM PDT 24 Jul 02 09:05:42 AM PDT 24 2901642485 ps
T952 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1291938967 Jul 02 09:05:48 AM PDT 24 Jul 02 09:05:53 AM PDT 24 25287296 ps
T953 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.896215037 Jul 02 09:05:42 AM PDT 24 Jul 02 09:05:46 AM PDT 24 200704100 ps
T218 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1775682955 Jul 02 09:05:37 AM PDT 24 Jul 02 09:05:39 AM PDT 24 22728674 ps
T954 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2708740028 Jul 02 09:05:34 AM PDT 24 Jul 02 09:05:36 AM PDT 24 140754722 ps
T955 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.372337622 Jul 02 09:05:49 AM PDT 24 Jul 02 09:05:56 AM PDT 24 38058321 ps
T956 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.744526629 Jul 02 09:05:46 AM PDT 24 Jul 02 09:05:51 AM PDT 24 344486425 ps
T957 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2871273921 Jul 02 09:05:50 AM PDT 24 Jul 02 09:05:57 AM PDT 24 36449184 ps
T958 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1044310416 Jul 02 09:05:40 AM PDT 24 Jul 02 09:05:41 AM PDT 24 104492386 ps
T150 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3079978317 Jul 02 09:05:46 AM PDT 24 Jul 02 09:05:51 AM PDT 24 76582373 ps
T959 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.448156689 Jul 02 09:05:21 AM PDT 24 Jul 02 09:05:23 AM PDT 24 148963060 ps
T960 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1194241381 Jul 02 09:05:21 AM PDT 24 Jul 02 09:05:32 AM PDT 24 1439539566 ps
T961 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2813815953 Jul 02 09:05:31 AM PDT 24 Jul 02 09:05:33 AM PDT 24 106038694 ps
T962 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1073828724 Jul 02 09:05:45 AM PDT 24 Jul 02 09:05:47 AM PDT 24 45226326 ps
T139 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.4294234969 Jul 02 09:05:48 AM PDT 24 Jul 02 09:05:57 AM PDT 24 137241576 ps
T963 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3779409085 Jul 02 09:05:48 AM PDT 24 Jul 02 09:05:54 AM PDT 24 69079395 ps
T964 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2513095122 Jul 02 09:05:41 AM PDT 24 Jul 02 09:05:45 AM PDT 24 227216961 ps
T965 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1951087458 Jul 02 09:05:47 AM PDT 24 Jul 02 09:05:52 AM PDT 24 292077620 ps
T966 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3445555167 Jul 02 09:05:31 AM PDT 24 Jul 02 09:05:33 AM PDT 24 182017078 ps
T967 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.770620262 Jul 02 09:05:54 AM PDT 24 Jul 02 09:06:03 AM PDT 24 95230171 ps
T968 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1404279628 Jul 02 09:05:37 AM PDT 24 Jul 02 09:05:43 AM PDT 24 3875089209 ps
T969 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.779260144 Jul 02 09:05:35 AM PDT 24 Jul 02 09:05:37 AM PDT 24 96139898 ps
T970 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2950663900 Jul 02 09:05:40 AM PDT 24 Jul 02 09:05:41 AM PDT 24 17836188 ps
T971 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2125568056 Jul 02 09:05:37 AM PDT 24 Jul 02 09:05:39 AM PDT 24 118540496 ps
T972 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1991853009 Jul 02 09:05:38 AM PDT 24 Jul 02 09:05:40 AM PDT 24 50672834 ps
T973 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.4231304894 Jul 02 09:05:59 AM PDT 24 Jul 02 09:06:03 AM PDT 24 25919583 ps
T974 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1588160600 Jul 02 09:05:47 AM PDT 24 Jul 02 09:05:53 AM PDT 24 30719427 ps
T975 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3315582105 Jul 02 09:05:48 AM PDT 24 Jul 02 09:05:54 AM PDT 24 116662208 ps
T141 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.76655393 Jul 02 09:05:53 AM PDT 24 Jul 02 09:06:04 AM PDT 24 2734368919 ps
T976 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2621989802 Jul 02 09:05:45 AM PDT 24 Jul 02 09:05:47 AM PDT 24 59246156 ps
T977 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3864272009 Jul 02 09:05:21 AM PDT 24 Jul 02 09:05:29 AM PDT 24 2753863255 ps
T978 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2449379390 Jul 02 09:05:49 AM PDT 24 Jul 02 09:05:55 AM PDT 24 18266862 ps
T979 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3829763436 Jul 02 09:05:30 AM PDT 24 Jul 02 09:05:34 AM PDT 24 195565242 ps
T980 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2497610761 Jul 02 09:05:51 AM PDT 24 Jul 02 09:06:00 AM PDT 24 484308653 ps
T981 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1509833834 Jul 02 09:05:28 AM PDT 24 Jul 02 09:05:34 AM PDT 24 2157777305 ps
T982 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3289790856 Jul 02 09:05:45 AM PDT 24 Jul 02 09:05:52 AM PDT 24 647953391 ps
T983 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.746764751 Jul 02 09:05:51 AM PDT 24 Jul 02 09:05:57 AM PDT 24 30663428 ps
T984 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1326634777 Jul 02 09:05:34 AM PDT 24 Jul 02 09:05:36 AM PDT 24 29533076 ps
T985 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3955954193 Jul 02 09:05:30 AM PDT 24 Jul 02 09:05:34 AM PDT 24 202047812 ps
T986 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2746207675 Jul 02 09:05:49 AM PDT 24 Jul 02 09:05:56 AM PDT 24 16964826 ps
T987 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1116895131 Jul 02 09:05:27 AM PDT 24 Jul 02 09:05:33 AM PDT 24 2177371389 ps
T988 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.321822467 Jul 02 09:05:28 AM PDT 24 Jul 02 09:05:31 AM PDT 24 34483803 ps
T989 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2919018842 Jul 02 09:05:21 AM PDT 24 Jul 02 09:05:23 AM PDT 24 66594140 ps
T990 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.863923103 Jul 02 09:05:46 AM PDT 24 Jul 02 09:05:57 AM PDT 24 1653335629 ps
T991 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2166886314 Jul 02 09:05:46 AM PDT 24 Jul 02 09:05:51 AM PDT 24 88771532 ps
T992 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2664135288 Jul 02 09:05:21 AM PDT 24 Jul 02 09:05:23 AM PDT 24 35933084 ps
T993 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.2148948715 Jul 02 09:05:49 AM PDT 24 Jul 02 09:06:00 AM PDT 24 2373943924 ps
T994 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3529273126 Jul 02 09:05:44 AM PDT 24 Jul 02 09:05:46 AM PDT 24 166835793 ps

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.3405843719
Short name T12
Test name
Test status
Simulation time 2914529723 ps
CPU time 11.02 seconds
Started Jul 02 09:42:11 AM PDT 24
Finished Jul 02 09:42:23 AM PDT 24
Peak memory 217816 kb
Host smart-837d2ebf-9358-4630-95c5-f385d11b5bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405843719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.3405843719
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.592582502
Short name T19
Test name
Test status
Simulation time 1010031403 ps
CPU time 52.12 seconds
Started Jul 02 09:41:49 AM PDT 24
Finished Jul 02 09:42:42 AM PDT 24
Peak memory 269224 kb
Host smart-83b1da54-a153-46b9-b6f9-a556ba6b67cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592582502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.592582502
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.497899601
Short name T4
Test name
Test status
Simulation time 1281580520 ps
CPU time 9.53 seconds
Started Jul 02 09:41:22 AM PDT 24
Finished Jul 02 09:41:33 AM PDT 24
Peak memory 225564 kb
Host smart-7faf0d7e-2652-4692-8292-b178d36f57be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497899601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.497899601
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.1513956136
Short name T71
Test name
Test status
Simulation time 42505348713 ps
CPU time 261.14 seconds
Started Jul 02 09:41:26 AM PDT 24
Finished Jul 02 09:45:49 AM PDT 24
Peak memory 283308 kb
Host smart-a15599a6-9555-4432-8abe-23b069211a03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513956136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.1513956136
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.1514902664
Short name T45
Test name
Test status
Simulation time 44472648 ps
CPU time 0.88 seconds
Started Jul 02 09:41:41 AM PDT 24
Finished Jul 02 09:41:42 AM PDT 24
Peak memory 208576 kb
Host smart-d0742eab-ced6-4b41-a74c-7c4db8624e31
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514902664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.1514902664
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2247195388
Short name T122
Test name
Test status
Simulation time 562909292 ps
CPU time 3.18 seconds
Started Jul 02 09:05:47 AM PDT 24
Finished Jul 02 09:05:54 AM PDT 24
Peak memory 219092 kb
Host smart-b50a6ce6-bfbc-4cb8-a99b-3aea0faa5cef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247195388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.2247195388
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.3076044278
Short name T3
Test name
Test status
Simulation time 2218477212 ps
CPU time 12.44 seconds
Started Jul 02 09:42:22 AM PDT 24
Finished Jul 02 09:42:38 AM PDT 24
Peak memory 217812 kb
Host smart-7c09fe73-5305-4730-8338-5432ce78c3c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076044278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
3076044278
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.1940871651
Short name T68
Test name
Test status
Simulation time 327281392 ps
CPU time 37.64 seconds
Started Jul 02 09:40:08 AM PDT 24
Finished Jul 02 09:40:47 AM PDT 24
Peak memory 281968 kb
Host smart-b0c31256-a506-4576-8711-7102f7e209a8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940871651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.1940871651
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.2608296701
Short name T65
Test name
Test status
Simulation time 1472416969 ps
CPU time 12.93 seconds
Started Jul 02 09:42:07 AM PDT 24
Finished Jul 02 09:42:21 AM PDT 24
Peak memory 217788 kb
Host smart-f22a30bd-785e-437f-8e4e-b6d4f62bf763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608296701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.2608296701
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.2706923530
Short name T96
Test name
Test status
Simulation time 15126926988 ps
CPU time 332.65 seconds
Started Jul 02 09:42:02 AM PDT 24
Finished Jul 02 09:47:35 AM PDT 24
Peak memory 316236 kb
Host smart-22371c9f-c30f-4fd9-a413-c97bac1d04dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2706923530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.2706923530
Directory /workspace/39.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.2237363864
Short name T62
Test name
Test status
Simulation time 392403260 ps
CPU time 4.96 seconds
Started Jul 02 09:40:40 AM PDT 24
Finished Jul 02 09:40:46 AM PDT 24
Peak memory 225972 kb
Host smart-ca92bd9c-8401-48cb-a34e-8ea4f4cfbcb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237363864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.2237363864
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.445181222
Short name T33
Test name
Test status
Simulation time 464533128 ps
CPU time 13.14 seconds
Started Jul 02 09:40:31 AM PDT 24
Finished Jul 02 09:40:46 AM PDT 24
Peak memory 217756 kb
Host smart-9a3be2af-79ab-42e8-ae33-eb27144edf0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445181222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.445181222
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1259634436
Short name T126
Test name
Test status
Simulation time 86536543 ps
CPU time 2.68 seconds
Started Jul 02 09:05:25 AM PDT 24
Finished Jul 02 09:05:28 AM PDT 24
Peak memory 222352 kb
Host smart-c907af3a-748b-4aff-ab0e-49ab219c8659
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259634436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.1259634436
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.3528422415
Short name T8
Test name
Test status
Simulation time 1552724338 ps
CPU time 10.89 seconds
Started Jul 02 09:41:35 AM PDT 24
Finished Jul 02 09:41:47 AM PDT 24
Peak memory 217148 kb
Host smart-3c865712-86ec-49be-b438-e5dab1f75a0a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528422415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.3528422415
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.1113468711
Short name T92
Test name
Test status
Simulation time 84954552640 ps
CPU time 338.94 seconds
Started Jul 02 09:41:11 AM PDT 24
Finished Jul 02 09:46:52 AM PDT 24
Peak memory 250356 kb
Host smart-19e95fbc-ef62-4779-b392-93afad528905
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113468711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.1113468711
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.3767288214
Short name T13
Test name
Test status
Simulation time 72174587 ps
CPU time 1.12 seconds
Started Jul 02 09:41:03 AM PDT 24
Finished Jul 02 09:41:05 AM PDT 24
Peak memory 208520 kb
Host smart-507bf3b9-41fe-465b-abe9-a5d6d3b71492
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767288214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.3767288214
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1521481235
Short name T217
Test name
Test status
Simulation time 37752406 ps
CPU time 1.29 seconds
Started Jul 02 09:05:26 AM PDT 24
Finished Jul 02 09:05:28 AM PDT 24
Peak memory 209284 kb
Host smart-987f4caa-09c9-4a00-b507-b8a10bf945a1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521481235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.1521481235
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3160320354
Short name T155
Test name
Test status
Simulation time 2756002953 ps
CPU time 15.64 seconds
Started Jul 02 09:05:37 AM PDT 24
Finished Jul 02 09:05:53 AM PDT 24
Peak memory 209268 kb
Host smart-2f7d28e1-3020-4845-b2d8-6711f0f3341c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160320354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.3160320354
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.574283524
Short name T56
Test name
Test status
Simulation time 15812214880 ps
CPU time 735.52 seconds
Started Jul 02 09:42:27 AM PDT 24
Finished Jul 02 09:54:43 AM PDT 24
Peak memory 524380 kb
Host smart-bc6514e9-72f2-4819-a4f4-4c0c9a3f889a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=574283524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all_with_rand_reset.574283524
Directory /workspace/49.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.98404544
Short name T133
Test name
Test status
Simulation time 137228579 ps
CPU time 2.82 seconds
Started Jul 02 09:05:25 AM PDT 24
Finished Jul 02 09:05:28 AM PDT 24
Peak memory 221828 kb
Host smart-41d9486f-e14a-4b28-afb8-66d21f23566e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98404544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_er
r.98404544
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2974967845
Short name T143
Test name
Test status
Simulation time 270557482 ps
CPU time 2.66 seconds
Started Jul 02 09:05:51 AM PDT 24
Finished Jul 02 09:05:59 AM PDT 24
Peak memory 221680 kb
Host smart-bfd6d1e7-67ce-4373-b572-a75971cc93b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974967845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.2974967845
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2433393261
Short name T166
Test name
Test status
Simulation time 82032465 ps
CPU time 1.38 seconds
Started Jul 02 09:05:46 AM PDT 24
Finished Jul 02 09:05:50 AM PDT 24
Peak memory 211272 kb
Host smart-70bd2609-f114-4bca-aa07-c4b1a118729e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433393261 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.2433393261
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2901644555
Short name T135
Test name
Test status
Simulation time 182238420 ps
CPU time 4.01 seconds
Started Jul 02 09:05:46 AM PDT 24
Finished Jul 02 09:05:53 AM PDT 24
Peak memory 217564 kb
Host smart-df561259-dfc9-4e2f-a638-0d5685b16cb9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901644555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.2901644555
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1206094864
Short name T6
Test name
Test status
Simulation time 4146992683 ps
CPU time 16.4 seconds
Started Jul 02 09:40:10 AM PDT 24
Finished Jul 02 09:40:28 AM PDT 24
Peak memory 217228 kb
Host smart-a4f25fa1-111c-4ab4-bbda-50d88c0fec04
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206094864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.1206094864
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.1425433109
Short name T118
Test name
Test status
Simulation time 4324307770 ps
CPU time 214.53 seconds
Started Jul 02 09:41:37 AM PDT 24
Finished Jul 02 09:45:12 AM PDT 24
Peak memory 322936 kb
Host smart-a873f4a2-3f43-49fb-a936-a82affc2798f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425433109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.1425433109
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3079978317
Short name T150
Test name
Test status
Simulation time 76582373 ps
CPU time 2.94 seconds
Started Jul 02 09:05:46 AM PDT 24
Finished Jul 02 09:05:51 AM PDT 24
Peak memory 213328 kb
Host smart-e02452ab-006d-48e3-9101-8174d0281697
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079978317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.3079978317
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.942840302
Short name T72
Test name
Test status
Simulation time 382287598 ps
CPU time 15.99 seconds
Started Jul 02 09:40:55 AM PDT 24
Finished Jul 02 09:41:13 AM PDT 24
Peak memory 225436 kb
Host smart-b6d52bfc-cb0e-431e-a0af-c31d4bde5919
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942840302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.942840302
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4181562005
Short name T132
Test name
Test status
Simulation time 1819029609 ps
CPU time 2.68 seconds
Started Jul 02 09:05:18 AM PDT 24
Finished Jul 02 09:05:22 AM PDT 24
Peak memory 217644 kb
Host smart-ee1fcdad-66d1-415c-8410-d897f4a8055b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418156
2005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4181562005
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3347117899
Short name T149
Test name
Test status
Simulation time 120608604 ps
CPU time 3.18 seconds
Started Jul 02 09:05:47 AM PDT 24
Finished Jul 02 09:05:53 AM PDT 24
Peak memory 222364 kb
Host smart-6c11131d-5869-45a8-a10e-04819bbfcd17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347117899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.3347117899
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.2536858070
Short name T232
Test name
Test status
Simulation time 24167680 ps
CPU time 0.79 seconds
Started Jul 02 09:40:19 AM PDT 24
Finished Jul 02 09:40:24 AM PDT 24
Peak memory 208512 kb
Host smart-e368c144-7157-4e0d-8ff2-ef55840fa586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536858070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.2536858070
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.2199253570
Short name T234
Test name
Test status
Simulation time 41014112 ps
CPU time 0.82 seconds
Started Jul 02 09:40:18 AM PDT 24
Finished Jul 02 09:40:23 AM PDT 24
Peak memory 208552 kb
Host smart-642b8314-d98d-48c2-81f8-5b12f4033863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199253570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.2199253570
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.1923876022
Short name T230
Test name
Test status
Simulation time 15807049 ps
CPU time 0.74 seconds
Started Jul 02 09:40:20 AM PDT 24
Finished Jul 02 09:40:25 AM PDT 24
Peak memory 208476 kb
Host smart-a74cdfe8-524e-4e1a-989a-701fe834c9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923876022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.1923876022
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.773893761
Short name T233
Test name
Test status
Simulation time 13510416 ps
CPU time 0.81 seconds
Started Jul 02 09:40:29 AM PDT 24
Finished Jul 02 09:40:31 AM PDT 24
Peak memory 208572 kb
Host smart-2309a4cc-c90c-4837-ba31-8077e01ac375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773893761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.773893761
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2716334786
Short name T144
Test name
Test status
Simulation time 82127770 ps
CPU time 3.55 seconds
Started Jul 02 09:05:21 AM PDT 24
Finished Jul 02 09:05:26 AM PDT 24
Peak memory 222224 kb
Host smart-183af759-0de5-4bd8-bd7a-f1776bceaa54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716334786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.2716334786
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.4294234969
Short name T139
Test name
Test status
Simulation time 137241576 ps
CPU time 4.39 seconds
Started Jul 02 09:05:48 AM PDT 24
Finished Jul 02 09:05:57 AM PDT 24
Peak memory 217556 kb
Host smart-0bc8997d-5bef-46c1-8954-8e3b7af406fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294234969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.4294234969
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1939049706
Short name T151
Test name
Test status
Simulation time 389395394 ps
CPU time 2.92 seconds
Started Jul 02 09:05:51 AM PDT 24
Finished Jul 02 09:05:59 AM PDT 24
Peak memory 217444 kb
Host smart-5bb693c6-93a7-446b-91e6-d985bc809f7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939049706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.1939049706
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3309960659
Short name T152
Test name
Test status
Simulation time 195583980 ps
CPU time 2.45 seconds
Started Jul 02 09:05:53 AM PDT 24
Finished Jul 02 09:06:01 AM PDT 24
Peak memory 222156 kb
Host smart-7566173c-da59-4119-9a8a-170c08fac882
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309960659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.3309960659
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.4133118923
Short name T147
Test name
Test status
Simulation time 76586864 ps
CPU time 2.83 seconds
Started Jul 02 09:05:37 AM PDT 24
Finished Jul 02 09:05:40 AM PDT 24
Peak memory 222188 kb
Host smart-115e28a2-5b94-4b5a-a515-f4cd5e71387e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133118923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.4133118923
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.3830573597
Short name T60
Test name
Test status
Simulation time 271373391357 ps
CPU time 2724.56 seconds
Started Jul 02 09:41:15 AM PDT 24
Finished Jul 02 10:26:43 AM PDT 24
Peak memory 905340 kb
Host smart-ead53259-4cc5-4ba8-9b7a-434634d585bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3830573597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.3830573597
Directory /workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.1760396700
Short name T61
Test name
Test status
Simulation time 93118644552 ps
CPU time 364.98 seconds
Started Jul 02 09:41:56 AM PDT 24
Finished Jul 02 09:48:02 AM PDT 24
Peak memory 316148 kb
Host smart-f64d09c1-4124-46f5-8c32-3ae3bdb4709c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760396700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.1760396700
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.2403634929
Short name T49
Test name
Test status
Simulation time 398410778 ps
CPU time 11.16 seconds
Started Jul 02 09:40:00 AM PDT 24
Finished Jul 02 09:40:13 AM PDT 24
Peak memory 214316 kb
Host smart-97fa401f-1655-466d-8355-2e9c9000d5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403634929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.2403634929
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3339411945
Short name T219
Test name
Test status
Simulation time 95891081 ps
CPU time 1.54 seconds
Started Jul 02 09:05:21 AM PDT 24
Finished Jul 02 09:05:24 AM PDT 24
Peak memory 209248 kb
Host smart-99ad4ebc-f406-4bf0-9d18-e09596ce30a6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339411945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.3339411945
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.226919753
Short name T881
Test name
Test status
Simulation time 45773382 ps
CPU time 1.11 seconds
Started Jul 02 09:05:25 AM PDT 24
Finished Jul 02 09:05:27 AM PDT 24
Peak memory 211532 kb
Host smart-a560c2c4-ff5d-4124-a78d-58e0132653fc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226919753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_reset
.226919753
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2664135288
Short name T992
Test name
Test status
Simulation time 35933084 ps
CPU time 1.17 seconds
Started Jul 02 09:05:21 AM PDT 24
Finished Jul 02 09:05:23 AM PDT 24
Peak memory 217548 kb
Host smart-c5bebcb7-268a-42af-974a-9cac1ca135c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664135288 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.2664135288
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.345957692
Short name T883
Test name
Test status
Simulation time 26241098 ps
CPU time 1.01 seconds
Started Jul 02 09:05:22 AM PDT 24
Finished Jul 02 09:05:24 AM PDT 24
Peak memory 209180 kb
Host smart-08b3599d-4ff7-4208-b2b8-90df569e5e88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345957692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.345957692
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.556433846
Short name T878
Test name
Test status
Simulation time 32469050 ps
CPU time 1.17 seconds
Started Jul 02 09:05:23 AM PDT 24
Finished Jul 02 09:05:26 AM PDT 24
Peak memory 209172 kb
Host smart-0313573c-9904-4536-8ab4-bfdff26bb3f3
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556433846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.lc_ctrl_jtag_alert_test.556433846
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3163553554
Short name T938
Test name
Test status
Simulation time 744653167 ps
CPU time 5.12 seconds
Started Jul 02 09:05:21 AM PDT 24
Finished Jul 02 09:05:27 AM PDT 24
Peak memory 217024 kb
Host smart-aba0ab89-008b-4e8d-b941-4756c439f276
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163553554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.3163553554
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1172490236
Short name T873
Test name
Test status
Simulation time 700728050 ps
CPU time 17.53 seconds
Started Jul 02 09:05:21 AM PDT 24
Finished Jul 02 09:05:40 AM PDT 24
Peak memory 209244 kb
Host smart-d27a6e53-4211-4898-a074-ab539aa24c58
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172490236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.1172490236
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1304054581
Short name T917
Test name
Test status
Simulation time 121961630 ps
CPU time 3.47 seconds
Started Jul 02 09:05:17 AM PDT 24
Finished Jul 02 09:05:22 AM PDT 24
Peak memory 210840 kb
Host smart-cba09223-37ba-438c-9cf7-18cee5065060
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304054581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.1304054581
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.631329027
Short name T875
Test name
Test status
Simulation time 45045624 ps
CPU time 1.17 seconds
Started Jul 02 09:05:21 AM PDT 24
Finished Jul 02 09:05:22 AM PDT 24
Peak memory 209188 kb
Host smart-58b6f300-6a0c-4d97-b2ec-50ac995d2b9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631329027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.631329027
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2571598996
Short name T895
Test name
Test status
Simulation time 36352018 ps
CPU time 1.86 seconds
Started Jul 02 09:05:21 AM PDT 24
Finished Jul 02 09:05:23 AM PDT 24
Peak memory 217504 kb
Host smart-5aa9e626-c107-4275-9f3f-1def68045a0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571598996 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.2571598996
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.835977726
Short name T927
Test name
Test status
Simulation time 16310844 ps
CPU time 1.03 seconds
Started Jul 02 09:05:28 AM PDT 24
Finished Jul 02 09:05:30 AM PDT 24
Peak memory 209284 kb
Host smart-56bf970c-94a7-4ed8-98b1-968c0730c58c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835977726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
same_csr_outstanding.835977726
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1750371582
Short name T142
Test name
Test status
Simulation time 428381376 ps
CPU time 4.58 seconds
Started Jul 02 09:05:22 AM PDT 24
Finished Jul 02 09:05:28 AM PDT 24
Peak memory 217560 kb
Host smart-a0ee408a-1b84-4fe3-8463-4909f06de868
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750371582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.1750371582
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2389613420
Short name T212
Test name
Test status
Simulation time 27356689 ps
CPU time 1.44 seconds
Started Jul 02 09:05:36 AM PDT 24
Finished Jul 02 09:05:39 AM PDT 24
Peak memory 209292 kb
Host smart-4aa42af1-a8ff-4697-b7c4-f1b42285e251
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389613420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.2389613420
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3303835217
Short name T165
Test name
Test status
Simulation time 186854563 ps
CPU time 1.33 seconds
Started Jul 02 09:05:44 AM PDT 24
Finished Jul 02 09:05:46 AM PDT 24
Peak memory 208968 kb
Host smart-09d7a136-c3f6-4a11-baed-64ddac44c820
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303835217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.3303835217
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2919018842
Short name T989
Test name
Test status
Simulation time 66594140 ps
CPU time 1.1 seconds
Started Jul 02 09:05:21 AM PDT 24
Finished Jul 02 09:05:23 AM PDT 24
Peak memory 209972 kb
Host smart-743abb93-eea4-4179-923b-5d3ea3932326
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919018842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.2919018842
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.243367989
Short name T892
Test name
Test status
Simulation time 30919734 ps
CPU time 1.99 seconds
Started Jul 02 09:05:27 AM PDT 24
Finished Jul 02 09:05:30 AM PDT 24
Peak memory 225652 kb
Host smart-5410c9d6-444e-49c0-8f7a-726a70d6334d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243367989 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.243367989
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1893531047
Short name T885
Test name
Test status
Simulation time 16025666 ps
CPU time 1.11 seconds
Started Jul 02 09:05:23 AM PDT 24
Finished Jul 02 09:05:26 AM PDT 24
Peak memory 209308 kb
Host smart-25155e7c-6656-403b-af94-4c234f9724c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893531047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.1893531047
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2133879064
Short name T949
Test name
Test status
Simulation time 42415885 ps
CPU time 1.69 seconds
Started Jul 02 09:05:21 AM PDT 24
Finished Jul 02 09:05:24 AM PDT 24
Peak memory 209132 kb
Host smart-f46006cb-8bbe-4c61-b9eb-5430ccd4ebd4
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133879064 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.2133879064
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1194241381
Short name T960
Test name
Test status
Simulation time 1439539566 ps
CPU time 9.25 seconds
Started Jul 02 09:05:21 AM PDT 24
Finished Jul 02 09:05:32 AM PDT 24
Peak memory 209200 kb
Host smart-1e1ceba0-e3b3-4da8-810b-c82ab54dbdcd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194241381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.1194241381
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3864272009
Short name T977
Test name
Test status
Simulation time 2753863255 ps
CPU time 7.7 seconds
Started Jul 02 09:05:21 AM PDT 24
Finished Jul 02 09:05:29 AM PDT 24
Peak memory 209264 kb
Host smart-55881fd2-c120-40b1-93dd-8db644e960c4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864272009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.3864272009
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3699429151
Short name T909
Test name
Test status
Simulation time 187769707 ps
CPU time 2.98 seconds
Started Jul 02 09:05:23 AM PDT 24
Finished Jul 02 09:05:27 AM PDT 24
Peak memory 210932 kb
Host smart-174393c0-92c1-443f-9512-8e87223a23c4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699429151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.3699429151
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.576616505
Short name T893
Test name
Test status
Simulation time 804404623 ps
CPU time 2.88 seconds
Started Jul 02 09:05:24 AM PDT 24
Finished Jul 02 09:05:28 AM PDT 24
Peak memory 217612 kb
Host smart-d01d338d-9ef3-43d7-b90b-ca481258bcf0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576616
505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.576616505
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2967502051
Short name T945
Test name
Test status
Simulation time 80316723 ps
CPU time 1.14 seconds
Started Jul 02 09:05:22 AM PDT 24
Finished Jul 02 09:05:24 AM PDT 24
Peak memory 217420 kb
Host smart-3c6739b8-aebf-42c9-97e2-2c583b3f6d44
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967502051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.2967502051
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.448156689
Short name T959
Test name
Test status
Simulation time 148963060 ps
CPU time 1.33 seconds
Started Jul 02 09:05:21 AM PDT 24
Finished Jul 02 09:05:23 AM PDT 24
Peak memory 217440 kb
Host smart-22aabd7e-5385-4201-9b6c-c876fa1279db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448156689 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.448156689
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2100923927
Short name T950
Test name
Test status
Simulation time 36634264 ps
CPU time 1.4 seconds
Started Jul 02 09:05:26 AM PDT 24
Finished Jul 02 09:05:28 AM PDT 24
Peak memory 209232 kb
Host smart-71253040-4398-4608-af3c-c37257ad740d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100923927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.2100923927
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3384523899
Short name T911
Test name
Test status
Simulation time 100925330 ps
CPU time 1.8 seconds
Started Jul 02 09:05:21 AM PDT 24
Finished Jul 02 09:05:25 AM PDT 24
Peak memory 217608 kb
Host smart-bd849be5-9088-4662-be57-f1126ed87df3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384523899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.3384523899
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1588160600
Short name T974
Test name
Test status
Simulation time 30719427 ps
CPU time 2.45 seconds
Started Jul 02 09:05:47 AM PDT 24
Finished Jul 02 09:05:53 AM PDT 24
Peak memory 217712 kb
Host smart-6cb7ce1d-f01d-4d28-a1b5-aa756fd50538
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588160600 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.1588160600
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1718919264
Short name T168
Test name
Test status
Simulation time 16709206 ps
CPU time 0.93 seconds
Started Jul 02 09:05:48 AM PDT 24
Finished Jul 02 09:05:53 AM PDT 24
Peak memory 209248 kb
Host smart-2e630f27-c6c5-4902-b6f0-e987d123e711
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718919264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.1718919264
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2166886314
Short name T991
Test name
Test status
Simulation time 88771532 ps
CPU time 1.28 seconds
Started Jul 02 09:05:46 AM PDT 24
Finished Jul 02 09:05:51 AM PDT 24
Peak memory 209308 kb
Host smart-0441ad52-73cc-4c42-8927-58c527270de0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166886314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.2166886314
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2257719202
Short name T894
Test name
Test status
Simulation time 71916874 ps
CPU time 1.47 seconds
Started Jul 02 09:05:47 AM PDT 24
Finished Jul 02 09:05:52 AM PDT 24
Peak memory 219700 kb
Host smart-09bbdc90-28f0-4238-a39e-bde250a325e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257719202 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.2257719202
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.33895853
Short name T925
Test name
Test status
Simulation time 16791160 ps
CPU time 1.08 seconds
Started Jul 02 09:05:46 AM PDT 24
Finished Jul 02 09:05:50 AM PDT 24
Peak memory 209296 kb
Host smart-8aedbc2a-7a7f-4213-a5ac-001def894c49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33895853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.33895853
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.3195159541
Short name T225
Test name
Test status
Simulation time 43359845 ps
CPU time 1.49 seconds
Started Jul 02 09:05:46 AM PDT 24
Finished Jul 02 09:05:51 AM PDT 24
Peak memory 211284 kb
Host smart-fdfa33d9-3c29-4bec-b7ef-03399dc5f204
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195159541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.3195159541
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.447407802
Short name T910
Test name
Test status
Simulation time 143308661 ps
CPU time 2.93 seconds
Started Jul 02 09:05:49 AM PDT 24
Finished Jul 02 09:05:57 AM PDT 24
Peak memory 217512 kb
Host smart-df076f18-d8d3-4cfc-8b81-94cb22503cfb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447407802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.447407802
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.80277457
Short name T121
Test name
Test status
Simulation time 220095391 ps
CPU time 2.54 seconds
Started Jul 02 09:05:47 AM PDT 24
Finished Jul 02 09:05:54 AM PDT 24
Peak memory 217600 kb
Host smart-811a7920-7713-4253-83c6-7ebb0defc201
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80277457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg_e
rr.80277457
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3988675635
Short name T884
Test name
Test status
Simulation time 17658117 ps
CPU time 1.27 seconds
Started Jul 02 09:05:46 AM PDT 24
Finished Jul 02 09:05:49 AM PDT 24
Peak memory 217612 kb
Host smart-2dd6595a-b084-4029-977c-2f23b7fba244
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988675635 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.3988675635
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.593805457
Short name T922
Test name
Test status
Simulation time 20925649 ps
CPU time 0.92 seconds
Started Jul 02 09:05:46 AM PDT 24
Finished Jul 02 09:05:50 AM PDT 24
Peak memory 209288 kb
Host smart-e17dd38b-0de3-4c6a-8b92-4ade2c88915a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593805457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.593805457
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3779409085
Short name T963
Test name
Test status
Simulation time 69079395 ps
CPU time 1.92 seconds
Started Jul 02 09:05:48 AM PDT 24
Finished Jul 02 09:05:54 AM PDT 24
Peak memory 217508 kb
Host smart-cea33306-efa7-476b-a494-afd0eb9d7278
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779409085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.3779409085
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2669455443
Short name T904
Test name
Test status
Simulation time 390182125 ps
CPU time 4.19 seconds
Started Jul 02 09:05:46 AM PDT 24
Finished Jul 02 09:05:53 AM PDT 24
Peak memory 217528 kb
Host smart-2838141d-bc59-4788-b90f-ecde5cdbfd1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669455443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.2669455443
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3769770155
Short name T891
Test name
Test status
Simulation time 86753316 ps
CPU time 1.45 seconds
Started Jul 02 09:05:52 AM PDT 24
Finished Jul 02 09:05:59 AM PDT 24
Peak memory 218288 kb
Host smart-68e758ce-147f-4e9b-8f3f-6610ca0ae0fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769770155 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.3769770155
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1359292478
Short name T130
Test name
Test status
Simulation time 18120385 ps
CPU time 1.16 seconds
Started Jul 02 09:05:52 AM PDT 24
Finished Jul 02 09:05:59 AM PDT 24
Peak memory 209296 kb
Host smart-3d99f347-6caa-498c-abb6-2504404ee523
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359292478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.1359292478
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3315582105
Short name T975
Test name
Test status
Simulation time 116662208 ps
CPU time 1.25 seconds
Started Jul 02 09:05:48 AM PDT 24
Finished Jul 02 09:05:54 AM PDT 24
Peak memory 209348 kb
Host smart-dd49464c-d63f-4869-ad6d-20c37ff7818f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315582105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.3315582105
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.1147996572
Short name T934
Test name
Test status
Simulation time 136258011 ps
CPU time 2.31 seconds
Started Jul 02 09:05:48 AM PDT 24
Finished Jul 02 09:05:55 AM PDT 24
Peak memory 218556 kb
Host smart-5f006edd-96c7-4da4-8e20-3db588dfd6e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147996572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.1147996572
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.76655393
Short name T141
Test name
Test status
Simulation time 2734368919 ps
CPU time 6.06 seconds
Started Jul 02 09:05:53 AM PDT 24
Finished Jul 02 09:06:04 AM PDT 24
Peak memory 217576 kb
Host smart-7303d6a0-6a8b-474f-b17e-f94ee8a60237
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76655393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg_e
rr.76655393
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.4231304894
Short name T973
Test name
Test status
Simulation time 25919583 ps
CPU time 1.17 seconds
Started Jul 02 09:05:59 AM PDT 24
Finished Jul 02 09:06:03 AM PDT 24
Peak memory 218984 kb
Host smart-6bd2e193-8145-40d8-9c7a-220091d4e4de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231304894 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.4231304894
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.4290596911
Short name T912
Test name
Test status
Simulation time 45109661 ps
CPU time 0.86 seconds
Started Jul 02 09:05:47 AM PDT 24
Finished Jul 02 09:05:51 AM PDT 24
Peak memory 209272 kb
Host smart-a57191ab-92a0-422d-926a-42fd1be14fa4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290596911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.4290596911
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.905897382
Short name T222
Test name
Test status
Simulation time 84446872 ps
CPU time 1.08 seconds
Started Jul 02 09:05:46 AM PDT 24
Finished Jul 02 09:05:49 AM PDT 24
Peak memory 209200 kb
Host smart-f10f7805-03c1-4230-b778-c27eee1636df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905897382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_same_csr_outstanding.905897382
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1223006862
Short name T929
Test name
Test status
Simulation time 419984565 ps
CPU time 4.59 seconds
Started Jul 02 09:05:51 AM PDT 24
Finished Jul 02 09:06:01 AM PDT 24
Peak memory 217452 kb
Host smart-960c1694-87ad-42eb-b2ba-bc9f31f2827c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223006862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.1223006862
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.1436045565
Short name T924
Test name
Test status
Simulation time 32400641 ps
CPU time 1.22 seconds
Started Jul 02 09:05:47 AM PDT 24
Finished Jul 02 09:05:53 AM PDT 24
Peak memory 218628 kb
Host smart-f70ad301-d2af-4e4b-b809-65333592b3da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436045565 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.1436045565
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3737353718
Short name T224
Test name
Test status
Simulation time 41620221 ps
CPU time 0.92 seconds
Started Jul 02 09:06:03 AM PDT 24
Finished Jul 02 09:06:06 AM PDT 24
Peak memory 209256 kb
Host smart-2edbb489-cfbb-4afe-a08a-8315cede9258
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737353718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.3737353718
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1291938967
Short name T952
Test name
Test status
Simulation time 25287296 ps
CPU time 1.44 seconds
Started Jul 02 09:05:48 AM PDT 24
Finished Jul 02 09:05:53 AM PDT 24
Peak memory 217468 kb
Host smart-ef459f13-ddff-4679-a4db-c45cc3f6bb79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291938967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.1291938967
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2497610761
Short name T980
Test name
Test status
Simulation time 484308653 ps
CPU time 3.24 seconds
Started Jul 02 09:05:51 AM PDT 24
Finished Jul 02 09:06:00 AM PDT 24
Peak memory 217492 kb
Host smart-0d7d3456-03a5-4eac-af19-a0051917cb77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497610761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.2497610761
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.4136572968
Short name T167
Test name
Test status
Simulation time 20717352 ps
CPU time 1.35 seconds
Started Jul 02 09:05:52 AM PDT 24
Finished Jul 02 09:05:59 AM PDT 24
Peak memory 218940 kb
Host smart-6d0fb41a-ec73-484c-84d7-5893c7d5c567
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136572968 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.4136572968
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1442839877
Short name T948
Test name
Test status
Simulation time 48215521 ps
CPU time 0.97 seconds
Started Jul 02 09:05:46 AM PDT 24
Finished Jul 02 09:05:51 AM PDT 24
Peak memory 208688 kb
Host smart-5676f052-45f4-48a6-be79-8d1c05268efc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442839877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.1442839877
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.278506712
Short name T947
Test name
Test status
Simulation time 18956315 ps
CPU time 1.37 seconds
Started Jul 02 09:05:51 AM PDT 24
Finished Jul 02 09:05:58 AM PDT 24
Peak memory 209220 kb
Host smart-2ca6717f-958f-4723-b1a5-0231480c31ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278506712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_same_csr_outstanding.278506712
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1013405659
Short name T123
Test name
Test status
Simulation time 161944386 ps
CPU time 3.58 seconds
Started Jul 02 09:05:59 AM PDT 24
Finished Jul 02 09:06:05 AM PDT 24
Peak memory 217488 kb
Host smart-9841283f-03a2-4f38-ac04-4f25cf0afe45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013405659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.1013405659
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1450072735
Short name T921
Test name
Test status
Simulation time 61408079 ps
CPU time 1.7 seconds
Started Jul 02 09:05:54 AM PDT 24
Finished Jul 02 09:06:01 AM PDT 24
Peak memory 218040 kb
Host smart-18f158a9-b72c-4cb0-ae55-314d18c7c377
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450072735 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.1450072735
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.746764751
Short name T983
Test name
Test status
Simulation time 30663428 ps
CPU time 0.81 seconds
Started Jul 02 09:05:51 AM PDT 24
Finished Jul 02 09:05:57 AM PDT 24
Peak memory 209172 kb
Host smart-af7b79c7-f7ae-423b-894b-8aab79a40c9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746764751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.746764751
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.948530250
Short name T918
Test name
Test status
Simulation time 43298873 ps
CPU time 1.07 seconds
Started Jul 02 09:05:52 AM PDT 24
Finished Jul 02 09:05:59 AM PDT 24
Peak memory 209160 kb
Host smart-895cff6c-c922-4038-95d8-0f0ef2ecaed6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948530250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_same_csr_outstanding.948530250
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.1879584224
Short name T899
Test name
Test status
Simulation time 372366156 ps
CPU time 2.86 seconds
Started Jul 02 09:05:51 AM PDT 24
Finished Jul 02 09:05:59 AM PDT 24
Peak memory 217604 kb
Host smart-48ba0eb6-ff92-462d-9af9-7ef5d1f9f570
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879584224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.1879584224
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.386169558
Short name T179
Test name
Test status
Simulation time 15516590 ps
CPU time 1.37 seconds
Started Jul 02 09:05:51 AM PDT 24
Finished Jul 02 09:05:58 AM PDT 24
Peak memory 217644 kb
Host smart-c40bedeb-e58b-4de3-82ae-e4037aa6bd8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386169558 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.386169558
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.538234033
Short name T939
Test name
Test status
Simulation time 24817685 ps
CPU time 0.93 seconds
Started Jul 02 09:05:53 AM PDT 24
Finished Jul 02 09:05:59 AM PDT 24
Peak memory 209328 kb
Host smart-d8510e66-a6a0-4414-907a-acf265e9cd38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538234033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.538234033
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2871273921
Short name T957
Test name
Test status
Simulation time 36449184 ps
CPU time 1.32 seconds
Started Jul 02 09:05:50 AM PDT 24
Finished Jul 02 09:05:57 AM PDT 24
Peak memory 209256 kb
Host smart-fdf208af-1b83-4126-9bcf-e3b61c4821da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871273921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.2871273921
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3439278174
Short name T946
Test name
Test status
Simulation time 88460569 ps
CPU time 2.15 seconds
Started Jul 02 09:05:52 AM PDT 24
Finished Jul 02 09:06:00 AM PDT 24
Peak memory 217532 kb
Host smart-e0336860-eebc-4d33-bbf3-9fa064473ac0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439278174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.3439278174
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.4043973137
Short name T146
Test name
Test status
Simulation time 1014378268 ps
CPU time 3.5 seconds
Started Jul 02 09:05:51 AM PDT 24
Finished Jul 02 09:06:00 AM PDT 24
Peak memory 217452 kb
Host smart-8d87039c-4e4d-4e4b-94d5-29ebdabc84ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043973137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.4043973137
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3051204082
Short name T900
Test name
Test status
Simulation time 147634677 ps
CPU time 1.66 seconds
Started Jul 02 09:05:49 AM PDT 24
Finished Jul 02 09:05:56 AM PDT 24
Peak memory 219156 kb
Host smart-5520cafc-9a8c-4e5c-ab94-17f55ab906fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051204082 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.3051204082
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1991840850
Short name T919
Test name
Test status
Simulation time 11364815 ps
CPU time 1 seconds
Started Jul 02 09:05:48 AM PDT 24
Finished Jul 02 09:05:53 AM PDT 24
Peak memory 209252 kb
Host smart-357268d2-54c6-42ba-bb61-01c71653adfe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991840850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.1991840850
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2092938731
Short name T223
Test name
Test status
Simulation time 16497373 ps
CPU time 1.02 seconds
Started Jul 02 09:05:47 AM PDT 24
Finished Jul 02 09:05:51 AM PDT 24
Peak memory 209292 kb
Host smart-6250ce7f-b864-4fd2-95f3-07a50e06f691
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092938731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.2092938731
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.770620262
Short name T967
Test name
Test status
Simulation time 95230171 ps
CPU time 4.01 seconds
Started Jul 02 09:05:54 AM PDT 24
Finished Jul 02 09:06:03 AM PDT 24
Peak memory 217472 kb
Host smart-ef686aeb-fc69-4603-aa06-f5a7f3fec776
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770620262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.770620262
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.243921852
Short name T127
Test name
Test status
Simulation time 68407179 ps
CPU time 2.63 seconds
Started Jul 02 09:06:03 AM PDT 24
Finished Jul 02 09:06:08 AM PDT 24
Peak memory 217544 kb
Host smart-0150c449-933c-4c64-aae5-209dbab37c6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243921852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg_
err.243921852
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.145923323
Short name T215
Test name
Test status
Simulation time 267564551 ps
CPU time 1.74 seconds
Started Jul 02 09:05:25 AM PDT 24
Finished Jul 02 09:05:28 AM PDT 24
Peak memory 209300 kb
Host smart-989181e1-d536-43f5-91f9-1ebc1bd7cd25
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145923323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasing
.145923323
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.4158838091
Short name T914
Test name
Test status
Simulation time 102000310 ps
CPU time 1.49 seconds
Started Jul 02 09:05:46 AM PDT 24
Finished Jul 02 09:05:50 AM PDT 24
Peak memory 209288 kb
Host smart-e2ec3ada-71a5-4f6b-a218-41087d2b8c32
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158838091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.4158838091
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1697807358
Short name T214
Test name
Test status
Simulation time 14499487 ps
CPU time 1.09 seconds
Started Jul 02 09:05:27 AM PDT 24
Finished Jul 02 09:05:29 AM PDT 24
Peak memory 209708 kb
Host smart-7b2542fd-9315-4819-85b1-c4325e0a2f56
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697807358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.1697807358
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.321822467
Short name T988
Test name
Test status
Simulation time 34483803 ps
CPU time 1.6 seconds
Started Jul 02 09:05:28 AM PDT 24
Finished Jul 02 09:05:31 AM PDT 24
Peak memory 217688 kb
Host smart-eaf719e6-a55f-4732-83c3-00a47776ee50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321822467 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.321822467
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2217534590
Short name T879
Test name
Test status
Simulation time 14085917 ps
CPU time 1.05 seconds
Started Jul 02 09:05:29 AM PDT 24
Finished Jul 02 09:05:30 AM PDT 24
Peak memory 209272 kb
Host smart-271f6003-d2c4-46b1-8160-d9d1c4d26978
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217534590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.2217534590
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3595499058
Short name T888
Test name
Test status
Simulation time 87163841 ps
CPU time 1.51 seconds
Started Jul 02 09:05:27 AM PDT 24
Finished Jul 02 09:05:30 AM PDT 24
Peak memory 209108 kb
Host smart-7e4041d6-dd19-4c88-9165-a6b018252b2b
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595499058 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.3595499058
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1635637911
Short name T951
Test name
Test status
Simulation time 2901642485 ps
CPU time 14.34 seconds
Started Jul 02 09:05:27 AM PDT 24
Finished Jul 02 09:05:42 AM PDT 24
Peak memory 209220 kb
Host smart-270fd1d1-7845-4396-a752-06fbd67d7308
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635637911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.1635637911
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1509833834
Short name T981
Test name
Test status
Simulation time 2157777305 ps
CPU time 5.81 seconds
Started Jul 02 09:05:28 AM PDT 24
Finished Jul 02 09:05:34 AM PDT 24
Peak memory 209244 kb
Host smart-f7831432-1a63-4272-b504-3093d9cc2917
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509833834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.1509833834
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2713168117
Short name T877
Test name
Test status
Simulation time 75897631 ps
CPU time 1.37 seconds
Started Jul 02 09:05:34 AM PDT 24
Finished Jul 02 09:05:36 AM PDT 24
Peak memory 217448 kb
Host smart-f6e00914-94cd-4ebd-832e-ee0559b51567
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713168117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.2713168117
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1116895131
Short name T987
Test name
Test status
Simulation time 2177371389 ps
CPU time 5.91 seconds
Started Jul 02 09:05:27 AM PDT 24
Finished Jul 02 09:05:33 AM PDT 24
Peak memory 217684 kb
Host smart-31aa3fa7-3dae-4b28-bb75-92034e8f7f9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111689
5131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1116895131
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1961702945
Short name T908
Test name
Test status
Simulation time 265478221 ps
CPU time 1.1 seconds
Started Jul 02 09:05:29 AM PDT 24
Finished Jul 02 09:05:31 AM PDT 24
Peak memory 209208 kb
Host smart-a55ae2eb-4b70-4bad-92e5-d3d60311f1c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961702945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.1961702945
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2449379390
Short name T978
Test name
Test status
Simulation time 18266862 ps
CPU time 1.02 seconds
Started Jul 02 09:05:49 AM PDT 24
Finished Jul 02 09:05:55 AM PDT 24
Peak memory 209392 kb
Host smart-0ad1207a-46b0-4cf2-8f54-a0a613e94edd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449379390 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.2449379390
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3305206274
Short name T903
Test name
Test status
Simulation time 158439637 ps
CPU time 1.87 seconds
Started Jul 02 09:05:39 AM PDT 24
Finished Jul 02 09:05:41 AM PDT 24
Peak memory 217592 kb
Host smart-6e1215a1-7be8-48d5-af81-bf9acad0b144
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305206274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.3305206274
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.934228897
Short name T128
Test name
Test status
Simulation time 63436476 ps
CPU time 2.83 seconds
Started Jul 02 09:05:46 AM PDT 24
Finished Jul 02 09:05:52 AM PDT 24
Peak memory 217520 kb
Host smart-9b1a80e5-13f2-4507-a5ec-455399c338fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934228897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.934228897
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2813815953
Short name T961
Test name
Test status
Simulation time 106038694 ps
CPU time 1.07 seconds
Started Jul 02 09:05:31 AM PDT 24
Finished Jul 02 09:05:33 AM PDT 24
Peak memory 209288 kb
Host smart-1564f352-63e6-434b-8f1a-74ef15e3214b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813815953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.2813815953
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2621989802
Short name T976
Test name
Test status
Simulation time 59246156 ps
CPU time 1.77 seconds
Started Jul 02 09:05:45 AM PDT 24
Finished Jul 02 09:05:47 AM PDT 24
Peak memory 208724 kb
Host smart-75228e26-18b1-408f-9366-92f3c7832e5e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621989802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.2621989802
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3702586007
Short name T915
Test name
Test status
Simulation time 35133331 ps
CPU time 1.23 seconds
Started Jul 02 09:05:49 AM PDT 24
Finished Jul 02 09:05:55 AM PDT 24
Peak memory 217528 kb
Host smart-43d06af2-b128-407d-b281-3c839e9deedc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702586007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.3702586007
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.779260144
Short name T969
Test name
Test status
Simulation time 96139898 ps
CPU time 1.7 seconds
Started Jul 02 09:05:35 AM PDT 24
Finished Jul 02 09:05:37 AM PDT 24
Peak memory 218668 kb
Host smart-f3678b65-32e4-4ce6-baf0-24d571fb1293
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779260144 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.779260144
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1685309447
Short name T930
Test name
Test status
Simulation time 77422806 ps
CPU time 0.94 seconds
Started Jul 02 09:05:39 AM PDT 24
Finished Jul 02 09:05:41 AM PDT 24
Peak memory 208960 kb
Host smart-b5d7c0da-031d-4955-a1ae-b2d54499c37e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685309447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.1685309447
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1000387108
Short name T872
Test name
Test status
Simulation time 18996873 ps
CPU time 0.93 seconds
Started Jul 02 09:05:30 AM PDT 24
Finished Jul 02 09:05:32 AM PDT 24
Peak memory 208568 kb
Host smart-83b2f7bd-d9dd-40fd-8c42-e578fbca5980
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000387108 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.1000387108
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3289790856
Short name T982
Test name
Test status
Simulation time 647953391 ps
CPU time 6.04 seconds
Started Jul 02 09:05:45 AM PDT 24
Finished Jul 02 09:05:52 AM PDT 24
Peak memory 216920 kb
Host smart-a2eb864e-5013-4587-a4e0-6bc862366576
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289790856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.3289790856
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3423350121
Short name T886
Test name
Test status
Simulation time 2767901880 ps
CPU time 15.08 seconds
Started Jul 02 09:05:35 AM PDT 24
Finished Jul 02 09:05:51 AM PDT 24
Peak memory 209268 kb
Host smart-9864b555-1409-4f5e-a2f6-afcbb1d780b1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423350121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.3423350121
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.502158465
Short name T936
Test name
Test status
Simulation time 47272890 ps
CPU time 1.77 seconds
Started Jul 02 09:05:33 AM PDT 24
Finished Jul 02 09:05:35 AM PDT 24
Peak memory 210616 kb
Host smart-2e4c107e-4957-41e7-8554-cecae6562c3a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502158465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.502158465
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3955954193
Short name T985
Test name
Test status
Simulation time 202047812 ps
CPU time 3.68 seconds
Started Jul 02 09:05:30 AM PDT 24
Finished Jul 02 09:05:34 AM PDT 24
Peak memory 217756 kb
Host smart-e64d251e-73c0-43d1-9a4c-987808ccd46a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395595
4193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3955954193
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.67121182
Short name T901
Test name
Test status
Simulation time 143760255 ps
CPU time 2.12 seconds
Started Jul 02 09:05:32 AM PDT 24
Finished Jul 02 09:05:34 AM PDT 24
Peak memory 209228 kb
Host smart-b6b14e10-342c-4745-9d24-1a6d6f98fcfe
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67121182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test
+UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 3.lc_ctrl_jtag_csr_rw.67121182
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3445555167
Short name T966
Test name
Test status
Simulation time 182017078 ps
CPU time 1.38 seconds
Started Jul 02 09:05:31 AM PDT 24
Finished Jul 02 09:05:33 AM PDT 24
Peak memory 211480 kb
Host smart-82a9e9da-4ca1-4904-9c33-c2438c6746b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445555167 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.3445555167
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2502200725
Short name T221
Test name
Test status
Simulation time 20928426 ps
CPU time 1.23 seconds
Started Jul 02 09:05:45 AM PDT 24
Finished Jul 02 09:05:49 AM PDT 24
Peak memory 209308 kb
Host smart-fe38815d-7b79-4abd-87c7-3462f5278d5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502200725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.2502200725
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.744526629
Short name T956
Test name
Test status
Simulation time 344486425 ps
CPU time 1.65 seconds
Started Jul 02 09:05:46 AM PDT 24
Finished Jul 02 09:05:51 AM PDT 24
Peak memory 217588 kb
Host smart-55ff4b23-4443-4b9f-a772-6a84ad5bccdf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744526629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.744526629
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.33023763
Short name T153
Test name
Test status
Simulation time 193675721 ps
CPU time 3.95 seconds
Started Jul 02 09:05:28 AM PDT 24
Finished Jul 02 09:05:33 AM PDT 24
Peak memory 217496 kb
Host smart-4c335783-bc85-48ca-9ede-bd9641e10a45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33023763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_er
r.33023763
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1110039118
Short name T213
Test name
Test status
Simulation time 99961545 ps
CPU time 1.37 seconds
Started Jul 02 09:05:49 AM PDT 24
Finished Jul 02 09:05:57 AM PDT 24
Peak memory 209528 kb
Host smart-8cf297d6-a5b1-4923-a414-00f820bc0490
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110039118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.1110039118
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.372337622
Short name T955
Test name
Test status
Simulation time 38058321 ps
CPU time 1.24 seconds
Started Jul 02 09:05:49 AM PDT 24
Finished Jul 02 09:05:56 AM PDT 24
Peak memory 208924 kb
Host smart-cecad251-e2c7-47b5-8f9a-f89749d46aef
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372337622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bash
.372337622
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1775682955
Short name T218
Test name
Test status
Simulation time 22728674 ps
CPU time 1.24 seconds
Started Jul 02 09:05:37 AM PDT 24
Finished Jul 02 09:05:39 AM PDT 24
Peak memory 211656 kb
Host smart-b5c7ad85-9c7f-4139-8bc0-94850d8fcb83
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775682955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.1775682955
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.281070393
Short name T178
Test name
Test status
Simulation time 51738842 ps
CPU time 1.3 seconds
Started Jul 02 09:05:46 AM PDT 24
Finished Jul 02 09:05:50 AM PDT 24
Peak memory 219100 kb
Host smart-baa84f11-9808-4f4b-9463-471bf85f97f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281070393 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.281070393
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1166219381
Short name T880
Test name
Test status
Simulation time 19848422 ps
CPU time 0.8 seconds
Started Jul 02 09:05:30 AM PDT 24
Finished Jul 02 09:05:31 AM PDT 24
Peak memory 208560 kb
Host smart-c3d591e7-30f4-4adf-8164-2914629b4feb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166219381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.1166219381
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.963514079
Short name T158
Test name
Test status
Simulation time 1364753130 ps
CPU time 1.82 seconds
Started Jul 02 09:05:47 AM PDT 24
Finished Jul 02 09:05:52 AM PDT 24
Peak memory 209124 kb
Host smart-f97a69dd-7666-43f1-8097-20e2d9f9a9d8
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963514079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.lc_ctrl_jtag_alert_test.963514079
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.819077831
Short name T905
Test name
Test status
Simulation time 1890579036 ps
CPU time 5.13 seconds
Started Jul 02 09:05:33 AM PDT 24
Finished Jul 02 09:05:39 AM PDT 24
Peak memory 217104 kb
Host smart-c274933e-2598-49ca-8877-42a8bb48c544
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819077831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.819077831
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2125568056
Short name T971
Test name
Test status
Simulation time 118540496 ps
CPU time 1.36 seconds
Started Jul 02 09:05:37 AM PDT 24
Finished Jul 02 09:05:39 AM PDT 24
Peak memory 210212 kb
Host smart-65482e85-085e-4c6c-9fe8-8afbb6c387f0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125568056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.2125568056
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3829763436
Short name T979
Test name
Test status
Simulation time 195565242 ps
CPU time 2.86 seconds
Started Jul 02 09:05:30 AM PDT 24
Finished Jul 02 09:05:34 AM PDT 24
Peak memory 218712 kb
Host smart-9817dddb-d8a5-40fb-98b6-c261bf256616
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382976
3436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3829763436
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1848972124
Short name T882
Test name
Test status
Simulation time 71896835 ps
CPU time 1.6 seconds
Started Jul 02 09:05:49 AM PDT 24
Finished Jul 02 09:05:56 AM PDT 24
Peak memory 209228 kb
Host smart-7ad4e23b-d4ff-4145-ba54-a22ff4b0e9bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848972124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.1848972124
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1600089382
Short name T134
Test name
Test status
Simulation time 59985344 ps
CPU time 1.42 seconds
Started Jul 02 09:05:34 AM PDT 24
Finished Jul 02 09:05:36 AM PDT 24
Peak memory 217580 kb
Host smart-a289e7da-baac-4d47-8919-6ac247c19a16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600089382 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.1600089382
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1991853009
Short name T972
Test name
Test status
Simulation time 50672834 ps
CPU time 1.16 seconds
Started Jul 02 09:05:38 AM PDT 24
Finished Jul 02 09:05:40 AM PDT 24
Peak memory 209332 kb
Host smart-7f0395ae-38ce-4f61-886d-f033e2234c0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991853009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.1991853009
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3776831993
Short name T148
Test name
Test status
Simulation time 52119464 ps
CPU time 1.89 seconds
Started Jul 02 09:05:45 AM PDT 24
Finished Jul 02 09:05:48 AM PDT 24
Peak memory 218524 kb
Host smart-349f00cb-41b1-40d4-a1ff-bd42c5a3bb36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776831993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.3776831993
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1338696733
Short name T896
Test name
Test status
Simulation time 43411795 ps
CPU time 1.13 seconds
Started Jul 02 09:05:35 AM PDT 24
Finished Jul 02 09:05:37 AM PDT 24
Peak memory 219064 kb
Host smart-231ee66a-c516-4cc1-8507-a2bdc7a7584f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338696733 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.1338696733
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2030845373
Short name T216
Test name
Test status
Simulation time 15276401 ps
CPU time 0.86 seconds
Started Jul 02 09:05:43 AM PDT 24
Finished Jul 02 09:05:45 AM PDT 24
Peak memory 208972 kb
Host smart-b43e5877-6330-47a4-a387-23c114516ef1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030845373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.2030845373
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1404279628
Short name T968
Test name
Test status
Simulation time 3875089209 ps
CPU time 4.96 seconds
Started Jul 02 09:05:37 AM PDT 24
Finished Jul 02 09:05:43 AM PDT 24
Peak memory 209116 kb
Host smart-b8d6f646-faa1-40ef-b19d-b82aae55a0c5
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404279628 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.1404279628
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.467443994
Short name T129
Test name
Test status
Simulation time 593457028 ps
CPU time 14.22 seconds
Started Jul 02 09:05:50 AM PDT 24
Finished Jul 02 09:06:10 AM PDT 24
Peak memory 217052 kb
Host smart-93c831f0-127a-46d6-93d5-c7b7837e7f15
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467443994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.467443994
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.4072727752
Short name T229
Test name
Test status
Simulation time 8870680178 ps
CPU time 15.77 seconds
Started Jul 02 09:05:39 AM PDT 24
Finished Jul 02 09:05:55 AM PDT 24
Peak memory 209288 kb
Host smart-dcd38654-109e-43c5-9bec-b3297bf54a90
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072727752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.4072727752
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.272467601
Short name T871
Test name
Test status
Simulation time 344556084 ps
CPU time 3.01 seconds
Started Jul 02 09:06:02 AM PDT 24
Finished Jul 02 09:06:08 AM PDT 24
Peak memory 217432 kb
Host smart-0590b128-fbc5-4696-a480-d1c70f8c2e63
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272467601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.272467601
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2799197913
Short name T941
Test name
Test status
Simulation time 203576557 ps
CPU time 3.56 seconds
Started Jul 02 09:05:58 AM PDT 24
Finished Jul 02 09:06:04 AM PDT 24
Peak memory 217632 kb
Host smart-74e423c6-0dc1-4e0d-9f6b-3d4214f4935f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279919
7913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2799197913
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3837562436
Short name T935
Test name
Test status
Simulation time 91914361 ps
CPU time 1.62 seconds
Started Jul 02 09:05:50 AM PDT 24
Finished Jul 02 09:05:57 AM PDT 24
Peak memory 209104 kb
Host smart-5dd0ae7f-b4e0-4803-a224-b54c9623c823
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837562436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.3837562436
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2708740028
Short name T954
Test name
Test status
Simulation time 140754722 ps
CPU time 1.05 seconds
Started Jul 02 09:05:34 AM PDT 24
Finished Jul 02 09:05:36 AM PDT 24
Peak memory 209376 kb
Host smart-b2713796-2cbd-45f7-80d3-6ff958b3561b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708740028 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.2708740028
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1326634777
Short name T984
Test name
Test status
Simulation time 29533076 ps
CPU time 1.08 seconds
Started Jul 02 09:05:34 AM PDT 24
Finished Jul 02 09:05:36 AM PDT 24
Peak memory 209296 kb
Host smart-4adfd9ba-0e29-4f86-919c-3408ee0f991a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326634777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.1326634777
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1144178125
Short name T923
Test name
Test status
Simulation time 89109607 ps
CPU time 3.5 seconds
Started Jul 02 09:05:37 AM PDT 24
Finished Jul 02 09:05:41 AM PDT 24
Peak memory 217740 kb
Host smart-b34de556-de5c-4313-9fa0-543d6522e5ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144178125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.1144178125
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2798127381
Short name T154
Test name
Test status
Simulation time 241559250 ps
CPU time 1.82 seconds
Started Jul 02 09:05:37 AM PDT 24
Finished Jul 02 09:05:40 AM PDT 24
Peak memory 221992 kb
Host smart-c012a22d-2071-4147-a6f2-6b721678c31e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798127381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.2798127381
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2746207675
Short name T986
Test name
Test status
Simulation time 16964826 ps
CPU time 1.23 seconds
Started Jul 02 09:05:49 AM PDT 24
Finished Jul 02 09:05:56 AM PDT 24
Peak memory 218132 kb
Host smart-b85a724f-acff-49a6-8de9-71f8f796c122
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746207675 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.2746207675
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.249289068
Short name T907
Test name
Test status
Simulation time 55708225 ps
CPU time 1.08 seconds
Started Jul 02 09:05:39 AM PDT 24
Finished Jul 02 09:05:41 AM PDT 24
Peak memory 209304 kb
Host smart-b6ae0fda-bc3c-42a5-ab32-639930bfd443
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249289068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.249289068
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3572128929
Short name T869
Test name
Test status
Simulation time 39099702 ps
CPU time 1.64 seconds
Started Jul 02 09:05:44 AM PDT 24
Finished Jul 02 09:05:46 AM PDT 24
Peak memory 209132 kb
Host smart-dc318dcf-36f3-4957-ad8f-221c2a45b83f
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572128929 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.3572128929
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3852675424
Short name T887
Test name
Test status
Simulation time 3698246473 ps
CPU time 9.24 seconds
Started Jul 02 09:05:41 AM PDT 24
Finished Jul 02 09:05:51 AM PDT 24
Peak memory 209304 kb
Host smart-d708a1f8-b0a5-44a8-8db3-d02cff034a0c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852675424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.3852675424
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.4281904289
Short name T932
Test name
Test status
Simulation time 4906845430 ps
CPU time 27.68 seconds
Started Jul 02 09:05:50 AM PDT 24
Finished Jul 02 09:06:23 AM PDT 24
Peak memory 217436 kb
Host smart-c32b4ee9-7fea-435d-bdd9-a5ef15adc8fb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281904289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.4281904289
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1047895695
Short name T157
Test name
Test status
Simulation time 801136372 ps
CPU time 4.79 seconds
Started Jul 02 09:05:50 AM PDT 24
Finished Jul 02 09:06:00 AM PDT 24
Peak memory 210888 kb
Host smart-e1c109c4-5e32-497f-abd9-20951698baf2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047895695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.1047895695
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3044914004
Short name T199
Test name
Test status
Simulation time 1371786458 ps
CPU time 6.67 seconds
Started Jul 02 09:05:44 AM PDT 24
Finished Jul 02 09:05:51 AM PDT 24
Peak memory 218576 kb
Host smart-bef9b52a-0bef-44a2-a339-a24dc4597fcd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304491
4004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3044914004
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.2407217583
Short name T156
Test name
Test status
Simulation time 99602673 ps
CPU time 1.96 seconds
Started Jul 02 09:05:39 AM PDT 24
Finished Jul 02 09:05:42 AM PDT 24
Peak memory 209244 kb
Host smart-19d57132-1f26-4f9a-856a-8775be282bbd
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407217583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.2407217583
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.4030160200
Short name T913
Test name
Test status
Simulation time 40137630 ps
CPU time 1.26 seconds
Started Jul 02 09:05:34 AM PDT 24
Finished Jul 02 09:05:36 AM PDT 24
Peak memory 209472 kb
Host smart-5e837154-7d24-4313-a59f-e620a999e0b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030160200 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.4030160200
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3835586752
Short name T943
Test name
Test status
Simulation time 46993141 ps
CPU time 1.36 seconds
Started Jul 02 09:05:36 AM PDT 24
Finished Jul 02 09:05:38 AM PDT 24
Peak memory 209264 kb
Host smart-e3c5cd56-e5f5-4d2b-a374-e58101bcc408
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835586752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.3835586752
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.192876079
Short name T942
Test name
Test status
Simulation time 215432897 ps
CPU time 2.01 seconds
Started Jul 02 09:05:47 AM PDT 24
Finished Jul 02 09:05:53 AM PDT 24
Peak memory 217496 kb
Host smart-a0aea860-dfb4-43ae-9d49-32377bbb1e72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192876079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.192876079
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2701854659
Short name T898
Test name
Test status
Simulation time 74260088 ps
CPU time 1.77 seconds
Started Jul 02 09:05:58 AM PDT 24
Finished Jul 02 09:06:03 AM PDT 24
Peak memory 219476 kb
Host smart-ef54bbf7-869d-42db-8004-52c5121f5465
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701854659 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.2701854659
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2950663900
Short name T970
Test name
Test status
Simulation time 17836188 ps
CPU time 1.17 seconds
Started Jul 02 09:05:40 AM PDT 24
Finished Jul 02 09:05:41 AM PDT 24
Peak memory 209004 kb
Host smart-71c536fd-937d-4cae-932c-e0e5e65e5f5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950663900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.2950663900
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1362260976
Short name T906
Test name
Test status
Simulation time 20565886 ps
CPU time 0.89 seconds
Started Jul 02 09:05:48 AM PDT 24
Finished Jul 02 09:05:53 AM PDT 24
Peak memory 209096 kb
Host smart-9434c424-8af3-4479-9940-20166f405e01
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362260976 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.1362260976
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2574183314
Short name T874
Test name
Test status
Simulation time 487440982 ps
CPU time 11.37 seconds
Started Jul 02 09:05:52 AM PDT 24
Finished Jul 02 09:06:08 AM PDT 24
Peak memory 209224 kb
Host smart-e0902dd6-3235-4ab8-9a0c-32db5d4506ae
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574183314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.2574183314
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2142135228
Short name T876
Test name
Test status
Simulation time 1788897074 ps
CPU time 9.41 seconds
Started Jul 02 09:05:36 AM PDT 24
Finished Jul 02 09:05:46 AM PDT 24
Peak memory 209220 kb
Host smart-aa596d21-1fda-46ab-b10d-ace9624910ca
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142135228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.2142135228
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.609612341
Short name T944
Test name
Test status
Simulation time 371768844 ps
CPU time 3.44 seconds
Started Jul 02 09:05:45 AM PDT 24
Finished Jul 02 09:05:51 AM PDT 24
Peak memory 210928 kb
Host smart-589428b8-6f5e-4ade-b753-1a46e3cb3fdd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609612341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.609612341
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4017897645
Short name T937
Test name
Test status
Simulation time 79062381 ps
CPU time 2.69 seconds
Started Jul 02 09:05:37 AM PDT 24
Finished Jul 02 09:05:41 AM PDT 24
Peak memory 217548 kb
Host smart-58c14f32-de51-4298-9320-94cff0c616d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401789
7645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4017897645
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3522560829
Short name T870
Test name
Test status
Simulation time 1169248760 ps
CPU time 1.48 seconds
Started Jul 02 09:05:38 AM PDT 24
Finished Jul 02 09:05:40 AM PDT 24
Peak memory 209180 kb
Host smart-c910b5ef-9ece-4c3f-a36f-e68aa4a1780a
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522560829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.3522560829
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1984465222
Short name T226
Test name
Test status
Simulation time 32182516 ps
CPU time 1.11 seconds
Started Jul 02 09:05:51 AM PDT 24
Finished Jul 02 09:05:58 AM PDT 24
Peak memory 209292 kb
Host smart-d077569c-529a-4909-afd3-2a776f55af85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984465222 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.1984465222
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.251978984
Short name T227
Test name
Test status
Simulation time 16918176 ps
CPU time 0.98 seconds
Started Jul 02 09:05:46 AM PDT 24
Finished Jul 02 09:05:49 AM PDT 24
Peak memory 209264 kb
Host smart-0f4abbdc-f4b5-4dbc-b88a-34cd3362e7c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251978984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
same_csr_outstanding.251978984
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.2189098057
Short name T897
Test name
Test status
Simulation time 47789943 ps
CPU time 3.51 seconds
Started Jul 02 09:05:42 AM PDT 24
Finished Jul 02 09:05:46 AM PDT 24
Peak memory 217532 kb
Host smart-719a20b0-cab7-4e1d-b1ed-6bfd2a2b5fd3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189098057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.2189098057
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.290821250
Short name T140
Test name
Test status
Simulation time 47875506 ps
CPU time 2.02 seconds
Started Jul 02 09:05:46 AM PDT 24
Finished Jul 02 09:05:51 AM PDT 24
Peak memory 221964 kb
Host smart-32c671a0-a083-4d7d-b783-a8a95b37da3d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290821250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_e
rr.290821250
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3494859292
Short name T931
Test name
Test status
Simulation time 67469264 ps
CPU time 1.27 seconds
Started Jul 02 09:05:47 AM PDT 24
Finished Jul 02 09:05:52 AM PDT 24
Peak memory 218372 kb
Host smart-c6477818-6c41-4ead-a948-ee4ad0b1d45d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494859292 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.3494859292
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2029351526
Short name T916
Test name
Test status
Simulation time 29148915 ps
CPU time 1.04 seconds
Started Jul 02 09:05:41 AM PDT 24
Finished Jul 02 09:05:43 AM PDT 24
Peak memory 209336 kb
Host smart-1b03cef8-e9d0-431d-b93b-a86a06d8a38b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029351526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.2029351526
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2709079404
Short name T889
Test name
Test status
Simulation time 58510287 ps
CPU time 2.07 seconds
Started Jul 02 09:05:46 AM PDT 24
Finished Jul 02 09:05:51 AM PDT 24
Peak memory 209144 kb
Host smart-c88e9fbb-aee4-45cf-a509-2da3593713dc
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709079404 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.2709079404
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2056914845
Short name T902
Test name
Test status
Simulation time 6597199593 ps
CPU time 7.11 seconds
Started Jul 02 09:05:41 AM PDT 24
Finished Jul 02 09:05:49 AM PDT 24
Peak memory 209276 kb
Host smart-7d9c8981-02b7-479f-931b-693d36f4be7e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056914845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.2056914845
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.2148948715
Short name T993
Test name
Test status
Simulation time 2373943924 ps
CPU time 5.26 seconds
Started Jul 02 09:05:49 AM PDT 24
Finished Jul 02 09:06:00 AM PDT 24
Peak memory 209288 kb
Host smart-656a7e33-fc0c-465e-8d50-0a4bffce0814
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148948715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.2148948715
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3529273126
Short name T994
Test name
Test status
Simulation time 166835793 ps
CPU time 1.17 seconds
Started Jul 02 09:05:44 AM PDT 24
Finished Jul 02 09:05:46 AM PDT 24
Peak memory 210612 kb
Host smart-9e60ce39-b679-4ede-8d11-ae8e4b5885d9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529273126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.3529273126
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1675514006
Short name T190
Test name
Test status
Simulation time 189784910 ps
CPU time 1.4 seconds
Started Jul 02 09:05:46 AM PDT 24
Finished Jul 02 09:05:50 AM PDT 24
Peak memory 217580 kb
Host smart-60161c48-49cc-4f9e-af6b-f0ed40a87f7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167551
4006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1675514006
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3667969736
Short name T940
Test name
Test status
Simulation time 108964493 ps
CPU time 1.7 seconds
Started Jul 02 09:05:48 AM PDT 24
Finished Jul 02 09:05:54 AM PDT 24
Peak memory 209228 kb
Host smart-9bee820c-2fa5-429e-aed9-9f86224b154f
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667969736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.3667969736
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.896215037
Short name T953
Test name
Test status
Simulation time 200704100 ps
CPU time 2.04 seconds
Started Jul 02 09:05:42 AM PDT 24
Finished Jul 02 09:05:46 AM PDT 24
Peak memory 211364 kb
Host smart-a0df2921-a7b3-4fba-a701-c70abf222de6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896215037 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.896215037
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.782091873
Short name T220
Test name
Test status
Simulation time 23860960 ps
CPU time 1.03 seconds
Started Jul 02 09:05:41 AM PDT 24
Finished Jul 02 09:05:43 AM PDT 24
Peak memory 217540 kb
Host smart-6770028a-63e9-477c-a860-b43ff80182dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782091873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
same_csr_outstanding.782091873
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.756298307
Short name T137
Test name
Test status
Simulation time 171416897 ps
CPU time 5.88 seconds
Started Jul 02 09:05:41 AM PDT 24
Finished Jul 02 09:05:48 AM PDT 24
Peak memory 217496 kb
Host smart-8a764e6b-5104-4da2-99e7-e2bad54da5a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756298307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.756298307
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2970043969
Short name T136
Test name
Test status
Simulation time 311771185 ps
CPU time 3.79 seconds
Started Jul 02 09:05:45 AM PDT 24
Finished Jul 02 09:05:50 AM PDT 24
Peak memory 217616 kb
Host smart-906978e9-7db3-47c9-bb3d-0b36abe2c7f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970043969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.2970043969
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.606727133
Short name T928
Test name
Test status
Simulation time 46464301 ps
CPU time 1.14 seconds
Started Jul 02 09:05:47 AM PDT 24
Finished Jul 02 09:05:52 AM PDT 24
Peak memory 217708 kb
Host smart-4f55b386-0302-42e2-929d-5fa73392bcb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606727133 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.606727133
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1073828724
Short name T962
Test name
Test status
Simulation time 45226326 ps
CPU time 0.97 seconds
Started Jul 02 09:05:45 AM PDT 24
Finished Jul 02 09:05:47 AM PDT 24
Peak memory 209024 kb
Host smart-d9a879a1-8e08-4dc0-b550-eb1b02435e4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073828724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.1073828724
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1044310416
Short name T958
Test name
Test status
Simulation time 104492386 ps
CPU time 1.18 seconds
Started Jul 02 09:05:40 AM PDT 24
Finished Jul 02 09:05:41 AM PDT 24
Peak memory 209124 kb
Host smart-c0c2ac9c-7982-40fc-8ec2-e508ef3ef03b
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044310416 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.1044310416
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2513095122
Short name T964
Test name
Test status
Simulation time 227216961 ps
CPU time 3.2 seconds
Started Jul 02 09:05:41 AM PDT 24
Finished Jul 02 09:05:45 AM PDT 24
Peak memory 209220 kb
Host smart-2977edb4-4c57-46b8-aa0a-7487c058e8df
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513095122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.2513095122
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.863923103
Short name T990
Test name
Test status
Simulation time 1653335629 ps
CPU time 7.4 seconds
Started Jul 02 09:05:46 AM PDT 24
Finished Jul 02 09:05:57 AM PDT 24
Peak memory 209212 kb
Host smart-11d09ca0-1bae-4ce5-8ef7-26d4cd954ac4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863923103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.863923103
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1951087458
Short name T965
Test name
Test status
Simulation time 292077620 ps
CPU time 1.46 seconds
Started Jul 02 09:05:47 AM PDT 24
Finished Jul 02 09:05:52 AM PDT 24
Peak memory 210668 kb
Host smart-35bafb7e-5684-4c1e-98d7-434e09ebbcd6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951087458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.1951087458
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.710868613
Short name T926
Test name
Test status
Simulation time 95019828 ps
CPU time 2.25 seconds
Started Jul 02 09:05:47 AM PDT 24
Finished Jul 02 09:05:53 AM PDT 24
Peak memory 217596 kb
Host smart-8c2b8854-e85b-454a-8a91-feea12167cba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710868
613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.710868613
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1241914244
Short name T933
Test name
Test status
Simulation time 694545944 ps
CPU time 2.13 seconds
Started Jul 02 09:05:49 AM PDT 24
Finished Jul 02 09:05:57 AM PDT 24
Peak memory 209224 kb
Host smart-b1974fea-91b0-400c-b942-f3524248ad2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241914244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.1241914244
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.389285765
Short name T890
Test name
Test status
Simulation time 106256343 ps
CPU time 1.38 seconds
Started Jul 02 09:05:47 AM PDT 24
Finished Jul 02 09:05:52 AM PDT 24
Peak memory 217468 kb
Host smart-8b439cbb-905e-4da0-90b8-8ae394a0607b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389285765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
same_csr_outstanding.389285765
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1378679694
Short name T920
Test name
Test status
Simulation time 203926114 ps
CPU time 2.9 seconds
Started Jul 02 09:05:49 AM PDT 24
Finished Jul 02 09:05:58 AM PDT 24
Peak memory 217480 kb
Host smart-c38e6b8e-17b0-4d89-a138-401f3ec78131
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378679694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.1378679694
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2863708695
Short name T145
Test name
Test status
Simulation time 498832210 ps
CPU time 2.28 seconds
Started Jul 02 09:05:46 AM PDT 24
Finished Jul 02 09:05:52 AM PDT 24
Peak memory 221272 kb
Host smart-1633a915-154b-4465-8b10-3d286f9283f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863708695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.2863708695
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.3065104840
Short name T15
Test name
Test status
Simulation time 44552749 ps
CPU time 0.97 seconds
Started Jul 02 09:40:01 AM PDT 24
Finished Jul 02 09:40:03 AM PDT 24
Peak memory 208560 kb
Host smart-d65ca452-ac00-43b6-a235-0c38282d1068
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065104840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.3065104840
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.83382661
Short name T248
Test name
Test status
Simulation time 10720542 ps
CPU time 0.99 seconds
Started Jul 02 09:39:58 AM PDT 24
Finished Jul 02 09:40:01 AM PDT 24
Peak memory 208480 kb
Host smart-333ba7a4-d167-4524-9135-e0e27bead053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83382661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.83382661
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.2925785223
Short name T300
Test name
Test status
Simulation time 370099915 ps
CPU time 11.53 seconds
Started Jul 02 09:40:10 AM PDT 24
Finished Jul 02 09:40:23 AM PDT 24
Peak memory 217532 kb
Host smart-d69763ad-7309-41a4-a243-29ea818f97fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925785223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.2925785223
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.922017236
Short name T7
Test name
Test status
Simulation time 431356460 ps
CPU time 5.74 seconds
Started Jul 02 09:39:56 AM PDT 24
Finished Jul 02 09:40:03 AM PDT 24
Peak memory 216760 kb
Host smart-fa3961eb-0b46-4c4c-9fc6-4aaa3a42d203
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922017236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.922017236
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.3776281398
Short name T704
Test name
Test status
Simulation time 1874405345 ps
CPU time 31.86 seconds
Started Jul 02 09:39:58 AM PDT 24
Finished Jul 02 09:40:32 AM PDT 24
Peak memory 217780 kb
Host smart-50d16b8a-8b2d-4acb-af40-55523601cc29
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776281398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.3776281398
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.2949740388
Short name T206
Test name
Test status
Simulation time 805878315 ps
CPU time 3.6 seconds
Started Jul 02 09:40:09 AM PDT 24
Finished Jul 02 09:40:14 AM PDT 24
Peak memory 217084 kb
Host smart-ab04283a-b76d-4e5d-81a0-9ad52a207876
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949740388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.2
949740388
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.3782708690
Short name T448
Test name
Test status
Simulation time 418200701 ps
CPU time 7.01 seconds
Started Jul 02 09:40:09 AM PDT 24
Finished Jul 02 09:40:18 AM PDT 24
Peak memory 217708 kb
Host smart-e25236c9-9f91-44bf-8f75-41a7f298dc4d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782708690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.3782708690
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.2027212731
Short name T81
Test name
Test status
Simulation time 15216672341 ps
CPU time 15.33 seconds
Started Jul 02 09:40:09 AM PDT 24
Finished Jul 02 09:40:26 AM PDT 24
Peak memory 217184 kb
Host smart-fa328315-69bb-4079-9e44-4b5c8fba3da0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027212731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.2027212731
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.3277559089
Short name T508
Test name
Test status
Simulation time 272054163 ps
CPU time 8.21 seconds
Started Jul 02 09:40:09 AM PDT 24
Finished Jul 02 09:40:19 AM PDT 24
Peak memory 216988 kb
Host smart-10b4383f-a2bf-4253-bbe7-0cfe3797b3db
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277559089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
3277559089
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.1923819698
Short name T559
Test name
Test status
Simulation time 1026221895 ps
CPU time 36.67 seconds
Started Jul 02 09:39:58 AM PDT 24
Finished Jul 02 09:40:37 AM PDT 24
Peak memory 266836 kb
Host smart-08787aea-bd72-41d7-8df4-248c5ffadaf0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923819698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.1923819698
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.2007364896
Short name T275
Test name
Test status
Simulation time 401637324 ps
CPU time 12.26 seconds
Started Jul 02 09:39:58 AM PDT 24
Finished Jul 02 09:40:13 AM PDT 24
Peak memory 250596 kb
Host smart-c9ba3e55-81de-47a3-855a-2e716fa35aa8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007364896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.2007364896
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.1098551724
Short name T769
Test name
Test status
Simulation time 84571614 ps
CPU time 2.96 seconds
Started Jul 02 09:39:59 AM PDT 24
Finished Jul 02 09:40:04 AM PDT 24
Peak memory 217780 kb
Host smart-7f8750f8-024f-4ae1-adbf-869c48596830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098551724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.1098551724
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.3869774207
Short name T855
Test name
Test status
Simulation time 1053535797 ps
CPU time 10.24 seconds
Started Jul 02 09:40:09 AM PDT 24
Finished Jul 02 09:40:21 AM PDT 24
Peak memory 217220 kb
Host smart-0a41d361-f450-4702-96eb-918180fa40a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869774207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.3869774207
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.3146984848
Short name T107
Test name
Test status
Simulation time 239912496 ps
CPU time 23.06 seconds
Started Jul 02 09:40:00 AM PDT 24
Finished Jul 02 09:40:24 AM PDT 24
Peak memory 269220 kb
Host smart-88523c7c-bde1-4ec4-b873-0d8ff72517dd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146984848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.3146984848
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.582702320
Short name T485
Test name
Test status
Simulation time 914033754 ps
CPU time 11.77 seconds
Started Jul 02 09:39:58 AM PDT 24
Finished Jul 02 09:40:12 AM PDT 24
Peak memory 217888 kb
Host smart-94699875-ef91-4bc3-ba63-67c3f78abc65
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582702320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.582702320
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.4195263688
Short name T664
Test name
Test status
Simulation time 508318591 ps
CPU time 10.77 seconds
Started Jul 02 09:39:58 AM PDT 24
Finished Jul 02 09:40:11 AM PDT 24
Peak memory 225504 kb
Host smart-bc8bf73f-81a9-4f4b-8a13-9fbcc3f62a10
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195263688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.4195263688
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.2258010021
Short name T112
Test name
Test status
Simulation time 3267569424 ps
CPU time 9.32 seconds
Started Jul 02 09:40:10 AM PDT 24
Finished Jul 02 09:40:20 AM PDT 24
Peak memory 217644 kb
Host smart-21b035e5-3512-4d34-b8ab-4cfe3502bce7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258010021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.2
258010021
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.1882317700
Short name T320
Test name
Test status
Simulation time 278808313 ps
CPU time 10.03 seconds
Started Jul 02 09:39:58 AM PDT 24
Finished Jul 02 09:40:10 AM PDT 24
Peak memory 224504 kb
Host smart-a94ea189-e231-498e-b982-385e49a48a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882317700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.1882317700
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.530198442
Short name T866
Test name
Test status
Simulation time 104204051 ps
CPU time 1.25 seconds
Started Jul 02 09:39:58 AM PDT 24
Finished Jul 02 09:40:01 AM PDT 24
Peak memory 213192 kb
Host smart-80c2663a-3e5a-4330-b6f8-d9e4601a6773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530198442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.530198442
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.1980544708
Short name T284
Test name
Test status
Simulation time 852983794 ps
CPU time 16.49 seconds
Started Jul 02 09:39:56 AM PDT 24
Finished Jul 02 09:40:14 AM PDT 24
Peak memory 250512 kb
Host smart-18fe51f2-a137-4f05-acaa-a8ad71b68687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980544708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.1980544708
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.2245946038
Short name T249
Test name
Test status
Simulation time 83207740 ps
CPU time 4.31 seconds
Started Jul 02 09:39:59 AM PDT 24
Finished Jul 02 09:40:05 AM PDT 24
Peak memory 225960 kb
Host smart-bd8d26e8-a6fe-47b1-ab54-fa2629072e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245946038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.2245946038
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.3598382334
Short name T733
Test name
Test status
Simulation time 5677788068 ps
CPU time 241.68 seconds
Started Jul 02 09:40:02 AM PDT 24
Finished Jul 02 09:44:05 AM PDT 24
Peak memory 250536 kb
Host smart-9c9a5cb9-4c46-47f8-b53d-0aeb42f9bca6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598382334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.3598382334
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.3712156231
Short name T606
Test name
Test status
Simulation time 39637599 ps
CPU time 0.76 seconds
Started Jul 02 09:39:58 AM PDT 24
Finished Jul 02 09:40:01 AM PDT 24
Peak memory 208212 kb
Host smart-1adf9cf1-ba47-4927-a7fc-7d005cf9b08e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712156231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.3712156231
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.2775739974
Short name T538
Test name
Test status
Simulation time 51384143 ps
CPU time 1.06 seconds
Started Jul 02 09:40:05 AM PDT 24
Finished Jul 02 09:40:07 AM PDT 24
Peak memory 208636 kb
Host smart-e456b65a-3675-476e-9839-0d81e85d3eea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775739974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.2775739974
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.161282685
Short name T80
Test name
Test status
Simulation time 22460295 ps
CPU time 0.95 seconds
Started Jul 02 09:40:03 AM PDT 24
Finished Jul 02 09:40:05 AM PDT 24
Peak memory 208464 kb
Host smart-ddc4c2e6-f35b-4085-a1c5-5d4e0158c537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161282685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.161282685
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.1741225900
Short name T367
Test name
Test status
Simulation time 319180862 ps
CPU time 10.06 seconds
Started Jul 02 09:40:02 AM PDT 24
Finished Jul 02 09:40:13 AM PDT 24
Peak memory 217772 kb
Host smart-ecb1f5e4-0b9b-46f0-aaca-2ef7051936f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741225900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.1741225900
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.2888098060
Short name T396
Test name
Test status
Simulation time 252407363 ps
CPU time 3.26 seconds
Started Jul 02 09:40:03 AM PDT 24
Finished Jul 02 09:40:07 AM PDT 24
Peak memory 217144 kb
Host smart-eb4ef0d2-a38b-48aa-9104-ebc7647ec419
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888098060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.2888098060
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.751745542
Short name T374
Test name
Test status
Simulation time 1810118153 ps
CPU time 51.37 seconds
Started Jul 02 09:40:01 AM PDT 24
Finished Jul 02 09:40:53 AM PDT 24
Peak memory 217672 kb
Host smart-fdd35da7-9ebc-43b3-afc5-919500cd60a0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751745542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_err
ors.751745542
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.2619623443
Short name T340
Test name
Test status
Simulation time 6130091257 ps
CPU time 35.3 seconds
Started Jul 02 09:39:59 AM PDT 24
Finished Jul 02 09:40:36 AM PDT 24
Peak memory 217300 kb
Host smart-1c3ca56f-98af-42b7-bdbb-1a891f4a1c84
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619623443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.2
619623443
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.3197843100
Short name T395
Test name
Test status
Simulation time 2302535627 ps
CPU time 9.84 seconds
Started Jul 02 09:40:05 AM PDT 24
Finished Jul 02 09:40:15 AM PDT 24
Peak memory 223824 kb
Host smart-9a994e96-36b4-47a6-a3b2-a33c664b0b58
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197843100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.3197843100
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.1191239655
Short name T345
Test name
Test status
Simulation time 1881118864 ps
CPU time 11.71 seconds
Started Jul 02 09:40:01 AM PDT 24
Finished Jul 02 09:40:14 AM PDT 24
Peak memory 217140 kb
Host smart-36319e75-4a59-40aa-a680-81b775485333
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191239655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.1191239655
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.2582425837
Short name T348
Test name
Test status
Simulation time 274547755 ps
CPU time 8.4 seconds
Started Jul 02 09:40:00 AM PDT 24
Finished Jul 02 09:40:10 AM PDT 24
Peak memory 217068 kb
Host smart-0391edc4-e62b-4420-9afa-9b3ac7258b9d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582425837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
2582425837
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.2453181077
Short name T316
Test name
Test status
Simulation time 1748258766 ps
CPU time 44.71 seconds
Started Jul 02 09:40:05 AM PDT 24
Finished Jul 02 09:40:51 AM PDT 24
Peak memory 283192 kb
Host smart-c9bc41ef-02d3-496d-856f-ec151fb57c9b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453181077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.2453181077
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.650366011
Short name T271
Test name
Test status
Simulation time 9980885914 ps
CPU time 22.4 seconds
Started Jul 02 09:40:03 AM PDT 24
Finished Jul 02 09:40:26 AM PDT 24
Peak memory 250532 kb
Host smart-6bdbecf7-ee21-40fc-9d77-845ca31c24f4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650366011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_j
tag_state_post_trans.650366011
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.904584346
Short name T314
Test name
Test status
Simulation time 81530875 ps
CPU time 1.83 seconds
Started Jul 02 09:40:00 AM PDT 24
Finished Jul 02 09:40:03 AM PDT 24
Peak memory 217804 kb
Host smart-acd783a5-9673-4bec-a8e0-4dd2a275af1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904584346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.904584346
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.1591801465
Short name T205
Test name
Test status
Simulation time 563003535 ps
CPU time 9.73 seconds
Started Jul 02 09:40:00 AM PDT 24
Finished Jul 02 09:40:12 AM PDT 24
Peak memory 225580 kb
Host smart-eb34224d-0e77-404c-ab50-6d7d6c987fa4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591801465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.1591801465
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.2189712904
Short name T784
Test name
Test status
Simulation time 1434379573 ps
CPU time 15.52 seconds
Started Jul 02 09:40:01 AM PDT 24
Finished Jul 02 09:40:18 AM PDT 24
Peak memory 225500 kb
Host smart-bff4f102-b901-44a4-b79f-d02a6e978641
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189712904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.2189712904
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.3853892542
Short name T301
Test name
Test status
Simulation time 683609953 ps
CPU time 12.67 seconds
Started Jul 02 09:40:01 AM PDT 24
Finished Jul 02 09:40:15 AM PDT 24
Peak memory 217736 kb
Host smart-c8399df7-54f9-4ae7-be6f-a91abbbca7cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853892542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.3
853892542
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.1121761416
Short name T191
Test name
Test status
Simulation time 224001751 ps
CPU time 6.31 seconds
Started Jul 02 09:40:02 AM PDT 24
Finished Jul 02 09:40:10 AM PDT 24
Peak memory 217848 kb
Host smart-bcfbcaed-0e87-4758-b098-e8f81c8d95e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121761416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.1121761416
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.1672782821
Short name T556
Test name
Test status
Simulation time 196302904 ps
CPU time 2.46 seconds
Started Jul 02 09:40:02 AM PDT 24
Finished Jul 02 09:40:06 AM PDT 24
Peak memory 223000 kb
Host smart-fe93424a-5a6e-4a44-bc6f-890238207af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672782821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.1672782821
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.2076061006
Short name T336
Test name
Test status
Simulation time 485785981 ps
CPU time 26.9 seconds
Started Jul 02 09:40:00 AM PDT 24
Finished Jul 02 09:40:28 AM PDT 24
Peak memory 250512 kb
Host smart-415aac69-2c52-4a53-b02f-be2938b31761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076061006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.2076061006
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.1998092033
Short name T381
Test name
Test status
Simulation time 503192830 ps
CPU time 4.01 seconds
Started Jul 02 09:40:02 AM PDT 24
Finished Jul 02 09:40:07 AM PDT 24
Peak memory 222236 kb
Host smart-101920f6-1d6e-4eb9-b2ef-f3169ab19e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998092033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.1998092033
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.3777105010
Short name T677
Test name
Test status
Simulation time 918882664 ps
CPU time 19.03 seconds
Started Jul 02 09:40:04 AM PDT 24
Finished Jul 02 09:40:24 AM PDT 24
Peak memory 250464 kb
Host smart-b95daccd-7007-4dc9-ba7e-05b8fe3e2128
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777105010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.3777105010
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.1374502077
Short name T163
Test name
Test status
Simulation time 73959212220 ps
CPU time 479.45 seconds
Started Jul 02 09:40:01 AM PDT 24
Finished Jul 02 09:48:02 AM PDT 24
Peak memory 447320 kb
Host smart-2c7efce3-e6d8-472b-a1d2-e4b39f9fc37e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1374502077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all_with_rand_reset.1374502077
Directory /workspace/1.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2497388531
Short name T529
Test name
Test status
Simulation time 76550110 ps
CPU time 1.01 seconds
Started Jul 02 09:40:02 AM PDT 24
Finished Jul 02 09:40:04 AM PDT 24
Peak memory 211440 kb
Host smart-4da577dd-9bfb-47b0-9227-50365a42f9ae
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497388531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.2497388531
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.738350440
Short name T837
Test name
Test status
Simulation time 24036603 ps
CPU time 0.91 seconds
Started Jul 02 09:40:45 AM PDT 24
Finished Jul 02 09:40:48 AM PDT 24
Peak memory 208516 kb
Host smart-c271721a-c972-414b-bc14-649c1d96c83d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738350440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.738350440
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.954000702
Short name T591
Test name
Test status
Simulation time 2417089431 ps
CPU time 10.03 seconds
Started Jul 02 09:40:41 AM PDT 24
Finished Jul 02 09:40:52 AM PDT 24
Peak memory 225648 kb
Host smart-bbf85347-bfec-46eb-94f7-68438ece9186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954000702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.954000702
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.2800361861
Short name T582
Test name
Test status
Simulation time 296827393 ps
CPU time 2.39 seconds
Started Jul 02 09:40:41 AM PDT 24
Finished Jul 02 09:40:44 AM PDT 24
Peak memory 217188 kb
Host smart-d61d2abc-6a64-42d6-afbf-72a21e961b1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800361861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.2800361861
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.1102020046
Short name T1
Test name
Test status
Simulation time 3743094926 ps
CPU time 52.83 seconds
Started Jul 02 09:40:44 AM PDT 24
Finished Jul 02 09:41:38 AM PDT 24
Peak memory 218420 kb
Host smart-324c8855-3f33-4944-bbd0-265e3bc8577e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102020046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.1102020046
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.3236958358
Short name T841
Test name
Test status
Simulation time 2022736848 ps
CPU time 5.02 seconds
Started Jul 02 09:40:43 AM PDT 24
Finished Jul 02 09:40:48 AM PDT 24
Peak memory 217752 kb
Host smart-46b7802b-f6c2-45fa-aca4-15410bb096d9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236958358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.3236958358
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.762939756
Short name T663
Test name
Test status
Simulation time 352951848 ps
CPU time 10 seconds
Started Jul 02 09:40:41 AM PDT 24
Finished Jul 02 09:40:52 AM PDT 24
Peak memory 217216 kb
Host smart-20687d04-1d5a-4deb-bff7-44d58896f01e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762939756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke.
762939756
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.3017467
Short name T193
Test name
Test status
Simulation time 6416330495 ps
CPU time 48.1 seconds
Started Jul 02 09:40:42 AM PDT 24
Finished Jul 02 09:41:30 AM PDT 24
Peak memory 275600 kb
Host smart-15010873-7467-433e-a6aa-f04c0ac8947e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_st
ate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_
state_failure.3017467
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.2481594986
Short name T739
Test name
Test status
Simulation time 531694900 ps
CPU time 14.05 seconds
Started Jul 02 09:40:43 AM PDT 24
Finished Jul 02 09:40:58 AM PDT 24
Peak memory 250412 kb
Host smart-d06211f3-1e3e-49b6-95b5-6572da13e9e6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481594986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.2481594986
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.3364676129
Short name T565
Test name
Test status
Simulation time 112765546 ps
CPU time 2.39 seconds
Started Jul 02 09:40:43 AM PDT 24
Finished Jul 02 09:40:46 AM PDT 24
Peak memory 221848 kb
Host smart-f8de647e-28f1-4150-9502-139ffe1cca1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364676129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.3364676129
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.3253822087
Short name T764
Test name
Test status
Simulation time 314736012 ps
CPU time 14.93 seconds
Started Jul 02 09:40:44 AM PDT 24
Finished Jul 02 09:41:00 AM PDT 24
Peak memory 218420 kb
Host smart-0d4e7533-7fa0-4685-8d6c-f30061574e94
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253822087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.3253822087
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.3803292260
Short name T295
Test name
Test status
Simulation time 1442693510 ps
CPU time 12.28 seconds
Started Jul 02 09:40:41 AM PDT 24
Finished Jul 02 09:40:54 AM PDT 24
Peak memory 225520 kb
Host smart-10c3d2a2-b757-413e-93c1-25edf6692166
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803292260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.3803292260
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.2863396094
Short name T860
Test name
Test status
Simulation time 231984571 ps
CPU time 8.86 seconds
Started Jul 02 09:40:42 AM PDT 24
Finished Jul 02 09:40:51 AM PDT 24
Peak memory 225540 kb
Host smart-2d7f41eb-685b-4924-aac2-99a0a55c95be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863396094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
2863396094
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.3173221589
Short name T707
Test name
Test status
Simulation time 400625955 ps
CPU time 9.04 seconds
Started Jul 02 09:40:44 AM PDT 24
Finished Jul 02 09:40:54 AM PDT 24
Peak memory 223928 kb
Host smart-87f03509-1868-4ff1-a782-efa7159d0871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173221589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.3173221589
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.3047564191
Short name T360
Test name
Test status
Simulation time 81969232 ps
CPU time 3.32 seconds
Started Jul 02 09:40:36 AM PDT 24
Finished Jul 02 09:40:41 AM PDT 24
Peak memory 217292 kb
Host smart-7b570c8a-ee91-4050-8e88-d9c0afeed6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047564191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.3047564191
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.2951483981
Short name T608
Test name
Test status
Simulation time 1315354668 ps
CPU time 27.41 seconds
Started Jul 02 09:40:36 AM PDT 24
Finished Jul 02 09:41:05 AM PDT 24
Peak memory 250524 kb
Host smart-23b4ca80-d62f-4c7f-a24e-1b0e7e878781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951483981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.2951483981
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.445443128
Short name T603
Test name
Test status
Simulation time 8798244027 ps
CPU time 287.34 seconds
Started Jul 02 09:40:46 AM PDT 24
Finished Jul 02 09:45:36 AM PDT 24
Peak memory 283336 kb
Host smart-3494eaca-a356-4b25-926e-d42e2ba35a33
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445443128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.445443128
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.741842892
Short name T325
Test name
Test status
Simulation time 47822745 ps
CPU time 0.98 seconds
Started Jul 02 09:40:38 AM PDT 24
Finished Jul 02 09:40:40 AM PDT 24
Peak memory 211452 kb
Host smart-b8f2a862-29c8-49b3-b232-95803d9afbfa
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741842892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ct
rl_volatile_unlock_smoke.741842892
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.2445294054
Short name T347
Test name
Test status
Simulation time 19952855 ps
CPU time 0.94 seconds
Started Jul 02 09:40:46 AM PDT 24
Finished Jul 02 09:40:50 AM PDT 24
Peak memory 208512 kb
Host smart-a0f86895-5b18-46ee-a5e7-56ac45c352b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445294054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.2445294054
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.1410278281
Short name T688
Test name
Test status
Simulation time 375364848 ps
CPU time 8.11 seconds
Started Jul 02 09:40:45 AM PDT 24
Finished Jul 02 09:40:54 AM PDT 24
Peak memory 225588 kb
Host smart-9a93cd79-8d78-4b3e-a0fa-afb094f871e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410278281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.1410278281
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.2772662391
Short name T833
Test name
Test status
Simulation time 395488857 ps
CPU time 5.61 seconds
Started Jul 02 09:40:45 AM PDT 24
Finished Jul 02 09:40:53 AM PDT 24
Peak memory 217312 kb
Host smart-f316b57d-e0f3-4d98-a7e9-057c8f102778
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772662391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.2772662391
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.168032075
Short name T534
Test name
Test status
Simulation time 2312107296 ps
CPU time 38.73 seconds
Started Jul 02 09:40:47 AM PDT 24
Finished Jul 02 09:41:28 AM PDT 24
Peak memory 218368 kb
Host smart-da12f0fc-2975-4efc-a543-980554a600f6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168032075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_er
rors.168032075
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.2468559033
Short name T20
Test name
Test status
Simulation time 555457540 ps
CPU time 9.04 seconds
Started Jul 02 09:40:46 AM PDT 24
Finished Jul 02 09:40:58 AM PDT 24
Peak memory 217728 kb
Host smart-5f6ce1a4-9381-49c7-9554-e4a9df405383
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468559033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.2468559033
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.2191360871
Short name T709
Test name
Test status
Simulation time 738480113 ps
CPU time 4.06 seconds
Started Jul 02 09:40:44 AM PDT 24
Finished Jul 02 09:40:49 AM PDT 24
Peak memory 217144 kb
Host smart-c203f239-d936-4cc6-8955-fe82839b4164
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191360871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.2191360871
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.399124001
Short name T355
Test name
Test status
Simulation time 2076108340 ps
CPU time 46.82 seconds
Started Jul 02 09:40:49 AM PDT 24
Finished Jul 02 09:41:38 AM PDT 24
Peak memory 250592 kb
Host smart-90913e3f-fdd1-4ac3-b65c-cb7ab67b9882
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399124001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_state_failure.399124001
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.4010337891
Short name T421
Test name
Test status
Simulation time 1685591259 ps
CPU time 8.4 seconds
Started Jul 02 09:40:48 AM PDT 24
Finished Jul 02 09:40:59 AM PDT 24
Peak memory 217660 kb
Host smart-093ddbe0-c565-4562-90a8-2686bb640beb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010337891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.4010337891
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.2965381889
Short name T401
Test name
Test status
Simulation time 65919311 ps
CPU time 2.7 seconds
Started Jul 02 09:40:45 AM PDT 24
Finished Jul 02 09:40:50 AM PDT 24
Peak memory 217784 kb
Host smart-edd7b77d-eca7-4903-b428-71e1803b55ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965381889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.2965381889
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.857123312
Short name T526
Test name
Test status
Simulation time 362012662 ps
CPU time 15.82 seconds
Started Jul 02 09:40:46 AM PDT 24
Finished Jul 02 09:41:05 AM PDT 24
Peak memory 218448 kb
Host smart-7c8fa48a-413a-4f65-9b52-127dd7bf6212
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857123312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.857123312
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.2683542558
Short name T744
Test name
Test status
Simulation time 368556064 ps
CPU time 13.35 seconds
Started Jul 02 09:40:45 AM PDT 24
Finished Jul 02 09:41:00 AM PDT 24
Peak memory 225536 kb
Host smart-9f5ee0b4-f4b5-4890-a943-b52888f893ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683542558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.2683542558
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.2598651899
Short name T672
Test name
Test status
Simulation time 312409673 ps
CPU time 9.44 seconds
Started Jul 02 09:40:45 AM PDT 24
Finished Jul 02 09:40:57 AM PDT 24
Peak memory 225504 kb
Host smart-3eccfa37-00fd-411d-9754-9b775dc59501
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598651899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
2598651899
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.498032593
Short name T440
Test name
Test status
Simulation time 1537657688 ps
CPU time 10.42 seconds
Started Jul 02 09:40:44 AM PDT 24
Finished Jul 02 09:40:55 AM PDT 24
Peak memory 225544 kb
Host smart-1957efd9-507b-4ed7-a2ca-5fe482f81744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498032593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.498032593
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.44196958
Short name T328
Test name
Test status
Simulation time 322315282 ps
CPU time 2.76 seconds
Started Jul 02 09:40:45 AM PDT 24
Finished Jul 02 09:40:49 AM PDT 24
Peak memory 214044 kb
Host smart-7b9aa496-331f-43ab-aa7c-c11a8f98d7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44196958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.44196958
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.396152224
Short name T331
Test name
Test status
Simulation time 524836469 ps
CPU time 31.61 seconds
Started Jul 02 09:40:45 AM PDT 24
Finished Jul 02 09:41:18 AM PDT 24
Peak memory 250520 kb
Host smart-09f2da8e-a6c2-4781-bebb-e8c231490d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396152224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.396152224
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.4140411060
Short name T105
Test name
Test status
Simulation time 231680926 ps
CPU time 7.55 seconds
Started Jul 02 09:40:45 AM PDT 24
Finished Jul 02 09:40:54 AM PDT 24
Peak memory 250516 kb
Host smart-bc3c4e36-1fcc-418d-b850-00a734c5ccb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140411060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.4140411060
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.61441557
Short name T296
Test name
Test status
Simulation time 27202324224 ps
CPU time 78.09 seconds
Started Jul 02 09:40:46 AM PDT 24
Finished Jul 02 09:42:07 AM PDT 24
Peak memory 280488 kb
Host smart-517f1df2-dd57-47c7-8e45-28a4a225dcb9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61441557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.lc_ctrl_stress_all.61441557
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.3560006607
Short name T568
Test name
Test status
Simulation time 46470546 ps
CPU time 0.99 seconds
Started Jul 02 09:40:47 AM PDT 24
Finished Jul 02 09:40:50 AM PDT 24
Peak memory 211348 kb
Host smart-94da00c2-f9a2-4fb1-8df6-5cdb3a9756c3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560006607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.3560006607
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.2630510327
Short name T758
Test name
Test status
Simulation time 36813135 ps
CPU time 1.12 seconds
Started Jul 02 09:40:49 AM PDT 24
Finished Jul 02 09:40:52 AM PDT 24
Peak memory 208516 kb
Host smart-901396e0-35d5-48e0-953a-5bb85836879b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630510327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.2630510327
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.3755875928
Short name T303
Test name
Test status
Simulation time 1972112163 ps
CPU time 15.01 seconds
Started Jul 02 09:40:50 AM PDT 24
Finished Jul 02 09:41:07 AM PDT 24
Peak memory 225564 kb
Host smart-a79fde0c-5130-4370-8b51-955d1b153052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755875928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.3755875928
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.3415784830
Short name T864
Test name
Test status
Simulation time 813488429 ps
CPU time 3.17 seconds
Started Jul 02 09:40:49 AM PDT 24
Finished Jul 02 09:40:55 AM PDT 24
Peak memory 216724 kb
Host smart-3dd2fc6c-0385-493a-91eb-815f369a3d50
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415784830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.3415784830
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.3847746192
Short name T528
Test name
Test status
Simulation time 1774838440 ps
CPU time 53.51 seconds
Started Jul 02 09:40:50 AM PDT 24
Finished Jul 02 09:41:46 AM PDT 24
Peak memory 218344 kb
Host smart-5af1c2e4-9a1e-4493-be6b-016f414179da
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847746192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.3847746192
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.1321409383
Short name T253
Test name
Test status
Simulation time 462840788 ps
CPU time 4.99 seconds
Started Jul 02 09:40:53 AM PDT 24
Finished Jul 02 09:41:00 AM PDT 24
Peak memory 217708 kb
Host smart-a3b0cd83-096c-4d7a-b8bb-b8325ade95d7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321409383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.1321409383
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.871634957
Short name T286
Test name
Test status
Simulation time 447434637 ps
CPU time 11.64 seconds
Started Jul 02 09:40:52 AM PDT 24
Finished Jul 02 09:41:06 AM PDT 24
Peak memory 217116 kb
Host smart-94469612-7709-467d-b4db-37b377c6b0f6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871634957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke.
871634957
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.1156415442
Short name T414
Test name
Test status
Simulation time 18225959571 ps
CPU time 67.41 seconds
Started Jul 02 09:40:52 AM PDT 24
Finished Jul 02 09:42:02 AM PDT 24
Peak memory 276128 kb
Host smart-7005c6f9-ff3a-450f-8c8b-30de9dff5a32
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156415442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.1156415442
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.567289982
Short name T823
Test name
Test status
Simulation time 559096135 ps
CPU time 13.86 seconds
Started Jul 02 09:40:50 AM PDT 24
Finished Jul 02 09:41:07 AM PDT 24
Peak memory 250320 kb
Host smart-5736ec1f-52c0-4d27-8318-7a40066efd52
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567289982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_
jtag_state_post_trans.567289982
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.1605330881
Short name T264
Test name
Test status
Simulation time 172107872 ps
CPU time 2.32 seconds
Started Jul 02 09:40:49 AM PDT 24
Finished Jul 02 09:40:53 AM PDT 24
Peak memory 217808 kb
Host smart-a78d5d2a-6f82-4f9a-bdb9-62f496985b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605330881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.1605330881
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.770817206
Short name T425
Test name
Test status
Simulation time 2919894485 ps
CPU time 17.12 seconds
Started Jul 02 09:40:47 AM PDT 24
Finished Jul 02 09:41:07 AM PDT 24
Peak memory 219572 kb
Host smart-86980e65-9744-4ea1-b8e1-e486e053f470
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770817206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.770817206
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.2982409155
Short name T394
Test name
Test status
Simulation time 374429478 ps
CPU time 9.74 seconds
Started Jul 02 09:40:50 AM PDT 24
Finished Jul 02 09:41:03 AM PDT 24
Peak memory 225512 kb
Host smart-f7ef6b07-79fd-4d18-9439-6854bb1dfa69
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982409155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.2982409155
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.2064029287
Short name T533
Test name
Test status
Simulation time 249349236 ps
CPU time 7.38 seconds
Started Jul 02 09:40:50 AM PDT 24
Finished Jul 02 09:41:00 AM PDT 24
Peak memory 217736 kb
Host smart-0327b6fc-99db-4a53-9426-9a3ff236687e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064029287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
2064029287
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.393693871
Short name T842
Test name
Test status
Simulation time 766573597 ps
CPU time 11.19 seconds
Started Jul 02 09:40:50 AM PDT 24
Finished Jul 02 09:41:04 AM PDT 24
Peak memory 225548 kb
Host smart-e13abf8a-fdfa-4fbd-951a-4c09be93a389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393693871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.393693871
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.2675936522
Short name T723
Test name
Test status
Simulation time 1892044535 ps
CPU time 6.21 seconds
Started Jul 02 09:40:48 AM PDT 24
Finished Jul 02 09:40:56 AM PDT 24
Peak memory 217212 kb
Host smart-e0b59b84-d759-4408-aa38-63fca49e15f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675936522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.2675936522
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.1223464721
Short name T868
Test name
Test status
Simulation time 598690760 ps
CPU time 19.88 seconds
Started Jul 02 09:40:52 AM PDT 24
Finished Jul 02 09:41:14 AM PDT 24
Peak memory 250644 kb
Host smart-80d861ee-219a-42bd-985f-28cfe01e7fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223464721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.1223464721
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.3398127195
Short name T487
Test name
Test status
Simulation time 101420934 ps
CPU time 3.77 seconds
Started Jul 02 09:40:49 AM PDT 24
Finished Jul 02 09:40:56 AM PDT 24
Peak memory 222152 kb
Host smart-081149e9-8984-4fd6-98b6-043a565738c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398127195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.3398127195
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.1038414485
Short name T171
Test name
Test status
Simulation time 15955883506 ps
CPU time 84.08 seconds
Started Jul 02 09:40:52 AM PDT 24
Finished Jul 02 09:42:19 AM PDT 24
Peak memory 274316 kb
Host smart-989a4be8-3750-49bc-99c0-3192c4afe0c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038414485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.1038414485
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.149849709
Short name T283
Test name
Test status
Simulation time 12548801 ps
CPU time 0.96 seconds
Started Jul 02 09:40:52 AM PDT 24
Finished Jul 02 09:40:55 AM PDT 24
Peak memory 208836 kb
Host smart-f9e876d7-af15-453d-bb99-2002c6f66881
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149849709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ct
rl_volatile_unlock_smoke.149849709
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.2686102812
Short name T679
Test name
Test status
Simulation time 54554555 ps
CPU time 0.88 seconds
Started Jul 02 09:40:55 AM PDT 24
Finished Jul 02 09:40:58 AM PDT 24
Peak memory 208532 kb
Host smart-96dd6972-5641-4db3-b55b-cd36a17996e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686102812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.2686102812
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.1252653724
Short name T475
Test name
Test status
Simulation time 365957770 ps
CPU time 7.18 seconds
Started Jul 02 09:40:54 AM PDT 24
Finished Jul 02 09:41:03 AM PDT 24
Peak memory 225360 kb
Host smart-68abbfae-7a58-473d-9fa5-eacb9cb01d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252653724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.1252653724
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.4046116369
Short name T481
Test name
Test status
Simulation time 1543172191 ps
CPU time 5.07 seconds
Started Jul 02 09:40:55 AM PDT 24
Finished Jul 02 09:41:02 AM PDT 24
Peak memory 217196 kb
Host smart-16bbfb62-e824-4a0b-8d85-837a48a3f22c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046116369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.4046116369
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.2219075816
Short name T405
Test name
Test status
Simulation time 8244133640 ps
CPU time 25.47 seconds
Started Jul 02 09:40:54 AM PDT 24
Finished Jul 02 09:41:22 AM PDT 24
Peak memory 218416 kb
Host smart-698dfdc6-f9e6-440d-8823-2200a016d360
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219075816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.2219075816
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.65582964
Short name T626
Test name
Test status
Simulation time 1651470122 ps
CPU time 12.57 seconds
Started Jul 02 09:40:52 AM PDT 24
Finished Jul 02 09:41:07 AM PDT 24
Peak memory 217680 kb
Host smart-9f4e9425-53dc-43bf-841a-977889085e55
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65582964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p
rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_
prog_failure.65582964
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.636711829
Short name T527
Test name
Test status
Simulation time 1736066112 ps
CPU time 10.35 seconds
Started Jul 02 09:40:53 AM PDT 24
Finished Jul 02 09:41:05 AM PDT 24
Peak memory 217088 kb
Host smart-788af0bf-cc92-45ff-8a7d-9f1f5634da09
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636711829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke.
636711829
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.3632500740
Short name T781
Test name
Test status
Simulation time 3346948654 ps
CPU time 32.07 seconds
Started Jul 02 09:40:54 AM PDT 24
Finished Jul 02 09:41:28 AM PDT 24
Peak memory 250480 kb
Host smart-1412f33c-1935-4ca7-9f23-0821824b34d9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632500740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.3632500740
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.3126696319
Short name T587
Test name
Test status
Simulation time 8371810020 ps
CPU time 13.76 seconds
Started Jul 02 09:40:55 AM PDT 24
Finished Jul 02 09:41:10 AM PDT 24
Peak memory 225932 kb
Host smart-c9f5da1c-4678-4ec6-ba83-b15083d47c23
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126696319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.3126696319
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.489095622
Short name T293
Test name
Test status
Simulation time 49330333 ps
CPU time 2.97 seconds
Started Jul 02 09:40:53 AM PDT 24
Finished Jul 02 09:40:58 AM PDT 24
Peak memory 217752 kb
Host smart-10f2b562-baf3-4d47-beb4-c8a02fffa9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489095622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.489095622
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.350718924
Short name T466
Test name
Test status
Simulation time 611131462 ps
CPU time 9.13 seconds
Started Jul 02 09:40:54 AM PDT 24
Finished Jul 02 09:41:05 AM PDT 24
Peak memory 225500 kb
Host smart-ed21f129-aa61-499c-9810-312343e0a1b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350718924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_di
gest.350718924
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.935738322
Short name T172
Test name
Test status
Simulation time 222011483 ps
CPU time 7.54 seconds
Started Jul 02 09:40:55 AM PDT 24
Finished Jul 02 09:41:04 AM PDT 24
Peak memory 217716 kb
Host smart-a1dde34d-cfcf-45a6-bea1-416ef6a76ddd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935738322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.935738322
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.3982458557
Short name T601
Test name
Test status
Simulation time 1147225865 ps
CPU time 7.56 seconds
Started Jul 02 09:40:53 AM PDT 24
Finished Jul 02 09:41:03 AM PDT 24
Peak memory 224788 kb
Host smart-b1fd2690-8ce2-44b5-afe8-7dcd94b9f811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982458557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.3982458557
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.3338162000
Short name T305
Test name
Test status
Simulation time 160006584 ps
CPU time 1.79 seconds
Started Jul 02 09:40:55 AM PDT 24
Finished Jul 02 09:40:59 AM PDT 24
Peak memory 217180 kb
Host smart-213b59d5-fbc1-412e-b349-1b1bd32da908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338162000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.3338162000
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.4126601575
Short name T413
Test name
Test status
Simulation time 266205605 ps
CPU time 25.31 seconds
Started Jul 02 09:40:59 AM PDT 24
Finished Jul 02 09:41:25 AM PDT 24
Peak memory 250636 kb
Host smart-dcac1de6-47cf-4650-b5de-3eb873f3d129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126601575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.4126601575
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.4057338370
Short name T595
Test name
Test status
Simulation time 77639618 ps
CPU time 7.41 seconds
Started Jul 02 09:40:52 AM PDT 24
Finished Jul 02 09:41:02 AM PDT 24
Peak memory 250524 kb
Host smart-9067749c-1623-4535-9a0e-7fe4b85e7968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057338370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.4057338370
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.528609975
Short name T209
Test name
Test status
Simulation time 5564753949 ps
CPU time 97.22 seconds
Started Jul 02 09:40:54 AM PDT 24
Finished Jul 02 09:42:33 AM PDT 24
Peak memory 251008 kb
Host smart-46074839-4cda-4062-8b10-dea75dfc0d3a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528609975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.528609975
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.2971901950
Short name T189
Test name
Test status
Simulation time 68717544815 ps
CPU time 474.18 seconds
Started Jul 02 09:40:54 AM PDT 24
Finished Jul 02 09:48:51 AM PDT 24
Peak memory 283500 kb
Host smart-f487dda7-afe9-4a39-a292-e4671c2d41eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2971901950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.2971901950
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.2352537677
Short name T353
Test name
Test status
Simulation time 13738976 ps
CPU time 1 seconds
Started Jul 02 09:40:54 AM PDT 24
Finished Jul 02 09:40:57 AM PDT 24
Peak memory 208448 kb
Host smart-80158e0a-43cd-4b25-a37d-e0489219526a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352537677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.2352537677
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.2226026892
Short name T246
Test name
Test status
Simulation time 100661527 ps
CPU time 1.32 seconds
Started Jul 02 09:40:58 AM PDT 24
Finished Jul 02 09:41:00 AM PDT 24
Peak memory 208668 kb
Host smart-8f9811c0-e341-4a3c-b7c9-6c01c8f3c467
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226026892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.2226026892
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.240996677
Short name T684
Test name
Test status
Simulation time 2354210516 ps
CPU time 14.12 seconds
Started Jul 02 09:41:05 AM PDT 24
Finished Jul 02 09:41:20 AM PDT 24
Peak memory 218492 kb
Host smart-30f04646-eb69-4836-bd09-342a4c0d8c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240996677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.240996677
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.2770669606
Short name T30
Test name
Test status
Simulation time 704362496 ps
CPU time 7.18 seconds
Started Jul 02 09:41:00 AM PDT 24
Finished Jul 02 09:41:08 AM PDT 24
Peak memory 217144 kb
Host smart-17f7bd79-0bab-4cf9-b503-87834a53a103
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770669606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.2770669606
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.309174264
Short name T762
Test name
Test status
Simulation time 11461670946 ps
CPU time 76.25 seconds
Started Jul 02 09:41:00 AM PDT 24
Finished Jul 02 09:42:17 AM PDT 24
Peak memory 218204 kb
Host smart-f854fed0-413f-43ad-9eca-974ad9b466f4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309174264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_er
rors.309174264
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.1261025633
Short name T423
Test name
Test status
Simulation time 106483549 ps
CPU time 2.54 seconds
Started Jul 02 09:41:00 AM PDT 24
Finished Jul 02 09:41:03 AM PDT 24
Peak memory 221124 kb
Host smart-6f87250a-54c0-4504-895f-75159fa3d96e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261025633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.1261025633
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.2100976096
Short name T313
Test name
Test status
Simulation time 954797412 ps
CPU time 7.77 seconds
Started Jul 02 09:41:01 AM PDT 24
Finished Jul 02 09:41:09 AM PDT 24
Peak memory 217116 kb
Host smart-f2cf7f68-2e08-4749-9d77-d46f0925e045
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100976096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.2100976096
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.1456929086
Short name T729
Test name
Test status
Simulation time 4257815250 ps
CPU time 46.41 seconds
Started Jul 02 09:40:59 AM PDT 24
Finished Jul 02 09:41:47 AM PDT 24
Peak memory 266932 kb
Host smart-5e6948f3-78e7-4a8e-aae2-6be8be4ee8a5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456929086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.1456929086
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.2400501287
Short name T486
Test name
Test status
Simulation time 483399384 ps
CPU time 18.92 seconds
Started Jul 02 09:41:06 AM PDT 24
Finished Jul 02 09:41:27 AM PDT 24
Peak memory 250428 kb
Host smart-db3167d6-9f58-4f9d-95c2-4a7dfb361497
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400501287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.2400501287
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.4040029371
Short name T499
Test name
Test status
Simulation time 73478716 ps
CPU time 3.01 seconds
Started Jul 02 09:40:57 AM PDT 24
Finished Jul 02 09:41:01 AM PDT 24
Peak memory 222080 kb
Host smart-da37e655-cecf-4d9d-8b2f-a91aee2e842f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040029371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.4040029371
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.562925580
Short name T256
Test name
Test status
Simulation time 590947335 ps
CPU time 14.82 seconds
Started Jul 02 09:40:59 AM PDT 24
Finished Jul 02 09:41:15 AM PDT 24
Peak memory 225580 kb
Host smart-d99da1b4-e3ae-4caf-8603-63c3f242f5af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562925580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.562925580
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.2395829032
Short name T779
Test name
Test status
Simulation time 569393730 ps
CPU time 19.55 seconds
Started Jul 02 09:40:57 AM PDT 24
Finished Jul 02 09:41:18 AM PDT 24
Peak memory 225476 kb
Host smart-a0ae3061-7004-42cc-93f1-9725b35e4b55
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395829032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.2395829032
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.3474338031
Short name T292
Test name
Test status
Simulation time 307025382 ps
CPU time 7.95 seconds
Started Jul 02 09:40:58 AM PDT 24
Finished Jul 02 09:41:06 AM PDT 24
Peak memory 225516 kb
Host smart-c0aac0dd-7272-496c-a495-8b9b31f16c95
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474338031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
3474338031
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.2139303617
Short name T850
Test name
Test status
Simulation time 272691932 ps
CPU time 6.48 seconds
Started Jul 02 09:41:00 AM PDT 24
Finished Jul 02 09:41:07 AM PDT 24
Peak memory 223988 kb
Host smart-3f064670-de3a-4cd8-83ae-113e9a849c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139303617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.2139303617
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.4114505697
Short name T577
Test name
Test status
Simulation time 138044056 ps
CPU time 4.22 seconds
Started Jul 02 09:40:56 AM PDT 24
Finished Jul 02 09:41:01 AM PDT 24
Peak memory 217128 kb
Host smart-841070dd-b46a-43da-9187-d68fdce878d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114505697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.4114505697
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.2642190428
Short name T294
Test name
Test status
Simulation time 894168341 ps
CPU time 18.4 seconds
Started Jul 02 09:41:06 AM PDT 24
Finished Jul 02 09:41:26 AM PDT 24
Peak memory 250536 kb
Host smart-1817d0a8-a4a0-45a3-9b29-00e81eb8b6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642190428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.2642190428
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.2898526684
Short name T235
Test name
Test status
Simulation time 93094606 ps
CPU time 8.97 seconds
Started Jul 02 09:41:00 AM PDT 24
Finished Jul 02 09:41:10 AM PDT 24
Peak memory 250536 kb
Host smart-114d4465-a5cb-42f0-b584-fe42fe010f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898526684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.2898526684
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.1940980642
Short name T417
Test name
Test status
Simulation time 22552928749 ps
CPU time 113.81 seconds
Started Jul 02 09:40:58 AM PDT 24
Finished Jul 02 09:42:52 AM PDT 24
Peak memory 273616 kb
Host smart-4173e328-9749-49aa-a24d-3aa97f1a3a41
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940980642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.1940980642
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.118848811
Short name T794
Test name
Test status
Simulation time 15488697 ps
CPU time 0.94 seconds
Started Jul 02 09:40:55 AM PDT 24
Finished Jul 02 09:40:58 AM PDT 24
Peak memory 212424 kb
Host smart-9661d805-e45c-4fd5-a601-aba88a2c7828
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118848811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ct
rl_volatile_unlock_smoke.118848811
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.2654468566
Short name T621
Test name
Test status
Simulation time 635047986 ps
CPU time 10.74 seconds
Started Jul 02 09:41:06 AM PDT 24
Finished Jul 02 09:41:18 AM PDT 24
Peak memory 217800 kb
Host smart-31c5be0a-7f9b-427d-b0db-644a6bfab45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654468566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.2654468566
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.2798163315
Short name T29
Test name
Test status
Simulation time 408122226 ps
CPU time 10.92 seconds
Started Jul 02 09:41:05 AM PDT 24
Finished Jul 02 09:41:16 AM PDT 24
Peak memory 217176 kb
Host smart-dc77b640-806d-46ce-9f73-6c087f2c7760
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798163315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.2798163315
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.2921585155
Short name T350
Test name
Test status
Simulation time 1352953817 ps
CPU time 22.74 seconds
Started Jul 02 09:41:02 AM PDT 24
Finished Jul 02 09:41:26 AM PDT 24
Peak memory 217684 kb
Host smart-8c772c14-70df-45d1-bdd8-6666ee603d47
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921585155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.2921585155
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.1461391707
Short name T683
Test name
Test status
Simulation time 415551453 ps
CPU time 12.94 seconds
Started Jul 02 09:41:01 AM PDT 24
Finished Jul 02 09:41:15 AM PDT 24
Peak memory 217800 kb
Host smart-49c8e52a-b743-447d-884c-6fd8bac5bbd2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461391707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.1461391707
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.1655813530
Short name T699
Test name
Test status
Simulation time 153032202 ps
CPU time 2.69 seconds
Started Jul 02 09:41:02 AM PDT 24
Finished Jul 02 09:41:05 AM PDT 24
Peak memory 217144 kb
Host smart-a54d66dc-3a62-4a8b-ac83-7c6c1fde5a8e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655813530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.1655813530
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.1613703778
Short name T852
Test name
Test status
Simulation time 3621815173 ps
CPU time 69.63 seconds
Started Jul 02 09:41:03 AM PDT 24
Finished Jul 02 09:42:13 AM PDT 24
Peak memory 270308 kb
Host smart-e7d91a06-b988-4219-8479-93814f5e82f2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613703778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.1613703778
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.3292810858
Short name T776
Test name
Test status
Simulation time 2012625512 ps
CPU time 11.98 seconds
Started Jul 02 09:41:02 AM PDT 24
Finished Jul 02 09:41:15 AM PDT 24
Peak memory 217644 kb
Host smart-f514b555-7c5f-4a5c-817c-1c2dc3c34acf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292810858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.3292810858
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.3159268822
Short name T630
Test name
Test status
Simulation time 205829681 ps
CPU time 3.79 seconds
Started Jul 02 09:40:59 AM PDT 24
Finished Jul 02 09:41:03 AM PDT 24
Peak memory 217764 kb
Host smart-ca6b6745-291a-43fd-83f4-8b6ab446b535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159268822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.3159268822
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.1639997343
Short name T288
Test name
Test status
Simulation time 629843427 ps
CPU time 12.48 seconds
Started Jul 02 09:41:10 AM PDT 24
Finished Jul 02 09:41:25 AM PDT 24
Peak memory 225496 kb
Host smart-ba8da1fc-3718-4ccd-bbc8-235fb4561dc1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639997343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.1639997343
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.1906416483
Short name T586
Test name
Test status
Simulation time 358193500 ps
CPU time 12.8 seconds
Started Jul 02 09:41:06 AM PDT 24
Finished Jul 02 09:41:20 AM PDT 24
Peak memory 225532 kb
Host smart-b06107f8-c9db-46a7-bffb-bf9b2677c0e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906416483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
1906416483
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.3285577684
Short name T478
Test name
Test status
Simulation time 1421818586 ps
CPU time 12.32 seconds
Started Jul 02 09:41:06 AM PDT 24
Finished Jul 02 09:41:19 AM PDT 24
Peak memory 217856 kb
Host smart-078b59d0-50f2-4ea2-9f6f-992a38fe4959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285577684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.3285577684
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.2063101420
Short name T79
Test name
Test status
Simulation time 50283934 ps
CPU time 3.15 seconds
Started Jul 02 09:40:58 AM PDT 24
Finished Jul 02 09:41:02 AM PDT 24
Peak memory 214388 kb
Host smart-45d3c896-1d8a-482d-b91f-4f208a0c1ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063101420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.2063101420
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.2381320336
Short name T798
Test name
Test status
Simulation time 1006726872 ps
CPU time 23.25 seconds
Started Jul 02 09:40:58 AM PDT 24
Finished Jul 02 09:41:23 AM PDT 24
Peak memory 244528 kb
Host smart-e2750b39-530d-4046-9661-2563348c94d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381320336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.2381320336
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.1312222292
Short name T849
Test name
Test status
Simulation time 682678495 ps
CPU time 7.3 seconds
Started Jul 02 09:40:58 AM PDT 24
Finished Jul 02 09:41:06 AM PDT 24
Peak memory 250512 kb
Host smart-db3959a8-d93c-40fa-bf81-7385b7af9a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312222292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.1312222292
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.3900255055
Short name T169
Test name
Test status
Simulation time 11839610072 ps
CPU time 46.63 seconds
Started Jul 02 09:41:03 AM PDT 24
Finished Jul 02 09:41:51 AM PDT 24
Peak memory 275384 kb
Host smart-d8988b08-022d-4ef3-8d30-f1c91ab4a15b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900255055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.3900255055
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.1374842514
Short name T633
Test name
Test status
Simulation time 27200569 ps
CPU time 1.25 seconds
Started Jul 02 09:41:07 AM PDT 24
Finished Jul 02 09:41:09 AM PDT 24
Peak memory 211420 kb
Host smart-56cddbcc-3e51-41ae-af3e-15b288717038
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374842514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.1374842514
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.2098836601
Short name T726
Test name
Test status
Simulation time 19734640 ps
CPU time 0.93 seconds
Started Jul 02 09:41:03 AM PDT 24
Finished Jul 02 09:41:05 AM PDT 24
Peak memory 208528 kb
Host smart-e7b19a0e-b52b-479e-9860-731522eef9f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098836601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.2098836601
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.3624154365
Short name T778
Test name
Test status
Simulation time 234710592 ps
CPU time 9.77 seconds
Started Jul 02 09:41:03 AM PDT 24
Finished Jul 02 09:41:14 AM PDT 24
Peak memory 217832 kb
Host smart-a2dafd4a-f11d-4afc-97cc-9f9ae9be432f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624154365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.3624154365
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.1208151275
Short name T639
Test name
Test status
Simulation time 43433108 ps
CPU time 1.25 seconds
Started Jul 02 09:41:01 AM PDT 24
Finished Jul 02 09:41:03 AM PDT 24
Peak memory 217132 kb
Host smart-818bc43a-0c71-45f0-9900-fe6c360eba19
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208151275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.1208151275
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.300480040
Short name T669
Test name
Test status
Simulation time 4914490975 ps
CPU time 37.69 seconds
Started Jul 02 09:41:07 AM PDT 24
Finished Jul 02 09:41:46 AM PDT 24
Peak memory 218432 kb
Host smart-1ad828e1-a712-4a3a-8faa-9f885e5272b0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300480040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_er
rors.300480040
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1775953956
Short name T484
Test name
Test status
Simulation time 1409618494 ps
CPU time 3.48 seconds
Started Jul 02 09:41:03 AM PDT 24
Finished Jul 02 09:41:07 AM PDT 24
Peak memory 221260 kb
Host smart-ef79cfbd-a0b7-414b-adcf-646ce1c7e49f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775953956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.1775953956
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.129585771
Short name T86
Test name
Test status
Simulation time 452287129 ps
CPU time 6.66 seconds
Started Jul 02 09:41:09 AM PDT 24
Finished Jul 02 09:41:16 AM PDT 24
Peak memory 217156 kb
Host smart-c0d5fb21-4f80-4f24-9ae4-9ea168f899ea
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129585771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke.
129585771
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.3797559299
Short name T788
Test name
Test status
Simulation time 1802909919 ps
CPU time 29.29 seconds
Started Jul 02 09:41:03 AM PDT 24
Finished Jul 02 09:41:33 AM PDT 24
Peak memory 250472 kb
Host smart-dc2b5f0a-539d-4603-8a36-5b5592817048
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797559299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.3797559299
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.2065441612
Short name T656
Test name
Test status
Simulation time 722409853 ps
CPU time 25.91 seconds
Started Jul 02 09:41:02 AM PDT 24
Finished Jul 02 09:41:28 AM PDT 24
Peak memory 250444 kb
Host smart-657072bd-ced5-4a42-991f-88a88ceb6027
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065441612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.2065441612
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.2724866910
Short name T743
Test name
Test status
Simulation time 451970184 ps
CPU time 2.71 seconds
Started Jul 02 09:41:02 AM PDT 24
Finished Jul 02 09:41:06 AM PDT 24
Peak memory 217768 kb
Host smart-3a249661-7fc4-4b7a-b6e7-211a2ec5a1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724866910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.2724866910
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.567427046
Short name T376
Test name
Test status
Simulation time 1100065516 ps
CPU time 11.41 seconds
Started Jul 02 09:41:07 AM PDT 24
Finished Jul 02 09:41:20 AM PDT 24
Peak memory 218420 kb
Host smart-f0d6cbb2-47c1-4ef2-bd16-87cc9dade56e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567427046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.567427046
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.29066600
Short name T730
Test name
Test status
Simulation time 188042441 ps
CPU time 7.36 seconds
Started Jul 02 09:41:06 AM PDT 24
Finished Jul 02 09:41:15 AM PDT 24
Peak memory 225564 kb
Host smart-eb057033-99df-4dbb-ba0a-c8d4d8687c43
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29066600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_dig
est.29066600
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.174966132
Short name T287
Test name
Test status
Simulation time 434045331 ps
CPU time 7.82 seconds
Started Jul 02 09:41:02 AM PDT 24
Finished Jul 02 09:41:11 AM PDT 24
Peak memory 224004 kb
Host smart-50e0b2de-2bbd-496c-9095-59cc9dd208a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174966132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.174966132
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.713248616
Short name T69
Test name
Test status
Simulation time 367707333 ps
CPU time 10.93 seconds
Started Jul 02 09:41:12 AM PDT 24
Finished Jul 02 09:41:26 AM PDT 24
Peak memory 217824 kb
Host smart-d24730c2-40fb-46f3-8292-e4348d6bfa08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713248616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.713248616
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.4010770186
Short name T77
Test name
Test status
Simulation time 86420781 ps
CPU time 2.93 seconds
Started Jul 02 09:41:07 AM PDT 24
Finished Jul 02 09:41:11 AM PDT 24
Peak memory 217232 kb
Host smart-a6960616-5b0f-4e2c-8c8f-331cd6491f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010770186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.4010770186
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.3558306804
Short name T202
Test name
Test status
Simulation time 629572987 ps
CPU time 20.31 seconds
Started Jul 02 09:41:11 AM PDT 24
Finished Jul 02 09:41:34 AM PDT 24
Peak memory 250512 kb
Host smart-835e5bab-28cf-4a22-801e-9c1a5c9ae3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558306804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.3558306804
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.662814753
Short name T500
Test name
Test status
Simulation time 296020493 ps
CPU time 3.31 seconds
Started Jul 02 09:41:05 AM PDT 24
Finished Jul 02 09:41:09 AM PDT 24
Peak memory 223976 kb
Host smart-52a69135-9f2c-464a-8ea9-608eec2092d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662814753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.662814753
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.2222775516
Short name T483
Test name
Test status
Simulation time 26973948714 ps
CPU time 245.93 seconds
Started Jul 02 09:41:11 AM PDT 24
Finished Jul 02 09:45:18 AM PDT 24
Peak memory 299780 kb
Host smart-64da399e-f13d-433d-9c5d-0682903dc03c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222775516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.2222775516
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.1901216106
Short name T416
Test name
Test status
Simulation time 77332035 ps
CPU time 0.79 seconds
Started Jul 02 09:41:01 AM PDT 24
Finished Jul 02 09:41:03 AM PDT 24
Peak memory 208276 kb
Host smart-a0723b91-35f7-4a4c-8d01-3630302e085a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901216106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.1901216106
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.2130903292
Short name T174
Test name
Test status
Simulation time 162898887 ps
CPU time 0.96 seconds
Started Jul 02 09:41:06 AM PDT 24
Finished Jul 02 09:41:08 AM PDT 24
Peak memory 208500 kb
Host smart-44b7648f-430c-41c8-b6bf-99f3a64bae23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130903292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.2130903292
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.2986993871
Short name T609
Test name
Test status
Simulation time 1188186949 ps
CPU time 13.22 seconds
Started Jul 02 09:41:05 AM PDT 24
Finished Jul 02 09:41:19 AM PDT 24
Peak memory 217800 kb
Host smart-10e0f036-4488-4589-976c-b55a4a729921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986993871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.2986993871
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.2023091657
Short name T368
Test name
Test status
Simulation time 349994349 ps
CPU time 4.41 seconds
Started Jul 02 09:41:08 AM PDT 24
Finished Jul 02 09:41:14 AM PDT 24
Peak memory 216824 kb
Host smart-f140cd0d-da03-44c4-a87a-8b3306baa0da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023091657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.2023091657
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.3971177569
Short name T55
Test name
Test status
Simulation time 6342314846 ps
CPU time 56.29 seconds
Started Jul 02 09:41:08 AM PDT 24
Finished Jul 02 09:42:05 AM PDT 24
Peak memory 218508 kb
Host smart-7b003a78-5450-40fd-96d7-abafec87e5f5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971177569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.3971177569
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.679999102
Short name T297
Test name
Test status
Simulation time 1049851655 ps
CPU time 15.12 seconds
Started Jul 02 09:41:10 AM PDT 24
Finished Jul 02 09:41:26 AM PDT 24
Peak memory 217708 kb
Host smart-5cac0b1e-40c8-40e1-9fec-9d32984e1488
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679999102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag
_prog_failure.679999102
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.3493544061
Short name T75
Test name
Test status
Simulation time 647012114 ps
CPU time 3.4 seconds
Started Jul 02 09:41:07 AM PDT 24
Finished Jul 02 09:41:12 AM PDT 24
Peak memory 217152 kb
Host smart-50aef0ef-7685-454b-ad62-37031a8ef626
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493544061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.3493544061
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.456727609
Short name T575
Test name
Test status
Simulation time 933638534 ps
CPU time 43.77 seconds
Started Jul 02 09:41:09 AM PDT 24
Finished Jul 02 09:41:54 AM PDT 24
Peak memory 250468 kb
Host smart-11b67320-980c-4a44-b2d1-77a101d15d09
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456727609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_state_failure.456727609
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.679425067
Short name T400
Test name
Test status
Simulation time 544748898 ps
CPU time 10.19 seconds
Started Jul 02 09:41:10 AM PDT 24
Finished Jul 02 09:41:22 AM PDT 24
Peak memory 250288 kb
Host smart-1e3e0a91-53dc-49a9-b675-8312fbad813f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679425067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_
jtag_state_post_trans.679425067
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.1600158687
Short name T443
Test name
Test status
Simulation time 120299124 ps
CPU time 3.37 seconds
Started Jul 02 09:41:09 AM PDT 24
Finished Jul 02 09:41:14 AM PDT 24
Peak memory 217688 kb
Host smart-2844fbe9-5f95-4826-8961-92637db4970e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600158687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.1600158687
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.3684569029
Short name T351
Test name
Test status
Simulation time 505310759 ps
CPU time 10.94 seconds
Started Jul 02 09:41:06 AM PDT 24
Finished Jul 02 09:41:17 AM PDT 24
Peak memory 218424 kb
Host smart-507203aa-ce92-4c53-8678-6194fa0c42a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684569029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.3684569029
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.557191923
Short name T16
Test name
Test status
Simulation time 6963644401 ps
CPU time 31.98 seconds
Started Jul 02 09:41:14 AM PDT 24
Finished Jul 02 09:41:49 AM PDT 24
Peak memory 225564 kb
Host smart-dcbeccf3-d2c2-4c42-b681-d85bc2fd9230
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557191923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_di
gest.557191923
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.3281578975
Short name T304
Test name
Test status
Simulation time 1113377125 ps
CPU time 11.51 seconds
Started Jul 02 09:41:06 AM PDT 24
Finished Jul 02 09:41:18 AM PDT 24
Peak memory 217744 kb
Host smart-cb519832-0899-4b88-b636-fbd8282c6e72
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281578975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
3281578975
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.736757518
Short name T827
Test name
Test status
Simulation time 1424447670 ps
CPU time 13.64 seconds
Started Jul 02 09:41:07 AM PDT 24
Finished Jul 02 09:41:21 AM PDT 24
Peak memory 218004 kb
Host smart-43bf570c-279b-49f2-bc6b-2ccbb36ff108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736757518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.736757518
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.1619632024
Short name T835
Test name
Test status
Simulation time 48502513 ps
CPU time 1.81 seconds
Started Jul 02 09:41:02 AM PDT 24
Finished Jul 02 09:41:05 AM PDT 24
Peak memory 217216 kb
Host smart-b2d85e96-cc62-42b3-866f-660458bfa680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619632024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.1619632024
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.1817573201
Short name T274
Test name
Test status
Simulation time 313180341 ps
CPU time 37.36 seconds
Started Jul 02 09:41:10 AM PDT 24
Finished Jul 02 09:41:49 AM PDT 24
Peak memory 250512 kb
Host smart-54fa8e70-1d21-456a-905d-2e85c42996a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817573201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.1817573201
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.128221262
Short name T306
Test name
Test status
Simulation time 52650407 ps
CPU time 6.41 seconds
Started Jul 02 09:41:07 AM PDT 24
Finished Jul 02 09:41:15 AM PDT 24
Peak memory 242360 kb
Host smart-05bcbde9-50d4-4c36-b2a3-8bd559712f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128221262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.128221262
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.2777726302
Short name T91
Test name
Test status
Simulation time 11403297374 ps
CPU time 64.53 seconds
Started Jul 02 09:41:09 AM PDT 24
Finished Jul 02 09:42:15 AM PDT 24
Peak memory 266964 kb
Host smart-b90da3a3-7ada-4738-a038-4f2db5f1d6df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777726302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.2777726302
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.93403447
Short name T161
Test name
Test status
Simulation time 21496440244 ps
CPU time 431.61 seconds
Started Jul 02 09:41:08 AM PDT 24
Finished Jul 02 09:48:21 AM PDT 24
Peak memory 262572 kb
Host smart-6e59436a-7a56-400e-8671-9f823d25c7b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=93403447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.93403447
Directory /workspace/17.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.1871046753
Short name T110
Test name
Test status
Simulation time 21955171 ps
CPU time 0.93 seconds
Started Jul 02 09:41:07 AM PDT 24
Finished Jul 02 09:41:09 AM PDT 24
Peak memory 208580 kb
Host smart-1f78367c-876e-4873-bca0-5fa1d1228186
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871046753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.1871046753
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.3445748906
Short name T201
Test name
Test status
Simulation time 14188764 ps
CPU time 0.87 seconds
Started Jul 02 09:41:12 AM PDT 24
Finished Jul 02 09:41:14 AM PDT 24
Peak memory 208536 kb
Host smart-b9dc4991-e7ef-458a-a922-7406e55d5696
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445748906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.3445748906
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.4055449092
Short name T604
Test name
Test status
Simulation time 2339201271 ps
CPU time 13.83 seconds
Started Jul 02 09:41:08 AM PDT 24
Finished Jul 02 09:41:23 AM PDT 24
Peak memory 217840 kb
Host smart-1258223e-1524-4e67-8c2e-d6127c85cec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055449092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.4055449092
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.3114519818
Short name T362
Test name
Test status
Simulation time 626952875 ps
CPU time 4.32 seconds
Started Jul 02 09:41:12 AM PDT 24
Finished Jul 02 09:41:18 AM PDT 24
Peak memory 216676 kb
Host smart-5ad2ee51-a960-476c-aa82-087eec392c3f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114519818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.3114519818
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.173236083
Short name T570
Test name
Test status
Simulation time 4228695802 ps
CPU time 40.5 seconds
Started Jul 02 09:41:13 AM PDT 24
Finished Jul 02 09:41:56 AM PDT 24
Peak memory 219752 kb
Host smart-11415557-3970-4327-8fae-4df178448bfe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173236083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_er
rors.173236083
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.3885253573
Short name T602
Test name
Test status
Simulation time 659563306 ps
CPU time 8.4 seconds
Started Jul 02 09:41:14 AM PDT 24
Finished Jul 02 09:41:25 AM PDT 24
Peak memory 222496 kb
Host smart-23c95a4c-1291-441e-a13f-f5219462f740
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885253573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.3885253573
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.462424341
Short name T765
Test name
Test status
Simulation time 192723670 ps
CPU time 3.93 seconds
Started Jul 02 09:41:07 AM PDT 24
Finished Jul 02 09:41:12 AM PDT 24
Peak memory 217132 kb
Host smart-5d90f428-63ad-48b2-8444-98653bf4a887
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462424341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke.
462424341
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.1184472833
Short name T364
Test name
Test status
Simulation time 1827800760 ps
CPU time 84.02 seconds
Started Jul 02 09:41:13 AM PDT 24
Finished Jul 02 09:42:39 AM PDT 24
Peak memory 266852 kb
Host smart-ccdc69eb-6e19-4928-bcba-fdff27db5c72
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184472833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.1184472833
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.1576722432
Short name T390
Test name
Test status
Simulation time 354163500 ps
CPU time 11.19 seconds
Started Jul 02 09:41:12 AM PDT 24
Finished Jul 02 09:41:25 AM PDT 24
Peak memory 250440 kb
Host smart-54b67845-c41d-4869-8ddc-bc9663043f2a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576722432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.1576722432
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.2322670462
Short name T520
Test name
Test status
Simulation time 524056181 ps
CPU time 5.43 seconds
Started Jul 02 09:41:09 AM PDT 24
Finished Jul 02 09:41:15 AM PDT 24
Peak memory 222316 kb
Host smart-b449d225-3d53-4479-8cc7-c9436de79bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322670462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.2322670462
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.233945841
Short name T512
Test name
Test status
Simulation time 428255534 ps
CPU time 17.01 seconds
Started Jul 02 09:41:10 AM PDT 24
Finished Jul 02 09:41:29 AM PDT 24
Peak memory 225516 kb
Host smart-84ded052-e921-4e44-a278-ebc00f2dc78f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233945841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_di
gest.233945841
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.3780981981
Short name T195
Test name
Test status
Simulation time 307996611 ps
CPU time 9.05 seconds
Started Jul 02 09:41:10 AM PDT 24
Finished Jul 02 09:41:21 AM PDT 24
Peak memory 225504 kb
Host smart-e6e19007-14e8-4cc6-991e-02417a20b678
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780981981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
3780981981
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.3513312872
Short name T377
Test name
Test status
Simulation time 302745879 ps
CPU time 11.74 seconds
Started Jul 02 09:41:14 AM PDT 24
Finished Jul 02 09:41:28 AM PDT 24
Peak memory 225648 kb
Host smart-47953176-b001-4920-828d-d3fc4721a519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513312872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.3513312872
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.4153433439
Short name T759
Test name
Test status
Simulation time 34837306 ps
CPU time 1.65 seconds
Started Jul 02 09:41:09 AM PDT 24
Finished Jul 02 09:41:12 AM PDT 24
Peak memory 213440 kb
Host smart-677a0759-6525-4fd6-945b-e495f6f9ae10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153433439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.4153433439
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.831722544
Short name T659
Test name
Test status
Simulation time 429495075 ps
CPU time 25.43 seconds
Started Jul 02 09:41:07 AM PDT 24
Finished Jul 02 09:41:34 AM PDT 24
Peak memory 250484 kb
Host smart-0eed0bae-1af0-49cd-aff7-bd41240716dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831722544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.831722544
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.2473026052
Short name T441
Test name
Test status
Simulation time 184190040 ps
CPU time 2.84 seconds
Started Jul 02 09:41:08 AM PDT 24
Finished Jul 02 09:41:12 AM PDT 24
Peak memory 217768 kb
Host smart-454a086e-684b-477e-8c38-6cb005a283ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473026052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.2473026052
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.1104087450
Short name T352
Test name
Test status
Simulation time 44034365 ps
CPU time 1.01 seconds
Started Jul 02 09:41:06 AM PDT 24
Finished Jul 02 09:41:08 AM PDT 24
Peak memory 211584 kb
Host smart-7aab3055-4bc0-4f4a-9cb2-6472af02faf0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104087450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.1104087450
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.2397331151
Short name T501
Test name
Test status
Simulation time 54543313 ps
CPU time 0.9 seconds
Started Jul 02 09:41:18 AM PDT 24
Finished Jul 02 09:41:21 AM PDT 24
Peak memory 208564 kb
Host smart-f6f8d648-6786-4571-a760-4fc00bfd2b8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397331151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.2397331151
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.2702757218
Short name T547
Test name
Test status
Simulation time 504526648 ps
CPU time 15.96 seconds
Started Jul 02 09:41:12 AM PDT 24
Finished Jul 02 09:41:30 AM PDT 24
Peak memory 225576 kb
Host smart-d5d4c165-381b-4be1-b3d4-6e2639070bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702757218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.2702757218
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.1406902185
Short name T26
Test name
Test status
Simulation time 1042233951 ps
CPU time 13.81 seconds
Started Jul 02 09:41:15 AM PDT 24
Finished Jul 02 09:41:31 AM PDT 24
Peak memory 217184 kb
Host smart-94114a84-0a2b-4574-8afd-31c08a9b6c7c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406902185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.1406902185
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.693960049
Short name T641
Test name
Test status
Simulation time 9792883702 ps
CPU time 44.11 seconds
Started Jul 02 09:41:11 AM PDT 24
Finished Jul 02 09:41:57 AM PDT 24
Peak memory 218208 kb
Host smart-20482e02-de5b-4d55-a52a-cda065dafc1e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693960049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_er
rors.693960049
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.1149613490
Short name T21
Test name
Test status
Simulation time 66814925 ps
CPU time 2.61 seconds
Started Jul 02 09:41:13 AM PDT 24
Finished Jul 02 09:41:18 AM PDT 24
Peak memory 217728 kb
Host smart-71d18170-fa54-4f7f-8f6f-2a0d70947558
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149613490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.1149613490
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.2351969818
Short name T550
Test name
Test status
Simulation time 2068615723 ps
CPU time 7.14 seconds
Started Jul 02 09:41:12 AM PDT 24
Finished Jul 02 09:41:22 AM PDT 24
Peak memory 217136 kb
Host smart-0bfe2a4c-aaa7-44a6-bd9e-79a58f002554
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351969818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.2351969818
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.971422310
Short name T844
Test name
Test status
Simulation time 55982776178 ps
CPU time 135.14 seconds
Started Jul 02 09:41:15 AM PDT 24
Finished Jul 02 09:43:32 AM PDT 24
Peak memory 283304 kb
Host smart-25affb84-aa1a-4e35-aab6-28dfff109539
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971422310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_state_failure.971422310
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.2907874962
Short name T35
Test name
Test status
Simulation time 1059713621 ps
CPU time 18.77 seconds
Started Jul 02 09:41:09 AM PDT 24
Finished Jul 02 09:41:30 AM PDT 24
Peak memory 250452 kb
Host smart-0e03d7d9-fbbd-4931-80c9-e4a1d74c9298
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907874962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.2907874962
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.4206695157
Short name T757
Test name
Test status
Simulation time 50872248 ps
CPU time 1.97 seconds
Started Jul 02 09:41:14 AM PDT 24
Finished Jul 02 09:41:19 AM PDT 24
Peak memory 221748 kb
Host smart-648e1ee0-0c72-43c5-bfb7-eb0df97add27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206695157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.4206695157
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.900703698
Short name T310
Test name
Test status
Simulation time 367491068 ps
CPU time 10.91 seconds
Started Jul 02 09:41:12 AM PDT 24
Finished Jul 02 09:41:26 AM PDT 24
Peak memory 225500 kb
Host smart-0b1e6629-23da-43b2-94c5-a222a5279fb7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900703698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_di
gest.900703698
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.2554105584
Short name T615
Test name
Test status
Simulation time 553536522 ps
CPU time 6.73 seconds
Started Jul 02 09:41:10 AM PDT 24
Finished Jul 02 09:41:18 AM PDT 24
Peak memory 217740 kb
Host smart-890f1920-c7f4-4b70-ba57-44043ddac3cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554105584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
2554105584
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.1850906296
Short name T809
Test name
Test status
Simulation time 376342503 ps
CPU time 14.86 seconds
Started Jul 02 09:41:11 AM PDT 24
Finished Jul 02 09:41:27 AM PDT 24
Peak memory 225568 kb
Host smart-d4c7dba0-9feb-4c83-9630-224425205009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850906296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.1850906296
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.3795277960
Short name T357
Test name
Test status
Simulation time 63750347 ps
CPU time 2.25 seconds
Started Jul 02 09:41:12 AM PDT 24
Finished Jul 02 09:41:17 AM PDT 24
Peak memory 217196 kb
Host smart-1c6d9be8-c881-4e88-9a59-8388f7b7b2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795277960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.3795277960
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.2919405335
Short name T531
Test name
Test status
Simulation time 370864833 ps
CPU time 42.96 seconds
Started Jul 02 09:41:10 AM PDT 24
Finished Jul 02 09:41:55 AM PDT 24
Peak memory 250532 kb
Host smart-46bd1e36-1e30-4271-8dcd-9256bb413372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919405335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.2919405335
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.1376950836
Short name T670
Test name
Test status
Simulation time 68792126 ps
CPU time 6.98 seconds
Started Jul 02 09:41:10 AM PDT 24
Finished Jul 02 09:41:19 AM PDT 24
Peak memory 250456 kb
Host smart-5823dec7-7031-4af3-b874-ecd3b0cc2d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376950836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.1376950836
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.1854620978
Short name T379
Test name
Test status
Simulation time 11225108196 ps
CPU time 102.56 seconds
Started Jul 02 09:41:12 AM PDT 24
Finished Jul 02 09:42:57 AM PDT 24
Peak memory 297744 kb
Host smart-9ca73a5e-da6c-4a05-994a-8a533d2f219a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854620978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.1854620978
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.3620777526
Short name T207
Test name
Test status
Simulation time 28188114 ps
CPU time 1.23 seconds
Started Jul 02 09:41:12 AM PDT 24
Finished Jul 02 09:41:17 AM PDT 24
Peak memory 217204 kb
Host smart-8bf1fa6e-d5fd-4979-94b9-156c24b4eec6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620777526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.3620777526
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.3414975907
Short name T854
Test name
Test status
Simulation time 48884349 ps
CPU time 0.87 seconds
Started Jul 02 09:40:06 AM PDT 24
Finished Jul 02 09:40:07 AM PDT 24
Peak memory 208520 kb
Host smart-19d80d4c-799b-44be-94ef-2d7e0e7c6752
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414975907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.3414975907
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.2856991276
Short name T581
Test name
Test status
Simulation time 14398353 ps
CPU time 1.02 seconds
Started Jul 02 09:40:09 AM PDT 24
Finished Jul 02 09:40:11 AM PDT 24
Peak memory 208712 kb
Host smart-30049cf3-892e-43b5-86b0-ed9582d904ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856991276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.2856991276
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.2574546645
Short name T767
Test name
Test status
Simulation time 840568143 ps
CPU time 13.52 seconds
Started Jul 02 09:40:07 AM PDT 24
Finished Jul 02 09:40:21 AM PDT 24
Peak memory 217800 kb
Host smart-642aefc0-a48a-4fda-bf30-861818fc29c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574546645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.2574546645
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.2922591240
Short name T523
Test name
Test status
Simulation time 2370832038 ps
CPU time 6.37 seconds
Started Jul 02 09:40:04 AM PDT 24
Finished Jul 02 09:40:12 AM PDT 24
Peak memory 217268 kb
Host smart-cfb3ea85-e2cc-40ed-b52d-ca9431dcdffe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922591240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.2922591240
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.574053723
Short name T5
Test name
Test status
Simulation time 1959921583 ps
CPU time 30.73 seconds
Started Jul 02 09:40:05 AM PDT 24
Finished Jul 02 09:40:37 AM PDT 24
Peak memory 217892 kb
Host smart-df8c2211-4694-4396-8768-0751ced11898
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574053723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_err
ors.574053723
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.3367454852
Short name T318
Test name
Test status
Simulation time 646616329 ps
CPU time 4.95 seconds
Started Jul 02 09:40:07 AM PDT 24
Finished Jul 02 09:40:13 AM PDT 24
Peak memory 217256 kb
Host smart-4b8c7a11-97e4-4844-8249-6229ed4a5950
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367454852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.3
367454852
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.3236574649
Short name T23
Test name
Test status
Simulation time 601966772 ps
CPU time 6.98 seconds
Started Jul 02 09:40:03 AM PDT 24
Finished Jul 02 09:40:11 AM PDT 24
Peak memory 217744 kb
Host smart-06755b46-98b0-4fda-821e-8c20167a5a38
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236574649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.3236574649
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.591080717
Short name T385
Test name
Test status
Simulation time 4718408327 ps
CPU time 13.94 seconds
Started Jul 02 09:40:08 AM PDT 24
Finished Jul 02 09:40:23 AM PDT 24
Peak memory 217184 kb
Host smart-6860ecd9-6991-4f04-adb9-eb3a48a0950d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591080717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_regwen_during_op.591080717
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.3604560668
Short name T558
Test name
Test status
Simulation time 1070418282 ps
CPU time 4.23 seconds
Started Jul 02 09:40:08 AM PDT 24
Finished Jul 02 09:40:13 AM PDT 24
Peak memory 217144 kb
Host smart-3fbc1fa2-6219-41b1-8a85-b088900d4cfd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604560668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
3604560668
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.1121896830
Short name T359
Test name
Test status
Simulation time 1731278213 ps
CPU time 50.53 seconds
Started Jul 02 09:40:06 AM PDT 24
Finished Jul 02 09:40:58 AM PDT 24
Peak memory 266860 kb
Host smart-2f3c58c5-ec80-4eba-9c55-225d86bb8f49
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121896830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.1121896830
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.1554368824
Short name T753
Test name
Test status
Simulation time 3665502559 ps
CPU time 30.39 seconds
Started Jul 02 09:40:02 AM PDT 24
Finished Jul 02 09:40:33 AM PDT 24
Peak memory 250524 kb
Host smart-fa675d70-3584-4c04-bb81-0dee25de95b6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554368824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.1554368824
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.1020113901
Short name T780
Test name
Test status
Simulation time 304280847 ps
CPU time 3.87 seconds
Started Jul 02 09:40:09 AM PDT 24
Finished Jul 02 09:40:14 AM PDT 24
Peak memory 217792 kb
Host smart-b59bdcca-fdb5-4a4a-a6a1-c8ce6d16054b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020113901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.1020113901
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.1190472432
Short name T228
Test name
Test status
Simulation time 969560783 ps
CPU time 9.75 seconds
Started Jul 02 09:40:07 AM PDT 24
Finished Jul 02 09:40:18 AM PDT 24
Peak memory 217220 kb
Host smart-ca3de4e6-b5d7-441c-9127-e17cd742655f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190472432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.1190472432
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.292685456
Short name T106
Test name
Test status
Simulation time 991248176 ps
CPU time 36.34 seconds
Started Jul 02 09:40:09 AM PDT 24
Finished Jul 02 09:40:47 AM PDT 24
Peak memory 269748 kb
Host smart-983b09da-2b3f-4265-a2bd-0ef26084aadb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292685456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.292685456
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.527559702
Short name T714
Test name
Test status
Simulation time 2665945940 ps
CPU time 16.06 seconds
Started Jul 02 09:40:03 AM PDT 24
Finished Jul 02 09:40:20 AM PDT 24
Peak memory 225660 kb
Host smart-7265cb9f-6281-4c92-82bf-1485db02e6a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527559702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.527559702
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.557737963
Short name T131
Test name
Test status
Simulation time 995687915 ps
CPU time 8.92 seconds
Started Jul 02 09:40:06 AM PDT 24
Finished Jul 02 09:40:16 AM PDT 24
Peak memory 225480 kb
Host smart-ccb28665-a74d-44e9-9fa0-bf3e8f4ac82d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557737963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_dig
est.557737963
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.444038202
Short name T792
Test name
Test status
Simulation time 1270964681 ps
CPU time 12.07 seconds
Started Jul 02 09:40:08 AM PDT 24
Finished Jul 02 09:40:21 AM PDT 24
Peak memory 225504 kb
Host smart-1c69ea89-a43a-45a4-9106-2254598e933c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444038202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.444038202
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.3926850964
Short name T867
Test name
Test status
Simulation time 367297303 ps
CPU time 13.04 seconds
Started Jul 02 09:40:06 AM PDT 24
Finished Jul 02 09:40:19 AM PDT 24
Peak memory 225564 kb
Host smart-3fb93407-a498-4c1d-a750-14d2fbc6a2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926850964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.3926850964
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.3679952653
Short name T90
Test name
Test status
Simulation time 287780374 ps
CPU time 3.02 seconds
Started Jul 02 09:40:05 AM PDT 24
Finished Jul 02 09:40:09 AM PDT 24
Peak memory 217280 kb
Host smart-3a402f82-37c5-4b85-a3d3-9dea3f04c10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679952653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.3679952653
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.3315322264
Short name T273
Test name
Test status
Simulation time 447596040 ps
CPU time 28.72 seconds
Started Jul 02 09:40:04 AM PDT 24
Finished Jul 02 09:40:34 AM PDT 24
Peak memory 250516 kb
Host smart-afd76f98-9528-4e46-8b2c-c3690920c7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315322264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.3315322264
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.1914739719
Short name T755
Test name
Test status
Simulation time 482149139 ps
CPU time 7.57 seconds
Started Jul 02 09:40:04 AM PDT 24
Finished Jul 02 09:40:12 AM PDT 24
Peak memory 246356 kb
Host smart-81133880-1f8d-43e5-88bc-02b0b4004471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914739719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.1914739719
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.2602311207
Short name T323
Test name
Test status
Simulation time 1196988479 ps
CPU time 53.7 seconds
Started Jul 02 09:40:03 AM PDT 24
Finished Jul 02 09:40:58 AM PDT 24
Peak memory 251008 kb
Host smart-006c184d-10fb-46bf-a729-85b5fc241a11
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602311207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.2602311207
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.1017454313
Short name T445
Test name
Test status
Simulation time 14917856 ps
CPU time 1.13 seconds
Started Jul 02 09:40:06 AM PDT 24
Finished Jul 02 09:40:08 AM PDT 24
Peak memory 211400 kb
Host smart-539cb9dd-2a87-4e27-bd43-5b54f594805c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017454313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.1017454313
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.3812902543
Short name T561
Test name
Test status
Simulation time 62263544 ps
CPU time 0.93 seconds
Started Jul 02 09:41:17 AM PDT 24
Finished Jul 02 09:41:20 AM PDT 24
Peak memory 208612 kb
Host smart-08782ef2-11d4-48c2-a10a-de07a0d54cb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812902543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.3812902543
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.2799249805
Short name T752
Test name
Test status
Simulation time 362342546 ps
CPU time 16.28 seconds
Started Jul 02 09:41:16 AM PDT 24
Finished Jul 02 09:41:35 AM PDT 24
Peak memory 217772 kb
Host smart-eec882e2-41fd-4ed7-a35b-fd3b64001a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799249805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.2799249805
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.4179230905
Short name T700
Test name
Test status
Simulation time 328019763 ps
CPU time 9.02 seconds
Started Jul 02 09:41:15 AM PDT 24
Finished Jul 02 09:41:27 AM PDT 24
Peak memory 217196 kb
Host smart-c0a3b00a-d9bb-4a6e-92fe-a4333c8d46cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179230905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.4179230905
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.2835806543
Short name T497
Test name
Test status
Simulation time 472067886 ps
CPU time 3.21 seconds
Started Jul 02 09:41:16 AM PDT 24
Finished Jul 02 09:41:21 AM PDT 24
Peak memory 217768 kb
Host smart-3e34512e-6447-41a9-9268-d1ab88d411a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835806543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.2835806543
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.1149582159
Short name T705
Test name
Test status
Simulation time 1544164734 ps
CPU time 10.6 seconds
Started Jul 02 09:41:16 AM PDT 24
Finished Jul 02 09:41:29 AM PDT 24
Peak memory 225744 kb
Host smart-b4cfe6e5-8d65-4f51-b54f-1c9abc1873b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149582159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.1149582159
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.3042786423
Short name T462
Test name
Test status
Simulation time 1843880065 ps
CPU time 6.76 seconds
Started Jul 02 09:41:17 AM PDT 24
Finished Jul 02 09:41:26 AM PDT 24
Peak memory 225488 kb
Host smart-7f1343b6-bc13-408c-b474-07bcb0fcc695
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042786423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.3042786423
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.3780433448
Short name T354
Test name
Test status
Simulation time 1483275971 ps
CPU time 12.18 seconds
Started Jul 02 09:41:17 AM PDT 24
Finished Jul 02 09:41:31 AM PDT 24
Peak memory 225524 kb
Host smart-47fb0a41-c8f0-40ef-9460-1a143793ca13
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780433448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
3780433448
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.2869784047
Short name T562
Test name
Test status
Simulation time 329336218 ps
CPU time 11.14 seconds
Started Jul 02 09:41:17 AM PDT 24
Finished Jul 02 09:41:31 AM PDT 24
Peak memory 224712 kb
Host smart-80fbdfe7-8011-452b-9c38-bd4684e523fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869784047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.2869784047
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.579409818
Short name T197
Test name
Test status
Simulation time 33702346 ps
CPU time 1.55 seconds
Started Jul 02 09:41:17 AM PDT 24
Finished Jul 02 09:41:20 AM PDT 24
Peak memory 222596 kb
Host smart-8ac70e96-1b2a-451c-9a6e-433e9230ff46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579409818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.579409818
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.1320901288
Short name T863
Test name
Test status
Simulation time 271942260 ps
CPU time 28.4 seconds
Started Jul 02 09:41:17 AM PDT 24
Finished Jul 02 09:41:47 AM PDT 24
Peak memory 250508 kb
Host smart-22a761e0-d11e-4766-9d4f-cbed09bdb26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320901288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.1320901288
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.1466843963
Short name T652
Test name
Test status
Simulation time 242024938 ps
CPU time 6.49 seconds
Started Jul 02 09:41:15 AM PDT 24
Finished Jul 02 09:41:24 AM PDT 24
Peak memory 246620 kb
Host smart-75260c8e-4739-4b4e-82fd-d8d2c13aa9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466843963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.1466843963
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.2809112556
Short name T695
Test name
Test status
Simulation time 13878570848 ps
CPU time 97.5 seconds
Started Jul 02 09:41:14 AM PDT 24
Finished Jul 02 09:42:54 AM PDT 24
Peak memory 267868 kb
Host smart-e13a554e-e612-4bb7-aa38-7eb94712dcd2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809112556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.2809112556
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.2065229930
Short name T418
Test name
Test status
Simulation time 15717587 ps
CPU time 0.98 seconds
Started Jul 02 09:41:14 AM PDT 24
Finished Jul 02 09:41:18 AM PDT 24
Peak memory 208388 kb
Host smart-d70ddb0d-7880-4d3a-96b2-6d4b038550b0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065229930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.2065229930
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.517076702
Short name T517
Test name
Test status
Simulation time 177432049 ps
CPU time 0.86 seconds
Started Jul 02 09:41:20 AM PDT 24
Finished Jul 02 09:41:23 AM PDT 24
Peak memory 208532 kb
Host smart-ac8ab43b-b6eb-4d37-a556-10263e9c2090
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517076702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.517076702
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.2076631591
Short name T58
Test name
Test status
Simulation time 277756296 ps
CPU time 13.02 seconds
Started Jul 02 09:41:19 AM PDT 24
Finished Jul 02 09:41:34 AM PDT 24
Peak memory 225552 kb
Host smart-2d152128-1eca-402f-88c8-e52089bb5ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076631591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.2076631591
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.3673784893
Short name T605
Test name
Test status
Simulation time 2078518820 ps
CPU time 12.64 seconds
Started Jul 02 09:41:21 AM PDT 24
Finished Jul 02 09:41:36 AM PDT 24
Peak memory 216924 kb
Host smart-24595cb6-7afc-4b96-9b3c-afaac47af3b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673784893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.3673784893
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.1509529371
Short name T238
Test name
Test status
Simulation time 269552451 ps
CPU time 2.98 seconds
Started Jul 02 09:41:24 AM PDT 24
Finished Jul 02 09:41:28 AM PDT 24
Peak memory 221756 kb
Host smart-450597e1-9c8b-4ac8-835e-9d62bb9ac07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509529371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.1509529371
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.1035645018
Short name T657
Test name
Test status
Simulation time 851773315 ps
CPU time 10.13 seconds
Started Jul 02 09:41:20 AM PDT 24
Finished Jul 02 09:41:33 AM PDT 24
Peak memory 218448 kb
Host smart-44ecf47d-bb2e-45f1-b7c1-31b983e909d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035645018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.1035645018
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.4293056175
Short name T268
Test name
Test status
Simulation time 933912581 ps
CPU time 8.87 seconds
Started Jul 02 09:41:25 AM PDT 24
Finished Jul 02 09:41:36 AM PDT 24
Peak memory 225496 kb
Host smart-98c4d3b7-fd3a-4b7a-ac55-c7f41e4324cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293056175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.4293056175
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.3096549243
Short name T646
Test name
Test status
Simulation time 434121946 ps
CPU time 8 seconds
Started Jul 02 09:41:18 AM PDT 24
Finished Jul 02 09:41:28 AM PDT 24
Peak memory 217708 kb
Host smart-943352a5-cebe-4364-87ea-208f17011fee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096549243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
3096549243
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.2773965963
Short name T638
Test name
Test status
Simulation time 4338194013 ps
CPU time 8.94 seconds
Started Jul 02 09:41:20 AM PDT 24
Finished Jul 02 09:41:31 AM PDT 24
Peak memory 225632 kb
Host smart-d92442a1-c5b4-4b0c-b734-3279dbcdde1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773965963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.2773965963
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.4136761717
Short name T382
Test name
Test status
Simulation time 51985377 ps
CPU time 1 seconds
Started Jul 02 09:41:14 AM PDT 24
Finished Jul 02 09:41:18 AM PDT 24
Peak memory 211776 kb
Host smart-c1b72d68-0aa6-4b20-ab27-313001dbb5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136761717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.4136761717
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.852776246
Short name T851
Test name
Test status
Simulation time 585477745 ps
CPU time 24.76 seconds
Started Jul 02 09:41:17 AM PDT 24
Finished Jul 02 09:41:44 AM PDT 24
Peak memory 250504 kb
Host smart-d5af2c00-a530-41be-af67-5e5321851f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852776246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.852776246
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.2559522086
Short name T812
Test name
Test status
Simulation time 236592672 ps
CPU time 9.34 seconds
Started Jul 02 09:41:21 AM PDT 24
Finished Jul 02 09:41:32 AM PDT 24
Peak memory 250628 kb
Host smart-1fe11fb4-2c62-4515-b37c-5408f43a79c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559522086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.2559522086
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.2066767487
Short name T613
Test name
Test status
Simulation time 3342693300 ps
CPU time 140.41 seconds
Started Jul 02 09:41:20 AM PDT 24
Finished Jul 02 09:43:42 AM PDT 24
Peak memory 250732 kb
Host smart-98281ed3-3f43-4be2-8333-dddf49edc4fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066767487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.2066767487
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.1920206620
Short name T476
Test name
Test status
Simulation time 8179761745 ps
CPU time 389.78 seconds
Started Jul 02 09:41:22 AM PDT 24
Finished Jul 02 09:47:54 AM PDT 24
Peak memory 496460 kb
Host smart-9f58c3d5-ad0e-4074-a926-2526fa5f29f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1920206620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all_with_rand_reset.1920206620
Directory /workspace/21.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.2871368601
Short name T44
Test name
Test status
Simulation time 47270770 ps
CPU time 0.85 seconds
Started Jul 02 09:41:14 AM PDT 24
Finished Jul 02 09:41:17 AM PDT 24
Peak memory 211384 kb
Host smart-268471e4-7ea4-4cd1-b2a6-672e4d618dde
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871368601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.2871368601
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.2739187027
Short name T532
Test name
Test status
Simulation time 61477774 ps
CPU time 0.9 seconds
Started Jul 02 09:41:27 AM PDT 24
Finished Jul 02 09:41:30 AM PDT 24
Peak memory 208536 kb
Host smart-9b1be8ad-1d23-471a-97ad-f978e8da830d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739187027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.2739187027
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.2748149037
Short name T846
Test name
Test status
Simulation time 1361346061 ps
CPU time 9.07 seconds
Started Jul 02 09:41:22 AM PDT 24
Finished Jul 02 09:41:33 AM PDT 24
Peak memory 217716 kb
Host smart-577d056f-160d-4748-b2f7-2cca642c62ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748149037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.2748149037
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.3805586418
Short name T710
Test name
Test status
Simulation time 789322829 ps
CPU time 1.85 seconds
Started Jul 02 09:41:19 AM PDT 24
Finished Jul 02 09:41:22 AM PDT 24
Peak memory 217380 kb
Host smart-32947f62-833f-4f37-b1bb-5a7fb04af411
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805586418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.3805586418
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.442649446
Short name T449
Test name
Test status
Simulation time 199688167 ps
CPU time 2.81 seconds
Started Jul 02 09:41:21 AM PDT 24
Finished Jul 02 09:41:26 AM PDT 24
Peak memory 217688 kb
Host smart-51cda9cf-ec17-40e7-bbff-1501b257453b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442649446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.442649446
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.4218579343
Short name T424
Test name
Test status
Simulation time 880322144 ps
CPU time 8.73 seconds
Started Jul 02 09:41:20 AM PDT 24
Finished Jul 02 09:41:30 AM PDT 24
Peak memory 225512 kb
Host smart-cb6b5cb9-a5d0-4c85-8448-f0afe58cdceb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218579343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.4218579343
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.1182610012
Short name T463
Test name
Test status
Simulation time 815725049 ps
CPU time 13.55 seconds
Started Jul 02 09:41:25 AM PDT 24
Finished Jul 02 09:41:41 AM PDT 24
Peak memory 217708 kb
Host smart-534845b3-c928-463f-87f7-af2d0b70ae32
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182610012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
1182610012
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.615418999
Short name T442
Test name
Test status
Simulation time 235393344 ps
CPU time 7.93 seconds
Started Jul 02 09:41:23 AM PDT 24
Finished Jul 02 09:41:33 AM PDT 24
Peak memory 225476 kb
Host smart-0d286cc0-97a1-455e-9cc9-f48e6d0c8887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615418999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.615418999
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.1298146210
Short name T322
Test name
Test status
Simulation time 106066843 ps
CPU time 2.33 seconds
Started Jul 02 09:41:22 AM PDT 24
Finished Jul 02 09:41:27 AM PDT 24
Peak memory 213920 kb
Host smart-1b89cf46-25bd-4962-b42c-f0c58dd5dd48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298146210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.1298146210
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.3063247053
Short name T277
Test name
Test status
Simulation time 233800078 ps
CPU time 20.39 seconds
Started Jul 02 09:41:22 AM PDT 24
Finished Jul 02 09:41:45 AM PDT 24
Peak memory 250520 kb
Host smart-10a04fb2-e102-4f58-95c3-7348e518ec4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063247053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.3063247053
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.2956447179
Short name T369
Test name
Test status
Simulation time 151625079 ps
CPU time 6.38 seconds
Started Jul 02 09:41:21 AM PDT 24
Finished Jul 02 09:41:30 AM PDT 24
Peak memory 246284 kb
Host smart-c62377fb-6a6b-47c8-b9c5-656e324d5c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956447179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.2956447179
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.3523618861
Short name T116
Test name
Test status
Simulation time 8732802746 ps
CPU time 287.59 seconds
Started Jul 02 09:41:20 AM PDT 24
Finished Jul 02 09:46:09 AM PDT 24
Peak memory 279428 kb
Host smart-d3e32d6d-1823-4d7a-8909-53a69c0df82a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523618861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.3523618861
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.1561869962
Short name T162
Test name
Test status
Simulation time 44234289721 ps
CPU time 571.53 seconds
Started Jul 02 09:41:20 AM PDT 24
Finished Jul 02 09:50:53 AM PDT 24
Peak memory 291264 kb
Host smart-8d85d9a0-ccb4-4039-ab7e-0169e3e42e2b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1561869962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all_with_rand_reset.1561869962
Directory /workspace/22.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.1232303839
Short name T750
Test name
Test status
Simulation time 54486554 ps
CPU time 0.89 seconds
Started Jul 02 09:41:21 AM PDT 24
Finished Jul 02 09:41:25 AM PDT 24
Peak memory 211348 kb
Host smart-66b43f3e-21f4-47b6-87d0-6e403d3be883
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232303839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.1232303839
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.1905602016
Short name T244
Test name
Test status
Simulation time 38207579 ps
CPU time 1.05 seconds
Started Jul 02 09:41:25 AM PDT 24
Finished Jul 02 09:41:27 AM PDT 24
Peak memory 208584 kb
Host smart-acd96508-f4dd-4533-b2bd-9ef392aa62c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905602016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.1905602016
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.3115026250
Short name T245
Test name
Test status
Simulation time 470543314 ps
CPU time 10.61 seconds
Started Jul 02 09:41:23 AM PDT 24
Finished Jul 02 09:41:35 AM PDT 24
Peak memory 225592 kb
Host smart-ba04f7ba-e340-418c-9ac3-0ced33447420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115026250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.3115026250
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.2717544997
Short name T373
Test name
Test status
Simulation time 2806609995 ps
CPU time 4.95 seconds
Started Jul 02 09:41:27 AM PDT 24
Finished Jul 02 09:41:34 AM PDT 24
Peak memory 217164 kb
Host smart-264159bf-0f5e-44ae-96bc-17342bbc614a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717544997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.2717544997
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.2744008095
Short name T391
Test name
Test status
Simulation time 64305021 ps
CPU time 1.99 seconds
Started Jul 02 09:41:25 AM PDT 24
Finished Jul 02 09:41:28 AM PDT 24
Peak memory 221688 kb
Host smart-7a323af9-b7c8-404b-be49-ba3c3f582ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744008095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.2744008095
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.3069008758
Short name T829
Test name
Test status
Simulation time 287988297 ps
CPU time 9.89 seconds
Started Jul 02 09:41:24 AM PDT 24
Finished Jul 02 09:41:36 AM PDT 24
Peak memory 218388 kb
Host smart-89a50b26-52af-43e6-9562-c7693f047147
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069008758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.3069008758
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.4214816582
Short name T259
Test name
Test status
Simulation time 355895126 ps
CPU time 13.64 seconds
Started Jul 02 09:41:25 AM PDT 24
Finished Jul 02 09:41:40 AM PDT 24
Peak memory 225408 kb
Host smart-13089a4d-d589-4528-bef4-07b0644a7033
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214816582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.4214816582
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.181631085
Short name T836
Test name
Test status
Simulation time 627850987 ps
CPU time 8.57 seconds
Started Jul 02 09:41:25 AM PDT 24
Finished Jul 02 09:41:36 AM PDT 24
Peak memory 217708 kb
Host smart-9e085da3-61f8-40d3-8d56-47af7c5e4ccd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181631085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.181631085
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.3212158359
Short name T41
Test name
Test status
Simulation time 369701137 ps
CPU time 7.14 seconds
Started Jul 02 09:41:21 AM PDT 24
Finished Jul 02 09:41:31 AM PDT 24
Peak memory 217860 kb
Host smart-f1f9c37a-1286-47a9-b153-e35cf87d4267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212158359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.3212158359
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.3726679619
Short name T815
Test name
Test status
Simulation time 64038814 ps
CPU time 2.37 seconds
Started Jul 02 09:41:21 AM PDT 24
Finished Jul 02 09:41:26 AM PDT 24
Peak memory 214044 kb
Host smart-d172636e-763a-474f-9a80-911585b39e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726679619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.3726679619
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.1841536233
Short name T494
Test name
Test status
Simulation time 991365712 ps
CPU time 23.19 seconds
Started Jul 02 09:41:25 AM PDT 24
Finished Jul 02 09:41:51 AM PDT 24
Peak memory 250524 kb
Host smart-2674a79b-f57f-4ece-87b3-43630b500978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841536233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.1841536233
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.2113683187
Short name T691
Test name
Test status
Simulation time 117218614 ps
CPU time 7.61 seconds
Started Jul 02 09:41:26 AM PDT 24
Finished Jul 02 09:41:35 AM PDT 24
Peak memory 246200 kb
Host smart-307da108-7514-4cd3-8374-6ac07fde0a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113683187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.2113683187
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.2524752468
Short name T333
Test name
Test status
Simulation time 6657012324 ps
CPU time 71.28 seconds
Started Jul 02 09:41:24 AM PDT 24
Finished Jul 02 09:42:37 AM PDT 24
Peak memory 271408 kb
Host smart-35844131-87e5-454b-a3a7-6aa1ea421984
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524752468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.2524752468
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.723001183
Short name T42
Test name
Test status
Simulation time 14333723 ps
CPU time 0.79 seconds
Started Jul 02 09:41:25 AM PDT 24
Finished Jul 02 09:41:27 AM PDT 24
Peak memory 208372 kb
Host smart-9547001b-31e7-4754-b663-44c05e70283c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723001183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ct
rl_volatile_unlock_smoke.723001183
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.3437816498
Short name T200
Test name
Test status
Simulation time 16928969 ps
CPU time 0.96 seconds
Started Jul 02 09:41:29 AM PDT 24
Finished Jul 02 09:41:31 AM PDT 24
Peak memory 208508 kb
Host smart-047e7670-05c6-428f-ae92-e0a6efde2461
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437816498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.3437816498
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.2574313267
Short name T309
Test name
Test status
Simulation time 655508903 ps
CPU time 8.73 seconds
Started Jul 02 09:41:21 AM PDT 24
Finished Jul 02 09:41:33 AM PDT 24
Peak memory 217688 kb
Host smart-99dfd3da-42ce-4c2d-a051-86e0cf72c5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574313267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.2574313267
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.3294194083
Short name T557
Test name
Test status
Simulation time 147045059 ps
CPU time 4.23 seconds
Started Jul 02 09:41:23 AM PDT 24
Finished Jul 02 09:41:29 AM PDT 24
Peak memory 216708 kb
Host smart-4206f0f3-0389-47e6-a4b6-c90b9641e460
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294194083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.3294194083
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.739754677
Short name T799
Test name
Test status
Simulation time 288568035 ps
CPU time 3.44 seconds
Started Jul 02 09:41:22 AM PDT 24
Finished Jul 02 09:41:28 AM PDT 24
Peak memory 217764 kb
Host smart-cf74f647-ad95-4d64-99d2-f0f10310315d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739754677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.739754677
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.4262318932
Short name T344
Test name
Test status
Simulation time 239445877 ps
CPU time 9.45 seconds
Started Jul 02 09:41:25 AM PDT 24
Finished Jul 02 09:41:36 AM PDT 24
Peak memory 225568 kb
Host smart-809aa929-a454-4191-9471-d584ec172712
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262318932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.4262318932
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.4220415954
Short name T266
Test name
Test status
Simulation time 3916327545 ps
CPU time 14.29 seconds
Started Jul 02 09:41:26 AM PDT 24
Finished Jul 02 09:41:42 AM PDT 24
Peak memory 225416 kb
Host smart-1e500e0b-c158-4726-b813-7ef9dbc84225
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220415954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.4220415954
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.4288139925
Short name T502
Test name
Test status
Simulation time 161431329 ps
CPU time 5.09 seconds
Started Jul 02 09:41:27 AM PDT 24
Finished Jul 02 09:41:34 AM PDT 24
Peak memory 217740 kb
Host smart-296b4708-b58b-49b3-9989-21852bc49551
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288139925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
4288139925
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.3602017166
Short name T806
Test name
Test status
Simulation time 471631805 ps
CPU time 7.36 seconds
Started Jul 02 09:41:27 AM PDT 24
Finished Jul 02 09:41:36 AM PDT 24
Peak memory 225584 kb
Host smart-db8fc3bc-e11a-4fa2-b907-adfcfb6fd138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602017166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.3602017166
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.2073710191
Short name T375
Test name
Test status
Simulation time 69763612 ps
CPU time 1.38 seconds
Started Jul 02 09:41:24 AM PDT 24
Finished Jul 02 09:41:27 AM PDT 24
Peak memory 217200 kb
Host smart-eb0fd93f-bde3-4ddc-8705-b06b579c4d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073710191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.2073710191
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.260119601
Short name T388
Test name
Test status
Simulation time 177141887 ps
CPU time 22.73 seconds
Started Jul 02 09:41:23 AM PDT 24
Finished Jul 02 09:41:48 AM PDT 24
Peak memory 250544 kb
Host smart-c0d24229-c69a-4adc-acdf-7014d9fcf72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260119601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.260119601
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.4168755461
Short name T185
Test name
Test status
Simulation time 83656332 ps
CPU time 6.58 seconds
Started Jul 02 09:41:27 AM PDT 24
Finished Jul 02 09:41:35 AM PDT 24
Peak memory 250104 kb
Host smart-0125bd79-6697-48f2-b38a-1189c21adffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168755461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.4168755461
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.3588593639
Short name T692
Test name
Test status
Simulation time 16962262634 ps
CPU time 572.51 seconds
Started Jul 02 09:41:29 AM PDT 24
Finished Jul 02 09:51:03 AM PDT 24
Peak memory 267596 kb
Host smart-761d0175-b743-4e94-95d6-7453bcbddbbf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588593639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.3588593639
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.3011252154
Short name T124
Test name
Test status
Simulation time 108591511521 ps
CPU time 920.18 seconds
Started Jul 02 09:41:29 AM PDT 24
Finished Jul 02 09:56:50 AM PDT 24
Peak memory 332620 kb
Host smart-8c0e6f9b-939d-4164-9d5a-bd82d4d14885
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3011252154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all_with_rand_reset.3011252154
Directory /workspace/24.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.1997335428
Short name T511
Test name
Test status
Simulation time 87971330 ps
CPU time 0.9 seconds
Started Jul 02 09:41:25 AM PDT 24
Finished Jul 02 09:41:28 AM PDT 24
Peak memory 211332 kb
Host smart-3a7134cc-f368-4b79-8e40-dd25dcec92b6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997335428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.1997335428
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.191987277
Short name T490
Test name
Test status
Simulation time 23372205 ps
CPU time 1.03 seconds
Started Jul 02 09:41:33 AM PDT 24
Finished Jul 02 09:41:34 AM PDT 24
Peak memory 208572 kb
Host smart-51d6e528-13d4-4262-8c59-88907efe5346
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191987277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.191987277
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.2769273242
Short name T438
Test name
Test status
Simulation time 962573898 ps
CPU time 22.17 seconds
Started Jul 02 09:41:26 AM PDT 24
Finished Jul 02 09:41:50 AM PDT 24
Peak memory 225572 kb
Host smart-092b54a9-aae4-454a-a18a-0ca5801753e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769273242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.2769273242
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.986160530
Short name T647
Test name
Test status
Simulation time 105583273 ps
CPU time 2.04 seconds
Started Jul 02 09:41:29 AM PDT 24
Finished Jul 02 09:41:32 AM PDT 24
Peak memory 216672 kb
Host smart-3164333a-d9e4-4b5d-a3ff-c378f53318cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986160530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.986160530
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.1846359248
Short name T103
Test name
Test status
Simulation time 55916447 ps
CPU time 2.94 seconds
Started Jul 02 09:41:27 AM PDT 24
Finished Jul 02 09:41:32 AM PDT 24
Peak memory 217764 kb
Host smart-66fd44a2-902f-4e7e-9af6-9d9ddc3de1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846359248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.1846359248
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.4089181620
Short name T654
Test name
Test status
Simulation time 358404185 ps
CPU time 11.72 seconds
Started Jul 02 09:41:30 AM PDT 24
Finished Jul 02 09:41:43 AM PDT 24
Peak memory 218688 kb
Host smart-c2c6f803-f601-419c-9f6d-4041374d118c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089181620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.4089181620
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.3954641136
Short name T825
Test name
Test status
Simulation time 494293654 ps
CPU time 7.09 seconds
Started Jul 02 09:41:30 AM PDT 24
Finished Jul 02 09:41:38 AM PDT 24
Peak memory 225484 kb
Host smart-25ad4423-0346-4d6e-9667-d061d0b81e5e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954641136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.3954641136
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.1698277759
Short name T536
Test name
Test status
Simulation time 570204989 ps
CPU time 8.72 seconds
Started Jul 02 09:41:32 AM PDT 24
Finished Jul 02 09:41:42 AM PDT 24
Peak memory 217644 kb
Host smart-52fc0ce8-7a2f-48f5-a53d-8518d32a0c0f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698277759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
1698277759
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.2656735214
Short name T811
Test name
Test status
Simulation time 410204872 ps
CPU time 10.17 seconds
Started Jul 02 09:41:28 AM PDT 24
Finished Jul 02 09:41:40 AM PDT 24
Peak memory 224456 kb
Host smart-e171196b-180f-45d6-ba1c-e50ced22de99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656735214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.2656735214
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.3393257358
Short name T662
Test name
Test status
Simulation time 44396158 ps
CPU time 2.27 seconds
Started Jul 02 09:41:30 AM PDT 24
Finished Jul 02 09:41:33 AM PDT 24
Peak memory 223180 kb
Host smart-5ac40c00-0069-4557-97b2-086c8838b0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393257358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.3393257358
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.1473551002
Short name T366
Test name
Test status
Simulation time 344975167 ps
CPU time 29.06 seconds
Started Jul 02 09:41:25 AM PDT 24
Finished Jul 02 09:41:56 AM PDT 24
Peak memory 250544 kb
Host smart-348d7182-7440-4542-8a8e-fa17b3c2ef0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473551002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.1473551002
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.1487491689
Short name T539
Test name
Test status
Simulation time 284830386 ps
CPU time 6.68 seconds
Started Jul 02 09:41:28 AM PDT 24
Finished Jul 02 09:41:36 AM PDT 24
Peak memory 248076 kb
Host smart-5fe65ef6-1cf7-400d-85ee-fdb836d2d705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487491689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.1487491689
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.1658263087
Short name T43
Test name
Test status
Simulation time 25706475 ps
CPU time 1.03 seconds
Started Jul 02 09:41:25 AM PDT 24
Finished Jul 02 09:41:28 AM PDT 24
Peak memory 211468 kb
Host smart-2b19052b-094a-4003-8bb1-e87b74a0833a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658263087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.1658263087
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.2520766140
Short name T282
Test name
Test status
Simulation time 18877858 ps
CPU time 0.88 seconds
Started Jul 02 09:41:32 AM PDT 24
Finished Jul 02 09:41:34 AM PDT 24
Peak memory 208584 kb
Host smart-f807539e-e41e-483e-96e9-29cb3b77c588
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520766140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.2520766140
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.2733757525
Short name T285
Test name
Test status
Simulation time 603588648 ps
CPU time 12.18 seconds
Started Jul 02 09:41:27 AM PDT 24
Finished Jul 02 09:41:41 AM PDT 24
Peak memory 217784 kb
Host smart-d8c80972-11aa-4e76-9834-7d0685fcffc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733757525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.2733757525
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.3911806790
Short name T101
Test name
Test status
Simulation time 42209714 ps
CPU time 1.54 seconds
Started Jul 02 09:41:27 AM PDT 24
Finished Jul 02 09:41:31 AM PDT 24
Peak memory 217784 kb
Host smart-381615b3-2e42-4cbb-88c0-351565c06530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911806790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.3911806790
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.2192499017
Short name T569
Test name
Test status
Simulation time 3086806916 ps
CPU time 12.27 seconds
Started Jul 02 09:41:32 AM PDT 24
Finished Jul 02 09:41:46 AM PDT 24
Peak memory 219104 kb
Host smart-fdefb0fc-7c86-430e-89e0-bcd1acd30ca2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192499017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.2192499017
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.1085436583
Short name T242
Test name
Test status
Simulation time 363347548 ps
CPU time 14.54 seconds
Started Jul 02 09:41:31 AM PDT 24
Finished Jul 02 09:41:47 AM PDT 24
Peak memory 225696 kb
Host smart-14f0cfad-1180-44a5-ab88-27b49c75bf2d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085436583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.1085436583
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.3380716123
Short name T432
Test name
Test status
Simulation time 851994658 ps
CPU time 14.29 seconds
Started Jul 02 09:41:32 AM PDT 24
Finished Jul 02 09:41:47 AM PDT 24
Peak memory 217744 kb
Host smart-b41abeca-71e4-42c2-af2e-7202e31c5ff3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380716123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
3380716123
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.2189104693
Short name T365
Test name
Test status
Simulation time 430006098 ps
CPU time 6.67 seconds
Started Jul 02 09:41:35 AM PDT 24
Finished Jul 02 09:41:43 AM PDT 24
Peak memory 217940 kb
Host smart-dd994cae-cee3-4667-93e5-2482642d865a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189104693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.2189104693
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.2842244659
Short name T83
Test name
Test status
Simulation time 16335013 ps
CPU time 1.37 seconds
Started Jul 02 09:41:26 AM PDT 24
Finished Jul 02 09:41:30 AM PDT 24
Peak memory 221292 kb
Host smart-0e030a29-8a79-473b-ad2d-42db77b76e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842244659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.2842244659
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.2645881312
Short name T109
Test name
Test status
Simulation time 1250890242 ps
CPU time 32.11 seconds
Started Jul 02 09:41:30 AM PDT 24
Finished Jul 02 09:42:03 AM PDT 24
Peak memory 250548 kb
Host smart-5470b7ab-f17e-4f32-be3f-f8599ddb59df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645881312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.2645881312
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.1307374173
Short name T862
Test name
Test status
Simulation time 295177072 ps
CPU time 7.6 seconds
Started Jul 02 09:41:27 AM PDT 24
Finished Jul 02 09:41:36 AM PDT 24
Peak memory 250348 kb
Host smart-473c6911-96b1-4409-a809-fba1202ee2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307374173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.1307374173
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.1581084432
Short name T433
Test name
Test status
Simulation time 1527285151 ps
CPU time 41.87 seconds
Started Jul 02 09:41:31 AM PDT 24
Finished Jul 02 09:42:14 AM PDT 24
Peak memory 217356 kb
Host smart-fff37094-4a87-421a-909b-133c9dda5227
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581084432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.1581084432
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1665282066
Short name T46
Test name
Test status
Simulation time 12107194 ps
CPU time 0.79 seconds
Started Jul 02 09:41:30 AM PDT 24
Finished Jul 02 09:41:31 AM PDT 24
Peak memory 208356 kb
Host smart-a701c01d-6d44-414c-9262-c2a8c8678b8d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665282066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.1665282066
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.3995000261
Short name T257
Test name
Test status
Simulation time 18822950 ps
CPU time 1.13 seconds
Started Jul 02 09:41:33 AM PDT 24
Finished Jul 02 09:41:35 AM PDT 24
Peak memory 208612 kb
Host smart-3c1e28d7-f6b5-42e4-b15f-31cb0d5ae95e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995000261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.3995000261
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.350801335
Short name T258
Test name
Test status
Simulation time 1159498961 ps
CPU time 9.09 seconds
Started Jul 02 09:41:33 AM PDT 24
Finished Jul 02 09:41:43 AM PDT 24
Peak memory 217800 kb
Host smart-676c065d-e6ac-43b9-96a3-a921901c3329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350801335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.350801335
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.2160495306
Short name T31
Test name
Test status
Simulation time 339090464 ps
CPU time 4.67 seconds
Started Jul 02 09:41:31 AM PDT 24
Finished Jul 02 09:41:37 AM PDT 24
Peak memory 216672 kb
Host smart-13f18bf8-4717-4400-bf1a-d1117e095a4b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160495306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.2160495306
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.1227262246
Short name T789
Test name
Test status
Simulation time 79234720 ps
CPU time 2.54 seconds
Started Jul 02 09:41:30 AM PDT 24
Finished Jul 02 09:41:33 AM PDT 24
Peak memory 217792 kb
Host smart-0f18c18f-9e39-4d53-a15d-aac70c697e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227262246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.1227262246
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.1780133852
Short name T629
Test name
Test status
Simulation time 689419256 ps
CPU time 10.99 seconds
Started Jul 02 09:41:31 AM PDT 24
Finished Jul 02 09:41:43 AM PDT 24
Peak memory 225576 kb
Host smart-3ccb57df-2024-4713-88ac-636f8d0e385c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780133852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.1780133852
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.1423338136
Short name T797
Test name
Test status
Simulation time 204197127 ps
CPU time 9.92 seconds
Started Jul 02 09:41:31 AM PDT 24
Finished Jul 02 09:41:41 AM PDT 24
Peak memory 225484 kb
Host smart-6f9043bc-1af4-48df-9268-0cb1ace7cc07
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423338136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.1423338136
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.2851298079
Short name T250
Test name
Test status
Simulation time 986344821 ps
CPU time 8.08 seconds
Started Jul 02 09:41:31 AM PDT 24
Finished Jul 02 09:41:40 AM PDT 24
Peak memory 225520 kb
Host smart-974a23ef-651b-4806-a6eb-0bb91b4b7b9f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851298079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
2851298079
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.2759956787
Short name T785
Test name
Test status
Simulation time 240503804 ps
CPU time 9.49 seconds
Started Jul 02 09:41:32 AM PDT 24
Finished Jul 02 09:41:43 AM PDT 24
Peak memory 224472 kb
Host smart-473de4d4-2ae2-4df9-bb18-bdaa55301c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759956787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.2759956787
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.822752221
Short name T571
Test name
Test status
Simulation time 583504919 ps
CPU time 2.75 seconds
Started Jul 02 09:41:32 AM PDT 24
Finished Jul 02 09:41:35 AM PDT 24
Peak memory 214340 kb
Host smart-2faa3b50-1bcf-4c62-b111-03d0a41a9f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822752221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.822752221
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.3310387599
Short name T771
Test name
Test status
Simulation time 491890019 ps
CPU time 22.98 seconds
Started Jul 02 09:41:35 AM PDT 24
Finished Jul 02 09:41:59 AM PDT 24
Peak memory 250440 kb
Host smart-44d24832-6466-4061-a0d5-0f8554483191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310387599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.3310387599
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.2963980944
Short name T17
Test name
Test status
Simulation time 80786626 ps
CPU time 2.97 seconds
Started Jul 02 09:41:33 AM PDT 24
Finished Jul 02 09:41:36 AM PDT 24
Peak memory 222028 kb
Host smart-2c3832c2-17e4-45d2-9549-b602a863f555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963980944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.2963980944
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.2484920529
Short name T690
Test name
Test status
Simulation time 9625852540 ps
CPU time 240.65 seconds
Started Jul 02 09:41:31 AM PDT 24
Finished Jul 02 09:45:33 AM PDT 24
Peak memory 248556 kb
Host smart-011a9882-7bc4-4216-856a-eef0270353e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484920529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.2484920529
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.1146372524
Short name T666
Test name
Test status
Simulation time 46821125 ps
CPU time 0.81 seconds
Started Jul 02 09:41:31 AM PDT 24
Finished Jul 02 09:41:33 AM PDT 24
Peak memory 208364 kb
Host smart-c6a8e845-1265-4b15-9ca9-1ccbb3ab9233
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146372524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.1146372524
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.2158769241
Short name T397
Test name
Test status
Simulation time 72175102 ps
CPU time 0.81 seconds
Started Jul 02 09:41:38 AM PDT 24
Finished Jul 02 09:41:40 AM PDT 24
Peak memory 208404 kb
Host smart-e21b53c2-1bb4-4f19-93c2-8114ded8204d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158769241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.2158769241
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.2038091328
Short name T290
Test name
Test status
Simulation time 1435566815 ps
CPU time 15.63 seconds
Started Jul 02 09:41:34 AM PDT 24
Finished Jul 02 09:41:51 AM PDT 24
Peak memory 217804 kb
Host smart-2d1046cb-8ffc-4744-8bf5-47e47da6d50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038091328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.2038091328
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.1951223714
Short name T186
Test name
Test status
Simulation time 174861851 ps
CPU time 1.3 seconds
Started Jul 02 09:41:34 AM PDT 24
Finished Jul 02 09:41:36 AM PDT 24
Peak memory 217160 kb
Host smart-6806da81-5096-41d0-875e-f192ce9356f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951223714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.1951223714
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.3541433184
Short name T563
Test name
Test status
Simulation time 363768449 ps
CPU time 2.4 seconds
Started Jul 02 09:41:35 AM PDT 24
Finished Jul 02 09:41:39 AM PDT 24
Peak memory 217788 kb
Host smart-fcbf70af-00bf-48ec-97aa-bb6d2cb19872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541433184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.3541433184
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.499421140
Short name T73
Test name
Test status
Simulation time 276549705 ps
CPU time 10.26 seconds
Started Jul 02 09:41:37 AM PDT 24
Finished Jul 02 09:41:48 AM PDT 24
Peak memory 225584 kb
Host smart-a525c008-b281-4ed1-93bf-9287c77e1b0f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499421140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.499421140
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.1350231063
Short name T247
Test name
Test status
Simulation time 2452586049 ps
CPU time 17.15 seconds
Started Jul 02 09:41:36 AM PDT 24
Finished Jul 02 09:41:54 AM PDT 24
Peak memory 217816 kb
Host smart-3f79d409-9b01-4b07-bd95-9bb07ea8b794
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350231063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.1350231063
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.1021159173
Short name T50
Test name
Test status
Simulation time 237014587 ps
CPU time 8.47 seconds
Started Jul 02 09:41:36 AM PDT 24
Finished Jul 02 09:41:46 AM PDT 24
Peak memory 217692 kb
Host smart-1c2bab64-7516-4103-8b74-4471e8faba02
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021159173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
1021159173
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.642871469
Short name T810
Test name
Test status
Simulation time 1231627070 ps
CPU time 17.23 seconds
Started Jul 02 09:41:38 AM PDT 24
Finished Jul 02 09:41:56 AM PDT 24
Peak memory 225512 kb
Host smart-c32dda98-4d65-4f0f-8b37-d3388e0342af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642871469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.642871469
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.1845334710
Short name T774
Test name
Test status
Simulation time 51978212 ps
CPU time 1.18 seconds
Started Jul 02 09:41:34 AM PDT 24
Finished Jul 02 09:41:36 AM PDT 24
Peak memory 217212 kb
Host smart-506577f7-3a52-428c-95d2-0f878b210d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845334710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.1845334710
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.4262229442
Short name T276
Test name
Test status
Simulation time 254753946 ps
CPU time 23.67 seconds
Started Jul 02 09:41:39 AM PDT 24
Finished Jul 02 09:42:03 AM PDT 24
Peak memory 250592 kb
Host smart-6d31d3cb-d453-4d35-838e-f2588a7421de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262229442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.4262229442
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.9420569
Short name T11
Test name
Test status
Simulation time 381354717 ps
CPU time 8.19 seconds
Started Jul 02 09:41:40 AM PDT 24
Finished Jul 02 09:41:49 AM PDT 24
Peak memory 250020 kb
Host smart-79c6ca32-8882-46ce-99c1-af582d109f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9420569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.9420569
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.1776098453
Short name T795
Test name
Test status
Simulation time 16969665 ps
CPU time 0.83 seconds
Started Jul 02 09:41:36 AM PDT 24
Finished Jul 02 09:41:38 AM PDT 24
Peak memory 208460 kb
Host smart-d370d5aa-156e-44a7-9d6c-435010f6c302
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776098453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.1776098453
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.769143431
Short name T660
Test name
Test status
Simulation time 27848235 ps
CPU time 0.91 seconds
Started Jul 02 09:41:39 AM PDT 24
Finished Jul 02 09:41:41 AM PDT 24
Peak memory 208552 kb
Host smart-4242f3ee-ca77-4c30-acbc-44ed14cecb94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769143431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.769143431
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.630511645
Short name T492
Test name
Test status
Simulation time 768950951 ps
CPU time 9.19 seconds
Started Jul 02 09:41:35 AM PDT 24
Finished Jul 02 09:41:44 AM PDT 24
Peak memory 217768 kb
Host smart-076af466-05bb-4cb7-8404-8b49a67569dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630511645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.630511645
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.1189051625
Short name T412
Test name
Test status
Simulation time 989461596 ps
CPU time 22.92 seconds
Started Jul 02 09:41:34 AM PDT 24
Finished Jul 02 09:41:58 AM PDT 24
Peak memory 216952 kb
Host smart-4e5db777-375c-40a8-b4cf-7fda79276963
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189051625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.1189051625
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.2686671298
Short name T649
Test name
Test status
Simulation time 342348790 ps
CPU time 3.16 seconds
Started Jul 02 09:41:36 AM PDT 24
Finished Jul 02 09:41:40 AM PDT 24
Peak memory 222152 kb
Host smart-dbddd939-82d5-4766-8a75-f2be1095a9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686671298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.2686671298
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.738570749
Short name T370
Test name
Test status
Simulation time 314197137 ps
CPU time 12.38 seconds
Started Jul 02 09:41:36 AM PDT 24
Finished Jul 02 09:41:50 AM PDT 24
Peak memory 225568 kb
Host smart-61440553-413f-402e-b6c4-dbb8f7ecaef1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738570749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.738570749
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.215751837
Short name T52
Test name
Test status
Simulation time 830862370 ps
CPU time 11.14 seconds
Started Jul 02 09:41:41 AM PDT 24
Finished Jul 02 09:41:53 AM PDT 24
Peak memory 225296 kb
Host smart-c33d09c3-7f60-4042-9c89-f2497fdcb8b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215751837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_di
gest.215751837
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.3347933662
Short name T363
Test name
Test status
Simulation time 156230022 ps
CPU time 7.03 seconds
Started Jul 02 09:41:40 AM PDT 24
Finished Jul 02 09:41:47 AM PDT 24
Peak memory 217584 kb
Host smart-b36cb489-a878-45f2-bc53-5b1a98933b0f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347933662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
3347933662
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.1901795878
Short name T332
Test name
Test status
Simulation time 530215042 ps
CPU time 10.16 seconds
Started Jul 02 09:41:37 AM PDT 24
Finished Jul 02 09:41:48 AM PDT 24
Peak memory 217860 kb
Host smart-c95c0e0f-6f3e-458d-bb66-d7a7514fd167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901795878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.1901795878
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.3779056296
Short name T624
Test name
Test status
Simulation time 40493102 ps
CPU time 1.12 seconds
Started Jul 02 09:41:36 AM PDT 24
Finished Jul 02 09:41:38 AM PDT 24
Peak memory 211560 kb
Host smart-64e1b49a-88d5-4e55-8bc0-2ad19d062300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779056296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.3779056296
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.3989675186
Short name T676
Test name
Test status
Simulation time 268346511 ps
CPU time 31.21 seconds
Started Jul 02 09:41:37 AM PDT 24
Finished Jul 02 09:42:09 AM PDT 24
Peak memory 250464 kb
Host smart-4c333e61-96db-44e1-9f8a-027beb6356fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989675186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.3989675186
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.646006632
Short name T824
Test name
Test status
Simulation time 317683712 ps
CPU time 6.11 seconds
Started Jul 02 09:41:36 AM PDT 24
Finished Jul 02 09:41:43 AM PDT 24
Peak memory 246280 kb
Host smart-535bdf92-23a5-4f5b-98f0-c7231b5b5256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646006632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.646006632
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.303514335
Short name T208
Test name
Test status
Simulation time 33497718724 ps
CPU time 183.57 seconds
Started Jul 02 09:41:41 AM PDT 24
Finished Jul 02 09:44:45 AM PDT 24
Peak memory 275656 kb
Host smart-f458a825-132a-4e3c-836b-47891bc00d85
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303514335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.303514335
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.3239971326
Short name T100
Test name
Test status
Simulation time 78110780 ps
CPU time 0.8 seconds
Started Jul 02 09:41:35 AM PDT 24
Finished Jul 02 09:41:37 AM PDT 24
Peak memory 208248 kb
Host smart-6f59bb5c-6fca-4342-889b-55e58fc76f0e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239971326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.3239971326
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.1782796851
Short name T718
Test name
Test status
Simulation time 21119332 ps
CPU time 0.88 seconds
Started Jul 02 09:40:17 AM PDT 24
Finished Jul 02 09:40:21 AM PDT 24
Peak memory 208416 kb
Host smart-b5da06e5-ca7f-4ffd-bda8-5b8686235163
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782796851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.1782796851
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.1769959657
Short name T138
Test name
Test status
Simulation time 22657154 ps
CPU time 0.89 seconds
Started Jul 02 09:40:14 AM PDT 24
Finished Jul 02 09:40:16 AM PDT 24
Peak memory 208448 kb
Host smart-07c51b53-7012-40de-a9fc-333d713328fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769959657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.1769959657
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.4143988791
Short name T236
Test name
Test status
Simulation time 1778874080 ps
CPU time 14.29 seconds
Started Jul 02 09:40:09 AM PDT 24
Finished Jul 02 09:40:24 AM PDT 24
Peak memory 217780 kb
Host smart-c624e11e-519d-4e96-8340-79e4a75895f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143988791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.4143988791
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.2002463545
Short name T211
Test name
Test status
Simulation time 2355857907 ps
CPU time 9.62 seconds
Started Jul 02 09:40:09 AM PDT 24
Finished Jul 02 09:40:20 AM PDT 24
Peak memory 217264 kb
Host smart-b0f82b0a-93b4-440c-b688-dcdb515478f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002463545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.2002463545
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.3273411206
Short name T409
Test name
Test status
Simulation time 13356864408 ps
CPU time 28.23 seconds
Started Jul 02 09:40:19 AM PDT 24
Finished Jul 02 09:40:51 AM PDT 24
Peak memory 218420 kb
Host smart-ed043e47-13b6-43aa-b4d8-c47b81199aaf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273411206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.3273411206
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.4194153879
Short name T748
Test name
Test status
Simulation time 723137466 ps
CPU time 18.61 seconds
Started Jul 02 09:40:16 AM PDT 24
Finished Jul 02 09:40:38 AM PDT 24
Peak memory 217372 kb
Host smart-2cd669ba-bce9-4231-8752-2b16af05aed7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194153879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.4
194153879
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.1878241764
Short name T444
Test name
Test status
Simulation time 4394438735 ps
CPU time 12.67 seconds
Started Jul 02 09:40:16 AM PDT 24
Finished Jul 02 09:40:31 AM PDT 24
Peak memory 225556 kb
Host smart-126b3ff9-0ba1-4b2d-a184-90b336c9f877
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878241764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.1878241764
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.2728112664
Short name T470
Test name
Test status
Simulation time 188011277 ps
CPU time 3.05 seconds
Started Jul 02 09:40:08 AM PDT 24
Finished Jul 02 09:40:12 AM PDT 24
Peak memory 217144 kb
Host smart-648ec892-a3ee-4447-8287-20d0afb26e13
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728112664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
2728112664
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.3751213765
Short name T642
Test name
Test status
Simulation time 1702023969 ps
CPU time 46.36 seconds
Started Jul 02 09:40:12 AM PDT 24
Finished Jul 02 09:40:59 AM PDT 24
Peak memory 250468 kb
Host smart-1fd4af8b-86d4-4408-be38-bc90f18d8d0f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751213765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.3751213765
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.1974558100
Short name T648
Test name
Test status
Simulation time 429184337 ps
CPU time 13.41 seconds
Started Jul 02 09:40:17 AM PDT 24
Finished Jul 02 09:40:33 AM PDT 24
Peak memory 250464 kb
Host smart-14354497-d894-470e-9d58-c120bddc2172
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974558100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.1974558100
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.613707279
Short name T272
Test name
Test status
Simulation time 197114779 ps
CPU time 2.66 seconds
Started Jul 02 09:40:17 AM PDT 24
Finished Jul 02 09:40:24 AM PDT 24
Peak memory 217768 kb
Host smart-075cf0fd-99cb-4379-b9b2-d79ee62e2d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613707279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.613707279
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.350780682
Short name T415
Test name
Test status
Simulation time 1222661580 ps
CPU time 8.15 seconds
Started Jul 02 09:40:17 AM PDT 24
Finished Jul 02 09:40:28 AM PDT 24
Peak memory 217224 kb
Host smart-4b9a20b9-6401-445b-a110-aad7e0936924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350780682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.350780682
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.519914673
Short name T95
Test name
Test status
Simulation time 421780914 ps
CPU time 38.92 seconds
Started Jul 02 09:40:08 AM PDT 24
Finished Jul 02 09:40:49 AM PDT 24
Peak memory 281988 kb
Host smart-f787b200-9e51-4530-80c5-afdd38650488
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519914673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.519914673
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.1743333862
Short name T818
Test name
Test status
Simulation time 210202295 ps
CPU time 10.79 seconds
Started Jul 02 09:40:16 AM PDT 24
Finished Jul 02 09:40:29 AM PDT 24
Peak memory 218488 kb
Host smart-aeb9d76b-2549-4500-a175-4d8ea61e7054
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743333862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.1743333862
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.565568909
Short name T518
Test name
Test status
Simulation time 460629082 ps
CPU time 10.96 seconds
Started Jul 02 09:40:17 AM PDT 24
Finished Jul 02 09:40:32 AM PDT 24
Peak memory 225520 kb
Host smart-f98e3ef3-55d0-48bf-b214-3d7ff0469232
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565568909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_dig
est.565568909
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.3989343561
Short name T821
Test name
Test status
Simulation time 901097392 ps
CPU time 8.78 seconds
Started Jul 02 09:40:08 AM PDT 24
Finished Jul 02 09:40:17 AM PDT 24
Peak memory 217700 kb
Host smart-63f0a5f9-04cb-4e48-9764-11d2f8770244
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989343561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.3
989343561
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.2391778104
Short name T477
Test name
Test status
Simulation time 923142247 ps
CPU time 7.66 seconds
Started Jul 02 09:40:10 AM PDT 24
Finished Jul 02 09:40:19 AM PDT 24
Peak memory 217840 kb
Host smart-864b71af-0ccb-4114-b595-432267e16a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391778104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.2391778104
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.3189983906
Short name T435
Test name
Test status
Simulation time 80790526 ps
CPU time 1.48 seconds
Started Jul 02 09:40:16 AM PDT 24
Finished Jul 02 09:40:21 AM PDT 24
Peak memory 217184 kb
Host smart-a1d5e2a3-066f-4ef9-ba4c-277ae0178afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189983906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.3189983906
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.854382409
Short name T315
Test name
Test status
Simulation time 1372999014 ps
CPU time 32.14 seconds
Started Jul 02 09:40:17 AM PDT 24
Finished Jul 02 09:40:52 AM PDT 24
Peak memory 250512 kb
Host smart-76b5436b-c0c0-4652-b745-80ec581dfff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854382409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.854382409
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.1399863794
Short name T371
Test name
Test status
Simulation time 49927978 ps
CPU time 6.67 seconds
Started Jul 02 09:40:10 AM PDT 24
Finished Jul 02 09:40:18 AM PDT 24
Peak memory 250220 kb
Host smart-e6cd03bc-5fe2-4430-be89-2962bfed9755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399863794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.1399863794
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.1687976960
Short name T85
Test name
Test status
Simulation time 4204774577 ps
CPU time 76.38 seconds
Started Jul 02 09:40:09 AM PDT 24
Finished Jul 02 09:41:27 AM PDT 24
Peak memory 275544 kb
Host smart-831d2648-57eb-4540-8061-520c9a7a01f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687976960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.1687976960
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.3017277755
Short name T53
Test name
Test status
Simulation time 36313254 ps
CPU time 0.94 seconds
Started Jul 02 09:40:15 AM PDT 24
Finished Jul 02 09:40:17 AM PDT 24
Peak memory 212324 kb
Host smart-760cfe4d-365f-4528-be9f-f9c1b376cbee
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017277755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.3017277755
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.314123524
Short name T635
Test name
Test status
Simulation time 22851857 ps
CPU time 1.25 seconds
Started Jul 02 09:41:41 AM PDT 24
Finished Jul 02 09:41:43 AM PDT 24
Peak memory 208572 kb
Host smart-920fa8d5-6432-472f-a9b9-86330f6cc680
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314123524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.314123524
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.1750170741
Short name T114
Test name
Test status
Simulation time 1266034320 ps
CPU time 14.74 seconds
Started Jul 02 09:41:42 AM PDT 24
Finished Jul 02 09:41:58 AM PDT 24
Peak memory 217756 kb
Host smart-3ef91e27-626a-4c3a-9a27-8b4a57fa5999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750170741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.1750170741
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.1403064261
Short name T403
Test name
Test status
Simulation time 727210817 ps
CPU time 16.49 seconds
Started Jul 02 09:41:38 AM PDT 24
Finished Jul 02 09:41:55 AM PDT 24
Peak memory 217188 kb
Host smart-bed47aa8-cc8e-4868-a582-adecd3e18938
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403064261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.1403064261
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.1693766957
Short name T816
Test name
Test status
Simulation time 29633948 ps
CPU time 1.89 seconds
Started Jul 02 09:41:40 AM PDT 24
Finished Jul 02 09:41:43 AM PDT 24
Peak memory 221760 kb
Host smart-9604a264-9869-4ace-811f-9a0c2b4c81ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693766957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.1693766957
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.578640429
Short name T564
Test name
Test status
Simulation time 971005529 ps
CPU time 12.33 seconds
Started Jul 02 09:41:43 AM PDT 24
Finished Jul 02 09:41:56 AM PDT 24
Peak memory 217684 kb
Host smart-ac7bfc01-1a99-49aa-979d-b69bf4c96aa5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578640429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_di
gest.578640429
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.185271522
Short name T580
Test name
Test status
Simulation time 347312148 ps
CPU time 6.12 seconds
Started Jul 02 09:41:39 AM PDT 24
Finished Jul 02 09:41:46 AM PDT 24
Peak memory 217736 kb
Host smart-39bae9b3-c5d1-48e5-a82c-93fdc390cf04
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185271522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.185271522
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.3491353472
Short name T479
Test name
Test status
Simulation time 280851623 ps
CPU time 11.53 seconds
Started Jul 02 09:41:49 AM PDT 24
Finished Jul 02 09:42:01 AM PDT 24
Peak memory 225560 kb
Host smart-13debc09-39e8-40f4-9b15-462f0f72a63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491353472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.3491353472
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.3693359202
Short name T782
Test name
Test status
Simulation time 50688358 ps
CPU time 2.74 seconds
Started Jul 02 09:41:49 AM PDT 24
Finished Jul 02 09:41:52 AM PDT 24
Peak memory 217104 kb
Host smart-97d9b688-6653-4d98-abbe-2d1e504b0745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693359202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.3693359202
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.487420091
Short name T668
Test name
Test status
Simulation time 820079607 ps
CPU time 20.72 seconds
Started Jul 02 09:41:39 AM PDT 24
Finished Jul 02 09:42:00 AM PDT 24
Peak memory 250532 kb
Host smart-b4f88093-c6a0-482c-86c3-1c5c082f3d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487420091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.487420091
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.3107288262
Short name T576
Test name
Test status
Simulation time 118612690 ps
CPU time 3.42 seconds
Started Jul 02 09:41:40 AM PDT 24
Finished Jul 02 09:41:44 AM PDT 24
Peak memory 221832 kb
Host smart-c5854650-e693-415a-8625-f7726eacc0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107288262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.3107288262
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.302854617
Short name T380
Test name
Test status
Simulation time 22437906000 ps
CPU time 192.62 seconds
Started Jul 02 09:41:48 AM PDT 24
Finished Jul 02 09:45:02 AM PDT 24
Peak memory 270096 kb
Host smart-1ccb93eb-2c77-40bd-b40d-295e347caf78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302854617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.302854617
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.1726406521
Short name T120
Test name
Test status
Simulation time 23460838735 ps
CPU time 144.13 seconds
Started Jul 02 09:41:41 AM PDT 24
Finished Jul 02 09:44:05 AM PDT 24
Peak memory 276108 kb
Host smart-b70744a2-c479-466f-b6b6-cf10dcd925a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1726406521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.1726406521
Directory /workspace/30.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.3863227255
Short name T384
Test name
Test status
Simulation time 55408305 ps
CPU time 0.98 seconds
Started Jul 02 09:41:52 AM PDT 24
Finished Jul 02 09:41:54 AM PDT 24
Peak memory 208672 kb
Host smart-102d8e41-5e1f-46bd-ab34-9f36f10f8f1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863227255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.3863227255
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.3376580539
Short name T578
Test name
Test status
Simulation time 1831339349 ps
CPU time 12.33 seconds
Started Jul 02 09:41:50 AM PDT 24
Finished Jul 02 09:42:03 AM PDT 24
Peak memory 217748 kb
Host smart-aaec0e90-7371-42e6-970a-51afa5732ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376580539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.3376580539
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.3721574040
Short name T464
Test name
Test status
Simulation time 339323922 ps
CPU time 2.86 seconds
Started Jul 02 09:41:50 AM PDT 24
Finished Jul 02 09:41:54 AM PDT 24
Peak memory 217316 kb
Host smart-646e177e-0320-4828-9508-3cf0927e3a87
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721574040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.3721574040
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.931662248
Short name T724
Test name
Test status
Simulation time 157960888 ps
CPU time 2.84 seconds
Started Jul 02 09:41:44 AM PDT 24
Finished Jul 02 09:41:48 AM PDT 24
Peak memory 222148 kb
Host smart-499b7864-4fcb-42ac-a575-868ccb3a0aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931662248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.931662248
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.2743143828
Short name T251
Test name
Test status
Simulation time 303150338 ps
CPU time 11.45 seconds
Started Jul 02 09:41:44 AM PDT 24
Finished Jul 02 09:41:56 AM PDT 24
Peak memory 225532 kb
Host smart-8e5c2e36-24c6-45ec-a5b9-43ee81438bd4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743143828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.2743143828
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.1135177854
Short name T173
Test name
Test status
Simulation time 845244440 ps
CPU time 11.51 seconds
Started Jul 02 09:41:43 AM PDT 24
Finished Jul 02 09:41:55 AM PDT 24
Peak memory 217676 kb
Host smart-666cd228-c88d-4b64-9c1a-2e1efc3c183b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135177854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
1135177854
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.480714411
Short name T813
Test name
Test status
Simulation time 1590257419 ps
CPU time 11.11 seconds
Started Jul 02 09:41:44 AM PDT 24
Finished Jul 02 09:41:56 AM PDT 24
Peak memory 217748 kb
Host smart-1daa769d-d40b-444c-b044-59616c7e1e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480714411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.480714411
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.3682290740
Short name T674
Test name
Test status
Simulation time 99477415 ps
CPU time 2.91 seconds
Started Jul 02 09:41:39 AM PDT 24
Finished Jul 02 09:41:43 AM PDT 24
Peak memory 214204 kb
Host smart-766e2775-0b59-4982-aa08-6fbdac164721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682290740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.3682290740
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.1862758472
Short name T796
Test name
Test status
Simulation time 289865257 ps
CPU time 30.16 seconds
Started Jul 02 09:41:43 AM PDT 24
Finished Jul 02 09:42:14 AM PDT 24
Peak memory 250540 kb
Host smart-5b1d941b-7dd0-4ef1-822a-b5f5fd2ea7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862758472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.1862758472
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.1266607771
Short name T702
Test name
Test status
Simulation time 103228996 ps
CPU time 2.89 seconds
Started Jul 02 09:41:40 AM PDT 24
Finished Jul 02 09:41:44 AM PDT 24
Peak memory 222144 kb
Host smart-7ef28b7c-a5f2-4d75-b6a8-14047886ccb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266607771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.1266607771
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.1803311210
Short name T746
Test name
Test status
Simulation time 60273825292 ps
CPU time 208.62 seconds
Started Jul 02 09:41:48 AM PDT 24
Finished Jul 02 09:45:18 AM PDT 24
Peak memory 225640 kb
Host smart-e9432560-7c45-457e-b346-2ad561faa5cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803311210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.1803311210
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.1883527887
Short name T596
Test name
Test status
Simulation time 141409197562 ps
CPU time 874.76 seconds
Started Jul 02 09:41:50 AM PDT 24
Finished Jul 02 09:56:25 AM PDT 24
Peak memory 306520 kb
Host smart-aea83406-52e2-4517-b4fc-7f2ab85a249e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1883527887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all_with_rand_reset.1883527887
Directory /workspace/31.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.3033241606
Short name T549
Test name
Test status
Simulation time 17193496 ps
CPU time 1.07 seconds
Started Jul 02 09:41:48 AM PDT 24
Finished Jul 02 09:41:50 AM PDT 24
Peak memory 211432 kb
Host smart-ebd3dec8-ff9d-40b9-b2c4-5a9a09e6dfa5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033241606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.3033241606
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.192434688
Short name T600
Test name
Test status
Simulation time 75360646 ps
CPU time 0.99 seconds
Started Jul 02 09:41:52 AM PDT 24
Finished Jul 02 09:41:54 AM PDT 24
Peak memory 208520 kb
Host smart-e95cdad6-7b45-48a3-9ac5-946c25ad94c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192434688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.192434688
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.2655348487
Short name T428
Test name
Test status
Simulation time 3151976390 ps
CPU time 12.64 seconds
Started Jul 02 09:41:50 AM PDT 24
Finished Jul 02 09:42:04 AM PDT 24
Peak memory 217764 kb
Host smart-efb7e959-8397-4671-a1ba-cef473edc8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655348487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.2655348487
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.1560153774
Short name T653
Test name
Test status
Simulation time 1204102711 ps
CPU time 26.39 seconds
Started Jul 02 09:41:50 AM PDT 24
Finished Jul 02 09:42:17 AM PDT 24
Peak memory 217160 kb
Host smart-ad67c8ad-fbb2-4784-92ab-a930a04bd68b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560153774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.1560153774
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.38109366
Short name T237
Test name
Test status
Simulation time 166327631 ps
CPU time 3.96 seconds
Started Jul 02 09:41:51 AM PDT 24
Finished Jul 02 09:41:56 AM PDT 24
Peak memory 217960 kb
Host smart-0558d2cd-9e67-45ad-9140-d7a532865445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38109366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.38109366
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.3595423415
Short name T848
Test name
Test status
Simulation time 230238061 ps
CPU time 7.82 seconds
Started Jul 02 09:41:45 AM PDT 24
Finished Jul 02 09:41:53 AM PDT 24
Peak memory 218432 kb
Host smart-f6a928f7-187d-40d4-91a0-7553655c5bc7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595423415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.3595423415
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.2946820594
Short name T402
Test name
Test status
Simulation time 278585705 ps
CPU time 12.62 seconds
Started Jul 02 09:41:49 AM PDT 24
Finished Jul 02 09:42:02 AM PDT 24
Peak memory 225528 kb
Host smart-6b11203b-1330-4068-9282-8baba1194030
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946820594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.2946820594
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.239641711
Short name T708
Test name
Test status
Simulation time 1680781431 ps
CPU time 10.98 seconds
Started Jul 02 09:41:49 AM PDT 24
Finished Jul 02 09:42:01 AM PDT 24
Peak memory 217736 kb
Host smart-919a10d6-3f92-4c68-8f73-7d55b3a7fde4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239641711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.239641711
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.1413428719
Short name T40
Test name
Test status
Simulation time 325065085 ps
CPU time 8.8 seconds
Started Jul 02 09:41:44 AM PDT 24
Finished Jul 02 09:41:53 AM PDT 24
Peak memory 225568 kb
Host smart-5f3d62bb-1c37-4694-852f-ceffc50a9ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413428719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.1413428719
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.4090216835
Short name T617
Test name
Test status
Simulation time 34525649 ps
CPU time 1.88 seconds
Started Jul 02 09:41:45 AM PDT 24
Finished Jul 02 09:41:48 AM PDT 24
Peak memory 213452 kb
Host smart-561b6001-6f30-42a8-a000-a21800466923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090216835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.4090216835
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.2903229163
Short name T537
Test name
Test status
Simulation time 1373066226 ps
CPU time 27.74 seconds
Started Jul 02 09:41:50 AM PDT 24
Finished Jul 02 09:42:19 AM PDT 24
Peak memory 250608 kb
Host smart-38d213d7-0825-4ebf-bac4-91586fa4e0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903229163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.2903229163
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.1663030018
Short name T203
Test name
Test status
Simulation time 163620079 ps
CPU time 4.01 seconds
Started Jul 02 09:41:44 AM PDT 24
Finished Jul 02 09:41:49 AM PDT 24
Peak memory 221820 kb
Host smart-9a45cc93-a187-4f5c-94e9-d2a68eb4d778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663030018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.1663030018
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.1519878923
Short name T473
Test name
Test status
Simulation time 39182618620 ps
CPU time 162.72 seconds
Started Jul 02 09:41:51 AM PDT 24
Finished Jul 02 09:44:34 AM PDT 24
Peak memory 267160 kb
Host smart-63a3b357-170b-4a85-992a-022d8ea646a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519878923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.1519878923
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.1775610151
Short name T588
Test name
Test status
Simulation time 38301106 ps
CPU time 0.97 seconds
Started Jul 02 09:41:44 AM PDT 24
Finished Jul 02 09:41:45 AM PDT 24
Peak memory 211368 kb
Host smart-df4b5d40-b4e3-403a-bf12-0555c4e5c9c6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775610151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.1775610151
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.4231554856
Short name T239
Test name
Test status
Simulation time 53488959 ps
CPU time 1.05 seconds
Started Jul 02 09:41:51 AM PDT 24
Finished Jul 02 09:41:53 AM PDT 24
Peak memory 208548 kb
Host smart-c0ddaa30-6fbb-40f1-a59d-c23f6aa4cb6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231554856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.4231554856
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.1183131021
Short name T548
Test name
Test status
Simulation time 1898102560 ps
CPU time 15.57 seconds
Started Jul 02 09:41:53 AM PDT 24
Finished Jul 02 09:42:09 AM PDT 24
Peak memory 217776 kb
Host smart-d976617f-0975-4cee-b264-9e1a5c00295c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183131021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.1183131021
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.3340908875
Short name T544
Test name
Test status
Simulation time 51851400 ps
CPU time 1.99 seconds
Started Jul 02 09:41:53 AM PDT 24
Finished Jul 02 09:41:56 AM PDT 24
Peak memory 217188 kb
Host smart-c25696b0-bcd8-4a70-bbe3-882c19814bd3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340908875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.3340908875
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.1519341839
Short name T430
Test name
Test status
Simulation time 162699859 ps
CPU time 2.24 seconds
Started Jul 02 09:41:48 AM PDT 24
Finished Jul 02 09:41:51 AM PDT 24
Peak memory 217684 kb
Host smart-e3ce514b-acc2-4db5-9e9d-f82b5df5c1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519341839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.1519341839
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.2104570026
Short name T38
Test name
Test status
Simulation time 330458499 ps
CPU time 9.16 seconds
Started Jul 02 09:41:49 AM PDT 24
Finished Jul 02 09:41:59 AM PDT 24
Peak memory 218436 kb
Host smart-21973bd9-dcc7-4188-86a6-5f634939b2f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104570026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.2104570026
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.1124810484
Short name T793
Test name
Test status
Simulation time 1620623203 ps
CPU time 9.32 seconds
Started Jul 02 09:41:50 AM PDT 24
Finished Jul 02 09:42:01 AM PDT 24
Peak memory 225512 kb
Host smart-41658937-dcc1-4c56-99ce-f387ae41f855
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124810484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.1124810484
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.2565863294
Short name T804
Test name
Test status
Simulation time 1063005808 ps
CPU time 8.29 seconds
Started Jul 02 09:41:51 AM PDT 24
Finished Jul 02 09:42:00 AM PDT 24
Peak memory 217744 kb
Host smart-7081d03b-5b8f-4e5d-bd3d-0fbb1bb20509
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565863294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
2565863294
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.1646414930
Short name T612
Test name
Test status
Simulation time 355870234 ps
CPU time 9.68 seconds
Started Jul 02 09:41:49 AM PDT 24
Finished Jul 02 09:41:59 AM PDT 24
Peak memory 225604 kb
Host smart-14753be0-6e7c-4494-8af9-c5d891e5b165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646414930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.1646414930
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.3708327964
Short name T686
Test name
Test status
Simulation time 167833966 ps
CPU time 5.28 seconds
Started Jul 02 09:41:50 AM PDT 24
Finished Jul 02 09:41:56 AM PDT 24
Peak memory 217172 kb
Host smart-801bb3e4-c64a-47d5-a4bc-1a197a45d781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708327964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.3708327964
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.988753418
Short name T307
Test name
Test status
Simulation time 467844845 ps
CPU time 21.12 seconds
Started Jul 02 09:41:48 AM PDT 24
Finished Jul 02 09:42:10 AM PDT 24
Peak memory 244572 kb
Host smart-94fba229-6e38-475d-b873-1d89a7b09188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988753418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.988753418
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.1483130652
Short name T725
Test name
Test status
Simulation time 353885052 ps
CPU time 6.62 seconds
Started Jul 02 09:41:48 AM PDT 24
Finished Jul 02 09:41:55 AM PDT 24
Peak memory 250008 kb
Host smart-a6e67e89-8ec4-4169-bb00-2ba2b3a4aa79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483130652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.1483130652
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.1135422991
Short name T482
Test name
Test status
Simulation time 3339319621 ps
CPU time 112.74 seconds
Started Jul 02 09:41:51 AM PDT 24
Finished Jul 02 09:43:45 AM PDT 24
Peak memory 270680 kb
Host smart-ae065ab2-96d6-4fd1-8a26-b76ab07e79fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1135422991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.1135422991
Directory /workspace/33.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.610421302
Short name T74
Test name
Test status
Simulation time 44439714 ps
CPU time 0.94 seconds
Started Jul 02 09:41:48 AM PDT 24
Finished Jul 02 09:41:50 AM PDT 24
Peak memory 211432 kb
Host smart-999ffa35-a92b-4de7-8945-1d21b122059d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610421302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ct
rl_volatile_unlock_smoke.610421302
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.2534400081
Short name T2
Test name
Test status
Simulation time 13021920 ps
CPU time 1 seconds
Started Jul 02 09:41:54 AM PDT 24
Finished Jul 02 09:41:55 AM PDT 24
Peak memory 208608 kb
Host smart-cc04a517-92ee-4f06-b756-cee5e33735d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534400081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.2534400081
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.1993648058
Short name T751
Test name
Test status
Simulation time 229894444 ps
CPU time 10.1 seconds
Started Jul 02 09:41:53 AM PDT 24
Finished Jul 02 09:42:04 AM PDT 24
Peak memory 217788 kb
Host smart-1b9bee40-d06d-43d3-acba-fa47f97cd927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993648058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.1993648058
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.758113407
Short name T420
Test name
Test status
Simulation time 1885838967 ps
CPU time 4.48 seconds
Started Jul 02 09:41:52 AM PDT 24
Finished Jul 02 09:41:58 AM PDT 24
Peak memory 217196 kb
Host smart-50831b13-5811-4b3d-8c59-aaa41e5e2f64
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758113407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.758113407
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.3331592687
Short name T308
Test name
Test status
Simulation time 218308323 ps
CPU time 2.17 seconds
Started Jul 02 09:41:55 AM PDT 24
Finished Jul 02 09:41:58 AM PDT 24
Peak memory 217800 kb
Host smart-8991eff0-64b7-40e3-ad6d-d15f1e5cb0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331592687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.3331592687
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.2354209526
Short name T553
Test name
Test status
Simulation time 942627222 ps
CPU time 19.5 seconds
Started Jul 02 09:42:00 AM PDT 24
Finished Jul 02 09:42:21 AM PDT 24
Peak memory 225576 kb
Host smart-b2d31fe4-e7b0-4e7a-a84e-38b10521c967
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354209526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.2354209526
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.137156818
Short name T436
Test name
Test status
Simulation time 208877207 ps
CPU time 9.75 seconds
Started Jul 02 09:41:51 AM PDT 24
Finished Jul 02 09:42:01 AM PDT 24
Peak memory 225496 kb
Host smart-b7314cc4-a182-4747-86c1-bdcb8be7a73d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137156818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_di
gest.137156818
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.3166437547
Short name T335
Test name
Test status
Simulation time 244795987 ps
CPU time 10.23 seconds
Started Jul 02 09:41:52 AM PDT 24
Finished Jul 02 09:42:03 AM PDT 24
Peak memory 217748 kb
Host smart-c8e5eb7e-7c3d-4f9c-9681-4691681ac0bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166437547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
3166437547
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.3496993473
Short name T786
Test name
Test status
Simulation time 819273932 ps
CPU time 11.15 seconds
Started Jul 02 09:42:00 AM PDT 24
Finished Jul 02 09:42:12 AM PDT 24
Peak memory 225572 kb
Host smart-62007e68-8220-4915-9cbf-fc3072a09c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496993473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.3496993473
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.3956054718
Short name T773
Test name
Test status
Simulation time 19124913 ps
CPU time 1.67 seconds
Started Jul 02 09:41:52 AM PDT 24
Finished Jul 02 09:41:55 AM PDT 24
Peak memory 213332 kb
Host smart-af4909f0-720a-4850-bd4e-3cc5396a4f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956054718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.3956054718
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.4285055965
Short name T102
Test name
Test status
Simulation time 168206267 ps
CPU time 23.42 seconds
Started Jul 02 09:41:55 AM PDT 24
Finished Jul 02 09:42:19 AM PDT 24
Peak memory 250552 kb
Host smart-520e6529-aafe-4937-8f10-918fc6bc40ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285055965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.4285055965
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.2871682599
Short name T338
Test name
Test status
Simulation time 80606804 ps
CPU time 7.31 seconds
Started Jul 02 09:41:50 AM PDT 24
Finished Jul 02 09:41:58 AM PDT 24
Peak memory 246432 kb
Host smart-7b1d5529-e9e1-4b22-b4d4-509082d5f5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871682599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.2871682599
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.1161358715
Short name T680
Test name
Test status
Simulation time 1581797568 ps
CPU time 40.35 seconds
Started Jul 02 09:41:53 AM PDT 24
Finished Jul 02 09:42:34 AM PDT 24
Peak memory 250512 kb
Host smart-c5cb35cf-0939-450e-802a-8c80e7f73ece
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161358715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.1161358715
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1479218520
Short name T458
Test name
Test status
Simulation time 12463299 ps
CPU time 1.09 seconds
Started Jul 02 09:41:53 AM PDT 24
Finished Jul 02 09:41:55 AM PDT 24
Peak memory 211460 kb
Host smart-6040792b-45c6-449e-a19d-9ef17e716203
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479218520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.1479218520
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.3026748388
Short name T585
Test name
Test status
Simulation time 28953310 ps
CPU time 1.39 seconds
Started Jul 02 09:41:53 AM PDT 24
Finished Jul 02 09:41:55 AM PDT 24
Peak memory 208544 kb
Host smart-9b5d109b-e91b-4682-83d9-175c170d9be1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026748388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.3026748388
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.1391851590
Short name T543
Test name
Test status
Simulation time 438577499 ps
CPU time 17.95 seconds
Started Jul 02 09:41:50 AM PDT 24
Finished Jul 02 09:42:09 AM PDT 24
Peak memory 217748 kb
Host smart-1f02fb4f-b48d-40a9-8e1b-34b9d38bc566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391851590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.1391851590
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.1633337396
Short name T734
Test name
Test status
Simulation time 821545199 ps
CPU time 5.17 seconds
Started Jul 02 09:42:00 AM PDT 24
Finished Jul 02 09:42:07 AM PDT 24
Peak memory 217192 kb
Host smart-ba10fb98-d026-41a0-82e2-42e6da69d3b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633337396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.1633337396
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.894028059
Short name T429
Test name
Test status
Simulation time 91277917 ps
CPU time 2.17 seconds
Started Jul 02 09:41:56 AM PDT 24
Finished Jul 02 09:41:59 AM PDT 24
Peak memory 217796 kb
Host smart-b0e075b6-82a7-49f9-a4c0-396dcacd1c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894028059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.894028059
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.439811526
Short name T70
Test name
Test status
Simulation time 1258337082 ps
CPU time 11.47 seconds
Started Jul 02 09:41:50 AM PDT 24
Finished Jul 02 09:42:02 AM PDT 24
Peak memory 225580 kb
Host smart-cd4a027e-d5e2-4c9e-8232-f54093377253
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439811526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.439811526
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.3489425481
Short name T311
Test name
Test status
Simulation time 178548397 ps
CPU time 8.75 seconds
Started Jul 02 09:41:53 AM PDT 24
Finished Jul 02 09:42:02 AM PDT 24
Peak memory 225500 kb
Host smart-fc617437-f8ca-45d0-ab26-eef693753318
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489425481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.3489425481
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.3396025721
Short name T472
Test name
Test status
Simulation time 1162149630 ps
CPU time 7.19 seconds
Started Jul 02 09:41:55 AM PDT 24
Finished Jul 02 09:42:03 AM PDT 24
Peak memory 224512 kb
Host smart-d63fc2c1-cac4-46b6-9767-804976e052e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396025721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
3396025721
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.277484277
Short name T514
Test name
Test status
Simulation time 493385892 ps
CPU time 8.64 seconds
Started Jul 02 09:41:51 AM PDT 24
Finished Jul 02 09:42:01 AM PDT 24
Peak memory 224672 kb
Host smart-e49dcf9b-5f97-4625-9ff9-4b8b7fdfd9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277484277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.277484277
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.278203065
Short name T593
Test name
Test status
Simulation time 139404438 ps
CPU time 7.71 seconds
Started Jul 02 09:41:51 AM PDT 24
Finished Jul 02 09:42:00 AM PDT 24
Peak memory 217228 kb
Host smart-9963ff0e-baa3-45a8-b687-92cb9dbe3f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278203065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.278203065
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.2600321450
Short name T113
Test name
Test status
Simulation time 2052226425 ps
CPU time 27.35 seconds
Started Jul 02 09:41:52 AM PDT 24
Finished Jul 02 09:42:20 AM PDT 24
Peak memory 250540 kb
Host smart-ac482bdc-2b25-48ed-b04b-8fff4ddc1134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600321450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.2600321450
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.759757487
Short name T471
Test name
Test status
Simulation time 81193020 ps
CPU time 3.38 seconds
Started Jul 02 09:42:00 AM PDT 24
Finished Jul 02 09:42:05 AM PDT 24
Peak memory 221772 kb
Host smart-4e216fe1-e5d2-4562-8ec2-423c4b974f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759757487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.759757487
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.2679960772
Short name T507
Test name
Test status
Simulation time 6905766670 ps
CPU time 140 seconds
Started Jul 02 09:41:52 AM PDT 24
Finished Jul 02 09:44:12 AM PDT 24
Peak memory 280304 kb
Host smart-41ce31de-5c99-4805-bbf5-b7652c727ca2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679960772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.2679960772
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.3017785606
Short name T552
Test name
Test status
Simulation time 13743758 ps
CPU time 0.9 seconds
Started Jul 02 09:41:51 AM PDT 24
Finished Jul 02 09:41:53 AM PDT 24
Peak memory 208480 kb
Host smart-3516fce4-ef1d-4cb8-934e-0ceed3a8e665
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017785606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.3017785606
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.3736264908
Short name T839
Test name
Test status
Simulation time 20382260 ps
CPU time 0.9 seconds
Started Jul 02 09:41:59 AM PDT 24
Finished Jul 02 09:42:00 AM PDT 24
Peak memory 208528 kb
Host smart-9bcfa15d-fcc2-4897-9d06-a4c92de9fdd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736264908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.3736264908
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.1797587019
Short name T594
Test name
Test status
Simulation time 1755496021 ps
CPU time 19.76 seconds
Started Jul 02 09:41:58 AM PDT 24
Finished Jul 02 09:42:18 AM PDT 24
Peak memory 217804 kb
Host smart-51aa4a76-2545-4537-bb63-023ce6eee604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797587019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.1797587019
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.1009771475
Short name T761
Test name
Test status
Simulation time 778741959 ps
CPU time 11.63 seconds
Started Jul 02 09:41:56 AM PDT 24
Finished Jul 02 09:42:09 AM PDT 24
Peak memory 217072 kb
Host smart-a8cd8e62-754c-4254-9a39-628c20e00340
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009771475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.1009771475
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.3455661512
Short name T498
Test name
Test status
Simulation time 107286054 ps
CPU time 3.43 seconds
Started Jul 02 09:41:57 AM PDT 24
Finished Jul 02 09:42:01 AM PDT 24
Peak memory 217788 kb
Host smart-36c4dbd2-7f70-4f2c-8799-87be68dd44bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455661512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.3455661512
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.185499873
Short name T651
Test name
Test status
Simulation time 5879934529 ps
CPU time 10.16 seconds
Started Jul 02 09:41:58 AM PDT 24
Finished Jul 02 09:42:08 AM PDT 24
Peak memory 219020 kb
Host smart-16227b38-b319-42e6-84da-38e4b61aada7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185499873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.185499873
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.2388931798
Short name T204
Test name
Test status
Simulation time 4236472825 ps
CPU time 11.73 seconds
Started Jul 02 09:41:56 AM PDT 24
Finished Jul 02 09:42:09 AM PDT 24
Peak memory 225588 kb
Host smart-8d7904a2-cd54-4c54-86f4-bb476cc192b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388931798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.2388931798
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.2270605832
Short name T622
Test name
Test status
Simulation time 752920169 ps
CPU time 21.52 seconds
Started Jul 02 09:42:01 AM PDT 24
Finished Jul 02 09:42:23 AM PDT 24
Peak memory 225416 kb
Host smart-ff2c81ba-f173-4f36-8c11-d9e5b6a7a26c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270605832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
2270605832
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.1870618072
Short name T735
Test name
Test status
Simulation time 428796948 ps
CPU time 6.57 seconds
Started Jul 02 09:41:57 AM PDT 24
Finished Jul 02 09:42:04 AM PDT 24
Peak memory 225520 kb
Host smart-697310cb-02ef-415f-a7df-70ee62e1702b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870618072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.1870618072
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.690168874
Short name T108
Test name
Test status
Simulation time 23399024 ps
CPU time 1.66 seconds
Started Jul 02 09:41:51 AM PDT 24
Finished Jul 02 09:41:53 AM PDT 24
Peak memory 213316 kb
Host smart-47437d59-7687-4c6f-8d3a-0d16a58cf202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690168874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.690168874
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.550425267
Short name T628
Test name
Test status
Simulation time 254005214 ps
CPU time 27.14 seconds
Started Jul 02 09:41:58 AM PDT 24
Finished Jul 02 09:42:25 AM PDT 24
Peak memory 250496 kb
Host smart-19b8b2bb-c318-43af-a296-c045015b8e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550425267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.550425267
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.3289142317
Short name T263
Test name
Test status
Simulation time 114447630 ps
CPU time 3.52 seconds
Started Jul 02 09:41:55 AM PDT 24
Finished Jul 02 09:41:59 AM PDT 24
Peak memory 223616 kb
Host smart-6c3d5b6f-dc55-4e78-84bf-5a6d20a9c587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289142317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.3289142317
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.2428452697
Short name T697
Test name
Test status
Simulation time 16776135873 ps
CPU time 397.2 seconds
Started Jul 02 09:41:55 AM PDT 24
Finished Jul 02 09:48:33 AM PDT 24
Peak memory 279204 kb
Host smart-4fa8a9eb-6b94-4e50-8453-c95fc7cbe8e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2428452697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.2428452697
Directory /workspace/36.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.3004675212
Short name T589
Test name
Test status
Simulation time 28992226 ps
CPU time 0.93 seconds
Started Jul 02 09:41:54 AM PDT 24
Finished Jul 02 09:41:56 AM PDT 24
Peak memory 211384 kb
Host smart-8a2fc30d-cd07-4ffe-80e2-f7b89abccc91
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004675212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.3004675212
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.2139519819
Short name T270
Test name
Test status
Simulation time 47225208 ps
CPU time 1.07 seconds
Started Jul 02 09:42:04 AM PDT 24
Finished Jul 02 09:42:06 AM PDT 24
Peak memory 208436 kb
Host smart-5cbb4247-2855-49b2-b947-a3f53e9e1635
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139519819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.2139519819
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.2623073520
Short name T341
Test name
Test status
Simulation time 1943982490 ps
CPU time 17.98 seconds
Started Jul 02 09:42:00 AM PDT 24
Finished Jul 02 09:42:18 AM PDT 24
Peak memory 217728 kb
Host smart-8b8b0683-f000-46df-8ed8-d711871d5784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623073520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.2623073520
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.2818967734
Short name T592
Test name
Test status
Simulation time 3363300591 ps
CPU time 8.15 seconds
Started Jul 02 09:42:03 AM PDT 24
Finished Jul 02 09:42:12 AM PDT 24
Peak memory 217252 kb
Host smart-7ecc647a-10e7-42d6-9a72-464b4081b2b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818967734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.2818967734
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.2103100458
Short name T493
Test name
Test status
Simulation time 42641692 ps
CPU time 1.74 seconds
Started Jul 02 09:42:00 AM PDT 24
Finished Jul 02 09:42:02 AM PDT 24
Peak memory 217760 kb
Host smart-aec505f1-daa1-4e67-9fae-b3037ffeb9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103100458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.2103100458
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.2344254973
Short name T187
Test name
Test status
Simulation time 406087057 ps
CPU time 17.58 seconds
Started Jul 02 09:42:02 AM PDT 24
Finished Jul 02 09:42:20 AM PDT 24
Peak memory 219448 kb
Host smart-b6b15b4f-0b48-4ce6-aa47-b4ca1191a88d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344254973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.2344254973
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.385004609
Short name T625
Test name
Test status
Simulation time 400876862 ps
CPU time 15.25 seconds
Started Jul 02 09:42:01 AM PDT 24
Finished Jul 02 09:42:17 AM PDT 24
Peak memory 225512 kb
Host smart-b6c8d1bb-51c4-4418-8657-48436a9f3332
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385004609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_di
gest.385004609
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.676895714
Short name T104
Test name
Test status
Simulation time 9934147146 ps
CPU time 15.1 seconds
Started Jul 02 09:42:04 AM PDT 24
Finished Jul 02 09:42:20 AM PDT 24
Peak memory 217740 kb
Host smart-e0ae3a8d-0dde-4bb0-8c9f-a1f3f83e1a03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676895714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.676895714
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.892494420
Short name T623
Test name
Test status
Simulation time 1246173036 ps
CPU time 9.3 seconds
Started Jul 02 09:42:05 AM PDT 24
Finished Jul 02 09:42:16 AM PDT 24
Peak memory 225584 kb
Host smart-dc5262d7-f478-4402-b4f4-ad3527b4d804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892494420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.892494420
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.1375263376
Short name T437
Test name
Test status
Simulation time 51951140 ps
CPU time 2.3 seconds
Started Jul 02 09:41:55 AM PDT 24
Finished Jul 02 09:41:59 AM PDT 24
Peak memory 217212 kb
Host smart-16d69ebb-a410-4c6a-abe3-d63c38ea135e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375263376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.1375263376
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.3238701413
Short name T826
Test name
Test status
Simulation time 230254538 ps
CPU time 21.67 seconds
Started Jul 02 09:42:01 AM PDT 24
Finished Jul 02 09:42:23 AM PDT 24
Peak memory 250516 kb
Host smart-e6c7e7c1-e954-4bdd-9809-74b1d3a4cd7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238701413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.3238701413
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.1935486872
Short name T618
Test name
Test status
Simulation time 128403163 ps
CPU time 7.84 seconds
Started Jul 02 09:42:00 AM PDT 24
Finished Jul 02 09:42:08 AM PDT 24
Peak memory 250548 kb
Host smart-f2e6f27b-3163-4097-9583-db13dcddfe28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935486872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.1935486872
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.2915462690
Short name T183
Test name
Test status
Simulation time 4941426958 ps
CPU time 22.36 seconds
Started Jul 02 09:42:01 AM PDT 24
Finished Jul 02 09:42:24 AM PDT 24
Peak memory 249000 kb
Host smart-37271b32-1f8d-43d5-a914-a66765e0393e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915462690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.2915462690
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.2095402854
Short name T599
Test name
Test status
Simulation time 27878033690 ps
CPU time 391.08 seconds
Started Jul 02 09:42:02 AM PDT 24
Finished Jul 02 09:48:34 AM PDT 24
Peak memory 299436 kb
Host smart-f6332d60-5b92-4889-ac71-a3c59cc71198
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2095402854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.2095402854
Directory /workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.208872032
Short name T54
Test name
Test status
Simulation time 15364601 ps
CPU time 0.83 seconds
Started Jul 02 09:41:56 AM PDT 24
Finished Jul 02 09:41:57 AM PDT 24
Peak memory 208392 kb
Host smart-742df52e-5723-4116-ad26-be63889fcbfe
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208872032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ct
rl_volatile_unlock_smoke.208872032
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.188691773
Short name T843
Test name
Test status
Simulation time 22497763 ps
CPU time 0.93 seconds
Started Jul 02 09:42:02 AM PDT 24
Finished Jul 02 09:42:04 AM PDT 24
Peak memory 208440 kb
Host smart-b05a3835-ddf9-4ec5-a867-099d3fe5edad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188691773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.188691773
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.2315983297
Short name T713
Test name
Test status
Simulation time 2448355690 ps
CPU time 14.93 seconds
Started Jul 02 09:42:04 AM PDT 24
Finished Jul 02 09:42:20 AM PDT 24
Peak memory 218500 kb
Host smart-331e4b72-8b76-40d6-b7d4-237f5026a67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315983297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.2315983297
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.627664816
Short name T378
Test name
Test status
Simulation time 3304716301 ps
CPU time 8.42 seconds
Started Jul 02 09:42:02 AM PDT 24
Finished Jul 02 09:42:12 AM PDT 24
Peak memory 217216 kb
Host smart-77b6f068-e12e-4b20-99b7-c62acc286900
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627664816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.627664816
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.2780064558
Short name T819
Test name
Test status
Simulation time 186801822 ps
CPU time 2.12 seconds
Started Jul 02 09:42:02 AM PDT 24
Finished Jul 02 09:42:05 AM PDT 24
Peak memory 217828 kb
Host smart-8981aee0-64bd-4d97-a1ef-b14c857b76ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780064558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.2780064558
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.2393891157
Short name T57
Test name
Test status
Simulation time 1155995099 ps
CPU time 15.44 seconds
Started Jul 02 09:42:04 AM PDT 24
Finished Jul 02 09:42:21 AM PDT 24
Peak memory 219504 kb
Host smart-9a41632a-93e5-4b28-96aa-be53bb2b8953
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393891157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.2393891157
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.2794564967
Short name T530
Test name
Test status
Simulation time 286088719 ps
CPU time 11.42 seconds
Started Jul 02 09:42:01 AM PDT 24
Finished Jul 02 09:42:13 AM PDT 24
Peak memory 217744 kb
Host smart-3db4d3ba-1027-4759-acf6-15021a2ee245
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794564967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.2794564967
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.484375217
Short name T754
Test name
Test status
Simulation time 332770291 ps
CPU time 9.7 seconds
Started Jul 02 09:42:04 AM PDT 24
Finished Jul 02 09:42:14 AM PDT 24
Peak memory 217668 kb
Host smart-94c3d06c-47b6-412a-b980-b6ad3acaf266
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484375217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.484375217
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.431718215
Short name T820
Test name
Test status
Simulation time 675212367 ps
CPU time 15.31 seconds
Started Jul 02 09:42:02 AM PDT 24
Finished Jul 02 09:42:17 AM PDT 24
Peak memory 225424 kb
Host smart-a53fbe7f-6ef1-4784-a7fa-c8547e39474a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431718215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.431718215
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.109160167
Short name T422
Test name
Test status
Simulation time 283275139 ps
CPU time 4.26 seconds
Started Jul 02 09:42:03 AM PDT 24
Finished Jul 02 09:42:08 AM PDT 24
Peak memory 217212 kb
Host smart-92c1cc53-be53-4824-be0f-78683c3b2b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109160167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.109160167
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.4076061601
Short name T98
Test name
Test status
Simulation time 3020830435 ps
CPU time 32.92 seconds
Started Jul 02 09:42:05 AM PDT 24
Finished Jul 02 09:42:39 AM PDT 24
Peak memory 250604 kb
Host smart-afa86ebb-2e50-4930-947f-fe8235787796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076061601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.4076061601
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.3984803520
Short name T317
Test name
Test status
Simulation time 70235137 ps
CPU time 7.19 seconds
Started Jul 02 09:42:03 AM PDT 24
Finished Jul 02 09:42:11 AM PDT 24
Peak memory 250444 kb
Host smart-5ed98dd0-36b6-48a1-8b5d-94e48f0ade0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984803520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.3984803520
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.2877138998
Short name T720
Test name
Test status
Simulation time 21059617957 ps
CPU time 206.39 seconds
Started Jul 02 09:42:03 AM PDT 24
Finished Jul 02 09:45:30 AM PDT 24
Peak memory 314160 kb
Host smart-e77f4efc-5f82-48e7-81eb-8be4f098ea1a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877138998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.2877138998
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.2060471289
Short name T731
Test name
Test status
Simulation time 14622440 ps
CPU time 0.8 seconds
Started Jul 02 09:42:02 AM PDT 24
Finished Jul 02 09:42:04 AM PDT 24
Peak memory 208356 kb
Host smart-9f179493-f8ab-4a82-b362-2ea6ba200cb9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060471289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.2060471289
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.3654871352
Short name T567
Test name
Test status
Simulation time 19664030 ps
CPU time 1.16 seconds
Started Jul 02 09:42:06 AM PDT 24
Finished Jul 02 09:42:08 AM PDT 24
Peak memory 208616 kb
Host smart-66acba23-8ccb-46f2-aa64-c892397f8562
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654871352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.3654871352
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.1649995518
Short name T431
Test name
Test status
Simulation time 2602761782 ps
CPU time 14.39 seconds
Started Jul 02 09:42:04 AM PDT 24
Finished Jul 02 09:42:19 AM PDT 24
Peak memory 217816 kb
Host smart-b480ce9e-d45b-441b-857f-db1c08bb3d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649995518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.1649995518
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.3349959634
Short name T32
Test name
Test status
Simulation time 868301615 ps
CPU time 6.69 seconds
Started Jul 02 09:42:02 AM PDT 24
Finished Jul 02 09:42:10 AM PDT 24
Peak memory 217172 kb
Host smart-01d7d4d6-ae80-43d8-abf9-e71117466722
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349959634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.3349959634
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.3336289736
Short name T687
Test name
Test status
Simulation time 61417554 ps
CPU time 3.03 seconds
Started Jul 02 09:42:02 AM PDT 24
Finished Jul 02 09:42:05 AM PDT 24
Peak memory 217772 kb
Host smart-38714498-2336-48a4-8f5a-019211f4a9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336289736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.3336289736
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.1188376301
Short name T299
Test name
Test status
Simulation time 1559835209 ps
CPU time 11.27 seconds
Started Jul 02 09:42:04 AM PDT 24
Finished Jul 02 09:42:16 AM PDT 24
Peak memory 218420 kb
Host smart-1d895b50-637b-43e7-826a-260c434fbb1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188376301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.1188376301
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.205693912
Short name T831
Test name
Test status
Simulation time 428180564 ps
CPU time 8.01 seconds
Started Jul 02 09:42:14 AM PDT 24
Finished Jul 02 09:42:23 AM PDT 24
Peak memory 225500 kb
Host smart-24c9b7cd-2bb2-49dd-bd53-c9a67488672c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205693912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_di
gest.205693912
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.2375672247
Short name T184
Test name
Test status
Simulation time 224089389 ps
CPU time 8.12 seconds
Started Jul 02 09:42:01 AM PDT 24
Finished Jul 02 09:42:10 AM PDT 24
Peak memory 224520 kb
Host smart-1f7e6ef9-b30f-4366-8858-e4c50a086027
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375672247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
2375672247
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.1065921015
Short name T535
Test name
Test status
Simulation time 506144076 ps
CPU time 7.74 seconds
Started Jul 02 09:42:05 AM PDT 24
Finished Jul 02 09:42:14 AM PDT 24
Peak memory 225568 kb
Host smart-cecf27ce-46e0-4bbe-ac9a-116f40dee0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065921015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.1065921015
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.2430886915
Short name T361
Test name
Test status
Simulation time 448080962 ps
CPU time 6.96 seconds
Started Jul 02 09:42:04 AM PDT 24
Finished Jul 02 09:42:12 AM PDT 24
Peak memory 217204 kb
Host smart-cb93752b-dce6-4c86-b886-a6a2b82f79eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430886915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.2430886915
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.1477532743
Short name T346
Test name
Test status
Simulation time 753541493 ps
CPU time 20.17 seconds
Started Jul 02 09:42:02 AM PDT 24
Finished Jul 02 09:42:24 AM PDT 24
Peak memory 250520 kb
Host smart-7aaf5729-58d4-413f-8320-05babe883486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477532743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.1477532743
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.3269701354
Short name T426
Test name
Test status
Simulation time 185409219 ps
CPU time 10.73 seconds
Started Jul 02 09:42:03 AM PDT 24
Finished Jul 02 09:42:14 AM PDT 24
Peak memory 250536 kb
Host smart-272c34d7-aee3-4ac5-9bc9-679416d740e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269701354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.3269701354
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.929095403
Short name T597
Test name
Test status
Simulation time 23484440498 ps
CPU time 88.15 seconds
Started Jul 02 09:42:02 AM PDT 24
Finished Jul 02 09:43:32 AM PDT 24
Peak memory 267176 kb
Host smart-090a5279-6108-47c8-bf09-6ab127a609d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929095403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.929095403
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.946833621
Short name T489
Test name
Test status
Simulation time 14624548 ps
CPU time 0.81 seconds
Started Jul 02 09:42:06 AM PDT 24
Finished Jul 02 09:42:08 AM PDT 24
Peak memory 208360 kb
Host smart-8cdef9eb-6351-4ef8-b98b-6598e98fa268
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946833621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ct
rl_volatile_unlock_smoke.946833621
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.1413391616
Short name T175
Test name
Test status
Simulation time 165994372 ps
CPU time 1.1 seconds
Started Jul 02 09:40:16 AM PDT 24
Finished Jul 02 09:40:21 AM PDT 24
Peak memory 208556 kb
Host smart-76e32322-04ed-462d-a781-c980f638b537
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413391616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.1413391616
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.3562652944
Short name T488
Test name
Test status
Simulation time 1876002158 ps
CPU time 12.06 seconds
Started Jul 02 09:40:17 AM PDT 24
Finished Jul 02 09:40:32 AM PDT 24
Peak memory 217776 kb
Host smart-206b8622-6520-4282-a8eb-93ad163848c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562652944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.3562652944
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.1828017145
Short name T716
Test name
Test status
Simulation time 1818736540 ps
CPU time 9.78 seconds
Started Jul 02 09:40:17 AM PDT 24
Finished Jul 02 09:40:30 AM PDT 24
Peak memory 217148 kb
Host smart-e7292c83-8ef6-4ecd-899b-8487a830910a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828017145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.1828017145
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.2764106065
Short name T252
Test name
Test status
Simulation time 1144995271 ps
CPU time 21.42 seconds
Started Jul 02 09:40:18 AM PDT 24
Finished Jul 02 09:40:44 AM PDT 24
Peak memory 217916 kb
Host smart-aa54f5e2-5cf2-4e03-91cf-19536e842a63
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764106065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.2764106065
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.890855546
Short name T696
Test name
Test status
Simulation time 848442861 ps
CPU time 19.47 seconds
Started Jul 02 09:40:18 AM PDT 24
Finished Jul 02 09:40:42 AM PDT 24
Peak memory 217220 kb
Host smart-e52bb734-5b99-4943-a271-7e2a0e541995
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890855546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.890855546
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.2549516572
Short name T480
Test name
Test status
Simulation time 942288838 ps
CPU time 6.44 seconds
Started Jul 02 09:40:21 AM PDT 24
Finished Jul 02 09:40:30 AM PDT 24
Peak memory 217636 kb
Host smart-5a9e9bbf-96e3-40c9-ab9f-d74224270689
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549516572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.2549516572
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.1565526847
Short name T88
Test name
Test status
Simulation time 1996091366 ps
CPU time 17.88 seconds
Started Jul 02 09:40:20 AM PDT 24
Finished Jul 02 09:40:41 AM PDT 24
Peak memory 217108 kb
Host smart-9a7b4a3a-4572-4d38-b457-d2dc5d40aa1c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565526847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.1565526847
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.594698814
Short name T78
Test name
Test status
Simulation time 462059553 ps
CPU time 3.25 seconds
Started Jul 02 09:40:17 AM PDT 24
Finished Jul 02 09:40:23 AM PDT 24
Peak memory 217132 kb
Host smart-2fb4ce66-e85b-4816-898c-fccea64270d1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594698814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.594698814
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.3668911985
Short name T37
Test name
Test status
Simulation time 12900340497 ps
CPU time 57.36 seconds
Started Jul 02 09:40:17 AM PDT 24
Finished Jul 02 09:41:17 AM PDT 24
Peak memory 274632 kb
Host smart-7bfa0f40-4d70-4a5a-80f0-cb38da50dcbb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668911985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.3668911985
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.64736587
Short name T39
Test name
Test status
Simulation time 604056960 ps
CPU time 6.62 seconds
Started Jul 02 09:40:19 AM PDT 24
Finished Jul 02 09:40:30 AM PDT 24
Peak memory 221564 kb
Host smart-520307eb-53f9-47c3-96c7-ff0d478ce19e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64736587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jt
ag_state_post_trans.64736587
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.3896944352
Short name T339
Test name
Test status
Simulation time 158453043 ps
CPU time 3.15 seconds
Started Jul 02 09:40:20 AM PDT 24
Finished Jul 02 09:40:27 AM PDT 24
Peak memory 221912 kb
Host smart-cc43f8d6-5f99-4cc7-b109-3d7cadd0f264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896944352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.3896944352
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.276866254
Short name T673
Test name
Test status
Simulation time 3855910250 ps
CPU time 13.89 seconds
Started Jul 02 09:40:12 AM PDT 24
Finished Jul 02 09:40:27 AM PDT 24
Peak memory 214904 kb
Host smart-7787998b-8c15-4537-b00f-e70a1c93995f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276866254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.276866254
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.1934075953
Short name T94
Test name
Test status
Simulation time 117881019 ps
CPU time 22.24 seconds
Started Jul 02 09:40:12 AM PDT 24
Finished Jul 02 09:40:35 AM PDT 24
Peak memory 267580 kb
Host smart-e46ee21f-cb82-4dbd-b462-7dc120ef7edf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934075953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.1934075953
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.1794997919
Short name T279
Test name
Test status
Simulation time 1209287413 ps
CPU time 14.53 seconds
Started Jul 02 09:40:19 AM PDT 24
Finished Jul 02 09:40:38 AM PDT 24
Peak memory 218428 kb
Host smart-2ae3d5f5-3c26-44d9-8e4c-72d6bc959a65
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794997919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.1794997919
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.1206988116
Short name T454
Test name
Test status
Simulation time 979850881 ps
CPU time 17.86 seconds
Started Jul 02 09:40:16 AM PDT 24
Finished Jul 02 09:40:37 AM PDT 24
Peak memory 225456 kb
Host smart-6c4a0107-dc53-4e8f-a60f-5206cbec13cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206988116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.1206988116
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.2795613053
Short name T787
Test name
Test status
Simulation time 328080975 ps
CPU time 7.97 seconds
Started Jul 02 09:40:13 AM PDT 24
Finished Jul 02 09:40:21 AM PDT 24
Peak memory 217744 kb
Host smart-ea3d7738-7b1c-4d6f-bb7f-fd1afa66619f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795613053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.2
795613053
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.2930405694
Short name T67
Test name
Test status
Simulation time 1150164020 ps
CPU time 9.05 seconds
Started Jul 02 09:40:13 AM PDT 24
Finished Jul 02 09:40:22 AM PDT 24
Peak memory 225640 kb
Host smart-8d1ecd07-bd7d-45e5-a15d-67c7f548b5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930405694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.2930405694
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.3229436151
Short name T583
Test name
Test status
Simulation time 90864173 ps
CPU time 2.07 seconds
Started Jul 02 09:40:14 AM PDT 24
Finished Jul 02 09:40:17 AM PDT 24
Peak memory 213948 kb
Host smart-82e53e32-3b4b-4492-b0e0-399a121228ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229436151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.3229436151
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.941125597
Short name T805
Test name
Test status
Simulation time 297382145 ps
CPU time 30.65 seconds
Started Jul 02 09:40:09 AM PDT 24
Finished Jul 02 09:40:41 AM PDT 24
Peak memory 250536 kb
Host smart-cd312a1b-f269-4abd-87b7-437045865443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941125597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.941125597
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.3709925617
Short name T509
Test name
Test status
Simulation time 77005448 ps
CPU time 6.53 seconds
Started Jul 02 09:40:18 AM PDT 24
Finished Jul 02 09:40:29 AM PDT 24
Peak memory 246704 kb
Host smart-a02531df-a287-47f9-b359-d7c4cc34554a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709925617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.3709925617
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.1085375514
Short name T455
Test name
Test status
Simulation time 1060631358 ps
CPU time 34.37 seconds
Started Jul 02 09:40:18 AM PDT 24
Finished Jul 02 09:40:57 AM PDT 24
Peak memory 247620 kb
Host smart-4b8d8f0c-807f-454b-a2c9-2e6b38e514d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085375514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.1085375514
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.3408974128
Short name T160
Test name
Test status
Simulation time 25642124997 ps
CPU time 416.95 seconds
Started Jul 02 09:40:11 AM PDT 24
Finished Jul 02 09:47:09 AM PDT 24
Peak memory 316152 kb
Host smart-69b097dc-4f9d-47f3-b1b5-71328278ae42
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3408974128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.3408974128
Directory /workspace/4.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.1317179949
Short name T89
Test name
Test status
Simulation time 13838415 ps
CPU time 0.97 seconds
Started Jul 02 09:40:20 AM PDT 24
Finished Jul 02 09:40:24 AM PDT 24
Peak memory 211440 kb
Host smart-71730148-e816-4e27-8ee6-d9e4fb50eb7e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317179949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.1317179949
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.1707954003
Short name T240
Test name
Test status
Simulation time 59703974 ps
CPU time 0.9 seconds
Started Jul 02 09:42:05 AM PDT 24
Finished Jul 02 09:42:06 AM PDT 24
Peak memory 208524 kb
Host smart-80dded3a-f187-4f2e-bdaf-83dc95d35af5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707954003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.1707954003
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.566544676
Short name T678
Test name
Test status
Simulation time 596810851 ps
CPU time 20.48 seconds
Started Jul 02 09:42:04 AM PDT 24
Finished Jul 02 09:42:25 AM PDT 24
Peak memory 217808 kb
Host smart-a1bab0f1-7746-4c3e-97eb-250c305de4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566544676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.566544676
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.1374984433
Short name T342
Test name
Test status
Simulation time 218317871 ps
CPU time 2.24 seconds
Started Jul 02 09:42:06 AM PDT 24
Finished Jul 02 09:42:09 AM PDT 24
Peak memory 217236 kb
Host smart-d540a6c7-681d-4b84-ad7f-21d62966738b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374984433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.1374984433
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.180876063
Short name T742
Test name
Test status
Simulation time 424026170 ps
CPU time 2.8 seconds
Started Jul 02 09:42:06 AM PDT 24
Finished Jul 02 09:42:10 AM PDT 24
Peak memory 221936 kb
Host smart-bce80ec6-e6f9-4305-8b17-d3030b7e8b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180876063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.180876063
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.3060435001
Short name T727
Test name
Test status
Simulation time 6879280627 ps
CPU time 17.81 seconds
Started Jul 02 09:42:06 AM PDT 24
Finished Jul 02 09:42:25 AM PDT 24
Peak memory 225684 kb
Host smart-1caecf1c-bee6-4653-9e21-a0d6112135aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060435001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.3060435001
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.3399308602
Short name T334
Test name
Test status
Simulation time 724592254 ps
CPU time 14.62 seconds
Started Jul 02 09:42:08 AM PDT 24
Finished Jul 02 09:42:23 AM PDT 24
Peak memory 225484 kb
Host smart-2cecb414-f4c2-4f50-b884-0558d72bc506
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399308602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.3399308602
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.1727645927
Short name T749
Test name
Test status
Simulation time 1046617416 ps
CPU time 8.94 seconds
Started Jul 02 09:42:06 AM PDT 24
Finished Jul 02 09:42:16 AM PDT 24
Peak memory 225308 kb
Host smart-06d5d5c2-ca69-4e18-b659-e32e00f25191
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727645927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
1727645927
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.1510255880
Short name T560
Test name
Test status
Simulation time 369694785 ps
CPU time 13.89 seconds
Started Jul 02 09:42:05 AM PDT 24
Finished Jul 02 09:42:20 AM PDT 24
Peak memory 225576 kb
Host smart-9ae40858-5dfb-4492-a15d-168445dca107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510255880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.1510255880
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.1076233969
Short name T387
Test name
Test status
Simulation time 55030190 ps
CPU time 2.7 seconds
Started Jul 02 09:42:02 AM PDT 24
Finished Jul 02 09:42:06 AM PDT 24
Peak memory 217180 kb
Host smart-fce10cc8-cb34-4098-9c2d-cd1a1df352d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076233969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.1076233969
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.1448728531
Short name T847
Test name
Test status
Simulation time 1542151908 ps
CPU time 24.1 seconds
Started Jul 02 09:42:06 AM PDT 24
Finished Jul 02 09:42:31 AM PDT 24
Peak memory 250496 kb
Host smart-5692db1d-7443-45ed-89ff-b51b4f6f1580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448728531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.1448728531
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.866835113
Short name T389
Test name
Test status
Simulation time 54442004 ps
CPU time 8.66 seconds
Started Jul 02 09:42:05 AM PDT 24
Finished Jul 02 09:42:14 AM PDT 24
Peak memory 250476 kb
Host smart-8c63a74c-b480-4852-a277-018418da0c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866835113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.866835113
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.148679723
Short name T180
Test name
Test status
Simulation time 4879440661 ps
CPU time 42.09 seconds
Started Jul 02 09:42:05 AM PDT 24
Finished Jul 02 09:42:48 AM PDT 24
Peak memory 250580 kb
Host smart-919e3b30-1d85-4d35-8af2-52b9ec77bcd3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148679723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.148679723
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.3088365303
Short name T358
Test name
Test status
Simulation time 13694446 ps
CPU time 0.76 seconds
Started Jul 02 09:42:05 AM PDT 24
Finished Jul 02 09:42:06 AM PDT 24
Peak memory 208328 kb
Host smart-d4269ece-cc9d-44b2-ae2a-96171e2caa3e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088365303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.3088365303
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.472068496
Short name T777
Test name
Test status
Simulation time 28317944 ps
CPU time 0.87 seconds
Started Jul 02 09:42:05 AM PDT 24
Finished Jul 02 09:42:07 AM PDT 24
Peak memory 208560 kb
Host smart-c421d6b4-f435-4e42-9ac3-559f81528609
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472068496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.472068496
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.3625990127
Short name T407
Test name
Test status
Simulation time 1526573928 ps
CPU time 9.55 seconds
Started Jul 02 09:42:05 AM PDT 24
Finished Jul 02 09:42:16 AM PDT 24
Peak memory 225572 kb
Host smart-94affb01-4dbd-437d-a683-475fc7744918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625990127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.3625990127
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.3598980628
Short name T28
Test name
Test status
Simulation time 605911595 ps
CPU time 4.98 seconds
Started Jul 02 09:42:08 AM PDT 24
Finished Jul 02 09:42:14 AM PDT 24
Peak memory 216728 kb
Host smart-a88e7582-f804-44f5-a66f-38cf22141bbe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598980628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.3598980628
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.595696170
Short name T329
Test name
Test status
Simulation time 48880164 ps
CPU time 2.33 seconds
Started Jul 02 09:42:07 AM PDT 24
Finished Jul 02 09:42:10 AM PDT 24
Peak memory 217784 kb
Host smart-1fe63e5a-b037-43e2-bf76-64b83bfab183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595696170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.595696170
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.2949472189
Short name T48
Test name
Test status
Simulation time 217082601 ps
CPU time 7.71 seconds
Started Jul 02 09:42:21 AM PDT 24
Finished Jul 02 09:42:31 AM PDT 24
Peak memory 217800 kb
Host smart-8e7fcc87-b86a-4c50-a994-cdfdeeb4cf9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949472189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.2949472189
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.45446328
Short name T665
Test name
Test status
Simulation time 295043532 ps
CPU time 8.14 seconds
Started Jul 02 09:42:07 AM PDT 24
Finished Jul 02 09:42:16 AM PDT 24
Peak memory 225496 kb
Host smart-2243d5a5-d038-4982-a6c8-ffac87e11e06
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45446328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_dig
est.45446328
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.1185163378
Short name T63
Test name
Test status
Simulation time 1274101693 ps
CPU time 11.67 seconds
Started Jul 02 09:42:07 AM PDT 24
Finished Jul 02 09:42:20 AM PDT 24
Peak memory 217668 kb
Host smart-ccc334ac-93b1-4510-9b73-856c949dba8c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185163378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
1185163378
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.3590769604
Short name T196
Test name
Test status
Simulation time 2877284028 ps
CPU time 10.89 seconds
Started Jul 02 09:42:06 AM PDT 24
Finished Jul 02 09:42:18 AM PDT 24
Peak memory 225656 kb
Host smart-1f19911e-807b-4865-bb73-9565bbd12227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590769604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.3590769604
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.1093505610
Short name T671
Test name
Test status
Simulation time 947252993 ps
CPU time 12.49 seconds
Started Jul 02 09:42:18 AM PDT 24
Finished Jul 02 09:42:32 AM PDT 24
Peak memory 217208 kb
Host smart-3ed95865-26a9-4606-8da3-6f9a1288bbd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093505610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.1093505610
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.4081231291
Short name T117
Test name
Test status
Simulation time 1632729374 ps
CPU time 28.32 seconds
Started Jul 02 09:42:05 AM PDT 24
Finished Jul 02 09:42:35 AM PDT 24
Peak memory 250476 kb
Host smart-1634e5e6-bf5f-496e-aeca-4df86376d1d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081231291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.4081231291
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.1617764441
Short name T406
Test name
Test status
Simulation time 85364072 ps
CPU time 3.41 seconds
Started Jul 02 09:42:05 AM PDT 24
Finished Jul 02 09:42:09 AM PDT 24
Peak memory 222192 kb
Host smart-d9a4bcdb-46f5-4c39-bbb0-fb5fd540b0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617764441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.1617764441
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.2831684620
Short name T584
Test name
Test status
Simulation time 5667704636 ps
CPU time 29.22 seconds
Started Jul 02 09:42:21 AM PDT 24
Finished Jul 02 09:42:53 AM PDT 24
Peak memory 245480 kb
Host smart-c9a3e4cf-7b0d-46e1-9506-cf51a078d54f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831684620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.2831684620
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.2368280804
Short name T177
Test name
Test status
Simulation time 53051864608 ps
CPU time 332.22 seconds
Started Jul 02 09:42:10 AM PDT 24
Finished Jul 02 09:47:43 AM PDT 24
Peak memory 267116 kb
Host smart-287ace7a-9a4c-4fbf-81f2-714fe84a959a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2368280804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.2368280804
Directory /workspace/41.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.2569745196
Short name T610
Test name
Test status
Simulation time 30640751 ps
CPU time 0.84 seconds
Started Jul 02 09:42:06 AM PDT 24
Finished Jul 02 09:42:08 AM PDT 24
Peak memory 208436 kb
Host smart-dd27dcb1-0341-4e59-b731-69b7cc2de870
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569745196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.2569745196
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.1250655895
Short name T269
Test name
Test status
Simulation time 25862948 ps
CPU time 1.41 seconds
Started Jul 02 09:42:12 AM PDT 24
Finished Jul 02 09:42:15 AM PDT 24
Peak memory 208576 kb
Host smart-4f61bf7b-ffae-4500-b7fe-0fb12280637a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250655895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.1250655895
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.857956926
Short name T198
Test name
Test status
Simulation time 1027307054 ps
CPU time 10.49 seconds
Started Jul 02 09:42:07 AM PDT 24
Finished Jul 02 09:42:18 AM PDT 24
Peak memory 217944 kb
Host smart-57a26404-3f23-441a-8ea5-84085d0c5361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857956926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.857956926
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.3230215555
Short name T632
Test name
Test status
Simulation time 195271441 ps
CPU time 2.76 seconds
Started Jul 02 09:42:21 AM PDT 24
Finished Jul 02 09:42:27 AM PDT 24
Peak memory 217164 kb
Host smart-f899cb60-2fbb-4f34-90f2-f8fd6eb66ab8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230215555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.3230215555
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.3595189813
Short name T546
Test name
Test status
Simulation time 153649547 ps
CPU time 3.03 seconds
Started Jul 02 09:42:18 AM PDT 24
Finished Jul 02 09:42:22 AM PDT 24
Peak memory 221860 kb
Host smart-e95ea886-a440-4b48-8253-8061509879a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595189813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.3595189813
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.203288730
Short name T859
Test name
Test status
Simulation time 328749297 ps
CPU time 14.67 seconds
Started Jul 02 09:42:22 AM PDT 24
Finished Jul 02 09:42:40 AM PDT 24
Peak memory 218452 kb
Host smart-6c4cb7d1-3978-4624-8422-a2d358a1d757
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203288730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.203288730
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.1362038087
Short name T814
Test name
Test status
Simulation time 3134095769 ps
CPU time 11.9 seconds
Started Jul 02 09:42:12 AM PDT 24
Finished Jul 02 09:42:24 AM PDT 24
Peak memory 225584 kb
Host smart-fcf9270c-53f4-4876-b21c-4c62394dbe09
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362038087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.1362038087
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.3991629085
Short name T619
Test name
Test status
Simulation time 276749879 ps
CPU time 7.99 seconds
Started Jul 02 09:42:06 AM PDT 24
Finished Jul 02 09:42:15 AM PDT 24
Peak memory 217204 kb
Host smart-fefac3f0-d787-4855-b662-40edb3d6507c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991629085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.3991629085
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.420325170
Short name T658
Test name
Test status
Simulation time 386471543 ps
CPU time 26.41 seconds
Started Jul 02 09:42:10 AM PDT 24
Finished Jul 02 09:42:37 AM PDT 24
Peak memory 250620 kb
Host smart-6498fb61-3768-48ad-8dca-27895e9c32e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420325170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.420325170
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.1716275773
Short name T453
Test name
Test status
Simulation time 82320620 ps
CPU time 7.37 seconds
Started Jul 02 09:42:15 AM PDT 24
Finished Jul 02 09:42:23 AM PDT 24
Peak memory 250528 kb
Host smart-68a964b4-e0a9-423b-87c3-03b56d47bec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716275773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.1716275773
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.434704344
Short name T312
Test name
Test status
Simulation time 614837457 ps
CPU time 20.76 seconds
Started Jul 02 09:42:21 AM PDT 24
Finished Jul 02 09:42:45 AM PDT 24
Peak memory 248984 kb
Host smart-fab76a49-c8bf-4da1-a1a7-f12d61fb718f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434704344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.434704344
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.3954168126
Short name T119
Test name
Test status
Simulation time 53426382685 ps
CPU time 931.15 seconds
Started Jul 02 09:42:10 AM PDT 24
Finished Jul 02 09:57:42 AM PDT 24
Peak memory 519456 kb
Host smart-62d98e04-ff7e-4739-b370-e0dbeb36a774
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3954168126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.3954168126
Directory /workspace/42.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.2855131118
Short name T82
Test name
Test status
Simulation time 25809141 ps
CPU time 1.03 seconds
Started Jul 02 09:42:12 AM PDT 24
Finished Jul 02 09:42:14 AM PDT 24
Peak memory 208516 kb
Host smart-4bd4bb3a-88ec-409d-9395-a844fd301952
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855131118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.2855131118
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.603647365
Short name T703
Test name
Test status
Simulation time 990330276 ps
CPU time 12.65 seconds
Started Jul 02 09:42:15 AM PDT 24
Finished Jul 02 09:42:29 AM PDT 24
Peak memory 225580 kb
Host smart-497bcf3a-2cfd-4b66-a87e-7c1b61d29b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603647365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.603647365
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.1843583558
Short name T451
Test name
Test status
Simulation time 118682074 ps
CPU time 3.21 seconds
Started Jul 02 09:42:11 AM PDT 24
Finished Jul 02 09:42:15 AM PDT 24
Peak memory 217212 kb
Host smart-dad3c7c0-02f1-4335-a50e-63ef2895db20
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843583558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.1843583558
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.2925072151
Short name T260
Test name
Test status
Simulation time 151860127 ps
CPU time 3.56 seconds
Started Jul 02 09:42:13 AM PDT 24
Finished Jul 02 09:42:17 AM PDT 24
Peak memory 217768 kb
Host smart-b4c9bf19-a75a-46ff-99e4-8c171a136de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925072151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.2925072151
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.3069645595
Short name T643
Test name
Test status
Simulation time 2278035351 ps
CPU time 10.49 seconds
Started Jul 02 09:42:09 AM PDT 24
Finished Jul 02 09:42:20 AM PDT 24
Peak memory 217864 kb
Host smart-713bb334-e0c8-49c2-a030-80f6b116be33
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069645595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.3069645595
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.4097495534
Short name T631
Test name
Test status
Simulation time 478516401 ps
CPU time 9.62 seconds
Started Jul 02 09:42:22 AM PDT 24
Finished Jul 02 09:42:35 AM PDT 24
Peak memory 225532 kb
Host smart-d392f720-3619-44dd-bfb3-f0c0b4a656a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097495534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.4097495534
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.1531738501
Short name T737
Test name
Test status
Simulation time 4994049769 ps
CPU time 11.13 seconds
Started Jul 02 09:42:15 AM PDT 24
Finished Jul 02 09:42:27 AM PDT 24
Peak memory 217800 kb
Host smart-00ddd803-ba99-451c-bf5a-20e9e0fa8b1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531738501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
1531738501
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.2457158727
Short name T590
Test name
Test status
Simulation time 71401577 ps
CPU time 3.65 seconds
Started Jul 02 09:42:09 AM PDT 24
Finished Jul 02 09:42:14 AM PDT 24
Peak memory 214596 kb
Host smart-eec17aaf-ef93-46a7-8bea-c5ff46904eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457158727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.2457158727
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.3850242103
Short name T573
Test name
Test status
Simulation time 1000097250 ps
CPU time 27.08 seconds
Started Jul 02 09:42:10 AM PDT 24
Finished Jul 02 09:42:38 AM PDT 24
Peak memory 250524 kb
Host smart-fc88b774-92dd-45bd-a09c-61b11a088bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850242103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.3850242103
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.3893619493
Short name T545
Test name
Test status
Simulation time 102068454 ps
CPU time 6.55 seconds
Started Jul 02 09:42:08 AM PDT 24
Finished Jul 02 09:42:15 AM PDT 24
Peak memory 246504 kb
Host smart-a3d7a6b3-4173-4eaf-b10d-94dec5360858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893619493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.3893619493
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.2898610947
Short name T59
Test name
Test status
Simulation time 4832334641 ps
CPU time 159.7 seconds
Started Jul 02 09:42:09 AM PDT 24
Finished Jul 02 09:44:50 AM PDT 24
Peak memory 239352 kb
Host smart-e9f683a6-e574-4528-b9ba-c07901ee8722
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898610947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.2898610947
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.2493738094
Short name T324
Test name
Test status
Simulation time 30615547 ps
CPU time 0.85 seconds
Started Jul 02 09:42:14 AM PDT 24
Finished Jul 02 09:42:16 AM PDT 24
Peak memory 208412 kb
Host smart-531fb5fe-cd76-4d75-8a34-64645ce247e6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493738094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.2493738094
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.2718527782
Short name T756
Test name
Test status
Simulation time 87982554 ps
CPU time 1 seconds
Started Jul 02 09:42:12 AM PDT 24
Finished Jul 02 09:42:14 AM PDT 24
Peak memory 208516 kb
Host smart-10e91d71-ae02-44e3-ad36-2a139e33227a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718527782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.2718527782
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.1709614887
Short name T450
Test name
Test status
Simulation time 1161496167 ps
CPU time 18.51 seconds
Started Jul 02 09:42:11 AM PDT 24
Finished Jul 02 09:42:30 AM PDT 24
Peak memory 217768 kb
Host smart-363efc61-bff7-498e-885b-15f830c77f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709614887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.1709614887
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.2357801617
Short name T772
Test name
Test status
Simulation time 733498547 ps
CPU time 2.93 seconds
Started Jul 02 09:42:12 AM PDT 24
Finished Jul 02 09:42:16 AM PDT 24
Peak memory 217192 kb
Host smart-87e50891-f8d6-4c83-a70b-81e59b4daaf6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357801617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.2357801617
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.716897513
Short name T521
Test name
Test status
Simulation time 205325968 ps
CPU time 2.91 seconds
Started Jul 02 09:42:11 AM PDT 24
Finished Jul 02 09:42:14 AM PDT 24
Peak memory 217764 kb
Host smart-271ef3a5-af88-4580-a913-438e24f0f7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716897513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.716897513
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.2084252738
Short name T838
Test name
Test status
Simulation time 784712211 ps
CPU time 15.15 seconds
Started Jul 02 09:42:11 AM PDT 24
Finished Jul 02 09:42:26 AM PDT 24
Peak memory 225484 kb
Host smart-5cb115e5-575a-4e4d-9517-32d3dee8e4bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084252738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.2084252738
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.882344177
Short name T515
Test name
Test status
Simulation time 423941813 ps
CPU time 11.6 seconds
Started Jul 02 09:42:15 AM PDT 24
Finished Jul 02 09:42:28 AM PDT 24
Peak memory 217724 kb
Host smart-05fd1443-aaa7-4955-ad7b-ac35800069b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882344177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.882344177
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.1189350958
Short name T194
Test name
Test status
Simulation time 1045220081 ps
CPU time 10.12 seconds
Started Jul 02 09:42:09 AM PDT 24
Finished Jul 02 09:42:20 AM PDT 24
Peak memory 225652 kb
Host smart-f3ee9778-5fc0-4d53-a0f8-ecebae419b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189350958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.1189350958
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.1187875319
Short name T770
Test name
Test status
Simulation time 284649102 ps
CPU time 6.89 seconds
Started Jul 02 09:42:09 AM PDT 24
Finished Jul 02 09:42:16 AM PDT 24
Peak memory 217184 kb
Host smart-f24b4597-4f51-47f3-a46c-6926f4833e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187875319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.1187875319
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.2019688231
Short name T321
Test name
Test status
Simulation time 207296385 ps
CPU time 22.02 seconds
Started Jul 02 09:42:15 AM PDT 24
Finished Jul 02 09:42:38 AM PDT 24
Peak memory 250504 kb
Host smart-6f8fba0a-a82a-4a8b-ab17-c88b06c06f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019688231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.2019688231
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.4079383844
Short name T446
Test name
Test status
Simulation time 207527777 ps
CPU time 7.72 seconds
Started Jul 02 09:42:13 AM PDT 24
Finished Jul 02 09:42:22 AM PDT 24
Peak memory 250488 kb
Host smart-091179f6-dc54-4ab7-ba82-bbb6827800cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079383844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.4079383844
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.683367510
Short name T598
Test name
Test status
Simulation time 972316595 ps
CPU time 13.48 seconds
Started Jul 02 09:42:21 AM PDT 24
Finished Jul 02 09:42:37 AM PDT 24
Peak memory 250548 kb
Host smart-db14e7b9-0286-4fee-b28d-f483171b77be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683367510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.683367510
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.4143565698
Short name T541
Test name
Test status
Simulation time 15670860 ps
CPU time 0.77 seconds
Started Jul 02 09:42:11 AM PDT 24
Finished Jul 02 09:42:12 AM PDT 24
Peak memory 208404 kb
Host smart-19deecb3-43d6-4678-b660-a0a52c4117b8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143565698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.4143565698
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.1422123823
Short name T457
Test name
Test status
Simulation time 37597336 ps
CPU time 1.19 seconds
Started Jul 02 09:42:11 AM PDT 24
Finished Jul 02 09:42:13 AM PDT 24
Peak memory 208568 kb
Host smart-acbadd5e-cc6d-4dc4-87ff-cef9f5926879
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422123823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.1422123823
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.2518502024
Short name T255
Test name
Test status
Simulation time 3833026160 ps
CPU time 10.61 seconds
Started Jul 02 09:42:16 AM PDT 24
Finished Jul 02 09:42:27 AM PDT 24
Peak memory 217752 kb
Host smart-14614445-0e13-48b5-8c88-e10cb01e231d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518502024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.2518502024
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.2318653794
Short name T9
Test name
Test status
Simulation time 149067553 ps
CPU time 4.12 seconds
Started Jul 02 09:42:12 AM PDT 24
Finished Jul 02 09:42:16 AM PDT 24
Peak memory 217108 kb
Host smart-cf65d4bc-d500-4de4-9a77-ffa0970d174c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318653794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.2318653794
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.2407711879
Short name T822
Test name
Test status
Simulation time 56162709 ps
CPU time 2.07 seconds
Started Jul 02 09:42:12 AM PDT 24
Finished Jul 02 09:42:15 AM PDT 24
Peak memory 217772 kb
Host smart-23d6f557-f243-4987-9e32-2b1bd93b7052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407711879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.2407711879
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.4020211869
Short name T706
Test name
Test status
Simulation time 507778380 ps
CPU time 20.39 seconds
Started Jul 02 09:42:16 AM PDT 24
Finished Jul 02 09:42:37 AM PDT 24
Peak memory 225596 kb
Host smart-8cf4be32-35ec-49a4-828c-ee5c891910ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020211869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.4020211869
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.590695271
Short name T853
Test name
Test status
Simulation time 1645360079 ps
CPU time 15.89 seconds
Started Jul 02 09:42:14 AM PDT 24
Finished Jul 02 09:42:30 AM PDT 24
Peak memory 225524 kb
Host smart-15174466-f555-4669-82ee-b149545fbff6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590695271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_di
gest.590695271
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.1310456362
Short name T555
Test name
Test status
Simulation time 880467718 ps
CPU time 6 seconds
Started Jul 02 09:42:14 AM PDT 24
Finished Jul 02 09:42:21 AM PDT 24
Peak memory 225484 kb
Host smart-84443834-4852-49e8-b943-a6cd8b99fd9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310456362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
1310456362
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.629861925
Short name T808
Test name
Test status
Simulation time 1739557971 ps
CPU time 10.86 seconds
Started Jul 02 09:42:18 AM PDT 24
Finished Jul 02 09:42:30 AM PDT 24
Peak memory 225560 kb
Host smart-826567c0-4a1d-42e5-9086-f8d761ee1e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629861925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.629861925
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.3215102573
Short name T408
Test name
Test status
Simulation time 379546544 ps
CPU time 5.8 seconds
Started Jul 02 09:42:22 AM PDT 24
Finished Jul 02 09:42:31 AM PDT 24
Peak memory 217288 kb
Host smart-90f27d4e-b4af-4d12-a9f1-80150f72ab3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215102573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.3215102573
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.145004148
Short name T694
Test name
Test status
Simulation time 307696384 ps
CPU time 28.82 seconds
Started Jul 02 09:42:17 AM PDT 24
Finished Jul 02 09:42:46 AM PDT 24
Peak memory 250504 kb
Host smart-d564b571-def2-4134-8885-6d889b3558d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145004148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.145004148
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.3829125470
Short name T698
Test name
Test status
Simulation time 278093878 ps
CPU time 4.58 seconds
Started Jul 02 09:42:13 AM PDT 24
Finished Jul 02 09:42:18 AM PDT 24
Peak memory 222612 kb
Host smart-68302d9e-4125-4066-b977-8bd1a093f85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829125470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.3829125470
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.4180680679
Short name T681
Test name
Test status
Simulation time 14164440579 ps
CPU time 135.03 seconds
Started Jul 02 09:42:13 AM PDT 24
Finished Jul 02 09:44:29 AM PDT 24
Peak memory 221288 kb
Host smart-851b6206-8e2c-4351-8b4c-3be1f44a30d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180680679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.4180680679
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.3018812540
Short name T636
Test name
Test status
Simulation time 47501072 ps
CPU time 1.04 seconds
Started Jul 02 09:42:10 AM PDT 24
Finished Jul 02 09:42:12 AM PDT 24
Peak memory 211444 kb
Host smart-d254d09f-3c3c-43de-9778-48140dfe67d3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018812540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.3018812540
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.201340070
Short name T343
Test name
Test status
Simulation time 57642898 ps
CPU time 0.87 seconds
Started Jul 02 09:42:17 AM PDT 24
Finished Jul 02 09:42:18 AM PDT 24
Peak memory 208496 kb
Host smart-7e619b9a-591e-4c6e-8707-35f725ee0595
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201340070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.201340070
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.2326049542
Short name T192
Test name
Test status
Simulation time 1396290306 ps
CPU time 12.39 seconds
Started Jul 02 09:42:19 AM PDT 24
Finished Jul 02 09:42:33 AM PDT 24
Peak memory 217768 kb
Host smart-fc111fbd-b4bb-4286-be62-2b1098799825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326049542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.2326049542
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.591320189
Short name T419
Test name
Test status
Simulation time 92320578 ps
CPU time 1.81 seconds
Started Jul 02 09:42:18 AM PDT 24
Finished Jul 02 09:42:21 AM PDT 24
Peak memory 217200 kb
Host smart-b8888e0f-79c9-49d3-8ebe-59006d1bd6cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591320189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.591320189
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.843925931
Short name T411
Test name
Test status
Simulation time 209447938 ps
CPU time 2.81 seconds
Started Jul 02 09:42:17 AM PDT 24
Finished Jul 02 09:42:20 AM PDT 24
Peak memory 222012 kb
Host smart-6e022584-56b8-432d-8916-5ffdcd3a9981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843925931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.843925931
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.1706900834
Short name T554
Test name
Test status
Simulation time 491097634 ps
CPU time 19.42 seconds
Started Jul 02 09:42:19 AM PDT 24
Finished Jul 02 09:42:40 AM PDT 24
Peak memory 218440 kb
Host smart-9ee04295-ccc4-45fb-96c3-e656e1104311
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706900834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.1706900834
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.989575583
Short name T828
Test name
Test status
Simulation time 1747215623 ps
CPU time 11.76 seconds
Started Jul 02 09:42:19 AM PDT 24
Finished Jul 02 09:42:33 AM PDT 24
Peak memory 225524 kb
Host smart-4bb8fe57-8c98-4936-bf79-8225a6d066ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989575583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_di
gest.989575583
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.3760231739
Short name T740
Test name
Test status
Simulation time 558913152 ps
CPU time 12.32 seconds
Started Jul 02 09:42:18 AM PDT 24
Finished Jul 02 09:42:31 AM PDT 24
Peak memory 225516 kb
Host smart-6dcc02d1-6cbb-4d43-9826-07d529b723c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760231739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
3760231739
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.4193141609
Short name T372
Test name
Test status
Simulation time 362066860 ps
CPU time 13.99 seconds
Started Jul 02 09:42:18 AM PDT 24
Finished Jul 02 09:42:34 AM PDT 24
Peak memory 217800 kb
Host smart-51fdeb81-4e0f-4d8a-b074-641df8db53ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193141609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.4193141609
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.4143328569
Short name T281
Test name
Test status
Simulation time 606505942 ps
CPU time 3.27 seconds
Started Jul 02 09:42:18 AM PDT 24
Finished Jul 02 09:42:22 AM PDT 24
Peak memory 217212 kb
Host smart-a7a80d81-853d-4f77-845d-555ceb328a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143328569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.4143328569
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.247319150
Short name T832
Test name
Test status
Simulation time 1941300607 ps
CPU time 31.74 seconds
Started Jul 02 09:42:15 AM PDT 24
Finished Jul 02 09:42:48 AM PDT 24
Peak memory 250512 kb
Host smart-e67426a0-e816-48d8-b796-ae7b2964cba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247319150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.247319150
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.2380892447
Short name T356
Test name
Test status
Simulation time 90767679 ps
CPU time 6.52 seconds
Started Jul 02 09:42:19 AM PDT 24
Finished Jul 02 09:42:27 AM PDT 24
Peak memory 247096 kb
Host smart-066c16ca-3d79-406a-9b49-0620d57bbc81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380892447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.2380892447
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.2934848467
Short name T447
Test name
Test status
Simulation time 23104323019 ps
CPU time 123.69 seconds
Started Jul 02 09:42:18 AM PDT 24
Finished Jul 02 09:44:23 AM PDT 24
Peak memory 283388 kb
Host smart-2faa2e02-d4df-4ffd-9458-eff2972e2c48
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934848467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.2934848467
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.777396542
Short name T125
Test name
Test status
Simulation time 75839107509 ps
CPU time 594.56 seconds
Started Jul 02 09:42:19 AM PDT 24
Finished Jul 02 09:52:16 AM PDT 24
Peak memory 271632 kb
Host smart-2459f155-0c32-4349-86ca-f6ae28d1d587
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=777396542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all_with_rand_reset.777396542
Directory /workspace/46.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.3150909535
Short name T265
Test name
Test status
Simulation time 15648179 ps
CPU time 1.13 seconds
Started Jul 02 09:42:14 AM PDT 24
Finished Jul 02 09:42:15 AM PDT 24
Peak memory 211384 kb
Host smart-6f9168a0-fded-4076-8d31-fdf37818a235
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150909535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.3150909535
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.2375048595
Short name T775
Test name
Test status
Simulation time 16394274 ps
CPU time 0.91 seconds
Started Jul 02 09:42:24 AM PDT 24
Finished Jul 02 09:42:27 AM PDT 24
Peak memory 208548 kb
Host smart-6a4b2d0a-61ac-4923-9c4b-919cbe300911
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375048595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.2375048595
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.2878632678
Short name T452
Test name
Test status
Simulation time 224820377 ps
CPU time 11.09 seconds
Started Jul 02 09:42:19 AM PDT 24
Finished Jul 02 09:42:33 AM PDT 24
Peak memory 217704 kb
Host smart-ab0d58d5-645d-412c-865a-48dcc3c0b43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878632678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.2878632678
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.124184537
Short name T27
Test name
Test status
Simulation time 1555918236 ps
CPU time 11.39 seconds
Started Jul 02 09:42:18 AM PDT 24
Finished Jul 02 09:42:31 AM PDT 24
Peak memory 217208 kb
Host smart-a1725730-bbd4-425f-86de-e06b131cc101
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124184537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.124184537
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.2930406813
Short name T399
Test name
Test status
Simulation time 52344754 ps
CPU time 2.76 seconds
Started Jul 02 09:42:17 AM PDT 24
Finished Jul 02 09:42:20 AM PDT 24
Peak memory 221708 kb
Host smart-1121e7a5-8377-4e79-96ec-fd495abffc29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930406813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.2930406813
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.695232394
Short name T760
Test name
Test status
Simulation time 1868790103 ps
CPU time 13.2 seconds
Started Jul 02 09:42:24 AM PDT 24
Finished Jul 02 09:42:39 AM PDT 24
Peak memory 225496 kb
Host smart-d38c8731-d8dc-4b47-8d75-8e39c47d4586
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695232394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_di
gest.695232394
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.3116723661
Short name T298
Test name
Test status
Simulation time 6287823634 ps
CPU time 14.29 seconds
Started Jul 02 09:42:17 AM PDT 24
Finished Jul 02 09:42:32 AM PDT 24
Peak memory 225584 kb
Host smart-155d4cfe-f23a-4f5f-ac4e-e8fd2d178134
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116723661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
3116723661
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.2033605315
Short name T66
Test name
Test status
Simulation time 1405541060 ps
CPU time 9.19 seconds
Started Jul 02 09:42:19 AM PDT 24
Finished Jul 02 09:42:30 AM PDT 24
Peak memory 225584 kb
Host smart-6760f4ad-3a0b-49ed-899d-58a8c0daddd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033605315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.2033605315
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.2130785294
Short name T262
Test name
Test status
Simulation time 160033333 ps
CPU time 4.68 seconds
Started Jul 02 09:42:18 AM PDT 24
Finished Jul 02 09:42:25 AM PDT 24
Peak memory 217180 kb
Host smart-991d7c4a-05ac-417f-acc8-3eb1dadc302c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130785294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.2130785294
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.3100854576
Short name T865
Test name
Test status
Simulation time 1245091837 ps
CPU time 31.5 seconds
Started Jul 02 09:42:19 AM PDT 24
Finished Jul 02 09:42:52 AM PDT 24
Peak memory 250504 kb
Host smart-59785de2-4665-41f2-9770-7e63029653ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100854576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.3100854576
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.3824328213
Short name T834
Test name
Test status
Simulation time 331118170 ps
CPU time 6.52 seconds
Started Jul 02 09:42:17 AM PDT 24
Finished Jul 02 09:42:24 AM PDT 24
Peak memory 248280 kb
Host smart-8ecbb570-e30a-4867-a24a-fe7ef2cfded7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824328213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.3824328213
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.1799285686
Short name T790
Test name
Test status
Simulation time 5669315194 ps
CPU time 89.69 seconds
Started Jul 02 09:42:17 AM PDT 24
Finished Jul 02 09:43:48 AM PDT 24
Peak memory 220920 kb
Host smart-82fc2c29-9d53-48d6-9fb0-5a93e07e8ed5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799285686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.1799285686
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.3693087008
Short name T159
Test name
Test status
Simulation time 86243447168 ps
CPU time 417.09 seconds
Started Jul 02 09:42:20 AM PDT 24
Finished Jul 02 09:49:19 AM PDT 24
Peak memory 316184 kb
Host smart-fa2a795a-ad08-4065-875b-6b33e6a741fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3693087008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all_with_rand_reset.3693087008
Directory /workspace/47.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.2281264045
Short name T393
Test name
Test status
Simulation time 25523890 ps
CPU time 1.1 seconds
Started Jul 02 09:42:19 AM PDT 24
Finished Jul 02 09:42:22 AM PDT 24
Peak memory 211412 kb
Host smart-1368d01c-ff53-4c8b-a8dd-6e70e238970b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281264045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.2281264045
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.1246418580
Short name T627
Test name
Test status
Simulation time 20140365 ps
CPU time 1.2 seconds
Started Jul 02 09:42:19 AM PDT 24
Finished Jul 02 09:42:22 AM PDT 24
Peak memory 208512 kb
Host smart-f3c1258c-a9a0-4c61-8b76-f0c46e97aad3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246418580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.1246418580
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.2344267078
Short name T47
Test name
Test status
Simulation time 1035278945 ps
CPU time 12.89 seconds
Started Jul 02 09:42:23 AM PDT 24
Finished Jul 02 09:42:39 AM PDT 24
Peak memory 217768 kb
Host smart-81d10b19-847f-4012-9dab-43a7621dddeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344267078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.2344267078
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.2639205960
Short name T791
Test name
Test status
Simulation time 4561902688 ps
CPU time 3.01 seconds
Started Jul 02 09:42:22 AM PDT 24
Finished Jul 02 09:42:28 AM PDT 24
Peak memory 217276 kb
Host smart-d2285227-7c7f-4041-9f0d-a7f95ddc29cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639205960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.2639205960
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.3095093136
Short name T18
Test name
Test status
Simulation time 950706958 ps
CPU time 2.88 seconds
Started Jul 02 09:42:20 AM PDT 24
Finished Jul 02 09:42:26 AM PDT 24
Peak memory 221984 kb
Host smart-447751e1-05b6-412c-888d-965b0ec0b7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095093136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.3095093136
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.3928182579
Short name T460
Test name
Test status
Simulation time 1114070237 ps
CPU time 9.14 seconds
Started Jul 02 09:42:20 AM PDT 24
Finished Jul 02 09:42:33 AM PDT 24
Peak memory 225516 kb
Host smart-4d8dec55-f8f9-4e10-a36d-afc8472054eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928182579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.3928182579
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.1734344423
Short name T64
Test name
Test status
Simulation time 365435202 ps
CPU time 7.26 seconds
Started Jul 02 09:42:23 AM PDT 24
Finished Jul 02 09:42:33 AM PDT 24
Peak memory 217700 kb
Host smart-68f7b6c3-02a0-4124-ad41-72525b2afd45
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734344423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
1734344423
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.2279039567
Short name T741
Test name
Test status
Simulation time 237254782 ps
CPU time 6.34 seconds
Started Jul 02 09:42:23 AM PDT 24
Finished Jul 02 09:42:32 AM PDT 24
Peak memory 224284 kb
Host smart-d9ba09cf-d1dc-4ef8-8d44-d1a185ade02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279039567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.2279039567
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.1976146135
Short name T280
Test name
Test status
Simulation time 35180691 ps
CPU time 2.62 seconds
Started Jul 02 09:42:25 AM PDT 24
Finished Jul 02 09:42:29 AM PDT 24
Peak memory 214140 kb
Host smart-9d4c8f63-58a1-43d7-9189-f32bf2dd7536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976146135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.1976146135
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.3245767257
Short name T267
Test name
Test status
Simulation time 979035318 ps
CPU time 30.69 seconds
Started Jul 02 09:42:22 AM PDT 24
Finished Jul 02 09:42:56 AM PDT 24
Peak memory 250528 kb
Host smart-e094c9c0-002c-44d5-88ed-6ab73b2002a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245767257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.3245767257
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.403371777
Short name T519
Test name
Test status
Simulation time 122402180 ps
CPU time 7.87 seconds
Started Jul 02 09:42:22 AM PDT 24
Finished Jul 02 09:42:32 AM PDT 24
Peak memory 250516 kb
Host smart-940b1636-b642-49e3-8e0d-ddfd519d399d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403371777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.403371777
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.3165030144
Short name T99
Test name
Test status
Simulation time 3617154749 ps
CPU time 157.13 seconds
Started Jul 02 09:42:22 AM PDT 24
Finished Jul 02 09:45:02 AM PDT 24
Peak memory 332500 kb
Host smart-367d5f24-ba99-4f7b-bb51-9fbce717897c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165030144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.3165030144
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.1111374836
Short name T97
Test name
Test status
Simulation time 13922398964 ps
CPU time 253.11 seconds
Started Jul 02 09:42:22 AM PDT 24
Finished Jul 02 09:46:38 AM PDT 24
Peak memory 268080 kb
Host smart-f80bd6e9-f20f-40cb-8926-bfd77db2b80f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1111374836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.1111374836
Directory /workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.831043499
Short name T383
Test name
Test status
Simulation time 35936051 ps
CPU time 1.01 seconds
Started Jul 02 09:42:21 AM PDT 24
Finished Jul 02 09:42:25 AM PDT 24
Peak memory 211392 kb
Host smart-9be5f258-9368-48e0-a2cf-88252bae03ff
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831043499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ct
rl_volatile_unlock_smoke.831043499
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.3852445987
Short name T620
Test name
Test status
Simulation time 94922194 ps
CPU time 1.16 seconds
Started Jul 02 09:42:27 AM PDT 24
Finished Jul 02 09:42:29 AM PDT 24
Peak memory 208544 kb
Host smart-50c43159-f7d1-498f-b81b-1b978910e902
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852445987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.3852445987
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.2455417680
Short name T650
Test name
Test status
Simulation time 1111040247 ps
CPU time 12.61 seconds
Started Jul 02 09:42:25 AM PDT 24
Finished Jul 02 09:42:39 AM PDT 24
Peak memory 217964 kb
Host smart-dbd8f363-2a30-46a7-b120-2a8b57e0b325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455417680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.2455417680
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.507502263
Short name T566
Test name
Test status
Simulation time 363676570 ps
CPU time 9 seconds
Started Jul 02 09:42:26 AM PDT 24
Finished Jul 02 09:42:36 AM PDT 24
Peak memory 217284 kb
Host smart-3e22a0ae-fce2-4be0-8c99-e63974f8c5d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507502263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.507502263
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.3520381310
Short name T427
Test name
Test status
Simulation time 56421924 ps
CPU time 2.79 seconds
Started Jul 02 09:42:21 AM PDT 24
Finished Jul 02 09:42:27 AM PDT 24
Peak memory 217800 kb
Host smart-7f307105-bf4c-46ea-811e-34cabe8b501f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520381310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.3520381310
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.3194956344
Short name T685
Test name
Test status
Simulation time 1078744836 ps
CPU time 22.1 seconds
Started Jul 02 09:42:26 AM PDT 24
Finished Jul 02 09:42:49 AM PDT 24
Peak memory 218452 kb
Host smart-ff9b7ecd-78d2-43a7-8988-e6933acb6afb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194956344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.3194956344
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.172221499
Short name T410
Test name
Test status
Simulation time 1128728172 ps
CPU time 10.92 seconds
Started Jul 02 09:42:22 AM PDT 24
Finished Jul 02 09:42:36 AM PDT 24
Peak memory 225528 kb
Host smart-66aa71a3-f133-4365-8695-3156bc4f53a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172221499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_di
gest.172221499
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.2143971847
Short name T524
Test name
Test status
Simulation time 341934525 ps
CPU time 12.84 seconds
Started Jul 02 09:42:25 AM PDT 24
Finished Jul 02 09:42:39 AM PDT 24
Peak memory 217740 kb
Host smart-97673eeb-5c4a-4cd3-8d63-344e2e8270b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143971847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
2143971847
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.1525440952
Short name T398
Test name
Test status
Simulation time 408961963 ps
CPU time 12.76 seconds
Started Jul 02 09:42:26 AM PDT 24
Finished Jul 02 09:42:40 AM PDT 24
Peak memory 217864 kb
Host smart-4041f3fe-5aeb-4544-ae05-bd3246b14596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525440952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.1525440952
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.2647376726
Short name T84
Test name
Test status
Simulation time 620384932 ps
CPU time 9.84 seconds
Started Jul 02 09:42:20 AM PDT 24
Finished Jul 02 09:42:33 AM PDT 24
Peak memory 217176 kb
Host smart-fec674a6-a5cc-4063-a53c-686170b14c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647376726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.2647376726
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.3984085276
Short name T170
Test name
Test status
Simulation time 5035731590 ps
CPU time 32.04 seconds
Started Jul 02 09:42:22 AM PDT 24
Finished Jul 02 09:42:57 AM PDT 24
Peak memory 250672 kb
Host smart-f5540d05-9919-4bf3-a0f4-bd1a74115dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984085276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.3984085276
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.600602129
Short name T243
Test name
Test status
Simulation time 264475248 ps
CPU time 6.71 seconds
Started Jul 02 09:42:19 AM PDT 24
Finished Jul 02 09:42:28 AM PDT 24
Peak memory 250080 kb
Host smart-5e9305d1-d5ab-454d-9d8f-100b1138e723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600602129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.600602129
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.2015489689
Short name T210
Test name
Test status
Simulation time 6237854760 ps
CPU time 64.51 seconds
Started Jul 02 09:42:24 AM PDT 24
Finished Jul 02 09:43:31 AM PDT 24
Peak memory 266972 kb
Host smart-a1781ef0-c799-48c1-97f6-09f641114f71
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015489689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.2015489689
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.447637353
Short name T693
Test name
Test status
Simulation time 27656968 ps
CPU time 1.05 seconds
Started Jul 02 09:42:23 AM PDT 24
Finished Jul 02 09:42:27 AM PDT 24
Peak memory 217204 kb
Host smart-9162bb7b-c972-4971-a2be-6b53bfb36503
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447637353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ct
rl_volatile_unlock_smoke.447637353
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.2977203510
Short name T572
Test name
Test status
Simulation time 72597333 ps
CPU time 0.91 seconds
Started Jul 02 09:40:20 AM PDT 24
Finished Jul 02 09:40:24 AM PDT 24
Peak memory 208580 kb
Host smart-2a514629-2178-4a75-8eec-1c66304f64da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977203510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.2977203510
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.4177330690
Short name T845
Test name
Test status
Simulation time 327903278 ps
CPU time 12.03 seconds
Started Jul 02 09:40:16 AM PDT 24
Finished Jul 02 09:40:31 AM PDT 24
Peak memory 217784 kb
Host smart-4d6f1923-e450-446d-8e4b-85b22aba4782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177330690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.4177330690
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.2885558908
Short name T551
Test name
Test status
Simulation time 369749010 ps
CPU time 2.97 seconds
Started Jul 02 09:40:18 AM PDT 24
Finished Jul 02 09:40:24 AM PDT 24
Peak memory 217188 kb
Host smart-adb34791-7306-4936-b6eb-f2a50b792488
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885558908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.2885558908
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.1891646524
Short name T505
Test name
Test status
Simulation time 25467095988 ps
CPU time 46.71 seconds
Started Jul 02 09:40:20 AM PDT 24
Finished Jul 02 09:41:10 AM PDT 24
Peak memory 218288 kb
Host smart-ea4cfef4-d527-46a6-8d35-8a7198b4d73e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891646524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.1891646524
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.1955396569
Short name T327
Test name
Test status
Simulation time 2695465724 ps
CPU time 8.57 seconds
Started Jul 02 09:40:17 AM PDT 24
Finished Jul 02 09:40:29 AM PDT 24
Peak memory 217332 kb
Host smart-d773f07c-5469-4dae-90d2-8d34c19a8622
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955396569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.1
955396569
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.1403323112
Short name T474
Test name
Test status
Simulation time 119644110 ps
CPU time 3.91 seconds
Started Jul 02 09:40:19 AM PDT 24
Finished Jul 02 09:40:27 AM PDT 24
Peak memory 217668 kb
Host smart-8dbff0b0-3afd-498c-beff-bb999a392f1e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403323112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.1403323112
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.3973459289
Short name T745
Test name
Test status
Simulation time 3706269720 ps
CPU time 13.78 seconds
Started Jul 02 09:40:18 AM PDT 24
Finished Jul 02 09:40:35 AM PDT 24
Peak memory 217192 kb
Host smart-9a5298bd-28bf-4086-9a3e-be35d2c06364
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973459289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.3973459289
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.3821039825
Short name T513
Test name
Test status
Simulation time 429915831 ps
CPU time 5.84 seconds
Started Jul 02 09:40:18 AM PDT 24
Finished Jul 02 09:40:27 AM PDT 24
Peak memory 217080 kb
Host smart-818072e1-85c2-4564-8233-05f7827759fa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821039825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
3821039825
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.4085642800
Short name T738
Test name
Test status
Simulation time 4593027570 ps
CPU time 57.98 seconds
Started Jul 02 09:40:16 AM PDT 24
Finished Jul 02 09:41:17 AM PDT 24
Peak memory 266924 kb
Host smart-7917c3e8-d85b-4c28-8dad-f7d1b81aa9f4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085642800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.4085642800
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.3967926958
Short name T24
Test name
Test status
Simulation time 2528514398 ps
CPU time 16.04 seconds
Started Jul 02 09:40:19 AM PDT 24
Finished Jul 02 09:40:39 AM PDT 24
Peak memory 250512 kb
Host smart-755cf300-03bb-413f-993a-c67bde9dd69c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967926958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.3967926958
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.2306654315
Short name T516
Test name
Test status
Simulation time 52382356 ps
CPU time 2.84 seconds
Started Jul 02 09:40:17 AM PDT 24
Finished Jul 02 09:40:24 AM PDT 24
Peak memory 217760 kb
Host smart-6c7fb41e-636d-47fc-8027-c3c1a6d25406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306654315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.2306654315
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.1369260548
Short name T614
Test name
Test status
Simulation time 351151390 ps
CPU time 5.19 seconds
Started Jul 02 09:40:19 AM PDT 24
Finished Jul 02 09:40:28 AM PDT 24
Peak memory 217200 kb
Host smart-a5ee4c3a-0754-4d56-89a1-ea27e008b140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369260548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.1369260548
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.853688863
Short name T675
Test name
Test status
Simulation time 687094073 ps
CPU time 19.61 seconds
Started Jul 02 09:40:21 AM PDT 24
Finished Jul 02 09:40:44 AM PDT 24
Peak memory 225584 kb
Host smart-792a396d-5382-4637-bed4-67ebc94858ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853688863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.853688863
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.2062848484
Short name T337
Test name
Test status
Simulation time 865918581 ps
CPU time 9.25 seconds
Started Jul 02 09:40:20 AM PDT 24
Finished Jul 02 09:40:33 AM PDT 24
Peak memory 225504 kb
Host smart-7207bb9c-2998-4bfc-b5dd-1d8c773cc39e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062848484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.2062848484
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.3835886403
Short name T830
Test name
Test status
Simulation time 2313844863 ps
CPU time 9.12 seconds
Started Jul 02 09:40:19 AM PDT 24
Finished Jul 02 09:40:32 AM PDT 24
Peak memory 217956 kb
Host smart-40a211e9-8a61-4db7-8e54-48de43531cea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835886403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.3
835886403
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.788210276
Short name T439
Test name
Test status
Simulation time 4177008628 ps
CPU time 14.2 seconds
Started Jul 02 09:40:19 AM PDT 24
Finished Jul 02 09:40:37 AM PDT 24
Peak memory 225664 kb
Host smart-a91b35c8-d8ca-4874-8f2b-76e59748193e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788210276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.788210276
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.1148428104
Short name T319
Test name
Test status
Simulation time 41935439 ps
CPU time 2.69 seconds
Started Jul 02 09:40:16 AM PDT 24
Finished Jul 02 09:40:20 AM PDT 24
Peak memory 217284 kb
Host smart-db061c1a-9b9d-49d5-ad1b-09ef3c0b35e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148428104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.1148428104
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.2230576836
Short name T540
Test name
Test status
Simulation time 1106156767 ps
CPU time 25.81 seconds
Started Jul 02 09:40:19 AM PDT 24
Finished Jul 02 09:40:49 AM PDT 24
Peak memory 250500 kb
Host smart-02cd00f8-d03b-447c-962e-1ef5f80588a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230576836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.2230576836
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.3435044489
Short name T289
Test name
Test status
Simulation time 86356065 ps
CPU time 4.05 seconds
Started Jul 02 09:40:19 AM PDT 24
Finished Jul 02 09:40:27 AM PDT 24
Peak memory 221824 kb
Host smart-882440a9-994c-4c6a-bfa7-b9cc61402874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435044489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.3435044489
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.1027542916
Short name T661
Test name
Test status
Simulation time 5022772781 ps
CPU time 91.64 seconds
Started Jul 02 09:40:24 AM PDT 24
Finished Jul 02 09:41:57 AM PDT 24
Peak memory 275712 kb
Host smart-051fcc60-3947-41f9-87a1-a82ed1f7f999
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027542916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.1027542916
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.887981104
Short name T465
Test name
Test status
Simulation time 71799254 ps
CPU time 0.95 seconds
Started Jul 02 09:40:16 AM PDT 24
Finished Jul 02 09:40:19 AM PDT 24
Peak memory 211472 kb
Host smart-2fe4c4ff-a6bb-4d08-9cf0-91875bb17a71
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887981104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctr
l_volatile_unlock_smoke.887981104
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.733942022
Short name T469
Test name
Test status
Simulation time 21448120 ps
CPU time 1.17 seconds
Started Jul 02 09:40:25 AM PDT 24
Finished Jul 02 09:40:28 AM PDT 24
Peak memory 208700 kb
Host smart-c1f842a7-df03-4db1-b3d0-aeb70e746dbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733942022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.733942022
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.3762259184
Short name T386
Test name
Test status
Simulation time 582279275 ps
CPU time 11.92 seconds
Started Jul 02 09:40:20 AM PDT 24
Finished Jul 02 09:40:36 AM PDT 24
Peak memory 217732 kb
Host smart-afb6407d-209f-44dd-8ef9-1a1c4b1820ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762259184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.3762259184
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.4146387483
Short name T747
Test name
Test status
Simulation time 1299032320 ps
CPU time 12.64 seconds
Started Jul 02 09:40:22 AM PDT 24
Finished Jul 02 09:40:37 AM PDT 24
Peak memory 217208 kb
Host smart-47255c4f-8415-431b-b144-bc7f96787780
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146387483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.4146387483
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.156063567
Short name T801
Test name
Test status
Simulation time 78738177836 ps
CPU time 71.01 seconds
Started Jul 02 09:40:24 AM PDT 24
Finished Jul 02 09:41:37 AM PDT 24
Peak memory 219364 kb
Host smart-f0958401-dcec-4a69-9c4a-846a8aa467df
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156063567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_err
ors.156063567
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.928501071
Short name T803
Test name
Test status
Simulation time 628363912 ps
CPU time 2.36 seconds
Started Jul 02 09:40:24 AM PDT 24
Finished Jul 02 09:40:27 AM PDT 24
Peak memory 217240 kb
Host smart-2d026f04-af14-427e-a0aa-7053ba9b62a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928501071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.928501071
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.1761137120
Short name T802
Test name
Test status
Simulation time 190444896 ps
CPU time 4.03 seconds
Started Jul 02 09:40:36 AM PDT 24
Finished Jul 02 09:40:41 AM PDT 24
Peak memory 217612 kb
Host smart-0a468d8b-d952-419a-94e6-85e90f5e1e36
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761137120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.1761137120
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.2631248067
Short name T722
Test name
Test status
Simulation time 6825341195 ps
CPU time 40.5 seconds
Started Jul 02 09:40:37 AM PDT 24
Finished Jul 02 09:41:19 AM PDT 24
Peak memory 217092 kb
Host smart-a857dca8-71bc-4838-a37c-2ee13d202317
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631248067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.2631248067
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.2345393531
Short name T763
Test name
Test status
Simulation time 286226609 ps
CPU time 5.21 seconds
Started Jul 02 09:40:22 AM PDT 24
Finished Jul 02 09:40:29 AM PDT 24
Peak memory 217112 kb
Host smart-bb9dd70c-7b97-4c0e-8b7a-e145c3385878
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345393531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
2345393531
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.3037974865
Short name T349
Test name
Test status
Simulation time 1675316654 ps
CPU time 26.01 seconds
Started Jul 02 09:40:27 AM PDT 24
Finished Jul 02 09:40:55 AM PDT 24
Peak memory 250364 kb
Host smart-1ed100e6-2780-4b15-9cdc-46602740fc95
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037974865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.3037974865
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.628838272
Short name T36
Test name
Test status
Simulation time 412047732 ps
CPU time 16.04 seconds
Started Jul 02 09:40:25 AM PDT 24
Finished Jul 02 09:40:42 AM PDT 24
Peak memory 250348 kb
Host smart-1a241d35-6621-4240-80ad-08b698268a29
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628838272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_j
tag_state_post_trans.628838272
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.532541860
Short name T640
Test name
Test status
Simulation time 585019677 ps
CPU time 2.49 seconds
Started Jul 02 09:40:24 AM PDT 24
Finished Jul 02 09:40:28 AM PDT 24
Peak memory 217676 kb
Host smart-bbfda230-ac88-469b-aeb6-28ab424036dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532541860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.532541860
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.3680994160
Short name T495
Test name
Test status
Simulation time 646854304 ps
CPU time 12.16 seconds
Started Jul 02 09:40:27 AM PDT 24
Finished Jul 02 09:40:40 AM PDT 24
Peak memory 217220 kb
Host smart-7e9af904-9cbd-4375-990e-7112433c0559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680994160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.3680994160
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.4062990597
Short name T783
Test name
Test status
Simulation time 1376624038 ps
CPU time 10.36 seconds
Started Jul 02 09:40:25 AM PDT 24
Finished Jul 02 09:40:36 AM PDT 24
Peak memory 225552 kb
Host smart-a2f4e8b8-0daa-472d-a9d1-7882c2215796
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062990597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.4062990597
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.3645119716
Short name T807
Test name
Test status
Simulation time 2955017886 ps
CPU time 9.12 seconds
Started Jul 02 09:40:22 AM PDT 24
Finished Jul 02 09:40:34 AM PDT 24
Peak memory 225660 kb
Host smart-af0791b1-9ee7-44ad-8953-3e092352c379
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645119716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.3645119716
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.3912391119
Short name T261
Test name
Test status
Simulation time 328197157 ps
CPU time 8.56 seconds
Started Jul 02 09:40:25 AM PDT 24
Finished Jul 02 09:40:35 AM PDT 24
Peak memory 217736 kb
Host smart-03cde7c4-ecda-4190-98f1-b7ddad80fd74
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912391119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.3
912391119
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.4272942467
Short name T736
Test name
Test status
Simulation time 279741687 ps
CPU time 8.38 seconds
Started Jul 02 09:40:20 AM PDT 24
Finished Jul 02 09:40:32 AM PDT 24
Peak memory 224536 kb
Host smart-144d861c-adb1-48cb-9e2a-d38ecf4ed83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272942467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.4272942467
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.3207816671
Short name T840
Test name
Test status
Simulation time 41326766 ps
CPU time 1.51 seconds
Started Jul 02 09:40:20 AM PDT 24
Finished Jul 02 09:40:25 AM PDT 24
Peak memory 217216 kb
Host smart-df13c1cd-e8cf-4ca0-8f65-90318375fd6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207816671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.3207816671
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.4041492121
Short name T330
Test name
Test status
Simulation time 697493652 ps
CPU time 21.5 seconds
Started Jul 02 09:40:20 AM PDT 24
Finished Jul 02 09:40:45 AM PDT 24
Peak memory 250548 kb
Host smart-d3aa9bda-87fc-4baa-8fd2-f51c91c97a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041492121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.4041492121
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.2355231354
Short name T10
Test name
Test status
Simulation time 541065886 ps
CPU time 6.58 seconds
Started Jul 02 09:40:21 AM PDT 24
Finished Jul 02 09:40:30 AM PDT 24
Peak memory 250504 kb
Host smart-5dbfaf27-82b6-4888-8d3d-7f9cff4d746b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355231354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.2355231354
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.709617051
Short name T87
Test name
Test status
Simulation time 15108405602 ps
CPU time 494.04 seconds
Started Jul 02 09:40:26 AM PDT 24
Finished Jul 02 09:48:42 AM PDT 24
Peak memory 266956 kb
Host smart-d561db89-ca25-4359-be0f-4895e2f8edeb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709617051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.709617051
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.1801145939
Short name T164
Test name
Test status
Simulation time 29857287379 ps
CPU time 991.18 seconds
Started Jul 02 09:40:24 AM PDT 24
Finished Jul 02 09:56:57 AM PDT 24
Peak memory 316236 kb
Host smart-d8bd38b8-b4a7-4590-8c60-23d4b32ac1a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1801145939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.1801145939
Directory /workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.601660896
Short name T719
Test name
Test status
Simulation time 31688957 ps
CPU time 0.83 seconds
Started Jul 02 09:40:19 AM PDT 24
Finished Jul 02 09:40:24 AM PDT 24
Peak memory 208632 kb
Host smart-aaa373ef-6553-4f2d-af3b-c9d108f0537e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601660896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctr
l_volatile_unlock_smoke.601660896
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.1289889204
Short name T645
Test name
Test status
Simulation time 127895075 ps
CPU time 1.04 seconds
Started Jul 02 09:40:29 AM PDT 24
Finished Jul 02 09:40:31 AM PDT 24
Peak memory 208544 kb
Host smart-aa421e4a-a11c-4edc-aaf9-9af2b4cf7689
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289889204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.1289889204
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.3070499569
Short name T468
Test name
Test status
Simulation time 177503088 ps
CPU time 7.45 seconds
Started Jul 02 09:40:22 AM PDT 24
Finished Jul 02 09:40:32 AM PDT 24
Peak memory 225588 kb
Host smart-2e81fe4e-4026-4bc3-9448-83c3213f7644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070499569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.3070499569
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.90688509
Short name T857
Test name
Test status
Simulation time 3241009869 ps
CPU time 12.03 seconds
Started Jul 02 09:40:25 AM PDT 24
Finished Jul 02 09:40:38 AM PDT 24
Peak memory 217264 kb
Host smart-1d0c2bd0-b210-4e39-a4a0-7e9196eb9362
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90688509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.90688509
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.3838271834
Short name T667
Test name
Test status
Simulation time 17473356577 ps
CPU time 21.96 seconds
Started Jul 02 09:40:36 AM PDT 24
Finished Jul 02 09:40:59 AM PDT 24
Peak memory 218308 kb
Host smart-a1400bd8-0992-45b4-af83-c8c6cdc8b405
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838271834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.3838271834
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.2766185975
Short name T22
Test name
Test status
Simulation time 129652658 ps
CPU time 2.31 seconds
Started Jul 02 09:40:26 AM PDT 24
Finished Jul 02 09:40:29 AM PDT 24
Peak memory 217288 kb
Host smart-59de16a1-f162-423a-8d1e-e5db1c1f38bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766185975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.2
766185975
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.95107278
Short name T496
Test name
Test status
Simulation time 2093111057 ps
CPU time 14.33 seconds
Started Jul 02 09:40:30 AM PDT 24
Finished Jul 02 09:40:46 AM PDT 24
Peak memory 223708 kb
Host smart-2c538abf-0ae2-4ebd-99ca-9ad7f38b22ef
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95107278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p
rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_p
rog_failure.95107278
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.768926507
Short name T76
Test name
Test status
Simulation time 1551050694 ps
CPU time 40.74 seconds
Started Jul 02 09:40:25 AM PDT 24
Finished Jul 02 09:41:07 AM PDT 24
Peak memory 217104 kb
Host smart-7ac5c019-baec-48d2-8e59-683d1d0ef5fc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768926507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_regwen_during_op.768926507
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.1821775661
Short name T644
Test name
Test status
Simulation time 788240846 ps
CPU time 5.34 seconds
Started Jul 02 09:40:25 AM PDT 24
Finished Jul 02 09:40:31 AM PDT 24
Peak memory 217096 kb
Host smart-1fe7fca6-68f0-4829-900d-ba8e9c786a42
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821775661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
1821775661
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.1241111130
Short name T392
Test name
Test status
Simulation time 4589500167 ps
CPU time 45.46 seconds
Started Jul 02 09:40:30 AM PDT 24
Finished Jul 02 09:41:16 AM PDT 24
Peak memory 251160 kb
Host smart-bdcf9b3c-79a5-4b44-af14-b86cf7d7f982
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241111130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.1241111130
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.1652649285
Short name T701
Test name
Test status
Simulation time 281605499 ps
CPU time 13.44 seconds
Started Jul 02 09:40:31 AM PDT 24
Finished Jul 02 09:40:46 AM PDT 24
Peak memory 250468 kb
Host smart-f267c476-255d-4221-8337-1357e2c8bebc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652649285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.1652649285
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.3996704647
Short name T459
Test name
Test status
Simulation time 170213346 ps
CPU time 4.56 seconds
Started Jul 02 09:40:25 AM PDT 24
Finished Jul 02 09:40:31 AM PDT 24
Peak memory 217688 kb
Host smart-3628f7a1-e66f-4157-b45c-ada9b41c522b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996704647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.3996704647
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.4242584673
Short name T525
Test name
Test status
Simulation time 503160355 ps
CPU time 14.08 seconds
Started Jul 02 09:40:38 AM PDT 24
Finished Jul 02 09:40:53 AM PDT 24
Peak memory 217116 kb
Host smart-786e9e71-6c5f-47b5-b949-c222fd06b2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242584673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.4242584673
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.1617924107
Short name T241
Test name
Test status
Simulation time 272482026 ps
CPU time 9.79 seconds
Started Jul 02 09:40:36 AM PDT 24
Finished Jul 02 09:40:47 AM PDT 24
Peak memory 225464 kb
Host smart-af578e79-e377-483b-9e4a-6fc7afbfeccb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617924107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.1617924107
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.433299618
Short name T503
Test name
Test status
Simulation time 1934111432 ps
CPU time 12.84 seconds
Started Jul 02 09:40:25 AM PDT 24
Finished Jul 02 09:40:39 AM PDT 24
Peak memory 225516 kb
Host smart-a78cbaa9-d1de-4f79-90a6-8cc775215504
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433299618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_dig
est.433299618
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.1522838255
Short name T579
Test name
Test status
Simulation time 376438244 ps
CPU time 14 seconds
Started Jul 02 09:40:39 AM PDT 24
Finished Jul 02 09:40:54 AM PDT 24
Peak memory 225420 kb
Host smart-3e197cd0-a2bb-4ff4-a01b-95feb586fcd1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522838255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.1
522838255
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.3065952723
Short name T404
Test name
Test status
Simulation time 268871517 ps
CPU time 11.32 seconds
Started Jul 02 09:40:30 AM PDT 24
Finished Jul 02 09:40:43 AM PDT 24
Peak memory 225588 kb
Host smart-6e7be2bb-9f22-4ffc-8f3e-5741043bdb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065952723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.3065952723
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.3889315494
Short name T717
Test name
Test status
Simulation time 509723257 ps
CPU time 2.34 seconds
Started Jul 02 09:40:26 AM PDT 24
Finished Jul 02 09:40:29 AM PDT 24
Peak memory 213832 kb
Host smart-e0ba2ae3-5866-4e44-a51e-c3a459f7c7b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889315494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.3889315494
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.3343644255
Short name T93
Test name
Test status
Simulation time 855327152 ps
CPU time 23.78 seconds
Started Jul 02 09:40:27 AM PDT 24
Finished Jul 02 09:40:52 AM PDT 24
Peak memory 245308 kb
Host smart-7ddd2418-7cd6-4e1c-8281-0a29fbdc944d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343644255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.3343644255
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.3914115011
Short name T51
Test name
Test status
Simulation time 95166315 ps
CPU time 8.34 seconds
Started Jul 02 09:40:25 AM PDT 24
Finished Jul 02 09:40:35 AM PDT 24
Peak memory 250488 kb
Host smart-643ace02-e176-4768-bf10-f0d9c85ad8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914115011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.3914115011
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.137415591
Short name T634
Test name
Test status
Simulation time 3920998783 ps
CPU time 42.29 seconds
Started Jul 02 09:40:29 AM PDT 24
Finished Jul 02 09:41:13 AM PDT 24
Peak memory 250588 kb
Host smart-ab0c9c46-dc65-499a-9199-1ca5ba48addc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137415591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.137415591
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.2195481928
Short name T176
Test name
Test status
Simulation time 21509326405 ps
CPU time 157.75 seconds
Started Jul 02 09:40:28 AM PDT 24
Finished Jul 02 09:43:07 AM PDT 24
Peak memory 267136 kb
Host smart-fc4072c1-3b6c-49be-b8b5-557b90a2b9e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2195481928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all_with_rand_reset.2195481928
Directory /workspace/7.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.4258988312
Short name T712
Test name
Test status
Simulation time 11683890 ps
CPU time 1.04 seconds
Started Jul 02 09:40:25 AM PDT 24
Finished Jul 02 09:40:28 AM PDT 24
Peak memory 211384 kb
Host smart-4b0d0de2-cfac-415e-ba0c-35b692842f91
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258988312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.4258988312
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.4040597407
Short name T254
Test name
Test status
Simulation time 28259409 ps
CPU time 1.09 seconds
Started Jul 02 09:40:27 AM PDT 24
Finished Jul 02 09:40:30 AM PDT 24
Peak memory 208504 kb
Host smart-0f514276-2bdb-4181-995f-a149e923f924
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040597407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.4040597407
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.668801667
Short name T231
Test name
Test status
Simulation time 16685371 ps
CPU time 0.78 seconds
Started Jul 02 09:40:26 AM PDT 24
Finished Jul 02 09:40:28 AM PDT 24
Peak memory 208444 kb
Host smart-7201b242-e519-4a57-975d-ce79a7b6e0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668801667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.668801667
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.179897822
Short name T611
Test name
Test status
Simulation time 1086721036 ps
CPU time 22.49 seconds
Started Jul 02 09:40:28 AM PDT 24
Finished Jul 02 09:40:52 AM PDT 24
Peak memory 217828 kb
Host smart-82b24ad2-34fe-4c91-b2a4-f6a070ff8e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179897822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.179897822
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.2370576056
Short name T715
Test name
Test status
Simulation time 1480946685 ps
CPU time 4.47 seconds
Started Jul 02 09:40:30 AM PDT 24
Finished Jul 02 09:40:35 AM PDT 24
Peak memory 217280 kb
Host smart-c6294dde-7e55-4166-8018-eb1813047984
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370576056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.2370576056
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.300703343
Short name T278
Test name
Test status
Simulation time 3149280020 ps
CPU time 41.58 seconds
Started Jul 02 09:40:28 AM PDT 24
Finished Jul 02 09:41:11 AM PDT 24
Peak memory 218572 kb
Host smart-7fb7ff19-ae71-457f-aba0-aab1ac05d920
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300703343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_err
ors.300703343
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.1237929194
Short name T711
Test name
Test status
Simulation time 2200934408 ps
CPU time 12.03 seconds
Started Jul 02 09:40:29 AM PDT 24
Finished Jul 02 09:40:42 AM PDT 24
Peak memory 217272 kb
Host smart-68339ed7-7f85-432a-80d3-99f99c66c050
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237929194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.1
237929194
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.3333292474
Short name T504
Test name
Test status
Simulation time 269578486 ps
CPU time 2.99 seconds
Started Jul 02 09:40:31 AM PDT 24
Finished Jul 02 09:40:36 AM PDT 24
Peak memory 221204 kb
Host smart-38a4f4e6-caa5-4df1-bfdb-d5f50c369b87
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333292474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.3333292474
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.3226258615
Short name T326
Test name
Test status
Simulation time 4223027264 ps
CPU time 15.38 seconds
Started Jul 02 09:40:36 AM PDT 24
Finished Jul 02 09:40:53 AM PDT 24
Peak memory 217192 kb
Host smart-dc4c1dc5-f119-4df1-a8e3-e27496bd9ead
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226258615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.3226258615
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.2608700718
Short name T766
Test name
Test status
Simulation time 158533413 ps
CPU time 2.86 seconds
Started Jul 02 09:40:32 AM PDT 24
Finished Jul 02 09:40:37 AM PDT 24
Peak memory 217132 kb
Host smart-7eb97a36-b359-4ebe-90b4-e8774824dc6c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608700718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
2608700718
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.1486747011
Short name T291
Test name
Test status
Simulation time 5315500689 ps
CPU time 58.82 seconds
Started Jul 02 09:40:27 AM PDT 24
Finished Jul 02 09:41:28 AM PDT 24
Peak memory 283216 kb
Host smart-ae3f7392-d295-4b4e-8796-6402bdb03aa8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486747011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.1486747011
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.2377342072
Short name T856
Test name
Test status
Simulation time 1105959645 ps
CPU time 12.03 seconds
Started Jul 02 09:40:30 AM PDT 24
Finished Jul 02 09:40:44 AM PDT 24
Peak memory 250472 kb
Host smart-eed79062-062c-48c5-8728-86a45bd8aa1e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377342072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.2377342072
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.1558336055
Short name T467
Test name
Test status
Simulation time 1797341484 ps
CPU time 3.89 seconds
Started Jul 02 09:40:28 AM PDT 24
Finished Jul 02 09:40:33 AM PDT 24
Peak memory 217752 kb
Host smart-ddb736f6-9564-4f85-976b-f696a8f60b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558336055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.1558336055
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.4262347129
Short name T522
Test name
Test status
Simulation time 3539813303 ps
CPU time 26.47 seconds
Started Jul 02 09:40:30 AM PDT 24
Finished Jul 02 09:40:58 AM PDT 24
Peak memory 217372 kb
Host smart-762ef185-7f5c-489f-b551-6866925ccfa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262347129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.4262347129
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.4155058985
Short name T721
Test name
Test status
Simulation time 544083929 ps
CPU time 9.84 seconds
Started Jul 02 09:40:27 AM PDT 24
Finished Jul 02 09:40:38 AM PDT 24
Peak memory 225600 kb
Host smart-5dde9a2a-eb56-4d19-bf5a-e43ad4126df9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155058985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.4155058985
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.2276830997
Short name T861
Test name
Test status
Simulation time 503089064 ps
CPU time 9.64 seconds
Started Jul 02 09:40:29 AM PDT 24
Finished Jul 02 09:40:40 AM PDT 24
Peak memory 225520 kb
Host smart-66088c07-9fee-4eda-9135-764d0b322169
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276830997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.2276830997
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.1322296040
Short name T655
Test name
Test status
Simulation time 996701647 ps
CPU time 8.69 seconds
Started Jul 02 09:40:28 AM PDT 24
Finished Jul 02 09:40:38 AM PDT 24
Peak memory 225516 kb
Host smart-1da8437a-1cfd-4ebe-be81-08d52684c73b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322296040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.1
322296040
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.4173471194
Short name T637
Test name
Test status
Simulation time 545844168 ps
CPU time 11.99 seconds
Started Jul 02 09:40:28 AM PDT 24
Finished Jul 02 09:40:41 AM PDT 24
Peak memory 217764 kb
Host smart-dead30ae-f690-4672-8198-df9647c9e691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173471194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.4173471194
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.2407316284
Short name T14
Test name
Test status
Simulation time 984465366 ps
CPU time 2.77 seconds
Started Jul 02 09:40:29 AM PDT 24
Finished Jul 02 09:40:33 AM PDT 24
Peak memory 222452 kb
Host smart-705ec2eb-1283-4f41-b4fa-8b13a3240566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407316284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.2407316284
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.362922340
Short name T34
Test name
Test status
Simulation time 607615238 ps
CPU time 24.12 seconds
Started Jul 02 09:40:28 AM PDT 24
Finished Jul 02 09:40:53 AM PDT 24
Peak memory 246484 kb
Host smart-27e695ca-a58f-440b-80d4-6c0e2cb20028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362922340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.362922340
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.1308347816
Short name T682
Test name
Test status
Simulation time 231348793 ps
CPU time 7.84 seconds
Started Jul 02 09:40:28 AM PDT 24
Finished Jul 02 09:40:37 AM PDT 24
Peak memory 250508 kb
Host smart-5833e72b-815c-49b2-99a7-26cdf71daee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308347816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.1308347816
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.4160315572
Short name T456
Test name
Test status
Simulation time 62234276190 ps
CPU time 244.87 seconds
Started Jul 02 09:40:31 AM PDT 24
Finished Jul 02 09:44:38 AM PDT 24
Peak memory 272696 kb
Host smart-beeb9457-5b06-4514-bfff-04af3ed018a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160315572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.4160315572
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.4251384760
Short name T115
Test name
Test status
Simulation time 27813010436 ps
CPU time 560.82 seconds
Started Jul 02 09:40:30 AM PDT 24
Finished Jul 02 09:49:52 AM PDT 24
Peak memory 250716 kb
Host smart-c9e5b1cf-dbec-4f17-aac0-13f87e463a08
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4251384760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.4251384760
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.2567184307
Short name T111
Test name
Test status
Simulation time 17079084 ps
CPU time 0.77 seconds
Started Jul 02 09:40:29 AM PDT 24
Finished Jul 02 09:40:31 AM PDT 24
Peak memory 208364 kb
Host smart-86281c11-d4ac-4f11-b1b5-2e88ee1d4114
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567184307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.2567184307
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.457841897
Short name T732
Test name
Test status
Simulation time 106388665 ps
CPU time 1.38 seconds
Started Jul 02 09:40:41 AM PDT 24
Finished Jul 02 09:40:43 AM PDT 24
Peak memory 208568 kb
Host smart-55055dd9-19f3-46ea-b9de-4574aabc4dc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457841897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.457841897
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.4283810282
Short name T510
Test name
Test status
Simulation time 10244658 ps
CPU time 0.85 seconds
Started Jul 02 09:40:33 AM PDT 24
Finished Jul 02 09:40:35 AM PDT 24
Peak memory 208288 kb
Host smart-87fa795b-be76-45a0-b2a7-516846f8eb0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283810282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.4283810282
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.2515578821
Short name T461
Test name
Test status
Simulation time 2280078380 ps
CPU time 14.66 seconds
Started Jul 02 09:40:35 AM PDT 24
Finished Jul 02 09:40:50 AM PDT 24
Peak memory 216884 kb
Host smart-2ff73f4b-27ed-4680-9201-2959afad8bbb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515578821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.2515578821
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.3925091484
Short name T616
Test name
Test status
Simulation time 3707284213 ps
CPU time 36.23 seconds
Started Jul 02 09:40:31 AM PDT 24
Finished Jul 02 09:41:09 AM PDT 24
Peak memory 218428 kb
Host smart-4fe013b0-df14-4d82-9927-2b49c220aa68
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925091484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.3925091484
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.418348543
Short name T800
Test name
Test status
Simulation time 4627710717 ps
CPU time 12.7 seconds
Started Jul 02 09:40:33 AM PDT 24
Finished Jul 02 09:40:47 AM PDT 24
Peak memory 217312 kb
Host smart-bc23aef4-3385-4db9-b6e9-fad86ea31a0c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418348543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.418348543
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.1567345673
Short name T302
Test name
Test status
Simulation time 1088757881 ps
CPU time 28.99 seconds
Started Jul 02 09:40:37 AM PDT 24
Finished Jul 02 09:41:08 AM PDT 24
Peak memory 218360 kb
Host smart-7ac21679-4ec9-4d93-947d-20ddbf6e0d49
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567345673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.1567345673
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.4166681471
Short name T689
Test name
Test status
Simulation time 1487504800 ps
CPU time 22.39 seconds
Started Jul 02 09:40:36 AM PDT 24
Finished Jul 02 09:41:00 AM PDT 24
Peak memory 217104 kb
Host smart-c89e099d-4efa-4e4a-8d28-a118ba9b7761
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166681471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.4166681471
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.2569136942
Short name T25
Test name
Test status
Simulation time 191826395 ps
CPU time 3.95 seconds
Started Jul 02 09:40:36 AM PDT 24
Finished Jul 02 09:40:41 AM PDT 24
Peak memory 217136 kb
Host smart-ebe99211-4bbf-48f8-9fec-fa97dcd603bf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569136942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
2569136942
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.3179536348
Short name T181
Test name
Test status
Simulation time 19439876885 ps
CPU time 51.51 seconds
Started Jul 02 09:40:33 AM PDT 24
Finished Jul 02 09:41:26 AM PDT 24
Peak memory 278164 kb
Host smart-ad6288a2-e906-47d6-bdee-16545f201337
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179536348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.3179536348
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.545205234
Short name T768
Test name
Test status
Simulation time 289970316 ps
CPU time 9.73 seconds
Started Jul 02 09:40:35 AM PDT 24
Finished Jul 02 09:40:46 AM PDT 24
Peak memory 249996 kb
Host smart-9f79e448-c5ac-4ac0-9c8a-c1bab6b3836c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545205234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j
tag_state_post_trans.545205234
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.2388076141
Short name T434
Test name
Test status
Simulation time 171915809 ps
CPU time 2.32 seconds
Started Jul 02 09:40:33 AM PDT 24
Finished Jul 02 09:40:36 AM PDT 24
Peak memory 217776 kb
Host smart-c4fb0f1f-9587-4606-9b81-2abcafe22ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388076141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.2388076141
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.3154205449
Short name T817
Test name
Test status
Simulation time 988931632 ps
CPU time 14.52 seconds
Started Jul 02 09:40:32 AM PDT 24
Finished Jul 02 09:40:48 AM PDT 24
Peak memory 217208 kb
Host smart-c05feabb-e04f-4e7d-b285-69d8e8eb6450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154205449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.3154205449
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.357209574
Short name T491
Test name
Test status
Simulation time 350553645 ps
CPU time 13.51 seconds
Started Jul 02 09:40:37 AM PDT 24
Finished Jul 02 09:40:52 AM PDT 24
Peak memory 218452 kb
Host smart-5e7a6ba6-9980-4e6c-9417-3c432263d8ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357209574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.357209574
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.40891773
Short name T542
Test name
Test status
Simulation time 1583345027 ps
CPU time 9.41 seconds
Started Jul 02 09:40:36 AM PDT 24
Finished Jul 02 09:40:47 AM PDT 24
Peak memory 225528 kb
Host smart-fc3e28ed-b0cf-454c-b164-946fc52f83c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40891773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_dige
st.40891773
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.96557699
Short name T574
Test name
Test status
Simulation time 544764864 ps
CPU time 11.97 seconds
Started Jul 02 09:40:37 AM PDT 24
Finished Jul 02 09:40:50 AM PDT 24
Peak memory 217720 kb
Host smart-f98a4261-1d74-4b90-872b-5d0eef7d5858
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96557699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.96557699
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.2223126258
Short name T607
Test name
Test status
Simulation time 2575035020 ps
CPU time 8.84 seconds
Started Jul 02 09:40:30 AM PDT 24
Finished Jul 02 09:40:41 AM PDT 24
Peak memory 217840 kb
Host smart-cc4d27a0-98d0-41ae-9e6e-23de6a0bac00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223126258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.2223126258
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.696481605
Short name T182
Test name
Test status
Simulation time 85527672 ps
CPU time 1.36 seconds
Started Jul 02 09:40:30 AM PDT 24
Finished Jul 02 09:40:33 AM PDT 24
Peak memory 213340 kb
Host smart-b091d9f8-4b91-4060-adde-f46bb7d8e2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696481605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.696481605
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.1933143939
Short name T858
Test name
Test status
Simulation time 842889103 ps
CPU time 27.87 seconds
Started Jul 02 09:40:33 AM PDT 24
Finished Jul 02 09:41:02 AM PDT 24
Peak memory 250512 kb
Host smart-b3dba5b3-b6a2-4afc-8be0-942ac006ed2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933143939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.1933143939
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.233397664
Short name T728
Test name
Test status
Simulation time 94336893 ps
CPU time 10.18 seconds
Started Jul 02 09:40:36 AM PDT 24
Finished Jul 02 09:40:48 AM PDT 24
Peak memory 250524 kb
Host smart-e19e4bfc-e237-42b1-a8df-7d221ce42210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233397664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.233397664
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.2653548457
Short name T188
Test name
Test status
Simulation time 4094396164 ps
CPU time 89.22 seconds
Started Jul 02 09:40:37 AM PDT 24
Finished Jul 02 09:42:08 AM PDT 24
Peak memory 276980 kb
Host smart-ee8e022f-d8a2-4f2c-8a3c-986fcb34cc17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653548457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.2653548457
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.1344533135
Short name T506
Test name
Test status
Simulation time 46966441 ps
CPU time 0.77 seconds
Started Jul 02 09:40:36 AM PDT 24
Finished Jul 02 09:40:38 AM PDT 24
Peak memory 208372 kb
Host smart-66096124-bdc9-40d9-95e7-95973c713a31
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344533135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.1344533135
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%