Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51436 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T3 |
1 |
auto[1] |
1867 |
1 |
|
|
T13 |
11 |
|
T44 |
12 |
|
T16 |
13 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52682 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T3 |
1 |
auto[1] |
621 |
1 |
|
|
T15 |
12 |
|
T35 |
15 |
|
T65 |
18 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51462 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T3 |
1 |
auto[1] |
1841 |
1 |
|
|
T14 |
7 |
|
T6 |
8 |
|
T47 |
1 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51472 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T3 |
1 |
auto[1] |
1831 |
1 |
|
|
T4 |
1 |
|
T12 |
1 |
|
T14 |
6 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51524 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T3 |
1 |
auto[1] |
1779 |
1 |
|
|
T12 |
2 |
|
T14 |
11 |
|
T6 |
10 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
48535 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T3 |
1 |
no_err_inj |
4768 |
1 |
|
|
T4 |
10 |
|
T12 |
9 |
|
T5 |
6 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51451 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T3 |
1 |
auto[1] |
1852 |
1 |
|
|
T13 |
14 |
|
T44 |
7 |
|
T16 |
14 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52652 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T3 |
1 |
auto[1] |
651 |
1 |
|
|
T15 |
13 |
|
T35 |
10 |
|
T65 |
17 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
36600 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T3 |
1 |
auto[1] |
16703 |
1 |
|
|
T4 |
15 |
|
T5 |
6 |
|
T6 |
90 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51384 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T3 |
1 |
auto[1] |
1919 |
1 |
|
|
T4 |
2 |
|
T12 |
1 |
|
T14 |
14 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51426 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T3 |
1 |
auto[1] |
1877 |
1 |
|
|
T14 |
5 |
|
T6 |
10 |
|
T47 |
1 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51469 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T3 |
1 |
auto[1] |
1834 |
1 |
|
|
T14 |
6 |
|
T6 |
8 |
|
T47 |
1 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51397 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T3 |
1 |
auto[1] |
1906 |
1 |
|
|
T13 |
10 |
|
T44 |
11 |
|
T16 |
24 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50961 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T10 |
55 |
auto[1] |
2342 |
1 |
|
|
T3 |
1 |
|
T11 |
9 |
|
T16 |
12 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52680 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T3 |
1 |
auto[1] |
623 |
1 |
|
|
T15 |
14 |
|
T35 |
16 |
|
T65 |
12 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52626 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T3 |
1 |
auto[1] |
677 |
1 |
|
|
T15 |
12 |
|
T35 |
18 |
|
T65 |
24 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52662 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T3 |
1 |
auto[1] |
641 |
1 |
|
|
T15 |
26 |
|
T35 |
18 |
|
T65 |
21 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50698 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T3 |
1 |
auto[1] |
2605 |
1 |
|
|
T4 |
15 |
|
T12 |
15 |
|
T47 |
15 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49464 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T3 |
1 |
auto[1] |
3839 |
1 |
|
|
T10 |
55 |
|
T60 |
79 |
|
T33 |
90 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51361 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T3 |
1 |
auto[1] |
1942 |
1 |
|
|
T4 |
1 |
|
T14 |
4 |
|
T6 |
10 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51478 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T3 |
1 |
auto[1] |
1825 |
1 |
|
|
T12 |
2 |
|
T14 |
6 |
|
T6 |
12 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51426 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T3 |
1 |
auto[1] |
1877 |
1 |
|
|
T4 |
1 |
|
T14 |
8 |
|
T6 |
13 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51472 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T3 |
1 |
auto[1] |
1831 |
1 |
|
|
T13 |
10 |
|
T44 |
6 |
|
T16 |
23 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47715 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T3 |
1 |
auto[1] |
5588 |
1 |
|
|
T13 |
9 |
|
T46 |
76 |
|
T44 |
5 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49540 |
1 |
|
|
T3 |
1 |
|
T10 |
55 |
|
T4 |
15 |
auto[1] |
3763 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T64 |
68 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53303 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T3 |
1 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51420 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T3 |
1 |
auto[1] |
1883 |
1 |
|
|
T13 |
12 |
|
T44 |
10 |
|
T16 |
19 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51390 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T3 |
1 |
auto[1] |
1913 |
1 |
|
|
T13 |
12 |
|
T44 |
8 |
|
T16 |
22 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51490 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T3 |
1 |
auto[1] |
1813 |
1 |
|
|
T13 |
9 |
|
T44 |
14 |
|
T16 |
23 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
47206 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T3 |
1 |
auto[0] |
no_err_inj |
3492 |
1 |
|
|
T5 |
6 |
|
T16 |
14 |
|
T17 |
25 |
auto[1] |
err_inj |
1329 |
1 |
|
|
T4 |
5 |
|
T12 |
6 |
|
T47 |
7 |
auto[1] |
no_err_inj |
1276 |
1 |
|
|
T4 |
10 |
|
T12 |
9 |
|
T47 |
8 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49044 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T3 |
1 |
auto[0] |
auto[1] |
1654 |
1 |
|
|
T14 |
6 |
|
T6 |
12 |
|
T16 |
28 |
auto[1] |
auto[0] |
2434 |
1 |
|
|
T4 |
15 |
|
T12 |
13 |
|
T47 |
13 |
auto[1] |
auto[1] |
171 |
1 |
|
|
T12 |
2 |
|
T47 |
2 |
|
T34 |
2 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48959 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T3 |
1 |
auto[0] |
auto[1] |
1739 |
1 |
|
|
T14 |
5 |
|
T6 |
10 |
|
T16 |
21 |
auto[1] |
auto[0] |
2467 |
1 |
|
|
T4 |
15 |
|
T12 |
15 |
|
T47 |
14 |
auto[1] |
auto[1] |
138 |
1 |
|
|
T47 |
1 |
|
T17 |
2 |
|
T199 |
2 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48961 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T3 |
1 |
auto[0] |
auto[1] |
1737 |
1 |
|
|
T14 |
8 |
|
T6 |
13 |
|
T16 |
25 |
auto[1] |
auto[0] |
2465 |
1 |
|
|
T4 |
14 |
|
T12 |
15 |
|
T47 |
14 |
auto[1] |
auto[1] |
140 |
1 |
|
|
T4 |
1 |
|
T47 |
1 |
|
T17 |
1 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49018 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T3 |
1 |
auto[0] |
auto[1] |
1680 |
1 |
|
|
T14 |
6 |
|
T6 |
9 |
|
T16 |
30 |
auto[1] |
auto[0] |
2454 |
1 |
|
|
T4 |
14 |
|
T12 |
14 |
|
T47 |
15 |
auto[1] |
auto[1] |
151 |
1 |
|
|
T4 |
1 |
|
T12 |
1 |
|
T17 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49060 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T3 |
1 |
auto[0] |
auto[1] |
1638 |
1 |
|
|
T14 |
11 |
|
T6 |
10 |
|
T16 |
21 |
auto[1] |
auto[0] |
2464 |
1 |
|
|
T4 |
15 |
|
T12 |
13 |
|
T47 |
15 |
auto[1] |
auto[1] |
141 |
1 |
|
|
T12 |
2 |
|
T199 |
1 |
|
T45 |
4 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49005 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T3 |
1 |
auto[0] |
auto[1] |
1693 |
1 |
|
|
T14 |
7 |
|
T6 |
8 |
|
T16 |
29 |
auto[1] |
auto[0] |
2457 |
1 |
|
|
T4 |
15 |
|
T12 |
15 |
|
T47 |
14 |
auto[1] |
auto[1] |
148 |
1 |
|
|
T47 |
1 |
|
T199 |
1 |
|
T34 |
2 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35532 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T3 |
1 |
auto[0] |
auto[1] |
1068 |
1 |
|
|
T13 |
11 |
|
T44 |
12 |
|
T17 |
23 |
auto[1] |
auto[0] |
15904 |
1 |
|
|
T4 |
15 |
|
T5 |
6 |
|
T6 |
90 |
auto[1] |
auto[1] |
799 |
1 |
|
|
T16 |
13 |
|
T17 |
5 |
|
T20 |
10 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35585 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T3 |
1 |
auto[0] |
auto[1] |
1015 |
1 |
|
|
T13 |
14 |
|
T44 |
7 |
|
T17 |
20 |
auto[1] |
auto[0] |
15866 |
1 |
|
|
T4 |
15 |
|
T5 |
6 |
|
T6 |
90 |
auto[1] |
auto[1] |
837 |
1 |
|
|
T16 |
14 |
|
T17 |
7 |
|
T20 |
12 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35261 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T10 |
55 |
auto[0] |
auto[1] |
1339 |
1 |
|
|
T3 |
1 |
|
T11 |
9 |
|
T17 |
30 |
auto[1] |
auto[0] |
15700 |
1 |
|
|
T4 |
15 |
|
T5 |
6 |
|
T6 |
90 |
auto[1] |
auto[1] |
1003 |
1 |
|
|
T16 |
12 |
|
T17 |
6 |
|
T21 |
5 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35530 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T3 |
1 |
auto[0] |
auto[1] |
1070 |
1 |
|
|
T13 |
10 |
|
T44 |
11 |
|
T17 |
23 |
auto[1] |
auto[0] |
15867 |
1 |
|
|
T4 |
15 |
|
T5 |
6 |
|
T6 |
90 |
auto[1] |
auto[1] |
836 |
1 |
|
|
T16 |
24 |
|
T17 |
8 |
|
T20 |
11 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
31835 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T3 |
1 |
auto[0] |
auto[1] |
4765 |
1 |
|
|
T13 |
9 |
|
T46 |
76 |
|
T44 |
5 |
auto[1] |
auto[0] |
15880 |
1 |
|
|
T4 |
15 |
|
T5 |
6 |
|
T6 |
90 |
auto[1] |
auto[1] |
823 |
1 |
|
|
T16 |
16 |
|
T17 |
9 |
|
T20 |
11 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35528 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T3 |
1 |
auto[0] |
auto[1] |
1072 |
1 |
|
|
T12 |
2 |
|
T14 |
6 |
|
T47 |
2 |
auto[1] |
auto[0] |
15950 |
1 |
|
|
T4 |
15 |
|
T5 |
6 |
|
T6 |
78 |
auto[1] |
auto[1] |
753 |
1 |
|
|
T6 |
12 |
|
T16 |
20 |
|
T17 |
14 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35448 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T3 |
1 |
auto[0] |
auto[1] |
1152 |
1 |
|
|
T14 |
4 |
|
T16 |
8 |
|
T87 |
8 |
auto[1] |
auto[0] |
15913 |
1 |
|
|
T4 |
14 |
|
T5 |
6 |
|
T6 |
80 |
auto[1] |
auto[1] |
790 |
1 |
|
|
T4 |
1 |
|
T6 |
10 |
|
T16 |
20 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35494 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T3 |
1 |
auto[0] |
auto[1] |
1106 |
1 |
|
|
T14 |
5 |
|
T47 |
1 |
|
T16 |
9 |
auto[1] |
auto[0] |
15932 |
1 |
|
|
T4 |
15 |
|
T5 |
6 |
|
T6 |
80 |
auto[1] |
auto[1] |
771 |
1 |
|
|
T6 |
10 |
|
T16 |
12 |
|
T17 |
15 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35478 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T3 |
1 |
auto[0] |
auto[1] |
1122 |
1 |
|
|
T12 |
1 |
|
T14 |
14 |
|
T47 |
1 |
auto[1] |
auto[0] |
15906 |
1 |
|
|
T4 |
13 |
|
T5 |
6 |
|
T6 |
80 |
auto[1] |
auto[1] |
797 |
1 |
|
|
T4 |
2 |
|
T6 |
10 |
|
T16 |
18 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35539 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T3 |
1 |
auto[0] |
auto[1] |
1061 |
1 |
|
|
T12 |
1 |
|
T14 |
6 |
|
T16 |
7 |
auto[1] |
auto[0] |
15933 |
1 |
|
|
T4 |
14 |
|
T5 |
6 |
|
T6 |
81 |
auto[1] |
auto[1] |
770 |
1 |
|
|
T4 |
1 |
|
T6 |
9 |
|
T16 |
23 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35545 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T3 |
1 |
auto[0] |
auto[1] |
1055 |
1 |
|
|
T14 |
7 |
|
T47 |
1 |
|
T16 |
7 |
auto[1] |
auto[0] |
15917 |
1 |
|
|
T4 |
15 |
|
T5 |
6 |
|
T6 |
82 |
auto[1] |
auto[1] |
786 |
1 |
|
|
T6 |
8 |
|
T16 |
22 |
|
T17 |
14 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35578 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T3 |
1 |
auto[0] |
auto[1] |
1022 |
1 |
|
|
T13 |
9 |
|
T44 |
14 |
|
T17 |
22 |
auto[1] |
auto[0] |
15912 |
1 |
|
|
T4 |
15 |
|
T5 |
6 |
|
T6 |
90 |
auto[1] |
auto[1] |
791 |
1 |
|
|
T16 |
23 |
|
T17 |
7 |
|
T20 |
10 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35543 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T3 |
1 |
auto[0] |
auto[1] |
1057 |
1 |
|
|
T13 |
12 |
|
T44 |
8 |
|
T17 |
22 |
auto[1] |
auto[0] |
15847 |
1 |
|
|
T4 |
15 |
|
T5 |
6 |
|
T6 |
90 |
auto[1] |
auto[1] |
856 |
1 |
|
|
T16 |
22 |
|
T17 |
13 |
|
T20 |
9 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35068 |
1 |
|
|
T1 |
60 |
|
T2 |
59 |
|
T3 |
1 |
auto[0] |
auto[1] |
1532 |
1 |
|
|
T12 |
15 |
|
T47 |
15 |
|
T199 |
10 |
auto[1] |
auto[0] |
15630 |
1 |
|
|
T5 |
6 |
|
T6 |
90 |
|
T16 |
341 |
auto[1] |
auto[1] |
1073 |
1 |
|
|
T4 |
15 |
|
T17 |
10 |
|
T38 |
24 |