Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

105145206

1

T1

18586

T2

19274

T3

1526

auto[1]

1379170

1

T3

99

T10

8183

T4

294

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

105136651

1

T1

18586

T2

19274

T3

1625

auto[1]

1387725

1

T10

7847

T4

98

T11

396

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7237789	1			T1	5424		T2	5346		T3	170
auto[IdleSt]	23239879	1			T1	2282		T2	1862		T3	1251
auto[ClkMuxSt]	35569	1			T1	60		T2	59		T3	1
auto[CntIncrSt]	35248	1			T1	60		T2	59		T3	1
auto[CntProgSt]	1728938	1			T1	935		T2	1656		T3	17
auto[TransCheckSt]	27303	1			T1	60		T2	59		T10	27
auto[TokenHashSt]	40899720	1			T1	502		T2	1160		T10	1053
auto[FlashRmaSt]	34883	1			T1	48		T2	31		T10	64
auto[TokenCheck0St]	12497	1			T1	19		T2	19		T10	21
auto[TokenCheck1St]	9310	1			T1	6		T2	7		T10	21
auto[TransProgSt]	477245	1			T10	49		T4	20		T12	18
auto[PostTransSt]	13832695	1			T1	9190		T2	9016		T3	59
auto[ScrapSt]	180407	1			T10	3		T5	321		T17	1065
auto[EscalateSt]	6914088	1			T3	126		T10	11633		T4	4740
auto[InvalidSt]	11856876	1			T4	4372		T12	854		T14	7210

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1929	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	11856876	1			T4	4372		T12	854		T14	7210
EscalateSt	6914088	1			T3	126		T10	11633		T4	4740
ScrapSt	180407	1			T10	3		T5	321		T17	1065
PostTransSt	13832695	1			T1	9190		T2	9016		T3	59
TransProgSt	477245	1			T10	49		T4	20		T12	18
TokenCheck1St	9310	1			T1	6		T2	7		T10	21
TokenCheck0St	12497	1			T1	19		T2	19		T10	21
FlashRmaSt	34883	1			T1	48		T2	31		T10	64
TokenHashSt	40899720	1			T1	502		T2	1160		T10	1053
TransCheckSt	27303	1			T1	60		T2	59		T10	27
CntProgSt	1728938	1			T1	935		T2	1656		T3	17
CntIncrSt	35248	1			T1	60		T2	59		T3	1
ClkMuxSt	35569	1			T1	60		T2	59		T3	1
IdleSt	23239879	1			T1	2282		T2	1862		T3	1251
ResetSt	7237789	1			T1	5424		T2	5346		T3	170
arcs[ResetSt=>IdleSt]	53492	1			T1	61		T2	60		T3	2
arcs[IdleSt=>ScrapSt]	304	1			T10	1		T5	1		T17	2
arcs[IdleSt=>ClkMuxSt]	35308	1			T1	60		T2	59		T3	1
arcs[ClkMuxSt=>CntIncrSt]	35248	1			T1	60		T2	59		T3	1
arcs[CntIncrSt=>PostTransSt]	1914	1			T13	12		T44	8		T16	22
arcs[CntIncrSt=>CntProgSt]	33265	1			T1	60		T2	59		T3	1
arcs[CntProgSt=>PostTransSt]	4802	1			T3	1		T11	9		T13	11
arcs[CntProgSt=>TransCheckSt]	27303	1			T1	60		T2	59		T10	27
arcs[TransCheckSt=>PostTransSt]	3739	1			T1	36		T2	32		T13	9
arcs[TransCheckSt=>TokenHashSt]	23450	1			T1	24		T2	27		T10	27
arcs[TokenHashSt=>PostTransSt]	10210	1			T1	5		T2	8		T13	31
arcs[TokenHashSt=>FlashRmaSt]	12591	1			T1	19		T2	19		T10	21
arcs[FlashRmaSt=>TokenCheck0St]	12497	1			T1	19		T2	19		T10	21
arcs[TokenCheck0St=>PostTransSt]	3156	1			T1	13		T2	12		T13	12
arcs[TokenCheck0St=>TokenCheck1St]	9310	1			T1	6		T2	7		T10	21
arcs[TokenCheck1St=>PostTransSt]	641	1			T1	6		T2	7		T13	2
arcs[TransProgSt=>PostTransSt]	7695	1			T10	1		T4	10		T12	9
arcs[IdleSt=>EscalateSt]	175	1			T10	3		T37	1		T61	6
arcs[ClkMuxSt=>EscalateSt]	60	1			T10	1		T33	2		T37	1
arcs[CntIncrSt=>EscalateSt]	69	1			T60	1		T33	4		T36	1
arcs[CntProgSt=>EscalateSt]	1160	1			T10	19		T60	8		T33	34
arcs[TransCheckSt=>EscalateSt]	114	1			T60	6		T36	5		T37	6
arcs[TokenHashSt=>EscalateSt]	649	1			T10	6		T44	1		T60	31
arcs[FlashRmaSt=>EscalateSt]	94	1			T60	2		T33	4		T61	2
arcs[TokenCheck0St=>EscalateSt]	31	1			T60	1		T33	3		T36	1
arcs[TokenCheck1St=>EscalateSt]	157	1			T10	1		T60	2		T33	7
arcs[TransProgSt=>EscalateSt]	817	1			T10	19		T60	10		T33	20
arcs[PostTransSt=>EscalateSt]	5026	1			T3	1		T10	1		T11	9
arcs[InvalidSt=>EscalateSt]	13709	1			T4	4		T12	6		T14	53

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7237619	1			T1	5424		T2	5346		T3	170
auto[0]	auto[IdleSt]	23239758	1			T1	2282		T2	1862		T3	1251
auto[0]	auto[ClkMuxSt]	35528	1			T1	60		T2	59		T3	1
auto[0]	auto[CntIncrSt]	35199	1			T1	60		T2	59		T3	1
auto[0]	auto[CntProgSt]	1728169	1			T1	935		T2	1656		T3	17
auto[0]	auto[TransCheckSt]	27225	1			T1	60		T2	59		T10	27
auto[0]	auto[TokenHashSt]	40899300	1			T1	502		T2	1160		T10	1051
auto[0]	auto[FlashRmaSt]	34825	1			T1	48		T2	31		T10	64
auto[0]	auto[TokenCheck0St]	12479	1			T1	19		T2	19		T10	21
auto[0]	auto[TokenCheck1St]	9204	1			T1	6		T2	7		T10	20
auto[0]	auto[TransProgSt]	476710	1			T10	34		T4	20		T12	18
auto[0]	auto[PostTransSt]	13830158	1			T1	9190		T2	9016		T3	58
auto[0]	auto[ScrapSt]	180345	1			T10	2		T5	321		T17	1065
auto[0]	auto[EscalateSt]	5546704	1			T3	28		T10	3488		T4	4449
auto[0]	auto[InvalidSt]	11850054	1			T4	4369		T12	850		T14	7188
auto[1]	auto[ResetSt]	170	1			T10	4		T60	3		T33	4
auto[1]	auto[IdleSt]	121	1			T10	1		T61	5		T198	6
auto[1]	auto[ClkMuxSt]	41	1			T10	1		T33	2		T37	1
auto[1]	auto[CntIncrSt]	49	1			T60	1		T33	4		T36	1
auto[1]	auto[CntProgSt]	769	1			T10	12		T60	3		T33	21
auto[1]	auto[TransCheckSt]	78	1			T60	2		T36	4		T37	4
auto[1]	auto[TokenHashSt]	420	1			T10	2		T44	1		T60	17
auto[1]	auto[FlashRmaSt]	58	1			T33	1		T61	1		T163	1
auto[1]	auto[TokenCheck0St]	18	1			T60	1		T33	2		T163	1
auto[1]	auto[TokenCheck1St]	106	1			T10	1		T60	2		T33	1
auto[1]	auto[TransProgSt]	535	1			T10	15		T60	5		T33	14
auto[1]	auto[PostTransSt]	2537	1			T3	1		T10	1		T11	5
auto[1]	auto[ScrapSt]	62	1			T10	1		T33	1		T36	2
auto[1]	auto[EscalateSt]	1367384	1			T3	98		T10	8145		T4	291
auto[1]	auto[InvalidSt]	6822	1			T4	3		T12	4		T14	22

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7237626	1			T1	5424		T2	5346		T3	170
auto[0]	auto[IdleSt]	23239773	1			T1	2282		T2	1862		T3	1251
auto[0]	auto[ClkMuxSt]	35535	1			T1	60		T2	59		T3	1
auto[0]	auto[CntIncrSt]	35202	1			T1	60		T2	59		T3	1
auto[0]	auto[CntProgSt]	1728163	1			T1	935		T2	1656		T3	17
auto[0]	auto[TransCheckSt]	27225	1			T1	60		T2	59		T10	27
auto[0]	auto[TokenHashSt]	40899287	1			T1	502		T2	1160		T10	1048
auto[0]	auto[FlashRmaSt]	34809	1			T1	48		T2	31		T10	64
auto[0]	auto[TokenCheck0St]	12480	1			T1	19		T2	19		T10	21
auto[0]	auto[TokenCheck1St]	9211	1			T1	6		T2	7		T10	21
auto[0]	auto[TransProgSt]	476700	1			T10	36		T4	20		T12	18
auto[0]	auto[PostTransSt]	13830144	1			T1	9190		T2	9016		T3	59
auto[0]	auto[ScrapSt]	180354	1			T10	3		T5	321		T17	1065
auto[0]	auto[EscalateSt]	5538224	1			T3	126		T10	3822		T4	4643
auto[0]	auto[InvalidSt]	11849989	1			T4	4371		T12	852		T14	7179
auto[1]	auto[ResetSt]	163	1			T10	3		T60	2		T33	8
auto[1]	auto[IdleSt]	106	1			T10	2		T37	1		T61	4
auto[1]	auto[ClkMuxSt]	34	1			T33	1		T61	2		T163	1
auto[1]	auto[CntIncrSt]	46	1			T60	1		T33	1		T36	1
auto[1]	auto[CntProgSt]	775	1			T10	12		T60	8		T33	23
auto[1]	auto[TransCheckSt]	78	1			T60	5		T36	5		T37	6
auto[1]	auto[TokenHashSt]	433	1			T10	5		T60	24		T33	1
auto[1]	auto[FlashRmaSt]	74	1			T60	2		T33	3		T61	1
auto[1]	auto[TokenCheck0St]	17	1			T33	1		T36	1		T37	1
auto[1]	auto[TokenCheck1St]	99	1			T60	1		T33	7		T36	3
auto[1]	auto[TransProgSt]	545	1			T10	13		T60	6		T33	13
auto[1]	auto[PostTransSt]	2551	1			T10	1		T11	4		T13	6
auto[1]	auto[ScrapSt]	53	1			T60	1		T33	2		T163	3
auto[1]	auto[EscalateSt]	1375864	1			T10	7811		T4	97		T11	392
auto[1]	auto[InvalidSt]	6887	1			T4	1		T12	2		T14	31