Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::sec_token_mux_idx_error_cg
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Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::sec_token_mux_idx_error_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00


Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::sec_token_mux_idx_error_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
fsm_state_q 8 0 8 100.00 100 1 1 0


Summary for Variable fsm_state_q

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for fsm_state_q

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fsm_states[ClkMuxSt] 479 1 T1 10 T2 6 T64 10
fsm_states[CntIncrSt] 490 1 T1 7 T2 8 T64 10
fsm_states[CntProgSt] 461 1 T1 9 T2 9 T64 5
fsm_states[TransCheckSt] 493 1 T1 10 T2 9 T64 7
fsm_states[FlashRmaSt] 442 1 T1 7 T2 6 T64 6
fsm_states[TokenHashSt] 487 1 T1 5 T2 8 T64 12
fsm_states[TokenCheck0St] 448 1 T1 6 T2 6 T64 10
fsm_states[TokenCheck1St] 463 1 T1 6 T2 7 T64 8

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%