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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.88 97.99 95.86 93.38 97.67 98.55 98.76 95.94


Total test records in report: 997
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T811 /workspace/coverage/default/28.lc_ctrl_errors.4098656065 Jul 03 07:13:13 PM PDT 24 Jul 03 07:13:28 PM PDT 24 545410954 ps
T812 /workspace/coverage/default/9.lc_ctrl_prog_failure.2929065690 Jul 03 07:11:33 PM PDT 24 Jul 03 07:12:02 PM PDT 24 196779699 ps
T813 /workspace/coverage/default/37.lc_ctrl_jtag_access.1851132034 Jul 03 07:14:28 PM PDT 24 Jul 03 07:14:42 PM PDT 24 391254661 ps
T814 /workspace/coverage/default/17.lc_ctrl_security_escalation.2734560729 Jul 03 07:12:26 PM PDT 24 Jul 03 07:12:40 PM PDT 24 1020367437 ps
T815 /workspace/coverage/default/10.lc_ctrl_jtag_errors.2844800244 Jul 03 07:11:52 PM PDT 24 Jul 03 07:12:53 PM PDT 24 2578000726 ps
T816 /workspace/coverage/default/1.lc_ctrl_prog_failure.4033053365 Jul 03 07:10:32 PM PDT 24 Jul 03 07:11:03 PM PDT 24 135868030 ps
T817 /workspace/coverage/default/16.lc_ctrl_alert_test.1059914658 Jul 03 07:12:22 PM PDT 24 Jul 03 07:12:31 PM PDT 24 144131964 ps
T818 /workspace/coverage/default/49.lc_ctrl_alert_test.3255985941 Jul 03 07:15:01 PM PDT 24 Jul 03 07:15:08 PM PDT 24 468850966 ps
T819 /workspace/coverage/default/21.lc_ctrl_errors.534335277 Jul 03 07:12:46 PM PDT 24 Jul 03 07:13:01 PM PDT 24 640845547 ps
T820 /workspace/coverage/default/40.lc_ctrl_state_failure.3100098559 Jul 03 07:14:33 PM PDT 24 Jul 03 07:15:03 PM PDT 24 900069234 ps
T821 /workspace/coverage/default/1.lc_ctrl_state_post_trans.227612844 Jul 03 07:10:31 PM PDT 24 Jul 03 07:11:08 PM PDT 24 120684432 ps
T822 /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.2964445487 Jul 03 07:10:55 PM PDT 24 Jul 03 07:12:22 PM PDT 24 1348988380 ps
T823 /workspace/coverage/default/46.lc_ctrl_sec_token_digest.1829069660 Jul 03 07:14:56 PM PDT 24 Jul 03 07:15:10 PM PDT 24 977946956 ps
T824 /workspace/coverage/default/6.lc_ctrl_alert_test.2851867449 Jul 03 07:11:15 PM PDT 24 Jul 03 07:11:47 PM PDT 24 26637219 ps
T59 /workspace/coverage/default/15.lc_ctrl_stress_all.1168177875 Jul 03 07:12:18 PM PDT 24 Jul 03 07:19:00 PM PDT 24 100326071241 ps
T825 /workspace/coverage/default/4.lc_ctrl_sec_token_digest.1972415493 Jul 03 07:10:55 PM PDT 24 Jul 03 07:11:40 PM PDT 24 402467292 ps
T826 /workspace/coverage/default/8.lc_ctrl_jtag_access.557238423 Jul 03 07:11:23 PM PDT 24 Jul 03 07:12:03 PM PDT 24 4833433841 ps
T827 /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.3299446045 Jul 03 07:13:04 PM PDT 24 Jul 03 07:13:06 PM PDT 24 30874066 ps
T828 /workspace/coverage/default/3.lc_ctrl_jtag_access.736674162 Jul 03 07:10:52 PM PDT 24 Jul 03 07:11:27 PM PDT 24 239660230 ps
T829 /workspace/coverage/default/33.lc_ctrl_jtag_access.3524825328 Jul 03 07:14:14 PM PDT 24 Jul 03 07:14:23 PM PDT 24 553577392 ps
T830 /workspace/coverage/default/0.lc_ctrl_sec_mubi.3226493482 Jul 03 07:10:25 PM PDT 24 Jul 03 07:11:17 PM PDT 24 4684824275 ps
T831 /workspace/coverage/default/8.lc_ctrl_prog_failure.3357151703 Jul 03 07:11:26 PM PDT 24 Jul 03 07:11:58 PM PDT 24 143528776 ps
T832 /workspace/coverage/default/2.lc_ctrl_stress_all.1560911822 Jul 03 07:10:48 PM PDT 24 Jul 03 07:12:37 PM PDT 24 15951681561 ps
T833 /workspace/coverage/default/14.lc_ctrl_sec_mubi.143143038 Jul 03 07:12:12 PM PDT 24 Jul 03 07:12:39 PM PDT 24 361609527 ps
T834 /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.2925161769 Jul 03 07:12:19 PM PDT 24 Jul 03 07:12:33 PM PDT 24 319591472 ps
T835 /workspace/coverage/default/6.lc_ctrl_jtag_errors.628031917 Jul 03 07:11:17 PM PDT 24 Jul 03 07:13:25 PM PDT 24 3663480719 ps
T836 /workspace/coverage/default/6.lc_ctrl_errors.1045909047 Jul 03 07:11:12 PM PDT 24 Jul 03 07:11:59 PM PDT 24 591770948 ps
T837 /workspace/coverage/default/40.lc_ctrl_smoke.90017767 Jul 03 07:14:33 PM PDT 24 Jul 03 07:14:38 PM PDT 24 75863595 ps
T838 /workspace/coverage/default/10.lc_ctrl_state_post_trans.3557314369 Jul 03 07:11:43 PM PDT 24 Jul 03 07:12:09 PM PDT 24 991960063 ps
T839 /workspace/coverage/default/27.lc_ctrl_sec_token_mux.2896722790 Jul 03 07:13:15 PM PDT 24 Jul 03 07:13:22 PM PDT 24 228298333 ps
T840 /workspace/coverage/default/0.lc_ctrl_regwen_during_op.333191412 Jul 03 07:10:18 PM PDT 24 Jul 03 07:10:52 PM PDT 24 232125638 ps
T841 /workspace/coverage/default/47.lc_ctrl_sec_token_digest.4210235571 Jul 03 07:14:59 PM PDT 24 Jul 03 07:15:17 PM PDT 24 1377494502 ps
T842 /workspace/coverage/default/42.lc_ctrl_state_failure.1992398133 Jul 03 07:14:35 PM PDT 24 Jul 03 07:14:58 PM PDT 24 319112280 ps
T843 /workspace/coverage/default/37.lc_ctrl_smoke.1331132880 Jul 03 07:14:22 PM PDT 24 Jul 03 07:14:29 PM PDT 24 386985213 ps
T155 /workspace/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.171538577 Jul 03 07:14:31 PM PDT 24 Jul 03 07:21:07 PM PDT 24 57792855543 ps
T844 /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.3979287494 Jul 03 07:14:13 PM PDT 24 Jul 03 07:14:16 PM PDT 24 14129113 ps
T845 /workspace/coverage/default/35.lc_ctrl_jtag_access.3204756535 Jul 03 07:14:22 PM PDT 24 Jul 03 07:14:34 PM PDT 24 438692101 ps
T846 /workspace/coverage/default/32.lc_ctrl_stress_all.3669750356 Jul 03 07:14:11 PM PDT 24 Jul 03 07:14:48 PM PDT 24 6383664534 ps
T847 /workspace/coverage/default/14.lc_ctrl_security_escalation.449191463 Jul 03 07:12:11 PM PDT 24 Jul 03 07:12:30 PM PDT 24 1037053933 ps
T848 /workspace/coverage/default/25.lc_ctrl_state_post_trans.4076855917 Jul 03 07:13:00 PM PDT 24 Jul 03 07:13:07 PM PDT 24 76789338 ps
T849 /workspace/coverage/default/39.lc_ctrl_state_post_trans.96553642 Jul 03 07:14:28 PM PDT 24 Jul 03 07:14:39 PM PDT 24 160798902 ps
T850 /workspace/coverage/default/26.lc_ctrl_security_escalation.3181272884 Jul 03 07:13:04 PM PDT 24 Jul 03 07:13:15 PM PDT 24 411902245 ps
T851 /workspace/coverage/default/9.lc_ctrl_smoke.1398862944 Jul 03 07:11:34 PM PDT 24 Jul 03 07:12:02 PM PDT 24 191021216 ps
T852 /workspace/coverage/default/2.lc_ctrl_sec_token_mux.4079284213 Jul 03 07:10:43 PM PDT 24 Jul 03 07:11:31 PM PDT 24 1348570802 ps
T853 /workspace/coverage/default/33.lc_ctrl_sec_mubi.2352374618 Jul 03 07:14:11 PM PDT 24 Jul 03 07:14:24 PM PDT 24 295974113 ps
T854 /workspace/coverage/default/3.lc_ctrl_security_escalation.3710695562 Jul 03 07:10:47 PM PDT 24 Jul 03 07:11:28 PM PDT 24 550201097 ps
T167 /workspace/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.1467047474 Jul 03 07:11:57 PM PDT 24 Jul 03 07:16:41 PM PDT 24 11579500239 ps
T855 /workspace/coverage/default/24.lc_ctrl_sec_token_digest.2329009417 Jul 03 07:12:59 PM PDT 24 Jul 03 07:13:14 PM PDT 24 1222286364 ps
T856 /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2970260088 Jul 03 07:12:49 PM PDT 24 Jul 03 07:12:51 PM PDT 24 28133453 ps
T857 /workspace/coverage/default/28.lc_ctrl_state_failure.2211212588 Jul 03 07:13:17 PM PDT 24 Jul 03 07:13:46 PM PDT 24 293111330 ps
T858 /workspace/coverage/default/44.lc_ctrl_alert_test.3274082864 Jul 03 07:14:49 PM PDT 24 Jul 03 07:14:52 PM PDT 24 17953545 ps
T859 /workspace/coverage/default/44.lc_ctrl_stress_all.4125787116 Jul 03 07:14:47 PM PDT 24 Jul 03 07:19:50 PM PDT 24 8102843630 ps
T860 /workspace/coverage/default/17.lc_ctrl_smoke.3970788456 Jul 03 07:12:22 PM PDT 24 Jul 03 07:12:34 PM PDT 24 74111880 ps
T861 /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.3149048305 Jul 03 07:12:17 PM PDT 24 Jul 03 07:12:27 PM PDT 24 27090432 ps
T862 /workspace/coverage/default/41.lc_ctrl_sec_token_digest.2166603866 Jul 03 07:14:35 PM PDT 24 Jul 03 07:14:52 PM PDT 24 614878943 ps
T863 /workspace/coverage/default/42.lc_ctrl_errors.1903336860 Jul 03 07:14:33 PM PDT 24 Jul 03 07:14:53 PM PDT 24 781442882 ps
T864 /workspace/coverage/default/17.lc_ctrl_jtag_smoke.912242636 Jul 03 07:12:24 PM PDT 24 Jul 03 07:12:35 PM PDT 24 365785037 ps
T865 /workspace/coverage/default/49.lc_ctrl_jtag_access.450081690 Jul 03 07:14:58 PM PDT 24 Jul 03 07:15:04 PM PDT 24 354889001 ps
T866 /workspace/coverage/default/20.lc_ctrl_errors.1263295678 Jul 03 07:12:40 PM PDT 24 Jul 03 07:12:51 PM PDT 24 657173246 ps
T867 /workspace/coverage/default/35.lc_ctrl_smoke.3807007204 Jul 03 07:14:14 PM PDT 24 Jul 03 07:14:20 PM PDT 24 76761386 ps
T868 /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.1175685569 Jul 03 07:10:33 PM PDT 24 Jul 03 07:11:13 PM PDT 24 730587317 ps
T869 /workspace/coverage/default/3.lc_ctrl_sec_token_digest.2157298473 Jul 03 07:10:53 PM PDT 24 Jul 03 07:11:35 PM PDT 24 1176237316 ps
T113 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.22946158 Jul 03 07:19:06 PM PDT 24 Jul 03 07:19:14 PM PDT 24 65484885 ps
T119 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1728783238 Jul 03 07:19:03 PM PDT 24 Jul 03 07:19:10 PM PDT 24 103761208 ps
T120 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2675086134 Jul 03 07:19:22 PM PDT 24 Jul 03 07:19:29 PM PDT 24 870333293 ps
T143 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1681952011 Jul 03 07:19:09 PM PDT 24 Jul 03 07:19:18 PM PDT 24 63950365 ps
T114 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.4032831909 Jul 03 07:19:16 PM PDT 24 Jul 03 07:19:25 PM PDT 24 83989502 ps
T870 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2674612845 Jul 03 07:19:08 PM PDT 24 Jul 03 07:19:16 PM PDT 24 18885382 ps
T156 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2988903883 Jul 03 07:19:05 PM PDT 24 Jul 03 07:19:11 PM PDT 24 45859890 ps
T144 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1507425032 Jul 03 07:19:10 PM PDT 24 Jul 03 07:19:20 PM PDT 24 1472614533 ps
T146 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2423273946 Jul 03 07:19:11 PM PDT 24 Jul 03 07:19:24 PM PDT 24 1226489343 ps
T871 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.706764153 Jul 03 07:19:06 PM PDT 24 Jul 03 07:19:13 PM PDT 24 342988796 ps
T872 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.275757490 Jul 03 07:19:12 PM PDT 24 Jul 03 07:19:21 PM PDT 24 84632047 ps
T115 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.969556912 Jul 03 07:19:29 PM PDT 24 Jul 03 07:19:35 PM PDT 24 35017682 ps
T145 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1714884941 Jul 03 07:19:17 PM PDT 24 Jul 03 07:19:27 PM PDT 24 1460513915 ps
T873 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.328375145 Jul 03 07:19:16 PM PDT 24 Jul 03 07:19:28 PM PDT 24 485169889 ps
T157 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3862152998 Jul 03 07:19:19 PM PDT 24 Jul 03 07:19:27 PM PDT 24 94515149 ps
T874 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3992407057 Jul 03 07:19:18 PM PDT 24 Jul 03 07:19:25 PM PDT 24 121105667 ps
T158 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1071435708 Jul 03 07:19:01 PM PDT 24 Jul 03 07:19:07 PM PDT 24 90426224 ps
T159 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.897720112 Jul 03 07:18:57 PM PDT 24 Jul 03 07:19:05 PM PDT 24 92749438 ps
T116 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3616713845 Jul 03 07:19:29 PM PDT 24 Jul 03 07:19:36 PM PDT 24 210403749 ps
T190 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3926086763 Jul 03 07:19:07 PM PDT 24 Jul 03 07:19:15 PM PDT 24 36167085 ps
T172 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.145481969 Jul 03 07:19:09 PM PDT 24 Jul 03 07:19:19 PM PDT 24 112967960 ps
T191 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.716776539 Jul 03 07:19:03 PM PDT 24 Jul 03 07:19:09 PM PDT 24 30219621 ps
T177 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3045248460 Jul 03 07:19:15 PM PDT 24 Jul 03 07:19:23 PM PDT 24 13767490 ps
T117 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2139412679 Jul 03 07:19:23 PM PDT 24 Jul 03 07:19:31 PM PDT 24 98092073 ps
T192 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.1827981387 Jul 03 07:19:16 PM PDT 24 Jul 03 07:19:25 PM PDT 24 53617679 ps
T875 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2852330010 Jul 03 07:19:11 PM PDT 24 Jul 03 07:19:22 PM PDT 24 967404381 ps
T876 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2882785131 Jul 03 07:19:17 PM PDT 24 Jul 03 07:19:31 PM PDT 24 1321882672 ps
T193 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2614893638 Jul 03 07:19:27 PM PDT 24 Jul 03 07:19:33 PM PDT 24 101553840 ps
T178 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3154693864 Jul 03 07:19:23 PM PDT 24 Jul 03 07:19:30 PM PDT 24 23925339 ps
T194 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.759280716 Jul 03 07:19:11 PM PDT 24 Jul 03 07:19:21 PM PDT 24 144083368 ps
T136 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3532495115 Jul 03 07:19:25 PM PDT 24 Jul 03 07:19:33 PM PDT 24 62927898 ps
T877 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.2634513447 Jul 03 07:19:13 PM PDT 24 Jul 03 07:19:42 PM PDT 24 2902371765 ps
T195 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.144412802 Jul 03 07:19:03 PM PDT 24 Jul 03 07:19:10 PM PDT 24 680778565 ps
T878 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1262094671 Jul 03 07:19:27 PM PDT 24 Jul 03 07:19:34 PM PDT 24 58654074 ps
T879 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2238142878 Jul 03 07:19:12 PM PDT 24 Jul 03 07:19:22 PM PDT 24 75517529 ps
T880 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3248823206 Jul 03 07:19:11 PM PDT 24 Jul 03 07:19:56 PM PDT 24 6432889453 ps
T881 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.40602878 Jul 03 07:19:13 PM PDT 24 Jul 03 07:19:23 PM PDT 24 148461414 ps
T118 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2705297761 Jul 03 07:19:24 PM PDT 24 Jul 03 07:19:31 PM PDT 24 143678109 ps
T882 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1439963034 Jul 03 07:19:02 PM PDT 24 Jul 03 07:19:09 PM PDT 24 25172291 ps
T123 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1145218010 Jul 03 07:19:06 PM PDT 24 Jul 03 07:19:17 PM PDT 24 150865358 ps
T179 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2948573210 Jul 03 07:18:57 PM PDT 24 Jul 03 07:19:04 PM PDT 24 108493265 ps
T125 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1246489548 Jul 03 07:19:20 PM PDT 24 Jul 03 07:19:28 PM PDT 24 29785821 ps
T883 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.422716561 Jul 03 07:19:10 PM PDT 24 Jul 03 07:19:22 PM PDT 24 113845090 ps
T884 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2756240920 Jul 03 07:19:00 PM PDT 24 Jul 03 07:19:07 PM PDT 24 198568502 ps
T885 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2122286591 Jul 03 07:18:59 PM PDT 24 Jul 03 07:19:06 PM PDT 24 126454255 ps
T886 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1441793676 Jul 03 07:19:22 PM PDT 24 Jul 03 07:19:29 PM PDT 24 57735365 ps
T887 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.4124915565 Jul 03 07:19:13 PM PDT 24 Jul 03 07:19:22 PM PDT 24 62013479 ps
T888 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3604716358 Jul 03 07:19:29 PM PDT 24 Jul 03 07:19:35 PM PDT 24 69035898 ps
T889 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1559361094 Jul 03 07:19:22 PM PDT 24 Jul 03 07:19:29 PM PDT 24 137858815 ps
T890 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.50644479 Jul 03 07:19:09 PM PDT 24 Jul 03 07:19:28 PM PDT 24 1779892821 ps
T891 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1096326306 Jul 03 07:19:09 PM PDT 24 Jul 03 07:19:18 PM PDT 24 26648992 ps
T892 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.194554468 Jul 03 07:19:22 PM PDT 24 Jul 03 07:19:28 PM PDT 24 55319236 ps
T121 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3088918607 Jul 03 07:19:02 PM PDT 24 Jul 03 07:19:11 PM PDT 24 462840416 ps
T138 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.492722121 Jul 03 07:19:30 PM PDT 24 Jul 03 07:19:38 PM PDT 24 512305992 ps
T180 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2181925909 Jul 03 07:19:06 PM PDT 24 Jul 03 07:19:13 PM PDT 24 39578259 ps
T893 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.1223702131 Jul 03 07:19:27 PM PDT 24 Jul 03 07:19:33 PM PDT 24 191273635 ps
T894 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1577292306 Jul 03 07:19:22 PM PDT 24 Jul 03 07:19:28 PM PDT 24 24488421 ps
T895 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1979063408 Jul 03 07:18:57 PM PDT 24 Jul 03 07:19:04 PM PDT 24 27227335 ps
T896 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1383892167 Jul 03 07:19:25 PM PDT 24 Jul 03 07:19:33 PM PDT 24 25729234 ps
T124 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2188328555 Jul 03 07:19:04 PM PDT 24 Jul 03 07:19:10 PM PDT 24 64996634 ps
T897 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1446376215 Jul 03 07:19:02 PM PDT 24 Jul 03 07:19:17 PM PDT 24 2010402530 ps
T181 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1793651548 Jul 03 07:19:27 PM PDT 24 Jul 03 07:19:33 PM PDT 24 36948123 ps
T132 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3002544301 Jul 03 07:19:27 PM PDT 24 Jul 03 07:19:37 PM PDT 24 119262487 ps
T898 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2452892685 Jul 03 07:19:08 PM PDT 24 Jul 03 07:19:30 PM PDT 24 676559622 ps
T182 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1817302958 Jul 03 07:19:18 PM PDT 24 Jul 03 07:19:25 PM PDT 24 27127677 ps
T899 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1965771909 Jul 03 07:18:56 PM PDT 24 Jul 03 07:19:03 PM PDT 24 296781407 ps
T900 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3528471408 Jul 03 07:19:01 PM PDT 24 Jul 03 07:19:11 PM PDT 24 878267754 ps
T901 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1635777767 Jul 03 07:19:04 PM PDT 24 Jul 03 07:19:13 PM PDT 24 287179704 ps
T133 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1414231800 Jul 03 07:19:13 PM PDT 24 Jul 03 07:19:23 PM PDT 24 143604434 ps
T902 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.2879470857 Jul 03 07:19:19 PM PDT 24 Jul 03 07:19:29 PM PDT 24 170867020 ps
T903 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1072931410 Jul 03 07:19:25 PM PDT 24 Jul 03 07:19:31 PM PDT 24 14310495 ps
T904 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.219161122 Jul 03 07:19:03 PM PDT 24 Jul 03 07:19:10 PM PDT 24 117807175 ps
T905 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2211505585 Jul 03 07:19:29 PM PDT 24 Jul 03 07:19:35 PM PDT 24 163394170 ps
T906 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1698619759 Jul 03 07:19:01 PM PDT 24 Jul 03 07:19:08 PM PDT 24 542803880 ps
T126 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3066726734 Jul 03 07:19:27 PM PDT 24 Jul 03 07:19:35 PM PDT 24 232891280 ps
T907 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1783518526 Jul 03 07:18:52 PM PDT 24 Jul 03 07:19:02 PM PDT 24 230032157 ps
T908 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1874549709 Jul 03 07:19:09 PM PDT 24 Jul 03 07:19:18 PM PDT 24 242157303 ps
T129 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1510905217 Jul 03 07:19:25 PM PDT 24 Jul 03 07:19:32 PM PDT 24 86045676 ps
T909 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.207805130 Jul 03 07:19:22 PM PDT 24 Jul 03 07:19:29 PM PDT 24 30150104 ps
T910 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.4286204318 Jul 03 07:19:18 PM PDT 24 Jul 03 07:19:27 PM PDT 24 811578068 ps
T911 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1913405115 Jul 03 07:18:58 PM PDT 24 Jul 03 07:19:06 PM PDT 24 668212631 ps
T912 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.85945531 Jul 03 07:19:04 PM PDT 24 Jul 03 07:19:10 PM PDT 24 47397764 ps
T183 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2443880299 Jul 03 07:19:20 PM PDT 24 Jul 03 07:19:27 PM PDT 24 97515801 ps
T913 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3348847631 Jul 03 07:19:07 PM PDT 24 Jul 03 07:19:14 PM PDT 24 170193547 ps
T914 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.4154058846 Jul 03 07:18:59 PM PDT 24 Jul 03 07:19:11 PM PDT 24 1322405614 ps
T915 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3244366417 Jul 03 07:19:13 PM PDT 24 Jul 03 07:19:22 PM PDT 24 207626474 ps
T916 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2168873484 Jul 03 07:19:27 PM PDT 24 Jul 03 07:19:34 PM PDT 24 14786370 ps
T917 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1936843363 Jul 03 07:19:27 PM PDT 24 Jul 03 07:19:33 PM PDT 24 17012005 ps
T184 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.642362215 Jul 03 07:19:24 PM PDT 24 Jul 03 07:19:30 PM PDT 24 19145906 ps
T918 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1364674324 Jul 03 07:18:57 PM PDT 24 Jul 03 07:19:05 PM PDT 24 158557999 ps
T130 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.4113967788 Jul 03 07:19:15 PM PDT 24 Jul 03 07:19:25 PM PDT 24 75741767 ps
T140 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1605246134 Jul 03 07:19:25 PM PDT 24 Jul 03 07:19:33 PM PDT 24 429893516 ps
T919 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.1599048906 Jul 03 07:19:27 PM PDT 24 Jul 03 07:19:34 PM PDT 24 48400309 ps
T920 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.720307266 Jul 03 07:19:12 PM PDT 24 Jul 03 07:19:22 PM PDT 24 15738205 ps
T921 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.40149104 Jul 03 07:18:57 PM PDT 24 Jul 03 07:19:04 PM PDT 24 226549424 ps
T185 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3574325227 Jul 03 07:19:00 PM PDT 24 Jul 03 07:19:07 PM PDT 24 12442667 ps
T922 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.717801060 Jul 03 07:19:13 PM PDT 24 Jul 03 07:19:22 PM PDT 24 17014820 ps
T923 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3216137187 Jul 03 07:19:06 PM PDT 24 Jul 03 07:19:15 PM PDT 24 1078530188 ps
T924 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.47004326 Jul 03 07:18:58 PM PDT 24 Jul 03 07:19:05 PM PDT 24 33439138 ps
T925 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1179114397 Jul 03 07:19:25 PM PDT 24 Jul 03 07:19:32 PM PDT 24 27181891 ps
T127 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3680666751 Jul 03 07:19:19 PM PDT 24 Jul 03 07:19:28 PM PDT 24 111613229 ps
T186 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2691841548 Jul 03 07:19:23 PM PDT 24 Jul 03 07:19:29 PM PDT 24 126290427 ps
T926 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2970899658 Jul 03 07:19:16 PM PDT 24 Jul 03 07:19:29 PM PDT 24 4449301559 ps
T927 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1242276277 Jul 03 07:19:08 PM PDT 24 Jul 03 07:19:17 PM PDT 24 483219005 ps
T928 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2410419888 Jul 03 07:19:27 PM PDT 24 Jul 03 07:19:35 PM PDT 24 100312486 ps
T929 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1589717963 Jul 03 07:19:08 PM PDT 24 Jul 03 07:19:20 PM PDT 24 604001578 ps
T930 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.414274694 Jul 03 07:19:29 PM PDT 24 Jul 03 07:19:38 PM PDT 24 993690111 ps
T931 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3584240188 Jul 03 07:19:14 PM PDT 24 Jul 03 07:19:23 PM PDT 24 21412396 ps
T187 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2255157425 Jul 03 07:19:00 PM PDT 24 Jul 03 07:19:07 PM PDT 24 51724870 ps
T932 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2736700684 Jul 03 07:19:08 PM PDT 24 Jul 03 07:19:17 PM PDT 24 59967462 ps
T933 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.4235540506 Jul 03 07:19:21 PM PDT 24 Jul 03 07:19:33 PM PDT 24 623966292 ps
T934 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1537061750 Jul 03 07:19:21 PM PDT 24 Jul 03 07:19:28 PM PDT 24 101388541 ps
T935 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1281955938 Jul 03 07:19:12 PM PDT 24 Jul 03 07:19:23 PM PDT 24 416816858 ps
T936 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1014963545 Jul 03 07:19:06 PM PDT 24 Jul 03 07:19:14 PM PDT 24 56778487 ps
T937 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3903164957 Jul 03 07:18:58 PM PDT 24 Jul 03 07:19:06 PM PDT 24 64259834 ps
T135 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.692206011 Jul 03 07:19:29 PM PDT 24 Jul 03 07:19:36 PM PDT 24 53038298 ps
T938 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.224841270 Jul 03 07:19:05 PM PDT 24 Jul 03 07:19:15 PM PDT 24 160297268 ps
T939 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.490772043 Jul 03 07:19:25 PM PDT 24 Jul 03 07:19:31 PM PDT 24 23744486 ps
T141 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3307476909 Jul 03 07:19:07 PM PDT 24 Jul 03 07:19:16 PM PDT 24 62050691 ps
T940 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.4187737924 Jul 03 07:19:22 PM PDT 24 Jul 03 07:19:29 PM PDT 24 290832803 ps
T941 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1182583984 Jul 03 07:18:57 PM PDT 24 Jul 03 07:19:05 PM PDT 24 102322701 ps
T942 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3742795255 Jul 03 07:18:57 PM PDT 24 Jul 03 07:19:04 PM PDT 24 57825424 ps
T943 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1380865638 Jul 03 07:19:22 PM PDT 24 Jul 03 07:19:31 PM PDT 24 158063247 ps
T944 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.4165786085 Jul 03 07:19:01 PM PDT 24 Jul 03 07:19:09 PM PDT 24 325997427 ps
T945 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.996983769 Jul 03 07:19:10 PM PDT 24 Jul 03 07:19:19 PM PDT 24 147761561 ps
T946 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1553519169 Jul 03 07:18:56 PM PDT 24 Jul 03 07:19:02 PM PDT 24 48574450 ps
T947 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3075511252 Jul 03 07:19:17 PM PDT 24 Jul 03 07:19:26 PM PDT 24 34683407 ps
T948 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2428702134 Jul 03 07:18:57 PM PDT 24 Jul 03 07:19:04 PM PDT 24 45202902 ps
T949 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3139344181 Jul 03 07:19:05 PM PDT 24 Jul 03 07:19:12 PM PDT 24 73690907 ps
T137 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2340524630 Jul 03 07:19:08 PM PDT 24 Jul 03 07:19:18 PM PDT 24 387270215 ps
T950 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2407832750 Jul 03 07:19:08 PM PDT 24 Jul 03 07:19:16 PM PDT 24 187573916 ps
T951 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.109790476 Jul 03 07:19:03 PM PDT 24 Jul 03 07:19:10 PM PDT 24 46626890 ps
T134 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3041738895 Jul 03 07:19:04 PM PDT 24 Jul 03 07:19:12 PM PDT 24 311518273 ps
T952 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2572524130 Jul 03 07:19:16 PM PDT 24 Jul 03 07:19:25 PM PDT 24 89180404 ps
T953 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3182054846 Jul 03 07:19:24 PM PDT 24 Jul 03 07:19:30 PM PDT 24 42241316 ps
T128 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3460748136 Jul 03 07:19:22 PM PDT 24 Jul 03 07:19:30 PM PDT 24 93435767 ps
T954 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2780670265 Jul 03 07:19:09 PM PDT 24 Jul 03 07:19:18 PM PDT 24 145729144 ps
T955 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.486937534 Jul 03 07:19:12 PM PDT 24 Jul 03 07:19:22 PM PDT 24 29283555 ps
T122 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.4229876539 Jul 03 07:18:58 PM PDT 24 Jul 03 07:19:06 PM PDT 24 137378793 ps
T956 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3015915918 Jul 03 07:19:04 PM PDT 24 Jul 03 07:19:11 PM PDT 24 335415769 ps
T957 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1403442717 Jul 03 07:19:21 PM PDT 24 Jul 03 07:19:30 PM PDT 24 175787596 ps
T958 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3609008355 Jul 03 07:19:08 PM PDT 24 Jul 03 07:19:17 PM PDT 24 24653715 ps
T959 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2749626209 Jul 03 07:19:21 PM PDT 24 Jul 03 07:19:28 PM PDT 24 64556925 ps
T960 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.4286509596 Jul 03 07:19:19 PM PDT 24 Jul 03 07:19:26 PM PDT 24 35384142 ps
T961 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.860132371 Jul 03 07:18:58 PM PDT 24 Jul 03 07:19:08 PM PDT 24 1031007129 ps
T962 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2225731674 Jul 03 07:19:04 PM PDT 24 Jul 03 07:19:11 PM PDT 24 37094524 ps
T963 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2463356198 Jul 03 07:19:13 PM PDT 24 Jul 03 07:19:24 PM PDT 24 487296073 ps
T964 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.859235108 Jul 03 07:19:12 PM PDT 24 Jul 03 07:19:21 PM PDT 24 170067031 ps
T965 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.960904762 Jul 03 07:19:13 PM PDT 24 Jul 03 07:19:24 PM PDT 24 248153691 ps
T139 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2534703622 Jul 03 07:19:23 PM PDT 24 Jul 03 07:19:30 PM PDT 24 147834448 ps
T142 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2530556387 Jul 03 07:19:24 PM PDT 24 Jul 03 07:19:33 PM PDT 24 88210162 ps
T966 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3834929146 Jul 03 07:19:22 PM PDT 24 Jul 03 07:19:31 PM PDT 24 218169209 ps
T188 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.4175325047 Jul 03 07:19:05 PM PDT 24 Jul 03 07:19:11 PM PDT 24 33463101 ps
T189 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.637070033 Jul 03 07:18:57 PM PDT 24 Jul 03 07:19:04 PM PDT 24 27875700 ps
T967 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3400516568 Jul 03 07:19:08 PM PDT 24 Jul 03 07:19:15 PM PDT 24 38345442 ps
T968 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3919928635 Jul 03 07:19:12 PM PDT 24 Jul 03 07:19:37 PM PDT 24 2407792932 ps
T969 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2644965669 Jul 03 07:19:24 PM PDT 24 Jul 03 07:19:31 PM PDT 24 60997303 ps
T970 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1554187325 Jul 03 07:19:17 PM PDT 24 Jul 03 07:19:25 PM PDT 24 11780375 ps
T971 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1132997743 Jul 03 07:19:05 PM PDT 24 Jul 03 07:19:11 PM PDT 24 60708891 ps
T972 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.624653654 Jul 03 07:19:03 PM PDT 24 Jul 03 07:19:09 PM PDT 24 119949548 ps
T973 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2154789552 Jul 03 07:18:59 PM PDT 24 Jul 03 07:19:06 PM PDT 24 692163932 ps
T974 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.501900224 Jul 03 07:18:55 PM PDT 24 Jul 03 07:19:01 PM PDT 24 212565908 ps
T975 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1008016511 Jul 03 07:18:57 PM PDT 24 Jul 03 07:19:04 PM PDT 24 122525393 ps
T976 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.4217560898 Jul 03 07:19:07 PM PDT 24 Jul 03 07:19:15 PM PDT 24 187407885 ps
T977 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1278393094 Jul 03 07:19:11 PM PDT 24 Jul 03 07:19:21 PM PDT 24 21374907 ps
T978 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2131952989 Jul 03 07:19:22 PM PDT 24 Jul 03 07:19:29 PM PDT 24 70127622 ps
T979 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3437818005 Jul 03 07:19:10 PM PDT 24 Jul 03 07:19:20 PM PDT 24 238075947 ps
T980 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1890199354 Jul 03 07:19:13 PM PDT 24 Jul 03 07:19:25 PM PDT 24 119374459 ps
T981 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.2790287877 Jul 03 07:19:05 PM PDT 24 Jul 03 07:19:14 PM PDT 24 408710513 ps
T982 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3699986836 Jul 03 07:19:06 PM PDT 24 Jul 03 07:19:13 PM PDT 24 49804473 ps
T983 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1582416230 Jul 03 07:19:00 PM PDT 24 Jul 03 07:19:08 PM PDT 24 46750618 ps
T984 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1398209023 Jul 03 07:19:09 PM PDT 24 Jul 03 07:19:20 PM PDT 24 204936944 ps
T985 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.554719564 Jul 03 07:19:11 PM PDT 24 Jul 03 07:19:21 PM PDT 24 16570812 ps
T986 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.4026072896 Jul 03 07:19:03 PM PDT 24 Jul 03 07:19:11 PM PDT 24 866901263 ps
T987 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2950372226 Jul 03 07:19:18 PM PDT 24 Jul 03 07:19:26 PM PDT 24 93459699 ps
T988 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.4197990118 Jul 03 07:19:07 PM PDT 24 Jul 03 07:19:23 PM PDT 24 360081022 ps
T989 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1793121939 Jul 03 07:19:27 PM PDT 24 Jul 03 07:19:34 PM PDT 24 17390906 ps
T990 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3822387998 Jul 03 07:18:59 PM PDT 24 Jul 03 07:19:05 PM PDT 24 51867507 ps
T991 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3975514588 Jul 03 07:19:10 PM PDT 24 Jul 03 07:19:40 PM PDT 24 3872833911 ps
T992 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.560327334 Jul 03 07:18:58 PM PDT 24 Jul 03 07:19:39 PM PDT 24 26747963043 ps
T993 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3024310375 Jul 03 07:19:19 PM PDT 24 Jul 03 07:19:26 PM PDT 24 56658806 ps
T994 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1215894418 Jul 03 07:19:06 PM PDT 24 Jul 03 07:19:47 PM PDT 24 1797596765 ps
T995 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.1017470393 Jul 03 07:19:23 PM PDT 24 Jul 03 07:19:31 PM PDT 24 161731048 ps
T996 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2592563976 Jul 03 07:18:57 PM PDT 24 Jul 03 07:19:17 PM PDT 24 1264072750 ps
T997 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2277688108 Jul 03 07:19:23 PM PDT 24 Jul 03 07:19:30 PM PDT 24 109820067 ps

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.418594360
Short name T15
Test name
Test status
Simulation time 8214204959 ps
CPU time 22.32 seconds
Started Jul 03 07:10:42 PM PDT 24
Finished Jul 03 07:11:37 PM PDT 24
Peak memory 218280 kb
Host smart-d94bb55a-1ef2-4d00-a69b-3908ac0d1abb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418594360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.418594360
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.884379791
Short name T17
Test name
Test status
Simulation time 90806478564 ps
CPU time 743.88 seconds
Started Jul 03 07:13:06 PM PDT 24
Finished Jul 03 07:25:31 PM PDT 24
Peak memory 277860 kb
Host smart-0177a132-e860-4483-8dea-619e294a2b74
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884379791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.884379791
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.1248108095
Short name T61
Test name
Test status
Simulation time 705085252 ps
CPU time 13.99 seconds
Started Jul 03 07:12:31 PM PDT 24
Finished Jul 03 07:12:49 PM PDT 24
Peak memory 225588 kb
Host smart-e896c12d-94ed-4263-8c41-e2fd1017b08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248108095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.1248108095
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.2484579129
Short name T45
Test name
Test status
Simulation time 99966117832 ps
CPU time 920.32 seconds
Started Jul 03 07:13:13 PM PDT 24
Finished Jul 03 07:28:35 PM PDT 24
Peak memory 414568 kb
Host smart-0cccc8da-aea3-4c9c-83ed-28ba3aaa078a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2484579129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all_with_rand_reset.2484579129
Directory /workspace/27.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.3343308890
Short name T40
Test name
Test status
Simulation time 24961833 ps
CPU time 0.93 seconds
Started Jul 03 07:10:58 PM PDT 24
Finished Jul 03 07:11:34 PM PDT 24
Peak memory 208620 kb
Host smart-c75c6683-a410-4f1f-ac8b-0df6fe79e26e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343308890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.3343308890
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.1008780164
Short name T2
Test name
Test status
Simulation time 771031511 ps
CPU time 6.53 seconds
Started Jul 03 07:14:58 PM PDT 24
Finished Jul 03 07:15:08 PM PDT 24
Peak memory 217728 kb
Host smart-2ca72838-9b36-4994-a2ae-b57f08321aaf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008780164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
1008780164
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.2633691793
Short name T63
Test name
Test status
Simulation time 178323927 ps
CPU time 22.62 seconds
Started Jul 03 07:10:39 PM PDT 24
Finished Jul 03 07:11:33 PM PDT 24
Peak memory 284056 kb
Host smart-2ed25d0d-183a-463a-8dce-375897557b3b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633691793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.2633691793
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.4179194118
Short name T55
Test name
Test status
Simulation time 32637208682 ps
CPU time 1273.35 seconds
Started Jul 03 07:10:54 PM PDT 24
Finished Jul 03 07:32:42 PM PDT 24
Peak memory 327912 kb
Host smart-85cddda9-a794-49c6-8510-26a0f88c33e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4179194118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all_with_rand_reset.4179194118
Directory /workspace/3.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.284001434
Short name T60
Test name
Test status
Simulation time 493089325 ps
CPU time 10.62 seconds
Started Jul 03 07:12:52 PM PDT 24
Finished Jul 03 07:13:05 PM PDT 24
Peak memory 225108 kb
Host smart-f1339865-b067-4952-ab4b-a5e1fb2e1042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284001434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.284001434
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.22946158
Short name T113
Test name
Test status
Simulation time 65484885 ps
CPU time 2.57 seconds
Started Jul 03 07:19:06 PM PDT 24
Finished Jul 03 07:19:14 PM PDT 24
Peak memory 217580 kb
Host smart-35b76040-5531-4715-b4b9-bd70c5969333
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22946158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_er
r.22946158
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.313863332
Short name T7
Test name
Test status
Simulation time 219416436 ps
CPU time 6.07 seconds
Started Jul 03 07:12:26 PM PDT 24
Finished Jul 03 07:12:38 PM PDT 24
Peak memory 217172 kb
Host smart-3b98dc08-6257-41df-ac50-9cc6792fb2b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313863332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.313863332
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.2347841461
Short name T22
Test name
Test status
Simulation time 18793941 ps
CPU time 0.84 seconds
Started Jul 03 07:12:08 PM PDT 24
Finished Jul 03 07:12:20 PM PDT 24
Peak memory 208584 kb
Host smart-abe472fd-2bd2-4c1a-9091-154c67c4b7a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347841461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.2347841461
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1145218010
Short name T123
Test name
Test status
Simulation time 150865358 ps
CPU time 4.82 seconds
Started Jul 03 07:19:06 PM PDT 24
Finished Jul 03 07:19:17 PM PDT 24
Peak memory 224868 kb
Host smart-08c6a63e-3a04-4426-8eac-7836fccf691c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114521
8010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1145218010
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3154693864
Short name T178
Test name
Test status
Simulation time 23925339 ps
CPU time 0.9 seconds
Started Jul 03 07:19:23 PM PDT 24
Finished Jul 03 07:19:30 PM PDT 24
Peak memory 208404 kb
Host smart-021de8af-8886-45eb-a5f8-0cea2b6a42ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154693864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.3154693864
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2423273946
Short name T146
Test name
Test status
Simulation time 1226489343 ps
CPU time 4.27 seconds
Started Jul 03 07:19:11 PM PDT 24
Finished Jul 03 07:19:24 PM PDT 24
Peak memory 209224 kb
Host smart-ad747ab1-3f3c-4fbe-a5b9-b100b069d139
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423273946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.2423273946
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.2569237734
Short name T13
Test name
Test status
Simulation time 393991928 ps
CPU time 16.21 seconds
Started Jul 03 07:11:55 PM PDT 24
Finished Jul 03 07:12:27 PM PDT 24
Peak memory 217812 kb
Host smart-5f808427-e480-4b32-8f47-7b74219d4b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569237734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.2569237734
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.23035351
Short name T20
Test name
Test status
Simulation time 6260094237 ps
CPU time 85.27 seconds
Started Jul 03 07:12:20 PM PDT 24
Finished Jul 03 07:13:54 PM PDT 24
Peak memory 218448 kb
Host smart-b30bbcbb-9825-43f7-b6c3-aaa0f36707e4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23035351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_l
c_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_err
ors.23035351
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3041738895
Short name T134
Test name
Test status
Simulation time 311518273 ps
CPU time 3.68 seconds
Started Jul 03 07:19:04 PM PDT 24
Finished Jul 03 07:19:12 PM PDT 24
Peak memory 217464 kb
Host smart-4ba6dbce-357e-4849-8f52-e8d0573ca2b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041738895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.3041738895
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.4113967788
Short name T130
Test name
Test status
Simulation time 75741767 ps
CPU time 2.69 seconds
Started Jul 03 07:19:15 PM PDT 24
Finished Jul 03 07:19:25 PM PDT 24
Peak memory 222052 kb
Host smart-40dd9a3f-bbf1-4b8d-b8b0-1abb1a07ebcf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113967788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.4113967788
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.4229876539
Short name T122
Test name
Test status
Simulation time 137378793 ps
CPU time 3.09 seconds
Started Jul 03 07:18:58 PM PDT 24
Finished Jul 03 07:19:06 PM PDT 24
Peak memory 222104 kb
Host smart-7bcc3fe4-5daa-4917-a832-46f3986fe942
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229876539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.4229876539
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.1467047474
Short name T167
Test name
Test status
Simulation time 11579500239 ps
CPU time 269.04 seconds
Started Jul 03 07:11:57 PM PDT 24
Finished Jul 03 07:16:41 PM PDT 24
Peak memory 278568 kb
Host smart-2be94a88-76a0-4409-b748-1f3fa762cdb5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1467047474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all_with_rand_reset.1467047474
Directory /workspace/11.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.2959109049
Short name T5
Test name
Test status
Simulation time 434706284 ps
CPU time 2.25 seconds
Started Jul 03 07:11:02 PM PDT 24
Finished Jul 03 07:11:40 PM PDT 24
Peak memory 217224 kb
Host smart-1ea8c636-f079-49df-8bf7-43a58f5ab28e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959109049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
2959109049
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3066726734
Short name T126
Test name
Test status
Simulation time 232891280 ps
CPU time 2.92 seconds
Started Jul 03 07:19:27 PM PDT 24
Finished Jul 03 07:19:35 PM PDT 24
Peak memory 217560 kb
Host smart-55ab1cec-84e5-4907-a899-1c84118f42ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066726734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.3066726734
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1071435708
Short name T158
Test name
Test status
Simulation time 90426224 ps
CPU time 1.08 seconds
Started Jul 03 07:19:01 PM PDT 24
Finished Jul 03 07:19:07 PM PDT 24
Peak memory 209280 kb
Host smart-2b4f41fe-67ce-4c42-bd9c-53cc519edbac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071435708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.1071435708
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.549696074
Short name T93
Test name
Test status
Simulation time 28031070496 ps
CPU time 273.24 seconds
Started Jul 03 07:14:58 PM PDT 24
Finished Jul 03 07:19:35 PM PDT 24
Peak memory 283472 kb
Host smart-01bab359-55e1-4b44-aaf1-43de9f6c4571
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=549696074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.549696074
Directory /workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2139412679
Short name T117
Test name
Test status
Simulation time 98092073 ps
CPU time 2.83 seconds
Started Jul 03 07:19:23 PM PDT 24
Finished Jul 03 07:19:31 PM PDT 24
Peak memory 217516 kb
Host smart-0d17e514-b340-41ee-804d-a834d6903cc3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139412679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.2139412679
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1510905217
Short name T129
Test name
Test status
Simulation time 86045676 ps
CPU time 1.87 seconds
Started Jul 03 07:19:25 PM PDT 24
Finished Jul 03 07:19:32 PM PDT 24
Peak memory 221956 kb
Host smart-e9e7a25d-adc9-4ac9-8c4c-51fee84c83ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510905217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.1510905217
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3307476909
Short name T141
Test name
Test status
Simulation time 62050691 ps
CPU time 1.9 seconds
Started Jul 03 07:19:07 PM PDT 24
Finished Jul 03 07:19:16 PM PDT 24
Peak memory 222080 kb
Host smart-4fb477d2-a979-469a-83c1-6e78e867b4d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307476909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.3307476909
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.3868557859
Short name T197
Test name
Test status
Simulation time 13796649 ps
CPU time 0.99 seconds
Started Jul 03 07:10:20 PM PDT 24
Finished Jul 03 07:10:43 PM PDT 24
Peak memory 208460 kb
Host smart-6aafb511-b213-4d36-b5f2-8cfcf7997e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868557859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.3868557859
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.1125384170
Short name T76
Test name
Test status
Simulation time 101482173 ps
CPU time 0.8 seconds
Started Jul 03 07:10:41 PM PDT 24
Finished Jul 03 07:11:13 PM PDT 24
Peak memory 208280 kb
Host smart-f5bc162c-a2cc-4e96-8534-db0d45113b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125384170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.1125384170
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.3829379684
Short name T35
Test name
Test status
Simulation time 2248733666 ps
CPU time 18.86 seconds
Started Jul 03 07:10:33 PM PDT 24
Finished Jul 03 07:11:21 PM PDT 24
Peak memory 219588 kb
Host smart-ea3b55fd-8b5c-430a-9683-915ba8ef2e90
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829379684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.3829379684
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.2249025919
Short name T11
Test name
Test status
Simulation time 490205989 ps
CPU time 2.6 seconds
Started Jul 03 07:14:56 PM PDT 24
Finished Jul 03 07:15:01 PM PDT 24
Peak memory 217744 kb
Host smart-fec0377d-3c16-4280-a40e-72fe79789a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249025919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.2249025919
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3002544301
Short name T132
Test name
Test status
Simulation time 119262487 ps
CPU time 4.2 seconds
Started Jul 03 07:19:27 PM PDT 24
Finished Jul 03 07:19:37 PM PDT 24
Peak memory 217488 kb
Host smart-9b14f115-9a42-4315-81f3-a2eaa8f16b70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002544301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.3002544301
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2705297761
Short name T118
Test name
Test status
Simulation time 143678109 ps
CPU time 2.02 seconds
Started Jul 03 07:19:24 PM PDT 24
Finished Jul 03 07:19:31 PM PDT 24
Peak memory 222288 kb
Host smart-04574fba-7ff6-43d8-b711-2004008e91b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705297761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.2705297761
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.692206011
Short name T135
Test name
Test status
Simulation time 53038298 ps
CPU time 1.91 seconds
Started Jul 03 07:19:29 PM PDT 24
Finished Jul 03 07:19:36 PM PDT 24
Peak memory 221764 kb
Host smart-af122c66-58f2-4430-8e18-6d2524a6f9f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692206011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg_
err.692206011
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2340524630
Short name T137
Test name
Test status
Simulation time 387270215 ps
CPU time 2.99 seconds
Started Jul 03 07:19:08 PM PDT 24
Finished Jul 03 07:19:18 PM PDT 24
Peak memory 222252 kb
Host smart-34d89130-61e1-4b6a-a15f-240f989f037f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340524630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.2340524630
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.4032831909
Short name T114
Test name
Test status
Simulation time 83989502 ps
CPU time 2.24 seconds
Started Jul 03 07:19:16 PM PDT 24
Finished Jul 03 07:19:25 PM PDT 24
Peak memory 217472 kb
Host smart-d0d2af77-88bf-49d5-8d7b-24c1b5816780
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032831909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.4032831909
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.1168177875
Short name T59
Test name
Test status
Simulation time 100326071241 ps
CPU time 392.63 seconds
Started Jul 03 07:12:18 PM PDT 24
Finished Jul 03 07:19:00 PM PDT 24
Peak memory 250612 kb
Host smart-8dedd675-83b3-434f-a5b7-0456b22c31d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168177875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.1168177875
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.3719139990
Short name T6
Test name
Test status
Simulation time 8274028626 ps
CPU time 66.8 seconds
Started Jul 03 07:12:11 PM PDT 24
Finished Jul 03 07:13:28 PM PDT 24
Peak memory 266872 kb
Host smart-076e02d1-f7fc-4061-9d6b-963a6aa4b16d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719139990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.3719139990
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2948573210
Short name T179
Test name
Test status
Simulation time 108493265 ps
CPU time 1.28 seconds
Started Jul 03 07:18:57 PM PDT 24
Finished Jul 03 07:19:04 PM PDT 24
Peak memory 209104 kb
Host smart-22ae4c08-38b1-41d9-b007-6c0149aa235b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948573210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.2948573210
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3903164957
Short name T937
Test name
Test status
Simulation time 64259834 ps
CPU time 2.68 seconds
Started Jul 03 07:18:58 PM PDT 24
Finished Jul 03 07:19:06 PM PDT 24
Peak memory 209220 kb
Host smart-513bfc58-01d9-46f6-92df-daa6efa5ea63
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903164957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.3903164957
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2255157425
Short name T187
Test name
Test status
Simulation time 51724870 ps
CPU time 0.89 seconds
Started Jul 03 07:19:00 PM PDT 24
Finished Jul 03 07:19:07 PM PDT 24
Peak memory 209784 kb
Host smart-8de733d6-a674-4af8-b1f8-004186dca395
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255157425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.2255157425
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1979063408
Short name T895
Test name
Test status
Simulation time 27227335 ps
CPU time 1.13 seconds
Started Jul 03 07:18:57 PM PDT 24
Finished Jul 03 07:19:04 PM PDT 24
Peak memory 217572 kb
Host smart-e0df89e4-cda9-4b42-8d17-72a61715a410
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979063408 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.1979063408
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3822387998
Short name T990
Test name
Test status
Simulation time 51867507 ps
CPU time 0.82 seconds
Started Jul 03 07:18:59 PM PDT 24
Finished Jul 03 07:19:05 PM PDT 24
Peak memory 209100 kb
Host smart-909048a8-796c-443e-80bf-5c1f3441aef2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822387998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.3822387998
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2428702134
Short name T948
Test name
Test status
Simulation time 45202902 ps
CPU time 1.25 seconds
Started Jul 03 07:18:57 PM PDT 24
Finished Jul 03 07:19:04 PM PDT 24
Peak memory 209116 kb
Host smart-e422c1ec-265f-46da-b0c2-1dd1f1531d1f
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428702134 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.2428702134
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.860132371
Short name T961
Test name
Test status
Simulation time 1031007129 ps
CPU time 4.27 seconds
Started Jul 03 07:18:58 PM PDT 24
Finished Jul 03 07:19:08 PM PDT 24
Peak memory 209156 kb
Host smart-b40241ca-fa8b-4563-ab05-c7982d8dd0fc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860132371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.860132371
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2592563976
Short name T996
Test name
Test status
Simulation time 1264072750 ps
CPU time 14.64 seconds
Started Jul 03 07:18:57 PM PDT 24
Finished Jul 03 07:19:17 PM PDT 24
Peak memory 208888 kb
Host smart-be960aef-8264-4689-b999-c6c40f220ab3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592563976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.2592563976
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1182583984
Short name T941
Test name
Test status
Simulation time 102322701 ps
CPU time 1.55 seconds
Started Jul 03 07:18:57 PM PDT 24
Finished Jul 03 07:19:05 PM PDT 24
Peak memory 217412 kb
Host smart-477e7da1-ffe5-4492-bc6c-ef42858cc2df
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182583984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.1182583984
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1783518526
Short name T907
Test name
Test status
Simulation time 230032157 ps
CPU time 3.24 seconds
Started Jul 03 07:18:52 PM PDT 24
Finished Jul 03 07:19:02 PM PDT 24
Peak memory 217520 kb
Host smart-24dbe169-b745-4f64-8dca-863ac18e463d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178351
8526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1783518526
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.501900224
Short name T974
Test name
Test status
Simulation time 212565908 ps
CPU time 1.28 seconds
Started Jul 03 07:18:55 PM PDT 24
Finished Jul 03 07:19:01 PM PDT 24
Peak memory 209156 kb
Host smart-33166f54-ab36-4224-b9d9-a8d44a57e5d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501900224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.501900224
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3742795255
Short name T942
Test name
Test status
Simulation time 57825424 ps
CPU time 1.17 seconds
Started Jul 03 07:18:57 PM PDT 24
Finished Jul 03 07:19:04 PM PDT 24
Peak memory 211408 kb
Host smart-b8f2079f-8a76-4b22-acac-d4a78bec1a51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742795255 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.3742795255
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1582416230
Short name T983
Test name
Test status
Simulation time 46750618 ps
CPU time 2.2 seconds
Started Jul 03 07:19:00 PM PDT 24
Finished Jul 03 07:19:08 PM PDT 24
Peak memory 217504 kb
Host smart-36153701-5f1f-4dad-9e96-6922872b15fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582416230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.1582416230
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1008016511
Short name T975
Test name
Test status
Simulation time 122525393 ps
CPU time 2.15 seconds
Started Jul 03 07:18:57 PM PDT 24
Finished Jul 03 07:19:04 PM PDT 24
Peak memory 221624 kb
Host smart-32726cad-7c87-4efd-868e-dbbfab052d78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008016511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.1008016511
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.637070033
Short name T189
Test name
Test status
Simulation time 27875700 ps
CPU time 1.53 seconds
Started Jul 03 07:18:57 PM PDT 24
Finished Jul 03 07:19:04 PM PDT 24
Peak memory 209340 kb
Host smart-62095bd3-9724-4564-8f9a-4c419b294f4e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637070033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasing
.637070033
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.40149104
Short name T921
Test name
Test status
Simulation time 226549424 ps
CPU time 1.95 seconds
Started Jul 03 07:18:57 PM PDT 24
Finished Jul 03 07:19:04 PM PDT 24
Peak memory 209028 kb
Host smart-2b49b545-a0af-4996-b796-27c2eb0144cb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40149104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bash.40149104
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1553519169
Short name T946
Test name
Test status
Simulation time 48574450 ps
CPU time 1.1 seconds
Started Jul 03 07:18:56 PM PDT 24
Finished Jul 03 07:19:02 PM PDT 24
Peak memory 209864 kb
Host smart-50cacf17-4a7f-45a6-bd78-b307a9ec90dc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553519169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.1553519169
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2122286591
Short name T885
Test name
Test status
Simulation time 126454255 ps
CPU time 1.79 seconds
Started Jul 03 07:18:59 PM PDT 24
Finished Jul 03 07:19:06 PM PDT 24
Peak memory 219108 kb
Host smart-d1648e60-43bb-4ee0-965c-a1610a76ff26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122286591 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.2122286591
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3574325227
Short name T185
Test name
Test status
Simulation time 12442667 ps
CPU time 1.01 seconds
Started Jul 03 07:19:00 PM PDT 24
Finished Jul 03 07:19:07 PM PDT 24
Peak memory 209244 kb
Host smart-dd5ee5b4-951a-41ec-86eb-74dd35772314
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574325227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.3574325227
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2756240920
Short name T884
Test name
Test status
Simulation time 198568502 ps
CPU time 1.28 seconds
Started Jul 03 07:19:00 PM PDT 24
Finished Jul 03 07:19:07 PM PDT 24
Peak memory 208592 kb
Host smart-452518d1-f9aa-49f3-ba67-5a48b58eb032
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756240920 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.2756240920
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.4154058846
Short name T914
Test name
Test status
Simulation time 1322405614 ps
CPU time 6.31 seconds
Started Jul 03 07:18:59 PM PDT 24
Finished Jul 03 07:19:11 PM PDT 24
Peak memory 209204 kb
Host smart-ef5e501f-deb9-40c6-8a19-67ccebb6a788
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154058846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.4154058846
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.560327334
Short name T992
Test name
Test status
Simulation time 26747963043 ps
CPU time 35.85 seconds
Started Jul 03 07:18:58 PM PDT 24
Finished Jul 03 07:19:39 PM PDT 24
Peak memory 209268 kb
Host smart-d56cb156-032a-43ce-92b9-0a886f2f9873
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560327334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.560327334
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1364674324
Short name T918
Test name
Test status
Simulation time 158557999 ps
CPU time 1.77 seconds
Started Jul 03 07:18:57 PM PDT 24
Finished Jul 03 07:19:05 PM PDT 24
Peak memory 217568 kb
Host smart-beb48607-2a91-4df6-a9e6-2eb8cdf0fb36
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364674324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.1364674324
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1913405115
Short name T911
Test name
Test status
Simulation time 668212631 ps
CPU time 2.5 seconds
Started Jul 03 07:18:58 PM PDT 24
Finished Jul 03 07:19:06 PM PDT 24
Peak memory 218740 kb
Host smart-36f3e0e6-6738-4566-a03b-5580a166af06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191340
5115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1913405115
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1698619759
Short name T906
Test name
Test status
Simulation time 542803880 ps
CPU time 1.89 seconds
Started Jul 03 07:19:01 PM PDT 24
Finished Jul 03 07:19:08 PM PDT 24
Peak memory 209028 kb
Host smart-f6fe2dfb-3ba4-4102-bc4f-9eab0f3b06a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698619759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.1698619759
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.897720112
Short name T159
Test name
Test status
Simulation time 92749438 ps
CPU time 2.03 seconds
Started Jul 03 07:18:57 PM PDT 24
Finished Jul 03 07:19:05 PM PDT 24
Peak memory 209344 kb
Host smart-5c313b71-38b0-4c61-b529-649661c0a425
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897720112 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.897720112
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2154789552
Short name T973
Test name
Test status
Simulation time 692163932 ps
CPU time 1.78 seconds
Started Jul 03 07:18:59 PM PDT 24
Finished Jul 03 07:19:06 PM PDT 24
Peak memory 211280 kb
Host smart-37077de3-c3d5-45c6-9c6d-b380825ee332
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154789552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.2154789552
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1965771909
Short name T899
Test name
Test status
Simulation time 296781407 ps
CPU time 2.31 seconds
Started Jul 03 07:18:56 PM PDT 24
Finished Jul 03 07:19:03 PM PDT 24
Peak memory 217464 kb
Host smart-b6ac4681-542a-430b-9d41-d802d067fdaa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965771909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.1965771909
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3075511252
Short name T947
Test name
Test status
Simulation time 34683407 ps
CPU time 2.11 seconds
Started Jul 03 07:19:17 PM PDT 24
Finished Jul 03 07:19:26 PM PDT 24
Peak memory 225384 kb
Host smart-19d9a4d5-55b6-4990-95ee-dd02745579d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075511252 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.3075511252
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1817302958
Short name T182
Test name
Test status
Simulation time 27127677 ps
CPU time 0.8 seconds
Started Jul 03 07:19:18 PM PDT 24
Finished Jul 03 07:19:25 PM PDT 24
Peak memory 209312 kb
Host smart-7c6e2814-343d-4558-9a4d-4e82beb90fdc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817302958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.1817302958
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.1017470393
Short name T995
Test name
Test status
Simulation time 161731048 ps
CPU time 1.9 seconds
Started Jul 03 07:19:23 PM PDT 24
Finished Jul 03 07:19:31 PM PDT 24
Peak memory 210832 kb
Host smart-54a3fff4-848b-4e20-b469-fdb0b04cb852
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017470393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.1017470393
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1403442717
Short name T957
Test name
Test status
Simulation time 175787596 ps
CPU time 2.95 seconds
Started Jul 03 07:19:21 PM PDT 24
Finished Jul 03 07:19:30 PM PDT 24
Peak memory 218732 kb
Host smart-53d876fc-6f6e-4564-8999-ee4e129c20ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403442717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.1403442717
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3604716358
Short name T888
Test name
Test status
Simulation time 69035898 ps
CPU time 1.32 seconds
Started Jul 03 07:19:29 PM PDT 24
Finished Jul 03 07:19:35 PM PDT 24
Peak memory 218068 kb
Host smart-fd085353-c069-46ae-aaf0-54b057c55c78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604716358 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.3604716358
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.642362215
Short name T184
Test name
Test status
Simulation time 19145906 ps
CPU time 1.17 seconds
Started Jul 03 07:19:24 PM PDT 24
Finished Jul 03 07:19:30 PM PDT 24
Peak memory 209292 kb
Host smart-acfd1663-12f3-4b40-94b5-544058a4bbed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642362215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.642362215
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2277688108
Short name T997
Test name
Test status
Simulation time 109820067 ps
CPU time 1.42 seconds
Started Jul 03 07:19:23 PM PDT 24
Finished Jul 03 07:19:30 PM PDT 24
Peak memory 217572 kb
Host smart-67ab77ff-d1e5-4b10-acd5-2a659c3fa47f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277688108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.2277688108
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3834929146
Short name T966
Test name
Test status
Simulation time 218169209 ps
CPU time 3.08 seconds
Started Jul 03 07:19:22 PM PDT 24
Finished Jul 03 07:19:31 PM PDT 24
Peak memory 217536 kb
Host smart-358ff078-944e-416f-8d29-b93dbc92e4c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834929146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.3834929146
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3460748136
Short name T128
Test name
Test status
Simulation time 93435767 ps
CPU time 2.37 seconds
Started Jul 03 07:19:22 PM PDT 24
Finished Jul 03 07:19:30 PM PDT 24
Peak memory 221920 kb
Host smart-fe0d3982-72b8-4a1d-9413-458f33da722f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460748136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.3460748136
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2749626209
Short name T959
Test name
Test status
Simulation time 64556925 ps
CPU time 1.56 seconds
Started Jul 03 07:19:21 PM PDT 24
Finished Jul 03 07:19:28 PM PDT 24
Peak memory 217616 kb
Host smart-185bdf86-033b-4cbc-a514-cd7d1af9b0a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749626209 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.2749626209
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3182054846
Short name T953
Test name
Test status
Simulation time 42241316 ps
CPU time 1.05 seconds
Started Jul 03 07:19:24 PM PDT 24
Finished Jul 03 07:19:30 PM PDT 24
Peak memory 209420 kb
Host smart-f923933e-f8f8-456b-8e69-603c38ebf21d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182054846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.3182054846
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1441793676
Short name T886
Test name
Test status
Simulation time 57735365 ps
CPU time 1.02 seconds
Started Jul 03 07:19:22 PM PDT 24
Finished Jul 03 07:19:29 PM PDT 24
Peak memory 209284 kb
Host smart-8c097247-db78-4f9c-802d-9fc3700f0fa4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441793676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.1441793676
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2530556387
Short name T142
Test name
Test status
Simulation time 88210162 ps
CPU time 2.85 seconds
Started Jul 03 07:19:24 PM PDT 24
Finished Jul 03 07:19:33 PM PDT 24
Peak memory 217496 kb
Host smart-4b55d576-a69f-48a4-aaf2-cd7b89cb2c7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530556387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.2530556387
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1383892167
Short name T896
Test name
Test status
Simulation time 25729234 ps
CPU time 2.1 seconds
Started Jul 03 07:19:25 PM PDT 24
Finished Jul 03 07:19:33 PM PDT 24
Peak memory 217100 kb
Host smart-a85d3153-2a9c-41c1-b372-fc7ecf0d18c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383892167 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.1383892167
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2691841548
Short name T186
Test name
Test status
Simulation time 126290427 ps
CPU time 0.97 seconds
Started Jul 03 07:19:23 PM PDT 24
Finished Jul 03 07:19:29 PM PDT 24
Peak memory 208992 kb
Host smart-e964cc84-cc67-4902-99c2-07ab835695dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691841548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.2691841548
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.4187737924
Short name T940
Test name
Test status
Simulation time 290832803 ps
CPU time 1.07 seconds
Started Jul 03 07:19:22 PM PDT 24
Finished Jul 03 07:19:29 PM PDT 24
Peak memory 209288 kb
Host smart-05612685-2af8-41a9-9991-ae2e145ed561
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187737924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.4187737924
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2644965669
Short name T969
Test name
Test status
Simulation time 60997303 ps
CPU time 1.71 seconds
Started Jul 03 07:19:24 PM PDT 24
Finished Jul 03 07:19:31 PM PDT 24
Peak memory 218504 kb
Host smart-481ee4b6-aa68-404b-b3bf-725ad755e9b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644965669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.2644965669
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1537061750
Short name T934
Test name
Test status
Simulation time 101388541 ps
CPU time 1.43 seconds
Started Jul 03 07:19:21 PM PDT 24
Finished Jul 03 07:19:28 PM PDT 24
Peak memory 217660 kb
Host smart-522df5fa-e298-44bf-92e6-48cd06b4006f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537061750 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.1537061750
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2443880299
Short name T183
Test name
Test status
Simulation time 97515801 ps
CPU time 0.79 seconds
Started Jul 03 07:19:20 PM PDT 24
Finished Jul 03 07:19:27 PM PDT 24
Peak memory 209180 kb
Host smart-2c162b36-bd0b-4d4f-a272-a9f6d13af9dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443880299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.2443880299
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.194554468
Short name T892
Test name
Test status
Simulation time 55319236 ps
CPU time 1.09 seconds
Started Jul 03 07:19:22 PM PDT 24
Finished Jul 03 07:19:28 PM PDT 24
Peak memory 209320 kb
Host smart-5cff7d6a-a34b-4cf5-8410-752f2d6daaa1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194554468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_same_csr_outstanding.194554468
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1380865638
Short name T943
Test name
Test status
Simulation time 158063247 ps
CPU time 3.47 seconds
Started Jul 03 07:19:22 PM PDT 24
Finished Jul 03 07:19:31 PM PDT 24
Peak memory 217468 kb
Host smart-549a1aee-29f2-4db6-aff0-ccb3e7fb27c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380865638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.1380865638
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2534703622
Short name T139
Test name
Test status
Simulation time 147834448 ps
CPU time 1.92 seconds
Started Jul 03 07:19:23 PM PDT 24
Finished Jul 03 07:19:30 PM PDT 24
Peak memory 222076 kb
Host smart-91730de9-c687-4f75-ad55-efa07b09ba99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534703622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.2534703622
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2410419888
Short name T928
Test name
Test status
Simulation time 100312486 ps
CPU time 1.99 seconds
Started Jul 03 07:19:27 PM PDT 24
Finished Jul 03 07:19:35 PM PDT 24
Peak memory 217688 kb
Host smart-1ca64965-5a50-478b-9220-ffa37735a02e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410419888 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.2410419888
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3024310375
Short name T993
Test name
Test status
Simulation time 56658806 ps
CPU time 0.88 seconds
Started Jul 03 07:19:19 PM PDT 24
Finished Jul 03 07:19:26 PM PDT 24
Peak memory 209220 kb
Host smart-dd008a4e-b864-4c6e-a6e5-553707668e31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024310375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.3024310375
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1559361094
Short name T889
Test name
Test status
Simulation time 137858815 ps
CPU time 1.33 seconds
Started Jul 03 07:19:22 PM PDT 24
Finished Jul 03 07:19:29 PM PDT 24
Peak memory 217520 kb
Host smart-c7987d1f-8cd8-4010-bb50-1bc620e33545
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559361094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.1559361094
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.414274694
Short name T930
Test name
Test status
Simulation time 993690111 ps
CPU time 3.74 seconds
Started Jul 03 07:19:29 PM PDT 24
Finished Jul 03 07:19:38 PM PDT 24
Peak memory 217528 kb
Host smart-92cbdacf-eb10-46c8-b040-aa527baa9431
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414274694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.414274694
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2211505585
Short name T905
Test name
Test status
Simulation time 163394170 ps
CPU time 1.34 seconds
Started Jul 03 07:19:29 PM PDT 24
Finished Jul 03 07:19:35 PM PDT 24
Peak memory 217560 kb
Host smart-c80eb73a-21ac-4d4e-8e26-9c33a54c69e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211505585 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.2211505585
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.490772043
Short name T939
Test name
Test status
Simulation time 23744486 ps
CPU time 1.08 seconds
Started Jul 03 07:19:25 PM PDT 24
Finished Jul 03 07:19:31 PM PDT 24
Peak memory 208784 kb
Host smart-7290ef00-7319-453c-b862-28a91fb62c7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490772043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.490772043
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1262094671
Short name T878
Test name
Test status
Simulation time 58654074 ps
CPU time 1.19 seconds
Started Jul 03 07:19:27 PM PDT 24
Finished Jul 03 07:19:34 PM PDT 24
Peak memory 217468 kb
Host smart-87856092-c351-4401-b78d-3493559d2e6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262094671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.1262094671
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1246489548
Short name T125
Test name
Test status
Simulation time 29785821 ps
CPU time 2.08 seconds
Started Jul 03 07:19:20 PM PDT 24
Finished Jul 03 07:19:28 PM PDT 24
Peak memory 217628 kb
Host smart-9b815d28-e441-446a-8506-c7a55cb020b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246489548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.1246489548
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.969556912
Short name T115
Test name
Test status
Simulation time 35017682 ps
CPU time 1.38 seconds
Started Jul 03 07:19:29 PM PDT 24
Finished Jul 03 07:19:35 PM PDT 24
Peak memory 217700 kb
Host smart-a4fb53f3-71a0-4edb-8b47-6544a67bf152
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969556912 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.969556912
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1072931410
Short name T903
Test name
Test status
Simulation time 14310495 ps
CPU time 0.82 seconds
Started Jul 03 07:19:25 PM PDT 24
Finished Jul 03 07:19:31 PM PDT 24
Peak memory 209304 kb
Host smart-dee54f56-c022-4874-a71e-e4d87bbad143
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072931410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.1072931410
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2614893638
Short name T193
Test name
Test status
Simulation time 101553840 ps
CPU time 1.31 seconds
Started Jul 03 07:19:27 PM PDT 24
Finished Jul 03 07:19:33 PM PDT 24
Peak memory 209320 kb
Host smart-8fdb7a63-ac9a-44c5-8c58-1767cdf5a873
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614893638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.2614893638
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.1599048906
Short name T919
Test name
Test status
Simulation time 48400309 ps
CPU time 1.57 seconds
Started Jul 03 07:19:27 PM PDT 24
Finished Jul 03 07:19:34 PM PDT 24
Peak memory 217564 kb
Host smart-32b0b362-69b7-40b4-aae2-765b8080c153
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599048906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.1599048906
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.492722121
Short name T138
Test name
Test status
Simulation time 512305992 ps
CPU time 3.32 seconds
Started Jul 03 07:19:30 PM PDT 24
Finished Jul 03 07:19:38 PM PDT 24
Peak memory 222528 kb
Host smart-9fc28de2-e4b9-4e83-9f1a-a2cd83f1a872
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492722121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg_
err.492722121
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1179114397
Short name T925
Test name
Test status
Simulation time 27181891 ps
CPU time 1.45 seconds
Started Jul 03 07:19:25 PM PDT 24
Finished Jul 03 07:19:32 PM PDT 24
Peak memory 217540 kb
Host smart-c1bf38c7-343f-4be0-8cdf-02d92bf771d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179114397 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.1179114397
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2168873484
Short name T916
Test name
Test status
Simulation time 14786370 ps
CPU time 1.1 seconds
Started Jul 03 07:19:27 PM PDT 24
Finished Jul 03 07:19:34 PM PDT 24
Peak memory 209308 kb
Host smart-4d74150b-ffa5-432b-853a-f927698394f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168873484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.2168873484
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.1223702131
Short name T893
Test name
Test status
Simulation time 191273635 ps
CPU time 1.49 seconds
Started Jul 03 07:19:27 PM PDT 24
Finished Jul 03 07:19:33 PM PDT 24
Peak memory 217476 kb
Host smart-bdb7442a-2821-4489-8d80-d577de71a97b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223702131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.1223702131
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3616713845
Short name T116
Test name
Test status
Simulation time 210403749 ps
CPU time 2.01 seconds
Started Jul 03 07:19:29 PM PDT 24
Finished Jul 03 07:19:36 PM PDT 24
Peak memory 217468 kb
Host smart-e95a8a62-44fe-439d-b350-9ec3b02eaff0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616713845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.3616713845
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1936843363
Short name T917
Test name
Test status
Simulation time 17012005 ps
CPU time 1.1 seconds
Started Jul 03 07:19:27 PM PDT 24
Finished Jul 03 07:19:33 PM PDT 24
Peak memory 219716 kb
Host smart-69553bca-6db5-4dd5-9fec-a9b05632bcff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936843363 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.1936843363
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1793651548
Short name T181
Test name
Test status
Simulation time 36948123 ps
CPU time 0.86 seconds
Started Jul 03 07:19:27 PM PDT 24
Finished Jul 03 07:19:33 PM PDT 24
Peak memory 209212 kb
Host smart-1dbb87da-3e3e-41bd-acca-63f74a72ce98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793651548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.1793651548
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1793121939
Short name T989
Test name
Test status
Simulation time 17390906 ps
CPU time 1.19 seconds
Started Jul 03 07:19:27 PM PDT 24
Finished Jul 03 07:19:34 PM PDT 24
Peak memory 209368 kb
Host smart-12e15722-23c7-4c69-9c94-90de0d1ef87f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793121939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.1793121939
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3532495115
Short name T136
Test name
Test status
Simulation time 62927898 ps
CPU time 1.91 seconds
Started Jul 03 07:19:25 PM PDT 24
Finished Jul 03 07:19:33 PM PDT 24
Peak memory 218768 kb
Host smart-a0e3deb0-617e-465f-ab29-83a5aec0a8ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532495115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.3532495115
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1605246134
Short name T140
Test name
Test status
Simulation time 429893516 ps
CPU time 1.92 seconds
Started Jul 03 07:19:25 PM PDT 24
Finished Jul 03 07:19:33 PM PDT 24
Peak memory 221348 kb
Host smart-4709392d-4bd3-45b2-9b8b-2bd16df65efa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605246134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.1605246134
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2181925909
Short name T180
Test name
Test status
Simulation time 39578259 ps
CPU time 0.93 seconds
Started Jul 03 07:19:06 PM PDT 24
Finished Jul 03 07:19:13 PM PDT 24
Peak memory 209288 kb
Host smart-e643ce70-8196-4b80-9961-3130095c85b9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181925909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.2181925909
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2988903883
Short name T156
Test name
Test status
Simulation time 45859890 ps
CPU time 1.39 seconds
Started Jul 03 07:19:05 PM PDT 24
Finished Jul 03 07:19:11 PM PDT 24
Peak memory 217228 kb
Host smart-fa671c7b-cdd2-40c1-aeb8-7167d170010d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988903883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.2988903883
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1439963034
Short name T882
Test name
Test status
Simulation time 25172291 ps
CPU time 0.98 seconds
Started Jul 03 07:19:02 PM PDT 24
Finished Jul 03 07:19:09 PM PDT 24
Peak memory 209808 kb
Host smart-349cf23f-d1c9-45f0-8fe4-b70d8b0e5c9f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439963034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.1439963034
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2188328555
Short name T124
Test name
Test status
Simulation time 64996634 ps
CPU time 1.42 seconds
Started Jul 03 07:19:04 PM PDT 24
Finished Jul 03 07:19:10 PM PDT 24
Peak memory 217712 kb
Host smart-4c650e47-4e54-445c-a07b-209b9c4fd679
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188328555 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.2188328555
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1728783238
Short name T119
Test name
Test status
Simulation time 103761208 ps
CPU time 0.82 seconds
Started Jul 03 07:19:03 PM PDT 24
Finished Jul 03 07:19:10 PM PDT 24
Peak memory 209232 kb
Host smart-3a7b91f0-ed55-4d7b-8a57-8c1049cb4564
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728783238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.1728783238
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.624653654
Short name T972
Test name
Test status
Simulation time 119949548 ps
CPU time 1.03 seconds
Started Jul 03 07:19:03 PM PDT 24
Finished Jul 03 07:19:09 PM PDT 24
Peak memory 208620 kb
Host smart-76477863-343b-42c3-b8b3-6797be74e3bd
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624653654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.lc_ctrl_jtag_alert_test.624653654
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3528471408
Short name T900
Test name
Test status
Simulation time 878267754 ps
CPU time 4.74 seconds
Started Jul 03 07:19:01 PM PDT 24
Finished Jul 03 07:19:11 PM PDT 24
Peak memory 217004 kb
Host smart-87b7dbce-1d40-4e95-92fa-b2d2a61ab560
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528471408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.3528471408
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1446376215
Short name T897
Test name
Test status
Simulation time 2010402530 ps
CPU time 9.38 seconds
Started Jul 03 07:19:02 PM PDT 24
Finished Jul 03 07:19:17 PM PDT 24
Peak memory 217160 kb
Host smart-56d61dfb-6554-4c97-b69b-7b5a5f2548d9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446376215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.1446376215
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.4165786085
Short name T944
Test name
Test status
Simulation time 325997427 ps
CPU time 2.27 seconds
Started Jul 03 07:19:01 PM PDT 24
Finished Jul 03 07:19:09 PM PDT 24
Peak memory 210856 kb
Host smart-c278c4f8-9664-4353-bc48-832a3aebb188
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165786085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.4165786085
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3015915918
Short name T956
Test name
Test status
Simulation time 335415769 ps
CPU time 1.85 seconds
Started Jul 03 07:19:04 PM PDT 24
Finished Jul 03 07:19:11 PM PDT 24
Peak memory 217608 kb
Host smart-02483ffb-4cdb-4c30-98df-6fa0bd37b3d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301591
5918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3015915918
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.47004326
Short name T924
Test name
Test status
Simulation time 33439138 ps
CPU time 1.49 seconds
Started Jul 03 07:18:58 PM PDT 24
Finished Jul 03 07:19:05 PM PDT 24
Peak memory 217104 kb
Host smart-fe4cccf0-0290-483f-9f94-b2d0d75aefad
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47004326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test
+UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 2.lc_ctrl_jtag_csr_rw.47004326
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.716776539
Short name T191
Test name
Test status
Simulation time 30219621 ps
CPU time 1.51 seconds
Started Jul 03 07:19:03 PM PDT 24
Finished Jul 03 07:19:09 PM PDT 24
Peak memory 209308 kb
Host smart-dd4bec8f-e20e-4fcc-af33-2d10a8a091d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716776539 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.716776539
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.144412802
Short name T195
Test name
Test status
Simulation time 680778565 ps
CPU time 1.78 seconds
Started Jul 03 07:19:03 PM PDT 24
Finished Jul 03 07:19:10 PM PDT 24
Peak memory 217448 kb
Host smart-af469c3d-d53f-46a9-8278-4620b1891441
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144412802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
same_csr_outstanding.144412802
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3088918607
Short name T121
Test name
Test status
Simulation time 462840416 ps
CPU time 3.55 seconds
Started Jul 03 07:19:02 PM PDT 24
Finished Jul 03 07:19:11 PM PDT 24
Peak memory 217544 kb
Host smart-9d5001d0-6787-48b1-9005-a54dc252165e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088918607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.3088918607
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1132997743
Short name T971
Test name
Test status
Simulation time 60708891 ps
CPU time 1.09 seconds
Started Jul 03 07:19:05 PM PDT 24
Finished Jul 03 07:19:11 PM PDT 24
Peak memory 209308 kb
Host smart-78380979-2810-40eb-8ee8-f3390969e78f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132997743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.1132997743
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3139344181
Short name T949
Test name
Test status
Simulation time 73690907 ps
CPU time 1.45 seconds
Started Jul 03 07:19:05 PM PDT 24
Finished Jul 03 07:19:12 PM PDT 24
Peak memory 209324 kb
Host smart-20e41aad-15dc-456d-b922-cf2c5e35e738
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139344181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.3139344181
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.4175325047
Short name T188
Test name
Test status
Simulation time 33463101 ps
CPU time 0.94 seconds
Started Jul 03 07:19:05 PM PDT 24
Finished Jul 03 07:19:11 PM PDT 24
Peak memory 209844 kb
Host smart-73a9677d-723d-4cfa-8d8e-a36b7fc1b52d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175325047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.4175325047
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3699986836
Short name T982
Test name
Test status
Simulation time 49804473 ps
CPU time 1.27 seconds
Started Jul 03 07:19:06 PM PDT 24
Finished Jul 03 07:19:13 PM PDT 24
Peak memory 219152 kb
Host smart-56fea3fb-41be-432a-8032-f5dd3e4284ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699986836 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.3699986836
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.85945531
Short name T912
Test name
Test status
Simulation time 47397764 ps
CPU time 0.89 seconds
Started Jul 03 07:19:04 PM PDT 24
Finished Jul 03 07:19:10 PM PDT 24
Peak memory 209256 kb
Host smart-63925e00-65c0-435b-9abf-3036fa7e0c21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85945531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.85945531
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.706764153
Short name T871
Test name
Test status
Simulation time 342988796 ps
CPU time 1.64 seconds
Started Jul 03 07:19:06 PM PDT 24
Finished Jul 03 07:19:13 PM PDT 24
Peak memory 208576 kb
Host smart-202802f9-9998-4f4e-b237-bb5a5f1151bb
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706764153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.lc_ctrl_jtag_alert_test.706764153
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.4026072896
Short name T986
Test name
Test status
Simulation time 866901263 ps
CPU time 3.4 seconds
Started Jul 03 07:19:03 PM PDT 24
Finished Jul 03 07:19:11 PM PDT 24
Peak memory 217012 kb
Host smart-c65dc123-6e51-4bfd-98c5-a7d32bb25ab7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026072896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.4026072896
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1215894418
Short name T994
Test name
Test status
Simulation time 1797596765 ps
CPU time 35.13 seconds
Started Jul 03 07:19:06 PM PDT 24
Finished Jul 03 07:19:47 PM PDT 24
Peak memory 209244 kb
Host smart-f3abedb5-a498-4f3e-a7f1-11261f46ce5d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215894418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.1215894418
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.2790287877
Short name T981
Test name
Test status
Simulation time 408710513 ps
CPU time 3.04 seconds
Started Jul 03 07:19:05 PM PDT 24
Finished Jul 03 07:19:14 PM PDT 24
Peak memory 217452 kb
Host smart-b74e759e-c2d5-4b9d-8993-17ab3af53380
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790287877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.2790287877
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.224841270
Short name T938
Test name
Test status
Simulation time 160297268 ps
CPU time 4.29 seconds
Started Jul 03 07:19:05 PM PDT 24
Finished Jul 03 07:19:15 PM PDT 24
Peak memory 217456 kb
Host smart-2b7a521a-7655-4053-b8a9-d4a152fee567
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224841270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.224841270
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.109790476
Short name T951
Test name
Test status
Simulation time 46626890 ps
CPU time 1.47 seconds
Started Jul 03 07:19:03 PM PDT 24
Finished Jul 03 07:19:10 PM PDT 24
Peak memory 209240 kb
Host smart-84459b6c-bbee-4d53-bb9a-bef16c624085
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109790476 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.109790476
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2225731674
Short name T962
Test name
Test status
Simulation time 37094524 ps
CPU time 1.82 seconds
Started Jul 03 07:19:04 PM PDT 24
Finished Jul 03 07:19:11 PM PDT 24
Peak memory 211392 kb
Host smart-b8651087-3a7a-44de-a21a-45837c2c64d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225731674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.2225731674
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1635777767
Short name T901
Test name
Test status
Simulation time 287179704 ps
CPU time 4.04 seconds
Started Jul 03 07:19:04 PM PDT 24
Finished Jul 03 07:19:13 PM PDT 24
Peak memory 217468 kb
Host smart-5d33e375-981b-4e8f-92b6-0d2d6a5f9b6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635777767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.1635777767
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.4217560898
Short name T976
Test name
Test status
Simulation time 187407885 ps
CPU time 0.99 seconds
Started Jul 03 07:19:07 PM PDT 24
Finished Jul 03 07:19:15 PM PDT 24
Peak memory 209268 kb
Host smart-40336f43-5bbf-415e-aacd-e7f168c142ce
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217560898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.4217560898
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2407832750
Short name T950
Test name
Test status
Simulation time 187573916 ps
CPU time 1.36 seconds
Started Jul 03 07:19:08 PM PDT 24
Finished Jul 03 07:19:16 PM PDT 24
Peak memory 209228 kb
Host smart-8fa2b93b-c80c-4bf6-ab03-ea2c65013559
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407832750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.2407832750
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2674612845
Short name T870
Test name
Test status
Simulation time 18885382 ps
CPU time 1.31 seconds
Started Jul 03 07:19:08 PM PDT 24
Finished Jul 03 07:19:16 PM PDT 24
Peak memory 217880 kb
Host smart-41f335bf-d710-467d-aad9-b869e8d39482
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674612845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.2674612845
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3400516568
Short name T967
Test name
Test status
Simulation time 38345442 ps
CPU time 1.04 seconds
Started Jul 03 07:19:08 PM PDT 24
Finished Jul 03 07:19:15 PM PDT 24
Peak memory 219212 kb
Host smart-77154b7f-eb16-4605-b53f-a813318b6101
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400516568 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.3400516568
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1096326306
Short name T891
Test name
Test status
Simulation time 26648992 ps
CPU time 0.87 seconds
Started Jul 03 07:19:09 PM PDT 24
Finished Jul 03 07:19:18 PM PDT 24
Peak memory 209220 kb
Host smart-92c50f56-2228-492d-9346-746abcf9a48e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096326306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.1096326306
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.275757490
Short name T872
Test name
Test status
Simulation time 84632047 ps
CPU time 0.9 seconds
Started Jul 03 07:19:12 PM PDT 24
Finished Jul 03 07:19:21 PM PDT 24
Peak memory 208556 kb
Host smart-0ead93e2-ba58-40b0-8c50-5847134e2d19
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275757490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.lc_ctrl_jtag_alert_test.275757490
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.50644479
Short name T890
Test name
Test status
Simulation time 1779892821 ps
CPU time 11.66 seconds
Started Jul 03 07:19:09 PM PDT 24
Finished Jul 03 07:19:28 PM PDT 24
Peak memory 209208 kb
Host smart-fb2ad43d-b763-4385-832d-256273f00651
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50644479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 4.lc_ctrl_jtag_csr_aliasing.50644479
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3975514588
Short name T991
Test name
Test status
Simulation time 3872833911 ps
CPU time 21.77 seconds
Started Jul 03 07:19:10 PM PDT 24
Finished Jul 03 07:19:40 PM PDT 24
Peak memory 209228 kb
Host smart-5be9c040-5fd3-4b8e-9509-bd4845be5818
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975514588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.3975514588
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3216137187
Short name T923
Test name
Test status
Simulation time 1078530188 ps
CPU time 2.99 seconds
Started Jul 03 07:19:06 PM PDT 24
Finished Jul 03 07:19:15 PM PDT 24
Peak memory 217468 kb
Host smart-0d8cc56b-5f5e-41e3-ae9c-b83be6eed058
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216137187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.3216137187
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1398209023
Short name T984
Test name
Test status
Simulation time 204936944 ps
CPU time 2.36 seconds
Started Jul 03 07:19:09 PM PDT 24
Finished Jul 03 07:19:20 PM PDT 24
Peak memory 217720 kb
Host smart-7b48b056-5081-458e-a8fa-95ad37b54e8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139820
9023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1398209023
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.219161122
Short name T904
Test name
Test status
Simulation time 117807175 ps
CPU time 1.74 seconds
Started Jul 03 07:19:03 PM PDT 24
Finished Jul 03 07:19:10 PM PDT 24
Peak memory 209236 kb
Host smart-7124b407-a77f-449c-96bd-59747166f99a
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219161122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.219161122
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1681952011
Short name T143
Test name
Test status
Simulation time 63950365 ps
CPU time 1.05 seconds
Started Jul 03 07:19:09 PM PDT 24
Finished Jul 03 07:19:18 PM PDT 24
Peak memory 209332 kb
Host smart-8c9253a5-94e9-4bc9-8bcd-aa883d91eb9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681952011 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.1681952011
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2780670265
Short name T954
Test name
Test status
Simulation time 145729144 ps
CPU time 1.37 seconds
Started Jul 03 07:19:09 PM PDT 24
Finished Jul 03 07:19:18 PM PDT 24
Peak memory 217556 kb
Host smart-2bd39b7e-e643-4849-a6b6-f575d71f7aee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780670265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.2780670265
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1014963545
Short name T936
Test name
Test status
Simulation time 56778487 ps
CPU time 2.27 seconds
Started Jul 03 07:19:06 PM PDT 24
Finished Jul 03 07:19:14 PM PDT 24
Peak memory 217916 kb
Host smart-c01561d4-3318-4c9f-87d2-af9076f21bd3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014963545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.1014963545
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.145481969
Short name T172
Test name
Test status
Simulation time 112967960 ps
CPU time 1.31 seconds
Started Jul 03 07:19:09 PM PDT 24
Finished Jul 03 07:19:19 PM PDT 24
Peak memory 217616 kb
Host smart-2decfa3b-5a0d-48db-bbe6-1b52ca88462b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145481969 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.145481969
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3926086763
Short name T190
Test name
Test status
Simulation time 36167085 ps
CPU time 0.86 seconds
Started Jul 03 07:19:07 PM PDT 24
Finished Jul 03 07:19:15 PM PDT 24
Peak memory 208788 kb
Host smart-beb09a6a-12d2-48c8-9d3d-c2f5668f4de1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926086763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.3926086763
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1242276277
Short name T927
Test name
Test status
Simulation time 483219005 ps
CPU time 2.57 seconds
Started Jul 03 07:19:08 PM PDT 24
Finished Jul 03 07:19:17 PM PDT 24
Peak memory 208812 kb
Host smart-4e081d9a-ff30-48cb-bf8b-1670351a3c2c
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242276277 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.1242276277
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2452892685
Short name T898
Test name
Test status
Simulation time 676559622 ps
CPU time 13.84 seconds
Started Jul 03 07:19:08 PM PDT 24
Finished Jul 03 07:19:30 PM PDT 24
Peak memory 209268 kb
Host smart-cce6f9c1-475f-49be-93b6-de44acf103ec
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452892685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.2452892685
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.4197990118
Short name T988
Test name
Test status
Simulation time 360081022 ps
CPU time 9.69 seconds
Started Jul 03 07:19:07 PM PDT 24
Finished Jul 03 07:19:23 PM PDT 24
Peak memory 209180 kb
Host smart-12e4717f-8f29-4bad-a39d-c8037dfc1de6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197990118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.4197990118
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.422716561
Short name T883
Test name
Test status
Simulation time 113845090 ps
CPU time 3.31 seconds
Started Jul 03 07:19:10 PM PDT 24
Finished Jul 03 07:19:22 PM PDT 24
Peak memory 217424 kb
Host smart-1bdf5153-ef9d-4d23-85a2-044ba45f63d4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422716561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.422716561
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1589717963
Short name T929
Test name
Test status
Simulation time 604001578 ps
CPU time 4.89 seconds
Started Jul 03 07:19:08 PM PDT 24
Finished Jul 03 07:19:20 PM PDT 24
Peak memory 222396 kb
Host smart-3589a03a-2186-4f60-8879-1e5bd0c02c50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158971
7963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1589717963
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.996983769
Short name T945
Test name
Test status
Simulation time 147761561 ps
CPU time 1.11 seconds
Started Jul 03 07:19:10 PM PDT 24
Finished Jul 03 07:19:19 PM PDT 24
Peak memory 209144 kb
Host smart-61fc159b-f159-4b93-9ec3-65fb965538b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996983769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.996983769
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3609008355
Short name T958
Test name
Test status
Simulation time 24653715 ps
CPU time 1.44 seconds
Started Jul 03 07:19:08 PM PDT 24
Finished Jul 03 07:19:17 PM PDT 24
Peak memory 209312 kb
Host smart-72ed9b74-f402-46f3-a96d-e064a1e95f93
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609008355 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.3609008355
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3348847631
Short name T913
Test name
Test status
Simulation time 170193547 ps
CPU time 1.17 seconds
Started Jul 03 07:19:07 PM PDT 24
Finished Jul 03 07:19:14 PM PDT 24
Peak memory 209364 kb
Host smart-f9c70bde-f040-4e03-9512-6f2518156c7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348847631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.3348847631
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2736700684
Short name T932
Test name
Test status
Simulation time 59967462 ps
CPU time 2.3 seconds
Started Jul 03 07:19:08 PM PDT 24
Finished Jul 03 07:19:17 PM PDT 24
Peak memory 217548 kb
Host smart-da0c8242-ca1a-45ac-9418-a2efcc510957
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736700684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.2736700684
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1278393094
Short name T977
Test name
Test status
Simulation time 21374907 ps
CPU time 1.09 seconds
Started Jul 03 07:19:11 PM PDT 24
Finished Jul 03 07:19:21 PM PDT 24
Peak memory 218608 kb
Host smart-6ad7d0a4-2909-4d5e-ace5-9852eb922785
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278393094 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.1278393094
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3045248460
Short name T177
Test name
Test status
Simulation time 13767490 ps
CPU time 0.85 seconds
Started Jul 03 07:19:15 PM PDT 24
Finished Jul 03 07:19:23 PM PDT 24
Peak memory 209084 kb
Host smart-aa8c72dd-a3f3-40ce-9cde-e5829becc297
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045248460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.3045248460
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.859235108
Short name T964
Test name
Test status
Simulation time 170067031 ps
CPU time 0.89 seconds
Started Jul 03 07:19:12 PM PDT 24
Finished Jul 03 07:19:21 PM PDT 24
Peak memory 208516 kb
Host smart-f4c2bb82-1142-42a8-a5fb-938ad0d2d5bc
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859235108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.lc_ctrl_jtag_alert_test.859235108
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3248823206
Short name T880
Test name
Test status
Simulation time 6432889453 ps
CPU time 36.33 seconds
Started Jul 03 07:19:11 PM PDT 24
Finished Jul 03 07:19:56 PM PDT 24
Peak memory 217300 kb
Host smart-16cc864d-2511-4bd2-a3ab-9086381f38fc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248823206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.3248823206
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1874549709
Short name T908
Test name
Test status
Simulation time 242157303 ps
CPU time 2.52 seconds
Started Jul 03 07:19:09 PM PDT 24
Finished Jul 03 07:19:18 PM PDT 24
Peak memory 210604 kb
Host smart-e03cadf5-f573-4098-90c2-48cda6587cbc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874549709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.1874549709
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3437818005
Short name T979
Test name
Test status
Simulation time 238075947 ps
CPU time 1.62 seconds
Started Jul 03 07:19:10 PM PDT 24
Finished Jul 03 07:19:20 PM PDT 24
Peak memory 218728 kb
Host smart-4c76e6f6-2baa-4f19-bf9c-fdccd3e03234
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343781
8005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3437818005
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1507425032
Short name T144
Test name
Test status
Simulation time 1472614533 ps
CPU time 1.54 seconds
Started Jul 03 07:19:10 PM PDT 24
Finished Jul 03 07:19:20 PM PDT 24
Peak memory 209156 kb
Host smart-0ad5a199-9732-460e-b3f1-64f48833513e
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507425032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.1507425032
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.554719564
Short name T985
Test name
Test status
Simulation time 16570812 ps
CPU time 1.25 seconds
Started Jul 03 07:19:11 PM PDT 24
Finished Jul 03 07:19:21 PM PDT 24
Peak memory 209356 kb
Host smart-2894be75-12af-40a3-ba12-01f5097d4fc9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554719564 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.554719564
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3584240188
Short name T931
Test name
Test status
Simulation time 21412396 ps
CPU time 1.29 seconds
Started Jul 03 07:19:14 PM PDT 24
Finished Jul 03 07:19:23 PM PDT 24
Peak memory 217516 kb
Host smart-eaa5c0ec-4093-4d2a-aa69-41069b055380
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584240188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.3584240188
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.486937534
Short name T955
Test name
Test status
Simulation time 29283555 ps
CPU time 2.1 seconds
Started Jul 03 07:19:12 PM PDT 24
Finished Jul 03 07:19:22 PM PDT 24
Peak memory 217596 kb
Host smart-3b73599b-35e5-4513-a421-398828e9d0f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486937534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.486937534
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.720307266
Short name T920
Test name
Test status
Simulation time 15738205 ps
CPU time 1.24 seconds
Started Jul 03 07:19:12 PM PDT 24
Finished Jul 03 07:19:22 PM PDT 24
Peak memory 217616 kb
Host smart-42b3c257-1dd1-4524-81ef-3b9d1ae0793e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720307266 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.720307266
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.717801060
Short name T922
Test name
Test status
Simulation time 17014820 ps
CPU time 0.93 seconds
Started Jul 03 07:19:13 PM PDT 24
Finished Jul 03 07:19:22 PM PDT 24
Peak memory 209260 kb
Host smart-6cefe855-274d-4ef3-8ab1-f4e2964312b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717801060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.717801060
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.4124915565
Short name T887
Test name
Test status
Simulation time 62013479 ps
CPU time 1.24 seconds
Started Jul 03 07:19:13 PM PDT 24
Finished Jul 03 07:19:22 PM PDT 24
Peak memory 209152 kb
Host smart-b974d539-c9fd-4b2f-b895-a7d41620b3c5
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124915565 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.4124915565
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2463356198
Short name T963
Test name
Test status
Simulation time 487296073 ps
CPU time 3.11 seconds
Started Jul 03 07:19:13 PM PDT 24
Finished Jul 03 07:19:24 PM PDT 24
Peak memory 209248 kb
Host smart-2c1c1d17-4b7d-4402-9586-82d801299f4a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463356198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.2463356198
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2970899658
Short name T926
Test name
Test status
Simulation time 4449301559 ps
CPU time 6.44 seconds
Started Jul 03 07:19:16 PM PDT 24
Finished Jul 03 07:19:29 PM PDT 24
Peak memory 209244 kb
Host smart-95d80ebf-6310-4bb0-8ffd-df0290217f4b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970899658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.2970899658
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2852330010
Short name T875
Test name
Test status
Simulation time 967404381 ps
CPU time 2.47 seconds
Started Jul 03 07:19:11 PM PDT 24
Finished Jul 03 07:19:22 PM PDT 24
Peak memory 210772 kb
Host smart-b123428f-d154-43ef-abc9-e21a27894576
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852330010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.2852330010
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1890199354
Short name T980
Test name
Test status
Simulation time 119374459 ps
CPU time 3.89 seconds
Started Jul 03 07:19:13 PM PDT 24
Finished Jul 03 07:19:25 PM PDT 24
Peak memory 218628 kb
Host smart-121882b4-d7c9-40ab-bbd4-1b998c132259
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189019
9354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1890199354
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.40602878
Short name T881
Test name
Test status
Simulation time 148461414 ps
CPU time 2.38 seconds
Started Jul 03 07:19:13 PM PDT 24
Finished Jul 03 07:19:23 PM PDT 24
Peak memory 217348 kb
Host smart-281dbb5d-b37b-4221-8974-8c2e590d4aa5
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40602878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test
+UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 7.lc_ctrl_jtag_csr_rw.40602878
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2238142878
Short name T879
Test name
Test status
Simulation time 75517529 ps
CPU time 1.5 seconds
Started Jul 03 07:19:12 PM PDT 24
Finished Jul 03 07:19:22 PM PDT 24
Peak memory 211432 kb
Host smart-2f69d6b0-13cb-4a0f-9895-a3ff7cfa7783
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238142878 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.2238142878
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.759280716
Short name T194
Test name
Test status
Simulation time 144083368 ps
CPU time 1.43 seconds
Started Jul 03 07:19:11 PM PDT 24
Finished Jul 03 07:19:21 PM PDT 24
Peak memory 217504 kb
Host smart-cfdf2baf-e51c-4c66-ae5f-1e3a97a07f26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759280716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
same_csr_outstanding.759280716
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1281955938
Short name T935
Test name
Test status
Simulation time 416816858 ps
CPU time 3.21 seconds
Started Jul 03 07:19:12 PM PDT 24
Finished Jul 03 07:19:23 PM PDT 24
Peak memory 217524 kb
Host smart-0b9c0f9c-2f69-4208-a4a4-030008aaf23b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281955938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.1281955938
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1414231800
Short name T133
Test name
Test status
Simulation time 143604434 ps
CPU time 1.73 seconds
Started Jul 03 07:19:13 PM PDT 24
Finished Jul 03 07:19:23 PM PDT 24
Peak memory 222016 kb
Host smart-b3faa512-0c4c-4282-9ce5-012e23fc1e14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414231800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.1414231800
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3862152998
Short name T157
Test name
Test status
Simulation time 94515149 ps
CPU time 1.29 seconds
Started Jul 03 07:19:19 PM PDT 24
Finished Jul 03 07:19:27 PM PDT 24
Peak memory 222428 kb
Host smart-1ad5968e-a3ef-4799-a212-21a93ecf0c9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862152998 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.3862152998
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1554187325
Short name T970
Test name
Test status
Simulation time 11780375 ps
CPU time 0.9 seconds
Started Jul 03 07:19:17 PM PDT 24
Finished Jul 03 07:19:25 PM PDT 24
Peak memory 209228 kb
Host smart-68f0e8c0-bb41-4414-9f43-58658630bd5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554187325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.1554187325
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3992407057
Short name T874
Test name
Test status
Simulation time 121105667 ps
CPU time 0.92 seconds
Started Jul 03 07:19:18 PM PDT 24
Finished Jul 03 07:19:25 PM PDT 24
Peak memory 209180 kb
Host smart-83ae232e-1ad1-4df5-90dd-3182d92e3b63
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992407057 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.3992407057
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3919928635
Short name T968
Test name
Test status
Simulation time 2407792932 ps
CPU time 16.8 seconds
Started Jul 03 07:19:12 PM PDT 24
Finished Jul 03 07:19:37 PM PDT 24
Peak memory 209252 kb
Host smart-e863e1fb-7f0e-4811-8994-07d45e50a12c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919928635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.3919928635
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.2634513447
Short name T877
Test name
Test status
Simulation time 2902371765 ps
CPU time 20.23 seconds
Started Jul 03 07:19:13 PM PDT 24
Finished Jul 03 07:19:42 PM PDT 24
Peak memory 209276 kb
Host smart-d1439946-5857-4486-8b16-1ab351d09c98
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634513447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.2634513447
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.960904762
Short name T965
Test name
Test status
Simulation time 248153691 ps
CPU time 3.55 seconds
Started Jul 03 07:19:13 PM PDT 24
Finished Jul 03 07:19:24 PM PDT 24
Peak memory 217456 kb
Host smart-a675d1ed-a43c-4d02-a479-244b510f8e6f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960904762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.960904762
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1714884941
Short name T145
Test name
Test status
Simulation time 1460513915 ps
CPU time 3.49 seconds
Started Jul 03 07:19:17 PM PDT 24
Finished Jul 03 07:19:27 PM PDT 24
Peak memory 217652 kb
Host smart-e995e311-db28-4707-a6f5-6d1d847ae1d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171488
4941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1714884941
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3244366417
Short name T915
Test name
Test status
Simulation time 207626474 ps
CPU time 1.76 seconds
Started Jul 03 07:19:13 PM PDT 24
Finished Jul 03 07:19:22 PM PDT 24
Peak memory 209132 kb
Host smart-a61ace1e-875a-4674-adf3-6c3a8cab4f8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244366417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.3244366417
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.4286204318
Short name T910
Test name
Test status
Simulation time 811578068 ps
CPU time 1.91 seconds
Started Jul 03 07:19:18 PM PDT 24
Finished Jul 03 07:19:27 PM PDT 24
Peak memory 209392 kb
Host smart-f8a76141-7aaa-4f79-b2ef-4c0691bb9b1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286204318 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.4286204318
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.207805130
Short name T909
Test name
Test status
Simulation time 30150104 ps
CPU time 1.07 seconds
Started Jul 03 07:19:22 PM PDT 24
Finished Jul 03 07:19:29 PM PDT 24
Peak memory 209272 kb
Host smart-3fb3c01c-5eb1-444f-a73e-e8aeeecf232e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207805130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
same_csr_outstanding.207805130
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.2879470857
Short name T902
Test name
Test status
Simulation time 170867020 ps
CPU time 3.15 seconds
Started Jul 03 07:19:19 PM PDT 24
Finished Jul 03 07:19:29 PM PDT 24
Peak memory 217504 kb
Host smart-c74bfcbd-c79d-464d-a85b-3a2f415c499b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879470857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.2879470857
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3680666751
Short name T127
Test name
Test status
Simulation time 111613229 ps
CPU time 2.88 seconds
Started Jul 03 07:19:19 PM PDT 24
Finished Jul 03 07:19:28 PM PDT 24
Peak memory 217472 kb
Host smart-cca98ce9-a23a-471c-abd0-6d21732225ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680666751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.3680666751
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.4286509596
Short name T960
Test name
Test status
Simulation time 35384142 ps
CPU time 1.08 seconds
Started Jul 03 07:19:19 PM PDT 24
Finished Jul 03 07:19:26 PM PDT 24
Peak memory 218636 kb
Host smart-387ab1e6-9f44-4744-9643-c08e48cee665
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286509596 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.4286509596
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2572524130
Short name T952
Test name
Test status
Simulation time 89180404 ps
CPU time 0.99 seconds
Started Jul 03 07:19:16 PM PDT 24
Finished Jul 03 07:19:25 PM PDT 24
Peak memory 208600 kb
Host smart-ffa35fbe-03da-45a9-9f0c-0711eefb8dfa
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572524130 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.2572524130
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.328375145
Short name T873
Test name
Test status
Simulation time 485169889 ps
CPU time 4.65 seconds
Started Jul 03 07:19:16 PM PDT 24
Finished Jul 03 07:19:28 PM PDT 24
Peak memory 209004 kb
Host smart-aa236ac6-af68-4bc3-9e4b-4cae5343ff71
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328375145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.328375145
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2882785131
Short name T876
Test name
Test status
Simulation time 1321882672 ps
CPU time 7.2 seconds
Started Jul 03 07:19:17 PM PDT 24
Finished Jul 03 07:19:31 PM PDT 24
Peak memory 209212 kb
Host smart-d8ef6ed2-d7ab-4ac9-85a4-ba8a56a480c7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882785131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.2882785131
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2675086134
Short name T120
Test name
Test status
Simulation time 870333293 ps
CPU time 2.07 seconds
Started Jul 03 07:19:22 PM PDT 24
Finished Jul 03 07:19:29 PM PDT 24
Peak memory 217504 kb
Host smart-12c68bd9-dc8a-4700-bdeb-785795ceba21
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675086134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.2675086134
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2131952989
Short name T978
Test name
Test status
Simulation time 70127622 ps
CPU time 2.21 seconds
Started Jul 03 07:19:22 PM PDT 24
Finished Jul 03 07:19:29 PM PDT 24
Peak memory 219752 kb
Host smart-caab3475-b9be-4faa-b0b5-416f8b30396c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213195
2989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2131952989
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2950372226
Short name T987
Test name
Test status
Simulation time 93459699 ps
CPU time 1.48 seconds
Started Jul 03 07:19:18 PM PDT 24
Finished Jul 03 07:19:26 PM PDT 24
Peak memory 209088 kb
Host smart-99766b9c-0bbb-4c74-82cd-489a35164ce4
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950372226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.2950372226
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1577292306
Short name T894
Test name
Test status
Simulation time 24488421 ps
CPU time 1.23 seconds
Started Jul 03 07:19:22 PM PDT 24
Finished Jul 03 07:19:28 PM PDT 24
Peak memory 209376 kb
Host smart-0e3d033b-3d44-408a-b7cd-ec2916cde750
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577292306 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.1577292306
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.1827981387
Short name T192
Test name
Test status
Simulation time 53617679 ps
CPU time 1.1 seconds
Started Jul 03 07:19:16 PM PDT 24
Finished Jul 03 07:19:25 PM PDT 24
Peak memory 209304 kb
Host smart-ebc758a2-127c-4bd6-89a4-1ebb6af812ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827981387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.1827981387
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.4235540506
Short name T933
Test name
Test status
Simulation time 623966292 ps
CPU time 5.52 seconds
Started Jul 03 07:19:21 PM PDT 24
Finished Jul 03 07:19:33 PM PDT 24
Peak memory 217640 kb
Host smart-1dbc95ce-2ecd-4fc3-b042-7a623a8ca71e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235540506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.4235540506
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.925889829
Short name T685
Test name
Test status
Simulation time 130770035 ps
CPU time 0.93 seconds
Started Jul 03 07:10:29 PM PDT 24
Finished Jul 03 07:10:56 PM PDT 24
Peak memory 208532 kb
Host smart-6282d8bf-e659-4ff4-9ccc-aeb36b47de7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925889829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.925889829
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.700759616
Short name T782
Test name
Test status
Simulation time 477076794 ps
CPU time 17.17 seconds
Started Jul 03 07:10:19 PM PDT 24
Finished Jul 03 07:10:57 PM PDT 24
Peak memory 217732 kb
Host smart-e0729c55-7a35-4916-85cf-254c7d20780c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700759616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.700759616
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.2709787276
Short name T787
Test name
Test status
Simulation time 578669212 ps
CPU time 7.38 seconds
Started Jul 03 07:10:20 PM PDT 24
Finished Jul 03 07:10:49 PM PDT 24
Peak memory 217184 kb
Host smart-544efdb9-c73c-430a-b00d-bd9eacb3bbf7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709787276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.2709787276
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.2693894382
Short name T294
Test name
Test status
Simulation time 3160657047 ps
CPU time 40.9 seconds
Started Jul 03 07:10:19 PM PDT 24
Finished Jul 03 07:11:22 PM PDT 24
Peak memory 219472 kb
Host smart-ccf46cb1-8072-4556-b9a3-0f915035f3c0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693894382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.2693894382
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.1698515014
Short name T477
Test name
Test status
Simulation time 3866004799 ps
CPU time 8.22 seconds
Started Jul 03 07:10:24 PM PDT 24
Finished Jul 03 07:10:55 PM PDT 24
Peak memory 217312 kb
Host smart-326064be-11f2-4cac-ae49-6fda51bedaf5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698515014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.1
698515014
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.4064661126
Short name T462
Test name
Test status
Simulation time 417261846 ps
CPU time 6.35 seconds
Started Jul 03 07:10:20 PM PDT 24
Finished Jul 03 07:10:48 PM PDT 24
Peak memory 217752 kb
Host smart-cc211dc9-0299-4810-9750-72e21f221295
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064661126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.4064661126
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.345017542
Short name T306
Test name
Test status
Simulation time 998006870 ps
CPU time 28.68 seconds
Started Jul 03 07:10:23 PM PDT 24
Finished Jul 03 07:11:16 PM PDT 24
Peak memory 217132 kb
Host smart-5c2e4c61-12ed-4a52-84c2-b689c2ac5157
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345017542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_regwen_during_op.345017542
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.1749009993
Short name T559
Test name
Test status
Simulation time 425027360 ps
CPU time 7.11 seconds
Started Jul 03 07:10:18 PM PDT 24
Finished Jul 03 07:10:46 PM PDT 24
Peak memory 217160 kb
Host smart-834ed21a-1488-4dfb-b2ac-d3b037f17386
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749009993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
1749009993
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.3193026528
Short name T716
Test name
Test status
Simulation time 4933138200 ps
CPU time 47.55 seconds
Started Jul 03 07:10:20 PM PDT 24
Finished Jul 03 07:11:30 PM PDT 24
Peak memory 276688 kb
Host smart-8f37f2bf-3598-49d2-a132-7cf132b54b88
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193026528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.3193026528
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.2307513217
Short name T4
Test name
Test status
Simulation time 389836257 ps
CPU time 10.66 seconds
Started Jul 03 07:10:22 PM PDT 24
Finished Jul 03 07:10:54 PM PDT 24
Peak memory 245820 kb
Host smart-9ad05b02-eb97-4cc2-bee1-72086d385594
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307513217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.2307513217
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.739803310
Short name T420
Test name
Test status
Simulation time 306357270 ps
CPU time 2.78 seconds
Started Jul 03 07:10:18 PM PDT 24
Finished Jul 03 07:10:42 PM PDT 24
Peak memory 222004 kb
Host smart-bfcd7b12-7fd9-43ec-87c8-f3b3675417db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739803310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.739803310
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.333191412
Short name T840
Test name
Test status
Simulation time 232125638 ps
CPU time 12.88 seconds
Started Jul 03 07:10:18 PM PDT 24
Finished Jul 03 07:10:52 PM PDT 24
Peak memory 217208 kb
Host smart-dd4c0d0b-86c5-4028-9ed8-c04c2bb9f561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333191412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.333191412
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.879856789
Short name T102
Test name
Test status
Simulation time 244584517 ps
CPU time 25.21 seconds
Started Jul 03 07:10:33 PM PDT 24
Finished Jul 03 07:11:26 PM PDT 24
Peak memory 269320 kb
Host smart-143c1c51-d9e7-48df-b8b4-8738a523a499
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879856789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.879856789
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.3226493482
Short name T830
Test name
Test status
Simulation time 4684824275 ps
CPU time 26.62 seconds
Started Jul 03 07:10:25 PM PDT 24
Finished Jul 03 07:11:17 PM PDT 24
Peak memory 225632 kb
Host smart-6babb6f5-0329-4555-9205-3a8803d08585
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226493482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.3226493482
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.1393384185
Short name T700
Test name
Test status
Simulation time 505354712 ps
CPU time 9.48 seconds
Started Jul 03 07:10:33 PM PDT 24
Finished Jul 03 07:11:12 PM PDT 24
Peak memory 225492 kb
Host smart-6eab7298-77ea-4118-9a47-20b9172ad3d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393384185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.1393384185
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.2600775299
Short name T437
Test name
Test status
Simulation time 1249566036 ps
CPU time 10.05 seconds
Started Jul 03 07:10:24 PM PDT 24
Finished Jul 03 07:10:57 PM PDT 24
Peak memory 217716 kb
Host smart-a21428d2-04df-4cc5-acec-aa5d2b4a2d0f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600775299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.2
600775299
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.3252565132
Short name T739
Test name
Test status
Simulation time 289246209 ps
CPU time 13.36 seconds
Started Jul 03 07:10:18 PM PDT 24
Finished Jul 03 07:10:52 PM PDT 24
Peak memory 217844 kb
Host smart-dcce8f95-880c-4c49-8903-76b80525df75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252565132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.3252565132
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.2023505876
Short name T606
Test name
Test status
Simulation time 515054216 ps
CPU time 4.56 seconds
Started Jul 03 07:10:20 PM PDT 24
Finished Jul 03 07:10:47 PM PDT 24
Peak memory 217220 kb
Host smart-69200c49-9435-4981-9b50-e2256b89cc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023505876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.2023505876
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.3739047779
Short name T681
Test name
Test status
Simulation time 881267499 ps
CPU time 22.68 seconds
Started Jul 03 07:10:20 PM PDT 24
Finished Jul 03 07:11:05 PM PDT 24
Peak memory 250552 kb
Host smart-da3ad1ab-57af-49d3-b92f-21756a78db3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739047779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.3739047779
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.1874367443
Short name T12
Test name
Test status
Simulation time 104013554 ps
CPU time 3.4 seconds
Started Jul 03 07:10:20 PM PDT 24
Finished Jul 03 07:10:45 PM PDT 24
Peak memory 225960 kb
Host smart-dbce4cab-e0d1-4e94-872a-7a86811fd46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874367443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.1874367443
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.2741228699
Short name T353
Test name
Test status
Simulation time 17808435738 ps
CPU time 315.12 seconds
Started Jul 03 07:10:28 PM PDT 24
Finished Jul 03 07:16:09 PM PDT 24
Peak memory 250732 kb
Host smart-beb2711a-a7b3-44ec-803a-4ee111179bf5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741228699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.2741228699
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.2863734344
Short name T352
Test name
Test status
Simulation time 17263396 ps
CPU time 1.11 seconds
Started Jul 03 07:10:20 PM PDT 24
Finished Jul 03 07:10:43 PM PDT 24
Peak memory 212456 kb
Host smart-d894b205-1c22-4d1e-ab02-6122a0f099a2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863734344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.2863734344
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.1369792242
Short name T429
Test name
Test status
Simulation time 26073334 ps
CPU time 1 seconds
Started Jul 03 07:10:37 PM PDT 24
Finished Jul 03 07:11:09 PM PDT 24
Peak memory 208532 kb
Host smart-2302c05b-7bf7-4818-a2cf-fb7c73ac3dc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369792242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.1369792242
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.3116926761
Short name T413
Test name
Test status
Simulation time 888060382 ps
CPU time 11.53 seconds
Started Jul 03 07:10:35 PM PDT 24
Finished Jul 03 07:11:16 PM PDT 24
Peak memory 217800 kb
Host smart-7ca1b6d7-725f-4d0a-937f-a8d66a9b93f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116926761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.3116926761
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.2950701341
Short name T8
Test name
Test status
Simulation time 145589517 ps
CPU time 1.86 seconds
Started Jul 03 07:10:35 PM PDT 24
Finished Jul 03 07:11:06 PM PDT 24
Peak memory 217212 kb
Host smart-0b832cb9-d8f0-4883-b1d6-6be19234abe4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950701341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.2950701341
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.102264009
Short name T676
Test name
Test status
Simulation time 2339453145 ps
CPU time 22.82 seconds
Started Jul 03 07:10:34 PM PDT 24
Finished Jul 03 07:11:25 PM PDT 24
Peak memory 217792 kb
Host smart-0d6d8c2e-2923-40a3-90ee-60f9089d1d4f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102264009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_err
ors.102264009
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.1473190301
Short name T500
Test name
Test status
Simulation time 118066979 ps
CPU time 3 seconds
Started Jul 03 07:10:42 PM PDT 24
Finished Jul 03 07:11:18 PM PDT 24
Peak memory 217240 kb
Host smart-f01433d6-8ab1-4f53-ae59-04d2ecef75e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473190301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.1
473190301
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.249607202
Short name T398
Test name
Test status
Simulation time 192416805 ps
CPU time 2.39 seconds
Started Jul 03 07:10:34 PM PDT 24
Finished Jul 03 07:11:06 PM PDT 24
Peak memory 217696 kb
Host smart-ed482501-3f9e-4f53-8b04-83deb10bb7a0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249607202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_
prog_failure.249607202
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.1175685569
Short name T868
Test name
Test status
Simulation time 730587317 ps
CPU time 11.07 seconds
Started Jul 03 07:10:33 PM PDT 24
Finished Jul 03 07:11:13 PM PDT 24
Peak memory 217156 kb
Host smart-ada287bb-bc15-49df-a0a0-79b6d3b3aeec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175685569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.1175685569
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.1042354923
Short name T204
Test name
Test status
Simulation time 8226139214 ps
CPU time 7.29 seconds
Started Jul 03 07:10:32 PM PDT 24
Finished Jul 03 07:11:08 PM PDT 24
Peak memory 217216 kb
Host smart-ff5d5912-f445-454a-abd2-841dd7c7d572
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042354923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
1042354923
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.1088291169
Short name T576
Test name
Test status
Simulation time 955924027 ps
CPU time 31.01 seconds
Started Jul 03 07:10:42 PM PDT 24
Finished Jul 03 07:11:46 PM PDT 24
Peak memory 250472 kb
Host smart-0540be90-b19c-4f13-99b1-1aaa0ab31aea
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088291169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.1088291169
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.435226339
Short name T308
Test name
Test status
Simulation time 3627398989 ps
CPU time 30.67 seconds
Started Jul 03 07:10:33 PM PDT 24
Finished Jul 03 07:11:33 PM PDT 24
Peak memory 250520 kb
Host smart-bdc620c1-90c6-4db1-a304-cea8edeb3b99
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435226339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_j
tag_state_post_trans.435226339
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.4033053365
Short name T816
Test name
Test status
Simulation time 135868030 ps
CPU time 2.54 seconds
Started Jul 03 07:10:32 PM PDT 24
Finished Jul 03 07:11:03 PM PDT 24
Peak memory 217768 kb
Host smart-a66076d8-c8d2-490f-a70d-27088308f179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033053365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.4033053365
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.4089176663
Short name T84
Test name
Test status
Simulation time 1115468375 ps
CPU time 20.51 seconds
Started Jul 03 07:10:34 PM PDT 24
Finished Jul 03 07:11:23 PM PDT 24
Peak memory 214140 kb
Host smart-0e76550f-edd9-41fd-af4b-671c82375d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089176663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.4089176663
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.3890780661
Short name T729
Test name
Test status
Simulation time 3833195692 ps
CPU time 14.15 seconds
Started Jul 03 07:10:33 PM PDT 24
Finished Jul 03 07:11:16 PM PDT 24
Peak memory 225568 kb
Host smart-01543b05-523f-4d24-9701-c3981c3b4916
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890780661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.3890780661
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.2743407447
Short name T64
Test name
Test status
Simulation time 581321493 ps
CPU time 6.79 seconds
Started Jul 03 07:10:34 PM PDT 24
Finished Jul 03 07:11:10 PM PDT 24
Peak memory 217704 kb
Host smart-466cc4c7-d819-4cd6-bfcf-45ecc2fbcc37
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743407447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.2
743407447
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.238008099
Short name T662
Test name
Test status
Simulation time 278183917 ps
CPU time 11.11 seconds
Started Jul 03 07:10:35 PM PDT 24
Finished Jul 03 07:11:15 PM PDT 24
Peak memory 225560 kb
Host smart-1a919b31-eb9d-4496-a802-1f50ff3ca61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238008099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.238008099
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.294643045
Short name T458
Test name
Test status
Simulation time 42546519 ps
CPU time 1.46 seconds
Started Jul 03 07:10:28 PM PDT 24
Finished Jul 03 07:10:55 PM PDT 24
Peak memory 213336 kb
Host smart-b59e1e32-d717-40e1-a404-d29fb3118a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294643045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.294643045
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.1782025659
Short name T659
Test name
Test status
Simulation time 1684124167 ps
CPU time 26.96 seconds
Started Jul 03 07:10:28 PM PDT 24
Finished Jul 03 07:11:20 PM PDT 24
Peak memory 250484 kb
Host smart-dfcca790-cdbf-45c4-8273-a876a8a06f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782025659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.1782025659
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.227612844
Short name T821
Test name
Test status
Simulation time 120684432 ps
CPU time 7.91 seconds
Started Jul 03 07:10:31 PM PDT 24
Finished Jul 03 07:11:08 PM PDT 24
Peak memory 250572 kb
Host smart-c80fe321-9b3f-4d1b-a8c2-2e9c9b8ae76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227612844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.227612844
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.1295084309
Short name T631
Test name
Test status
Simulation time 11603261889 ps
CPU time 103.61 seconds
Started Jul 03 07:10:33 PM PDT 24
Finished Jul 03 07:12:45 PM PDT 24
Peak memory 283424 kb
Host smart-1d8ed4a0-dca1-4d48-be8b-c135adc77c28
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295084309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.1295084309
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.2811309329
Short name T154
Test name
Test status
Simulation time 29417573750 ps
CPU time 713.15 seconds
Started Jul 03 07:10:38 PM PDT 24
Finished Jul 03 07:23:02 PM PDT 24
Peak memory 496152 kb
Host smart-591db744-05b8-4965-b1c1-ab448bc5cfc4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2811309329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all_with_rand_reset.2811309329
Directory /workspace/1.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.3798623000
Short name T726
Test name
Test status
Simulation time 24585475 ps
CPU time 0.81 seconds
Started Jul 03 07:10:30 PM PDT 24
Finished Jul 03 07:10:58 PM PDT 24
Peak memory 208544 kb
Host smart-9c3de722-b7e9-42df-8aaf-fdabca728f61
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798623000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.3798623000
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.797332826
Short name T656
Test name
Test status
Simulation time 172228065 ps
CPU time 0.84 seconds
Started Jul 03 07:11:52 PM PDT 24
Finished Jul 03 07:12:10 PM PDT 24
Peak memory 208368 kb
Host smart-cfe99b6b-1bda-4cce-95c8-469a4ea9aa60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797332826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.797332826
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.4287804160
Short name T235
Test name
Test status
Simulation time 626828846 ps
CPU time 16.03 seconds
Started Jul 03 07:11:44 PM PDT 24
Finished Jul 03 07:12:21 PM PDT 24
Peak memory 217776 kb
Host smart-c6b15018-e7b6-42d9-b85d-c04c30294c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287804160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.4287804160
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.44197398
Short name T360
Test name
Test status
Simulation time 1582753705 ps
CPU time 5.98 seconds
Started Jul 03 07:11:50 PM PDT 24
Finished Jul 03 07:12:15 PM PDT 24
Peak memory 217264 kb
Host smart-05e71f58-1f2f-4a30-96b2-40c0db360755
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44197398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.44197398
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.2844800244
Short name T815
Test name
Test status
Simulation time 2578000726 ps
CPU time 43.82 seconds
Started Jul 03 07:11:52 PM PDT 24
Finished Jul 03 07:12:53 PM PDT 24
Peak memory 217668 kb
Host smart-af8a3c70-b451-400a-b453-6a081bf630fd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844800244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.2844800244
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.611628406
Short name T657
Test name
Test status
Simulation time 1002884303 ps
CPU time 4.99 seconds
Started Jul 03 07:11:51 PM PDT 24
Finished Jul 03 07:12:14 PM PDT 24
Peak memory 222652 kb
Host smart-33905dce-c0fa-44b6-827c-973be3ca05e2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611628406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag
_prog_failure.611628406
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.1260831229
Short name T518
Test name
Test status
Simulation time 219406753 ps
CPU time 2.25 seconds
Started Jul 03 07:11:46 PM PDT 24
Finished Jul 03 07:12:09 PM PDT 24
Peak memory 217152 kb
Host smart-cab4a92a-ed46-4d1a-96dd-e1e154ac83ec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260831229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.1260831229
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.258737731
Short name T597
Test name
Test status
Simulation time 1251678152 ps
CPU time 51.52 seconds
Started Jul 03 07:11:47 PM PDT 24
Finished Jul 03 07:12:58 PM PDT 24
Peak memory 266848 kb
Host smart-b9be2c78-e28f-4193-9329-e4808aae6118
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258737731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_state_failure.258737731
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.2612756848
Short name T809
Test name
Test status
Simulation time 1153799176 ps
CPU time 17.55 seconds
Started Jul 03 07:11:48 PM PDT 24
Finished Jul 03 07:12:25 PM PDT 24
Peak memory 250280 kb
Host smart-304fdd4f-7a1e-45ac-8c7b-d2993deaceff
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612756848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.2612756848
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.2959749591
Short name T233
Test name
Test status
Simulation time 116784335 ps
CPU time 2.11 seconds
Started Jul 03 07:11:42 PM PDT 24
Finished Jul 03 07:12:07 PM PDT 24
Peak memory 221528 kb
Host smart-414a4452-162a-4ebe-9077-81f0aa95a43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959749591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.2959749591
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.2743251080
Short name T414
Test name
Test status
Simulation time 1793860147 ps
CPU time 12.49 seconds
Started Jul 03 07:11:47 PM PDT 24
Finished Jul 03 07:12:19 PM PDT 24
Peak memory 218444 kb
Host smart-332c3d57-616c-491b-b668-04f763420b96
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743251080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.2743251080
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.450993320
Short name T522
Test name
Test status
Simulation time 358762665 ps
CPU time 10.42 seconds
Started Jul 03 07:11:52 PM PDT 24
Finished Jul 03 07:12:19 PM PDT 24
Peak memory 225448 kb
Host smart-522985c9-aeb2-4ad5-9b73-020c6fe05d5f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450993320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_di
gest.450993320
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.1260716352
Short name T452
Test name
Test status
Simulation time 1490380742 ps
CPU time 12.61 seconds
Started Jul 03 07:11:46 PM PDT 24
Finished Jul 03 07:12:19 PM PDT 24
Peak memory 217756 kb
Host smart-f9236ad9-5ed0-4bc5-85d0-fae27ca2acd9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260716352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
1260716352
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.2890066843
Short name T303
Test name
Test status
Simulation time 566715209 ps
CPU time 9.73 seconds
Started Jul 03 07:11:45 PM PDT 24
Finished Jul 03 07:12:16 PM PDT 24
Peak memory 225120 kb
Host smart-db7f11ac-8842-4d9f-a9f5-be67c1e15d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890066843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.2890066843
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.3309442353
Short name T453
Test name
Test status
Simulation time 17026248 ps
CPU time 1 seconds
Started Jul 03 07:11:36 PM PDT 24
Finished Jul 03 07:12:02 PM PDT 24
Peak memory 217176 kb
Host smart-bf14a69b-d7f3-4651-a777-7c0228370934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309442353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.3309442353
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.271941735
Short name T207
Test name
Test status
Simulation time 430903068 ps
CPU time 26.24 seconds
Started Jul 03 07:11:45 PM PDT 24
Finished Jul 03 07:12:32 PM PDT 24
Peak memory 250540 kb
Host smart-b5580f1f-03b0-4859-9e55-fb5b83dd73e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271941735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.271941735
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.3557314369
Short name T838
Test name
Test status
Simulation time 991960063 ps
CPU time 4.2 seconds
Started Jul 03 07:11:43 PM PDT 24
Finished Jul 03 07:12:09 PM PDT 24
Peak memory 222340 kb
Host smart-cb3c7d34-a5a1-4e15-891e-31e90ec4f5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557314369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.3557314369
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.2127196046
Short name T584
Test name
Test status
Simulation time 7601983984 ps
CPU time 65.94 seconds
Started Jul 03 07:11:48 PM PDT 24
Finished Jul 03 07:13:14 PM PDT 24
Peak memory 275528 kb
Host smart-483ee297-8c24-42eb-9565-a2b68a8c0cac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127196046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.2127196046
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.3420447072
Short name T583
Test name
Test status
Simulation time 16062196 ps
CPU time 1.18 seconds
Started Jul 03 07:11:39 PM PDT 24
Finished Jul 03 07:12:04 PM PDT 24
Peak memory 211400 kb
Host smart-1186f5f2-dad6-4467-9a8c-4a98ee09558c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420447072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.3420447072
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.1657455179
Short name T614
Test name
Test status
Simulation time 63268570 ps
CPU time 0.81 seconds
Started Jul 03 07:11:57 PM PDT 24
Finished Jul 03 07:12:13 PM PDT 24
Peak memory 208504 kb
Host smart-947d680c-f6a8-4b59-ad84-6d6eb0fc8fac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657455179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.1657455179
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.1048063445
Short name T531
Test name
Test status
Simulation time 669615967 ps
CPU time 6.92 seconds
Started Jul 03 07:11:56 PM PDT 24
Finished Jul 03 07:12:17 PM PDT 24
Peak memory 217368 kb
Host smart-ea847a8b-5b4e-4808-836b-e85b4c37b72a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048063445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.1048063445
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.1763349854
Short name T471
Test name
Test status
Simulation time 14060646031 ps
CPU time 88.77 seconds
Started Jul 03 07:11:51 PM PDT 24
Finished Jul 03 07:13:38 PM PDT 24
Peak memory 219476 kb
Host smart-953a82ca-6d59-4681-83ce-444fd5082f53
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763349854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.1763349854
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.3443800996
Short name T373
Test name
Test status
Simulation time 3233325031 ps
CPU time 10.45 seconds
Started Jul 03 07:11:51 PM PDT 24
Finished Jul 03 07:12:19 PM PDT 24
Peak memory 224452 kb
Host smart-028d9a1a-8c5e-4bd0-9d99-2f2035cec1e4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443800996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.3443800996
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.2439001091
Short name T94
Test name
Test status
Simulation time 140973762 ps
CPU time 1.82 seconds
Started Jul 03 07:11:51 PM PDT 24
Finished Jul 03 07:12:11 PM PDT 24
Peak memory 217152 kb
Host smart-e56f46cb-1610-47b2-bbc7-d522fb69ed32
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439001091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.2439001091
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.1883054895
Short name T382
Test name
Test status
Simulation time 7160460302 ps
CPU time 47.01 seconds
Started Jul 03 07:11:50 PM PDT 24
Finished Jul 03 07:12:56 PM PDT 24
Peak memory 275068 kb
Host smart-e320de75-3cb2-4895-ba7c-339bcef197a7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883054895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.1883054895
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.1605315346
Short name T539
Test name
Test status
Simulation time 551865713 ps
CPU time 14.19 seconds
Started Jul 03 07:11:56 PM PDT 24
Finished Jul 03 07:12:25 PM PDT 24
Peak memory 250564 kb
Host smart-1477cab1-09f4-4ba0-9d11-81988bde6b1d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605315346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.1605315346
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.3543441600
Short name T329
Test name
Test status
Simulation time 35693104 ps
CPU time 2.12 seconds
Started Jul 03 07:11:54 PM PDT 24
Finished Jul 03 07:12:12 PM PDT 24
Peak memory 221592 kb
Host smart-2eeaa3bc-838a-41fc-ac7b-43af0bb61616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543441600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.3543441600
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.2857524094
Short name T65
Test name
Test status
Simulation time 384023618 ps
CPU time 17.05 seconds
Started Jul 03 07:11:51 PM PDT 24
Finished Jul 03 07:12:26 PM PDT 24
Peak memory 219452 kb
Host smart-8369ef41-b71b-45c0-b912-5ef8aaf2a337
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857524094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.2857524094
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.3868642427
Short name T227
Test name
Test status
Simulation time 304569232 ps
CPU time 8.79 seconds
Started Jul 03 07:12:02 PM PDT 24
Finished Jul 03 07:12:24 PM PDT 24
Peak memory 225652 kb
Host smart-6547386f-b381-47f6-b37f-feb45620595d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868642427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.3868642427
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.20563105
Short name T250
Test name
Test status
Simulation time 1314169232 ps
CPU time 11.43 seconds
Started Jul 03 07:11:54 PM PDT 24
Finished Jul 03 07:12:21 PM PDT 24
Peak memory 217712 kb
Host smart-54a16695-a914-46c9-98a4-189d6fdf637e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20563105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.20563105
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.2050964522
Short name T387
Test name
Test status
Simulation time 327218201 ps
CPU time 8.6 seconds
Started Jul 03 07:11:51 PM PDT 24
Finished Jul 03 07:12:17 PM PDT 24
Peak memory 225592 kb
Host smart-14f11fb4-7ebf-4e60-87d4-9ae1687d35d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050964522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.2050964522
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.3769970174
Short name T81
Test name
Test status
Simulation time 52675346 ps
CPU time 1.3 seconds
Started Jul 03 07:11:52 PM PDT 24
Finished Jul 03 07:12:10 PM PDT 24
Peak memory 213252 kb
Host smart-18635f9c-10cd-4bcc-a504-0416cc5da3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769970174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.3769970174
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.4158774809
Short name T442
Test name
Test status
Simulation time 243780354 ps
CPU time 23.49 seconds
Started Jul 03 07:11:52 PM PDT 24
Finished Jul 03 07:12:33 PM PDT 24
Peak memory 245536 kb
Host smart-03697cad-0037-4727-9c85-95e8fc274006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158774809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.4158774809
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.2498474331
Short name T445
Test name
Test status
Simulation time 157149555 ps
CPU time 10.38 seconds
Started Jul 03 07:11:51 PM PDT 24
Finished Jul 03 07:12:19 PM PDT 24
Peak memory 250616 kb
Host smart-25db0a64-d68e-4315-8f8d-d249b6247194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498474331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.2498474331
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.492860351
Short name T512
Test name
Test status
Simulation time 7279956661 ps
CPU time 247.5 seconds
Started Jul 03 07:11:57 PM PDT 24
Finished Jul 03 07:16:20 PM PDT 24
Peak memory 283360 kb
Host smart-eba91982-98ed-4a2a-980c-4b9485ee9644
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492860351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.492860351
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.2533823348
Short name T246
Test name
Test status
Simulation time 27760881 ps
CPU time 0.98 seconds
Started Jul 03 07:11:51 PM PDT 24
Finished Jul 03 07:12:10 PM PDT 24
Peak memory 217344 kb
Host smart-c05e7f82-4901-47c3-9a7a-19fd6e233645
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533823348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.2533823348
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.3783158943
Short name T169
Test name
Test status
Simulation time 94333102 ps
CPU time 0.97 seconds
Started Jul 03 07:12:05 PM PDT 24
Finished Jul 03 07:12:18 PM PDT 24
Peak memory 208628 kb
Host smart-11f9349c-a000-4042-a36b-0e2173df32ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783158943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.3783158943
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.82756120
Short name T459
Test name
Test status
Simulation time 997268289 ps
CPU time 11.67 seconds
Started Jul 03 07:11:59 PM PDT 24
Finished Jul 03 07:12:24 PM PDT 24
Peak memory 225564 kb
Host smart-f1000d4d-fb56-43ee-9f42-6b13d9c3e358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82756120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.82756120
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.2199612639
Short name T28
Test name
Test status
Simulation time 1174987202 ps
CPU time 12.6 seconds
Started Jul 03 07:11:56 PM PDT 24
Finished Jul 03 07:12:23 PM PDT 24
Peak memory 217184 kb
Host smart-01a14304-fa42-4cd9-b426-fa2b305ab8e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199612639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.2199612639
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.2725600015
Short name T242
Test name
Test status
Simulation time 1018985801 ps
CPU time 17.7 seconds
Started Jul 03 07:11:56 PM PDT 24
Finished Jul 03 07:12:29 PM PDT 24
Peak memory 217816 kb
Host smart-a28bbc73-f99b-4dc2-b262-4bd2055e6752
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725600015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.2725600015
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.1788609354
Short name T21
Test name
Test status
Simulation time 1135464915 ps
CPU time 4.77 seconds
Started Jul 03 07:11:55 PM PDT 24
Finished Jul 03 07:12:15 PM PDT 24
Peak memory 217740 kb
Host smart-1511cfa0-8767-4439-b658-b751f2abba63
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788609354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.1788609354
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.3467695649
Short name T73
Test name
Test status
Simulation time 475094821 ps
CPU time 2.29 seconds
Started Jul 03 07:11:58 PM PDT 24
Finished Jul 03 07:12:15 PM PDT 24
Peak memory 217128 kb
Host smart-73fd089c-55a6-4aff-99c0-5f1c8c3780e4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467695649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.3467695649
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.3741915005
Short name T637
Test name
Test status
Simulation time 8077574770 ps
CPU time 65.11 seconds
Started Jul 03 07:12:03 PM PDT 24
Finished Jul 03 07:13:20 PM PDT 24
Peak memory 266924 kb
Host smart-7e486062-17eb-4851-8bb3-1d0f9756021a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741915005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.3741915005
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.665265791
Short name T587
Test name
Test status
Simulation time 1716525759 ps
CPU time 17.04 seconds
Started Jul 03 07:11:59 PM PDT 24
Finished Jul 03 07:12:30 PM PDT 24
Peak memory 250468 kb
Host smart-395c3940-2f9a-40fe-9c90-e632c282ba27
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665265791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_
jtag_state_post_trans.665265791
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.1618579941
Short name T680
Test name
Test status
Simulation time 99703804 ps
CPU time 2.38 seconds
Started Jul 03 07:11:57 PM PDT 24
Finished Jul 03 07:12:14 PM PDT 24
Peak memory 217744 kb
Host smart-a0996bcb-3fbd-4f1b-b0f9-afcd36bbbb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618579941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.1618579941
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.1517730398
Short name T54
Test name
Test status
Simulation time 288958259 ps
CPU time 14.47 seconds
Started Jul 03 07:12:02 PM PDT 24
Finished Jul 03 07:12:30 PM PDT 24
Peak memory 225592 kb
Host smart-bf66fc2f-a8c4-4182-866a-987fa31e4eba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517730398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.1517730398
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.4026339615
Short name T533
Test name
Test status
Simulation time 8616088297 ps
CPU time 12.1 seconds
Started Jul 03 07:12:01 PM PDT 24
Finished Jul 03 07:12:26 PM PDT 24
Peak memory 225596 kb
Host smart-a18df132-e04a-410b-970a-29aeacf3d8bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026339615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.4026339615
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.1830799599
Short name T214
Test name
Test status
Simulation time 522548172 ps
CPU time 7.97 seconds
Started Jul 03 07:11:59 PM PDT 24
Finished Jul 03 07:12:21 PM PDT 24
Peak memory 217684 kb
Host smart-0504f831-9fc3-414b-9851-8d3eac70fe7b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830799599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
1830799599
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.3085668148
Short name T390
Test name
Test status
Simulation time 617328168 ps
CPU time 11.49 seconds
Started Jul 03 07:11:59 PM PDT 24
Finished Jul 03 07:12:25 PM PDT 24
Peak memory 217840 kb
Host smart-d0959430-d9d1-474f-9192-338bb8473789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085668148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.3085668148
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.3587695202
Short name T86
Test name
Test status
Simulation time 309660989 ps
CPU time 3.57 seconds
Started Jul 03 07:11:58 PM PDT 24
Finished Jul 03 07:12:16 PM PDT 24
Peak memory 217328 kb
Host smart-4a1d4c73-e42d-4c36-90d4-c056d21fd792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587695202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.3587695202
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.1987284188
Short name T698
Test name
Test status
Simulation time 1115613251 ps
CPU time 28.89 seconds
Started Jul 03 07:11:56 PM PDT 24
Finished Jul 03 07:12:41 PM PDT 24
Peak memory 250540 kb
Host smart-926245de-771f-4598-ab68-8498d61a78b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987284188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.1987284188
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.3364885869
Short name T580
Test name
Test status
Simulation time 648315008 ps
CPU time 12.22 seconds
Started Jul 03 07:11:58 PM PDT 24
Finished Jul 03 07:12:25 PM PDT 24
Peak memory 250516 kb
Host smart-db489e73-9444-42ef-a767-bac7bf9a7252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364885869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.3364885869
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.249048201
Short name T52
Test name
Test status
Simulation time 23752560363 ps
CPU time 101.82 seconds
Started Jul 03 07:12:01 PM PDT 24
Finished Jul 03 07:13:56 PM PDT 24
Peak memory 277220 kb
Host smart-88249248-5d9d-4e3b-b166-9ad3f932fdc1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249048201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.249048201
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.3628091815
Short name T109
Test name
Test status
Simulation time 163482438590 ps
CPU time 446.78 seconds
Started Jul 03 07:12:01 PM PDT 24
Finished Jul 03 07:19:40 PM PDT 24
Peak memory 421692 kb
Host smart-fc53661b-7362-4875-b320-d2693f24a50d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3628091815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all_with_rand_reset.3628091815
Directory /workspace/12.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.3164250265
Short name T803
Test name
Test status
Simulation time 14509486 ps
CPU time 0.98 seconds
Started Jul 03 07:12:02 PM PDT 24
Finished Jul 03 07:12:15 PM PDT 24
Peak memory 211384 kb
Host smart-cdb8f187-cf1d-48c9-a822-4fb4ab3ace66
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164250265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.3164250265
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.3579928317
Short name T799
Test name
Test status
Simulation time 313432061 ps
CPU time 14.01 seconds
Started Jul 03 07:12:00 PM PDT 24
Finished Jul 03 07:12:28 PM PDT 24
Peak memory 217776 kb
Host smart-6679bfe9-bdd6-4764-8adb-367d4e8ad242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579928317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.3579928317
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.3680813609
Short name T563
Test name
Test status
Simulation time 2854798285 ps
CPU time 7.16 seconds
Started Jul 03 07:12:06 PM PDT 24
Finished Jul 03 07:12:25 PM PDT 24
Peak memory 217276 kb
Host smart-7876ee2e-af2f-4003-9020-c7ed919238fd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680813609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.3680813609
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.3289247243
Short name T264
Test name
Test status
Simulation time 12030593876 ps
CPU time 39.24 seconds
Started Jul 03 07:12:07 PM PDT 24
Finished Jul 03 07:12:57 PM PDT 24
Peak memory 219272 kb
Host smart-ad70e0f5-22a7-4ff2-ac27-b8f9a606b067
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289247243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.3289247243
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.4127005192
Short name T554
Test name
Test status
Simulation time 1048643756 ps
CPU time 5.36 seconds
Started Jul 03 07:12:06 PM PDT 24
Finished Jul 03 07:12:23 PM PDT 24
Peak memory 217744 kb
Host smart-0745eee5-538b-4a5a-bf42-8da0effa0364
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127005192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.4127005192
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.154896169
Short name T636
Test name
Test status
Simulation time 5708264158 ps
CPU time 7.61 seconds
Started Jul 03 07:12:06 PM PDT 24
Finished Jul 03 07:12:25 PM PDT 24
Peak memory 217216 kb
Host smart-048c8b99-eda0-431e-9b97-070a316f0b1e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154896169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke.
154896169
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.1888463830
Short name T260
Test name
Test status
Simulation time 3048363288 ps
CPU time 62.22 seconds
Started Jul 03 07:12:10 PM PDT 24
Finished Jul 03 07:13:22 PM PDT 24
Peak memory 253904 kb
Host smart-b7e36a90-5eca-4369-8135-2a7e77533e89
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888463830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.1888463830
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.2358595247
Short name T562
Test name
Test status
Simulation time 4912974799 ps
CPU time 6.56 seconds
Started Jul 03 07:12:06 PM PDT 24
Finished Jul 03 07:12:24 PM PDT 24
Peak memory 222980 kb
Host smart-c7d662d9-6ad0-4f44-b9cc-3f7c9e02ff77
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358595247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.2358595247
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.2431771937
Short name T708
Test name
Test status
Simulation time 80785684 ps
CPU time 3.63 seconds
Started Jul 03 07:12:00 PM PDT 24
Finished Jul 03 07:12:17 PM PDT 24
Peak memory 217788 kb
Host smart-b40f119f-2e81-4b6c-a812-3780e78d9aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431771937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.2431771937
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.2216911995
Short name T485
Test name
Test status
Simulation time 253002898 ps
CPU time 12.26 seconds
Started Jul 03 07:12:06 PM PDT 24
Finished Jul 03 07:12:30 PM PDT 24
Peak memory 217876 kb
Host smart-df06f87a-ed3b-4b1c-aa65-a05d3b0af1e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216911995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.2216911995
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.3871201474
Short name T612
Test name
Test status
Simulation time 1537441882 ps
CPU time 11.25 seconds
Started Jul 03 07:12:05 PM PDT 24
Finished Jul 03 07:12:28 PM PDT 24
Peak memory 225492 kb
Host smart-77405d26-3f40-4447-ae66-c8acdc02b3e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871201474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.3871201474
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.4104755008
Short name T1
Test name
Test status
Simulation time 193637960 ps
CPU time 7.55 seconds
Started Jul 03 07:12:10 PM PDT 24
Finished Jul 03 07:12:28 PM PDT 24
Peak memory 217740 kb
Host smart-9a23537c-b956-4322-a5b8-83cf1d74d556
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104755008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
4104755008
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.2755790841
Short name T625
Test name
Test status
Simulation time 391778662 ps
CPU time 8.14 seconds
Started Jul 03 07:12:00 PM PDT 24
Finished Jul 03 07:12:22 PM PDT 24
Peak memory 224544 kb
Host smart-945e8c8f-3fd5-401f-8203-94af9ec6620f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755790841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.2755790841
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.2601482249
Short name T229
Test name
Test status
Simulation time 105233839 ps
CPU time 6.96 seconds
Started Jul 03 07:12:01 PM PDT 24
Finished Jul 03 07:12:20 PM PDT 24
Peak memory 217208 kb
Host smart-0bb94cf3-d709-441b-a77b-5fa46242c9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601482249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.2601482249
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.1274758179
Short name T493
Test name
Test status
Simulation time 753438694 ps
CPU time 24.09 seconds
Started Jul 03 07:12:01 PM PDT 24
Finished Jul 03 07:12:38 PM PDT 24
Peak memory 250616 kb
Host smart-5eb41049-a024-448f-bc45-8f9d7470b91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274758179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.1274758179
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.1943482681
Short name T244
Test name
Test status
Simulation time 325971165 ps
CPU time 8.34 seconds
Started Jul 03 07:12:05 PM PDT 24
Finished Jul 03 07:12:25 PM PDT 24
Peak memory 250540 kb
Host smart-b5a4ab2e-fa4d-4ac7-8142-a3bc445aec0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943482681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.1943482681
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.1799766816
Short name T605
Test name
Test status
Simulation time 109493495700 ps
CPU time 427.79 seconds
Started Jul 03 07:12:11 PM PDT 24
Finished Jul 03 07:19:29 PM PDT 24
Peak memory 242044 kb
Host smart-b213f7f8-972d-480f-96f7-22e04b45c880
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799766816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.1799766816
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.1056107541
Short name T48
Test name
Test status
Simulation time 121638242 ps
CPU time 1.05 seconds
Started Jul 03 07:12:01 PM PDT 24
Finished Jul 03 07:12:15 PM PDT 24
Peak memory 211396 kb
Host smart-b26a2a91-28f3-4e68-a156-c820fa6fd422
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056107541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.1056107541
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.982325377
Short name T487
Test name
Test status
Simulation time 105858595 ps
CPU time 1.06 seconds
Started Jul 03 07:12:12 PM PDT 24
Finished Jul 03 07:12:22 PM PDT 24
Peak memory 208532 kb
Host smart-24b5d7c2-c324-4172-925e-47a9fe225a87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982325377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.982325377
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.2764323416
Short name T540
Test name
Test status
Simulation time 377988402 ps
CPU time 13.5 seconds
Started Jul 03 07:12:10 PM PDT 24
Finished Jul 03 07:12:34 PM PDT 24
Peak memory 225568 kb
Host smart-3cd7747c-932a-4bb2-a9c1-6c1a5d68b26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764323416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.2764323416
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.3972927670
Short name T423
Test name
Test status
Simulation time 591119338 ps
CPU time 6.46 seconds
Started Jul 03 07:12:11 PM PDT 24
Finished Jul 03 07:12:27 PM PDT 24
Peak memory 216940 kb
Host smart-c62c2eb3-9c11-41a7-b4e1-cbf3be97db6c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972927670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.3972927670
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.2826074460
Short name T31
Test name
Test status
Simulation time 5151361127 ps
CPU time 33.9 seconds
Started Jul 03 07:12:15 PM PDT 24
Finished Jul 03 07:12:58 PM PDT 24
Peak memory 217772 kb
Host smart-4001af16-0029-431e-b247-f9bd761fbde4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826074460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.2826074460
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.3366803924
Short name T663
Test name
Test status
Simulation time 1011986416 ps
CPU time 7.95 seconds
Started Jul 03 07:12:13 PM PDT 24
Finished Jul 03 07:12:30 PM PDT 24
Peak memory 217696 kb
Host smart-6f37f858-59ec-416e-8b74-24bc93c16fb6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366803924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.3366803924
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.3704902559
Short name T718
Test name
Test status
Simulation time 242558316 ps
CPU time 4.45 seconds
Started Jul 03 07:12:12 PM PDT 24
Finished Jul 03 07:12:26 PM PDT 24
Peak memory 217340 kb
Host smart-72731d43-1f52-4f8c-9b0d-26d2b9ca4ca6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704902559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.3704902559
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.1773829835
Short name T528
Test name
Test status
Simulation time 1724791057 ps
CPU time 15.14 seconds
Started Jul 03 07:12:12 PM PDT 24
Finished Jul 03 07:12:37 PM PDT 24
Peak memory 218384 kb
Host smart-0d8bea6f-df6f-4684-a5ef-ee349fd7f95f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773829835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.1773829835
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.3089305093
Short name T370
Test name
Test status
Simulation time 17029667 ps
CPU time 1.69 seconds
Started Jul 03 07:12:13 PM PDT 24
Finished Jul 03 07:12:24 PM PDT 24
Peak memory 221216 kb
Host smart-a04e1451-ff7a-4fec-9b6d-71eb2c2a757c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089305093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.3089305093
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.143143038
Short name T833
Test name
Test status
Simulation time 361609527 ps
CPU time 16.29 seconds
Started Jul 03 07:12:12 PM PDT 24
Finished Jul 03 07:12:39 PM PDT 24
Peak memory 225908 kb
Host smart-542b20d0-18d2-4133-b219-d91a601bd884
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143143038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.143143038
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.4126537675
Short name T236
Test name
Test status
Simulation time 299560825 ps
CPU time 12.48 seconds
Started Jul 03 07:12:11 PM PDT 24
Finished Jul 03 07:12:33 PM PDT 24
Peak memory 225492 kb
Host smart-e413a6ec-d948-42bb-af51-d944d72b60fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126537675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.4126537675
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.2720322567
Short name T741
Test name
Test status
Simulation time 344513191 ps
CPU time 8.41 seconds
Started Jul 03 07:12:10 PM PDT 24
Finished Jul 03 07:12:28 PM PDT 24
Peak memory 225488 kb
Host smart-03ab23f4-86e9-44dd-93ff-0629828f30e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720322567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
2720322567
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.449191463
Short name T847
Test name
Test status
Simulation time 1037053933 ps
CPU time 7.99 seconds
Started Jul 03 07:12:11 PM PDT 24
Finished Jul 03 07:12:30 PM PDT 24
Peak memory 224800 kb
Host smart-47d75377-6d72-47ec-8459-5ed27376dca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449191463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.449191463
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.2222174484
Short name T730
Test name
Test status
Simulation time 206368805 ps
CPU time 2.28 seconds
Started Jul 03 07:12:06 PM PDT 24
Finished Jul 03 07:12:20 PM PDT 24
Peak memory 213856 kb
Host smart-a7cad37d-acfd-4fcb-b636-2eade7550896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222174484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.2222174484
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.2199495145
Short name T206
Test name
Test status
Simulation time 450590773 ps
CPU time 23.29 seconds
Started Jul 03 07:12:09 PM PDT 24
Finished Jul 03 07:12:43 PM PDT 24
Peak memory 250620 kb
Host smart-f1f2c307-b54c-4b2e-a839-8c0c050449e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199495145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.2199495145
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.768641906
Short name T778
Test name
Test status
Simulation time 189626002 ps
CPU time 3.23 seconds
Started Jul 03 07:12:10 PM PDT 24
Finished Jul 03 07:12:23 PM PDT 24
Peak memory 221696 kb
Host smart-9173d58f-c5e7-4a14-a712-08b9e9188758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768641906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.768641906
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.1618609113
Short name T16
Test name
Test status
Simulation time 13115185827 ps
CPU time 306.03 seconds
Started Jul 03 07:12:12 PM PDT 24
Finished Jul 03 07:17:28 PM PDT 24
Peak memory 275704 kb
Host smart-7f181ee1-df11-47b7-bf6a-22c1613ca795
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618609113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.1618609113
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.1009177875
Short name T369
Test name
Test status
Simulation time 31919942 ps
CPU time 0.89 seconds
Started Jul 03 07:12:07 PM PDT 24
Finished Jul 03 07:12:19 PM PDT 24
Peak memory 208452 kb
Host smart-9b1b2e9e-11e1-4d46-b398-420e2887a9f5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009177875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.1009177875
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.1762564104
Short name T295
Test name
Test status
Simulation time 68921174 ps
CPU time 0.87 seconds
Started Jul 03 07:12:15 PM PDT 24
Finished Jul 03 07:12:25 PM PDT 24
Peak memory 208400 kb
Host smart-eb7d35af-d281-447c-af16-2cb2f7874612
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762564104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.1762564104
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.3826413826
Short name T44
Test name
Test status
Simulation time 395357377 ps
CPU time 11.05 seconds
Started Jul 03 07:12:18 PM PDT 24
Finished Jul 03 07:12:38 PM PDT 24
Peak memory 225572 kb
Host smart-29e7d812-da40-4a6d-86c9-e0d2d59fc234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826413826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.3826413826
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.3772947033
Short name T719
Test name
Test status
Simulation time 909711560 ps
CPU time 3.66 seconds
Started Jul 03 07:12:14 PM PDT 24
Finished Jul 03 07:12:28 PM PDT 24
Peak memory 217204 kb
Host smart-f351401e-62d3-4c61-87f4-7a42736effe6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772947033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.3772947033
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.683428589
Short name T750
Test name
Test status
Simulation time 4577356770 ps
CPU time 115.03 seconds
Started Jul 03 07:12:15 PM PDT 24
Finished Jul 03 07:14:19 PM PDT 24
Peak memory 219424 kb
Host smart-d87204cd-cdef-44fb-8cba-53d165ba5253
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683428589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_er
rors.683428589
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.2925161769
Short name T834
Test name
Test status
Simulation time 319591472 ps
CPU time 4.39 seconds
Started Jul 03 07:12:19 PM PDT 24
Finished Jul 03 07:12:33 PM PDT 24
Peak memory 222440 kb
Host smart-a2f85245-ba63-4317-aed9-b7b8acd33f96
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925161769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.2925161769
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.4241001717
Short name T784
Test name
Test status
Simulation time 711655643 ps
CPU time 8.97 seconds
Started Jul 03 07:12:17 PM PDT 24
Finished Jul 03 07:12:35 PM PDT 24
Peak memory 217136 kb
Host smart-fb31e097-8020-44bd-a89b-ea6b2d2d987a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241001717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.4241001717
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.3881412012
Short name T111
Test name
Test status
Simulation time 6283018263 ps
CPU time 37.73 seconds
Started Jul 03 07:12:19 PM PDT 24
Finished Jul 03 07:13:06 PM PDT 24
Peak memory 269032 kb
Host smart-aa60355c-c6ec-4f56-9df1-5b25baf8b597
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881412012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.3881412012
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.1695358976
Short name T725
Test name
Test status
Simulation time 2804877338 ps
CPU time 14.84 seconds
Started Jul 03 07:12:17 PM PDT 24
Finished Jul 03 07:12:41 PM PDT 24
Peak memory 250072 kb
Host smart-4269bcda-f5c5-4701-8686-0c02c0c77860
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695358976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.1695358976
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.1473561297
Short name T627
Test name
Test status
Simulation time 264386418 ps
CPU time 3.46 seconds
Started Jul 03 07:12:18 PM PDT 24
Finished Jul 03 07:12:30 PM PDT 24
Peak memory 222080 kb
Host smart-f29012b2-f806-4849-a1ea-9b1af2d8d08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473561297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.1473561297
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.493891560
Short name T756
Test name
Test status
Simulation time 3905036650 ps
CPU time 22.11 seconds
Started Jul 03 07:12:20 PM PDT 24
Finished Jul 03 07:12:51 PM PDT 24
Peak memory 218576 kb
Host smart-9683f8fa-c409-4e72-a512-141edacf3aa5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493891560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.493891560
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.1838249856
Short name T746
Test name
Test status
Simulation time 354647333 ps
CPU time 9.7 seconds
Started Jul 03 07:12:19 PM PDT 24
Finished Jul 03 07:12:38 PM PDT 24
Peak memory 225488 kb
Host smart-060908fe-17c2-41fb-9805-f2ae727e1256
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838249856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.1838249856
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.1726477174
Short name T258
Test name
Test status
Simulation time 316458350 ps
CPU time 12.78 seconds
Started Jul 03 07:12:16 PM PDT 24
Finished Jul 03 07:12:38 PM PDT 24
Peak memory 217748 kb
Host smart-db1d63be-4069-42ef-8b16-575d2f681010
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726477174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
1726477174
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.2679202608
Short name T727
Test name
Test status
Simulation time 1222290174 ps
CPU time 8.2 seconds
Started Jul 03 07:12:16 PM PDT 24
Finished Jul 03 07:12:33 PM PDT 24
Peak memory 217868 kb
Host smart-bcaaf6e5-7b0d-4c06-a0b3-1886166af651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679202608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.2679202608
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.397147744
Short name T618
Test name
Test status
Simulation time 181603479 ps
CPU time 2.3 seconds
Started Jul 03 07:12:13 PM PDT 24
Finished Jul 03 07:12:25 PM PDT 24
Peak memory 223016 kb
Host smart-e1d15e9e-52a4-4f10-a36f-6ca8d6305c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397147744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.397147744
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.1722746896
Short name T362
Test name
Test status
Simulation time 297991258 ps
CPU time 25.39 seconds
Started Jul 03 07:12:11 PM PDT 24
Finished Jul 03 07:12:46 PM PDT 24
Peak memory 250492 kb
Host smart-515c82dc-5892-48a5-94a1-acfd75cee9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722746896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.1722746896
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.2145898426
Short name T470
Test name
Test status
Simulation time 354817323 ps
CPU time 7.81 seconds
Started Jul 03 07:12:13 PM PDT 24
Finished Jul 03 07:12:30 PM PDT 24
Peak memory 250520 kb
Host smart-c6c7d1de-28ac-443f-a046-e20ab3992f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145898426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.2145898426
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.1401300300
Short name T147
Test name
Test status
Simulation time 29248284088 ps
CPU time 648.96 seconds
Started Jul 03 07:12:17 PM PDT 24
Finished Jul 03 07:23:15 PM PDT 24
Peak memory 283584 kb
Host smart-27194f33-25e9-423b-b167-d913d66a4200
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1401300300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all_with_rand_reset.1401300300
Directory /workspace/15.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.3149048305
Short name T861
Test name
Test status
Simulation time 27090432 ps
CPU time 1.18 seconds
Started Jul 03 07:12:17 PM PDT 24
Finished Jul 03 07:12:27 PM PDT 24
Peak memory 211408 kb
Host smart-a2d9f91c-740c-472d-a981-a1a3bdd3af2f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149048305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.3149048305
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.1059914658
Short name T817
Test name
Test status
Simulation time 144131964 ps
CPU time 1.08 seconds
Started Jul 03 07:12:22 PM PDT 24
Finished Jul 03 07:12:31 PM PDT 24
Peak memory 208524 kb
Host smart-5d523cd7-f2bc-4251-a95c-6dcf19d9ffc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059914658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.1059914658
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.2308191967
Short name T253
Test name
Test status
Simulation time 1385868925 ps
CPU time 9.57 seconds
Started Jul 03 07:12:22 PM PDT 24
Finished Jul 03 07:12:40 PM PDT 24
Peak memory 217756 kb
Host smart-6a2cd203-33f3-4944-aee0-9d3d2927f6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308191967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.2308191967
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.2148403430
Short name T498
Test name
Test status
Simulation time 295670521 ps
CPU time 4.18 seconds
Started Jul 03 07:12:21 PM PDT 24
Finished Jul 03 07:12:33 PM PDT 24
Peak memory 216912 kb
Host smart-4b9c3098-32cb-4861-86d4-aee556fe30fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148403430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.2148403430
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.2210655197
Short name T707
Test name
Test status
Simulation time 3619275248 ps
CPU time 9.62 seconds
Started Jul 03 07:12:20 PM PDT 24
Finished Jul 03 07:12:38 PM PDT 24
Peak memory 217748 kb
Host smart-635c1f92-f235-4698-a3b2-0b31e6e6520d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210655197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.2210655197
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.3085210811
Short name T74
Test name
Test status
Simulation time 466967713 ps
CPU time 12.09 seconds
Started Jul 03 07:12:20 PM PDT 24
Finished Jul 03 07:12:40 PM PDT 24
Peak memory 217160 kb
Host smart-a7e71300-bb77-4489-9a2d-c6b8849f21f0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085210811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.3085210811
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.2633296544
Short name T272
Test name
Test status
Simulation time 5072406941 ps
CPU time 60.27 seconds
Started Jul 03 07:12:19 PM PDT 24
Finished Jul 03 07:13:29 PM PDT 24
Peak memory 282888 kb
Host smart-f393173a-1fef-4919-bf42-827964837cae
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633296544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.2633296544
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.2825933632
Short name T380
Test name
Test status
Simulation time 586268658 ps
CPU time 22.59 seconds
Started Jul 03 07:12:19 PM PDT 24
Finished Jul 03 07:12:50 PM PDT 24
Peak memory 250568 kb
Host smart-ecb84063-34f2-49f6-93ff-d9251a181eed
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825933632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.2825933632
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.3658961249
Short name T256
Test name
Test status
Simulation time 238627464 ps
CPU time 2.89 seconds
Started Jul 03 07:12:22 PM PDT 24
Finished Jul 03 07:12:33 PM PDT 24
Peak memory 217792 kb
Host smart-39ce0710-3514-4c1a-8e8f-c33ddbd74630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658961249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.3658961249
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.347669118
Short name T677
Test name
Test status
Simulation time 519467519 ps
CPU time 15.93 seconds
Started Jul 03 07:12:21 PM PDT 24
Finished Jul 03 07:12:45 PM PDT 24
Peak memory 218404 kb
Host smart-cca27bbe-347a-4d23-887f-118872532319
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347669118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.347669118
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.2175628639
Short name T392
Test name
Test status
Simulation time 710429420 ps
CPU time 10.98 seconds
Started Jul 03 07:12:21 PM PDT 24
Finished Jul 03 07:12:41 PM PDT 24
Peak memory 225484 kb
Host smart-3005c420-c06c-477c-988f-2a8450060ae1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175628639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.2175628639
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.3156458186
Short name T354
Test name
Test status
Simulation time 266063559 ps
CPU time 7.58 seconds
Started Jul 03 07:12:21 PM PDT 24
Finished Jul 03 07:12:37 PM PDT 24
Peak memory 217612 kb
Host smart-65c6bf52-8670-41b4-a1f0-e1771bd19845
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156458186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
3156458186
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.2311285623
Short name T440
Test name
Test status
Simulation time 350569906 ps
CPU time 8.94 seconds
Started Jul 03 07:12:20 PM PDT 24
Finished Jul 03 07:12:38 PM PDT 24
Peak memory 225580 kb
Host smart-2cbd0aec-8cb3-4dd4-a3fe-de4e29c1988e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311285623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.2311285623
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.471020532
Short name T798
Test name
Test status
Simulation time 86360008 ps
CPU time 1.6 seconds
Started Jul 03 07:12:16 PM PDT 24
Finished Jul 03 07:12:27 PM PDT 24
Peak memory 217196 kb
Host smart-45e3a959-5e7e-4bca-99bf-1cf8aac1b662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471020532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.471020532
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.3235746475
Short name T444
Test name
Test status
Simulation time 377864196 ps
CPU time 30.02 seconds
Started Jul 03 07:12:18 PM PDT 24
Finished Jul 03 07:12:58 PM PDT 24
Peak memory 250392 kb
Host smart-59051a72-4e3b-4d52-8845-7cd24a596487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235746475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.3235746475
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.1010115302
Short name T591
Test name
Test status
Simulation time 150381943 ps
CPU time 6.17 seconds
Started Jul 03 07:12:22 PM PDT 24
Finished Jul 03 07:12:36 PM PDT 24
Peak memory 246056 kb
Host smart-20c734ad-c873-4e91-9a36-c1991e3ea111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010115302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.1010115302
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.1142922336
Short name T712
Test name
Test status
Simulation time 154721195724 ps
CPU time 406.96 seconds
Started Jul 03 07:12:21 PM PDT 24
Finished Jul 03 07:19:16 PM PDT 24
Peak memory 273664 kb
Host smart-57340079-1cd2-4123-b82f-41f35449c049
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142922336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.1142922336
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.107639859
Short name T558
Test name
Test status
Simulation time 12889885 ps
CPU time 0.81 seconds
Started Jul 03 07:12:15 PM PDT 24
Finished Jul 03 07:12:25 PM PDT 24
Peak memory 208360 kb
Host smart-4198cfba-f598-400d-923b-797317acac15
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107639859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ct
rl_volatile_unlock_smoke.107639859
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.2906501823
Short name T359
Test name
Test status
Simulation time 118306381 ps
CPU time 1.06 seconds
Started Jul 03 07:12:30 PM PDT 24
Finished Jul 03 07:12:36 PM PDT 24
Peak memory 208576 kb
Host smart-efdfe8b4-bff0-4ec2-9d51-1fc9749c138b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906501823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.2906501823
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.721867928
Short name T687
Test name
Test status
Simulation time 297728768 ps
CPU time 11.68 seconds
Started Jul 03 07:12:27 PM PDT 24
Finished Jul 03 07:12:44 PM PDT 24
Peak memory 217796 kb
Host smart-ccdb120e-d237-4b83-80d1-c0edd1c11a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721867928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.721867928
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.1019428411
Short name T336
Test name
Test status
Simulation time 1682827925 ps
CPU time 50.23 seconds
Started Jul 03 07:12:26 PM PDT 24
Finished Jul 03 07:13:22 PM PDT 24
Peak memory 218384 kb
Host smart-dbcbd702-5da0-429d-a1ac-358d79fafc1d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019428411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.1019428411
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.2604953532
Short name T695
Test name
Test status
Simulation time 1598073122 ps
CPU time 4.51 seconds
Started Jul 03 07:12:26 PM PDT 24
Finished Jul 03 07:12:37 PM PDT 24
Peak memory 221272 kb
Host smart-4d423d67-5a7d-4c58-affe-476ebdfd8e2e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604953532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.2604953532
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.912242636
Short name T864
Test name
Test status
Simulation time 365785037 ps
CPU time 3.44 seconds
Started Jul 03 07:12:24 PM PDT 24
Finished Jul 03 07:12:35 PM PDT 24
Peak memory 217092 kb
Host smart-888db0b8-fa97-4b1f-b013-cc1ac9c24b3d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912242636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke.
912242636
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.3678292298
Short name T810
Test name
Test status
Simulation time 1810795076 ps
CPU time 63.31 seconds
Started Jul 03 07:12:26 PM PDT 24
Finished Jul 03 07:13:35 PM PDT 24
Peak memory 275060 kb
Host smart-d16fca50-cd2b-426f-a74f-0e3840d28867
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678292298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.3678292298
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.1331511816
Short name T568
Test name
Test status
Simulation time 1141789544 ps
CPU time 9.56 seconds
Started Jul 03 07:12:25 PM PDT 24
Finished Jul 03 07:12:41 PM PDT 24
Peak memory 225872 kb
Host smart-f74a22f4-54f9-4a9c-939a-072d5b5f6f39
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331511816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.1331511816
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.1454749918
Short name T202
Test name
Test status
Simulation time 124217098 ps
CPU time 3.13 seconds
Started Jul 03 07:12:25 PM PDT 24
Finished Jul 03 07:12:35 PM PDT 24
Peak memory 221976 kb
Host smart-3f8d2bb6-8c22-4f3c-a7ad-9982e059dca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454749918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.1454749918
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.1556513695
Short name T585
Test name
Test status
Simulation time 289816143 ps
CPU time 11.78 seconds
Started Jul 03 07:12:26 PM PDT 24
Finished Jul 03 07:12:44 PM PDT 24
Peak memory 218440 kb
Host smart-6ed0cdbb-c10e-47c1-b7de-2f96708ec065
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556513695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.1556513695
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.3771295338
Short name T241
Test name
Test status
Simulation time 698394644 ps
CPU time 10.03 seconds
Started Jul 03 07:12:33 PM PDT 24
Finished Jul 03 07:12:47 PM PDT 24
Peak memory 224564 kb
Host smart-64e5be8f-fa3d-48a4-b8c1-bec74508411b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771295338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.3771295338
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.1986982352
Short name T547
Test name
Test status
Simulation time 1700984161 ps
CPU time 9.07 seconds
Started Jul 03 07:12:33 PM PDT 24
Finished Jul 03 07:12:45 PM PDT 24
Peak memory 225488 kb
Host smart-ff015c6f-3b44-4ea6-b343-705c0b06e5b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986982352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
1986982352
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.2734560729
Short name T814
Test name
Test status
Simulation time 1020367437 ps
CPU time 7.49 seconds
Started Jul 03 07:12:26 PM PDT 24
Finished Jul 03 07:12:40 PM PDT 24
Peak memory 224640 kb
Host smart-75ce3320-dddf-4d9b-8d8a-fc3b53df628e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734560729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.2734560729
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.3970788456
Short name T860
Test name
Test status
Simulation time 74111880 ps
CPU time 3.79 seconds
Started Jul 03 07:12:22 PM PDT 24
Finished Jul 03 07:12:34 PM PDT 24
Peak memory 217328 kb
Host smart-e74c3a08-82d3-4e31-8d93-810783d4b6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970788456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.3970788456
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.2527286594
Short name T375
Test name
Test status
Simulation time 589545350 ps
CPU time 27.95 seconds
Started Jul 03 07:12:30 PM PDT 24
Finished Jul 03 07:13:02 PM PDT 24
Peak memory 250516 kb
Host smart-9b63a627-c487-4d22-bd1c-5fb4777c2e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527286594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.2527286594
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.4057772651
Short name T267
Test name
Test status
Simulation time 159672337 ps
CPU time 7.86 seconds
Started Jul 03 07:12:26 PM PDT 24
Finished Jul 03 07:12:40 PM PDT 24
Peak memory 250520 kb
Host smart-dc146615-b2e2-4248-8a02-2e40dba634ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057772651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.4057772651
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.3157807836
Short name T672
Test name
Test status
Simulation time 1651938565 ps
CPU time 32.63 seconds
Started Jul 03 07:12:32 PM PDT 24
Finished Jul 03 07:13:08 PM PDT 24
Peak memory 250112 kb
Host smart-1c7366c2-f499-4386-8aec-a3adc7b504a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157807836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.3157807836
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.2437395363
Short name T482
Test name
Test status
Simulation time 10532319788 ps
CPU time 345.57 seconds
Started Jul 03 07:12:31 PM PDT 24
Finished Jul 03 07:18:21 PM PDT 24
Peak memory 273096 kb
Host smart-a79967bc-dcef-45e2-876e-244f03a2958f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2437395363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.2437395363
Directory /workspace/17.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.58150064
Short name T108
Test name
Test status
Simulation time 22935737 ps
CPU time 0.92 seconds
Started Jul 03 07:12:28 PM PDT 24
Finished Jul 03 07:12:34 PM PDT 24
Peak memory 208480 kb
Host smart-79871bd9-05c8-4178-b027-f55fb56b14a5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58150064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_volatile_unlock_smoke.58150064
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.451187590
Short name T99
Test name
Test status
Simulation time 308642609 ps
CPU time 1.32 seconds
Started Jul 03 07:12:41 PM PDT 24
Finished Jul 03 07:12:43 PM PDT 24
Peak memory 208636 kb
Host smart-20fa0035-7e5b-4834-87a2-ceb4b5e823b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451187590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.451187590
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.1736593450
Short name T490
Test name
Test status
Simulation time 405032281 ps
CPU time 15.88 seconds
Started Jul 03 07:12:31 PM PDT 24
Finished Jul 03 07:12:51 PM PDT 24
Peak memory 217800 kb
Host smart-05eb153f-f4ff-4051-94ef-6f285495b2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736593450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.1736593450
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.3303603099
Short name T529
Test name
Test status
Simulation time 568732399 ps
CPU time 5.82 seconds
Started Jul 03 07:12:31 PM PDT 24
Finished Jul 03 07:12:41 PM PDT 24
Peak memory 217144 kb
Host smart-1688d4a1-637a-4b99-9ed7-07fe92a66996
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303603099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.3303603099
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.1227475113
Short name T598
Test name
Test status
Simulation time 2077285750 ps
CPU time 30.85 seconds
Started Jul 03 07:12:32 PM PDT 24
Finished Jul 03 07:13:06 PM PDT 24
Peak memory 217744 kb
Host smart-0598529d-39d1-4fed-9bf8-c7c45276ec3d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227475113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.1227475113
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.408888737
Short name T342
Test name
Test status
Simulation time 87892989 ps
CPU time 3.61 seconds
Started Jul 03 07:12:31 PM PDT 24
Finished Jul 03 07:12:39 PM PDT 24
Peak memory 221276 kb
Host smart-a947fe20-cb77-4ce7-9312-542ecdcac834
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408888737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag
_prog_failure.408888737
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.122319566
Short name T18
Test name
Test status
Simulation time 394840545 ps
CPU time 4.69 seconds
Started Jul 03 07:12:30 PM PDT 24
Finished Jul 03 07:12:39 PM PDT 24
Peak memory 217124 kb
Host smart-021c5605-51ea-454b-a907-b4c5e33c811a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122319566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke.
122319566
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.2065384000
Short name T270
Test name
Test status
Simulation time 1744456528 ps
CPU time 67.35 seconds
Started Jul 03 07:12:30 PM PDT 24
Finished Jul 03 07:13:42 PM PDT 24
Peak memory 266844 kb
Host smart-8526ae0c-62bd-44df-9d5c-62da86582e29
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065384000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.2065384000
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.922251128
Short name T393
Test name
Test status
Simulation time 350243713 ps
CPU time 16.45 seconds
Started Jul 03 07:12:32 PM PDT 24
Finished Jul 03 07:12:52 PM PDT 24
Peak memory 250496 kb
Host smart-cc33b675-d178-4ade-9b41-ee1bfad312f7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922251128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_
jtag_state_post_trans.922251128
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.797074579
Short name T705
Test name
Test status
Simulation time 41690820 ps
CPU time 2.44 seconds
Started Jul 03 07:12:33 PM PDT 24
Finished Jul 03 07:12:39 PM PDT 24
Peak memory 217212 kb
Host smart-08e1f4a2-a01d-4422-ac4a-19c0bf68eb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797074579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.797074579
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.700588780
Short name T560
Test name
Test status
Simulation time 252637678 ps
CPU time 12.77 seconds
Started Jul 03 07:12:31 PM PDT 24
Finished Jul 03 07:12:48 PM PDT 24
Peak memory 225572 kb
Host smart-9502b5fe-e485-44e9-a0cf-f4d1342f99ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700588780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.700588780
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.349636911
Short name T684
Test name
Test status
Simulation time 387455322 ps
CPU time 15.33 seconds
Started Jul 03 07:12:32 PM PDT 24
Finished Jul 03 07:12:51 PM PDT 24
Peak memory 225496 kb
Host smart-90431840-260e-4719-93b3-8dccb1103fab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349636911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_di
gest.349636911
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.4123860653
Short name T667
Test name
Test status
Simulation time 635395822 ps
CPU time 10.18 seconds
Started Jul 03 07:12:32 PM PDT 24
Finished Jul 03 07:12:46 PM PDT 24
Peak memory 225496 kb
Host smart-6455190b-9dcb-419a-899d-87aebb573238
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123860653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
4123860653
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.1191894536
Short name T526
Test name
Test status
Simulation time 17946718 ps
CPU time 1.48 seconds
Started Jul 03 07:12:32 PM PDT 24
Finished Jul 03 07:12:37 PM PDT 24
Peak memory 217292 kb
Host smart-e8ddaceb-4bd8-42f1-8bff-526930a014d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191894536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.1191894536
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.2018285806
Short name T709
Test name
Test status
Simulation time 510724077 ps
CPU time 26.51 seconds
Started Jul 03 07:12:33 PM PDT 24
Finished Jul 03 07:13:03 PM PDT 24
Peak memory 250512 kb
Host smart-125e7311-488f-41b2-bb71-e43c00bfbfd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018285806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.2018285806
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.2576371807
Short name T503
Test name
Test status
Simulation time 969385658 ps
CPU time 9.3 seconds
Started Jul 03 07:12:31 PM PDT 24
Finished Jul 03 07:12:45 PM PDT 24
Peak memory 250524 kb
Host smart-fc517294-263e-45ba-b736-35f2e9a67f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576371807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.2576371807
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.2537400553
Short name T58
Test name
Test status
Simulation time 18469872997 ps
CPU time 357.29 seconds
Started Jul 03 07:12:33 PM PDT 24
Finished Jul 03 07:18:34 PM PDT 24
Peak memory 232048 kb
Host smart-17e18a74-91e5-4bf1-853d-f0d22eeed1eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537400553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.2537400553
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.1712093392
Short name T776
Test name
Test status
Simulation time 161922890556 ps
CPU time 446.58 seconds
Started Jul 03 07:12:37 PM PDT 24
Finished Jul 03 07:20:05 PM PDT 24
Peak memory 283488 kb
Host smart-ea517433-9629-4cf9-b10f-b2688fd83b51
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1712093392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.1712093392
Directory /workspace/18.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.792343271
Short name T574
Test name
Test status
Simulation time 29324032 ps
CPU time 0.97 seconds
Started Jul 03 07:12:33 PM PDT 24
Finished Jul 03 07:12:37 PM PDT 24
Peak memory 211400 kb
Host smart-3b02d144-389e-411c-9fcc-981a893a9c3b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792343271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ct
rl_volatile_unlock_smoke.792343271
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.1961237147
Short name T506
Test name
Test status
Simulation time 21659131 ps
CPU time 1.11 seconds
Started Jul 03 07:12:42 PM PDT 24
Finished Jul 03 07:12:44 PM PDT 24
Peak memory 208520 kb
Host smart-85d56cf7-7986-46f1-9ae9-57df0647e1c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961237147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.1961237147
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.843491855
Short name T650
Test name
Test status
Simulation time 324552343 ps
CPU time 13.37 seconds
Started Jul 03 07:12:39 PM PDT 24
Finished Jul 03 07:12:53 PM PDT 24
Peak memory 217852 kb
Host smart-0b6bf597-0769-4af4-ab44-f306b048d196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843491855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.843491855
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.497208598
Short name T394
Test name
Test status
Simulation time 262082559 ps
CPU time 3.43 seconds
Started Jul 03 07:12:36 PM PDT 24
Finished Jul 03 07:12:41 PM PDT 24
Peak memory 217148 kb
Host smart-ea9cfc84-5579-4e9f-b4d0-1fccc83451ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497208598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.497208598
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.2688813307
Short name T649
Test name
Test status
Simulation time 7533711068 ps
CPU time 45.44 seconds
Started Jul 03 07:12:44 PM PDT 24
Finished Jul 03 07:13:30 PM PDT 24
Peak memory 219496 kb
Host smart-b04e4ba8-7673-4d2b-9bab-d1b81314c474
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688813307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.2688813307
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.1545324737
Short name T519
Test name
Test status
Simulation time 740952900 ps
CPU time 7.5 seconds
Started Jul 03 07:12:36 PM PDT 24
Finished Jul 03 07:12:45 PM PDT 24
Peak memory 217752 kb
Host smart-1be0b0b2-2116-4681-9eb0-d0f4f2530a2e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545324737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.1545324737
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.2014274631
Short name T794
Test name
Test status
Simulation time 470883944 ps
CPU time 3.87 seconds
Started Jul 03 07:12:41 PM PDT 24
Finished Jul 03 07:12:46 PM PDT 24
Peak memory 217224 kb
Host smart-ec3eaf5b-5feb-455d-960f-796f573da94a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014274631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.2014274631
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.1763565797
Short name T555
Test name
Test status
Simulation time 2456697151 ps
CPU time 70 seconds
Started Jul 03 07:12:35 PM PDT 24
Finished Jul 03 07:13:47 PM PDT 24
Peak memory 276136 kb
Host smart-3c7779cd-0c57-44bb-8001-1dee1d2c8ed1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763565797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.1763565797
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.3133220246
Short name T262
Test name
Test status
Simulation time 795262800 ps
CPU time 23.01 seconds
Started Jul 03 07:12:37 PM PDT 24
Finished Jul 03 07:13:02 PM PDT 24
Peak memory 218396 kb
Host smart-63019ce7-ead7-4796-bb0a-c742c7e06bae
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133220246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.3133220246
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.1441027522
Short name T255
Test name
Test status
Simulation time 412992422 ps
CPU time 4.42 seconds
Started Jul 03 07:12:38 PM PDT 24
Finished Jul 03 07:12:43 PM PDT 24
Peak memory 222244 kb
Host smart-a9d7fe20-b03b-4fde-be01-3271a53133b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441027522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.1441027522
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.3042023828
Short name T335
Test name
Test status
Simulation time 362130139 ps
CPU time 15.3 seconds
Started Jul 03 07:12:37 PM PDT 24
Finished Jul 03 07:12:54 PM PDT 24
Peak memory 218424 kb
Host smart-35eff707-838c-42b3-b448-e184910648a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042023828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.3042023828
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.3998907333
Short name T761
Test name
Test status
Simulation time 575292850 ps
CPU time 9.47 seconds
Started Jul 03 07:12:45 PM PDT 24
Finished Jul 03 07:12:55 PM PDT 24
Peak memory 225496 kb
Host smart-9d162671-0d43-41ed-a868-207b1b60d31a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998907333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.3998907333
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.371543438
Short name T564
Test name
Test status
Simulation time 358264137 ps
CPU time 6.75 seconds
Started Jul 03 07:12:35 PM PDT 24
Finished Jul 03 07:12:44 PM PDT 24
Peak memory 225000 kb
Host smart-1cb197ab-de69-4942-ab72-361302009dcb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371543438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.371543438
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.3771783215
Short name T475
Test name
Test status
Simulation time 1708624630 ps
CPU time 10.25 seconds
Started Jul 03 07:12:38 PM PDT 24
Finished Jul 03 07:12:49 PM PDT 24
Peak memory 225548 kb
Host smart-d6fe00a1-03af-4a02-b0aa-8ccb030099ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771783215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.3771783215
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.1737706999
Short name T243
Test name
Test status
Simulation time 248869848 ps
CPU time 2.49 seconds
Started Jul 03 07:12:36 PM PDT 24
Finished Jul 03 07:12:40 PM PDT 24
Peak memory 213808 kb
Host smart-cbbaa08e-afa0-45de-97a9-ab3befdba966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737706999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.1737706999
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.873402331
Short name T322
Test name
Test status
Simulation time 3395715154 ps
CPU time 25.82 seconds
Started Jul 03 07:12:40 PM PDT 24
Finished Jul 03 07:13:06 PM PDT 24
Peak memory 250684 kb
Host smart-2805bb74-5de7-40f4-879d-596c5718d25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873402331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.873402331
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.132974378
Short name T208
Test name
Test status
Simulation time 65759612 ps
CPU time 8.81 seconds
Started Jul 03 07:12:38 PM PDT 24
Finished Jul 03 07:12:49 PM PDT 24
Peak memory 250564 kb
Host smart-d2fc78f9-18a2-4933-82f3-0d4c4a289ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132974378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.132974378
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.2084236663
Short name T481
Test name
Test status
Simulation time 10762952030 ps
CPU time 145.51 seconds
Started Jul 03 07:12:41 PM PDT 24
Finished Jul 03 07:15:08 PM PDT 24
Peak memory 219664 kb
Host smart-1b4f9d31-3992-4b3d-b8a6-14b2c7cccae7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084236663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.2084236663
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.3562332316
Short name T361
Test name
Test status
Simulation time 26333118 ps
CPU time 1.1 seconds
Started Jul 03 07:12:36 PM PDT 24
Finished Jul 03 07:12:39 PM PDT 24
Peak memory 211440 kb
Host smart-8b305543-f47a-4a36-a522-83be38f1840f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562332316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.3562332316
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.3141978963
Short name T645
Test name
Test status
Simulation time 18471825 ps
CPU time 1.09 seconds
Started Jul 03 07:10:46 PM PDT 24
Finished Jul 03 07:11:21 PM PDT 24
Peak memory 208624 kb
Host smart-5388c812-0207-4e40-b7dd-4e8f7717a3a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141978963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.3141978963
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.2805234481
Short name T436
Test name
Test status
Simulation time 17309410 ps
CPU time 0.91 seconds
Started Jul 03 07:10:42 PM PDT 24
Finished Jul 03 07:11:16 PM PDT 24
Peak memory 208428 kb
Host smart-aaa77141-8c40-400d-84cb-517535ab2f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805234481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.2805234481
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.2972914514
Short name T567
Test name
Test status
Simulation time 277695921 ps
CPU time 11.47 seconds
Started Jul 03 07:10:37 PM PDT 24
Finished Jul 03 07:11:20 PM PDT 24
Peak memory 225596 kb
Host smart-1fddf5d0-eb5a-4302-b12e-cba1c2f75e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972914514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.2972914514
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.2608528394
Short name T599
Test name
Test status
Simulation time 190080826 ps
CPU time 5.65 seconds
Started Jul 03 07:10:43 PM PDT 24
Finished Jul 03 07:11:21 PM PDT 24
Peak memory 217228 kb
Host smart-941df983-de01-4a37-b1d4-bcb337a4e31f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608528394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.2608528394
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.4172628139
Short name T668
Test name
Test status
Simulation time 1366786696 ps
CPU time 36.36 seconds
Started Jul 03 07:10:42 PM PDT 24
Finished Jul 03 07:11:52 PM PDT 24
Peak memory 217788 kb
Host smart-387a0c90-6f65-4b1e-90e0-54ea099838d2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172628139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.4172628139
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.847493409
Short name T162
Test name
Test status
Simulation time 569358468 ps
CPU time 4.43 seconds
Started Jul 03 07:10:43 PM PDT 24
Finished Jul 03 07:11:20 PM PDT 24
Peak memory 217188 kb
Host smart-ecb6cb18-ed00-4dcb-9eb3-564bc6631c3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847493409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.847493409
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.3847685914
Short name T400
Test name
Test status
Simulation time 206235343 ps
CPU time 7.25 seconds
Started Jul 03 07:10:41 PM PDT 24
Finished Jul 03 07:11:22 PM PDT 24
Peak memory 222612 kb
Host smart-3f551a62-87fb-4256-96ed-d5888336acfe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847685914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.3847685914
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.515488349
Short name T767
Test name
Test status
Simulation time 849129016 ps
CPU time 13.44 seconds
Started Jul 03 07:10:43 PM PDT 24
Finished Jul 03 07:11:29 PM PDT 24
Peak memory 217112 kb
Host smart-8fcc0efa-f461-4466-9edd-a361e9d6af2d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515488349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_regwen_during_op.515488349
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.746860041
Short name T332
Test name
Test status
Simulation time 127634462 ps
CPU time 4.13 seconds
Started Jul 03 07:10:40 PM PDT 24
Finished Jul 03 07:11:16 PM PDT 24
Peak memory 217104 kb
Host smart-90322b03-0bbd-4f9e-bd25-5dd016dd69c7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746860041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.746860041
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.1581752943
Short name T633
Test name
Test status
Simulation time 2584591473 ps
CPU time 51.23 seconds
Started Jul 03 07:10:42 PM PDT 24
Finished Jul 03 07:12:06 PM PDT 24
Peak memory 278348 kb
Host smart-0b5fb445-e6e9-42de-a003-2c44da63cb7c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581752943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.1581752943
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.730339087
Short name T579
Test name
Test status
Simulation time 921082595 ps
CPU time 11.86 seconds
Started Jul 03 07:10:38 PM PDT 24
Finished Jul 03 07:11:20 PM PDT 24
Peak memory 250188 kb
Host smart-74b8a45a-6b64-4b14-9fdf-161987a88331
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730339087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_state_post_trans.730339087
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.1551201807
Short name T223
Test name
Test status
Simulation time 26286348 ps
CPU time 1.45 seconds
Started Jul 03 07:10:38 PM PDT 24
Finished Jul 03 07:11:10 PM PDT 24
Peak memory 221476 kb
Host smart-ccb47c2e-b298-40aa-a30d-aacfe6d9e68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551201807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.1551201807
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.2436947638
Short name T69
Test name
Test status
Simulation time 458660803 ps
CPU time 9.82 seconds
Started Jul 03 07:10:38 PM PDT 24
Finished Jul 03 07:11:18 PM PDT 24
Peak memory 214264 kb
Host smart-154411bb-61f1-4342-bbb9-87997949b70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436947638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.2436947638
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.3207120781
Short name T62
Test name
Test status
Simulation time 568445892 ps
CPU time 24.31 seconds
Started Jul 03 07:10:49 PM PDT 24
Finished Jul 03 07:11:44 PM PDT 24
Peak memory 284084 kb
Host smart-eaa6bd90-0172-4cfe-9523-dea92cf50fe1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207120781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.3207120781
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.2447089487
Short name T174
Test name
Test status
Simulation time 368709101 ps
CPU time 12.69 seconds
Started Jul 03 07:10:42 PM PDT 24
Finished Jul 03 07:11:28 PM PDT 24
Peak memory 225520 kb
Host smart-72360c4b-07a0-42c6-aa7f-f3364deb3253
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447089487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.2447089487
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.4079284213
Short name T852
Test name
Test status
Simulation time 1348570802 ps
CPU time 14.16 seconds
Started Jul 03 07:10:43 PM PDT 24
Finished Jul 03 07:11:31 PM PDT 24
Peak memory 217688 kb
Host smart-f5fd85a2-73fa-402f-b401-6dabb26b7393
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079284213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.4
079284213
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.2804394911
Short name T37
Test name
Test status
Simulation time 912658879 ps
CPU time 9.14 seconds
Started Jul 03 07:10:39 PM PDT 24
Finished Jul 03 07:11:20 PM PDT 24
Peak memory 225544 kb
Host smart-d56e1dd1-18dd-4fd0-9f16-9c8ca716e05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804394911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.2804394911
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.791659633
Short name T339
Test name
Test status
Simulation time 40809643 ps
CPU time 1.98 seconds
Started Jul 03 07:10:38 PM PDT 24
Finished Jul 03 07:11:10 PM PDT 24
Peak memory 213776 kb
Host smart-19cc4969-5201-46b0-bf85-27fc106a5ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791659633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.791659633
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.2703277430
Short name T150
Test name
Test status
Simulation time 1056225275 ps
CPU time 31.28 seconds
Started Jul 03 07:10:39 PM PDT 24
Finished Jul 03 07:11:40 PM PDT 24
Peak memory 250580 kb
Host smart-1101af65-c4af-43ca-88f4-dbdadf05b6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703277430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.2703277430
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.1499743335
Short name T731
Test name
Test status
Simulation time 160226757 ps
CPU time 6.74 seconds
Started Jul 03 07:10:37 PM PDT 24
Finished Jul 03 07:11:15 PM PDT 24
Peak memory 246040 kb
Host smart-c25ab03d-dccb-4242-9492-03c423eaa16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499743335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.1499743335
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.1560911822
Short name T832
Test name
Test status
Simulation time 15951681561 ps
CPU time 77.21 seconds
Started Jul 03 07:10:48 PM PDT 24
Finished Jul 03 07:12:37 PM PDT 24
Peak memory 234172 kb
Host smart-756d3b73-fc0c-4085-8856-9b721bcf2ad6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560911822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.1560911822
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.2532734915
Short name T96
Test name
Test status
Simulation time 49044851450 ps
CPU time 223.14 seconds
Started Jul 03 07:10:47 PM PDT 24
Finished Jul 03 07:15:03 PM PDT 24
Peak memory 282588 kb
Host smart-09ad59d8-5f3e-4030-945f-ad17e52b3d40
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2532734915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.2532734915
Directory /workspace/2.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.2199985300
Short name T456
Test name
Test status
Simulation time 14663491 ps
CPU time 0.96 seconds
Started Jul 03 07:10:38 PM PDT 24
Finished Jul 03 07:11:09 PM PDT 24
Peak memory 208488 kb
Host smart-33413c72-5aa5-4e92-8f22-372887c73ff6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199985300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.2199985300
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.4012958624
Short name T91
Test name
Test status
Simulation time 15291405 ps
CPU time 1.03 seconds
Started Jul 03 07:12:42 PM PDT 24
Finished Jul 03 07:12:44 PM PDT 24
Peak memory 208548 kb
Host smart-66d83996-babb-4b1d-a387-9b913b4ae219
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012958624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.4012958624
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.1263295678
Short name T866
Test name
Test status
Simulation time 657173246 ps
CPU time 9.29 seconds
Started Jul 03 07:12:40 PM PDT 24
Finished Jul 03 07:12:51 PM PDT 24
Peak memory 225592 kb
Host smart-31636479-778d-4d07-93cb-061db11d6895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263295678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.1263295678
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.1475416466
Short name T474
Test name
Test status
Simulation time 587918031 ps
CPU time 5.66 seconds
Started Jul 03 07:12:42 PM PDT 24
Finished Jul 03 07:12:49 PM PDT 24
Peak memory 217188 kb
Host smart-4b494e00-d7b2-40af-ad25-d9954fe1eb87
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475416466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.1475416466
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.3459005943
Short name T349
Test name
Test status
Simulation time 63673349 ps
CPU time 3.44 seconds
Started Jul 03 07:12:41 PM PDT 24
Finished Jul 03 07:12:45 PM PDT 24
Peak memory 217744 kb
Host smart-2ddcb30f-729b-4e51-9309-600ea8a76bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459005943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.3459005943
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.3922547671
Short name T644
Test name
Test status
Simulation time 997130363 ps
CPU time 19.63 seconds
Started Jul 03 07:12:41 PM PDT 24
Finished Jul 03 07:13:02 PM PDT 24
Peak memory 225488 kb
Host smart-652eccc7-488b-4f67-ab6d-a8ee7d905c6c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922547671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.3922547671
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.2454893283
Short name T105
Test name
Test status
Simulation time 324485435 ps
CPU time 11.18 seconds
Started Jul 03 07:12:40 PM PDT 24
Finished Jul 03 07:12:52 PM PDT 24
Peak memory 217756 kb
Host smart-748e1213-96eb-43bf-983e-a54a8994d174
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454893283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
2454893283
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.1662164417
Short name T805
Test name
Test status
Simulation time 627711918 ps
CPU time 7.33 seconds
Started Jul 03 07:12:45 PM PDT 24
Finished Jul 03 07:12:53 PM PDT 24
Peak memory 224824 kb
Host smart-f041229f-14a1-48c0-a1a6-74ef226c8f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662164417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.1662164417
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.151024537
Short name T545
Test name
Test status
Simulation time 190104843 ps
CPU time 2.32 seconds
Started Jul 03 07:12:42 PM PDT 24
Finished Jul 03 07:12:45 PM PDT 24
Peak memory 213676 kb
Host smart-e2ef703c-3dc8-490e-9e74-f10343439c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151024537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.151024537
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.1658688888
Short name T443
Test name
Test status
Simulation time 337103017 ps
CPU time 29.68 seconds
Started Jul 03 07:12:45 PM PDT 24
Finished Jul 03 07:13:15 PM PDT 24
Peak memory 250500 kb
Host smart-ae4cddc9-6614-4438-91a0-65c220e3a062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658688888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.1658688888
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.536360271
Short name T424
Test name
Test status
Simulation time 65086787 ps
CPU time 7.4 seconds
Started Jul 03 07:12:43 PM PDT 24
Finished Jul 03 07:12:51 PM PDT 24
Peak memory 250540 kb
Host smart-7b6b6537-034b-44ae-ae18-262c2eac49a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536360271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.536360271
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.3220826838
Short name T802
Test name
Test status
Simulation time 11968686213 ps
CPU time 366.59 seconds
Started Jul 03 07:12:41 PM PDT 24
Finished Jul 03 07:18:49 PM PDT 24
Peak memory 250596 kb
Host smart-b1d48440-bf90-41a5-80ac-164096fcb43a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220826838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.3220826838
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.1478125108
Short name T51
Test name
Test status
Simulation time 392579447313 ps
CPU time 793.08 seconds
Started Jul 03 07:12:43 PM PDT 24
Finished Jul 03 07:25:57 PM PDT 24
Peak memory 529364 kb
Host smart-5b63ba9d-b8cb-4fe0-8229-74883d1e2c71
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1478125108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all_with_rand_reset.1478125108
Directory /workspace/20.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.1071794506
Short name T571
Test name
Test status
Simulation time 15045591 ps
CPU time 0.85 seconds
Started Jul 03 07:12:42 PM PDT 24
Finished Jul 03 07:12:44 PM PDT 24
Peak memory 208540 kb
Host smart-33ff4027-0137-4edd-8051-a04fa46c3f27
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071794506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.1071794506
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.2919017014
Short name T345
Test name
Test status
Simulation time 38112274 ps
CPU time 1.04 seconds
Started Jul 03 07:12:49 PM PDT 24
Finished Jul 03 07:12:50 PM PDT 24
Peak memory 208616 kb
Host smart-a3e61fd5-deaf-49fa-898f-e84149ff28ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919017014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.2919017014
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.534335277
Short name T819
Test name
Test status
Simulation time 640845547 ps
CPU time 14.31 seconds
Started Jul 03 07:12:46 PM PDT 24
Finished Jul 03 07:13:01 PM PDT 24
Peak memory 217780 kb
Host smart-5f300189-0166-42e5-9d8a-73b1a65902f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534335277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.534335277
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.2801337164
Short name T655
Test name
Test status
Simulation time 210759451 ps
CPU time 1.95 seconds
Started Jul 03 07:12:45 PM PDT 24
Finished Jul 03 07:12:48 PM PDT 24
Peak memory 216632 kb
Host smart-79e6784d-83f8-4b65-9258-ed6a65837882
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801337164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.2801337164
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.3359497889
Short name T679
Test name
Test status
Simulation time 56731007 ps
CPU time 2.52 seconds
Started Jul 03 07:12:46 PM PDT 24
Finished Jul 03 07:12:49 PM PDT 24
Peak memory 217764 kb
Host smart-0823d78a-6503-4099-9954-84d47f62f90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359497889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.3359497889
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.3024877208
Short name T274
Test name
Test status
Simulation time 451349531 ps
CPU time 19.18 seconds
Started Jul 03 07:12:47 PM PDT 24
Finished Jul 03 07:13:07 PM PDT 24
Peak memory 218444 kb
Host smart-5303a233-af65-4704-9b14-60779c0e3bef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024877208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.3024877208
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.13836225
Short name T448
Test name
Test status
Simulation time 705745196 ps
CPU time 11.82 seconds
Started Jul 03 07:12:46 PM PDT 24
Finished Jul 03 07:12:59 PM PDT 24
Peak memory 225444 kb
Host smart-c7791188-e897-4503-9ea0-7bbb2e69ce44
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13836225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_dig
est.13836225
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.426762642
Short name T434
Test name
Test status
Simulation time 351250463 ps
CPU time 8.39 seconds
Started Jul 03 07:12:45 PM PDT 24
Finished Jul 03 07:12:55 PM PDT 24
Peak memory 224440 kb
Host smart-68177b69-de22-4737-96ba-117e2fa86a1a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426762642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.426762642
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.3251337264
Short name T412
Test name
Test status
Simulation time 1018299310 ps
CPU time 12.27 seconds
Started Jul 03 07:12:46 PM PDT 24
Finished Jul 03 07:12:59 PM PDT 24
Peak memory 225668 kb
Host smart-7927a8ee-f9a0-4424-a910-e91530485710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251337264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.3251337264
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.1552896926
Short name T403
Test name
Test status
Simulation time 186303066 ps
CPU time 5.3 seconds
Started Jul 03 07:12:44 PM PDT 24
Finished Jul 03 07:12:50 PM PDT 24
Peak memory 217172 kb
Host smart-31b3742e-6e07-4b28-aff0-7568c109776c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552896926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.1552896926
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.862041550
Short name T14
Test name
Test status
Simulation time 235066067 ps
CPU time 19.67 seconds
Started Jul 03 07:12:45 PM PDT 24
Finished Jul 03 07:13:05 PM PDT 24
Peak memory 250624 kb
Host smart-425ce92d-0415-4430-9252-b7ce1f690224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862041550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.862041550
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.2393579438
Short name T800
Test name
Test status
Simulation time 307276131 ps
CPU time 9.27 seconds
Started Jul 03 07:12:41 PM PDT 24
Finished Jul 03 07:12:51 PM PDT 24
Peak memory 250620 kb
Host smart-c19f62a1-0e35-45cb-aa42-e8fc1d633d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393579438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.2393579438
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.672581407
Short name T431
Test name
Test status
Simulation time 37800925835 ps
CPU time 159.67 seconds
Started Jul 03 07:12:45 PM PDT 24
Finished Jul 03 07:15:26 PM PDT 24
Peak memory 283356 kb
Host smart-4ff0bde4-7fa7-4a4f-ae67-de6cb0b8ba08
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672581407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.672581407
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.2772319824
Short name T263
Test name
Test status
Simulation time 20018465 ps
CPU time 1.07 seconds
Started Jul 03 07:12:40 PM PDT 24
Finished Jul 03 07:12:42 PM PDT 24
Peak memory 211444 kb
Host smart-159fce7e-bc8a-4059-b2d4-337a802515d2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772319824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.2772319824
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.1570464737
Short name T238
Test name
Test status
Simulation time 59254293 ps
CPU time 1.03 seconds
Started Jul 03 07:12:50 PM PDT 24
Finished Jul 03 07:12:52 PM PDT 24
Peak memory 208556 kb
Host smart-dc40ed0e-448e-4550-9f08-590d07238a6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570464737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.1570464737
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.1783656450
Short name T149
Test name
Test status
Simulation time 382760276 ps
CPU time 12.08 seconds
Started Jul 03 07:12:50 PM PDT 24
Finished Jul 03 07:13:03 PM PDT 24
Peak memory 217796 kb
Host smart-4b38a9f8-183b-493c-b2c2-7d1f39df3917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783656450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.1783656450
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.375731080
Short name T755
Test name
Test status
Simulation time 3345545154 ps
CPU time 19.49 seconds
Started Jul 03 07:12:50 PM PDT 24
Finished Jul 03 07:13:10 PM PDT 24
Peak memory 217292 kb
Host smart-63db953e-d0eb-480a-8d40-499bb970d269
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375731080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.375731080
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.401990399
Short name T219
Test name
Test status
Simulation time 58253588 ps
CPU time 3.11 seconds
Started Jul 03 07:12:52 PM PDT 24
Finished Jul 03 07:12:57 PM PDT 24
Peak memory 217792 kb
Host smart-2ad9b5d9-995a-435f-bca0-8bca54209176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401990399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.401990399
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.1077799125
Short name T491
Test name
Test status
Simulation time 571569988 ps
CPU time 14.59 seconds
Started Jul 03 07:12:52 PM PDT 24
Finished Jul 03 07:13:09 PM PDT 24
Peak memory 218576 kb
Host smart-3380ce66-cf5c-4cb0-af3d-9575a1b434ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077799125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.1077799125
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.3538598419
Short name T405
Test name
Test status
Simulation time 3706026688 ps
CPU time 11.27 seconds
Started Jul 03 07:12:49 PM PDT 24
Finished Jul 03 07:13:01 PM PDT 24
Peak memory 225596 kb
Host smart-734c876b-10cd-4e66-be04-54446c96bdaa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538598419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.3538598419
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.2816085402
Short name T340
Test name
Test status
Simulation time 918821252 ps
CPU time 9.09 seconds
Started Jul 03 07:12:50 PM PDT 24
Finished Jul 03 07:13:00 PM PDT 24
Peak memory 225512 kb
Host smart-bac1ea12-1d99-4884-aaf3-17a784601ff8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816085402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
2816085402
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.1434065164
Short name T427
Test name
Test status
Simulation time 26420886 ps
CPU time 2.2 seconds
Started Jul 03 07:12:52 PM PDT 24
Finished Jul 03 07:12:56 PM PDT 24
Peak memory 213956 kb
Host smart-44ecc193-c39e-43e6-901a-ada08442d79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434065164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.1434065164
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.1991328168
Short name T502
Test name
Test status
Simulation time 3801957146 ps
CPU time 37.75 seconds
Started Jul 03 07:12:52 PM PDT 24
Finished Jul 03 07:13:31 PM PDT 24
Peak memory 250604 kb
Host smart-a09b5acb-78ee-43e3-8179-d30eb2a3fbf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991328168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.1991328168
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.3461383980
Short name T234
Test name
Test status
Simulation time 258361222 ps
CPU time 8.78 seconds
Started Jul 03 07:12:51 PM PDT 24
Finished Jul 03 07:13:01 PM PDT 24
Peak memory 243664 kb
Host smart-a7270c4f-bec7-4373-bed3-09639da4a58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461383980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.3461383980
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.2383898176
Short name T309
Test name
Test status
Simulation time 3361816805 ps
CPU time 42.97 seconds
Started Jul 03 07:12:50 PM PDT 24
Finished Jul 03 07:13:34 PM PDT 24
Peak memory 251004 kb
Host smart-d21a7780-682c-487e-a681-6c6481b7768a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383898176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.2383898176
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2970260088
Short name T856
Test name
Test status
Simulation time 28133453 ps
CPU time 0.84 seconds
Started Jul 03 07:12:49 PM PDT 24
Finished Jul 03 07:12:51 PM PDT 24
Peak memory 208460 kb
Host smart-b4ab3ecf-14f0-491f-a51e-6bf0c7b2675a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970260088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.2970260088
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.497341005
Short name T161
Test name
Test status
Simulation time 19818447 ps
CPU time 0.95 seconds
Started Jul 03 07:12:57 PM PDT 24
Finished Jul 03 07:12:59 PM PDT 24
Peak memory 208488 kb
Host smart-1b00af58-643f-40e8-a434-da6b50cb2c11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497341005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.497341005
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.110955968
Short name T497
Test name
Test status
Simulation time 213385072 ps
CPU time 10.63 seconds
Started Jul 03 07:12:55 PM PDT 24
Finished Jul 03 07:13:06 PM PDT 24
Peak memory 225568 kb
Host smart-f629631d-6c18-472b-b302-e82d2c949ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110955968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.110955968
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.1887638373
Short name T478
Test name
Test status
Simulation time 574992062 ps
CPU time 3.71 seconds
Started Jul 03 07:12:56 PM PDT 24
Finished Jul 03 07:13:01 PM PDT 24
Peak memory 217200 kb
Host smart-d1bfc574-4f4c-4d12-b759-2d6edb6d02f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887638373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.1887638373
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.2284337890
Short name T367
Test name
Test status
Simulation time 76474744 ps
CPU time 2.1 seconds
Started Jul 03 07:12:57 PM PDT 24
Finished Jul 03 07:13:00 PM PDT 24
Peak memory 217728 kb
Host smart-1b15e895-fd85-44b1-8bd4-349d22ec259c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284337890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.2284337890
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.3931016602
Short name T100
Test name
Test status
Simulation time 267218718 ps
CPU time 12.33 seconds
Started Jul 03 07:12:55 PM PDT 24
Finished Jul 03 07:13:09 PM PDT 24
Peak memory 217872 kb
Host smart-9afae289-805a-4cc0-aef4-68dba23068e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931016602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.3931016602
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.1403006817
Short name T315
Test name
Test status
Simulation time 425511454 ps
CPU time 9.64 seconds
Started Jul 03 07:12:58 PM PDT 24
Finished Jul 03 07:13:08 PM PDT 24
Peak memory 225480 kb
Host smart-b97909f2-f645-4108-835c-995d02158417
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403006817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.1403006817
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.2661618097
Short name T472
Test name
Test status
Simulation time 280161922 ps
CPU time 8.66 seconds
Started Jul 03 07:12:55 PM PDT 24
Finished Jul 03 07:13:04 PM PDT 24
Peak memory 225608 kb
Host smart-60aa3f27-dea1-4282-988c-d38ba1967b4d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661618097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
2661618097
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.3574400180
Short name T792
Test name
Test status
Simulation time 574234912 ps
CPU time 10.62 seconds
Started Jul 03 07:12:56 PM PDT 24
Finished Jul 03 07:13:08 PM PDT 24
Peak memory 225592 kb
Host smart-c10d33f6-ceba-4c39-a534-80243520d848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574400180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.3574400180
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.3587153274
Short name T774
Test name
Test status
Simulation time 34871277 ps
CPU time 1.88 seconds
Started Jul 03 07:12:50 PM PDT 24
Finished Jul 03 07:12:53 PM PDT 24
Peak memory 213528 kb
Host smart-04cf685e-b0d2-41e5-b500-09232a2803f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587153274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.3587153274
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.926178035
Short name T623
Test name
Test status
Simulation time 199539615 ps
CPU time 25.85 seconds
Started Jul 03 07:12:52 PM PDT 24
Finished Jul 03 07:13:20 PM PDT 24
Peak memory 250628 kb
Host smart-df40ef5b-2ef3-46a9-a415-97cec4423d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926178035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.926178035
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.919822012
Short name T323
Test name
Test status
Simulation time 121315129 ps
CPU time 6.34 seconds
Started Jul 03 07:12:50 PM PDT 24
Finished Jul 03 07:12:57 PM PDT 24
Peak memory 250472 kb
Host smart-4dce4912-53ec-4483-b1d9-b12b12838c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919822012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.919822012
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.1118918199
Short name T463
Test name
Test status
Simulation time 1918684639 ps
CPU time 79.88 seconds
Started Jul 03 07:12:55 PM PDT 24
Finished Jul 03 07:14:16 PM PDT 24
Peak memory 250480 kb
Host smart-9766db23-9bc8-48de-baa5-42b7c037d79e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118918199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.1118918199
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.2452131027
Short name T38
Test name
Test status
Simulation time 38410097437 ps
CPU time 458.97 seconds
Started Jul 03 07:12:56 PM PDT 24
Finished Jul 03 07:20:37 PM PDT 24
Peak memory 331868 kb
Host smart-09e5f728-0476-46d0-af58-fa6cf75d61ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2452131027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.2452131027
Directory /workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.207700625
Short name T372
Test name
Test status
Simulation time 16420337 ps
CPU time 0.8 seconds
Started Jul 03 07:12:51 PM PDT 24
Finished Jul 03 07:12:53 PM PDT 24
Peak memory 208368 kb
Host smart-ec24e4b6-778f-4d06-9ad1-f730be0e2f51
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207700625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ct
rl_volatile_unlock_smoke.207700625
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.1124369252
Short name T327
Test name
Test status
Simulation time 62993676 ps
CPU time 0.87 seconds
Started Jul 03 07:13:01 PM PDT 24
Finished Jul 03 07:13:03 PM PDT 24
Peak memory 208600 kb
Host smart-6fea1eb4-aab9-490f-81d0-73cb2da3abb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124369252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.1124369252
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.3995309246
Short name T254
Test name
Test status
Simulation time 1067783838 ps
CPU time 10.91 seconds
Started Jul 03 07:12:55 PM PDT 24
Finished Jul 03 07:13:07 PM PDT 24
Peak memory 225576 kb
Host smart-4827a0ba-8e01-472c-8b49-0f126fc698d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995309246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.3995309246
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.278181418
Short name T24
Test name
Test status
Simulation time 283090189 ps
CPU time 4.17 seconds
Started Jul 03 07:12:56 PM PDT 24
Finished Jul 03 07:13:01 PM PDT 24
Peak memory 216768 kb
Host smart-43782564-4fc3-4865-b002-b6057a368791
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278181418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.278181418
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.1298996871
Short name T693
Test name
Test status
Simulation time 369374680 ps
CPU time 3.55 seconds
Started Jul 03 07:12:56 PM PDT 24
Finished Jul 03 07:13:01 PM PDT 24
Peak memory 217792 kb
Host smart-c286446b-b201-4658-829e-3a75f36dba63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298996871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.1298996871
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.3414140412
Short name T734
Test name
Test status
Simulation time 398016770 ps
CPU time 8.88 seconds
Started Jul 03 07:12:59 PM PDT 24
Finished Jul 03 07:13:09 PM PDT 24
Peak memory 217800 kb
Host smart-1df65db0-b919-4add-a544-991d5a690df2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414140412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.3414140412
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.2329009417
Short name T855
Test name
Test status
Simulation time 1222286364 ps
CPU time 13.78 seconds
Started Jul 03 07:12:59 PM PDT 24
Finished Jul 03 07:13:14 PM PDT 24
Peak memory 217728 kb
Host smart-2458f356-b762-4ef6-aab5-76482534fa77
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329009417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.2329009417
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.2849087221
Short name T492
Test name
Test status
Simulation time 3150188359 ps
CPU time 11.63 seconds
Started Jul 03 07:13:01 PM PDT 24
Finished Jul 03 07:13:13 PM PDT 24
Peak memory 217760 kb
Host smart-d2e50578-7b2e-492c-b36f-ecf697c9c96f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849087221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
2849087221
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.155007121
Short name T594
Test name
Test status
Simulation time 834851076 ps
CPU time 9.31 seconds
Started Jul 03 07:12:55 PM PDT 24
Finished Jul 03 07:13:05 PM PDT 24
Peak memory 225596 kb
Host smart-f5f37294-d93c-40c3-8096-70a25e20dde4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155007121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.155007121
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.1171671848
Short name T302
Test name
Test status
Simulation time 131048100 ps
CPU time 1.58 seconds
Started Jul 03 07:12:55 PM PDT 24
Finished Jul 03 07:12:58 PM PDT 24
Peak memory 213372 kb
Host smart-c14a4650-a618-4c28-8879-94431dba3726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171671848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.1171671848
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.2514727113
Short name T364
Test name
Test status
Simulation time 1120520917 ps
CPU time 24.38 seconds
Started Jul 03 07:12:58 PM PDT 24
Finished Jul 03 07:13:23 PM PDT 24
Peak memory 250520 kb
Host smart-bd8710ef-fe50-4944-9a6b-d3b3898cfe31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514727113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.2514727113
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.2097922263
Short name T326
Test name
Test status
Simulation time 55032247 ps
CPU time 8.69 seconds
Started Jul 03 07:12:56 PM PDT 24
Finished Jul 03 07:13:06 PM PDT 24
Peak memory 250524 kb
Host smart-f0bb3417-633d-418b-9c63-3d1cf8b674a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097922263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.2097922263
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.723443532
Short name T793
Test name
Test status
Simulation time 5903647710 ps
CPU time 120.94 seconds
Started Jul 03 07:13:00 PM PDT 24
Finished Jul 03 07:15:01 PM PDT 24
Peak memory 276520 kb
Host smart-1d01fa2d-0385-42f5-86bc-1ebf0b2e4e85
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723443532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.723443532
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.2710227697
Short name T57
Test name
Test status
Simulation time 99032825686 ps
CPU time 2618.73 seconds
Started Jul 03 07:13:01 PM PDT 24
Finished Jul 03 07:56:42 PM PDT 24
Peak memory 944092 kb
Host smart-78e12655-a465-4210-a55b-7e5bc50c77be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2710227697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all_with_rand_reset.2710227697
Directory /workspace/24.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.924811661
Short name T752
Test name
Test status
Simulation time 15576185 ps
CPU time 0.85 seconds
Started Jul 03 07:12:55 PM PDT 24
Finished Jul 03 07:12:57 PM PDT 24
Peak memory 208364 kb
Host smart-df18346b-f91c-4a9a-b0d6-d0ff91259c7e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924811661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ct
rl_volatile_unlock_smoke.924811661
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.1468816040
Short name T92
Test name
Test status
Simulation time 20788567 ps
CPU time 1.23 seconds
Started Jul 03 07:13:01 PM PDT 24
Finished Jul 03 07:13:03 PM PDT 24
Peak memory 208484 kb
Host smart-8fd1843f-a08a-4401-ab3b-9f87ea7b8b75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468816040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.1468816040
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.19774146
Short name T217
Test name
Test status
Simulation time 1277911410 ps
CPU time 11 seconds
Started Jul 03 07:13:03 PM PDT 24
Finished Jul 03 07:13:15 PM PDT 24
Peak memory 225640 kb
Host smart-f14ef27a-b1d6-4d0e-827c-3525036bea28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19774146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.19774146
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.521319639
Short name T713
Test name
Test status
Simulation time 6044900293 ps
CPU time 6.74 seconds
Started Jul 03 07:12:59 PM PDT 24
Finished Jul 03 07:13:07 PM PDT 24
Peak memory 217264 kb
Host smart-d9dce492-8d9b-4390-b941-6db9e49105a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521319639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.521319639
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.4097599573
Short name T505
Test name
Test status
Simulation time 268606462 ps
CPU time 2.9 seconds
Started Jul 03 07:13:01 PM PDT 24
Finished Jul 03 07:13:05 PM PDT 24
Peak memory 222000 kb
Host smart-e0eed366-f2ee-4501-9c4b-0452c33ca5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097599573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.4097599573
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.867047229
Short name T789
Test name
Test status
Simulation time 5075282995 ps
CPU time 14.36 seconds
Started Jul 03 07:13:01 PM PDT 24
Finished Jul 03 07:13:16 PM PDT 24
Peak memory 225724 kb
Host smart-d733b098-7698-4c79-b76a-076e526b1532
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867047229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.867047229
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.2479742316
Short name T723
Test name
Test status
Simulation time 628812384 ps
CPU time 10.35 seconds
Started Jul 03 07:12:59 PM PDT 24
Finished Jul 03 07:13:10 PM PDT 24
Peak memory 225536 kb
Host smart-2828e9ec-01dd-46ed-bfb6-572b3eb13bc5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479742316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.2479742316
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.3045516499
Short name T421
Test name
Test status
Simulation time 869601772 ps
CPU time 8.28 seconds
Started Jul 03 07:13:00 PM PDT 24
Finished Jul 03 07:13:09 PM PDT 24
Peak memory 217740 kb
Host smart-11090d60-359f-4bfe-9151-ffbf92f48874
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045516499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
3045516499
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.765032549
Short name T621
Test name
Test status
Simulation time 317503155 ps
CPU time 8.04 seconds
Started Jul 03 07:13:01 PM PDT 24
Finished Jul 03 07:13:10 PM PDT 24
Peak memory 224672 kb
Host smart-eaf88def-bdfd-474c-85e4-396134cf2612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765032549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.765032549
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.1234153521
Short name T483
Test name
Test status
Simulation time 121166711 ps
CPU time 2.24 seconds
Started Jul 03 07:13:01 PM PDT 24
Finished Jul 03 07:13:04 PM PDT 24
Peak memory 217228 kb
Host smart-e78eb6fd-05e6-4376-92c2-a2ded8a08036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234153521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.1234153521
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.3671046262
Short name T683
Test name
Test status
Simulation time 697969151 ps
CPU time 21.06 seconds
Started Jul 03 07:13:03 PM PDT 24
Finished Jul 03 07:13:25 PM PDT 24
Peak memory 250516 kb
Host smart-f04373f2-1b00-48e0-9834-29f36ccc449b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671046262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.3671046262
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.4076855917
Short name T848
Test name
Test status
Simulation time 76789338 ps
CPU time 6.62 seconds
Started Jul 03 07:13:00 PM PDT 24
Finished Jul 03 07:13:07 PM PDT 24
Peak memory 250544 kb
Host smart-a51a5a90-d7f5-443c-abec-2ee94c9e3ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076855917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.4076855917
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.104113986
Short name T660
Test name
Test status
Simulation time 2413310903 ps
CPU time 89.77 seconds
Started Jul 03 07:12:59 PM PDT 24
Finished Jul 03 07:14:29 PM PDT 24
Peak memory 269304 kb
Host smart-de5e68ad-d8fb-4ed0-979d-fa7484a68c68
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104113986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.104113986
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.14855331
Short name T648
Test name
Test status
Simulation time 25051297 ps
CPU time 0.97 seconds
Started Jul 03 07:12:59 PM PDT 24
Finished Jul 03 07:13:00 PM PDT 24
Peak memory 208676 kb
Host smart-c1ba38f7-bb75-41a8-a0e9-cad40ac63869
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14855331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctr
l_volatile_unlock_smoke.14855331
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.3446361550
Short name T70
Test name
Test status
Simulation time 84293162 ps
CPU time 1.21 seconds
Started Jul 03 07:13:10 PM PDT 24
Finished Jul 03 07:13:12 PM PDT 24
Peak memory 208608 kb
Host smart-dfc3f85d-c76c-4526-9afd-f6898d7963b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446361550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.3446361550
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.240928377
Short name T56
Test name
Test status
Simulation time 617602196 ps
CPU time 12.76 seconds
Started Jul 03 07:13:05 PM PDT 24
Finished Jul 03 07:13:19 PM PDT 24
Peak memory 217708 kb
Host smart-1b9ebc80-0a3b-48f3-8b7d-c1c65b6a1ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240928377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.240928377
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.391344661
Short name T411
Test name
Test status
Simulation time 3406635831 ps
CPU time 7.41 seconds
Started Jul 03 07:13:03 PM PDT 24
Finished Jul 03 07:13:11 PM PDT 24
Peak memory 217236 kb
Host smart-51448c65-a0a6-4c96-b914-37e4bfdec408
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391344661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.391344661
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.2862610522
Short name T391
Test name
Test status
Simulation time 27087050 ps
CPU time 1.95 seconds
Started Jul 03 07:13:04 PM PDT 24
Finished Jul 03 07:13:07 PM PDT 24
Peak memory 217768 kb
Host smart-6c6bcffa-d9f3-4865-876a-9d006e5fa5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862610522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.2862610522
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.2404199932
Short name T457
Test name
Test status
Simulation time 1560051093 ps
CPU time 16.01 seconds
Started Jul 03 07:13:04 PM PDT 24
Finished Jul 03 07:13:21 PM PDT 24
Peak memory 225532 kb
Host smart-3811331a-666f-490a-ad05-6afd4f8bb529
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404199932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.2404199932
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.1273698168
Short name T209
Test name
Test status
Simulation time 639057001 ps
CPU time 12.39 seconds
Started Jul 03 07:13:05 PM PDT 24
Finished Jul 03 07:13:18 PM PDT 24
Peak memory 225536 kb
Host smart-cb7ef067-f724-4691-9e30-70af723114da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273698168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
1273698168
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.3181272884
Short name T850
Test name
Test status
Simulation time 411902245 ps
CPU time 9.86 seconds
Started Jul 03 07:13:04 PM PDT 24
Finished Jul 03 07:13:15 PM PDT 24
Peak memory 217808 kb
Host smart-bd1b596b-aec7-494b-a927-dbe6b7f4a94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181272884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.3181272884
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.1471174694
Short name T550
Test name
Test status
Simulation time 22026736 ps
CPU time 1.31 seconds
Started Jul 03 07:13:04 PM PDT 24
Finished Jul 03 07:13:07 PM PDT 24
Peak memory 222348 kb
Host smart-9aa8b9c3-5d7d-429f-82e2-2fbe282978db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471174694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.1471174694
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.1641901620
Short name T634
Test name
Test status
Simulation time 2945139690 ps
CPU time 23.91 seconds
Started Jul 03 07:13:03 PM PDT 24
Finished Jul 03 07:13:28 PM PDT 24
Peak memory 250584 kb
Host smart-d615858e-f7d7-490e-810b-8dd3a9a640ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641901620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.1641901620
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.4020052493
Short name T199
Test name
Test status
Simulation time 72336354 ps
CPU time 6.16 seconds
Started Jul 03 07:13:04 PM PDT 24
Finished Jul 03 07:13:11 PM PDT 24
Peak memory 249888 kb
Host smart-9b83fe80-f4e9-4dd6-92b4-1dffc038d873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020052493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.4020052493
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.1460350899
Short name T762
Test name
Test status
Simulation time 53987441227 ps
CPU time 877.44 seconds
Started Jul 03 07:13:04 PM PDT 24
Finished Jul 03 07:27:42 PM PDT 24
Peak memory 316252 kb
Host smart-aae799a0-0e13-40bc-8949-6ed76a1862d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1460350899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all_with_rand_reset.1460350899
Directory /workspace/26.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.3299446045
Short name T827
Test name
Test status
Simulation time 30874066 ps
CPU time 0.8 seconds
Started Jul 03 07:13:04 PM PDT 24
Finished Jul 03 07:13:06 PM PDT 24
Peak memory 207672 kb
Host smart-629ec15e-66c6-4acd-b071-e4d15995e361
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299446045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.3299446045
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.3088573849
Short name T652
Test name
Test status
Simulation time 19097006 ps
CPU time 0.89 seconds
Started Jul 03 07:13:14 PM PDT 24
Finished Jul 03 07:13:16 PM PDT 24
Peak memory 208632 kb
Host smart-e1f1a8c7-e53e-4bae-9f4f-15cd81a107ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088573849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.3088573849
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.3910188499
Short name T278
Test name
Test status
Simulation time 325521927 ps
CPU time 11.23 seconds
Started Jul 03 07:13:14 PM PDT 24
Finished Jul 03 07:13:27 PM PDT 24
Peak memory 217776 kb
Host smart-36b6aac3-83fd-448c-9e74-7f826c645602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910188499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.3910188499
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.2317184527
Short name T27
Test name
Test status
Simulation time 2751621407 ps
CPU time 16.31 seconds
Started Jul 03 07:13:14 PM PDT 24
Finished Jul 03 07:13:32 PM PDT 24
Peak memory 217200 kb
Host smart-c8fddf49-b82f-4ad1-abaa-59d2c5d0fe89
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317184527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.2317184527
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.888926538
Short name T745
Test name
Test status
Simulation time 234094200 ps
CPU time 3.57 seconds
Started Jul 03 07:13:15 PM PDT 24
Finished Jul 03 07:13:20 PM PDT 24
Peak memory 217652 kb
Host smart-dac308a9-1dd1-492c-b492-8ba24463b950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888926538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.888926538
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.497945230
Short name T602
Test name
Test status
Simulation time 1931258814 ps
CPU time 10.11 seconds
Started Jul 03 07:13:15 PM PDT 24
Finished Jul 03 07:13:26 PM PDT 24
Peak memory 225496 kb
Host smart-51d31db6-0313-49bd-b322-0b4227462d8c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497945230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_di
gest.497945230
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.2896722790
Short name T839
Test name
Test status
Simulation time 228298333 ps
CPU time 5.96 seconds
Started Jul 03 07:13:15 PM PDT 24
Finished Jul 03 07:13:22 PM PDT 24
Peak memory 224168 kb
Host smart-0c498ec9-c1b5-4b88-a6e8-df9847707e05
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896722790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
2896722790
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.3407371224
Short name T486
Test name
Test status
Simulation time 582540523 ps
CPU time 9.06 seconds
Started Jul 03 07:13:16 PM PDT 24
Finished Jul 03 07:13:25 PM PDT 24
Peak memory 217720 kb
Host smart-e7312e50-a15f-403b-8e29-cebea943fe58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407371224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.3407371224
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.2171194245
Short name T78
Test name
Test status
Simulation time 49085940 ps
CPU time 1.87 seconds
Started Jul 03 07:13:09 PM PDT 24
Finished Jul 03 07:13:11 PM PDT 24
Peak memory 213644 kb
Host smart-863bcd22-1e94-4d57-91e8-94cb2c8d3cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171194245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.2171194245
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.1543954251
Short name T220
Test name
Test status
Simulation time 441809827 ps
CPU time 29.88 seconds
Started Jul 03 07:13:08 PM PDT 24
Finished Jul 03 07:13:39 PM PDT 24
Peak memory 250540 kb
Host smart-9d6bf748-b71b-49ae-aa63-ff10d007f8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543954251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.1543954251
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.1278442264
Short name T298
Test name
Test status
Simulation time 204679340 ps
CPU time 8.89 seconds
Started Jul 03 07:13:16 PM PDT 24
Finished Jul 03 07:13:26 PM PDT 24
Peak memory 250508 kb
Host smart-b7e1fb6e-21c1-4cae-a9fa-27c498132efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278442264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.1278442264
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.4117034116
Short name T615
Test name
Test status
Simulation time 1644863129 ps
CPU time 27.87 seconds
Started Jul 03 07:13:13 PM PDT 24
Finished Jul 03 07:13:42 PM PDT 24
Peak memory 250572 kb
Host smart-cbae8434-e59b-4dd3-a014-f0db4c290d39
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117034116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.4117034116
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.2880747248
Short name T32
Test name
Test status
Simulation time 15831261 ps
CPU time 1.1 seconds
Started Jul 03 07:13:08 PM PDT 24
Finished Jul 03 07:13:10 PM PDT 24
Peak memory 211508 kb
Host smart-86283d16-80cc-4093-ad08-6a3003a79b7f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880747248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.2880747248
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.772515282
Short name T313
Test name
Test status
Simulation time 26743490 ps
CPU time 1.03 seconds
Started Jul 03 07:14:03 PM PDT 24
Finished Jul 03 07:14:05 PM PDT 24
Peak memory 208620 kb
Host smart-a853c8f4-c35f-42b7-9e31-59210ef9acfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772515282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.772515282
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.4098656065
Short name T811
Test name
Test status
Simulation time 545410954 ps
CPU time 12.97 seconds
Started Jul 03 07:13:13 PM PDT 24
Finished Jul 03 07:13:28 PM PDT 24
Peak memory 217744 kb
Host smart-e429f480-3caf-4c0e-95ed-fb0db22c34ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098656065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.4098656065
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.1708963330
Short name T465
Test name
Test status
Simulation time 99950166 ps
CPU time 1.22 seconds
Started Jul 03 07:13:13 PM PDT 24
Finished Jul 03 07:13:15 PM PDT 24
Peak memory 217192 kb
Host smart-38ec8b3d-749f-4ff9-b6d1-fabfe642ab90
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708963330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.1708963330
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.1043222981
Short name T669
Test name
Test status
Simulation time 299368001 ps
CPU time 3.34 seconds
Started Jul 03 07:13:13 PM PDT 24
Finished Jul 03 07:13:18 PM PDT 24
Peak memory 221884 kb
Host smart-1bea1c92-818e-42b3-83c6-9cbdd85b9547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043222981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.1043222981
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.46577783
Short name T670
Test name
Test status
Simulation time 2530111481 ps
CPU time 14.63 seconds
Started Jul 03 07:13:13 PM PDT 24
Finished Jul 03 07:13:29 PM PDT 24
Peak memory 219868 kb
Host smart-76002413-a9fd-452d-a12c-8c34868daa8a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46577783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.46577783
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.756583113
Short name T201
Test name
Test status
Simulation time 670916185 ps
CPU time 11.15 seconds
Started Jul 03 07:13:18 PM PDT 24
Finished Jul 03 07:13:30 PM PDT 24
Peak memory 217748 kb
Host smart-0cc5d5f1-c50e-4fcc-bac9-d830e728a6ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756583113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_di
gest.756583113
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.3104787436
Short name T696
Test name
Test status
Simulation time 288105182 ps
CPU time 7.16 seconds
Started Jul 03 07:13:17 PM PDT 24
Finished Jul 03 07:13:26 PM PDT 24
Peak memory 217684 kb
Host smart-b83ea5a4-ab21-4ad0-ab5b-cb6c297c8e69
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104787436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
3104787436
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.1471483229
Short name T358
Test name
Test status
Simulation time 1635919912 ps
CPU time 8.81 seconds
Started Jul 03 07:13:17 PM PDT 24
Finished Jul 03 07:13:27 PM PDT 24
Peak memory 225392 kb
Host smart-2cd7a331-cdb7-444e-957c-a99503181401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471483229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.1471483229
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.2922043036
Short name T368
Test name
Test status
Simulation time 54679813 ps
CPU time 3.31 seconds
Started Jul 03 07:13:13 PM PDT 24
Finished Jul 03 07:13:18 PM PDT 24
Peak memory 222264 kb
Host smart-31a5626b-1594-4317-906b-bf5071fd25a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922043036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.2922043036
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.2211212588
Short name T857
Test name
Test status
Simulation time 293111330 ps
CPU time 28.89 seconds
Started Jul 03 07:13:17 PM PDT 24
Finished Jul 03 07:13:46 PM PDT 24
Peak memory 250512 kb
Host smart-5a7fdf07-5e29-4e73-86e8-eeeb363890da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211212588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.2211212588
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.928863980
Short name T47
Test name
Test status
Simulation time 86073484 ps
CPU time 7.08 seconds
Started Jul 03 07:13:13 PM PDT 24
Finished Jul 03 07:13:21 PM PDT 24
Peak memory 249952 kb
Host smart-cda7d329-ae1a-47be-8022-5086ad970de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928863980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.928863980
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.23862220
Short name T381
Test name
Test status
Simulation time 11350883733 ps
CPU time 88.29 seconds
Started Jul 03 07:13:17 PM PDT 24
Finished Jul 03 07:14:46 PM PDT 24
Peak memory 248004 kb
Host smart-fcabef37-d921-4663-8fc2-a38cc2dc9723
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23862220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.lc_ctrl_stress_all.23862220
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.4153126749
Short name T42
Test name
Test status
Simulation time 24228050 ps
CPU time 0.79 seconds
Started Jul 03 07:13:14 PM PDT 24
Finished Jul 03 07:13:16 PM PDT 24
Peak memory 208388 kb
Host smart-cb9590ce-89a0-44d6-b595-175ce503b146
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153126749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.4153126749
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.308409812
Short name T98
Test name
Test status
Simulation time 290567221 ps
CPU time 1.04 seconds
Started Jul 03 07:14:06 PM PDT 24
Finished Jul 03 07:14:11 PM PDT 24
Peak memory 208696 kb
Host smart-01a0cb2c-5f97-4fc5-87ea-186a2e3ff740
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308409812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.308409812
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.3604026728
Short name T772
Test name
Test status
Simulation time 195943146 ps
CPU time 9.42 seconds
Started Jul 03 07:14:02 PM PDT 24
Finished Jul 03 07:14:13 PM PDT 24
Peak memory 217740 kb
Host smart-96026d8d-11c6-459e-9f65-9f7f56d1b300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604026728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.3604026728
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.422995171
Short name T611
Test name
Test status
Simulation time 4728049148 ps
CPU time 7.16 seconds
Started Jul 03 07:14:00 PM PDT 24
Finished Jul 03 07:14:10 PM PDT 24
Peak memory 217252 kb
Host smart-9533cc26-d779-4757-b263-8437d3fc3881
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422995171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.422995171
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.1038827129
Short name T325
Test name
Test status
Simulation time 57783636 ps
CPU time 3.15 seconds
Started Jul 03 07:14:04 PM PDT 24
Finished Jul 03 07:14:10 PM PDT 24
Peak memory 221848 kb
Host smart-6e8664bb-d515-48ec-9cfa-4061d01b0d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038827129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.1038827129
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.3328131519
Short name T508
Test name
Test status
Simulation time 300850031 ps
CPU time 10.15 seconds
Started Jul 03 07:14:02 PM PDT 24
Finished Jul 03 07:14:14 PM PDT 24
Peak memory 225472 kb
Host smart-9dcf02cf-8c70-4c19-9ad0-de917754c57d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328131519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.3328131519
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.2917415719
Short name T488
Test name
Test status
Simulation time 748328284 ps
CPU time 12.83 seconds
Started Jul 03 07:14:01 PM PDT 24
Finished Jul 03 07:14:16 PM PDT 24
Peak memory 217692 kb
Host smart-5c7a35db-da3d-4a0e-acb5-3cb9dcc9382c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917415719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
2917415719
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.2842074947
Short name T33
Test name
Test status
Simulation time 292729006 ps
CPU time 11.77 seconds
Started Jul 03 07:14:01 PM PDT 24
Finished Jul 03 07:14:15 PM PDT 24
Peak memory 225292 kb
Host smart-4e3ada88-697f-4bf2-b68d-8d9d7be8fe0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842074947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.2842074947
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.2049417727
Short name T79
Test name
Test status
Simulation time 16962004 ps
CPU time 1.07 seconds
Started Jul 03 07:14:00 PM PDT 24
Finished Jul 03 07:14:03 PM PDT 24
Peak memory 211408 kb
Host smart-5f823ef3-c029-41b3-b487-857860386d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049417727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.2049417727
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.4008466063
Short name T464
Test name
Test status
Simulation time 746149835 ps
CPU time 17.55 seconds
Started Jul 03 07:14:00 PM PDT 24
Finished Jul 03 07:14:20 PM PDT 24
Peak memory 250544 kb
Host smart-5407f514-dee9-438c-96fd-03d90226414d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008466063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.4008466063
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.2751311280
Short name T318
Test name
Test status
Simulation time 74491645 ps
CPU time 8.48 seconds
Started Jul 03 07:13:59 PM PDT 24
Finished Jul 03 07:14:09 PM PDT 24
Peak memory 250540 kb
Host smart-9d9577db-6f81-492e-9379-7f49642cfa75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751311280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.2751311280
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.1545519696
Short name T291
Test name
Test status
Simulation time 6361599192 ps
CPU time 97.34 seconds
Started Jul 03 07:14:05 PM PDT 24
Finished Jul 03 07:15:45 PM PDT 24
Peak memory 258848 kb
Host smart-a825433c-9825-4b9b-a5e1-8a35db3321d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545519696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.1545519696
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.3080393658
Short name T449
Test name
Test status
Simulation time 49609837 ps
CPU time 0.81 seconds
Started Jul 03 07:14:04 PM PDT 24
Finished Jul 03 07:14:06 PM PDT 24
Peak memory 208360 kb
Host smart-46f1e79f-35cb-4936-81ae-3f1c466a0dc2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080393658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.3080393658
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.2106110864
Short name T320
Test name
Test status
Simulation time 19668119 ps
CPU time 0.91 seconds
Started Jul 03 07:10:52 PM PDT 24
Finished Jul 03 07:11:25 PM PDT 24
Peak memory 208496 kb
Host smart-7f327086-6110-4b25-bf85-85db63ed4686
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106110864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.2106110864
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.3300830740
Short name T714
Test name
Test status
Simulation time 40438800 ps
CPU time 0.83 seconds
Started Jul 03 07:10:52 PM PDT 24
Finished Jul 03 07:11:25 PM PDT 24
Peak memory 208264 kb
Host smart-ae930e87-8f69-4a3e-8e94-dc5e54a57611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300830740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.3300830740
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.325188479
Short name T285
Test name
Test status
Simulation time 560613783 ps
CPU time 14.78 seconds
Started Jul 03 07:10:48 PM PDT 24
Finished Jul 03 07:11:35 PM PDT 24
Peak memory 217788 kb
Host smart-25c6a530-aaa3-4774-8c1d-467d17834a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325188479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.325188479
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.736674162
Short name T828
Test name
Test status
Simulation time 239660230 ps
CPU time 3.7 seconds
Started Jul 03 07:10:52 PM PDT 24
Finished Jul 03 07:11:27 PM PDT 24
Peak memory 216932 kb
Host smart-fd147ec1-1c9c-4830-bddb-59380c4b5a0a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736674162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.736674162
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.2320565727
Short name T582
Test name
Test status
Simulation time 1666707551 ps
CPU time 19.92 seconds
Started Jul 03 07:10:53 PM PDT 24
Finished Jul 03 07:11:46 PM PDT 24
Peak memory 217712 kb
Host smart-3c12e4a9-8cd3-4e68-b2c1-c3c7b8f26a71
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320565727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.2320565727
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.901514509
Short name T300
Test name
Test status
Simulation time 292770852 ps
CPU time 1.62 seconds
Started Jul 03 07:10:55 PM PDT 24
Finished Jul 03 07:11:30 PM PDT 24
Peak memory 217164 kb
Host smart-b86210d4-96d5-4bf5-b755-982991a4f2b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901514509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.901514509
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.1359450008
Short name T466
Test name
Test status
Simulation time 539250467 ps
CPU time 5.45 seconds
Started Jul 03 07:10:54 PM PDT 24
Finished Jul 03 07:11:34 PM PDT 24
Peak memory 222668 kb
Host smart-58956e06-a3e2-4700-9c1f-17a772fe93dd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359450008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.1359450008
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.299424232
Short name T557
Test name
Test status
Simulation time 952847532 ps
CPU time 25.64 seconds
Started Jul 03 07:10:54 PM PDT 24
Finished Jul 03 07:11:54 PM PDT 24
Peak memory 217020 kb
Host smart-314a1899-920c-4cd8-a921-67e92abf383e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299424232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_j
tag_regwen_during_op.299424232
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.2337174555
Short name T80
Test name
Test status
Simulation time 1482611050 ps
CPU time 9.07 seconds
Started Jul 03 07:10:54 PM PDT 24
Finished Jul 03 07:11:37 PM PDT 24
Peak memory 217140 kb
Host smart-2f92fa06-53e3-4bcd-aff2-cf07bcb71997
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337174555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
2337174555
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.2964445487
Short name T822
Test name
Test status
Simulation time 1348988380 ps
CPU time 53.11 seconds
Started Jul 03 07:10:55 PM PDT 24
Finished Jul 03 07:12:22 PM PDT 24
Peak memory 266868 kb
Host smart-dcd399ee-ffc9-4058-8743-625f94169f70
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964445487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.2964445487
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.2076621876
Short name T538
Test name
Test status
Simulation time 1776486740 ps
CPU time 13.85 seconds
Started Jul 03 07:10:54 PM PDT 24
Finished Jul 03 07:11:42 PM PDT 24
Peak memory 222328 kb
Host smart-9318955a-e392-43c4-86d6-8cfbb7b9c0aa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076621876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.2076621876
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.1793075605
Short name T689
Test name
Test status
Simulation time 78095575 ps
CPU time 2.45 seconds
Started Jul 03 07:10:49 PM PDT 24
Finished Jul 03 07:11:23 PM PDT 24
Peak memory 217664 kb
Host smart-18037210-0c6f-4069-8c1b-f9dffabc739e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793075605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.1793075605
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.619637034
Short name T131
Test name
Test status
Simulation time 205088886 ps
CPU time 6.21 seconds
Started Jul 03 07:10:55 PM PDT 24
Finished Jul 03 07:11:35 PM PDT 24
Peak memory 213956 kb
Host smart-71511784-d5ca-41f3-9cc1-6120162b8f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619637034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.619637034
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.4018116227
Short name T89
Test name
Test status
Simulation time 510331547 ps
CPU time 24.68 seconds
Started Jul 03 07:10:54 PM PDT 24
Finished Jul 03 07:11:53 PM PDT 24
Peak memory 282440 kb
Host smart-73dc37e1-3622-4a98-bf08-449d3c650d8a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018116227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.4018116227
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.4240105146
Short name T675
Test name
Test status
Simulation time 671193853 ps
CPU time 8.99 seconds
Started Jul 03 07:10:54 PM PDT 24
Finished Jul 03 07:11:37 PM PDT 24
Peak memory 217664 kb
Host smart-90b59b08-47ca-443a-b5b7-592e14580df8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240105146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.4240105146
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.2157298473
Short name T869
Test name
Test status
Simulation time 1176237316 ps
CPU time 8.71 seconds
Started Jul 03 07:10:53 PM PDT 24
Finished Jul 03 07:11:35 PM PDT 24
Peak memory 225496 kb
Host smart-dc90d649-0f35-4f92-b11d-3c1b7f4758bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157298473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.2157298473
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.676765454
Short name T366
Test name
Test status
Simulation time 306456817 ps
CPU time 9.89 seconds
Started Jul 03 07:10:51 PM PDT 24
Finished Jul 03 07:11:33 PM PDT 24
Peak memory 225496 kb
Host smart-e33d4330-6e36-4e9b-9c81-8e485c61c41a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676765454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.676765454
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.3710695562
Short name T854
Test name
Test status
Simulation time 550201097 ps
CPU time 8.35 seconds
Started Jul 03 07:10:47 PM PDT 24
Finished Jul 03 07:11:28 PM PDT 24
Peak memory 217864 kb
Host smart-71658ec2-56c2-4c24-9b86-7aa6045448dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710695562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.3710695562
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.830577109
Short name T588
Test name
Test status
Simulation time 173859844 ps
CPU time 2.43 seconds
Started Jul 03 07:10:48 PM PDT 24
Finished Jul 03 07:11:22 PM PDT 24
Peak memory 217152 kb
Host smart-58076176-9d3a-4780-9400-bbeaa7211113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830577109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.830577109
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.3402715288
Short name T152
Test name
Test status
Simulation time 526257827 ps
CPU time 30.48 seconds
Started Jul 03 07:10:50 PM PDT 24
Finished Jul 03 07:11:53 PM PDT 24
Peak memory 250544 kb
Host smart-884a43f7-7ee2-4afa-9f16-5ad95ac16fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402715288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.3402715288
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.1409648408
Short name T573
Test name
Test status
Simulation time 80978543 ps
CPU time 8.64 seconds
Started Jul 03 07:10:50 PM PDT 24
Finished Jul 03 07:11:31 PM PDT 24
Peak memory 250520 kb
Host smart-d16a5001-5a74-4658-bc12-761096ab6687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409648408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.1409648408
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.3431010797
Short name T168
Test name
Test status
Simulation time 12015011844 ps
CPU time 207.05 seconds
Started Jul 03 07:10:53 PM PDT 24
Finished Jul 03 07:14:53 PM PDT 24
Peak memory 266968 kb
Host smart-86ce6b3f-52ab-41ff-9109-88c85b23dd62
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431010797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.3431010797
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1446114068
Short name T101
Test name
Test status
Simulation time 21319573 ps
CPU time 0.87 seconds
Started Jul 03 07:10:49 PM PDT 24
Finished Jul 03 07:11:21 PM PDT 24
Peak memory 208096 kb
Host smart-5a27ad47-7273-4401-9a9e-a1e90080bfc3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446114068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.1446114068
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.1744329255
Short name T232
Test name
Test status
Simulation time 17163182 ps
CPU time 0.96 seconds
Started Jul 03 07:14:04 PM PDT 24
Finished Jul 03 07:14:07 PM PDT 24
Peak memory 208552 kb
Host smart-0c6afabd-b0ca-4ea3-b498-9e56321e135e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744329255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.1744329255
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.3172686019
Short name T740
Test name
Test status
Simulation time 1250070155 ps
CPU time 11.6 seconds
Started Jul 03 07:14:06 PM PDT 24
Finished Jul 03 07:14:22 PM PDT 24
Peak memory 217772 kb
Host smart-5d4ccd6b-5be9-4858-9f51-b626035fb34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172686019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.3172686019
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.111446896
Short name T29
Test name
Test status
Simulation time 1936934485 ps
CPU time 5.68 seconds
Started Jul 03 07:14:07 PM PDT 24
Finished Jul 03 07:14:17 PM PDT 24
Peak memory 217196 kb
Host smart-e107b69d-2067-46ed-9dad-7e8b273f9e76
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111446896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.111446896
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.4195876032
Short name T592
Test name
Test status
Simulation time 224810293 ps
CPU time 2.43 seconds
Started Jul 03 07:14:06 PM PDT 24
Finished Jul 03 07:14:11 PM PDT 24
Peak memory 217752 kb
Host smart-eb4f900b-24c4-4be3-8ced-7e49073b724a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195876032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.4195876032
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.2584330810
Short name T578
Test name
Test status
Simulation time 687838542 ps
CPU time 15.4 seconds
Started Jul 03 07:14:06 PM PDT 24
Finished Jul 03 07:14:25 PM PDT 24
Peak memory 225652 kb
Host smart-ce955c14-ad10-4800-9a7e-7eee31c46bdd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584330810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.2584330810
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.3227071686
Short name T711
Test name
Test status
Simulation time 971218531 ps
CPU time 19.78 seconds
Started Jul 03 07:14:06 PM PDT 24
Finished Jul 03 07:14:30 PM PDT 24
Peak memory 225500 kb
Host smart-07346a15-f3d6-418b-af90-bde3b66aed77
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227071686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.3227071686
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.3486770460
Short name T556
Test name
Test status
Simulation time 446196473 ps
CPU time 12.2 seconds
Started Jul 03 07:14:06 PM PDT 24
Finished Jul 03 07:14:22 PM PDT 24
Peak memory 217732 kb
Host smart-4bbc05dd-b786-4b92-8da5-44dff68424db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486770460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
3486770460
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.4177554549
Short name T357
Test name
Test status
Simulation time 484323340 ps
CPU time 6.18 seconds
Started Jul 03 07:14:04 PM PDT 24
Finished Jul 03 07:14:12 PM PDT 24
Peak memory 223936 kb
Host smart-235e8233-c7d8-4a44-ae70-95387e9b7e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177554549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.4177554549
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.936871681
Short name T71
Test name
Test status
Simulation time 69846486 ps
CPU time 3.55 seconds
Started Jul 03 07:14:06 PM PDT 24
Finished Jul 03 07:14:14 PM PDT 24
Peak memory 217216 kb
Host smart-a9699e3c-064d-4cc5-bb21-e2c09f0cb968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936871681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.936871681
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.3668359173
Short name T595
Test name
Test status
Simulation time 321650662 ps
CPU time 20.35 seconds
Started Jul 03 07:14:06 PM PDT 24
Finished Jul 03 07:14:29 PM PDT 24
Peak memory 250528 kb
Host smart-5370b38b-ff03-4901-b527-b2bb9b91aca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668359173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.3668359173
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.3043445099
Short name T647
Test name
Test status
Simulation time 112596943 ps
CPU time 7.65 seconds
Started Jul 03 07:14:06 PM PDT 24
Finished Jul 03 07:14:17 PM PDT 24
Peak memory 250484 kb
Host smart-b5736bf6-a7a6-4098-ab6d-c36835eac260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043445099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.3043445099
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.2199111254
Short name T635
Test name
Test status
Simulation time 18144152381 ps
CPU time 44.94 seconds
Started Jul 03 07:14:07 PM PDT 24
Finished Jul 03 07:14:55 PM PDT 24
Peak memory 275312 kb
Host smart-b2668d0f-7fa2-4f04-873b-fb2a4049bfe8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199111254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.2199111254
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.438550947
Short name T341
Test name
Test status
Simulation time 18368041 ps
CPU time 1.16 seconds
Started Jul 03 07:14:05 PM PDT 24
Finished Jul 03 07:14:09 PM PDT 24
Peak memory 217196 kb
Host smart-e2a3c17c-e0b8-4e6f-9101-9e33c5ac65a1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438550947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ct
rl_volatile_unlock_smoke.438550947
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.3993876485
Short name T632
Test name
Test status
Simulation time 24825381 ps
CPU time 0.99 seconds
Started Jul 03 07:14:09 PM PDT 24
Finished Jul 03 07:14:13 PM PDT 24
Peak memory 208480 kb
Host smart-14a87992-4e4e-4d9e-9437-0a6df68188ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993876485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.3993876485
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.1693458990
Short name T221
Test name
Test status
Simulation time 251114247 ps
CPU time 11.26 seconds
Started Jul 03 07:14:08 PM PDT 24
Finished Jul 03 07:14:22 PM PDT 24
Peak memory 217764 kb
Host smart-d0b3dac3-0537-4d1b-ba84-34ba0b70740b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693458990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.1693458990
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.1004653518
Short name T25
Test name
Test status
Simulation time 3624036407 ps
CPU time 9.05 seconds
Started Jul 03 07:14:04 PM PDT 24
Finished Jul 03 07:14:15 PM PDT 24
Peak memory 217204 kb
Host smart-d6b15410-9e77-44ba-88f9-23cd64da7de4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004653518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.1004653518
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.2729266462
Short name T671
Test name
Test status
Simulation time 104213059 ps
CPU time 4.44 seconds
Started Jul 03 07:14:06 PM PDT 24
Finished Jul 03 07:14:14 PM PDT 24
Peak memory 217744 kb
Host smart-372f5591-e9fb-4e83-996a-455e311748c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729266462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.2729266462
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.1951091223
Short name T532
Test name
Test status
Simulation time 732562731 ps
CPU time 12.69 seconds
Started Jul 03 07:14:04 PM PDT 24
Finished Jul 03 07:14:19 PM PDT 24
Peak memory 219488 kb
Host smart-81647ce7-49ba-444c-9b3c-87ed70e19ad6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951091223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.1951091223
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.2958930251
Short name T807
Test name
Test status
Simulation time 1840426844 ps
CPU time 11.75 seconds
Started Jul 03 07:14:05 PM PDT 24
Finished Jul 03 07:14:20 PM PDT 24
Peak memory 225496 kb
Host smart-6fab019e-d38b-4307-af6b-76ed901a3fa9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958930251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.2958930251
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.1042236027
Short name T664
Test name
Test status
Simulation time 1147756520 ps
CPU time 9.58 seconds
Started Jul 03 07:14:07 PM PDT 24
Finished Jul 03 07:14:20 PM PDT 24
Peak memory 217708 kb
Host smart-288f7be2-f371-4dfb-9377-e764856d1437
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042236027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
1042236027
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.3005347210
Short name T658
Test name
Test status
Simulation time 1647964243 ps
CPU time 11.88 seconds
Started Jul 03 07:14:05 PM PDT 24
Finished Jul 03 07:14:19 PM PDT 24
Peak memory 225528 kb
Host smart-0177b20b-067e-458e-9d29-71a6e343e062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005347210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.3005347210
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.1558610888
Short name T501
Test name
Test status
Simulation time 822091333 ps
CPU time 2.62 seconds
Started Jul 03 07:14:06 PM PDT 24
Finished Jul 03 07:14:12 PM PDT 24
Peak memory 214200 kb
Host smart-db8409bd-d473-46c5-a996-e1180e4c22fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558610888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.1558610888
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.1290450864
Short name T226
Test name
Test status
Simulation time 796789376 ps
CPU time 31.09 seconds
Started Jul 03 07:14:04 PM PDT 24
Finished Jul 03 07:14:37 PM PDT 24
Peak memory 250400 kb
Host smart-4aea48b1-ca4f-4273-81bb-bbafac20ebb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290450864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.1290450864
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.3393120717
Short name T775
Test name
Test status
Simulation time 65177008 ps
CPU time 6.29 seconds
Started Jul 03 07:14:05 PM PDT 24
Finished Jul 03 07:14:14 PM PDT 24
Peak memory 249972 kb
Host smart-575f2507-0584-4dde-9231-b6baa282e0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393120717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.3393120717
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.3020621820
Short name T720
Test name
Test status
Simulation time 30286757882 ps
CPU time 174.16 seconds
Started Jul 03 07:14:06 PM PDT 24
Finished Jul 03 07:17:05 PM PDT 24
Peak memory 272652 kb
Host smart-db710d5f-e692-4ed2-a7ac-ec2bb9e4505e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020621820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.3020621820
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.3847200954
Short name T376
Test name
Test status
Simulation time 13106963 ps
CPU time 0.95 seconds
Started Jul 03 07:14:06 PM PDT 24
Finished Jul 03 07:14:11 PM PDT 24
Peak memory 217380 kb
Host smart-a10b703d-c053-402e-9ec7-e7d0b51f1df5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847200954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.3847200954
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.4001962322
Short name T530
Test name
Test status
Simulation time 81080878 ps
CPU time 0.87 seconds
Started Jul 03 07:14:12 PM PDT 24
Finished Jul 03 07:14:16 PM PDT 24
Peak memory 208560 kb
Host smart-1c79fe17-7674-45bd-a70b-8867ce62b416
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001962322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.4001962322
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.2684402235
Short name T317
Test name
Test status
Simulation time 187036366 ps
CPU time 9.68 seconds
Started Jul 03 07:14:08 PM PDT 24
Finished Jul 03 07:14:21 PM PDT 24
Peak memory 217776 kb
Host smart-1b3d4070-1473-4e5e-a995-8624feea57ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684402235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.2684402235
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.1458702337
Short name T737
Test name
Test status
Simulation time 270413645 ps
CPU time 4.09 seconds
Started Jul 03 07:14:15 PM PDT 24
Finished Jul 03 07:14:22 PM PDT 24
Peak memory 216640 kb
Host smart-a412f39d-571a-4764-9a18-e0aab537fbec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458702337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.1458702337
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.1887748296
Short name T269
Test name
Test status
Simulation time 53625531 ps
CPU time 2.57 seconds
Started Jul 03 07:14:13 PM PDT 24
Finished Jul 03 07:14:19 PM PDT 24
Peak memory 221620 kb
Host smart-d9a89079-75a4-48f8-909e-a72ffb17d04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887748296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.1887748296
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.3552012099
Short name T53
Test name
Test status
Simulation time 325556664 ps
CPU time 10.08 seconds
Started Jul 03 07:14:12 PM PDT 24
Finished Jul 03 07:14:24 PM PDT 24
Peak memory 225692 kb
Host smart-60c06487-bf3a-49c3-a552-a476a1694f73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552012099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.3552012099
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.3931161239
Short name T252
Test name
Test status
Simulation time 960558806 ps
CPU time 8.88 seconds
Started Jul 03 07:14:10 PM PDT 24
Finished Jul 03 07:14:22 PM PDT 24
Peak memory 225480 kb
Host smart-12f97c9a-c207-4145-8b27-19d0b61ce5e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931161239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.3931161239
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.692784486
Short name T515
Test name
Test status
Simulation time 590717902 ps
CPU time 10.97 seconds
Started Jul 03 07:14:12 PM PDT 24
Finished Jul 03 07:14:26 PM PDT 24
Peak memory 217688 kb
Host smart-425c9624-5647-487b-9f6f-891c96921c50
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692784486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.692784486
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.2132485185
Short name T328
Test name
Test status
Simulation time 1888466058 ps
CPU time 14.88 seconds
Started Jul 03 07:14:13 PM PDT 24
Finished Jul 03 07:14:31 PM PDT 24
Peak memory 225676 kb
Host smart-558b6575-34ca-45af-acec-7db0effb35ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132485185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.2132485185
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.172148195
Short name T67
Test name
Test status
Simulation time 121063639 ps
CPU time 2.22 seconds
Started Jul 03 07:14:09 PM PDT 24
Finished Jul 03 07:14:15 PM PDT 24
Peak memory 222080 kb
Host smart-50fcd9af-fa9d-40a8-9ae9-512bba4a1744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172148195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.172148195
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.829501387
Short name T619
Test name
Test status
Simulation time 356913706 ps
CPU time 24.6 seconds
Started Jul 03 07:14:08 PM PDT 24
Finished Jul 03 07:14:36 PM PDT 24
Peak memory 250512 kb
Host smart-8687706b-600b-437e-9878-dfc0d01cfbd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829501387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.829501387
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.1533303501
Short name T426
Test name
Test status
Simulation time 244238549 ps
CPU time 6.78 seconds
Started Jul 03 07:14:12 PM PDT 24
Finished Jul 03 07:14:22 PM PDT 24
Peak memory 246868 kb
Host smart-378808f1-b6a5-4500-814e-cec0a4dcf5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533303501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.1533303501
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.3669750356
Short name T846
Test name
Test status
Simulation time 6383664534 ps
CPU time 34.81 seconds
Started Jul 03 07:14:11 PM PDT 24
Finished Jul 03 07:14:48 PM PDT 24
Peak memory 227628 kb
Host smart-14bd021a-08b7-4578-8c80-8d2cb315f117
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669750356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.3669750356
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.191466143
Short name T23
Test name
Test status
Simulation time 100010824 ps
CPU time 0.97 seconds
Started Jul 03 07:14:14 PM PDT 24
Finished Jul 03 07:14:19 PM PDT 24
Peak memory 212388 kb
Host smart-ac103344-edd2-4036-874c-551744a5d447
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191466143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ct
rl_volatile_unlock_smoke.191466143
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.2358714688
Short name T310
Test name
Test status
Simulation time 30396344 ps
CPU time 0.94 seconds
Started Jul 03 07:14:12 PM PDT 24
Finished Jul 03 07:14:16 PM PDT 24
Peak memory 208412 kb
Host smart-6f167a51-3e60-4a0f-a174-6678819bb134
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358714688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.2358714688
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.4278756362
Short name T107
Test name
Test status
Simulation time 250695215 ps
CPU time 12.97 seconds
Started Jul 03 07:14:10 PM PDT 24
Finished Jul 03 07:14:26 PM PDT 24
Peak memory 217780 kb
Host smart-3bd758be-88bd-49aa-b82e-ce8d6f46ac58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278756362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.4278756362
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.3524825328
Short name T829
Test name
Test status
Simulation time 553577392 ps
CPU time 5.68 seconds
Started Jul 03 07:14:14 PM PDT 24
Finished Jul 03 07:14:23 PM PDT 24
Peak memory 217180 kb
Host smart-e5e6165d-4999-4289-8d60-a8b0b7f07dbd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524825328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.3524825328
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.2752324070
Short name T742
Test name
Test status
Simulation time 127544793 ps
CPU time 2.98 seconds
Started Jul 03 07:14:12 PM PDT 24
Finished Jul 03 07:14:17 PM PDT 24
Peak memory 217652 kb
Host smart-8893b3cd-ea33-4115-9ace-15122a87bd33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752324070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.2752324070
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.2352374618
Short name T853
Test name
Test status
Simulation time 295974113 ps
CPU time 9.95 seconds
Started Jul 03 07:14:11 PM PDT 24
Finished Jul 03 07:14:24 PM PDT 24
Peak memory 218016 kb
Host smart-597b828c-279a-41b2-8e67-67730ef43e57
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352374618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.2352374618
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.2200170667
Short name T338
Test name
Test status
Simulation time 250040411 ps
CPU time 9.6 seconds
Started Jul 03 07:14:12 PM PDT 24
Finished Jul 03 07:14:24 PM PDT 24
Peak memory 225396 kb
Host smart-95bae7b6-6043-432d-981c-f18701dcc278
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200170667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.2200170667
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.1083296527
Short name T548
Test name
Test status
Simulation time 1309276485 ps
CPU time 12.84 seconds
Started Jul 03 07:14:14 PM PDT 24
Finished Jul 03 07:14:30 PM PDT 24
Peak memory 217612 kb
Host smart-d408ac63-a05d-4869-8471-cb409be7df25
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083296527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
1083296527
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.453195642
Short name T511
Test name
Test status
Simulation time 389371651 ps
CPU time 13.73 seconds
Started Jul 03 07:14:09 PM PDT 24
Finished Jul 03 07:14:26 PM PDT 24
Peak memory 225624 kb
Host smart-b63a3aa0-6d1d-4c80-a5ec-ab27fb41961f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453195642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.453195642
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.1536284830
Short name T537
Test name
Test status
Simulation time 28025690 ps
CPU time 2.31 seconds
Started Jul 03 07:14:12 PM PDT 24
Finished Jul 03 07:14:17 PM PDT 24
Peak memory 213568 kb
Host smart-c4635f55-f058-4591-8ecb-db5f499e6eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536284830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.1536284830
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.4281428720
Short name T284
Test name
Test status
Simulation time 271919739 ps
CPU time 26.95 seconds
Started Jul 03 07:14:13 PM PDT 24
Finished Jul 03 07:14:43 PM PDT 24
Peak memory 250488 kb
Host smart-ddfe87e9-5016-4ad1-bb93-982fb315facc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281428720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.4281428720
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.2568329773
Short name T808
Test name
Test status
Simulation time 87462970 ps
CPU time 9.37 seconds
Started Jul 03 07:14:13 PM PDT 24
Finished Jul 03 07:14:25 PM PDT 24
Peak memory 250484 kb
Host smart-100b7fcf-e2d6-4a96-b944-4129ec3b5df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568329773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.2568329773
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.3024106113
Short name T160
Test name
Test status
Simulation time 11787331630 ps
CPU time 55.79 seconds
Started Jul 03 07:14:11 PM PDT 24
Finished Jul 03 07:15:09 PM PDT 24
Peak memory 220344 kb
Host smart-074869aa-6c3c-46ec-b5f6-0c24c1415d7c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024106113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.3024106113
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.890963806
Short name T439
Test name
Test status
Simulation time 87818521961 ps
CPU time 340.77 seconds
Started Jul 03 07:14:12 PM PDT 24
Finished Jul 03 07:19:56 PM PDT 24
Peak memory 349252 kb
Host smart-ceaece73-56c5-4ee3-9250-ab788a7df8aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=890963806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.890963806
Directory /workspace/33.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.2736586723
Short name T722
Test name
Test status
Simulation time 14720490 ps
CPU time 1.12 seconds
Started Jul 03 07:14:14 PM PDT 24
Finished Jul 03 07:14:19 PM PDT 24
Peak memory 211464 kb
Host smart-d55001b4-6bcb-4a0a-a2b8-df80d8289c92
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736586723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.2736586723
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.2158927771
Short name T205
Test name
Test status
Simulation time 79359512 ps
CPU time 1.14 seconds
Started Jul 03 07:14:19 PM PDT 24
Finished Jul 03 07:14:22 PM PDT 24
Peak memory 208500 kb
Host smart-4e80c750-0997-4573-ad55-b22a2c50a2f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158927771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.2158927771
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.1531880882
Short name T467
Test name
Test status
Simulation time 820543985 ps
CPU time 9.53 seconds
Started Jul 03 07:14:14 PM PDT 24
Finished Jul 03 07:14:26 PM PDT 24
Peak memory 217892 kb
Host smart-3af6e019-6f07-440e-a025-d7735b3cef22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531880882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.1531880882
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.365263275
Short name T494
Test name
Test status
Simulation time 395856223 ps
CPU time 4.11 seconds
Started Jul 03 07:14:17 PM PDT 24
Finished Jul 03 07:14:23 PM PDT 24
Peak memory 217084 kb
Host smart-c6ae0174-0412-4e22-ab4a-0b84dfee0d33
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365263275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.365263275
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.2032429407
Short name T499
Test name
Test status
Simulation time 75038956 ps
CPU time 2.28 seconds
Started Jul 03 07:14:18 PM PDT 24
Finished Jul 03 07:14:21 PM PDT 24
Peak memory 217772 kb
Host smart-010c0c57-e11f-4a7d-9a98-54bb70baebb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032429407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.2032429407
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.4132543409
Short name T754
Test name
Test status
Simulation time 1447390393 ps
CPU time 14.71 seconds
Started Jul 03 07:14:16 PM PDT 24
Finished Jul 03 07:14:33 PM PDT 24
Peak memory 225568 kb
Host smart-3a00cf3f-3e9d-405a-a894-338a7542bc11
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132543409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.4132543409
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.3224651210
Short name T416
Test name
Test status
Simulation time 503885430 ps
CPU time 19.24 seconds
Started Jul 03 07:14:16 PM PDT 24
Finished Jul 03 07:14:38 PM PDT 24
Peak memory 225508 kb
Host smart-a54d9721-afa5-41d5-be9b-04ccf572bd83
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224651210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.3224651210
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.3276140476
Short name T641
Test name
Test status
Simulation time 318623707 ps
CPU time 7.91 seconds
Started Jul 03 07:14:19 PM PDT 24
Finished Jul 03 07:14:28 PM PDT 24
Peak memory 217696 kb
Host smart-efb57647-479d-41a9-ba82-b4323cbdbff6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276140476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
3276140476
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.658332624
Short name T293
Test name
Test status
Simulation time 300187373 ps
CPU time 7.73 seconds
Started Jul 03 07:14:16 PM PDT 24
Finished Jul 03 07:14:26 PM PDT 24
Peak memory 217852 kb
Host smart-532b06b4-cd6d-49e3-b702-fa682a37e3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658332624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.658332624
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.4264396268
Short name T469
Test name
Test status
Simulation time 147806187 ps
CPU time 2.84 seconds
Started Jul 03 07:14:13 PM PDT 24
Finished Jul 03 07:14:19 PM PDT 24
Peak memory 214244 kb
Host smart-606d776c-8f4a-417b-885e-c90a2d4ef93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264396268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.4264396268
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.1195250302
Short name T446
Test name
Test status
Simulation time 355968425 ps
CPU time 32.06 seconds
Started Jul 03 07:14:16 PM PDT 24
Finished Jul 03 07:14:51 PM PDT 24
Peak memory 250592 kb
Host smart-caa6513c-5791-482b-894f-330d37737eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195250302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.1195250302
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.1651539197
Short name T419
Test name
Test status
Simulation time 157936966 ps
CPU time 6.08 seconds
Started Jul 03 07:14:14 PM PDT 24
Finished Jul 03 07:14:24 PM PDT 24
Peak memory 246656 kb
Host smart-6be76140-4e7d-44d0-ab04-694838f97745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651539197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.1651539197
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.3243781653
Short name T604
Test name
Test status
Simulation time 4098391178 ps
CPU time 132.81 seconds
Started Jul 03 07:14:14 PM PDT 24
Finished Jul 03 07:16:30 PM PDT 24
Peak memory 275784 kb
Host smart-4d673b9e-7cf1-40ea-8981-9dbdc9274130
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243781653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.3243781653
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.2951605615
Short name T166
Test name
Test status
Simulation time 120404180994 ps
CPU time 796.49 seconds
Started Jul 03 07:14:17 PM PDT 24
Finished Jul 03 07:27:36 PM PDT 24
Peak memory 299860 kb
Host smart-fd86b808-051d-4903-b415-e7463a2ded89
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2951605615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.2951605615
Directory /workspace/34.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.3979287494
Short name T844
Test name
Test status
Simulation time 14129113 ps
CPU time 0.99 seconds
Started Jul 03 07:14:13 PM PDT 24
Finished Jul 03 07:14:16 PM PDT 24
Peak memory 211252 kb
Host smart-c5438735-842b-4333-a129-ee8858d8e233
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979287494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.3979287494
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.340652143
Short name T331
Test name
Test status
Simulation time 14879537 ps
CPU time 0.97 seconds
Started Jul 03 07:14:22 PM PDT 24
Finished Jul 03 07:14:25 PM PDT 24
Peak memory 208528 kb
Host smart-5923759a-5f3a-4a3a-bca6-b53dd7b6aac5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340652143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.340652143
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.3095451120
Short name T356
Test name
Test status
Simulation time 3770474961 ps
CPU time 12.08 seconds
Started Jul 03 07:14:20 PM PDT 24
Finished Jul 03 07:14:34 PM PDT 24
Peak memory 217960 kb
Host smart-d19df7f5-2586-4ad4-abd6-0c60cdea4147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095451120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.3095451120
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.3204756535
Short name T845
Test name
Test status
Simulation time 438692101 ps
CPU time 10.72 seconds
Started Jul 03 07:14:22 PM PDT 24
Finished Jul 03 07:14:34 PM PDT 24
Peak memory 216972 kb
Host smart-defa9d12-df88-4fc1-959d-5d20fa080b8d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204756535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.3204756535
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.2592556257
Short name T418
Test name
Test status
Simulation time 71812376 ps
CPU time 3.04 seconds
Started Jul 03 07:14:18 PM PDT 24
Finished Jul 03 07:14:23 PM PDT 24
Peak memory 217760 kb
Host smart-7eec1aeb-2d27-4959-aca1-b2dcc7227583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592556257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.2592556257
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.4053105234
Short name T781
Test name
Test status
Simulation time 414809889 ps
CPU time 17.72 seconds
Started Jul 03 07:14:19 PM PDT 24
Finished Jul 03 07:14:38 PM PDT 24
Peak memory 218416 kb
Host smart-13820f37-e790-4f8f-8931-9c270aa1fd79
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053105234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.4053105234
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.2941698631
Short name T266
Test name
Test status
Simulation time 472809214 ps
CPU time 11.74 seconds
Started Jul 03 07:14:19 PM PDT 24
Finished Jul 03 07:14:32 PM PDT 24
Peak memory 225500 kb
Host smart-4cf5823f-6211-4cd5-9496-d87bf6a02fd4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941698631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.2941698631
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.3750483042
Short name T763
Test name
Test status
Simulation time 193937455 ps
CPU time 8.15 seconds
Started Jul 03 07:14:22 PM PDT 24
Finished Jul 03 07:14:33 PM PDT 24
Peak memory 217748 kb
Host smart-5ce3ea02-4dcd-4ec3-85af-a4996b62889f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750483042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
3750483042
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.3365846700
Short name T36
Test name
Test status
Simulation time 502870280 ps
CPU time 6.84 seconds
Started Jul 03 07:14:20 PM PDT 24
Finished Jul 03 07:14:29 PM PDT 24
Peak memory 225144 kb
Host smart-088c7984-ce05-46d1-b9ed-39570c55c525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365846700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.3365846700
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.3807007204
Short name T867
Test name
Test status
Simulation time 76761386 ps
CPU time 3.06 seconds
Started Jul 03 07:14:14 PM PDT 24
Finished Jul 03 07:14:20 PM PDT 24
Peak memory 217336 kb
Host smart-bc80db3f-1df4-4f7b-b75f-186db60f742d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807007204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.3807007204
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.3231540243
Short name T757
Test name
Test status
Simulation time 1228568652 ps
CPU time 27.63 seconds
Started Jul 03 07:14:17 PM PDT 24
Finished Jul 03 07:14:47 PM PDT 24
Peak memory 250472 kb
Host smart-e87490d9-942b-447a-82d7-556b54919000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231540243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.3231540243
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.711302731
Short name T603
Test name
Test status
Simulation time 93109531 ps
CPU time 10.17 seconds
Started Jul 03 07:14:16 PM PDT 24
Finished Jul 03 07:14:29 PM PDT 24
Peak memory 250500 kb
Host smart-db9ffd76-bf23-4cf8-8010-5aa84672870b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711302731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.711302731
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.1513148926
Short name T363
Test name
Test status
Simulation time 52045581998 ps
CPU time 429.42 seconds
Started Jul 03 07:14:20 PM PDT 24
Finished Jul 03 07:21:32 PM PDT 24
Peak memory 228200 kb
Host smart-6f02c883-17bc-47d6-9bfe-c895802226c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513148926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.1513148926
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.3602726258
Short name T697
Test name
Test status
Simulation time 45743032 ps
CPU time 1.01 seconds
Started Jul 03 07:14:18 PM PDT 24
Finished Jul 03 07:14:21 PM PDT 24
Peak memory 211440 kb
Host smart-ad10b01e-ff21-4bc3-908c-16be18b288e3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602726258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.3602726258
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.3931985698
Short name T95
Test name
Test status
Simulation time 38151277 ps
CPU time 0.87 seconds
Started Jul 03 07:14:21 PM PDT 24
Finished Jul 03 07:14:23 PM PDT 24
Peak memory 208552 kb
Host smart-5bb28c57-6d73-4846-9b45-95b28394c7f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931985698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.3931985698
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.2117051191
Short name T468
Test name
Test status
Simulation time 420282849 ps
CPU time 11.99 seconds
Started Jul 03 07:14:21 PM PDT 24
Finished Jul 03 07:14:35 PM PDT 24
Peak memory 217796 kb
Host smart-7478461d-6edc-47fc-a61b-91bdacbf232d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117051191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.2117051191
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.3042242167
Short name T788
Test name
Test status
Simulation time 152167761 ps
CPU time 2.65 seconds
Started Jul 03 07:14:17 PM PDT 24
Finished Jul 03 07:14:22 PM PDT 24
Peak memory 216684 kb
Host smart-425720f7-d518-45e5-803b-60d7b2181a43
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042242167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.3042242167
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.788298992
Short name T350
Test name
Test status
Simulation time 29947125 ps
CPU time 1.78 seconds
Started Jul 03 07:14:22 PM PDT 24
Finished Jul 03 07:14:26 PM PDT 24
Peak memory 217868 kb
Host smart-f910bee5-c5f9-4527-b730-8547a18e212d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788298992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.788298992
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.1468751003
Short name T743
Test name
Test status
Simulation time 713776106 ps
CPU time 10.5 seconds
Started Jul 03 07:14:22 PM PDT 24
Finished Jul 03 07:14:35 PM PDT 24
Peak memory 225612 kb
Host smart-57e4ebaf-70e0-491f-bd7c-83505b83d223
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468751003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.1468751003
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.2527228620
Short name T549
Test name
Test status
Simulation time 738932567 ps
CPU time 16.91 seconds
Started Jul 03 07:14:23 PM PDT 24
Finished Jul 03 07:14:42 PM PDT 24
Peak memory 217812 kb
Host smart-52758b2f-a3b5-4ffc-b26e-2e84b42a7f4d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527228620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
2527228620
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.106506450
Short name T378
Test name
Test status
Simulation time 1163496359 ps
CPU time 10.45 seconds
Started Jul 03 07:14:20 PM PDT 24
Finished Jul 03 07:14:32 PM PDT 24
Peak memory 225588 kb
Host smart-0387f8ff-4942-48ca-b1e4-9d852bdaa892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106506450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.106506450
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.2172188484
Short name T77
Test name
Test status
Simulation time 57176268 ps
CPU time 2.88 seconds
Started Jul 03 07:14:19 PM PDT 24
Finished Jul 03 07:14:24 PM PDT 24
Peak memory 217172 kb
Host smart-3c2e59b5-b29f-4b0d-8319-8c22d8914702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172188484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.2172188484
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.3205999654
Short name T735
Test name
Test status
Simulation time 586523120 ps
CPU time 17.54 seconds
Started Jul 03 07:14:21 PM PDT 24
Finished Jul 03 07:14:40 PM PDT 24
Peak memory 250536 kb
Host smart-8b421ae1-9785-4a6c-87b0-03614a400395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205999654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.3205999654
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.908865881
Short name T301
Test name
Test status
Simulation time 96926694 ps
CPU time 3.33 seconds
Started Jul 03 07:14:22 PM PDT 24
Finished Jul 03 07:14:27 PM PDT 24
Peak memory 221876 kb
Host smart-049b54e6-0491-4b59-8dbb-d4d044beec08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908865881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.908865881
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.3886317302
Short name T768
Test name
Test status
Simulation time 28554442777 ps
CPU time 173.17 seconds
Started Jul 03 07:14:22 PM PDT 24
Finished Jul 03 07:17:17 PM PDT 24
Peak memory 487056 kb
Host smart-6fdf58cc-1ca1-4098-adc7-aa9c780259e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886317302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.3886317302
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.1473499547
Short name T371
Test name
Test status
Simulation time 15488984 ps
CPU time 0.9 seconds
Started Jul 03 07:14:21 PM PDT 24
Finished Jul 03 07:14:24 PM PDT 24
Peak memory 211352 kb
Host smart-81e3f130-89b9-4672-941d-30fa4eb38ab4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473499547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.1473499547
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.2405774527
Short name T251
Test name
Test status
Simulation time 14323571 ps
CPU time 1.05 seconds
Started Jul 03 07:14:27 PM PDT 24
Finished Jul 03 07:14:31 PM PDT 24
Peak memory 208600 kb
Host smart-0ab3b9f5-c32f-467a-8845-4ec620eca04f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405774527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.2405774527
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.1472532092
Short name T257
Test name
Test status
Simulation time 213999892 ps
CPU time 10.37 seconds
Started Jul 03 07:14:28 PM PDT 24
Finished Jul 03 07:14:41 PM PDT 24
Peak memory 217872 kb
Host smart-23cd3909-c134-4ca5-9919-bbb1a717e45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472532092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.1472532092
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.1851132034
Short name T813
Test name
Test status
Simulation time 391254661 ps
CPU time 10.92 seconds
Started Jul 03 07:14:28 PM PDT 24
Finished Jul 03 07:14:42 PM PDT 24
Peak memory 217284 kb
Host smart-e43fbcee-3e9f-4f88-9a16-a7cb9bd754a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851132034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.1851132034
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.3835910002
Short name T422
Test name
Test status
Simulation time 86826226 ps
CPU time 3.07 seconds
Started Jul 03 07:14:27 PM PDT 24
Finished Jul 03 07:14:32 PM PDT 24
Peak memory 217220 kb
Host smart-37f40202-a7a0-4a55-a162-f620ef432042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835910002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.3835910002
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.1642648235
Short name T410
Test name
Test status
Simulation time 221850198 ps
CPU time 10.42 seconds
Started Jul 03 07:14:27 PM PDT 24
Finished Jul 03 07:14:39 PM PDT 24
Peak memory 217252 kb
Host smart-173e61d0-9bda-4f14-a994-d35b5354cb88
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642648235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.1642648235
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.1489718763
Short name T674
Test name
Test status
Simulation time 1175256141 ps
CPU time 14.56 seconds
Started Jul 03 07:14:22 PM PDT 24
Finished Jul 03 07:14:39 PM PDT 24
Peak memory 225496 kb
Host smart-67c640d7-3a0c-4416-825a-a27dd621c6ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489718763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.1489718763
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.4231998178
Short name T706
Test name
Test status
Simulation time 835712498 ps
CPU time 14.64 seconds
Started Jul 03 07:14:22 PM PDT 24
Finished Jul 03 07:14:39 PM PDT 24
Peak memory 217756 kb
Host smart-26256512-9d1f-4ff4-89f1-ff8d7eec80cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231998178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
4231998178
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.1248296558
Short name T288
Test name
Test status
Simulation time 1773010578 ps
CPU time 15.22 seconds
Started Jul 03 07:14:26 PM PDT 24
Finished Jul 03 07:14:43 PM PDT 24
Peak memory 217596 kb
Host smart-b30ab804-e3c8-4b14-980f-ea25184dae7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248296558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.1248296558
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.1331132880
Short name T843
Test name
Test status
Simulation time 386985213 ps
CPU time 5.74 seconds
Started Jul 03 07:14:22 PM PDT 24
Finished Jul 03 07:14:29 PM PDT 24
Peak memory 217152 kb
Host smart-7075a831-84df-44c4-b7af-d9b881993d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331132880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.1331132880
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.329517056
Short name T572
Test name
Test status
Simulation time 378872353 ps
CPU time 25.55 seconds
Started Jul 03 07:14:19 PM PDT 24
Finished Jul 03 07:14:46 PM PDT 24
Peak memory 250516 kb
Host smart-2cf1a5cb-19fc-4c9e-8763-2822b63b30b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329517056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.329517056
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.201432265
Short name T686
Test name
Test status
Simulation time 83441736 ps
CPU time 6.71 seconds
Started Jul 03 07:14:20 PM PDT 24
Finished Jul 03 07:14:29 PM PDT 24
Peak memory 250532 kb
Host smart-fe9ca564-a699-4361-b13d-82557bd1a85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201432265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.201432265
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.4001177549
Short name T175
Test name
Test status
Simulation time 4316785618 ps
CPU time 139.38 seconds
Started Jul 03 07:14:24 PM PDT 24
Finished Jul 03 07:16:46 PM PDT 24
Peak memory 278232 kb
Host smart-3c179d8e-f905-45fe-9d85-1a7e00c88055
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001177549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.4001177549
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.3133637541
Short name T384
Test name
Test status
Simulation time 20757527953 ps
CPU time 363.87 seconds
Started Jul 03 07:14:28 PM PDT 24
Finished Jul 03 07:20:35 PM PDT 24
Peak memory 283500 kb
Host smart-0b392e29-1f2f-4d01-9024-b208359fd247
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3133637541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.3133637541
Directory /workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.2993977242
Short name T690
Test name
Test status
Simulation time 25538791 ps
CPU time 0.74 seconds
Started Jul 03 07:14:21 PM PDT 24
Finished Jul 03 07:14:24 PM PDT 24
Peak memory 208248 kb
Host smart-8de6b453-4c8a-4eee-bd0e-2f33d8758cee
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993977242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.2993977242
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.2361014181
Short name T324
Test name
Test status
Simulation time 74799857 ps
CPU time 0.97 seconds
Started Jul 03 07:14:33 PM PDT 24
Finished Jul 03 07:14:38 PM PDT 24
Peak memory 208508 kb
Host smart-3e8b6849-335c-40e9-b76e-bbc8cc6d380e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361014181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.2361014181
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.2638666483
Short name T173
Test name
Test status
Simulation time 1438623394 ps
CPU time 17.61 seconds
Started Jul 03 07:14:23 PM PDT 24
Finished Jul 03 07:14:43 PM PDT 24
Peak memory 217780 kb
Host smart-f53e3ace-a6bb-4780-8e14-a1b5ece29bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638666483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.2638666483
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.3934321805
Short name T401
Test name
Test status
Simulation time 106136501 ps
CPU time 2.62 seconds
Started Jul 03 07:14:26 PM PDT 24
Finished Jul 03 07:14:31 PM PDT 24
Peak memory 217164 kb
Host smart-23611c03-801d-46c0-a738-0fd0894acb9f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934321805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.3934321805
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.2515065893
Short name T535
Test name
Test status
Simulation time 39058463 ps
CPU time 1.58 seconds
Started Jul 03 07:14:27 PM PDT 24
Finished Jul 03 07:14:31 PM PDT 24
Peak memory 221412 kb
Host smart-f24562f5-6c11-43c1-afec-4bda7c859fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515065893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.2515065893
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.3403486830
Short name T673
Test name
Test status
Simulation time 2924389763 ps
CPU time 9.75 seconds
Started Jul 03 07:14:26 PM PDT 24
Finished Jul 03 07:14:38 PM PDT 24
Peak memory 218004 kb
Host smart-52694dcd-fc20-4ba5-98ee-99f16f9d8816
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403486830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.3403486830
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.4112719713
Short name T770
Test name
Test status
Simulation time 393978897 ps
CPU time 10.36 seconds
Started Jul 03 07:14:28 PM PDT 24
Finished Jul 03 07:14:41 PM PDT 24
Peak memory 225516 kb
Host smart-c29059b4-b2f9-43f8-b8c4-11d5831770b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112719713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.4112719713
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.2868261947
Short name T688
Test name
Test status
Simulation time 284414030 ps
CPU time 8.59 seconds
Started Jul 03 07:14:27 PM PDT 24
Finished Jul 03 07:14:39 PM PDT 24
Peak memory 217812 kb
Host smart-a3ed8898-cae1-435f-b608-ff1d9dd10732
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868261947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
2868261947
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.1781260753
Short name T510
Test name
Test status
Simulation time 1779270773 ps
CPU time 10.25 seconds
Started Jul 03 07:14:28 PM PDT 24
Finished Jul 03 07:14:41 PM PDT 24
Peak memory 224848 kb
Host smart-66fdff34-02ae-4fcb-971d-1efaf67df1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781260753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.1781260753
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.2099481654
Short name T165
Test name
Test status
Simulation time 67248948 ps
CPU time 1.59 seconds
Started Jul 03 07:14:30 PM PDT 24
Finished Jul 03 07:14:35 PM PDT 24
Peak memory 217204 kb
Host smart-87fd84b7-ab95-4843-a7f5-6bc0b9bfa138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099481654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.2099481654
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.2582673873
Short name T112
Test name
Test status
Simulation time 1319907611 ps
CPU time 32.82 seconds
Started Jul 03 07:14:28 PM PDT 24
Finished Jul 03 07:15:04 PM PDT 24
Peak memory 250504 kb
Host smart-02ab9899-9910-44e9-a25f-2ec191f31d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582673873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.2582673873
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.3656834294
Short name T801
Test name
Test status
Simulation time 85667450 ps
CPU time 8.1 seconds
Started Jul 03 07:14:27 PM PDT 24
Finished Jul 03 07:14:38 PM PDT 24
Peak memory 250496 kb
Host smart-7566eeb9-bfe8-46bc-87d4-5cec4d3c230d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656834294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.3656834294
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.1128385378
Short name T765
Test name
Test status
Simulation time 1158131186 ps
CPU time 57.65 seconds
Started Jul 03 07:14:26 PM PDT 24
Finished Jul 03 07:15:25 PM PDT 24
Peak memory 267640 kb
Host smart-6e9176a0-5423-47ff-a96e-c1b20cc48417
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128385378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.1128385378
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.3866298656
Short name T50
Test name
Test status
Simulation time 15487865 ps
CPU time 0.9 seconds
Started Jul 03 07:14:28 PM PDT 24
Finished Jul 03 07:14:32 PM PDT 24
Peak memory 211420 kb
Host smart-7bc7b298-c0bd-42df-bf99-edddf3666ef6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866298656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.3866298656
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.2701141956
Short name T552
Test name
Test status
Simulation time 247722552 ps
CPU time 0.94 seconds
Started Jul 03 07:14:28 PM PDT 24
Finished Jul 03 07:14:33 PM PDT 24
Peak memory 208508 kb
Host smart-80c3718c-9930-42e4-9427-966558e4b560
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701141956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.2701141956
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.4165623768
Short name T738
Test name
Test status
Simulation time 1696907206 ps
CPU time 10.9 seconds
Started Jul 03 07:14:34 PM PDT 24
Finished Jul 03 07:14:48 PM PDT 24
Peak memory 217924 kb
Host smart-d2a6fcf5-d78b-4919-8ed3-258a1d656954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165623768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.4165623768
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.1993945021
Short name T651
Test name
Test status
Simulation time 174635461 ps
CPU time 5.37 seconds
Started Jul 03 07:14:29 PM PDT 24
Finished Jul 03 07:14:38 PM PDT 24
Peak memory 216728 kb
Host smart-3990da94-5a3b-4f4b-aa5e-384705ea892a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993945021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.1993945021
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.307445797
Short name T280
Test name
Test status
Simulation time 158351803 ps
CPU time 2.36 seconds
Started Jul 03 07:14:33 PM PDT 24
Finished Jul 03 07:14:39 PM PDT 24
Peak memory 217792 kb
Host smart-8fa39e6c-4905-4b07-9910-3991f64e92ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307445797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.307445797
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.1923770809
Short name T593
Test name
Test status
Simulation time 678619283 ps
CPU time 13.44 seconds
Started Jul 03 07:14:29 PM PDT 24
Finished Jul 03 07:14:46 PM PDT 24
Peak memory 217832 kb
Host smart-33e3e8e2-6afc-4cf1-8493-a7a9bc7d109e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923770809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.1923770809
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.2456737824
Short name T46
Test name
Test status
Simulation time 1148409868 ps
CPU time 10.04 seconds
Started Jul 03 07:14:33 PM PDT 24
Finished Jul 03 07:14:47 PM PDT 24
Peak memory 225356 kb
Host smart-45b076bb-680d-40b2-8459-4350522307b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456737824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.2456737824
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.3237901671
Short name T609
Test name
Test status
Simulation time 636356108 ps
CPU time 7.74 seconds
Started Jul 03 07:14:32 PM PDT 24
Finished Jul 03 07:14:43 PM PDT 24
Peak memory 217712 kb
Host smart-ad614e9d-50ad-4f82-95cd-87dccca136ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237901671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
3237901671
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.2179059828
Short name T732
Test name
Test status
Simulation time 193842904 ps
CPU time 8.86 seconds
Started Jul 03 07:14:32 PM PDT 24
Finished Jul 03 07:14:44 PM PDT 24
Peak memory 224688 kb
Host smart-7592ecf1-7948-42e8-a3bc-efbfbaac8c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179059828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.2179059828
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.2746451646
Short name T283
Test name
Test status
Simulation time 61133079 ps
CPU time 2.38 seconds
Started Jul 03 07:14:32 PM PDT 24
Finished Jul 03 07:14:38 PM PDT 24
Peak memory 221984 kb
Host smart-07b125bb-32d4-482d-9534-4873d8e9f38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746451646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.2746451646
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.3216302613
Short name T624
Test name
Test status
Simulation time 1846714082 ps
CPU time 38.3 seconds
Started Jul 03 07:14:32 PM PDT 24
Finished Jul 03 07:15:14 PM PDT 24
Peak memory 250516 kb
Host smart-3eaeb754-cc32-4416-ad7e-81d429670607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216302613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.3216302613
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.96553642
Short name T849
Test name
Test status
Simulation time 160798902 ps
CPU time 8.34 seconds
Started Jul 03 07:14:28 PM PDT 24
Finished Jul 03 07:14:39 PM PDT 24
Peak memory 250488 kb
Host smart-236742f8-af0a-4c06-8e4e-80bbac5a5f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96553642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.96553642
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.1538104545
Short name T516
Test name
Test status
Simulation time 1912273987 ps
CPU time 17.23 seconds
Started Jul 03 07:14:33 PM PDT 24
Finished Jul 03 07:14:54 PM PDT 24
Peak memory 218524 kb
Host smart-4b8654c7-7ae2-4e2d-a498-57702defe4d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538104545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.1538104545
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.3061659503
Short name T170
Test name
Test status
Simulation time 15284802 ps
CPU time 1.01 seconds
Started Jul 03 07:14:34 PM PDT 24
Finished Jul 03 07:14:38 PM PDT 24
Peak memory 211468 kb
Host smart-90ba686b-c6ad-4e53-832f-66787d5dd7d2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061659503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.3061659503
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.2672603770
Short name T744
Test name
Test status
Simulation time 107523798 ps
CPU time 1.32 seconds
Started Jul 03 07:11:03 PM PDT 24
Finished Jul 03 07:11:40 PM PDT 24
Peak memory 208536 kb
Host smart-0456d00e-9d94-4a63-8903-69700fb67eef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672603770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.2672603770
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.3707556470
Short name T66
Test name
Test status
Simulation time 32013439 ps
CPU time 0.84 seconds
Started Jul 03 07:10:58 PM PDT 24
Finished Jul 03 07:11:33 PM PDT 24
Peak memory 208680 kb
Host smart-175ebd0d-1ada-4ace-a7a7-4b3e0d9276fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707556470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.3707556470
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.1212285466
Short name T296
Test name
Test status
Simulation time 524514752 ps
CPU time 12.09 seconds
Started Jul 03 07:10:52 PM PDT 24
Finished Jul 03 07:11:36 PM PDT 24
Peak memory 217764 kb
Host smart-5f34d4c0-33ec-4206-bd11-484df025592d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212285466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.1212285466
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.3782729921
Short name T9
Test name
Test status
Simulation time 1128066402 ps
CPU time 3.7 seconds
Started Jul 03 07:10:58 PM PDT 24
Finished Jul 03 07:11:37 PM PDT 24
Peak memory 217472 kb
Host smart-1f2d4899-0d57-48cb-ad3b-44fac79dd714
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782729921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.3782729921
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.438134572
Short name T441
Test name
Test status
Simulation time 7165475301 ps
CPU time 26.88 seconds
Started Jul 03 07:10:57 PM PDT 24
Finished Jul 03 07:11:58 PM PDT 24
Peak memory 217776 kb
Host smart-ae2d3edc-d37d-4ca4-a67a-fee2f52f25aa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438134572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_err
ors.438134572
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.243901071
Short name T397
Test name
Test status
Simulation time 1554291181 ps
CPU time 5.2 seconds
Started Jul 03 07:10:56 PM PDT 24
Finished Jul 03 07:11:35 PM PDT 24
Peak memory 217204 kb
Host smart-1c5d40e3-c4ef-44a8-8658-405b0b74c0ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243901071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.243901071
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.51805479
Short name T692
Test name
Test status
Simulation time 89261480 ps
CPU time 3.27 seconds
Started Jul 03 07:11:03 PM PDT 24
Finished Jul 03 07:11:42 PM PDT 24
Peak memory 217748 kb
Host smart-d36ddca9-6310-4038-9704-9d8791f05f99
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51805479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p
rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_p
rog_failure.51805479
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.201860021
Short name T231
Test name
Test status
Simulation time 4887703121 ps
CPU time 18.35 seconds
Started Jul 03 07:10:58 PM PDT 24
Finished Jul 03 07:11:51 PM PDT 24
Peak memory 217172 kb
Host smart-96b976f5-e08e-4413-88da-cdfc115744ad
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201860021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_j
tag_regwen_during_op.201860021
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.2649206428
Short name T83
Test name
Test status
Simulation time 65095878 ps
CPU time 2.49 seconds
Started Jul 03 07:10:57 PM PDT 24
Finished Jul 03 07:11:33 PM PDT 24
Peak memory 217164 kb
Host smart-36006f61-9ae8-4d90-bfec-d4f2e505f96f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649206428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
2649206428
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.45451490
Short name T395
Test name
Test status
Simulation time 2135706365 ps
CPU time 55.34 seconds
Started Jul 03 07:10:57 PM PDT 24
Finished Jul 03 07:12:26 PM PDT 24
Peak memory 276044 kb
Host smart-d4bb1e18-6b04-4f51-b3a5-93a447ecda0a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45451490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_
state_failure.45451490
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.3609768179
Short name T601
Test name
Test status
Simulation time 2728931348 ps
CPU time 18.1 seconds
Started Jul 03 07:10:58 PM PDT 24
Finished Jul 03 07:11:51 PM PDT 24
Peak memory 250060 kb
Host smart-e40a4ae0-0671-4ea7-96ef-693a2f58671d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609768179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.3609768179
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.934532683
Short name T247
Test name
Test status
Simulation time 230601860 ps
CPU time 3.07 seconds
Started Jul 03 07:10:53 PM PDT 24
Finished Jul 03 07:11:29 PM PDT 24
Peak memory 217764 kb
Host smart-e8da886d-4fa5-4a14-a756-dcdefe13ac10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934532683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.934532683
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.3305558954
Short name T82
Test name
Test status
Simulation time 396922560 ps
CPU time 6.46 seconds
Started Jul 03 07:10:56 PM PDT 24
Finished Jul 03 07:11:37 PM PDT 24
Peak memory 213996 kb
Host smart-e72dcf5d-45e7-4dcb-86fb-addb01358fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305558954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.3305558954
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.3055719757
Short name T90
Test name
Test status
Simulation time 150105238 ps
CPU time 24.62 seconds
Started Jul 03 07:10:57 PM PDT 24
Finished Jul 03 07:11:55 PM PDT 24
Peak memory 281844 kb
Host smart-c282930b-383c-47c1-8f87-b6035914a001
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055719757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.3055719757
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.1972415493
Short name T825
Test name
Test status
Simulation time 402467292 ps
CPU time 11.38 seconds
Started Jul 03 07:10:55 PM PDT 24
Finished Jul 03 07:11:40 PM PDT 24
Peak memory 225464 kb
Host smart-6fcfd7ab-2fed-49da-aff6-1b2765674e45
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972415493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.1972415493
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.1755242242
Short name T524
Test name
Test status
Simulation time 1389924228 ps
CPU time 9.71 seconds
Started Jul 03 07:10:58 PM PDT 24
Finished Jul 03 07:11:41 PM PDT 24
Peak memory 225476 kb
Host smart-0e76630f-8773-4bf6-a388-986d38018c83
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755242242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.1
755242242
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.1742952847
Short name T383
Test name
Test status
Simulation time 284714230 ps
CPU time 10.27 seconds
Started Jul 03 07:11:04 PM PDT 24
Finished Jul 03 07:11:49 PM PDT 24
Peak memory 225676 kb
Host smart-61b6c0ce-d979-4877-9ceb-588423e12bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742952847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.1742952847
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.115781511
Short name T460
Test name
Test status
Simulation time 23500936 ps
CPU time 1.7 seconds
Started Jul 03 07:10:52 PM PDT 24
Finished Jul 03 07:11:28 PM PDT 24
Peak memory 217216 kb
Host smart-fe4a37ab-1151-4f79-8be6-01433c78f752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115781511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.115781511
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.1120651299
Short name T87
Test name
Test status
Simulation time 646862052 ps
CPU time 19.13 seconds
Started Jul 03 07:10:53 PM PDT 24
Finished Jul 03 07:11:45 PM PDT 24
Peak memory 250508 kb
Host smart-5fc301ed-e9a2-48ff-9349-934a0af0f233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120651299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.1120651299
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.3895517964
Short name T290
Test name
Test status
Simulation time 297697712 ps
CPU time 7.75 seconds
Started Jul 03 07:10:51 PM PDT 24
Finished Jul 03 07:11:31 PM PDT 24
Peak memory 250524 kb
Host smart-0ad31ae4-f85f-44e2-933a-c58a90febdc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895517964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.3895517964
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.1811705662
Short name T473
Test name
Test status
Simulation time 4633145877 ps
CPU time 38.3 seconds
Started Jul 03 07:11:03 PM PDT 24
Finished Jul 03 07:12:17 PM PDT 24
Peak memory 267012 kb
Host smart-9ad436d2-35ea-4a27-b49f-8c525cc2964c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811705662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.1811705662
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.2840795625
Short name T148
Test name
Test status
Simulation time 16821974957 ps
CPU time 65.29 seconds
Started Jul 03 07:10:56 PM PDT 24
Finished Jul 03 07:12:34 PM PDT 24
Peak memory 257404 kb
Host smart-f93ac2cf-3a2c-4525-9b10-ba95a8f31dbf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2840795625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.2840795625
Directory /workspace/4.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.225103961
Short name T525
Test name
Test status
Simulation time 107096772 ps
CPU time 0.89 seconds
Started Jul 03 07:10:52 PM PDT 24
Finished Jul 03 07:11:25 PM PDT 24
Peak memory 211488 kb
Host smart-649504e3-90c0-4b75-9136-6fe7a9be1907
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225103961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctr
l_volatile_unlock_smoke.225103961
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.3179147076
Short name T218
Test name
Test status
Simulation time 12152659 ps
CPU time 0.85 seconds
Started Jul 03 07:14:32 PM PDT 24
Finished Jul 03 07:14:37 PM PDT 24
Peak memory 208404 kb
Host smart-a4cd1e49-a776-4db5-9e1e-3391536363f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179147076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.3179147076
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.324455764
Short name T476
Test name
Test status
Simulation time 1381762139 ps
CPU time 10.46 seconds
Started Jul 03 07:14:35 PM PDT 24
Finished Jul 03 07:14:49 PM PDT 24
Peak memory 217808 kb
Host smart-b4796806-a2a4-47ea-aa04-e102d3b0cf68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324455764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.324455764
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.3501674101
Short name T425
Test name
Test status
Simulation time 408319769 ps
CPU time 5.62 seconds
Started Jul 03 07:14:30 PM PDT 24
Finished Jul 03 07:14:39 PM PDT 24
Peak memory 216876 kb
Host smart-91d49dd5-ff42-4156-bec2-7cad4358a403
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501674101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.3501674101
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.822885665
Short name T665
Test name
Test status
Simulation time 178288675 ps
CPU time 1.75 seconds
Started Jul 03 07:14:30 PM PDT 24
Finished Jul 03 07:14:35 PM PDT 24
Peak memory 217780 kb
Host smart-b78230f2-f277-4929-aebd-c86a15bb268e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822885665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.822885665
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.869405278
Short name T259
Test name
Test status
Simulation time 861446783 ps
CPU time 13.5 seconds
Started Jul 03 07:14:32 PM PDT 24
Finished Jul 03 07:14:48 PM PDT 24
Peak memory 217696 kb
Host smart-685a4363-df97-4003-a1a7-19fcc2907734
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869405278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.869405278
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.2338513209
Short name T791
Test name
Test status
Simulation time 821748812 ps
CPU time 7.6 seconds
Started Jul 03 07:14:33 PM PDT 24
Finished Jul 03 07:14:45 PM PDT 24
Peak memory 225532 kb
Host smart-6053f1e8-23ac-471b-abb6-f6e204d74c0a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338513209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.2338513209
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.1024622582
Short name T377
Test name
Test status
Simulation time 1506808181 ps
CPU time 7.87 seconds
Started Jul 03 07:14:33 PM PDT 24
Finished Jul 03 07:14:45 PM PDT 24
Peak memory 217716 kb
Host smart-8bd5f7e2-5f65-4cba-ace0-c46d39c1dd06
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024622582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
1024622582
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.1048271058
Short name T337
Test name
Test status
Simulation time 357819337 ps
CPU time 11.98 seconds
Started Jul 03 07:14:35 PM PDT 24
Finished Jul 03 07:14:51 PM PDT 24
Peak memory 225560 kb
Host smart-147b8a7f-3666-473d-a2bd-eb9ac160d45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048271058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.1048271058
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.90017767
Short name T837
Test name
Test status
Simulation time 75863595 ps
CPU time 1.7 seconds
Started Jul 03 07:14:33 PM PDT 24
Finished Jul 03 07:14:38 PM PDT 24
Peak memory 213412 kb
Host smart-75fb118c-7c52-48ab-a6f8-c75ba8e7494f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90017767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.90017767
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.3100098559
Short name T820
Test name
Test status
Simulation time 900069234 ps
CPU time 25.64 seconds
Started Jul 03 07:14:33 PM PDT 24
Finished Jul 03 07:15:03 PM PDT 24
Peak memory 250540 kb
Host smart-572ec8ca-dee3-4400-9c04-dba4e374ac4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100098559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.3100098559
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.2662689239
Short name T517
Test name
Test status
Simulation time 79977754 ps
CPU time 4.37 seconds
Started Jul 03 07:14:32 PM PDT 24
Finished Jul 03 07:14:40 PM PDT 24
Peak memory 222336 kb
Host smart-076b10d9-0217-4e33-9244-8f50576c3745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662689239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.2662689239
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.1400767859
Short name T496
Test name
Test status
Simulation time 5386770056 ps
CPU time 38.03 seconds
Started Jul 03 07:14:35 PM PDT 24
Finished Jul 03 07:15:16 PM PDT 24
Peak memory 266992 kb
Host smart-c3cccc1a-14cc-4dea-b0e0-9a33b104b64d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400767859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.1400767859
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.171538577
Short name T155
Test name
Test status
Simulation time 57792855543 ps
CPU time 391.97 seconds
Started Jul 03 07:14:31 PM PDT 24
Finished Jul 03 07:21:07 PM PDT 24
Peak memory 298008 kb
Host smart-ebeb8916-9114-4cb6-b413-776165c6b4e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=171538577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all_with_rand_reset.171538577
Directory /workspace/40.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.3460893816
Short name T760
Test name
Test status
Simulation time 12333245 ps
CPU time 0.94 seconds
Started Jul 03 07:14:28 PM PDT 24
Finished Jul 03 07:14:32 PM PDT 24
Peak memory 211432 kb
Host smart-fbfd651d-457e-4157-bafe-a7802499b1a6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460893816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.3460893816
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.651453373
Short name T72
Test name
Test status
Simulation time 19622439 ps
CPU time 1.15 seconds
Started Jul 03 07:14:35 PM PDT 24
Finished Jul 03 07:14:39 PM PDT 24
Peak memory 208624 kb
Host smart-d05b72e8-a4ef-4532-ad04-1d53754cd826
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651453373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.651453373
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.2317884409
Short name T216
Test name
Test status
Simulation time 220003074 ps
CPU time 9.28 seconds
Started Jul 03 07:14:35 PM PDT 24
Finished Jul 03 07:14:47 PM PDT 24
Peak memory 217804 kb
Host smart-82b69dce-cce1-4dd4-8b3a-a247213ce395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317884409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.2317884409
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.3373536713
Short name T797
Test name
Test status
Simulation time 702227476 ps
CPU time 5.8 seconds
Started Jul 03 07:14:31 PM PDT 24
Finished Jul 03 07:14:40 PM PDT 24
Peak memory 217264 kb
Host smart-7f5382ec-9beb-4c78-ad30-b44a1e883ba4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373536713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.3373536713
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.4200401211
Short name T617
Test name
Test status
Simulation time 18165894 ps
CPU time 1.42 seconds
Started Jul 03 07:14:38 PM PDT 24
Finished Jul 03 07:14:41 PM PDT 24
Peak memory 217788 kb
Host smart-7cbe3b86-e435-4459-897f-193688151917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200401211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.4200401211
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.2241620433
Short name T622
Test name
Test status
Simulation time 237204140 ps
CPU time 11.84 seconds
Started Jul 03 07:14:30 PM PDT 24
Finished Jul 03 07:14:46 PM PDT 24
Peak memory 218444 kb
Host smart-69bbc52c-d397-4fa9-9427-a70386b3a838
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241620433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.2241620433
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.2166603866
Short name T862
Test name
Test status
Simulation time 614878943 ps
CPU time 13.39 seconds
Started Jul 03 07:14:35 PM PDT 24
Finished Jul 03 07:14:52 PM PDT 24
Peak memory 225536 kb
Host smart-e4fe6642-3553-44fc-9877-4042e014fce8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166603866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.2166603866
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.3570148994
Short name T779
Test name
Test status
Simulation time 370413844 ps
CPU time 9.74 seconds
Started Jul 03 07:14:38 PM PDT 24
Finished Jul 03 07:14:50 PM PDT 24
Peak memory 225532 kb
Host smart-cd765a5b-bd4d-4fab-8c65-6636ec9ae1e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570148994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
3570148994
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.1203407337
Short name T365
Test name
Test status
Simulation time 461907531 ps
CPU time 9.95 seconds
Started Jul 03 07:14:37 PM PDT 24
Finished Jul 03 07:14:49 PM PDT 24
Peak memory 225032 kb
Host smart-4e106366-3ef7-41a1-98fd-6e374e21fac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203407337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.1203407337
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.2589704551
Short name T432
Test name
Test status
Simulation time 108067208 ps
CPU time 1.18 seconds
Started Jul 03 07:14:36 PM PDT 24
Finished Jul 03 07:14:40 PM PDT 24
Peak memory 217288 kb
Host smart-87bf79a4-550a-4cf9-84f0-9ced401f3746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589704551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.2589704551
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.3803784780
Short name T613
Test name
Test status
Simulation time 161348032 ps
CPU time 24.79 seconds
Started Jul 03 07:14:37 PM PDT 24
Finished Jul 03 07:15:04 PM PDT 24
Peak memory 250524 kb
Host smart-2401c7a0-57d8-4611-88ea-d46acc1fa078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803784780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.3803784780
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.3758537862
Short name T785
Test name
Test status
Simulation time 108177784 ps
CPU time 6.79 seconds
Started Jul 03 07:14:38 PM PDT 24
Finished Jul 03 07:14:47 PM PDT 24
Peak memory 250536 kb
Host smart-9f4d9562-0998-4366-824f-b8f2dc8ae6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758537862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.3758537862
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.2033352400
Short name T176
Test name
Test status
Simulation time 7490871784 ps
CPU time 185.58 seconds
Started Jul 03 07:14:36 PM PDT 24
Finished Jul 03 07:17:44 PM PDT 24
Peak memory 267000 kb
Host smart-6508719e-3222-4e06-bf2b-7c1c2218c58c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033352400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.2033352400
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.2596065378
Short name T85
Test name
Test status
Simulation time 25050791333 ps
CPU time 573.69 seconds
Started Jul 03 07:14:38 PM PDT 24
Finished Jul 03 07:24:14 PM PDT 24
Peak memory 283500 kb
Host smart-97c90c8b-1cc6-48fa-9d33-3805080f43c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2596065378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.2596065378
Directory /workspace/41.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.2981689658
Short name T314
Test name
Test status
Simulation time 21707967 ps
CPU time 1.04 seconds
Started Jul 03 07:14:37 PM PDT 24
Finished Jul 03 07:14:40 PM PDT 24
Peak memory 211500 kb
Host smart-61064382-9462-499e-acc1-8d676c68a1ad
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981689658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.2981689658
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.2278571786
Short name T527
Test name
Test status
Simulation time 17473736 ps
CPU time 0.91 seconds
Started Jul 03 07:14:41 PM PDT 24
Finished Jul 03 07:14:44 PM PDT 24
Peak memory 208500 kb
Host smart-702f26d4-dd97-49c0-83c8-81c6fa69332e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278571786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.2278571786
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.1903336860
Short name T863
Test name
Test status
Simulation time 781442882 ps
CPU time 16.33 seconds
Started Jul 03 07:14:33 PM PDT 24
Finished Jul 03 07:14:53 PM PDT 24
Peak memory 217804 kb
Host smart-ecc756ba-006b-4632-a12a-aafa785c783a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903336860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.1903336860
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.3299253351
Short name T699
Test name
Test status
Simulation time 1257187369 ps
CPU time 4.3 seconds
Started Jul 03 07:14:41 PM PDT 24
Finished Jul 03 07:14:47 PM PDT 24
Peak memory 217156 kb
Host smart-cc7bd206-56d1-4f75-b0d7-928a904f8526
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299253351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.3299253351
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.1830481551
Short name T507
Test name
Test status
Simulation time 161278536 ps
CPU time 3.59 seconds
Started Jul 03 07:14:37 PM PDT 24
Finished Jul 03 07:14:43 PM PDT 24
Peak memory 221944 kb
Host smart-1386707d-68e9-4209-a21b-09f4223a2f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830481551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.1830481551
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.868458147
Short name T630
Test name
Test status
Simulation time 1112063806 ps
CPU time 12.59 seconds
Started Jul 03 07:14:37 PM PDT 24
Finished Jul 03 07:14:52 PM PDT 24
Peak memory 225596 kb
Host smart-e5057a50-8640-46c2-bef4-2d65e76a7f87
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868458147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.868458147
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.1431665130
Short name T561
Test name
Test status
Simulation time 2949899690 ps
CPU time 13.77 seconds
Started Jul 03 07:14:42 PM PDT 24
Finished Jul 03 07:14:58 PM PDT 24
Peak memory 225544 kb
Host smart-555695ed-b1f7-4f27-8325-22db4b7d957b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431665130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.1431665130
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.1871034212
Short name T289
Test name
Test status
Simulation time 1003636385 ps
CPU time 12.63 seconds
Started Jul 03 07:14:43 PM PDT 24
Finished Jul 03 07:14:57 PM PDT 24
Peak memory 225536 kb
Host smart-b5662a00-a2f9-4591-a883-acf3005541cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871034212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
1871034212
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.3385355859
Short name T407
Test name
Test status
Simulation time 1168076119 ps
CPU time 11.3 seconds
Started Jul 03 07:14:43 PM PDT 24
Finished Jul 03 07:14:56 PM PDT 24
Peak memory 225592 kb
Host smart-0f2f2ea4-77a2-41a3-b778-847e6aa21aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385355859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.3385355859
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.2111638608
Short name T509
Test name
Test status
Simulation time 96455491 ps
CPU time 3.28 seconds
Started Jul 03 07:14:37 PM PDT 24
Finished Jul 03 07:14:43 PM PDT 24
Peak memory 214268 kb
Host smart-2759adf7-e091-4ec4-8f1d-7aa7d925d4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111638608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.2111638608
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.1992398133
Short name T842
Test name
Test status
Simulation time 319112280 ps
CPU time 19.1 seconds
Started Jul 03 07:14:35 PM PDT 24
Finished Jul 03 07:14:58 PM PDT 24
Peak memory 250544 kb
Host smart-547ad9ba-1128-472d-80ae-e064134127b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992398133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.1992398133
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.2730459359
Short name T210
Test name
Test status
Simulation time 100326811 ps
CPU time 11.56 seconds
Started Jul 03 07:14:35 PM PDT 24
Finished Jul 03 07:14:50 PM PDT 24
Peak memory 250508 kb
Host smart-00d5bc76-38d0-438d-833d-f4cd90da6175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730459359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.2730459359
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.2237625350
Short name T575
Test name
Test status
Simulation time 15401247673 ps
CPU time 102.33 seconds
Started Jul 03 07:14:41 PM PDT 24
Finished Jul 03 07:16:25 PM PDT 24
Peak memory 271948 kb
Host smart-815f88aa-4112-42c0-a0a5-3658199f8263
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237625350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.2237625350
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.1092163382
Short name T461
Test name
Test status
Simulation time 14581692 ps
CPU time 0.99 seconds
Started Jul 03 07:14:36 PM PDT 24
Finished Jul 03 07:14:40 PM PDT 24
Peak memory 208532 kb
Host smart-7fb5d558-19f3-46a1-8e54-8dd516068890
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092163382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.1092163382
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.2413855749
Short name T758
Test name
Test status
Simulation time 60989597 ps
CPU time 0.84 seconds
Started Jul 03 07:14:50 PM PDT 24
Finished Jul 03 07:14:52 PM PDT 24
Peak memory 208480 kb
Host smart-ecb6bb19-bd0f-4675-9289-f927f12022b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413855749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.2413855749
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.1734421206
Short name T261
Test name
Test status
Simulation time 442285089 ps
CPU time 8.34 seconds
Started Jul 03 07:14:43 PM PDT 24
Finished Jul 03 07:14:53 PM PDT 24
Peak memory 217800 kb
Host smart-e84ec74d-813f-45f8-9f99-0455db698623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734421206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.1734421206
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.2004038844
Short name T281
Test name
Test status
Simulation time 1072378614 ps
CPU time 4.4 seconds
Started Jul 03 07:14:44 PM PDT 24
Finished Jul 03 07:14:50 PM PDT 24
Peak memory 216728 kb
Host smart-46f3e78e-421e-4f98-9fdd-46a8955ff634
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004038844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.2004038844
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.2554803915
Short name T790
Test name
Test status
Simulation time 238515347 ps
CPU time 3.26 seconds
Started Jul 03 07:14:43 PM PDT 24
Finished Jul 03 07:14:48 PM PDT 24
Peak memory 222224 kb
Host smart-72fff9ef-9f62-4f04-ad5c-b44ef89953a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554803915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.2554803915
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.3188403428
Short name T616
Test name
Test status
Simulation time 1411815588 ps
CPU time 18.7 seconds
Started Jul 03 07:14:43 PM PDT 24
Finished Jul 03 07:15:04 PM PDT 24
Peak memory 219504 kb
Host smart-0314675d-0e48-4df8-8666-01ccd1f8c4b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188403428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.3188403428
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.3587507126
Short name T694
Test name
Test status
Simulation time 2499111051 ps
CPU time 15.41 seconds
Started Jul 03 07:14:42 PM PDT 24
Finished Jul 03 07:14:59 PM PDT 24
Peak memory 225596 kb
Host smart-9cfe28ab-d9a9-4ffb-a573-070530d18382
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587507126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.3587507126
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.48289055
Short name T455
Test name
Test status
Simulation time 592434456 ps
CPU time 9.05 seconds
Started Jul 03 07:14:43 PM PDT 24
Finished Jul 03 07:14:54 PM PDT 24
Peak memory 217736 kb
Host smart-a44dc2c9-1fbb-4f5e-9181-3979c08c1a5e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48289055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.48289055
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.2508972779
Short name T297
Test name
Test status
Simulation time 2009649322 ps
CPU time 17.31 seconds
Started Jul 03 07:14:42 PM PDT 24
Finished Jul 03 07:15:01 PM PDT 24
Peak memory 217860 kb
Host smart-84cace56-4d24-48b2-bbed-f5c2bd5e01d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508972779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.2508972779
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.429382708
Short name T279
Test name
Test status
Simulation time 64703977 ps
CPU time 2.17 seconds
Started Jul 03 07:14:42 PM PDT 24
Finished Jul 03 07:14:45 PM PDT 24
Peak memory 217216 kb
Host smart-871e8adc-7c2a-409b-903e-f577a758b35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429382708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.429382708
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.4287249342
Short name T292
Test name
Test status
Simulation time 326259818 ps
CPU time 33.2 seconds
Started Jul 03 07:14:41 PM PDT 24
Finished Jul 03 07:15:16 PM PDT 24
Peak memory 250516 kb
Host smart-d6e23701-e90a-4908-a3f6-c27713bc0eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287249342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.4287249342
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.3264861757
Short name T589
Test name
Test status
Simulation time 132493770 ps
CPU time 7.6 seconds
Started Jul 03 07:14:44 PM PDT 24
Finished Jul 03 07:14:54 PM PDT 24
Peak memory 250512 kb
Host smart-c172dede-68b1-410b-bf7d-990a2ba08f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264861757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.3264861757
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.2272535295
Short name T480
Test name
Test status
Simulation time 6406850196 ps
CPU time 60.86 seconds
Started Jul 03 07:14:44 PM PDT 24
Finished Jul 03 07:15:47 PM PDT 24
Peak memory 250680 kb
Host smart-d036dc20-bbc0-4454-ae2e-00018ac9ded7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272535295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.2272535295
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.382412710
Short name T404
Test name
Test status
Simulation time 47314957 ps
CPU time 0.89 seconds
Started Jul 03 07:14:42 PM PDT 24
Finished Jul 03 07:14:44 PM PDT 24
Peak memory 211448 kb
Host smart-53900c10-ef73-44c2-8b1d-c18e28319d72
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382412710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ct
rl_volatile_unlock_smoke.382412710
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.3274082864
Short name T858
Test name
Test status
Simulation time 17953545 ps
CPU time 1.06 seconds
Started Jul 03 07:14:49 PM PDT 24
Finished Jul 03 07:14:52 PM PDT 24
Peak memory 208484 kb
Host smart-8a3c6789-0ed3-4c5b-b53e-547a6936921b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274082864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.3274082864
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.3040350145
Short name T804
Test name
Test status
Simulation time 1702875910 ps
CPU time 10.61 seconds
Started Jul 03 07:14:44 PM PDT 24
Finished Jul 03 07:14:57 PM PDT 24
Peak memory 225572 kb
Host smart-e61b3b8f-5e9a-40c8-aef7-17adcb8bd565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040350145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.3040350145
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.502490438
Short name T287
Test name
Test status
Simulation time 888788200 ps
CPU time 6.21 seconds
Started Jul 03 07:14:46 PM PDT 24
Finished Jul 03 07:14:54 PM PDT 24
Peak memory 216996 kb
Host smart-7cd62257-98b1-48df-8790-10d126716bc9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502490438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.502490438
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.3162012680
Short name T544
Test name
Test status
Simulation time 248394033 ps
CPU time 2.6 seconds
Started Jul 03 07:14:43 PM PDT 24
Finished Jul 03 07:14:48 PM PDT 24
Peak memory 217780 kb
Host smart-030b626c-2b2d-49cb-8c4b-f8667bb3ea69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162012680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.3162012680
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.3957364736
Short name T344
Test name
Test status
Simulation time 300250996 ps
CPU time 14.27 seconds
Started Jul 03 07:14:46 PM PDT 24
Finished Jul 03 07:15:03 PM PDT 24
Peak memory 225588 kb
Host smart-205006ea-c230-4b3e-8d05-3f43e6b28271
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957364736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.3957364736
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.3433041588
Short name T479
Test name
Test status
Simulation time 541825387 ps
CPU time 12.58 seconds
Started Jul 03 07:14:45 PM PDT 24
Finished Jul 03 07:15:00 PM PDT 24
Peak memory 225516 kb
Host smart-df5903c5-8e90-4317-969c-a1414d184685
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433041588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.3433041588
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.3243136568
Short name T211
Test name
Test status
Simulation time 1141382986 ps
CPU time 10.75 seconds
Started Jul 03 07:14:45 PM PDT 24
Finished Jul 03 07:14:58 PM PDT 24
Peak memory 217724 kb
Host smart-aba3e326-1c13-4cd0-9295-c71e8d8c71bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243136568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
3243136568
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.1479978600
Short name T389
Test name
Test status
Simulation time 174788001 ps
CPU time 7.43 seconds
Started Jul 03 07:14:49 PM PDT 24
Finished Jul 03 07:14:59 PM PDT 24
Peak memory 224044 kb
Host smart-747301a3-8c00-49e0-8435-f6a2334b0276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479978600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.1479978600
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.758537540
Short name T724
Test name
Test status
Simulation time 183955924 ps
CPU time 5.14 seconds
Started Jul 03 07:14:45 PM PDT 24
Finished Jul 03 07:14:53 PM PDT 24
Peak memory 217192 kb
Host smart-114f0f02-1cdf-4466-87d3-145a17c0823d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758537540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.758537540
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.3940638813
Short name T569
Test name
Test status
Simulation time 414454210 ps
CPU time 23.18 seconds
Started Jul 03 07:14:41 PM PDT 24
Finished Jul 03 07:15:05 PM PDT 24
Peak memory 250492 kb
Host smart-6b94eb07-57ee-4cee-a425-91e967a4774a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940638813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.3940638813
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.2717936083
Short name T521
Test name
Test status
Simulation time 182027621 ps
CPU time 3.89 seconds
Started Jul 03 07:14:50 PM PDT 24
Finished Jul 03 07:14:56 PM PDT 24
Peak memory 221988 kb
Host smart-cd691ea8-0532-49ee-b538-7b1dcf43478e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717936083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.2717936083
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.4125787116
Short name T859
Test name
Test status
Simulation time 8102843630 ps
CPU time 301.34 seconds
Started Jul 03 07:14:47 PM PDT 24
Finished Jul 03 07:19:50 PM PDT 24
Peak memory 258796 kb
Host smart-ade7480e-e797-4d21-8ff4-72a36b458b8b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125787116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.4125787116
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.2408610390
Short name T541
Test name
Test status
Simulation time 171827689 ps
CPU time 0.92 seconds
Started Jul 03 07:14:40 PM PDT 24
Finished Jul 03 07:14:42 PM PDT 24
Peak memory 211316 kb
Host smart-8f06757d-81bf-4d20-8321-bac0a814d209
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408610390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.2408610390
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.468845785
Short name T504
Test name
Test status
Simulation time 53295762 ps
CPU time 0.98 seconds
Started Jul 03 07:14:48 PM PDT 24
Finished Jul 03 07:14:50 PM PDT 24
Peak memory 208536 kb
Host smart-75dde937-7787-4647-923c-ba6eb7f5bc0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468845785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.468845785
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.1088250943
Short name T586
Test name
Test status
Simulation time 936823158 ps
CPU time 12.48 seconds
Started Jul 03 07:14:49 PM PDT 24
Finished Jul 03 07:15:03 PM PDT 24
Peak memory 225532 kb
Host smart-1062d63f-d497-4898-88f4-099b4f43b108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088250943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.1088250943
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.3670821419
Short name T764
Test name
Test status
Simulation time 84756500 ps
CPU time 1.47 seconds
Started Jul 03 07:14:45 PM PDT 24
Finished Jul 03 07:14:49 PM PDT 24
Peak memory 217264 kb
Host smart-cc5064d1-bd44-4b1e-b602-e90ca679aa44
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670821419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.3670821419
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.2832069118
Short name T450
Test name
Test status
Simulation time 45050757 ps
CPU time 2.14 seconds
Started Jul 03 07:14:50 PM PDT 24
Finished Jul 03 07:14:54 PM PDT 24
Peak memory 221752 kb
Host smart-95acd796-6827-42c4-ae00-66fa6ff9756b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832069118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.2832069118
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.2802623193
Short name T265
Test name
Test status
Simulation time 671119381 ps
CPU time 13.98 seconds
Started Jul 03 07:14:49 PM PDT 24
Finished Jul 03 07:15:04 PM PDT 24
Peak memory 225348 kb
Host smart-a1c7c7d4-1179-4249-8f2c-344d2a3a7f46
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802623193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.2802623193
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.3240992658
Short name T379
Test name
Test status
Simulation time 2047542437 ps
CPU time 8.61 seconds
Started Jul 03 07:14:55 PM PDT 24
Finished Jul 03 07:15:06 PM PDT 24
Peak memory 225508 kb
Host smart-be6505dd-831f-4edd-93b7-98290ea1da85
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240992658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.3240992658
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.196529956
Short name T451
Test name
Test status
Simulation time 426671333 ps
CPU time 9 seconds
Started Jul 03 07:14:55 PM PDT 24
Finished Jul 03 07:15:07 PM PDT 24
Peak memory 217812 kb
Host smart-274775f6-bad0-411e-863c-2802f497496d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196529956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.196529956
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.1210188296
Short name T653
Test name
Test status
Simulation time 766708895 ps
CPU time 12.71 seconds
Started Jul 03 07:14:56 PM PDT 24
Finished Jul 03 07:15:11 PM PDT 24
Peak memory 225272 kb
Host smart-8b2abf28-62ca-424f-b53b-04ec5a2ec6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210188296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.1210188296
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.546833207
Short name T68
Test name
Test status
Simulation time 63655310 ps
CPU time 2.16 seconds
Started Jul 03 07:14:49 PM PDT 24
Finished Jul 03 07:14:53 PM PDT 24
Peak memory 221996 kb
Host smart-94ad300b-c134-4cdb-a8b5-a34b10be694c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546833207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.546833207
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.484223010
Short name T733
Test name
Test status
Simulation time 2747617806 ps
CPU time 25 seconds
Started Jul 03 07:14:43 PM PDT 24
Finished Jul 03 07:15:10 PM PDT 24
Peak memory 250556 kb
Host smart-d9b8cb97-c7cd-412c-ae48-64ce1e5b3c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484223010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.484223010
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.2069861362
Short name T104
Test name
Test status
Simulation time 75827991 ps
CPU time 7.95 seconds
Started Jul 03 07:14:44 PM PDT 24
Finished Jul 03 07:14:54 PM PDT 24
Peak memory 250480 kb
Host smart-0c56b941-e219-4fe0-aa44-39143639aaeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069861362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.2069861362
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.648027484
Short name T751
Test name
Test status
Simulation time 16794407417 ps
CPU time 527.69 seconds
Started Jul 03 07:14:45 PM PDT 24
Finished Jul 03 07:23:34 PM PDT 24
Peak memory 250612 kb
Host smart-23092c49-72a3-4860-b10a-a96710405b64
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648027484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.648027484
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.4188439888
Short name T433
Test name
Test status
Simulation time 34520980 ps
CPU time 0.93 seconds
Started Jul 03 07:14:46 PM PDT 24
Finished Jul 03 07:14:49 PM PDT 24
Peak memory 208676 kb
Host smart-11418497-b2ce-4079-b68c-b50e81edf222
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188439888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.4188439888
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.2036485915
Short name T795
Test name
Test status
Simulation time 15546388 ps
CPU time 0.85 seconds
Started Jul 03 07:14:48 PM PDT 24
Finished Jul 03 07:14:51 PM PDT 24
Peak memory 208520 kb
Host smart-f334cbfe-25f8-4c51-9574-a04b6b60316d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036485915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.2036485915
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.1741022422
Short name T351
Test name
Test status
Simulation time 271003822 ps
CPU time 8.4 seconds
Started Jul 03 07:14:54 PM PDT 24
Finished Jul 03 07:15:04 PM PDT 24
Peak memory 217776 kb
Host smart-28b0f5d8-acde-431c-9631-5ab8efbea08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741022422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.1741022422
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.3058196116
Short name T26
Test name
Test status
Simulation time 331777946 ps
CPU time 9.16 seconds
Started Jul 03 07:14:55 PM PDT 24
Finished Jul 03 07:15:06 PM PDT 24
Peak memory 217144 kb
Host smart-b57c9c27-35cf-44cc-a945-24970da49535
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058196116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.3058196116
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.2043478463
Short name T3
Test name
Test status
Simulation time 24652027 ps
CPU time 1.69 seconds
Started Jul 03 07:14:47 PM PDT 24
Finished Jul 03 07:14:50 PM PDT 24
Peak memory 217720 kb
Host smart-cf3f662f-2d84-4fe2-9cfd-c1c54882083c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043478463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.2043478463
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.1684506497
Short name T581
Test name
Test status
Simulation time 2731992388 ps
CPU time 20.09 seconds
Started Jul 03 07:14:54 PM PDT 24
Finished Jul 03 07:15:16 PM PDT 24
Peak memory 225632 kb
Host smart-8abbc054-00ca-400e-a084-3eb17b175883
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684506497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.1684506497
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.1829069660
Short name T823
Test name
Test status
Simulation time 977946956 ps
CPU time 12.32 seconds
Started Jul 03 07:14:56 PM PDT 24
Finished Jul 03 07:15:10 PM PDT 24
Peak memory 225612 kb
Host smart-71a01dfa-a891-4e1b-94d6-e24cf4f64efd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829069660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.1829069660
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.2336019606
Short name T551
Test name
Test status
Simulation time 471287625 ps
CPU time 8.88 seconds
Started Jul 03 07:14:47 PM PDT 24
Finished Jul 03 07:14:58 PM PDT 24
Peak memory 225524 kb
Host smart-4c6f4fd0-8a5b-48af-8dc9-e9892a0bdd1b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336019606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
2336019606
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.3110315768
Short name T406
Test name
Test status
Simulation time 1555121042 ps
CPU time 9.37 seconds
Started Jul 03 07:14:55 PM PDT 24
Finished Jul 03 07:15:07 PM PDT 24
Peak memory 217936 kb
Host smart-8b7bdcb8-73e3-48b9-a20a-152b4e1564b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110315768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.3110315768
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.3818356429
Short name T553
Test name
Test status
Simulation time 56901525 ps
CPU time 3.22 seconds
Started Jul 03 07:14:44 PM PDT 24
Finished Jul 03 07:14:49 PM PDT 24
Peak memory 214032 kb
Host smart-4dd21321-cad2-46ad-8dd5-42ecaad6d054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818356429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.3818356429
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.1999158601
Short name T638
Test name
Test status
Simulation time 609018177 ps
CPU time 31.86 seconds
Started Jul 03 07:14:55 PM PDT 24
Finished Jul 03 07:15:29 PM PDT 24
Peak memory 250516 kb
Host smart-04958ce0-de7c-48cf-8cea-7c309a1ce957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999158601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.1999158601
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.4177966004
Short name T753
Test name
Test status
Simulation time 618972959 ps
CPU time 3.29 seconds
Started Jul 03 07:14:56 PM PDT 24
Finished Jul 03 07:15:01 PM PDT 24
Peak memory 225928 kb
Host smart-a7baea07-9303-4805-bd97-8719bef4035f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177966004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.4177966004
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.3129162458
Short name T678
Test name
Test status
Simulation time 6848415476 ps
CPU time 192.02 seconds
Started Jul 03 07:14:54 PM PDT 24
Finished Jul 03 07:18:08 PM PDT 24
Peak memory 222032 kb
Host smart-66279d78-4b16-40ee-919b-f178bbb10f78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129162458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.3129162458
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.962841163
Short name T639
Test name
Test status
Simulation time 17585768972 ps
CPU time 484.18 seconds
Started Jul 03 07:14:49 PM PDT 24
Finished Jul 03 07:22:55 PM PDT 24
Peak memory 496336 kb
Host smart-145e2d12-0f9b-4da8-817b-71f4c3cb2f4c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=962841163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all_with_rand_reset.962841163
Directory /workspace/46.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.2113420976
Short name T49
Test name
Test status
Simulation time 23192718 ps
CPU time 0.9 seconds
Started Jul 03 07:14:46 PM PDT 24
Finished Jul 03 07:14:49 PM PDT 24
Peak memory 211340 kb
Host smart-eeb16817-8f5e-4c0e-8ccc-e49195122d2a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113420976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.2113420976
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.1348653661
Short name T607
Test name
Test status
Simulation time 101870694 ps
CPU time 1.24 seconds
Started Jul 03 07:14:50 PM PDT 24
Finished Jul 03 07:14:53 PM PDT 24
Peak memory 208496 kb
Host smart-95d78b5a-2892-4c82-87d5-053f20eb559d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348653661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.1348653661
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.1397987580
Short name T305
Test name
Test status
Simulation time 319849252 ps
CPU time 10.8 seconds
Started Jul 03 07:14:49 PM PDT 24
Finished Jul 03 07:15:02 PM PDT 24
Peak memory 217712 kb
Host smart-e75834a8-3536-463e-a83b-1f25fbd4ac2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397987580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.1397987580
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.1287919813
Short name T330
Test name
Test status
Simulation time 206078051 ps
CPU time 5.85 seconds
Started Jul 03 07:14:49 PM PDT 24
Finished Jul 03 07:14:57 PM PDT 24
Peak memory 217208 kb
Host smart-0dcfa0fe-d155-4bb4-b8f1-8ee203bab33a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287919813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.1287919813
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.844897733
Short name T333
Test name
Test status
Simulation time 1278430171 ps
CPU time 10.35 seconds
Started Jul 03 07:14:49 PM PDT 24
Finished Jul 03 07:15:01 PM PDT 24
Peak memory 218400 kb
Host smart-33dbf11d-2d3d-4aec-89bb-1dde2d47c340
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844897733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.844897733
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.4210235571
Short name T841
Test name
Test status
Simulation time 1377494502 ps
CPU time 14.02 seconds
Started Jul 03 07:14:59 PM PDT 24
Finished Jul 03 07:15:17 PM PDT 24
Peak memory 225536 kb
Host smart-203878c2-db53-418f-b109-e25b0ec85815
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210235571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.4210235571
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.878388829
Short name T245
Test name
Test status
Simulation time 1744296515 ps
CPU time 14.19 seconds
Started Jul 03 07:14:58 PM PDT 24
Finished Jul 03 07:15:16 PM PDT 24
Peak memory 217736 kb
Host smart-7cc49ed0-870d-4cb2-a84f-d0b04081f098
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878388829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.878388829
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.507251721
Short name T566
Test name
Test status
Simulation time 977466182 ps
CPU time 9.86 seconds
Started Jul 03 07:14:57 PM PDT 24
Finished Jul 03 07:15:10 PM PDT 24
Peak memory 225744 kb
Host smart-965de9e8-03c3-4245-b0c2-9e9f058ea51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507251721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.507251721
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.2511833258
Short name T513
Test name
Test status
Simulation time 137544995 ps
CPU time 2.34 seconds
Started Jul 03 07:14:48 PM PDT 24
Finished Jul 03 07:14:52 PM PDT 24
Peak memory 213824 kb
Host smart-7daf30ab-bc43-4463-926c-25d67f4db16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511833258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.2511833258
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.2121426464
Short name T682
Test name
Test status
Simulation time 761631185 ps
CPU time 26.09 seconds
Started Jul 03 07:14:48 PM PDT 24
Finished Jul 03 07:15:16 PM PDT 24
Peak memory 250444 kb
Host smart-3003e167-5af5-4aab-a7b6-b53fb051911c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121426464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.2121426464
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.3072718500
Short name T334
Test name
Test status
Simulation time 50834489 ps
CPU time 7.9 seconds
Started Jul 03 07:14:44 PM PDT 24
Finished Jul 03 07:14:55 PM PDT 24
Peak memory 250544 kb
Host smart-1335b518-e9ca-4a39-b431-6abb166ac9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072718500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.3072718500
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.125073611
Short name T565
Test name
Test status
Simulation time 5288913412 ps
CPU time 127.23 seconds
Started Jul 03 07:14:49 PM PDT 24
Finished Jul 03 07:16:58 PM PDT 24
Peak memory 283344 kb
Host smart-6dbc889d-b56c-444e-b019-54ac059763a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125073611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.125073611
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.3536729520
Short name T171
Test name
Test status
Simulation time 11335381229 ps
CPU time 276.27 seconds
Started Jul 03 07:14:49 PM PDT 24
Finished Jul 03 07:19:27 PM PDT 24
Peak memory 277324 kb
Host smart-6e77874d-3884-4cd8-9bf6-dc89ee989c08
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3536729520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all_with_rand_reset.3536729520
Directory /workspace/47.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.444489848
Short name T43
Test name
Test status
Simulation time 31311008 ps
CPU time 0.76 seconds
Started Jul 03 07:14:55 PM PDT 24
Finished Jul 03 07:14:57 PM PDT 24
Peak memory 208248 kb
Host smart-106f0fc5-c852-46f7-93ab-9c34d4b57e1f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444489848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ct
rl_volatile_unlock_smoke.444489848
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.483928214
Short name T75
Test name
Test status
Simulation time 49757679 ps
CPU time 1 seconds
Started Jul 03 07:14:56 PM PDT 24
Finished Jul 03 07:15:00 PM PDT 24
Peak memory 208504 kb
Host smart-34e5217d-c335-422c-9894-879b083ce263
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483928214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.483928214
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.2786495349
Short name T203
Test name
Test status
Simulation time 796949875 ps
CPU time 12.59 seconds
Started Jul 03 07:14:50 PM PDT 24
Finished Jul 03 07:15:04 PM PDT 24
Peak memory 225536 kb
Host smart-8f6fc631-00ed-45c9-b6f2-434d2ea9eaee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786495349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.2786495349
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.1174093955
Short name T430
Test name
Test status
Simulation time 6004069536 ps
CPU time 11.1 seconds
Started Jul 03 07:15:00 PM PDT 24
Finished Jul 03 07:15:16 PM PDT 24
Peak memory 217212 kb
Host smart-911b59ab-d8ba-4b35-a1ff-06875674c8c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174093955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.1174093955
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.996926111
Short name T600
Test name
Test status
Simulation time 70747817 ps
CPU time 1.85 seconds
Started Jul 03 07:14:57 PM PDT 24
Finished Jul 03 07:15:02 PM PDT 24
Peak memory 217744 kb
Host smart-8753ebb9-28cb-4bb8-bd8c-5d7aeb1b60da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996926111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.996926111
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.3749116267
Short name T748
Test name
Test status
Simulation time 1034024107 ps
CPU time 8.98 seconds
Started Jul 03 07:15:00 PM PDT 24
Finished Jul 03 07:15:13 PM PDT 24
Peak memory 225360 kb
Host smart-4f6ca2c9-4f35-4e15-be8b-ae1b8ca82e7f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749116267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.3749116267
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.265754102
Short name T409
Test name
Test status
Simulation time 834405268 ps
CPU time 12.19 seconds
Started Jul 03 07:14:58 PM PDT 24
Finished Jul 03 07:15:13 PM PDT 24
Peak memory 225464 kb
Host smart-db7f7892-60a6-4536-a380-96fc0de4a8d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265754102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_di
gest.265754102
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.3829261001
Short name T198
Test name
Test status
Simulation time 375628089 ps
CPU time 12.88 seconds
Started Jul 03 07:14:57 PM PDT 24
Finished Jul 03 07:15:13 PM PDT 24
Peak memory 224432 kb
Host smart-80ad9c24-3e3a-4da7-adab-50105d4ea59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829261001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.3829261001
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.3491117910
Short name T286
Test name
Test status
Simulation time 45216573 ps
CPU time 1.01 seconds
Started Jul 03 07:14:48 PM PDT 24
Finished Jul 03 07:14:51 PM PDT 24
Peak memory 211720 kb
Host smart-bd452910-b72e-4e73-9cc5-ed87ebea8739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491117910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.3491117910
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.2547810912
Short name T626
Test name
Test status
Simulation time 2769978077 ps
CPU time 32.54 seconds
Started Jul 03 07:14:56 PM PDT 24
Finished Jul 03 07:15:31 PM PDT 24
Peak memory 250556 kb
Host smart-f664ec15-1b59-4ce5-801b-de28fb37c768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547810912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.2547810912
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.3072942457
Short name T523
Test name
Test status
Simulation time 59593883 ps
CPU time 7.99 seconds
Started Jul 03 07:15:01 PM PDT 24
Finished Jul 03 07:15:14 PM PDT 24
Peak memory 250468 kb
Host smart-6f52a3c1-875a-4613-92cd-3a262e59b398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072942457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.3072942457
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.2475984509
Short name T428
Test name
Test status
Simulation time 10227288232 ps
CPU time 318.62 seconds
Started Jul 03 07:14:59 PM PDT 24
Finished Jul 03 07:20:22 PM PDT 24
Peak memory 315204 kb
Host smart-354fb939-3116-4ee7-85c6-b2920332ea97
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475984509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.2475984509
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.1041275257
Short name T304
Test name
Test status
Simulation time 14936809 ps
CPU time 0.86 seconds
Started Jul 03 07:14:50 PM PDT 24
Finished Jul 03 07:14:52 PM PDT 24
Peak memory 208540 kb
Host smart-76d92461-cd95-43d4-bd52-7d765b04c44e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041275257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.1041275257
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.3255985941
Short name T818
Test name
Test status
Simulation time 468850966 ps
CPU time 1.26 seconds
Started Jul 03 07:15:01 PM PDT 24
Finished Jul 03 07:15:08 PM PDT 24
Peak memory 208580 kb
Host smart-fb32392d-2ab7-45b3-966a-7a6e16eac59d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255985941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.3255985941
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.3325446368
Short name T321
Test name
Test status
Simulation time 835040878 ps
CPU time 9.29 seconds
Started Jul 03 07:14:58 PM PDT 24
Finished Jul 03 07:15:10 PM PDT 24
Peak memory 217876 kb
Host smart-c8c4de07-5a16-4576-9aef-11b3e5d21835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325446368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.3325446368
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.450081690
Short name T865
Test name
Test status
Simulation time 354889001 ps
CPU time 2.61 seconds
Started Jul 03 07:14:58 PM PDT 24
Finished Jul 03 07:15:04 PM PDT 24
Peak memory 217192 kb
Host smart-586753a7-eb44-462d-b65a-c7df4f67a2e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450081690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.450081690
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.4146899885
Short name T520
Test name
Test status
Simulation time 139068628 ps
CPU time 3.5 seconds
Started Jul 03 07:14:47 PM PDT 24
Finished Jul 03 07:14:52 PM PDT 24
Peak memory 222168 kb
Host smart-2e61fa2b-9a01-41ff-95eb-3167d7786328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146899885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.4146899885
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.3764598953
Short name T620
Test name
Test status
Simulation time 564420639 ps
CPU time 9.68 seconds
Started Jul 03 07:14:59 PM PDT 24
Finished Jul 03 07:15:13 PM PDT 24
Peak memory 225536 kb
Host smart-d84e6654-f3d3-4fac-b640-a37e8fd73049
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764598953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.3764598953
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.4164480052
Short name T307
Test name
Test status
Simulation time 335883486 ps
CPU time 7.78 seconds
Started Jul 03 07:15:00 PM PDT 24
Finished Jul 03 07:15:13 PM PDT 24
Peak memory 217696 kb
Host smart-d2eff44f-8730-4ba3-9c3a-5a9a0f0c1273
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164480052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
4164480052
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.3284662862
Short name T10
Test name
Test status
Simulation time 258576402 ps
CPU time 7.19 seconds
Started Jul 03 07:15:01 PM PDT 24
Finished Jul 03 07:15:13 PM PDT 24
Peak memory 217816 kb
Host smart-6672d72f-622e-438f-964a-0eb42725f385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284662862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.3284662862
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.4030363232
Short name T666
Test name
Test status
Simulation time 38843038 ps
CPU time 2.94 seconds
Started Jul 03 07:15:00 PM PDT 24
Finished Jul 03 07:15:08 PM PDT 24
Peak memory 213912 kb
Host smart-aa5a3c3e-7365-4772-8131-07fbf481a1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030363232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.4030363232
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.1897622080
Short name T88
Test name
Test status
Simulation time 984852071 ps
CPU time 32.27 seconds
Started Jul 03 07:15:00 PM PDT 24
Finished Jul 03 07:15:37 PM PDT 24
Peak memory 250588 kb
Host smart-b6e506a5-9934-423a-8204-507dd4a2a08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897622080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.1897622080
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.539178817
Short name T355
Test name
Test status
Simulation time 105746316 ps
CPU time 3.79 seconds
Started Jul 03 07:14:58 PM PDT 24
Finished Jul 03 07:15:05 PM PDT 24
Peak memory 222352 kb
Host smart-4b4cbafa-1d4c-47c6-bb15-37119d88f6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539178817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.539178817
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.3848925625
Short name T773
Test name
Test status
Simulation time 38653040522 ps
CPU time 298.37 seconds
Started Jul 03 07:14:58 PM PDT 24
Finished Jul 03 07:20:00 PM PDT 24
Peak memory 311720 kb
Host smart-4b34aef9-842a-405d-8cb6-7e7966ee6b2a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848925625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.3848925625
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.1844866570
Short name T543
Test name
Test status
Simulation time 32665546597 ps
CPU time 228.21 seconds
Started Jul 03 07:15:01 PM PDT 24
Finished Jul 03 07:18:54 PM PDT 24
Peak memory 384844 kb
Host smart-996ef837-3397-46b8-b369-5def14843998
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1844866570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all_with_rand_reset.1844866570
Directory /workspace/49.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.3253361703
Short name T41
Test name
Test status
Simulation time 35006902 ps
CPU time 1.17 seconds
Started Jul 03 07:14:59 PM PDT 24
Finished Jul 03 07:15:04 PM PDT 24
Peak memory 212516 kb
Host smart-8f9f1c27-ea16-436e-a077-ed9263c05a42
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253361703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.3253361703
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.3693059072
Short name T691
Test name
Test status
Simulation time 79706029 ps
CPU time 0.92 seconds
Started Jul 03 07:11:29 PM PDT 24
Finished Jul 03 07:11:57 PM PDT 24
Peak memory 208508 kb
Host smart-2357ad04-9a4e-4368-8817-bc06edc60bc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693059072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.3693059072
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.3863707343
Short name T106
Test name
Test status
Simulation time 11016659 ps
CPU time 0.84 seconds
Started Jul 03 07:11:01 PM PDT 24
Finished Jul 03 07:11:37 PM PDT 24
Peak memory 208576 kb
Host smart-65c30ed1-35a2-46b1-ae1a-03e9f6e18e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863707343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.3863707343
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.570267111
Short name T312
Test name
Test status
Simulation time 2556074491 ps
CPU time 13.73 seconds
Started Jul 03 07:10:58 PM PDT 24
Finished Jul 03 07:11:47 PM PDT 24
Peak memory 225636 kb
Host smart-8d3e4cc7-0df7-49cd-a593-2d3ca5cb7b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570267111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.570267111
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.709689887
Short name T30
Test name
Test status
Simulation time 541537214 ps
CPU time 4.63 seconds
Started Jul 03 07:11:01 PM PDT 24
Finished Jul 03 07:11:40 PM PDT 24
Peak memory 217232 kb
Host smart-367693af-5ae0-402f-aa8c-48b663ab397d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709689887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.709689887
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.78115541
Short name T212
Test name
Test status
Simulation time 4450720630 ps
CPU time 35.86 seconds
Started Jul 03 07:11:02 PM PDT 24
Finished Jul 03 07:12:13 PM PDT 24
Peak memory 218424 kb
Host smart-de380491-d014-401d-9202-165861175d0b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78115541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_l
c_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_erro
rs.78115541
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.3530956428
Short name T222
Test name
Test status
Simulation time 489457150 ps
CPU time 4.97 seconds
Started Jul 03 07:11:04 PM PDT 24
Finished Jul 03 07:11:44 PM PDT 24
Peak memory 217228 kb
Host smart-0751a420-5f1e-41c8-a395-9aaba221ddfc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530956428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.3
530956428
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.333187715
Short name T780
Test name
Test status
Simulation time 269241491 ps
CPU time 8.34 seconds
Started Jul 03 07:11:03 PM PDT 24
Finished Jul 03 07:11:47 PM PDT 24
Peak memory 222512 kb
Host smart-96de1a88-ecfc-4dec-9f44-8efb31d467b0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333187715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_
prog_failure.333187715
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.600507552
Short name T629
Test name
Test status
Simulation time 2302186451 ps
CPU time 18.85 seconds
Started Jul 03 07:11:02 PM PDT 24
Finished Jul 03 07:11:55 PM PDT 24
Peak memory 217172 kb
Host smart-9c6acb65-8f91-4da7-ab7e-6da0ec61a096
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600507552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_regwen_during_op.600507552
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.3122940319
Short name T97
Test name
Test status
Simulation time 1418184738 ps
CPU time 31.99 seconds
Started Jul 03 07:11:02 PM PDT 24
Finished Jul 03 07:12:09 PM PDT 24
Peak memory 266844 kb
Host smart-cbdd64b5-0d5d-4b2f-bffd-61f854c26acc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122940319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.3122940319
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.3577166798
Short name T374
Test name
Test status
Simulation time 383355408 ps
CPU time 15.37 seconds
Started Jul 03 07:11:04 PM PDT 24
Finished Jul 03 07:11:55 PM PDT 24
Peak memory 245396 kb
Host smart-31892736-2b40-49d3-979d-e1b7da20cf37
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577166798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.3577166798
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.2031311403
Short name T343
Test name
Test status
Simulation time 43475572 ps
CPU time 2.25 seconds
Started Jul 03 07:10:58 PM PDT 24
Finished Jul 03 07:11:35 PM PDT 24
Peak memory 217792 kb
Host smart-fd431154-7e3d-4373-bf8d-cbcc31c8fd1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031311403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.2031311403
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.1196191892
Short name T408
Test name
Test status
Simulation time 1289195830 ps
CPU time 18.93 seconds
Started Jul 03 07:11:01 PM PDT 24
Finished Jul 03 07:11:55 PM PDT 24
Peak memory 214268 kb
Host smart-eb0124d1-3dd0-4e17-8d1a-59c5ea74d3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196191892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.1196191892
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.687144159
Short name T200
Test name
Test status
Simulation time 1288479196 ps
CPU time 12.9 seconds
Started Jul 03 07:11:01 PM PDT 24
Finished Jul 03 07:11:49 PM PDT 24
Peak memory 225572 kb
Host smart-0d66d920-04c1-43be-afd0-bd3c80d729d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687144159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.687144159
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.3110911288
Short name T438
Test name
Test status
Simulation time 1359284325 ps
CPU time 16.81 seconds
Started Jul 03 07:11:00 PM PDT 24
Finished Jul 03 07:11:51 PM PDT 24
Peak memory 225520 kb
Host smart-3ea8e0f1-b9e9-41c0-8565-74535cc665d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110911288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.3110911288
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.114082859
Short name T514
Test name
Test status
Simulation time 623921060 ps
CPU time 7.97 seconds
Started Jul 03 07:11:02 PM PDT 24
Finished Jul 03 07:11:45 PM PDT 24
Peak memory 217680 kb
Host smart-81e2921c-9b47-45c6-b8f8-28cdeefbf3a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114082859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.114082859
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.2146527863
Short name T163
Test name
Test status
Simulation time 1222760654 ps
CPU time 12.91 seconds
Started Jul 03 07:11:00 PM PDT 24
Finished Jul 03 07:11:47 PM PDT 24
Peak memory 225588 kb
Host smart-ca9c114a-bd5a-445a-b353-c2e61392c1f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146527863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.2146527863
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.3817535342
Short name T661
Test name
Test status
Simulation time 330999875 ps
CPU time 4.86 seconds
Started Jul 03 07:10:57 PM PDT 24
Finished Jul 03 07:11:36 PM PDT 24
Peak memory 217324 kb
Host smart-702d1cc1-c5c6-47b7-a2ed-f7bf9624ec88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817535342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.3817535342
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.1618371391
Short name T484
Test name
Test status
Simulation time 239311582 ps
CPU time 30.12 seconds
Started Jul 03 07:11:04 PM PDT 24
Finished Jul 03 07:12:09 PM PDT 24
Peak memory 245736 kb
Host smart-76027d9b-e110-414e-9631-97151333e347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618371391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.1618371391
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.2747385650
Short name T316
Test name
Test status
Simulation time 60234527 ps
CPU time 6.47 seconds
Started Jul 03 07:11:04 PM PDT 24
Finished Jul 03 07:11:46 PM PDT 24
Peak memory 246440 kb
Host smart-b2fc2bd0-4e31-4e86-ae7d-e1187b98a52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747385650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.2747385650
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.1746809914
Short name T224
Test name
Test status
Simulation time 5812622609 ps
CPU time 138.93 seconds
Started Jul 03 07:11:03 PM PDT 24
Finished Jul 03 07:13:58 PM PDT 24
Peak memory 273208 kb
Host smart-4ac325d4-04b2-45c0-a972-06e6f19cec9b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746809914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.1746809914
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.2851867449
Short name T824
Test name
Test status
Simulation time 26637219 ps
CPU time 1.33 seconds
Started Jul 03 07:11:15 PM PDT 24
Finished Jul 03 07:11:47 PM PDT 24
Peak memory 208656 kb
Host smart-eaef7f3b-12d3-4e36-8b91-a27fc50f35c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851867449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.2851867449
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.3417459681
Short name T215
Test name
Test status
Simulation time 74896872 ps
CPU time 0.78 seconds
Started Jul 03 07:11:10 PM PDT 24
Finished Jul 03 07:11:43 PM PDT 24
Peak memory 208524 kb
Host smart-6fef40bf-6872-4538-af3f-83a9afeaebe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417459681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.3417459681
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.1045909047
Short name T836
Test name
Test status
Simulation time 591770948 ps
CPU time 13.72 seconds
Started Jul 03 07:11:12 PM PDT 24
Finished Jul 03 07:11:59 PM PDT 24
Peak memory 217788 kb
Host smart-0b9c795b-d8ec-41a0-8c97-2982be17bc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045909047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.1045909047
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.565783949
Short name T783
Test name
Test status
Simulation time 283135796 ps
CPU time 3.86 seconds
Started Jul 03 07:11:14 PM PDT 24
Finished Jul 03 07:11:49 PM PDT 24
Peak memory 217204 kb
Host smart-1bec2847-23dd-46ab-917f-ce541520adca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565783949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.565783949
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.628031917
Short name T835
Test name
Test status
Simulation time 3663480719 ps
CPU time 96.68 seconds
Started Jul 03 07:11:17 PM PDT 24
Finished Jul 03 07:13:25 PM PDT 24
Peak memory 218924 kb
Host smart-efe2f0fb-3ec5-43e9-89e4-8f6eb979b3c5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628031917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_err
ors.628031917
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.1325002947
Short name T715
Test name
Test status
Simulation time 115563652 ps
CPU time 2.01 seconds
Started Jul 03 07:11:15 PM PDT 24
Finished Jul 03 07:11:48 PM PDT 24
Peak memory 217228 kb
Host smart-acdf75e9-95b3-4aa3-85b1-906ecf578adc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325002947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.1
325002947
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.184829686
Short name T248
Test name
Test status
Simulation time 690772638 ps
CPU time 12.84 seconds
Started Jul 03 07:11:16 PM PDT 24
Finished Jul 03 07:12:00 PM PDT 24
Peak memory 224608 kb
Host smart-a191d22e-b82a-4fdf-bac3-e7b549480bdb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184829686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_
prog_failure.184829686
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.1352747291
Short name T536
Test name
Test status
Simulation time 4955612705 ps
CPU time 27.75 seconds
Started Jul 03 07:11:19 PM PDT 24
Finished Jul 03 07:12:17 PM PDT 24
Peak memory 217180 kb
Host smart-0aafaeff-48ae-4a96-b2cd-c7136b889b88
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352747291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.1352747291
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.2175353730
Short name T239
Test name
Test status
Simulation time 161420348 ps
CPU time 5.61 seconds
Started Jul 03 07:11:09 PM PDT 24
Finished Jul 03 07:11:48 PM PDT 24
Peak memory 217224 kb
Host smart-e6f5af57-b092-4b86-b960-3123528d86d1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175353730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
2175353730
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.673731079
Short name T346
Test name
Test status
Simulation time 3854622552 ps
CPU time 63.16 seconds
Started Jul 03 07:11:18 PM PDT 24
Finished Jul 03 07:12:52 PM PDT 24
Peak memory 283320 kb
Host smart-ec7597c9-34d1-442e-888a-9b86b801cb27
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673731079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_state_failure.673731079
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.3645692145
Short name T447
Test name
Test status
Simulation time 398871209 ps
CPU time 12.73 seconds
Started Jul 03 07:11:15 PM PDT 24
Finished Jul 03 07:11:59 PM PDT 24
Peak memory 250560 kb
Host smart-94a6a9d6-10f7-4bc2-bfd6-b5a9c8982df2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645692145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.3645692145
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.2721125528
Short name T596
Test name
Test status
Simulation time 91130761 ps
CPU time 2.64 seconds
Started Jul 03 07:11:04 PM PDT 24
Finished Jul 03 07:11:42 PM PDT 24
Peak memory 217792 kb
Host smart-b4770276-f646-49f8-9bac-65b649a3a29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721125528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.2721125528
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.3312470457
Short name T717
Test name
Test status
Simulation time 329934107 ps
CPU time 7.9 seconds
Started Jul 03 07:11:10 PM PDT 24
Finished Jul 03 07:11:51 PM PDT 24
Peak memory 217200 kb
Host smart-8fdcdf01-8abe-4568-96da-d8e40630174a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312470457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.3312470457
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.1728354264
Short name T570
Test name
Test status
Simulation time 5492003432 ps
CPU time 18.46 seconds
Started Jul 03 07:11:15 PM PDT 24
Finished Jul 03 07:12:05 PM PDT 24
Peak memory 225560 kb
Host smart-9941fbd3-394e-4dae-9aca-c5a9a02c77bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728354264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.1728354264
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.2389385090
Short name T702
Test name
Test status
Simulation time 389355781 ps
CPU time 14.49 seconds
Started Jul 03 07:11:15 PM PDT 24
Finished Jul 03 07:12:00 PM PDT 24
Peak memory 217692 kb
Host smart-0dbb7449-09bb-4d3b-b28e-2fc57820f70a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389385090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.2
389385090
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.2444823761
Short name T771
Test name
Test status
Simulation time 822035929 ps
CPU time 9.47 seconds
Started Jul 03 07:11:13 PM PDT 24
Finished Jul 03 07:11:54 PM PDT 24
Peak memory 217812 kb
Host smart-a0dbbd07-cc22-4018-bf50-d7a5fedcf7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444823761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.2444823761
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.3481149625
Short name T347
Test name
Test status
Simulation time 63844791 ps
CPU time 2.51 seconds
Started Jul 03 07:11:06 PM PDT 24
Finished Jul 03 07:11:43 PM PDT 24
Peak memory 213908 kb
Host smart-ebae79e2-e249-47b7-8179-ccb4f473983f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481149625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.3481149625
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.935703452
Short name T388
Test name
Test status
Simulation time 932449742 ps
CPU time 30.77 seconds
Started Jul 03 07:11:05 PM PDT 24
Finished Jul 03 07:12:11 PM PDT 24
Peak memory 245920 kb
Host smart-1757c4d6-77f0-4683-81eb-cfcd08eb1bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935703452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.935703452
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.3848926373
Short name T228
Test name
Test status
Simulation time 257044308 ps
CPU time 7.75 seconds
Started Jul 03 07:11:06 PM PDT 24
Finished Jul 03 07:11:48 PM PDT 24
Peak memory 250476 kb
Host smart-b3e0c94a-e023-4e82-8242-273d8a64fe82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848926373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.3848926373
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.4070300087
Short name T34
Test name
Test status
Simulation time 2601511368 ps
CPU time 78.13 seconds
Started Jul 03 07:11:17 PM PDT 24
Finished Jul 03 07:13:07 PM PDT 24
Peak memory 276168 kb
Host smart-2b0d57e4-6b4d-4092-9681-de2180ae11dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070300087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.4070300087
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.2149684510
Short name T153
Test name
Test status
Simulation time 12517708310 ps
CPU time 193.54 seconds
Started Jul 03 07:11:18 PM PDT 24
Finished Jul 03 07:15:03 PM PDT 24
Peak memory 275924 kb
Host smart-c1a4f3df-9287-4ca1-b8bc-da8aaba91625
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2149684510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.2149684510
Directory /workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.3028406477
Short name T268
Test name
Test status
Simulation time 31737403 ps
CPU time 0.94 seconds
Started Jul 03 07:11:04 PM PDT 24
Finished Jul 03 07:11:40 PM PDT 24
Peak memory 217416 kb
Host smart-7b8398d4-6563-4b8b-9a4f-e22b9cedec66
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028406477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.3028406477
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.4279640199
Short name T151
Test name
Test status
Simulation time 50239607 ps
CPU time 1.35 seconds
Started Jul 03 07:11:24 PM PDT 24
Finished Jul 03 07:11:54 PM PDT 24
Peak memory 208504 kb
Host smart-1c208f64-10c9-4f1d-aa2c-efed49a58b51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279640199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.4279640199
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.2676467374
Short name T385
Test name
Test status
Simulation time 17979508 ps
CPU time 0.76 seconds
Started Jul 03 07:11:22 PM PDT 24
Finished Jul 03 07:11:52 PM PDT 24
Peak memory 208428 kb
Host smart-5282f87f-3b2f-4b90-aaa9-901bf45e25e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676467374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.2676467374
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.3971593288
Short name T577
Test name
Test status
Simulation time 289524414 ps
CPU time 14.37 seconds
Started Jul 03 07:11:22 PM PDT 24
Finished Jul 03 07:12:06 PM PDT 24
Peak memory 217844 kb
Host smart-ef2e015d-5fa1-4044-9a18-d2cd77991276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971593288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.3971593288
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.4110550549
Short name T766
Test name
Test status
Simulation time 1496052828 ps
CPU time 33.08 seconds
Started Jul 03 07:11:20 PM PDT 24
Finished Jul 03 07:12:24 PM PDT 24
Peak memory 216988 kb
Host smart-0c79ce73-c102-4acc-87a1-caab6f34fc98
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110550549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.4110550549
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.2233824926
Short name T348
Test name
Test status
Simulation time 1418669577 ps
CPU time 41.9 seconds
Started Jul 03 07:11:20 PM PDT 24
Finished Jul 03 07:12:33 PM PDT 24
Peak memory 225496 kb
Host smart-f26e79ac-49f5-4905-8c06-b4592b54fe4a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233824926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.2233824926
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.3941372818
Short name T703
Test name
Test status
Simulation time 1746669999 ps
CPU time 11.88 seconds
Started Jul 03 07:11:20 PM PDT 24
Finished Jul 03 07:12:03 PM PDT 24
Peak memory 217256 kb
Host smart-a7fb7c4f-a413-4107-bc4a-e229e557ddfe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941372818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.3
941372818
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.4255118283
Short name T786
Test name
Test status
Simulation time 320979015 ps
CPU time 3.18 seconds
Started Jul 03 07:11:19 PM PDT 24
Finished Jul 03 07:11:53 PM PDT 24
Peak memory 217716 kb
Host smart-b861ca00-c0d2-4ce9-b354-fbbb6a9f0f79
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255118283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.4255118283
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.1002030770
Short name T806
Test name
Test status
Simulation time 1391362650 ps
CPU time 19.85 seconds
Started Jul 03 07:11:20 PM PDT 24
Finished Jul 03 07:12:10 PM PDT 24
Peak memory 217156 kb
Host smart-3b23b7b5-f03e-48f0-881e-762b380ddc56
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002030770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.1002030770
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.1362751535
Short name T39
Test name
Test status
Simulation time 799898533 ps
CPU time 6.48 seconds
Started Jul 03 07:11:23 PM PDT 24
Finished Jul 03 07:11:59 PM PDT 24
Peak memory 217124 kb
Host smart-0ed38844-13b6-40a7-b2de-4e01a2f18624
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362751535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
1362751535
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.370842392
Short name T769
Test name
Test status
Simulation time 1017209313 ps
CPU time 50.01 seconds
Started Jul 03 07:11:18 PM PDT 24
Finished Jul 03 07:12:39 PM PDT 24
Peak memory 266828 kb
Host smart-557f31b6-1ce7-4d3c-9e54-bf9339d751e4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370842392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_state_failure.370842392
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.3821754477
Short name T237
Test name
Test status
Simulation time 1253561751 ps
CPU time 12.51 seconds
Started Jul 03 07:11:19 PM PDT 24
Finished Jul 03 07:12:02 PM PDT 24
Peak memory 248484 kb
Host smart-dd160af4-981a-45bc-9d1a-2ada7fc95a57
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821754477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.3821754477
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.4091029802
Short name T276
Test name
Test status
Simulation time 97998759 ps
CPU time 2.01 seconds
Started Jul 03 07:11:19 PM PDT 24
Finished Jul 03 07:11:51 PM PDT 24
Peak memory 217768 kb
Host smart-3e21062e-0f94-446a-a3b8-87206fb0017f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091029802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.4091029802
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.3637262294
Short name T415
Test name
Test status
Simulation time 256549359 ps
CPU time 9.54 seconds
Started Jul 03 07:11:23 PM PDT 24
Finished Jul 03 07:12:02 PM PDT 24
Peak memory 217184 kb
Host smart-0b0aad16-6e27-42ce-9fa4-fd4475dae3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637262294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.3637262294
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.1345745400
Short name T396
Test name
Test status
Simulation time 2403729787 ps
CPU time 21.47 seconds
Started Jul 03 07:11:23 PM PDT 24
Finished Jul 03 07:12:14 PM PDT 24
Peak memory 225640 kb
Host smart-8edd4df2-85b0-4f3d-81f1-ba7a0c21bc9b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345745400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.1345745400
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.830181388
Short name T277
Test name
Test status
Simulation time 1621636958 ps
CPU time 10.68 seconds
Started Jul 03 07:11:20 PM PDT 24
Finished Jul 03 07:12:01 PM PDT 24
Peak memory 225524 kb
Host smart-d0e88a6d-d0ba-4f36-b514-9f609f66bc0b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830181388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_dig
est.830181388
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.3521179340
Short name T728
Test name
Test status
Simulation time 1145399464 ps
CPU time 10.91 seconds
Started Jul 03 07:11:21 PM PDT 24
Finished Jul 03 07:12:02 PM PDT 24
Peak memory 217696 kb
Host smart-b004afc8-3dd0-4fce-b57c-e4992534e42f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521179340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.3
521179340
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.2520029429
Short name T608
Test name
Test status
Simulation time 630892801 ps
CPU time 12.87 seconds
Started Jul 03 07:11:19 PM PDT 24
Finished Jul 03 07:12:02 PM PDT 24
Peak memory 225548 kb
Host smart-3fa0a132-92d8-49a4-84c7-07575e909b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520029429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.2520029429
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.1359832415
Short name T319
Test name
Test status
Simulation time 96698207 ps
CPU time 3.14 seconds
Started Jul 03 07:11:14 PM PDT 24
Finished Jul 03 07:11:48 PM PDT 24
Peak memory 217180 kb
Host smart-58e1d228-258a-4933-b1f5-3f536ae7bdc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359832415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.1359832415
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.1195868423
Short name T225
Test name
Test status
Simulation time 230580281 ps
CPU time 20.55 seconds
Started Jul 03 07:11:14 PM PDT 24
Finished Jul 03 07:12:06 PM PDT 24
Peak memory 250544 kb
Host smart-52219e77-de23-40b6-987f-3c5edec52d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195868423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.1195868423
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.1367126711
Short name T736
Test name
Test status
Simulation time 164422915 ps
CPU time 6.58 seconds
Started Jul 03 07:11:15 PM PDT 24
Finished Jul 03 07:11:53 PM PDT 24
Peak memory 242328 kb
Host smart-1be67a24-128c-4482-8c3d-706ee52cdc98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367126711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.1367126711
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.2307734804
Short name T495
Test name
Test status
Simulation time 2149967087 ps
CPU time 24.86 seconds
Started Jul 03 07:11:21 PM PDT 24
Finished Jul 03 07:12:16 PM PDT 24
Peak memory 225600 kb
Host smart-34aa18df-ff90-4d2c-b944-d600549bbabc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307734804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.2307734804
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1625398416
Short name T240
Test name
Test status
Simulation time 11280772 ps
CPU time 0.82 seconds
Started Jul 03 07:11:14 PM PDT 24
Finished Jul 03 07:11:47 PM PDT 24
Peak memory 208384 kb
Host smart-ba4f12c4-a686-4149-9b89-d6dc8e832a8d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625398416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.1625398416
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.2155500711
Short name T796
Test name
Test status
Simulation time 52539186 ps
CPU time 1.15 seconds
Started Jul 03 07:11:30 PM PDT 24
Finished Jul 03 07:11:58 PM PDT 24
Peak memory 208520 kb
Host smart-d93ce6c3-16c2-41ba-aa1e-1d37e2e88dad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155500711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.2155500711
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.2038360501
Short name T546
Test name
Test status
Simulation time 32385180 ps
CPU time 0.95 seconds
Started Jul 03 07:11:26 PM PDT 24
Finished Jul 03 07:11:55 PM PDT 24
Peak memory 208460 kb
Host smart-de7ba032-91b1-4e81-99d3-26f334726971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038360501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.2038360501
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.2651895458
Short name T299
Test name
Test status
Simulation time 348626431 ps
CPU time 10.81 seconds
Started Jul 03 07:11:24 PM PDT 24
Finished Jul 03 07:12:04 PM PDT 24
Peak memory 225580 kb
Host smart-c8f7c508-bbe2-44a6-b484-e4beac8ab695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651895458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.2651895458
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.557238423
Short name T826
Test name
Test status
Simulation time 4833433841 ps
CPU time 10.55 seconds
Started Jul 03 07:11:23 PM PDT 24
Finished Jul 03 07:12:03 PM PDT 24
Peak memory 217224 kb
Host smart-7b15db1e-e151-47e9-aea2-f9047b2723af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557238423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.557238423
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.2770419985
Short name T386
Test name
Test status
Simulation time 4139279344 ps
CPU time 18.14 seconds
Started Jul 03 07:11:24 PM PDT 24
Finished Jul 03 07:12:11 PM PDT 24
Peak memory 218452 kb
Host smart-acbab51c-41b9-4c23-83f7-29e54a6df9c1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770419985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.2770419985
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.3464733669
Short name T710
Test name
Test status
Simulation time 901273708 ps
CPU time 9.55 seconds
Started Jul 03 07:11:27 PM PDT 24
Finished Jul 03 07:12:04 PM PDT 24
Peak memory 217208 kb
Host smart-45c68f20-f6db-4757-b1e9-58fb1c5fc5da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464733669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.3
464733669
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.4241071036
Short name T311
Test name
Test status
Simulation time 320637274 ps
CPU time 3.65 seconds
Started Jul 03 07:11:33 PM PDT 24
Finished Jul 03 07:12:03 PM PDT 24
Peak memory 221512 kb
Host smart-fea838f9-be7d-40ba-ac21-8fa8a46ea591
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241071036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.4241071036
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.547935077
Short name T701
Test name
Test status
Simulation time 1036689666 ps
CPU time 32.12 seconds
Started Jul 03 07:11:24 PM PDT 24
Finished Jul 03 07:12:25 PM PDT 24
Peak memory 217192 kb
Host smart-95bee0b5-11aa-4689-8950-22f871e5f843
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547935077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_j
tag_regwen_during_op.547935077
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.1199128702
Short name T399
Test name
Test status
Simulation time 275825708 ps
CPU time 5.1 seconds
Started Jul 03 07:11:24 PM PDT 24
Finished Jul 03 07:11:58 PM PDT 24
Peak memory 217092 kb
Host smart-17b51199-21ab-4326-8291-afe24b1e9dba
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199128702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
1199128702
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.3671567547
Short name T640
Test name
Test status
Simulation time 6598402392 ps
CPU time 66.81 seconds
Started Jul 03 07:11:28 PM PDT 24
Finished Jul 03 07:13:03 PM PDT 24
Peak memory 275364 kb
Host smart-d17ce88b-e8a1-43e4-90ef-c21f6336c020
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671567547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.3671567547
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.1803896224
Short name T704
Test name
Test status
Simulation time 772437717 ps
CPU time 12.91 seconds
Started Jul 03 07:11:24 PM PDT 24
Finished Jul 03 07:12:06 PM PDT 24
Peak memory 217700 kb
Host smart-48f77131-3cfd-4438-9c61-12605ea1370c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803896224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.1803896224
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.3357151703
Short name T831
Test name
Test status
Simulation time 143528776 ps
CPU time 3.18 seconds
Started Jul 03 07:11:26 PM PDT 24
Finished Jul 03 07:11:58 PM PDT 24
Peak memory 217728 kb
Host smart-38f9cfd1-8e02-4153-a821-84d4321b5cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357151703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.3357151703
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.3600739877
Short name T534
Test name
Test status
Simulation time 955621083 ps
CPU time 13.33 seconds
Started Jul 03 07:11:28 PM PDT 24
Finished Jul 03 07:12:09 PM PDT 24
Peak memory 214012 kb
Host smart-454fd49e-e455-4a52-b9b8-9921eb074704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600739877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.3600739877
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.2790738937
Short name T642
Test name
Test status
Simulation time 2675859529 ps
CPU time 11.86 seconds
Started Jul 03 07:11:27 PM PDT 24
Finished Jul 03 07:12:07 PM PDT 24
Peak memory 225600 kb
Host smart-649bb893-5275-4497-b612-ae4e61970d84
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790738937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.2790738937
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.1741728381
Short name T164
Test name
Test status
Simulation time 1706932637 ps
CPU time 17.9 seconds
Started Jul 03 07:11:31 PM PDT 24
Finished Jul 03 07:12:16 PM PDT 24
Peak memory 225516 kb
Host smart-e6441c04-bd52-4b7f-b877-7f1d0cc7fb05
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741728381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.1741728381
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.2470145662
Short name T249
Test name
Test status
Simulation time 3553440763 ps
CPU time 10.89 seconds
Started Jul 03 07:11:27 PM PDT 24
Finished Jul 03 07:12:06 PM PDT 24
Peak memory 225536 kb
Host smart-6e3c292b-992d-422e-82bc-245474b06b3a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470145662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.2
470145662
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.719427982
Short name T721
Test name
Test status
Simulation time 775808467 ps
CPU time 8.03 seconds
Started Jul 03 07:11:28 PM PDT 24
Finished Jul 03 07:12:03 PM PDT 24
Peak memory 225628 kb
Host smart-a04699cc-ff04-494e-9a17-9d9c8dbbdbf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719427982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.719427982
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.2725551036
Short name T435
Test name
Test status
Simulation time 27140224 ps
CPU time 1.71 seconds
Started Jul 03 07:11:26 PM PDT 24
Finished Jul 03 07:11:56 PM PDT 24
Peak memory 217152 kb
Host smart-0da05639-fbef-4929-a791-db0d4550d354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725551036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.2725551036
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.648822888
Short name T273
Test name
Test status
Simulation time 306857341 ps
CPU time 29.48 seconds
Started Jul 03 07:11:31 PM PDT 24
Finished Jul 03 07:12:28 PM PDT 24
Peak memory 250616 kb
Host smart-9679ca04-b0b4-4e12-ad81-45f860eb5ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648822888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.648822888
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.3281824415
Short name T759
Test name
Test status
Simulation time 68631797 ps
CPU time 6.68 seconds
Started Jul 03 07:11:25 PM PDT 24
Finished Jul 03 07:12:00 PM PDT 24
Peak memory 246676 kb
Host smart-d0325153-ac65-476b-bff1-06a3ed2ad9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281824415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.3281824415
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.792780115
Short name T590
Test name
Test status
Simulation time 477515263 ps
CPU time 8.95 seconds
Started Jul 03 07:11:27 PM PDT 24
Finished Jul 03 07:12:04 PM PDT 24
Peak memory 225920 kb
Host smart-d84e07c1-517f-4058-9c07-f141a4fb5aea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792780115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.792780115
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.3059226842
Short name T103
Test name
Test status
Simulation time 20849721 ps
CPU time 1.12 seconds
Started Jul 03 07:11:28 PM PDT 24
Finished Jul 03 07:11:57 PM PDT 24
Peak memory 211492 kb
Host smart-36787de0-0ae9-429d-a37a-b709b34274e1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059226842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.3059226842
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.774706508
Short name T196
Test name
Test status
Simulation time 20124418 ps
CPU time 0.93 seconds
Started Jul 03 07:11:40 PM PDT 24
Finished Jul 03 07:12:04 PM PDT 24
Peak memory 208480 kb
Host smart-114f4356-34d1-4148-8c56-7911dec6cf61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774706508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.774706508
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.2014287744
Short name T213
Test name
Test status
Simulation time 14050029 ps
CPU time 0.84 seconds
Started Jul 03 07:11:37 PM PDT 24
Finished Jul 03 07:12:02 PM PDT 24
Peak memory 208336 kb
Host smart-c425ead3-d0f6-458f-b4d1-d384698a71a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014287744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.2014287744
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.2536523614
Short name T747
Test name
Test status
Simulation time 1547148787 ps
CPU time 13.51 seconds
Started Jul 03 07:11:34 PM PDT 24
Finished Jul 03 07:12:13 PM PDT 24
Peak memory 217788 kb
Host smart-38337ea1-c5bd-443a-ad1a-e07ffdacc4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536523614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.2536523614
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.4114265640
Short name T417
Test name
Test status
Simulation time 432003111 ps
CPU time 1.73 seconds
Started Jul 03 07:11:41 PM PDT 24
Finished Jul 03 07:12:06 PM PDT 24
Peak memory 216676 kb
Host smart-41a32f03-476f-457d-baad-2b694510422a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114265640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.4114265640
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.6696527
Short name T542
Test name
Test status
Simulation time 9257515062 ps
CPU time 62.71 seconds
Started Jul 03 07:11:36 PM PDT 24
Finished Jul 03 07:13:03 PM PDT 24
Peak memory 219480 kb
Host smart-f6107c39-031b-4c5e-8b16-0709067c8550
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6696527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc
_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_error
s.6696527
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.3314545648
Short name T402
Test name
Test status
Simulation time 3270124357 ps
CPU time 17.27 seconds
Started Jul 03 07:11:41 PM PDT 24
Finished Jul 03 07:12:21 PM PDT 24
Peak memory 217336 kb
Host smart-89862c18-9d00-402d-be02-48ef4a6ec18b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314545648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.3
314545648
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.657932400
Short name T646
Test name
Test status
Simulation time 186337779 ps
CPU time 4.28 seconds
Started Jul 03 07:11:34 PM PDT 24
Finished Jul 03 07:12:04 PM PDT 24
Peak memory 217720 kb
Host smart-05dec479-e60a-4d12-a321-b04193599420
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657932400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_
prog_failure.657932400
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.1996960298
Short name T19
Test name
Test status
Simulation time 16052294102 ps
CPU time 15.75 seconds
Started Jul 03 07:11:37 PM PDT 24
Finished Jul 03 07:12:17 PM PDT 24
Peak memory 217224 kb
Host smart-56cd809d-060c-474d-8815-f582e2a2d11b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996960298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.1996960298
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.1125202189
Short name T643
Test name
Test status
Simulation time 5986752334 ps
CPU time 10 seconds
Started Jul 03 07:11:42 PM PDT 24
Finished Jul 03 07:12:14 PM PDT 24
Peak memory 217224 kb
Host smart-2aa40c00-82ca-4be5-89a3-dcbdf38cde8f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125202189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
1125202189
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.3518211539
Short name T654
Test name
Test status
Simulation time 9191709108 ps
CPU time 83.95 seconds
Started Jul 03 07:11:37 PM PDT 24
Finished Jul 03 07:13:25 PM PDT 24
Peak memory 282068 kb
Host smart-2ed64edf-8cb2-418b-b383-b618d83ed980
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518211539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.3518211539
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.2227951744
Short name T749
Test name
Test status
Simulation time 2164743801 ps
CPU time 18.47 seconds
Started Jul 03 07:11:33 PM PDT 24
Finished Jul 03 07:12:18 PM PDT 24
Peak memory 226064 kb
Host smart-9d9131db-0a20-4225-b8ad-bd185321bfdb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227951744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.2227951744
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.2929065690
Short name T812
Test name
Test status
Simulation time 196779699 ps
CPU time 3.05 seconds
Started Jul 03 07:11:33 PM PDT 24
Finished Jul 03 07:12:02 PM PDT 24
Peak memory 217792 kb
Host smart-68ef972e-102f-4742-b2a3-498308d6862d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929065690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.2929065690
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.812757436
Short name T628
Test name
Test status
Simulation time 206156845 ps
CPU time 7.36 seconds
Started Jul 03 07:11:34 PM PDT 24
Finished Jul 03 07:12:07 PM PDT 24
Peak memory 217216 kb
Host smart-e2830d47-0755-49a8-a08f-57098221645d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812757436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.812757436
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.1922776652
Short name T271
Test name
Test status
Simulation time 4334904967 ps
CPU time 13.1 seconds
Started Jul 03 07:11:34 PM PDT 24
Finished Jul 03 07:12:13 PM PDT 24
Peak memory 225628 kb
Host smart-bd31ea89-0995-4845-8fa7-0a0a8f7d9c47
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922776652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.1922776652
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.59646961
Short name T777
Test name
Test status
Simulation time 587354244 ps
CPU time 12.39 seconds
Started Jul 03 07:11:37 PM PDT 24
Finished Jul 03 07:12:14 PM PDT 24
Peak memory 225532 kb
Host smart-89495833-4e65-4501-8300-d8a20e95aac2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59646961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_dige
st.59646961
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.3772105541
Short name T275
Test name
Test status
Simulation time 882235711 ps
CPU time 7.36 seconds
Started Jul 03 07:11:37 PM PDT 24
Finished Jul 03 07:12:09 PM PDT 24
Peak memory 225528 kb
Host smart-9a344edb-da4c-40bf-a221-14c0add233dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772105541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.3
772105541
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.1538632436
Short name T610
Test name
Test status
Simulation time 456363354 ps
CPU time 10.82 seconds
Started Jul 03 07:11:32 PM PDT 24
Finished Jul 03 07:12:09 PM PDT 24
Peak memory 225164 kb
Host smart-ee0876ec-e37d-421d-9b19-4aea2bd3222e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538632436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.1538632436
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.1398862944
Short name T851
Test name
Test status
Simulation time 191021216 ps
CPU time 2.73 seconds
Started Jul 03 07:11:34 PM PDT 24
Finished Jul 03 07:12:02 PM PDT 24
Peak memory 217212 kb
Host smart-fbe02cc3-8b09-45d8-b6a7-8d979b2ef25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398862944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.1398862944
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.3538018273
Short name T110
Test name
Test status
Simulation time 275855524 ps
CPU time 26.23 seconds
Started Jul 03 07:11:30 PM PDT 24
Finished Jul 03 07:12:23 PM PDT 24
Peak memory 250628 kb
Host smart-8f397d49-b8de-4ab4-92ea-806823c33402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538018273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.3538018273
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.4273724643
Short name T282
Test name
Test status
Simulation time 71126964 ps
CPU time 8.18 seconds
Started Jul 03 07:11:31 PM PDT 24
Finished Jul 03 07:12:06 PM PDT 24
Peak memory 250548 kb
Host smart-29585bcb-d80e-48af-9c7e-89cd8e2f0ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273724643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.4273724643
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.1500689453
Short name T454
Test name
Test status
Simulation time 27090744027 ps
CPU time 468.51 seconds
Started Jul 03 07:11:35 PM PDT 24
Finished Jul 03 07:19:49 PM PDT 24
Peak memory 277504 kb
Host smart-392edbdf-7710-425e-b6f0-3777a0dcb24a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500689453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.1500689453
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.1133102831
Short name T489
Test name
Test status
Simulation time 20369920327 ps
CPU time 473.28 seconds
Started Jul 03 07:11:38 PM PDT 24
Finished Jul 03 07:19:55 PM PDT 24
Peak memory 496420 kb
Host smart-44d74755-eaba-4dd4-a065-db4af0774285
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1133102831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all_with_rand_reset.1133102831
Directory /workspace/9.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.4084900959
Short name T230
Test name
Test status
Simulation time 29735143 ps
CPU time 0.8 seconds
Started Jul 03 07:11:32 PM PDT 24
Finished Jul 03 07:11:59 PM PDT 24
Peak memory 208180 kb
Host smart-572aed81-b159-4a9e-8339-61d6ec36a499
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084900959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.4084900959
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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