Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54478 |
1 |
|
|
T3 |
14 |
|
T4 |
91 |
|
T5 |
15 |
auto[1] |
2063 |
1 |
|
|
T7 |
12 |
|
T19 |
18 |
|
T20 |
4 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55939 |
1 |
|
|
T3 |
14 |
|
T4 |
91 |
|
T5 |
15 |
auto[1] |
602 |
1 |
|
|
T11 |
14 |
|
T45 |
17 |
|
T54 |
20 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54604 |
1 |
|
|
T3 |
14 |
|
T4 |
91 |
|
T5 |
15 |
auto[1] |
1937 |
1 |
|
|
T17 |
7 |
|
T97 |
6 |
|
T19 |
9 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54519 |
1 |
|
|
T3 |
14 |
|
T4 |
91 |
|
T5 |
14 |
auto[1] |
2022 |
1 |
|
|
T5 |
1 |
|
T17 |
8 |
|
T48 |
1 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54532 |
1 |
|
|
T3 |
14 |
|
T4 |
91 |
|
T5 |
13 |
auto[1] |
2009 |
1 |
|
|
T5 |
2 |
|
T17 |
6 |
|
T97 |
8 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
51427 |
1 |
|
|
T4 |
91 |
|
T5 |
9 |
|
T11 |
69 |
no_err_inj |
5114 |
1 |
|
|
T3 |
14 |
|
T5 |
6 |
|
T13 |
7 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54395 |
1 |
|
|
T3 |
14 |
|
T4 |
91 |
|
T5 |
15 |
auto[1] |
2146 |
1 |
|
|
T7 |
12 |
|
T19 |
24 |
|
T20 |
8 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55959 |
1 |
|
|
T3 |
14 |
|
T4 |
91 |
|
T5 |
15 |
auto[1] |
582 |
1 |
|
|
T11 |
17 |
|
T45 |
17 |
|
T54 |
14 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39547 |
1 |
|
|
T4 |
91 |
|
T5 |
15 |
|
T11 |
69 |
auto[1] |
16994 |
1 |
|
|
T3 |
14 |
|
T6 |
5 |
|
T7 |
8 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54535 |
1 |
|
|
T3 |
14 |
|
T4 |
91 |
|
T5 |
13 |
auto[1] |
2006 |
1 |
|
|
T5 |
2 |
|
T17 |
4 |
|
T48 |
2 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54647 |
1 |
|
|
T3 |
14 |
|
T4 |
91 |
|
T5 |
14 |
auto[1] |
1894 |
1 |
|
|
T5 |
1 |
|
T17 |
1 |
|
T48 |
1 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54527 |
1 |
|
|
T3 |
14 |
|
T4 |
91 |
|
T5 |
14 |
auto[1] |
2014 |
1 |
|
|
T5 |
1 |
|
T17 |
4 |
|
T48 |
1 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54443 |
1 |
|
|
T3 |
14 |
|
T4 |
91 |
|
T5 |
15 |
auto[1] |
2098 |
1 |
|
|
T7 |
9 |
|
T19 |
22 |
|
T20 |
9 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54045 |
1 |
|
|
T3 |
14 |
|
T4 |
91 |
|
T5 |
15 |
auto[1] |
2496 |
1 |
|
|
T14 |
20 |
|
T15 |
5 |
|
T7 |
36 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55982 |
1 |
|
|
T3 |
14 |
|
T4 |
91 |
|
T5 |
15 |
auto[1] |
559 |
1 |
|
|
T11 |
11 |
|
T45 |
14 |
|
T54 |
11 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55939 |
1 |
|
|
T3 |
14 |
|
T4 |
91 |
|
T5 |
15 |
auto[1] |
602 |
1 |
|
|
T11 |
11 |
|
T45 |
20 |
|
T54 |
16 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55928 |
1 |
|
|
T3 |
14 |
|
T4 |
91 |
|
T5 |
15 |
auto[1] |
613 |
1 |
|
|
T11 |
16 |
|
T45 |
17 |
|
T54 |
18 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53652 |
1 |
|
|
T3 |
14 |
|
T4 |
91 |
|
T11 |
69 |
auto[1] |
2889 |
1 |
|
|
T5 |
15 |
|
T48 |
15 |
|
T19 |
15 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52750 |
1 |
|
|
T3 |
14 |
|
T4 |
91 |
|
T5 |
15 |
auto[1] |
3791 |
1 |
|
|
T16 |
100 |
|
T59 |
89 |
|
T33 |
87 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54576 |
1 |
|
|
T3 |
14 |
|
T4 |
91 |
|
T5 |
14 |
auto[1] |
1965 |
1 |
|
|
T5 |
1 |
|
T17 |
7 |
|
T48 |
1 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54641 |
1 |
|
|
T3 |
14 |
|
T4 |
91 |
|
T5 |
15 |
auto[1] |
1900 |
1 |
|
|
T17 |
8 |
|
T97 |
9 |
|
T19 |
10 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54592 |
1 |
|
|
T3 |
14 |
|
T4 |
91 |
|
T5 |
14 |
auto[1] |
1949 |
1 |
|
|
T5 |
1 |
|
T17 |
8 |
|
T48 |
3 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54333 |
1 |
|
|
T3 |
14 |
|
T4 |
91 |
|
T5 |
15 |
auto[1] |
2208 |
1 |
|
|
T7 |
10 |
|
T19 |
28 |
|
T20 |
16 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50681 |
1 |
|
|
T3 |
14 |
|
T5 |
15 |
|
T11 |
69 |
auto[1] |
5860 |
1 |
|
|
T4 |
91 |
|
T46 |
81 |
|
T7 |
8 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52863 |
1 |
|
|
T3 |
14 |
|
T4 |
91 |
|
T5 |
15 |
auto[1] |
3678 |
1 |
|
|
T58 |
92 |
|
T71 |
63 |
|
T72 |
89 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56541 |
1 |
|
|
T3 |
14 |
|
T4 |
91 |
|
T5 |
15 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54391 |
1 |
|
|
T3 |
14 |
|
T4 |
91 |
|
T5 |
15 |
auto[1] |
2150 |
1 |
|
|
T7 |
4 |
|
T19 |
23 |
|
T20 |
9 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54464 |
1 |
|
|
T3 |
14 |
|
T4 |
91 |
|
T5 |
15 |
auto[1] |
2077 |
1 |
|
|
T7 |
8 |
|
T19 |
31 |
|
T20 |
13 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54335 |
1 |
|
|
T3 |
14 |
|
T4 |
91 |
|
T5 |
15 |
auto[1] |
2206 |
1 |
|
|
T7 |
6 |
|
T19 |
20 |
|
T20 |
7 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
49991 |
1 |
|
|
T4 |
91 |
|
T11 |
69 |
|
T14 |
20 |
auto[0] |
no_err_inj |
3661 |
1 |
|
|
T3 |
14 |
|
T13 |
7 |
|
T6 |
5 |
auto[1] |
err_inj |
1436 |
1 |
|
|
T5 |
9 |
|
T48 |
9 |
|
T19 |
10 |
auto[1] |
no_err_inj |
1453 |
1 |
|
|
T5 |
6 |
|
T48 |
6 |
|
T19 |
5 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
51907 |
1 |
|
|
T3 |
14 |
|
T4 |
91 |
|
T11 |
69 |
auto[0] |
auto[1] |
1745 |
1 |
|
|
T17 |
8 |
|
T97 |
9 |
|
T19 |
10 |
auto[1] |
auto[0] |
2734 |
1 |
|
|
T5 |
15 |
|
T48 |
15 |
|
T19 |
15 |
auto[1] |
auto[1] |
155 |
1 |
|
|
T22 |
2 |
|
T68 |
3 |
|
T94 |
1 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
51915 |
1 |
|
|
T3 |
14 |
|
T4 |
91 |
|
T11 |
69 |
auto[0] |
auto[1] |
1737 |
1 |
|
|
T17 |
1 |
|
T97 |
4 |
|
T19 |
15 |
auto[1] |
auto[0] |
2732 |
1 |
|
|
T5 |
14 |
|
T48 |
14 |
|
T19 |
14 |
auto[1] |
auto[1] |
157 |
1 |
|
|
T5 |
1 |
|
T48 |
1 |
|
T19 |
1 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
51846 |
1 |
|
|
T3 |
14 |
|
T4 |
91 |
|
T11 |
69 |
auto[0] |
auto[1] |
1806 |
1 |
|
|
T17 |
8 |
|
T97 |
3 |
|
T19 |
15 |
auto[1] |
auto[0] |
2746 |
1 |
|
|
T5 |
14 |
|
T48 |
12 |
|
T19 |
15 |
auto[1] |
auto[1] |
143 |
1 |
|
|
T5 |
1 |
|
T48 |
3 |
|
T47 |
1 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
51792 |
1 |
|
|
T3 |
14 |
|
T4 |
91 |
|
T11 |
69 |
auto[0] |
auto[1] |
1860 |
1 |
|
|
T17 |
8 |
|
T97 |
6 |
|
T19 |
16 |
auto[1] |
auto[0] |
2727 |
1 |
|
|
T5 |
14 |
|
T48 |
14 |
|
T19 |
14 |
auto[1] |
auto[1] |
162 |
1 |
|
|
T5 |
1 |
|
T48 |
1 |
|
T19 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
51824 |
1 |
|
|
T3 |
14 |
|
T4 |
91 |
|
T11 |
69 |
auto[0] |
auto[1] |
1828 |
1 |
|
|
T17 |
6 |
|
T97 |
8 |
|
T19 |
12 |
auto[1] |
auto[0] |
2708 |
1 |
|
|
T5 |
13 |
|
T48 |
15 |
|
T19 |
14 |
auto[1] |
auto[1] |
181 |
1 |
|
|
T5 |
2 |
|
T19 |
1 |
|
T47 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
51876 |
1 |
|
|
T3 |
14 |
|
T4 |
91 |
|
T11 |
69 |
auto[0] |
auto[1] |
1776 |
1 |
|
|
T17 |
7 |
|
T97 |
6 |
|
T19 |
8 |
auto[1] |
auto[0] |
2728 |
1 |
|
|
T5 |
15 |
|
T48 |
15 |
|
T19 |
14 |
auto[1] |
auto[1] |
161 |
1 |
|
|
T19 |
1 |
|
T47 |
2 |
|
T21 |
3 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38379 |
1 |
|
|
T4 |
91 |
|
T5 |
15 |
|
T11 |
69 |
auto[0] |
auto[1] |
1168 |
1 |
|
|
T7 |
12 |
|
T19 |
18 |
|
T44 |
4 |
auto[1] |
auto[0] |
16099 |
1 |
|
|
T3 |
14 |
|
T6 |
5 |
|
T7 |
8 |
auto[1] |
auto[1] |
895 |
1 |
|
|
T20 |
4 |
|
T68 |
20 |
|
T100 |
21 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38326 |
1 |
|
|
T4 |
91 |
|
T5 |
15 |
|
T11 |
69 |
auto[0] |
auto[1] |
1221 |
1 |
|
|
T7 |
12 |
|
T19 |
24 |
|
T44 |
8 |
auto[1] |
auto[0] |
16069 |
1 |
|
|
T3 |
14 |
|
T6 |
5 |
|
T7 |
8 |
auto[1] |
auto[1] |
925 |
1 |
|
|
T20 |
8 |
|
T68 |
23 |
|
T100 |
9 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38060 |
1 |
|
|
T4 |
91 |
|
T5 |
15 |
|
T11 |
69 |
auto[0] |
auto[1] |
1487 |
1 |
|
|
T14 |
20 |
|
T15 |
5 |
|
T7 |
36 |
auto[1] |
auto[0] |
15985 |
1 |
|
|
T3 |
14 |
|
T6 |
5 |
|
T7 |
8 |
auto[1] |
auto[1] |
1009 |
1 |
|
|
T18 |
12 |
|
T68 |
10 |
|
T94 |
13 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38376 |
1 |
|
|
T4 |
91 |
|
T5 |
15 |
|
T11 |
69 |
auto[0] |
auto[1] |
1171 |
1 |
|
|
T7 |
9 |
|
T19 |
22 |
|
T44 |
7 |
auto[1] |
auto[0] |
16067 |
1 |
|
|
T3 |
14 |
|
T6 |
5 |
|
T7 |
8 |
auto[1] |
auto[1] |
927 |
1 |
|
|
T20 |
9 |
|
T68 |
15 |
|
T100 |
11 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34593 |
1 |
|
|
T5 |
15 |
|
T11 |
69 |
|
T13 |
7 |
auto[0] |
auto[1] |
4954 |
1 |
|
|
T4 |
91 |
|
T46 |
81 |
|
T7 |
8 |
auto[1] |
auto[0] |
16088 |
1 |
|
|
T3 |
14 |
|
T6 |
5 |
|
T7 |
8 |
auto[1] |
auto[1] |
906 |
1 |
|
|
T20 |
7 |
|
T68 |
30 |
|
T100 |
10 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38362 |
1 |
|
|
T4 |
91 |
|
T5 |
15 |
|
T11 |
69 |
auto[0] |
auto[1] |
1185 |
1 |
|
|
T17 |
8 |
|
T97 |
9 |
|
T19 |
2 |
auto[1] |
auto[0] |
16279 |
1 |
|
|
T3 |
14 |
|
T6 |
5 |
|
T7 |
8 |
auto[1] |
auto[1] |
715 |
1 |
|
|
T19 |
8 |
|
T22 |
2 |
|
T23 |
9 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38277 |
1 |
|
|
T4 |
91 |
|
T5 |
14 |
|
T11 |
69 |
auto[0] |
auto[1] |
1270 |
1 |
|
|
T5 |
1 |
|
T17 |
7 |
|
T48 |
1 |
auto[1] |
auto[0] |
16299 |
1 |
|
|
T3 |
14 |
|
T6 |
5 |
|
T7 |
8 |
auto[1] |
auto[1] |
695 |
1 |
|
|
T19 |
4 |
|
T22 |
1 |
|
T23 |
4 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38351 |
1 |
|
|
T4 |
91 |
|
T5 |
14 |
|
T11 |
69 |
auto[0] |
auto[1] |
1196 |
1 |
|
|
T5 |
1 |
|
T17 |
1 |
|
T48 |
1 |
auto[1] |
auto[0] |
16296 |
1 |
|
|
T3 |
14 |
|
T6 |
5 |
|
T7 |
8 |
auto[1] |
auto[1] |
698 |
1 |
|
|
T19 |
9 |
|
T23 |
5 |
|
T208 |
8 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38244 |
1 |
|
|
T4 |
91 |
|
T5 |
13 |
|
T11 |
69 |
auto[0] |
auto[1] |
1303 |
1 |
|
|
T5 |
2 |
|
T17 |
4 |
|
T48 |
2 |
auto[1] |
auto[0] |
16291 |
1 |
|
|
T3 |
14 |
|
T6 |
5 |
|
T7 |
8 |
auto[1] |
auto[1] |
703 |
1 |
|
|
T19 |
7 |
|
T21 |
3 |
|
T23 |
5 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38256 |
1 |
|
|
T4 |
91 |
|
T5 |
14 |
|
T11 |
69 |
auto[0] |
auto[1] |
1291 |
1 |
|
|
T5 |
1 |
|
T17 |
8 |
|
T48 |
1 |
auto[1] |
auto[0] |
16263 |
1 |
|
|
T3 |
14 |
|
T6 |
5 |
|
T7 |
8 |
auto[1] |
auto[1] |
731 |
1 |
|
|
T19 |
6 |
|
T23 |
9 |
|
T208 |
7 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38305 |
1 |
|
|
T4 |
91 |
|
T5 |
15 |
|
T11 |
69 |
auto[0] |
auto[1] |
1242 |
1 |
|
|
T17 |
7 |
|
T97 |
6 |
|
T19 |
5 |
auto[1] |
auto[0] |
16299 |
1 |
|
|
T3 |
14 |
|
T6 |
5 |
|
T7 |
8 |
auto[1] |
auto[1] |
695 |
1 |
|
|
T19 |
4 |
|
T21 |
2 |
|
T23 |
12 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38260 |
1 |
|
|
T4 |
91 |
|
T5 |
15 |
|
T11 |
69 |
auto[0] |
auto[1] |
1287 |
1 |
|
|
T7 |
6 |
|
T19 |
20 |
|
T44 |
7 |
auto[1] |
auto[0] |
16075 |
1 |
|
|
T3 |
14 |
|
T6 |
5 |
|
T7 |
8 |
auto[1] |
auto[1] |
919 |
1 |
|
|
T20 |
7 |
|
T68 |
16 |
|
T100 |
7 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38350 |
1 |
|
|
T4 |
91 |
|
T5 |
15 |
|
T11 |
69 |
auto[0] |
auto[1] |
1197 |
1 |
|
|
T7 |
8 |
|
T19 |
31 |
|
T44 |
5 |
auto[1] |
auto[0] |
16114 |
1 |
|
|
T3 |
14 |
|
T6 |
5 |
|
T7 |
8 |
auto[1] |
auto[1] |
880 |
1 |
|
|
T20 |
13 |
|
T68 |
25 |
|
T100 |
12 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37881 |
1 |
|
|
T4 |
91 |
|
T11 |
69 |
|
T13 |
7 |
auto[0] |
auto[1] |
1666 |
1 |
|
|
T5 |
15 |
|
T48 |
15 |
|
T19 |
15 |
auto[1] |
auto[0] |
15771 |
1 |
|
|
T3 |
14 |
|
T6 |
5 |
|
T7 |
8 |
auto[1] |
auto[1] |
1223 |
1 |
|
|
T21 |
11 |
|
T22 |
15 |
|
T209 |
14 |