Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

112536335

1

T1

1042

T2

1789

T3

19872

auto[1]

1442742

1

T5

495

T11

693

T14

1287

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

112541602

1

T1

1042

T2

1789

T3

19872

auto[1]

1437475

1

T5

198

T11

1782

T14

693

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7622138	1			T1	98		T2	66		T3	1525
auto[IdleSt]	24421371	1			T1	50		T2	52		T3	14365
auto[ClkMuxSt]	37885	1			T2	1		T3	14		T4	91
auto[CntIncrSt]	37572	1			T2	1		T3	14		T4	91
auto[CntProgSt]	1975862	1			T2	128		T3	28		T4	14895
auto[TransCheckSt]	29190	1			T2	1		T3	14		T4	91
auto[TokenHashSt]	46245575	1			T2	59		T3	851		T4	1918
auto[FlashRmaSt]	37240	1			T2	1		T3	26		T5	48
auto[TokenCheck0St]	13143	1			T2	1		T3	14		T5	6
auto[TokenCheck1St]	9697	1			T2	1		T3	14		T5	6
auto[TransProgSt]	532168	1			T2	583		T3	28		T5	131
auto[PostTransSt]	14787602	1			T1	894		T2	895		T3	2979
auto[ScrapSt]	125239	1			T16	9		T19	904		T24	319
auto[EscalateSt]	6934394	1			T5	2012		T11	3528		T14	2741
auto[InvalidSt]	11168034	1			T5	1095		T11	1576		T17	7901

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1967	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	11168034	1			T5	1095		T11	1576		T17	7901
EscalateSt	6934394	1			T5	2012		T11	3528		T14	2741
ScrapSt	125239	1			T16	9		T19	904		T24	319
PostTransSt	14787602	1			T1	894		T2	895		T3	2979
TransProgSt	532168	1			T2	583		T3	28		T5	131
TokenCheck1St	9697	1			T2	1		T3	14		T5	6
TokenCheck0St	13143	1			T2	1		T3	14		T5	6
FlashRmaSt	37240	1			T2	1		T3	26		T5	48
TokenHashSt	46245575	1			T2	59		T3	851		T4	1918
TransCheckSt	29190	1			T2	1		T3	14		T4	91
CntProgSt	1975862	1			T2	128		T3	28		T4	14895
CntIncrSt	37572	1			T2	1		T3	14		T4	91
ClkMuxSt	37885	1			T2	1		T3	14		T4	91
IdleSt	24421371	1			T1	50		T2	52		T3	14365
ResetSt	7622138	1			T1	98		T2	66		T3	1525
arcs[ResetSt=>IdleSt]	56760	1			T1	1		T2	1		T3	14
arcs[IdleSt=>ScrapSt]	290	1			T16	3		T19	2		T24	1
arcs[IdleSt=>ClkMuxSt]	37649	1			T2	1		T3	14		T4	91
arcs[ClkMuxSt=>CntIncrSt]	37572	1			T2	1		T3	14		T4	91
arcs[CntIncrSt=>PostTransSt]	2078	1			T7	8		T19	31		T20	13
arcs[CntIncrSt=>CntProgSt]	35425	1			T2	1		T3	14		T4	91
arcs[CntProgSt=>PostTransSt]	5145	1			T11	14		T14	20		T15	5
arcs[CntProgSt=>TransCheckSt]	29190	1			T2	1		T3	14		T4	91
arcs[TransCheckSt=>PostTransSt]	4012	1			T7	6		T19	20		T20	7
arcs[TransCheckSt=>TokenHashSt]	25053	1			T2	1		T3	14		T4	91
arcs[TokenHashSt=>PostTransSt]	11111	1			T4	91		T11	7		T46	81
arcs[TokenHashSt=>FlashRmaSt]	13242	1			T2	1		T3	14		T5	6
arcs[FlashRmaSt=>TokenCheck0St]	13143	1			T2	1		T3	14		T5	6
arcs[TokenCheck0St=>PostTransSt]	3419	1			T11	14		T7	9		T19	21
arcs[TokenCheck0St=>TokenCheck1St]	9697	1			T2	1		T3	14		T5	6
arcs[TokenCheck1St=>PostTransSt]	647	1			T7	3		T19	3		T58	6
arcs[TransProgSt=>PostTransSt]	8180	1			T2	1		T3	14		T5	6
arcs[IdleSt=>EscalateSt]	203	1			T16	6		T59	7		T33	5
arcs[ClkMuxSt=>EscalateSt]	77	1			T16	3		T59	4		T40	1
arcs[CntIncrSt=>EscalateSt]	69	1			T16	2		T59	2		T33	1
arcs[CntProgSt=>EscalateSt]	1090	1			T16	38		T59	37		T33	28
arcs[TransCheckSt=>EscalateSt]	125	1			T60	10		T65	6		T66	6
arcs[TokenHashSt=>EscalateSt]	700	1			T16	8		T59	12		T64	2
arcs[FlashRmaSt=>EscalateSt]	99	1			T16	1		T40	1		T60	4
arcs[TokenCheck0St=>EscalateSt]	27	1			T16	2		T33	1		T60	1
arcs[TokenCheck1St=>EscalateSt]	143	1			T16	5		T59	1		T33	5
arcs[TransProgSt=>EscalateSt]	727	1			T16	24		T59	16		T33	24
arcs[PostTransSt=>EscalateSt]	5373	1			T11	14		T14	20		T15	5
arcs[InvalidSt=>EscalateSt]	14349	1			T5	7		T11	11		T17	41

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7621962	1			T1	98		T2	66		T3	1525
auto[0]	auto[IdleSt]	24421229	1			T1	50		T2	52		T3	14365
auto[0]	auto[ClkMuxSt]	37826	1			T2	1		T3	14		T4	91
auto[0]	auto[CntIncrSt]	37526	1			T2	1		T3	14		T4	91
auto[0]	auto[CntProgSt]	1975121	1			T2	128		T3	28		T4	14895
auto[0]	auto[TransCheckSt]	29108	1			T2	1		T3	14		T4	91
auto[0]	auto[TokenHashSt]	46245095	1			T2	59		T3	851		T4	1918
auto[0]	auto[FlashRmaSt]	37175	1			T2	1		T3	26		T5	48
auto[0]	auto[TokenCheck0St]	13130	1			T2	1		T3	14		T5	6
auto[0]	auto[TokenCheck1St]	9602	1			T2	1		T3	14		T5	6
auto[0]	auto[TransProgSt]	531697	1			T2	583		T3	28		T5	131
auto[0]	auto[PostTransSt]	14784881	1			T1	894		T2	895		T3	2979
auto[0]	auto[ScrapSt]	125207	1			T16	8		T19	904		T24	319
auto[0]	auto[EscalateSt]	5503911	1			T5	1522		T11	2842		T14	1467
auto[0]	auto[InvalidSt]	11160898	1			T5	1090		T11	1572		T17	7887
auto[1]	auto[ResetSt]	176	1			T16	3		T59	4		T33	4
auto[1]	auto[IdleSt]	142	1			T16	3		T59	4		T242	4
auto[1]	auto[ClkMuxSt]	59	1			T16	3		T59	4		T40	1
auto[1]	auto[CntIncrSt]	46	1			T16	2		T59	1		T40	2
auto[1]	auto[CntProgSt]	741	1			T16	24		T59	24		T33	19
auto[1]	auto[TransCheckSt]	82	1			T60	7		T65	5		T66	6
auto[1]	auto[TokenHashSt]	480	1			T16	5		T59	9		T64	1
auto[1]	auto[FlashRmaSt]	65	1			T40	1		T60	3		T243	1
auto[1]	auto[TokenCheck0St]	13	1			T33	1		T60	1		T179	1
auto[1]	auto[TokenCheck1St]	95	1			T16	5		T59	1		T33	5
auto[1]	auto[TransProgSt]	471	1			T16	16		T59	13		T33	16
auto[1]	auto[PostTransSt]	2721	1			T11	3		T14	13		T15	2
auto[1]	auto[ScrapSt]	32	1			T16	1		T59	1		T33	1
auto[1]	auto[EscalateSt]	1430483	1			T5	490		T11	686		T14	1274
auto[1]	auto[InvalidSt]	7136	1			T5	5		T11	4		T17	14

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7621963	1			T1	98		T2	66		T3	1525
auto[0]	auto[IdleSt]	24421243	1			T1	50		T2	52		T3	14365
auto[0]	auto[ClkMuxSt]	37836	1			T2	1		T3	14		T4	91
auto[0]	auto[CntIncrSt]	37527	1			T2	1		T3	14		T4	91
auto[0]	auto[CntProgSt]	1975150	1			T2	128		T3	28		T4	14895
auto[0]	auto[TransCheckSt]	29106	1			T2	1		T3	14		T4	91
auto[0]	auto[TokenHashSt]	46245110	1			T2	59		T3	851		T4	1918
auto[0]	auto[FlashRmaSt]	37166	1			T2	1		T3	26		T5	48
auto[0]	auto[TokenCheck0St]	13124	1			T2	1		T3	14		T5	6
auto[0]	auto[TokenCheck1St]	9607	1			T2	1		T3	14		T5	6
auto[0]	auto[TransProgSt]	531697	1			T2	583		T3	28		T5	131
auto[0]	auto[PostTransSt]	14784875	1			T1	894		T2	895		T3	2979
auto[0]	auto[ScrapSt]	125194	1			T16	7		T19	904		T24	319
auto[0]	auto[EscalateSt]	5509216	1			T5	1816		T11	1764		T14	2055
auto[0]	auto[InvalidSt]	11160821	1			T5	1093		T11	1569		T17	7874
auto[1]	auto[ResetSt]	175	1			T16	5		T59	3		T33	4
auto[1]	auto[IdleSt]	128	1			T16	5		T59	4		T33	5
auto[1]	auto[ClkMuxSt]	49	1			T16	2		T59	2		T40	1
auto[1]	auto[CntIncrSt]	45	1			T59	2		T33	1		T40	2
auto[1]	auto[CntProgSt]	712	1			T16	25		T59	28		T33	16
auto[1]	auto[TransCheckSt]	84	1			T60	5		T65	2		T66	3
auto[1]	auto[TokenHashSt]	465	1			T16	4		T59	8		T64	1
auto[1]	auto[FlashRmaSt]	74	1			T16	1		T60	4		T243	2
auto[1]	auto[TokenCheck0St]	19	1			T16	2		T244	1		T200	1
auto[1]	auto[TokenCheck1St]	90	1			T16	1		T59	1		T33	1
auto[1]	auto[TransProgSt]	471	1			T16	16		T59	9		T33	18
auto[1]	auto[PostTransSt]	2727	1			T11	11		T14	7		T15	3
auto[1]	auto[ScrapSt]	45	1			T16	2		T59	1		T40	1
auto[1]	auto[EscalateSt]	1425178	1			T5	196		T11	1764		T14	686
auto[1]	auto[InvalidSt]	7213	1			T5	2		T11	7		T17	27