Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.36 97.99 96.13 93.38 100.00 98.55 99.00 96.47


Total test records in report: 995
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
T814 /workspace/coverage/default/11.lc_ctrl_jtag_smoke.421017897 Jul 04 07:12:42 PM PDT 24 Jul 04 07:13:14 PM PDT 24 1232601047 ps
T815 /workspace/coverage/default/46.lc_ctrl_alert_test.4014734031 Jul 04 07:14:54 PM PDT 24 Jul 04 07:14:59 PM PDT 24 13186884 ps
T816 /workspace/coverage/default/22.lc_ctrl_sec_token_mux.2294327579 Jul 04 07:13:39 PM PDT 24 Jul 04 07:14:12 PM PDT 24 1040761604 ps
T817 /workspace/coverage/default/48.lc_ctrl_stress_all.3626689750 Jul 04 07:14:55 PM PDT 24 Jul 04 07:21:58 PM PDT 24 28580105443 ps
T818 /workspace/coverage/default/21.lc_ctrl_jtag_access.2518586123 Jul 04 07:13:33 PM PDT 24 Jul 04 07:14:05 PM PDT 24 723929403 ps
T819 /workspace/coverage/default/12.lc_ctrl_state_post_trans.2484164514 Jul 04 07:12:48 PM PDT 24 Jul 04 07:13:26 PM PDT 24 612361917 ps
T820 /workspace/coverage/default/47.lc_ctrl_state_failure.4284032272 Jul 04 07:14:52 PM PDT 24 Jul 04 07:15:21 PM PDT 24 1135708397 ps
T821 /workspace/coverage/default/9.lc_ctrl_smoke.1668882154 Jul 04 07:12:36 PM PDT 24 Jul 04 07:13:03 PM PDT 24 149523192 ps
T822 /workspace/coverage/default/36.lc_ctrl_state_post_trans.3900865322 Jul 04 07:14:38 PM PDT 24 Jul 04 07:14:41 PM PDT 24 125776467 ps
T823 /workspace/coverage/default/41.lc_ctrl_smoke.2314369880 Jul 04 07:14:50 PM PDT 24 Jul 04 07:14:54 PM PDT 24 65506506 ps
T824 /workspace/coverage/default/48.lc_ctrl_alert_test.3318502421 Jul 04 07:14:58 PM PDT 24 Jul 04 07:15:00 PM PDT 24 27501726 ps
T825 /workspace/coverage/default/6.lc_ctrl_alert_test.2478098346 Jul 04 07:12:31 PM PDT 24 Jul 04 07:12:50 PM PDT 24 38852616 ps
T826 /workspace/coverage/default/40.lc_ctrl_sec_token_digest.3548337084 Jul 04 07:14:47 PM PDT 24 Jul 04 07:14:56 PM PDT 24 907139849 ps
T827 /workspace/coverage/default/36.lc_ctrl_state_failure.1047913729 Jul 04 07:14:30 PM PDT 24 Jul 04 07:14:52 PM PDT 24 359616784 ps
T175 /workspace/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.2945818031 Jul 04 07:13:49 PM PDT 24 Jul 04 07:30:13 PM PDT 24 750306023656 ps
T828 /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.2282233613 Jul 04 07:14:29 PM PDT 24 Jul 04 07:14:31 PM PDT 24 40354073 ps
T829 /workspace/coverage/default/43.lc_ctrl_errors.1176106833 Jul 04 07:14:50 PM PDT 24 Jul 04 07:15:00 PM PDT 24 228179968 ps
T830 /workspace/coverage/default/0.lc_ctrl_sec_token_digest.1353620598 Jul 04 07:12:06 PM PDT 24 Jul 04 07:12:16 PM PDT 24 228507264 ps
T831 /workspace/coverage/default/18.lc_ctrl_sec_mubi.3327381386 Jul 04 07:13:20 PM PDT 24 Jul 04 07:14:04 PM PDT 24 1303588390 ps
T832 /workspace/coverage/default/24.lc_ctrl_jtag_access.4291559998 Jul 04 07:13:52 PM PDT 24 Jul 04 07:14:15 PM PDT 24 259619920 ps
T833 /workspace/coverage/default/46.lc_ctrl_stress_all.342277432 Jul 04 07:14:59 PM PDT 24 Jul 04 07:16:15 PM PDT 24 3093674240 ps
T834 /workspace/coverage/default/14.lc_ctrl_sec_token_mux.1629789927 Jul 04 07:13:01 PM PDT 24 Jul 04 07:13:38 PM PDT 24 353512844 ps
T835 /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.108880404 Jul 04 07:14:31 PM PDT 24 Jul 04 07:14:33 PM PDT 24 16852954 ps
T836 /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.2501916162 Jul 04 07:13:15 PM PDT 24 Jul 04 07:13:50 PM PDT 24 50494895 ps
T837 /workspace/coverage/default/9.lc_ctrl_jtag_access.582484776 Jul 04 07:12:36 PM PDT 24 Jul 04 07:13:04 PM PDT 24 212482002 ps
T838 /workspace/coverage/default/14.lc_ctrl_smoke.1957153963 Jul 04 07:12:55 PM PDT 24 Jul 04 07:13:26 PM PDT 24 221699088 ps
T839 /workspace/coverage/default/16.lc_ctrl_jtag_access.3926696099 Jul 04 07:13:08 PM PDT 24 Jul 04 07:13:48 PM PDT 24 1559942475 ps
T840 /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.1956679140 Jul 04 07:12:30 PM PDT 24 Jul 04 07:12:57 PM PDT 24 938805366 ps
T841 /workspace/coverage/default/34.lc_ctrl_alert_test.3141388935 Jul 04 07:14:22 PM PDT 24 Jul 04 07:14:24 PM PDT 24 21677429 ps
T842 /workspace/coverage/default/15.lc_ctrl_smoke.2148040785 Jul 04 07:13:01 PM PDT 24 Jul 04 07:13:31 PM PDT 24 45544322 ps
T843 /workspace/coverage/default/26.lc_ctrl_stress_all.1358023560 Jul 04 07:13:58 PM PDT 24 Jul 04 07:20:06 PM PDT 24 9158150457 ps
T844 /workspace/coverage/default/0.lc_ctrl_state_failure.110623766 Jul 04 07:12:04 PM PDT 24 Jul 04 07:12:35 PM PDT 24 4979360644 ps
T845 /workspace/coverage/default/40.lc_ctrl_alert_test.638790688 Jul 04 07:14:46 PM PDT 24 Jul 04 07:14:47 PM PDT 24 53112284 ps
T846 /workspace/coverage/default/40.lc_ctrl_security_escalation.2134257140 Jul 04 07:14:55 PM PDT 24 Jul 04 07:15:06 PM PDT 24 1221436629 ps
T847 /workspace/coverage/default/45.lc_ctrl_smoke.503967999 Jul 04 07:14:53 PM PDT 24 Jul 04 07:15:00 PM PDT 24 247384315 ps
T848 /workspace/coverage/default/1.lc_ctrl_jtag_errors.405743472 Jul 04 07:12:10 PM PDT 24 Jul 04 07:12:40 PM PDT 24 6014776770 ps
T849 /workspace/coverage/default/18.lc_ctrl_sec_token_mux.441199912 Jul 04 07:13:20 PM PDT 24 Jul 04 07:14:04 PM PDT 24 1050442089 ps
T850 /workspace/coverage/default/41.lc_ctrl_stress_all.1927699304 Jul 04 07:14:54 PM PDT 24 Jul 04 07:15:29 PM PDT 24 3946407894 ps
T851 /workspace/coverage/default/5.lc_ctrl_prog_failure.1769667228 Jul 04 07:12:25 PM PDT 24 Jul 04 07:12:39 PM PDT 24 123829151 ps
T852 /workspace/coverage/default/36.lc_ctrl_sec_token_digest.2263731230 Jul 04 07:14:30 PM PDT 24 Jul 04 07:14:41 PM PDT 24 231634619 ps
T853 /workspace/coverage/default/38.lc_ctrl_smoke.4137340379 Jul 04 07:14:40 PM PDT 24 Jul 04 07:14:43 PM PDT 24 27693769 ps
T854 /workspace/coverage/default/42.lc_ctrl_state_post_trans.2568459531 Jul 04 07:14:48 PM PDT 24 Jul 04 07:14:57 PM PDT 24 73225957 ps
T855 /workspace/coverage/default/24.lc_ctrl_state_post_trans.3445276760 Jul 04 07:13:51 PM PDT 24 Jul 04 07:14:16 PM PDT 24 267931274 ps
T856 /workspace/coverage/default/12.lc_ctrl_stress_all.4019130628 Jul 04 07:12:49 PM PDT 24 Jul 04 07:19:48 PM PDT 24 11504864623 ps
T857 /workspace/coverage/default/30.lc_ctrl_sec_token_digest.969641149 Jul 04 07:14:15 PM PDT 24 Jul 04 07:14:29 PM PDT 24 265022279 ps
T858 /workspace/coverage/default/31.lc_ctrl_prog_failure.2686782496 Jul 04 07:14:10 PM PDT 24 Jul 04 07:14:15 PM PDT 24 65138372 ps
T859 /workspace/coverage/default/10.lc_ctrl_sec_token_digest.1324072008 Jul 04 07:12:40 PM PDT 24 Jul 04 07:13:22 PM PDT 24 1448017404 ps
T860 /workspace/coverage/default/3.lc_ctrl_stress_all.1546415812 Jul 04 07:12:16 PM PDT 24 Jul 04 07:13:51 PM PDT 24 8314537317 ps
T176 /workspace/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.3553828416 Jul 04 07:12:50 PM PDT 24 Jul 04 07:16:54 PM PDT 24 9333314287 ps
T861 /workspace/coverage/default/40.lc_ctrl_stress_all.597238900 Jul 04 07:14:50 PM PDT 24 Jul 04 07:16:37 PM PDT 24 18172952768 ps
T862 /workspace/coverage/default/17.lc_ctrl_security_escalation.565629532 Jul 04 07:13:15 PM PDT 24 Jul 04 07:13:57 PM PDT 24 321428769 ps
T863 /workspace/coverage/default/24.lc_ctrl_stress_all.3345538464 Jul 04 07:13:48 PM PDT 24 Jul 04 07:18:43 PM PDT 24 8242142983 ps
T864 /workspace/coverage/default/26.lc_ctrl_errors.3957844972 Jul 04 07:13:59 PM PDT 24 Jul 04 07:14:24 PM PDT 24 1302090209 ps
T865 /workspace/coverage/default/49.lc_ctrl_stress_all.4002352069 Jul 04 07:14:59 PM PDT 24 Jul 04 07:15:54 PM PDT 24 4606982115 ps
T866 /workspace/coverage/default/28.lc_ctrl_smoke.10837074 Jul 04 07:14:02 PM PDT 24 Jul 04 07:14:14 PM PDT 24 259550682 ps
T84 /workspace/coverage/default/11.lc_ctrl_alert_test.2266871686 Jul 04 07:12:49 PM PDT 24 Jul 04 07:13:18 PM PDT 24 70057055 ps
T867 /workspace/coverage/default/5.lc_ctrl_state_post_trans.4201901403 Jul 04 07:12:23 PM PDT 24 Jul 04 07:12:38 PM PDT 24 490968261 ps
T868 /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.1585493800 Jul 04 07:12:37 PM PDT 24 Jul 04 07:14:31 PM PDT 24 11863190855 ps
T869 /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.2885990945 Jul 04 07:12:16 PM PDT 24 Jul 04 07:12:20 PM PDT 24 137664308 ps
T870 /workspace/coverage/default/47.lc_ctrl_sec_mubi.3810719932 Jul 04 07:14:57 PM PDT 24 Jul 04 07:15:13 PM PDT 24 2141392146 ps
T142 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1077581905 Jul 04 07:11:34 PM PDT 24 Jul 04 07:11:35 PM PDT 24 13314380 ps
T135 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.583077745 Jul 04 07:12:05 PM PDT 24 Jul 04 07:12:07 PM PDT 24 55069180 ps
T132 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2649532030 Jul 04 07:11:48 PM PDT 24 Jul 04 07:11:52 PM PDT 24 468417613 ps
T136 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3673975748 Jul 04 07:11:57 PM PDT 24 Jul 04 07:11:59 PM PDT 24 41707086 ps
T138 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.1240421132 Jul 04 07:11:56 PM PDT 24 Jul 04 07:11:58 PM PDT 24 70558827 ps
T168 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2945828490 Jul 04 07:11:42 PM PDT 24 Jul 04 07:11:45 PM PDT 24 587501768 ps
T133 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.4149343858 Jul 04 07:11:23 PM PDT 24 Jul 04 07:11:27 PM PDT 24 89387572 ps
T134 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2006277352 Jul 04 07:11:57 PM PDT 24 Jul 04 07:12:00 PM PDT 24 250813405 ps
T177 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.305529105 Jul 04 07:12:03 PM PDT 24 Jul 04 07:12:05 PM PDT 24 58119104 ps
T154 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.2299557473 Jul 04 07:11:32 PM PDT 24 Jul 04 07:11:33 PM PDT 24 266356103 ps
T178 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3173068784 Jul 04 07:11:18 PM PDT 24 Jul 04 07:11:22 PM PDT 24 96629087 ps
T169 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.24550516 Jul 04 07:11:35 PM PDT 24 Jul 04 07:11:42 PM PDT 24 264458040 ps
T141 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.94314506 Jul 04 07:11:48 PM PDT 24 Jul 04 07:11:52 PM PDT 24 222043659 ps
T235 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3774842060 Jul 04 07:11:24 PM PDT 24 Jul 04 07:11:30 PM PDT 24 1676471339 ps
T149 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2614850578 Jul 04 07:11:51 PM PDT 24 Jul 04 07:11:53 PM PDT 24 249135918 ps
T871 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1915374384 Jul 04 07:11:20 PM PDT 24 Jul 04 07:11:21 PM PDT 24 40585621 ps
T139 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3373145178 Jul 04 07:11:56 PM PDT 24 Jul 04 07:11:58 PM PDT 24 113786449 ps
T872 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1695556689 Jul 04 07:11:21 PM PDT 24 Jul 04 07:11:23 PM PDT 24 97181840 ps
T873 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1474340763 Jul 04 07:11:19 PM PDT 24 Jul 04 07:11:22 PM PDT 24 1488547560 ps
T874 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.976874104 Jul 04 07:11:37 PM PDT 24 Jul 04 07:11:38 PM PDT 24 95608414 ps
T875 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2763247940 Jul 04 07:11:34 PM PDT 24 Jul 04 07:11:35 PM PDT 24 15251816 ps
T214 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2695996079 Jul 04 07:11:23 PM PDT 24 Jul 04 07:11:24 PM PDT 24 413943525 ps
T153 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2914890994 Jul 04 07:11:23 PM PDT 24 Jul 04 07:11:25 PM PDT 24 311647971 ps
T876 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3414161164 Jul 04 07:11:48 PM PDT 24 Jul 04 07:11:49 PM PDT 24 26385732 ps
T215 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.944828961 Jul 04 07:11:58 PM PDT 24 Jul 04 07:12:00 PM PDT 24 81203568 ps
T167 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3063275952 Jul 04 07:11:49 PM PDT 24 Jul 04 07:12:00 PM PDT 24 880543927 ps
T150 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2200020370 Jul 04 07:11:38 PM PDT 24 Jul 04 07:11:40 PM PDT 24 27356838 ps
T877 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.10498449 Jul 04 07:11:20 PM PDT 24 Jul 04 07:11:22 PM PDT 24 976882414 ps
T226 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2870587133 Jul 04 07:11:56 PM PDT 24 Jul 04 07:11:58 PM PDT 24 78825576 ps
T878 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.105205880 Jul 04 07:11:48 PM PDT 24 Jul 04 07:11:51 PM PDT 24 197549856 ps
T160 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3600960378 Jul 04 07:11:16 PM PDT 24 Jul 04 07:11:23 PM PDT 24 947311373 ps
T879 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3938192860 Jul 04 07:11:24 PM PDT 24 Jul 04 07:11:31 PM PDT 24 302844839 ps
T137 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1602587082 Jul 04 07:11:49 PM PDT 24 Jul 04 07:11:51 PM PDT 24 175756116 ps
T880 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.331472647 Jul 04 07:11:17 PM PDT 24 Jul 04 07:11:44 PM PDT 24 5103542139 ps
T881 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1189944552 Jul 04 07:11:43 PM PDT 24 Jul 04 07:11:45 PM PDT 24 39698474 ps
T882 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3797380027 Jul 04 07:11:44 PM PDT 24 Jul 04 07:11:46 PM PDT 24 72109555 ps
T151 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3104863732 Jul 04 07:11:57 PM PDT 24 Jul 04 07:12:00 PM PDT 24 38453948 ps
T883 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3619196346 Jul 04 07:11:56 PM PDT 24 Jul 04 07:11:57 PM PDT 24 79893869 ps
T884 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2500451881 Jul 04 07:11:24 PM PDT 24 Jul 04 07:11:25 PM PDT 24 61352158 ps
T145 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2037558350 Jul 04 07:11:27 PM PDT 24 Jul 04 07:11:29 PM PDT 24 103287329 ps
T143 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.4142288849 Jul 04 07:11:50 PM PDT 24 Jul 04 07:11:55 PM PDT 24 338811190 ps
T216 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1966571766 Jul 04 07:12:03 PM PDT 24 Jul 04 07:12:04 PM PDT 24 12159291 ps
T227 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.874451668 Jul 04 07:11:28 PM PDT 24 Jul 04 07:11:29 PM PDT 24 96954153 ps
T885 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.4050148773 Jul 04 07:11:31 PM PDT 24 Jul 04 07:11:32 PM PDT 24 14934236 ps
T228 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3568389696 Jul 04 07:11:20 PM PDT 24 Jul 04 07:11:22 PM PDT 24 87424850 ps
T886 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3911457255 Jul 04 07:11:35 PM PDT 24 Jul 04 07:11:46 PM PDT 24 4701625173 ps
T887 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.295873444 Jul 04 07:11:18 PM PDT 24 Jul 04 07:11:19 PM PDT 24 81607864 ps
T229 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3085688734 Jul 04 07:11:19 PM PDT 24 Jul 04 07:11:21 PM PDT 24 27409522 ps
T217 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.673914651 Jul 04 07:11:18 PM PDT 24 Jul 04 07:11:19 PM PDT 24 24514309 ps
T230 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.184598703 Jul 04 07:11:36 PM PDT 24 Jul 04 07:11:38 PM PDT 24 77295095 ps
T888 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.500089336 Jul 04 07:11:53 PM PDT 24 Jul 04 07:11:54 PM PDT 24 240072779 ps
T146 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.2302581307 Jul 04 07:12:02 PM PDT 24 Jul 04 07:12:05 PM PDT 24 38570742 ps
T152 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1350063233 Jul 04 07:12:04 PM PDT 24 Jul 04 07:12:08 PM PDT 24 314690792 ps
T889 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1500249793 Jul 04 07:11:44 PM PDT 24 Jul 04 07:11:51 PM PDT 24 1396693569 ps
T231 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.72760335 Jul 04 07:11:57 PM PDT 24 Jul 04 07:11:58 PM PDT 24 90158493 ps
T890 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.378024428 Jul 04 07:11:50 PM PDT 24 Jul 04 07:11:52 PM PDT 24 23507940 ps
T891 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.139708595 Jul 04 07:11:58 PM PDT 24 Jul 04 07:12:01 PM PDT 24 20457549 ps
T892 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2999352107 Jul 04 07:11:29 PM PDT 24 Jul 04 07:11:51 PM PDT 24 2069935020 ps
T232 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1576745509 Jul 04 07:11:30 PM PDT 24 Jul 04 07:11:32 PM PDT 24 38835039 ps
T893 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.3684204070 Jul 04 07:11:27 PM PDT 24 Jul 04 07:11:28 PM PDT 24 41778916 ps
T894 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.3329302762 Jul 04 07:11:58 PM PDT 24 Jul 04 07:12:00 PM PDT 24 15134692 ps
T895 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.134318426 Jul 04 07:11:28 PM PDT 24 Jul 04 07:11:29 PM PDT 24 20907478 ps
T896 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3577313068 Jul 04 07:11:09 PM PDT 24 Jul 04 07:11:19 PM PDT 24 3460052110 ps
T897 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2154816823 Jul 04 07:11:22 PM PDT 24 Jul 04 07:11:23 PM PDT 24 54262168 ps
T898 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.149501656 Jul 04 07:11:59 PM PDT 24 Jul 04 07:12:01 PM PDT 24 41538042 ps
T899 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2237678251 Jul 04 07:12:00 PM PDT 24 Jul 04 07:12:01 PM PDT 24 18747968 ps
T165 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2682915698 Jul 04 07:11:58 PM PDT 24 Jul 04 07:12:01 PM PDT 24 68729748 ps
T900 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1681714947 Jul 04 07:11:54 PM PDT 24 Jul 04 07:11:55 PM PDT 24 55482043 ps
T901 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.3987799863 Jul 04 07:11:35 PM PDT 24 Jul 04 07:11:37 PM PDT 24 198838479 ps
T902 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2857292505 Jul 04 07:11:18 PM PDT 24 Jul 04 07:11:19 PM PDT 24 39927617 ps
T148 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.951046361 Jul 04 07:11:16 PM PDT 24 Jul 04 07:11:18 PM PDT 24 886667529 ps
T147 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.505024398 Jul 04 07:12:07 PM PDT 24 Jul 04 07:12:10 PM PDT 24 64125938 ps
T903 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.200913228 Jul 04 07:11:27 PM PDT 24 Jul 04 07:11:30 PM PDT 24 162921224 ps
T904 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2952825376 Jul 04 07:11:24 PM PDT 24 Jul 04 07:11:26 PM PDT 24 49339457 ps
T218 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3170899567 Jul 04 07:11:17 PM PDT 24 Jul 04 07:11:18 PM PDT 24 44511459 ps
T905 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2193519876 Jul 04 07:11:24 PM PDT 24 Jul 04 07:11:32 PM PDT 24 587418894 ps
T906 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3773370398 Jul 04 07:11:58 PM PDT 24 Jul 04 07:12:00 PM PDT 24 238258945 ps
T907 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2500173508 Jul 04 07:11:23 PM PDT 24 Jul 04 07:11:25 PM PDT 24 102326558 ps
T908 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.491430570 Jul 04 07:11:57 PM PDT 24 Jul 04 07:11:59 PM PDT 24 48066208 ps
T157 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1367675182 Jul 04 07:11:49 PM PDT 24 Jul 04 07:11:51 PM PDT 24 246917401 ps
T909 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2008865825 Jul 04 07:11:48 PM PDT 24 Jul 04 07:11:51 PM PDT 24 86052563 ps
T910 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.243385781 Jul 04 07:11:48 PM PDT 24 Jul 04 07:12:06 PM PDT 24 18561054247 ps
T911 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1549519969 Jul 04 07:11:16 PM PDT 24 Jul 04 07:11:18 PM PDT 24 19098242 ps
T912 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2667965393 Jul 04 07:11:14 PM PDT 24 Jul 04 07:11:15 PM PDT 24 66951253 ps
T913 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.851034139 Jul 04 07:11:30 PM PDT 24 Jul 04 07:11:32 PM PDT 24 142408731 ps
T914 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1183384565 Jul 04 07:11:34 PM PDT 24 Jul 04 07:11:37 PM PDT 24 1184925608 ps
T161 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2248962653 Jul 04 07:11:59 PM PDT 24 Jul 04 07:12:02 PM PDT 24 354127859 ps
T915 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1076944981 Jul 04 07:11:51 PM PDT 24 Jul 04 07:11:52 PM PDT 24 136159551 ps
T158 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2449392550 Jul 04 07:12:03 PM PDT 24 Jul 04 07:12:05 PM PDT 24 262611649 ps
T916 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3312086711 Jul 04 07:11:24 PM PDT 24 Jul 04 07:11:26 PM PDT 24 103337183 ps
T917 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.56907747 Jul 04 07:11:11 PM PDT 24 Jul 04 07:11:14 PM PDT 24 81233492 ps
T219 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2262577530 Jul 04 07:11:17 PM PDT 24 Jul 04 07:11:18 PM PDT 24 18420803 ps
T918 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2707034267 Jul 04 07:11:49 PM PDT 24 Jul 04 07:11:52 PM PDT 24 75130063 ps
T919 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3191756662 Jul 04 07:12:03 PM PDT 24 Jul 04 07:12:05 PM PDT 24 105514340 ps
T920 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2143170504 Jul 04 07:11:59 PM PDT 24 Jul 04 07:12:02 PM PDT 24 418352487 ps
T921 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2574197824 Jul 04 07:11:24 PM PDT 24 Jul 04 07:11:25 PM PDT 24 34884559 ps
T922 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1252309921 Jul 04 07:11:09 PM PDT 24 Jul 04 07:11:11 PM PDT 24 513231140 ps
T923 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1065677001 Jul 04 07:11:19 PM PDT 24 Jul 04 07:11:20 PM PDT 24 42954119 ps
T924 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1485743250 Jul 04 07:11:50 PM PDT 24 Jul 04 07:11:56 PM PDT 24 3081399965 ps
T144 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1104181113 Jul 04 07:11:58 PM PDT 24 Jul 04 07:12:02 PM PDT 24 225328370 ps
T925 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2861258066 Jul 04 07:11:58 PM PDT 24 Jul 04 07:11:59 PM PDT 24 116645668 ps
T926 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2724012219 Jul 04 07:11:58 PM PDT 24 Jul 04 07:12:00 PM PDT 24 26585541 ps
T927 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3822440773 Jul 04 07:11:49 PM PDT 24 Jul 04 07:11:56 PM PDT 24 527068678 ps
T928 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3742045935 Jul 04 07:11:16 PM PDT 24 Jul 04 07:11:18 PM PDT 24 76635035 ps
T929 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1461640705 Jul 04 07:11:16 PM PDT 24 Jul 04 07:11:18 PM PDT 24 411159843 ps
T930 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.275596880 Jul 04 07:11:24 PM PDT 24 Jul 04 07:11:25 PM PDT 24 57188507 ps
T931 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1159620735 Jul 04 07:11:57 PM PDT 24 Jul 04 07:11:59 PM PDT 24 49457782 ps
T932 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3010863998 Jul 04 07:11:17 PM PDT 24 Jul 04 07:11:23 PM PDT 24 509028223 ps
T933 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.646545562 Jul 04 07:11:48 PM PDT 24 Jul 04 07:11:51 PM PDT 24 236379121 ps
T934 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3021062 Jul 04 07:11:37 PM PDT 24 Jul 04 07:11:39 PM PDT 24 91141831 ps
T220 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1589770340 Jul 04 07:12:05 PM PDT 24 Jul 04 07:12:08 PM PDT 24 46150185 ps
T935 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.65235611 Jul 04 07:11:57 PM PDT 24 Jul 04 07:11:58 PM PDT 24 99057120 ps
T936 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1986430022 Jul 04 07:11:18 PM PDT 24 Jul 04 07:11:21 PM PDT 24 897540929 ps
T937 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2696552471 Jul 04 07:11:49 PM PDT 24 Jul 04 07:11:51 PM PDT 24 975344212 ps
T938 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3902516562 Jul 04 07:11:10 PM PDT 24 Jul 04 07:11:12 PM PDT 24 46043199 ps
T939 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3889468059 Jul 04 07:11:18 PM PDT 24 Jul 04 07:11:27 PM PDT 24 3631909944 ps
T940 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.84474290 Jul 04 07:12:02 PM PDT 24 Jul 04 07:12:07 PM PDT 24 124161126 ps
T941 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.247133718 Jul 04 07:11:52 PM PDT 24 Jul 04 07:11:55 PM PDT 24 48155039 ps
T942 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.1568905382 Jul 04 07:11:36 PM PDT 24 Jul 04 07:11:38 PM PDT 24 50229125 ps
T943 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1696346546 Jul 04 07:11:46 PM PDT 24 Jul 04 07:11:47 PM PDT 24 131528923 ps
T221 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.4248715925 Jul 04 07:11:49 PM PDT 24 Jul 04 07:11:50 PM PDT 24 37287390 ps
T944 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1552055683 Jul 04 07:11:34 PM PDT 24 Jul 04 07:11:36 PM PDT 24 636818061 ps
T945 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2430463833 Jul 04 07:11:46 PM PDT 24 Jul 04 07:11:48 PM PDT 24 23159742 ps
T946 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2470986287 Jul 04 07:11:35 PM PDT 24 Jul 04 07:11:37 PM PDT 24 100867527 ps
T222 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3017587097 Jul 04 07:12:03 PM PDT 24 Jul 04 07:12:05 PM PDT 24 11167514 ps
T947 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3294839811 Jul 04 07:12:04 PM PDT 24 Jul 04 07:12:06 PM PDT 24 21290511 ps
T159 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.1682615581 Jul 04 07:11:58 PM PDT 24 Jul 04 07:12:01 PM PDT 24 70734586 ps
T948 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.1549372825 Jul 04 07:12:05 PM PDT 24 Jul 04 07:12:07 PM PDT 24 130888485 ps
T166 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.339496827 Jul 04 07:11:42 PM PDT 24 Jul 04 07:11:44 PM PDT 24 313219730 ps
T949 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3180901738 Jul 04 07:11:55 PM PDT 24 Jul 04 07:11:56 PM PDT 24 55851340 ps
T950 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1383499298 Jul 04 07:11:47 PM PDT 24 Jul 04 07:11:49 PM PDT 24 172836919 ps
T140 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2461222977 Jul 04 07:11:24 PM PDT 24 Jul 04 07:11:27 PM PDT 24 105940056 ps
T951 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.711045667 Jul 04 07:11:52 PM PDT 24 Jul 04 07:11:56 PM PDT 24 1575581877 ps
T163 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2809562677 Jul 04 07:11:56 PM PDT 24 Jul 04 07:11:59 PM PDT 24 227293160 ps
T952 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3012369019 Jul 04 07:11:48 PM PDT 24 Jul 04 07:12:05 PM PDT 24 4437911806 ps
T953 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3728625822 Jul 04 07:11:58 PM PDT 24 Jul 04 07:12:02 PM PDT 24 123129104 ps
T954 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2323406833 Jul 04 07:11:45 PM PDT 24 Jul 04 07:11:47 PM PDT 24 234389372 ps
T955 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1202804541 Jul 04 07:11:26 PM PDT 24 Jul 04 07:11:28 PM PDT 24 74676337 ps
T956 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2952928869 Jul 04 07:11:33 PM PDT 24 Jul 04 07:11:35 PM PDT 24 51933210 ps
T162 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2997118844 Jul 04 07:12:03 PM PDT 24 Jul 04 07:12:06 PM PDT 24 727586095 ps
T957 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.3144986639 Jul 04 07:11:30 PM PDT 24 Jul 04 07:11:32 PM PDT 24 63617362 ps
T958 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1183914365 Jul 04 07:11:32 PM PDT 24 Jul 04 07:11:34 PM PDT 24 254851253 ps
T959 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.619559265 Jul 04 07:11:38 PM PDT 24 Jul 04 07:11:40 PM PDT 24 21975255 ps
T960 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.48718587 Jul 04 07:11:58 PM PDT 24 Jul 04 07:12:00 PM PDT 24 299502746 ps
T961 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2873265923 Jul 04 07:11:16 PM PDT 24 Jul 04 07:11:18 PM PDT 24 74892616 ps
T156 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.419449089 Jul 04 07:11:17 PM PDT 24 Jul 04 07:11:19 PM PDT 24 1217851758 ps
T962 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3407614412 Jul 04 07:11:58 PM PDT 24 Jul 04 07:11:59 PM PDT 24 18485771 ps
T164 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2717755618 Jul 04 07:11:25 PM PDT 24 Jul 04 07:11:27 PM PDT 24 80752619 ps
T963 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2512738836 Jul 04 07:11:33 PM PDT 24 Jul 04 07:11:35 PM PDT 24 80297289 ps
T964 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3926864749 Jul 04 07:11:17 PM PDT 24 Jul 04 07:11:19 PM PDT 24 25539835 ps
T965 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1480255987 Jul 04 07:11:09 PM PDT 24 Jul 04 07:11:11 PM PDT 24 175267094 ps
T966 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3466552103 Jul 04 07:11:50 PM PDT 24 Jul 04 07:11:52 PM PDT 24 137660174 ps
T967 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.339290317 Jul 04 07:11:24 PM PDT 24 Jul 04 07:11:25 PM PDT 24 130520773 ps
T968 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3083176708 Jul 04 07:11:16 PM PDT 24 Jul 04 07:11:17 PM PDT 24 145732997 ps
T969 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3096467447 Jul 04 07:11:15 PM PDT 24 Jul 04 07:11:17 PM PDT 24 49605111 ps
T970 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.664244203 Jul 04 07:11:19 PM PDT 24 Jul 04 07:11:27 PM PDT 24 766263641 ps
T971 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2904433533 Jul 04 07:11:57 PM PDT 24 Jul 04 07:11:59 PM PDT 24 22055499 ps
T972 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.4264061311 Jul 04 07:11:17 PM PDT 24 Jul 04 07:11:21 PM PDT 24 456662538 ps
T973 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.479930228 Jul 04 07:11:42 PM PDT 24 Jul 04 07:11:43 PM PDT 24 25471636 ps
T974 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.803319852 Jul 04 07:11:31 PM PDT 24 Jul 04 07:11:32 PM PDT 24 20803352 ps
T975 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1130153976 Jul 04 07:11:57 PM PDT 24 Jul 04 07:12:00 PM PDT 24 30036775 ps
T976 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.354667287 Jul 04 07:11:58 PM PDT 24 Jul 04 07:12:00 PM PDT 24 16569597 ps
T977 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1672195100 Jul 04 07:11:30 PM PDT 24 Jul 04 07:11:32 PM PDT 24 32743787 ps
T978 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2293337447 Jul 04 07:11:31 PM PDT 24 Jul 04 07:11:36 PM PDT 24 433423645 ps
T979 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1994979633 Jul 04 07:11:36 PM PDT 24 Jul 04 07:11:39 PM PDT 24 240594370 ps
T223 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2508395408 Jul 04 07:11:56 PM PDT 24 Jul 04 07:11:57 PM PDT 24 31469065 ps
T980 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3181813848 Jul 04 07:11:48 PM PDT 24 Jul 04 07:11:52 PM PDT 24 139526185 ps
T981 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3370980579 Jul 04 07:11:53 PM PDT 24 Jul 04 07:11:55 PM PDT 24 57710589 ps
T982 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3797845502 Jul 04 07:11:57 PM PDT 24 Jul 04 07:11:59 PM PDT 24 29007517 ps
T983 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1359142434 Jul 04 07:11:14 PM PDT 24 Jul 04 07:11:16 PM PDT 24 98329386 ps
T984 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4049446796 Jul 04 07:11:37 PM PDT 24 Jul 04 07:11:42 PM PDT 24 208108988 ps
T985 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3494772534 Jul 04 07:11:28 PM PDT 24 Jul 04 07:11:31 PM PDT 24 53922659 ps
T986 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.2384054493 Jul 04 07:11:45 PM PDT 24 Jul 04 07:11:47 PM PDT 24 101310719 ps
T155 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1023283394 Jul 04 07:11:31 PM PDT 24 Jul 04 07:11:36 PM PDT 24 165294148 ps
T224 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.295068567 Jul 04 07:11:36 PM PDT 24 Jul 04 07:11:37 PM PDT 24 60974035 ps
T987 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.407415894 Jul 04 07:11:40 PM PDT 24 Jul 04 07:12:02 PM PDT 24 1661655641 ps
T225 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2892800463 Jul 04 07:11:56 PM PDT 24 Jul 04 07:11:57 PM PDT 24 19781638 ps
T988 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2694371220 Jul 04 07:12:06 PM PDT 24 Jul 04 07:12:09 PM PDT 24 21454209 ps
T989 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.168827245 Jul 04 07:11:29 PM PDT 24 Jul 04 07:11:31 PM PDT 24 45668481 ps
T990 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2841936768 Jul 04 07:11:57 PM PDT 24 Jul 04 07:11:58 PM PDT 24 76747355 ps
T991 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.111020699 Jul 04 07:11:55 PM PDT 24 Jul 04 07:11:57 PM PDT 24 20860173 ps
T992 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2808245468 Jul 04 07:11:30 PM PDT 24 Jul 04 07:11:42 PM PDT 24 2642473866 ps
T993 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2879812324 Jul 04 07:11:10 PM PDT 24 Jul 04 07:11:16 PM PDT 24 2722406346 ps
T994 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.4104814655 Jul 04 07:11:51 PM PDT 24 Jul 04 07:11:54 PM PDT 24 80350866 ps
T995 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3992771335 Jul 04 07:11:56 PM PDT 24 Jul 04 07:11:57 PM PDT 24 20053009 ps

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.867297836
Short name T11
Test name
Test status
Simulation time 934199620 ps
CPU time 19.45 seconds
Started Jul 04 07:14:40 PM PDT 24
Finished Jul 04 07:15:00 PM PDT 24
Peak memory 218436 kb
Host smart-2a3927be-f20f-4ba2-b965-572122771781
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867297836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.867297836
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.3360812147
Short name T19
Test name
Test status
Simulation time 58475221274 ps
CPU time 446.24 seconds
Started Jul 04 07:13:58 PM PDT 24
Finished Jul 04 07:21:35 PM PDT 24
Peak memory 272636 kb
Host smart-52fd2bab-81f6-40d1-b384-c97a43e1496b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360812147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.3360812147
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.1393973404
Short name T16
Test name
Test status
Simulation time 6183062900 ps
CPU time 12.77 seconds
Started Jul 04 07:12:36 PM PDT 24
Finished Jul 04 07:13:14 PM PDT 24
Peak memory 217936 kb
Host smart-c90f0568-b315-4c22-a028-efa73edb099d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393973404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.1393973404
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.1678678550
Short name T68
Test name
Test status
Simulation time 28290824056 ps
CPU time 2266.16 seconds
Started Jul 04 07:15:00 PM PDT 24
Finished Jul 04 07:52:47 PM PDT 24
Peak memory 1517796 kb
Host smart-bd00bc85-1a22-46a5-aca4-69fe10f3a74e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1678678550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all_with_rand_reset.1678678550
Directory /workspace/49.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.94314506
Short name T141
Test name
Test status
Simulation time 222043659 ps
CPU time 3.57 seconds
Started Jul 04 07:11:48 PM PDT 24
Finished Jul 04 07:11:52 PM PDT 24
Peak memory 218736 kb
Host smart-1cbe8b0c-764d-417f-a72b-42320d22a50a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943145
06 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.94314506
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3465462729
Short name T2
Test name
Test status
Simulation time 18852160 ps
CPU time 1.27 seconds
Started Jul 04 07:13:42 PM PDT 24
Finished Jul 04 07:14:07 PM PDT 24
Peak memory 217224 kb
Host smart-fa5202e3-d13b-48dd-9c91-5a50a0139abe
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465462729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.3465462729
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.457140808
Short name T179
Test name
Test status
Simulation time 424984472 ps
CPU time 11.09 seconds
Started Jul 04 07:14:49 PM PDT 24
Finished Jul 04 07:15:02 PM PDT 24
Peak memory 217768 kb
Host smart-3c875ee7-22ce-49dc-8ffc-89c8c52e79f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457140808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.457140808
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.2289173580
Short name T50
Test name
Test status
Simulation time 39281977 ps
CPU time 0.91 seconds
Started Jul 04 07:14:50 PM PDT 24
Finished Jul 04 07:14:53 PM PDT 24
Peak memory 208428 kb
Host smart-ac3ca160-4a55-4fec-abbb-61bb19c8b6b1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289173580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.2289173580
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.370796994
Short name T61
Test name
Test status
Simulation time 121811025 ps
CPU time 23.39 seconds
Started Jul 04 07:12:08 PM PDT 24
Finished Jul 04 07:12:33 PM PDT 24
Peak memory 284052 kb
Host smart-7ec00761-4372-4924-a3a3-c8390e1d87d9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370796994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.370796994
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2649532030
Short name T132
Test name
Test status
Simulation time 468417613 ps
CPU time 2.87 seconds
Started Jul 04 07:11:48 PM PDT 24
Finished Jul 04 07:11:52 PM PDT 24
Peak memory 222068 kb
Host smart-ef4e6bbd-f5ce-4f35-9295-9f1e469d7fa4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649532030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.2649532030
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.2216087908
Short name T27
Test name
Test status
Simulation time 490095922 ps
CPU time 4.92 seconds
Started Jul 04 07:12:41 PM PDT 24
Finished Jul 04 07:13:14 PM PDT 24
Peak memory 217204 kb
Host smart-fe97ce73-9681-445c-8caa-bde7a6623663
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216087908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.2216087908
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.3063055346
Short name T57
Test name
Test status
Simulation time 189975615114 ps
CPU time 1014.44 seconds
Started Jul 04 07:14:47 PM PDT 24
Finished Jul 04 07:31:44 PM PDT 24
Peak memory 356220 kb
Host smart-1f2194b6-e237-405e-9348-3c07226badaf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3063055346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all_with_rand_reset.3063055346
Directory /workspace/40.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.3151894173
Short name T25
Test name
Test status
Simulation time 17910401 ps
CPU time 1.09 seconds
Started Jul 04 07:12:21 PM PDT 24
Finished Jul 04 07:12:32 PM PDT 24
Peak memory 208612 kb
Host smart-921a4e68-ebda-427b-88e5-afc6b6f76a69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151894173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.3151894173
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.121851752
Short name T260
Test name
Test status
Simulation time 1403862559 ps
CPU time 11.29 seconds
Started Jul 04 07:12:08 PM PDT 24
Finished Jul 04 07:12:21 PM PDT 24
Peak memory 217700 kb
Host smart-0b60a7b2-8f71-44ab-a592-1b9e74b1f112
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121851752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.121851752
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2262577530
Short name T219
Test name
Test status
Simulation time 18420803 ps
CPU time 1.35 seconds
Started Jul 04 07:11:17 PM PDT 24
Finished Jul 04 07:11:18 PM PDT 24
Peak memory 217484 kb
Host smart-0a8ba252-65f7-4a2f-b7a0-370f6debd537
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262577530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.2262577530
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.926367846
Short name T6
Test name
Test status
Simulation time 843447618 ps
CPU time 22.92 seconds
Started Jul 04 07:12:34 PM PDT 24
Finished Jul 04 07:13:20 PM PDT 24
Peak memory 217136 kb
Host smart-f04598ea-ccb5-4c92-95ad-93ef6a14dbdc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926367846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_j
tag_regwen_during_op.926367846
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.583077745
Short name T135
Test name
Test status
Simulation time 55069180 ps
CPU time 1.69 seconds
Started Jul 04 07:12:05 PM PDT 24
Finished Jul 04 07:12:07 PM PDT 24
Peak memory 217472 kb
Host smart-25560d4f-771a-4a8b-8935-fc167f522cb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583077745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.583077745
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1350063233
Short name T152
Test name
Test status
Simulation time 314690792 ps
CPU time 3.22 seconds
Started Jul 04 07:12:04 PM PDT 24
Finished Jul 04 07:12:08 PM PDT 24
Peak memory 222476 kb
Host smart-88d22d98-fad9-435c-b593-0cfa4b26da15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350063233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.1350063233
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.1618668147
Short name T243
Test name
Test status
Simulation time 1800216134 ps
CPU time 6.52 seconds
Started Jul 04 07:13:03 PM PDT 24
Finished Jul 04 07:13:38 PM PDT 24
Peak memory 224060 kb
Host smart-58d69f43-b2b2-431c-8984-5d76192699ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618668147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.1618668147
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2449392550
Short name T158
Test name
Test status
Simulation time 262611649 ps
CPU time 1.88 seconds
Started Jul 04 07:12:03 PM PDT 24
Finished Jul 04 07:12:05 PM PDT 24
Peak memory 222044 kb
Host smart-9b0ec95a-c46d-4cc2-a9d5-2259128d2df7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449392550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.2449392550
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.2159644152
Short name T45
Test name
Test status
Simulation time 296507480 ps
CPU time 12.03 seconds
Started Jul 04 07:14:34 PM PDT 24
Finished Jul 04 07:14:46 PM PDT 24
Peak memory 225164 kb
Host smart-57bae5e8-05d4-4db4-9715-b8295d93c6fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159644152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.2159644152
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.953087596
Short name T53
Test name
Test status
Simulation time 6328461861 ps
CPU time 29.16 seconds
Started Jul 04 07:12:42 PM PDT 24
Finished Jul 04 07:13:39 PM PDT 24
Peak memory 218432 kb
Host smart-cf441ffa-6af2-4906-8902-ed70b157c424
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953087596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_er
rors.953087596
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.1715153764
Short name T48
Test name
Test status
Simulation time 86551804 ps
CPU time 6.29 seconds
Started Jul 04 07:13:22 PM PDT 24
Finished Jul 04 07:14:02 PM PDT 24
Peak memory 246820 kb
Host smart-3a38ecda-1e24-4bfc-9853-c9d62b922d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715153764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.1715153764
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3010863998
Short name T932
Test name
Test status
Simulation time 509028223 ps
CPU time 5.81 seconds
Started Jul 04 07:11:17 PM PDT 24
Finished Jul 04 07:11:23 PM PDT 24
Peak memory 217516 kb
Host smart-ac01b0cb-e71b-4d17-8269-c53298a60d8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010863998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.3010863998
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2717755618
Short name T164
Test name
Test status
Simulation time 80752619 ps
CPU time 2.41 seconds
Started Jul 04 07:11:25 PM PDT 24
Finished Jul 04 07:11:27 PM PDT 24
Peak memory 221944 kb
Host smart-870346d8-3ae9-42f8-884d-c7bd7645b686
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717755618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.2717755618
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3085688734
Short name T229
Test name
Test status
Simulation time 27409522 ps
CPU time 1.1 seconds
Started Jul 04 07:11:19 PM PDT 24
Finished Jul 04 07:11:21 PM PDT 24
Peak memory 217464 kb
Host smart-b641b053-ccf2-4f53-8323-46164863216e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085688734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.3085688734
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.600255941
Short name T104
Test name
Test status
Simulation time 20801324787 ps
CPU time 388.62 seconds
Started Jul 04 07:14:09 PM PDT 24
Finished Jul 04 07:20:40 PM PDT 24
Peak memory 276436 kb
Host smart-d2f6e5ac-5df2-48a4-9687-ee4925d6032b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=600255941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all_with_rand_reset.600255941
Directory /workspace/28.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.2953679805
Short name T113
Test name
Test status
Simulation time 14672636179 ps
CPU time 540.53 seconds
Started Jul 04 07:12:35 PM PDT 24
Finished Jul 04 07:22:01 PM PDT 24
Peak memory 381068 kb
Host smart-f5d13405-1ca5-4199-950f-d72bd7faa29a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2953679805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all_with_rand_reset.2953679805
Directory /workspace/7.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1104181113
Short name T144
Test name
Test status
Simulation time 225328370 ps
CPU time 4.35 seconds
Started Jul 04 07:11:58 PM PDT 24
Finished Jul 04 07:12:02 PM PDT 24
Peak memory 217608 kb
Host smart-0048b2ed-aa0a-4cd6-9978-ff6814cb7971
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104181113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.1104181113
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2461222977
Short name T140
Test name
Test status
Simulation time 105940056 ps
CPU time 2.88 seconds
Started Jul 04 07:11:24 PM PDT 24
Finished Jul 04 07:11:27 PM PDT 24
Peak memory 222324 kb
Host smart-e3b4ccc3-09b8-46d1-a075-954a8ba27f43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461222977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.2461222977
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.150938326
Short name T241
Test name
Test status
Simulation time 35118531 ps
CPU time 0.82 seconds
Started Jul 04 07:12:05 PM PDT 24
Finished Jul 04 07:12:06 PM PDT 24
Peak memory 208532 kb
Host smart-b5360b0a-5fb8-49b2-89d2-269ed3e0125b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150938326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.150938326
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.366342609
Short name T239
Test name
Test status
Simulation time 34565229 ps
CPU time 0.9 seconds
Started Jul 04 07:12:03 PM PDT 24
Finished Jul 04 07:12:05 PM PDT 24
Peak memory 208392 kb
Host smart-d5c0d408-bc95-4156-93fa-53ec6a94327d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366342609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.366342609
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.969298537
Short name T240
Test name
Test status
Simulation time 11069962 ps
CPU time 1.02 seconds
Started Jul 04 07:12:25 PM PDT 24
Finished Jul 04 07:12:40 PM PDT 24
Peak memory 208424 kb
Host smart-c7d95066-10bb-40d0-b336-73a67f6bda9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969298537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.969298537
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.3570834522
Short name T237
Test name
Test status
Simulation time 21090164 ps
CPU time 0.93 seconds
Started Jul 04 07:12:25 PM PDT 24
Finished Jul 04 07:12:40 PM PDT 24
Peak memory 208428 kb
Host smart-3bc4dce1-9eca-4a1d-bb92-ddd807c8db34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570834522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.3570834522
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.4198386341
Short name T236
Test name
Test status
Simulation time 14196041 ps
CPU time 0.81 seconds
Started Jul 04 07:12:31 PM PDT 24
Finished Jul 04 07:12:50 PM PDT 24
Peak memory 208188 kb
Host smart-20512605-31d4-4839-8130-52346bc651a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198386341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.4198386341
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.1827273568
Short name T4
Test name
Test status
Simulation time 2183861934 ps
CPU time 19.96 seconds
Started Jul 04 07:12:36 PM PDT 24
Finished Jul 04 07:13:21 PM PDT 24
Peak memory 225560 kb
Host smart-c74341b7-49fa-4eec-9d1c-e2703525dc90
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827273568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.1827273568
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.951046361
Short name T148
Test name
Test status
Simulation time 886667529 ps
CPU time 2.47 seconds
Started Jul 04 07:11:16 PM PDT 24
Finished Jul 04 07:11:18 PM PDT 24
Peak memory 217496 kb
Host smart-c6c244f5-5f97-4cfd-9423-32f0c9df69c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951046361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_e
rr.951046361
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.419449089
Short name T156
Test name
Test status
Simulation time 1217851758 ps
CPU time 2.75 seconds
Started Jul 04 07:11:17 PM PDT 24
Finished Jul 04 07:11:19 PM PDT 24
Peak memory 222340 kb
Host smart-95538f6e-fe8f-4faf-a4c7-010c31eee62a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419449089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_e
rr.419449089
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2997118844
Short name T162
Test name
Test status
Simulation time 727586095 ps
CPU time 3.53 seconds
Started Jul 04 07:12:03 PM PDT 24
Finished Jul 04 07:12:06 PM PDT 24
Peak memory 217552 kb
Host smart-e3b43934-0f8d-4180-81ad-0ab7997de487
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997118844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.2997118844
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1023283394
Short name T155
Test name
Test status
Simulation time 165294148 ps
CPU time 4.91 seconds
Started Jul 04 07:11:31 PM PDT 24
Finished Jul 04 07:11:36 PM PDT 24
Peak memory 217500 kb
Host smart-c6615ab3-cf8a-459f-9b7b-d16570df71f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023283394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.1023283394
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1602587082
Short name T137
Test name
Test status
Simulation time 175756116 ps
CPU time 2.25 seconds
Started Jul 04 07:11:49 PM PDT 24
Finished Jul 04 07:11:51 PM PDT 24
Peak memory 222048 kb
Host smart-8d02467a-6825-42bd-8772-b520c0f20ae0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602587082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.1602587082
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1367675182
Short name T157
Test name
Test status
Simulation time 246917401 ps
CPU time 1.84 seconds
Started Jul 04 07:11:49 PM PDT 24
Finished Jul 04 07:11:51 PM PDT 24
Peak memory 221884 kb
Host smart-bbc5afcd-8f09-4dd1-8e37-2f5a490c4e4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367675182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.1367675182
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.3275576898
Short name T14
Test name
Test status
Simulation time 98705770 ps
CPU time 3.49 seconds
Started Jul 04 07:12:05 PM PDT 24
Finished Jul 04 07:12:11 PM PDT 24
Peak memory 217700 kb
Host smart-6dcd0d83-4964-4569-9491-7cf3a3bfffc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275576898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.3275576898
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.401025382
Short name T18
Test name
Test status
Simulation time 371924789 ps
CPU time 6.12 seconds
Started Jul 04 07:13:10 PM PDT 24
Finished Jul 04 07:13:47 PM PDT 24
Peak memory 222592 kb
Host smart-e760eaa8-b5a9-4a29-92e6-6cb82834bcba
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401025382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag
_prog_failure.401025382
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3173068784
Short name T178
Test name
Test status
Simulation time 96629087 ps
CPU time 3.19 seconds
Started Jul 04 07:11:18 PM PDT 24
Finished Jul 04 07:11:22 PM PDT 24
Peak memory 209252 kb
Host smart-99baee10-a271-417f-a8a5-b92f4dd85080
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173068784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.3173068784
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1065677001
Short name T923
Test name
Test status
Simulation time 42954119 ps
CPU time 1.06 seconds
Started Jul 04 07:11:19 PM PDT 24
Finished Jul 04 07:11:20 PM PDT 24
Peak memory 210028 kb
Host smart-b2f42422-5cf4-44c6-8c66-3fca25703ba6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065677001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.1065677001
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.295873444
Short name T887
Test name
Test status
Simulation time 81607864 ps
CPU time 1.26 seconds
Started Jul 04 07:11:18 PM PDT 24
Finished Jul 04 07:11:19 PM PDT 24
Peak memory 224692 kb
Host smart-486a0c14-ab3a-4d37-86e1-e9feaae6e8f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295873444 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.295873444
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3083176708
Short name T968
Test name
Test status
Simulation time 145732997 ps
CPU time 0.85 seconds
Started Jul 04 07:11:16 PM PDT 24
Finished Jul 04 07:11:17 PM PDT 24
Peak memory 209092 kb
Host smart-8d5411cb-fa4d-4914-85b8-335d5c9aae00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083176708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.3083176708
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3902516562
Short name T938
Test name
Test status
Simulation time 46043199 ps
CPU time 1.13 seconds
Started Jul 04 07:11:10 PM PDT 24
Finished Jul 04 07:11:12 PM PDT 24
Peak memory 209140 kb
Host smart-199f76b4-fe29-485d-9f76-ad04b449cd06
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902516562 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.3902516562
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2879812324
Short name T993
Test name
Test status
Simulation time 2722406346 ps
CPU time 5.57 seconds
Started Jul 04 07:11:10 PM PDT 24
Finished Jul 04 07:11:16 PM PDT 24
Peak memory 209216 kb
Host smart-5cdcf7b8-0f70-432e-a466-533b3aec4963
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879812324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.2879812324
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3577313068
Short name T896
Test name
Test status
Simulation time 3460052110 ps
CPU time 9.92 seconds
Started Jul 04 07:11:09 PM PDT 24
Finished Jul 04 07:11:19 PM PDT 24
Peak memory 209248 kb
Host smart-1e49d116-867b-4832-b067-aec158a8e697
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577313068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.3577313068
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.56907747
Short name T917
Test name
Test status
Simulation time 81233492 ps
CPU time 2.53 seconds
Started Jul 04 07:11:11 PM PDT 24
Finished Jul 04 07:11:14 PM PDT 24
Peak memory 210988 kb
Host smart-c64e8c48-ee20-4f30-b198-5880a814723b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56907747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.56907747
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1252309921
Short name T922
Test name
Test status
Simulation time 513231140 ps
CPU time 2.49 seconds
Started Jul 04 07:11:09 PM PDT 24
Finished Jul 04 07:11:11 PM PDT 24
Peak memory 219216 kb
Host smart-b17b6728-a314-4a92-bce4-ebea74b90913
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125230
9921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1252309921
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1359142434
Short name T983
Test name
Test status
Simulation time 98329386 ps
CPU time 1.54 seconds
Started Jul 04 07:11:14 PM PDT 24
Finished Jul 04 07:11:16 PM PDT 24
Peak memory 209244 kb
Host smart-0978b533-4d40-430f-b4ab-3d3a600cd784
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359142434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.1359142434
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1480255987
Short name T965
Test name
Test status
Simulation time 175267094 ps
CPU time 1.67 seconds
Started Jul 04 07:11:09 PM PDT 24
Finished Jul 04 07:11:11 PM PDT 24
Peak memory 217480 kb
Host smart-85de2e00-0dfe-4519-be11-50a4fa09432d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480255987 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.1480255987
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.673914651
Short name T217
Test name
Test status
Simulation time 24514309 ps
CPU time 1.29 seconds
Started Jul 04 07:11:18 PM PDT 24
Finished Jul 04 07:11:19 PM PDT 24
Peak memory 217496 kb
Host smart-9f16c8f7-351d-4389-9cca-d8aa260c8325
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673914651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasing
.673914651
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3096467447
Short name T969
Test name
Test status
Simulation time 49605111 ps
CPU time 1.52 seconds
Started Jul 04 07:11:15 PM PDT 24
Finished Jul 04 07:11:17 PM PDT 24
Peak memory 217232 kb
Host smart-443f150b-f1c3-4018-a500-d315f3b94d6e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096467447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.3096467447
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3170899567
Short name T218
Test name
Test status
Simulation time 44511459 ps
CPU time 0.96 seconds
Started Jul 04 07:11:17 PM PDT 24
Finished Jul 04 07:11:18 PM PDT 24
Peak memory 210504 kb
Host smart-fd2ec3b9-3af8-40b5-b0cc-8c4e76c6a995
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170899567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.3170899567
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3742045935
Short name T928
Test name
Test status
Simulation time 76635035 ps
CPU time 1.2 seconds
Started Jul 04 07:11:16 PM PDT 24
Finished Jul 04 07:11:18 PM PDT 24
Peak memory 217624 kb
Host smart-b07dbeed-e275-4df5-bad1-5d3ffd2d3ad7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742045935 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.3742045935
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1915374384
Short name T871
Test name
Test status
Simulation time 40585621 ps
CPU time 0.91 seconds
Started Jul 04 07:11:20 PM PDT 24
Finished Jul 04 07:11:21 PM PDT 24
Peak memory 209244 kb
Host smart-9355f69d-964b-4d8c-8f67-beeb0285d1a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915374384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.1915374384
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2873265923
Short name T961
Test name
Test status
Simulation time 74892616 ps
CPU time 1.59 seconds
Started Jul 04 07:11:16 PM PDT 24
Finished Jul 04 07:11:18 PM PDT 24
Peak memory 209172 kb
Host smart-f9e90b75-eda6-4e4c-ad4d-9dd62d4c044a
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873265923 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.2873265923
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3889468059
Short name T939
Test name
Test status
Simulation time 3631909944 ps
CPU time 9.15 seconds
Started Jul 04 07:11:18 PM PDT 24
Finished Jul 04 07:11:27 PM PDT 24
Peak memory 217300 kb
Host smart-250e7b8e-0fcf-4abc-9f19-1260909ac0a7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889468059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.3889468059
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.331472647
Short name T880
Test name
Test status
Simulation time 5103542139 ps
CPU time 25.91 seconds
Started Jul 04 07:11:17 PM PDT 24
Finished Jul 04 07:11:44 PM PDT 24
Peak memory 209256 kb
Host smart-1df03351-a3ef-46ce-8bb7-9dcc45aab813
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331472647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.331472647
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2667965393
Short name T912
Test name
Test status
Simulation time 66951253 ps
CPU time 1.38 seconds
Started Jul 04 07:11:14 PM PDT 24
Finished Jul 04 07:11:15 PM PDT 24
Peak memory 210336 kb
Host smart-a6c01530-5973-4c13-8057-02f2c64d0416
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667965393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.2667965393
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3600960378
Short name T160
Test name
Test status
Simulation time 947311373 ps
CPU time 6.88 seconds
Started Jul 04 07:11:16 PM PDT 24
Finished Jul 04 07:11:23 PM PDT 24
Peak memory 217708 kb
Host smart-9eac14f7-cb6c-4977-bbe4-9c7b3df5d3e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360096
0378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3600960378
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1695556689
Short name T872
Test name
Test status
Simulation time 97181840 ps
CPU time 1.7 seconds
Started Jul 04 07:11:21 PM PDT 24
Finished Jul 04 07:11:23 PM PDT 24
Peak memory 209228 kb
Host smart-84755dbb-d997-4baf-af19-c1a952650797
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695556689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.1695556689
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1549519969
Short name T911
Test name
Test status
Simulation time 19098242 ps
CPU time 1.49 seconds
Started Jul 04 07:11:16 PM PDT 24
Finished Jul 04 07:11:18 PM PDT 24
Peak memory 209408 kb
Host smart-3746abdd-751c-4f98-a417-4df656308ac9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549519969 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.1549519969
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3568389696
Short name T228
Test name
Test status
Simulation time 87424850 ps
CPU time 1.39 seconds
Started Jul 04 07:11:20 PM PDT 24
Finished Jul 04 07:11:22 PM PDT 24
Peak memory 217504 kb
Host smart-4fc76175-3f4f-4110-916e-244e67a86a8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568389696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.3568389696
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1461640705
Short name T929
Test name
Test status
Simulation time 411159843 ps
CPU time 2.4 seconds
Started Jul 04 07:11:16 PM PDT 24
Finished Jul 04 07:11:18 PM PDT 24
Peak memory 217636 kb
Host smart-486927ed-408e-4065-afd5-24e30545c2b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461640705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.1461640705
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3619196346
Short name T883
Test name
Test status
Simulation time 79893869 ps
CPU time 1.3 seconds
Started Jul 04 07:11:56 PM PDT 24
Finished Jul 04 07:11:57 PM PDT 24
Peak memory 219212 kb
Host smart-422ed8fe-fc6c-49ae-8b6a-035e2db1373e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619196346 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.3619196346
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.491430570
Short name T908
Test name
Test status
Simulation time 48066208 ps
CPU time 0.85 seconds
Started Jul 04 07:11:57 PM PDT 24
Finished Jul 04 07:11:59 PM PDT 24
Peak memory 208896 kb
Host smart-bcc0fadd-2943-44a7-9018-6e0cde6e7e6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491430570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.491430570
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2724012219
Short name T926
Test name
Test status
Simulation time 26585541 ps
CPU time 1.04 seconds
Started Jul 04 07:11:58 PM PDT 24
Finished Jul 04 07:12:00 PM PDT 24
Peak memory 209392 kb
Host smart-233612c3-afe0-4368-baeb-d02a1887bc6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724012219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.2724012219
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2143170504
Short name T920
Test name
Test status
Simulation time 418352487 ps
CPU time 2.48 seconds
Started Jul 04 07:11:59 PM PDT 24
Finished Jul 04 07:12:02 PM PDT 24
Peak memory 219056 kb
Host smart-95599b1a-f7dc-479c-945f-240310e8c6cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143170504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.2143170504
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3673975748
Short name T136
Test name
Test status
Simulation time 41707086 ps
CPU time 1.28 seconds
Started Jul 04 07:11:57 PM PDT 24
Finished Jul 04 07:11:59 PM PDT 24
Peak memory 217732 kb
Host smart-fe5e92c7-76ab-4d11-a343-90fefe8722b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673975748 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.3673975748
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2892800463
Short name T225
Test name
Test status
Simulation time 19781638 ps
CPU time 0.8 seconds
Started Jul 04 07:11:56 PM PDT 24
Finished Jul 04 07:11:57 PM PDT 24
Peak memory 209316 kb
Host smart-069ab642-b531-434a-bf8f-b7ae9bc4d645
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892800463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.2892800463
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.72760335
Short name T231
Test name
Test status
Simulation time 90158493 ps
CPU time 1.38 seconds
Started Jul 04 07:11:57 PM PDT 24
Finished Jul 04 07:11:58 PM PDT 24
Peak memory 217520 kb
Host smart-c525942a-a75f-4875-86c9-f896146e4e6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72760335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_
same_csr_outstanding.72760335
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3373145178
Short name T139
Test name
Test status
Simulation time 113786449 ps
CPU time 1.39 seconds
Started Jul 04 07:11:56 PM PDT 24
Finished Jul 04 07:11:58 PM PDT 24
Peak memory 218592 kb
Host smart-14f240c0-d1c6-46b8-8a38-1db5381a732e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373145178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.3373145178
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3773370398
Short name T906
Test name
Test status
Simulation time 238258945 ps
CPU time 2.52 seconds
Started Jul 04 07:11:58 PM PDT 24
Finished Jul 04 07:12:00 PM PDT 24
Peak memory 217504 kb
Host smart-ed512c19-543b-484f-b2dd-8242414a276d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773370398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.3773370398
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.139708595
Short name T891
Test name
Test status
Simulation time 20457549 ps
CPU time 1.8 seconds
Started Jul 04 07:11:58 PM PDT 24
Finished Jul 04 07:12:01 PM PDT 24
Peak memory 221884 kb
Host smart-95ffdd5f-b929-4e3c-a496-ae6ffd9193d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139708595 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.139708595
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.354667287
Short name T976
Test name
Test status
Simulation time 16569597 ps
CPU time 0.83 seconds
Started Jul 04 07:11:58 PM PDT 24
Finished Jul 04 07:12:00 PM PDT 24
Peak memory 208872 kb
Host smart-a3c393f2-f4fc-404d-896d-7bdf3ceca3c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354667287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.354667287
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2841936768
Short name T990
Test name
Test status
Simulation time 76747355 ps
CPU time 1 seconds
Started Jul 04 07:11:57 PM PDT 24
Finished Jul 04 07:11:58 PM PDT 24
Peak memory 209328 kb
Host smart-f7e35716-5130-484d-ae78-1d786755d92a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841936768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.2841936768
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3104863732
Short name T151
Test name
Test status
Simulation time 38453948 ps
CPU time 3.02 seconds
Started Jul 04 07:11:57 PM PDT 24
Finished Jul 04 07:12:00 PM PDT 24
Peak memory 217924 kb
Host smart-654b93ed-8665-4b10-b43e-d9ff49bed7b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104863732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.3104863732
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.1682615581
Short name T159
Test name
Test status
Simulation time 70734586 ps
CPU time 2.31 seconds
Started Jul 04 07:11:58 PM PDT 24
Finished Jul 04 07:12:01 PM PDT 24
Peak memory 217500 kb
Host smart-c817c71b-e92a-4e7c-baa4-3651e3fbea88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682615581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.1682615581
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2904433533
Short name T971
Test name
Test status
Simulation time 22055499 ps
CPU time 1.76 seconds
Started Jul 04 07:11:57 PM PDT 24
Finished Jul 04 07:11:59 PM PDT 24
Peak memory 219852 kb
Host smart-0cadeb5e-e444-4aba-ae20-91f5753b38ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904433533 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.2904433533
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2508395408
Short name T223
Test name
Test status
Simulation time 31469065 ps
CPU time 1.09 seconds
Started Jul 04 07:11:56 PM PDT 24
Finished Jul 04 07:11:57 PM PDT 24
Peak memory 217264 kb
Host smart-60f2386b-2fcc-48c3-9c7a-2c69c187d72f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508395408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.2508395408
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.1240421132
Short name T138
Test name
Test status
Simulation time 70558827 ps
CPU time 1.35 seconds
Started Jul 04 07:11:56 PM PDT 24
Finished Jul 04 07:11:58 PM PDT 24
Peak memory 209384 kb
Host smart-65f1c052-6e46-4397-8963-bad898e05f67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240421132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.1240421132
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3728625822
Short name T953
Test name
Test status
Simulation time 123129104 ps
CPU time 2.74 seconds
Started Jul 04 07:11:58 PM PDT 24
Finished Jul 04 07:12:02 PM PDT 24
Peak memory 217928 kb
Host smart-b0a443da-a194-47c8-9d96-c147635408f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728625822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.3728625822
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2006277352
Short name T134
Test name
Test status
Simulation time 250813405 ps
CPU time 1.89 seconds
Started Jul 04 07:11:57 PM PDT 24
Finished Jul 04 07:12:00 PM PDT 24
Peak memory 217512 kb
Host smart-12611cf1-3136-4416-9ada-a10686c4befe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006277352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.2006277352
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3797845502
Short name T982
Test name
Test status
Simulation time 29007517 ps
CPU time 1.79 seconds
Started Jul 04 07:11:57 PM PDT 24
Finished Jul 04 07:11:59 PM PDT 24
Peak memory 224084 kb
Host smart-acb63780-d51f-409a-98c5-5d7c1c1c5ef3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797845502 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.3797845502
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.65235611
Short name T935
Test name
Test status
Simulation time 99057120 ps
CPU time 0.87 seconds
Started Jul 04 07:11:57 PM PDT 24
Finished Jul 04 07:11:58 PM PDT 24
Peak memory 217448 kb
Host smart-fc1167e1-098a-45b3-af82-06a74f3544d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65235611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.65235611
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2870587133
Short name T226
Test name
Test status
Simulation time 78825576 ps
CPU time 1.44 seconds
Started Jul 04 07:11:56 PM PDT 24
Finished Jul 04 07:11:58 PM PDT 24
Peak memory 211456 kb
Host smart-20297850-422c-4f3b-ad57-b155e6f5d907
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870587133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.2870587133
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1159620735
Short name T931
Test name
Test status
Simulation time 49457782 ps
CPU time 1.71 seconds
Started Jul 04 07:11:57 PM PDT 24
Finished Jul 04 07:11:59 PM PDT 24
Peak memory 217440 kb
Host smart-76fb102f-c138-4a3e-b22a-27c9e0622840
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159620735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.1159620735
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2248962653
Short name T161
Test name
Test status
Simulation time 354127859 ps
CPU time 2.27 seconds
Started Jul 04 07:11:59 PM PDT 24
Finished Jul 04 07:12:02 PM PDT 24
Peak memory 217572 kb
Host smart-eb2f41cc-1756-497e-973f-e0fb3c65380e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248962653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.2248962653
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3992771335
Short name T995
Test name
Test status
Simulation time 20053009 ps
CPU time 1.19 seconds
Started Jul 04 07:11:56 PM PDT 24
Finished Jul 04 07:11:57 PM PDT 24
Peak memory 218596 kb
Host smart-3ff0472b-e4c2-42c7-b540-94c202bb5e9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992771335 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.3992771335
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3407614412
Short name T962
Test name
Test status
Simulation time 18485771 ps
CPU time 0.86 seconds
Started Jul 04 07:11:58 PM PDT 24
Finished Jul 04 07:11:59 PM PDT 24
Peak memory 209252 kb
Host smart-6d48e8b8-6408-4b28-b34d-005a05dd6449
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407614412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.3407614412
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.3329302762
Short name T894
Test name
Test status
Simulation time 15134692 ps
CPU time 0.99 seconds
Started Jul 04 07:11:58 PM PDT 24
Finished Jul 04 07:12:00 PM PDT 24
Peak memory 209300 kb
Host smart-59f12782-f199-4917-a0d8-4d1cd5a1f83c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329302762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.3329302762
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1130153976
Short name T975
Test name
Test status
Simulation time 30036775 ps
CPU time 2.22 seconds
Started Jul 04 07:11:57 PM PDT 24
Finished Jul 04 07:12:00 PM PDT 24
Peak memory 217616 kb
Host smart-5339442b-38d8-479f-90a5-da78398f2093
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130153976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.1130153976
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2682915698
Short name T165
Test name
Test status
Simulation time 68729748 ps
CPU time 1.93 seconds
Started Jul 04 07:11:58 PM PDT 24
Finished Jul 04 07:12:01 PM PDT 24
Peak memory 217600 kb
Host smart-e7e9b5dd-baf1-4045-91b6-d7039777875c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682915698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.2682915698
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.149501656
Short name T898
Test name
Test status
Simulation time 41538042 ps
CPU time 1.38 seconds
Started Jul 04 07:11:59 PM PDT 24
Finished Jul 04 07:12:01 PM PDT 24
Peak memory 219416 kb
Host smart-5c8306c4-ace0-4048-bb81-4d38be4fea0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149501656 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.149501656
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.944828961
Short name T215
Test name
Test status
Simulation time 81203568 ps
CPU time 0.85 seconds
Started Jul 04 07:11:58 PM PDT 24
Finished Jul 04 07:12:00 PM PDT 24
Peak memory 208980 kb
Host smart-0f55e2a9-c5ec-4a8d-80b3-0f08c193588f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944828961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.944828961
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2861258066
Short name T925
Test name
Test status
Simulation time 116645668 ps
CPU time 1.26 seconds
Started Jul 04 07:11:58 PM PDT 24
Finished Jul 04 07:11:59 PM PDT 24
Peak memory 211464 kb
Host smart-d7cd5ae2-9e35-4631-92f8-8a6e3b0bc6a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861258066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.2861258066
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.48718587
Short name T960
Test name
Test status
Simulation time 299502746 ps
CPU time 1.92 seconds
Started Jul 04 07:11:58 PM PDT 24
Finished Jul 04 07:12:00 PM PDT 24
Peak memory 218468 kb
Host smart-715a7a96-af33-404c-a8ac-fab7d524d3e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48718587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.48718587
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2809562677
Short name T163
Test name
Test status
Simulation time 227293160 ps
CPU time 2.95 seconds
Started Jul 04 07:11:56 PM PDT 24
Finished Jul 04 07:11:59 PM PDT 24
Peak memory 222224 kb
Host smart-44f2db03-be36-42cd-a994-192dacd26730
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809562677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.2809562677
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3191756662
Short name T919
Test name
Test status
Simulation time 105514340 ps
CPU time 1.86 seconds
Started Jul 04 07:12:03 PM PDT 24
Finished Jul 04 07:12:05 PM PDT 24
Peak memory 219212 kb
Host smart-b1077892-477b-4c68-a979-bceff9e8805c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191756662 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.3191756662
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3017587097
Short name T222
Test name
Test status
Simulation time 11167514 ps
CPU time 0.9 seconds
Started Jul 04 07:12:03 PM PDT 24
Finished Jul 04 07:12:05 PM PDT 24
Peak memory 209260 kb
Host smart-0fd1c854-e79c-4934-b1d8-50910c7a9be5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017587097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.3017587097
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.1549372825
Short name T948
Test name
Test status
Simulation time 130888485 ps
CPU time 1.37 seconds
Started Jul 04 07:12:05 PM PDT 24
Finished Jul 04 07:12:07 PM PDT 24
Peak memory 209328 kb
Host smart-a28f0dd4-a7bc-4479-a9c9-fc347121d08a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549372825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.1549372825
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.84474290
Short name T940
Test name
Test status
Simulation time 124161126 ps
CPU time 5.01 seconds
Started Jul 04 07:12:02 PM PDT 24
Finished Jul 04 07:12:07 PM PDT 24
Peak memory 217600 kb
Host smart-e69093a1-9bd4-48e0-990a-a8650842c197
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84474290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.84474290
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2694371220
Short name T988
Test name
Test status
Simulation time 21454209 ps
CPU time 1.23 seconds
Started Jul 04 07:12:06 PM PDT 24
Finished Jul 04 07:12:09 PM PDT 24
Peak memory 217684 kb
Host smart-f4afe02a-6f54-4203-92a0-277818d7c30d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694371220 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.2694371220
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1966571766
Short name T216
Test name
Test status
Simulation time 12159291 ps
CPU time 0.91 seconds
Started Jul 04 07:12:03 PM PDT 24
Finished Jul 04 07:12:04 PM PDT 24
Peak memory 209092 kb
Host smart-580613bd-f76a-4ae0-8ee1-d191c1e35cef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966571766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.1966571766
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.305529105
Short name T177
Test name
Test status
Simulation time 58119104 ps
CPU time 1.11 seconds
Started Jul 04 07:12:03 PM PDT 24
Finished Jul 04 07:12:05 PM PDT 24
Peak memory 209252 kb
Host smart-e7574cf5-8ebc-4004-94a0-9fc404979597
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305529105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_same_csr_outstanding.305529105
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.2302581307
Short name T146
Test name
Test status
Simulation time 38570742 ps
CPU time 2.52 seconds
Started Jul 04 07:12:02 PM PDT 24
Finished Jul 04 07:12:05 PM PDT 24
Peak memory 217624 kb
Host smart-feb5e5fd-e559-481f-819e-5a89f39b70ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302581307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.2302581307
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.505024398
Short name T147
Test name
Test status
Simulation time 64125938 ps
CPU time 1.3 seconds
Started Jul 04 07:12:07 PM PDT 24
Finished Jul 04 07:12:10 PM PDT 24
Peak memory 217580 kb
Host smart-21ba125f-3fdb-4da7-ab66-17aa55f49e5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505024398 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.505024398
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1589770340
Short name T220
Test name
Test status
Simulation time 46150185 ps
CPU time 0.98 seconds
Started Jul 04 07:12:05 PM PDT 24
Finished Jul 04 07:12:08 PM PDT 24
Peak memory 209424 kb
Host smart-e9528892-9609-496a-b17d-de374cb5c45d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589770340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.1589770340
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3294839811
Short name T947
Test name
Test status
Simulation time 21290511 ps
CPU time 1.26 seconds
Started Jul 04 07:12:04 PM PDT 24
Finished Jul 04 07:12:06 PM PDT 24
Peak memory 217508 kb
Host smart-7470ecb4-ff61-4e43-a3e0-afb55ae17be9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294839811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.3294839811
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2695996079
Short name T214
Test name
Test status
Simulation time 413943525 ps
CPU time 1.2 seconds
Started Jul 04 07:11:23 PM PDT 24
Finished Jul 04 07:11:24 PM PDT 24
Peak memory 209224 kb
Host smart-7148f318-c1f1-4e2e-a731-3fc097e9c463
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695996079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.2695996079
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2500173508
Short name T907
Test name
Test status
Simulation time 102326558 ps
CPU time 1.74 seconds
Started Jul 04 07:11:23 PM PDT 24
Finished Jul 04 07:11:25 PM PDT 24
Peak memory 208964 kb
Host smart-4248a0c8-1a2e-4778-ad16-2e5f00f2d91d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500173508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.2500173508
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2154816823
Short name T897
Test name
Test status
Simulation time 54262168 ps
CPU time 0.96 seconds
Started Jul 04 07:11:22 PM PDT 24
Finished Jul 04 07:11:23 PM PDT 24
Peak memory 209928 kb
Host smart-d322fb70-5f75-48bf-a97f-7fb5de877500
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154816823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.2154816823
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2914890994
Short name T153
Test name
Test status
Simulation time 311647971 ps
CPU time 1.78 seconds
Started Jul 04 07:11:23 PM PDT 24
Finished Jul 04 07:11:25 PM PDT 24
Peak memory 223064 kb
Host smart-4c74ecbf-40cf-467b-b94a-c0bd4311199e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914890994 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.2914890994
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.275596880
Short name T930
Test name
Test status
Simulation time 57188507 ps
CPU time 0.98 seconds
Started Jul 04 07:11:24 PM PDT 24
Finished Jul 04 07:11:25 PM PDT 24
Peak memory 209288 kb
Host smart-87b0520e-cd2b-4df0-b98c-49d2e01e834b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275596880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.275596880
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2857292505
Short name T902
Test name
Test status
Simulation time 39927617 ps
CPU time 0.87 seconds
Started Jul 04 07:11:18 PM PDT 24
Finished Jul 04 07:11:19 PM PDT 24
Peak memory 209272 kb
Host smart-a62d4752-dc56-4d12-8a95-0f373cabcac3
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857292505 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.2857292505
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1986430022
Short name T936
Test name
Test status
Simulation time 897540929 ps
CPU time 2.8 seconds
Started Jul 04 07:11:18 PM PDT 24
Finished Jul 04 07:11:21 PM PDT 24
Peak memory 208576 kb
Host smart-e1a959c2-f1ff-4ba4-b868-d3aa3b58fe5a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986430022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.1986430022
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.664244203
Short name T970
Test name
Test status
Simulation time 766263641 ps
CPU time 7.58 seconds
Started Jul 04 07:11:19 PM PDT 24
Finished Jul 04 07:11:27 PM PDT 24
Peak memory 209232 kb
Host smart-e5537dab-fff4-4895-9101-ac98efc4e2ee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664244203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.664244203
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.4264061311
Short name T972
Test name
Test status
Simulation time 456662538 ps
CPU time 3.24 seconds
Started Jul 04 07:11:17 PM PDT 24
Finished Jul 04 07:11:21 PM PDT 24
Peak memory 210884 kb
Host smart-53e30369-bba3-406a-8291-1a6ff42ccb01
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264061311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.4264061311
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1474340763
Short name T873
Test name
Test status
Simulation time 1488547560 ps
CPU time 3.27 seconds
Started Jul 04 07:11:19 PM PDT 24
Finished Jul 04 07:11:22 PM PDT 24
Peak memory 217676 kb
Host smart-2e091e29-f0f8-433d-8374-32f656e44fe0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147434
0763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1474340763
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.10498449
Short name T877
Test name
Test status
Simulation time 976882414 ps
CPU time 1.25 seconds
Started Jul 04 07:11:20 PM PDT 24
Finished Jul 04 07:11:22 PM PDT 24
Peak memory 209236 kb
Host smart-52d93821-87db-4b93-bf08-60cb9d5ea53f
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10498449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test
+UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 2.lc_ctrl_jtag_csr_rw.10498449
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3926864749
Short name T964
Test name
Test status
Simulation time 25539835 ps
CPU time 1.31 seconds
Started Jul 04 07:11:17 PM PDT 24
Finished Jul 04 07:11:19 PM PDT 24
Peak memory 209308 kb
Host smart-890c241b-8f93-4474-b25f-2ec60ee20379
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926864749 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.3926864749
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3312086711
Short name T916
Test name
Test status
Simulation time 103337183 ps
CPU time 1.56 seconds
Started Jul 04 07:11:24 PM PDT 24
Finished Jul 04 07:11:26 PM PDT 24
Peak memory 210980 kb
Host smart-d474c988-d9d0-444a-97ff-da4a387ac9f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312086711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.3312086711
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2037558350
Short name T145
Test name
Test status
Simulation time 103287329 ps
CPU time 1.49 seconds
Started Jul 04 07:11:27 PM PDT 24
Finished Jul 04 07:11:29 PM PDT 24
Peak memory 217504 kb
Host smart-760e9879-e4f4-41b6-9ded-09db9eec66b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037558350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.2037558350
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.134318426
Short name T895
Test name
Test status
Simulation time 20907478 ps
CPU time 1.04 seconds
Started Jul 04 07:11:28 PM PDT 24
Finished Jul 04 07:11:29 PM PDT 24
Peak memory 209328 kb
Host smart-98171f8d-29a6-43d1-b811-357dd65a2214
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134318426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasing
.134318426
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2500451881
Short name T884
Test name
Test status
Simulation time 61352158 ps
CPU time 1.13 seconds
Started Jul 04 07:11:24 PM PDT 24
Finished Jul 04 07:11:25 PM PDT 24
Peak memory 217284 kb
Host smart-617aa5d3-65bc-4a8f-80a8-f14a650eed73
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500451881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.2500451881
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2952825376
Short name T904
Test name
Test status
Simulation time 49339457 ps
CPU time 0.92 seconds
Started Jul 04 07:11:24 PM PDT 24
Finished Jul 04 07:11:26 PM PDT 24
Peak memory 209904 kb
Host smart-33f9e820-2f2b-48ff-b542-2b11e0468a73
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952825376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.2952825376
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1672195100
Short name T977
Test name
Test status
Simulation time 32743787 ps
CPU time 0.98 seconds
Started Jul 04 07:11:30 PM PDT 24
Finished Jul 04 07:11:32 PM PDT 24
Peak memory 217436 kb
Host smart-7af061c1-8ee5-4dbd-8a98-0f453e690ffb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672195100 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.1672195100
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.3684204070
Short name T893
Test name
Test status
Simulation time 41778916 ps
CPU time 0.85 seconds
Started Jul 04 07:11:27 PM PDT 24
Finished Jul 04 07:11:28 PM PDT 24
Peak memory 209304 kb
Host smart-f59da36e-eba5-41d3-b35b-e6ada6cb6865
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684204070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.3684204070
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1202804541
Short name T955
Test name
Test status
Simulation time 74676337 ps
CPU time 1.47 seconds
Started Jul 04 07:11:26 PM PDT 24
Finished Jul 04 07:11:28 PM PDT 24
Peak memory 209160 kb
Host smart-f34443c0-1a68-4df0-ba8e-bbbab8850453
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202804541 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.1202804541
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3938192860
Short name T879
Test name
Test status
Simulation time 302844839 ps
CPU time 7.42 seconds
Started Jul 04 07:11:24 PM PDT 24
Finished Jul 04 07:11:31 PM PDT 24
Peak memory 208540 kb
Host smart-8f0e2c98-aec3-42be-877d-6accbb03d42e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938192860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.3938192860
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3774842060
Short name T235
Test name
Test status
Simulation time 1676471339 ps
CPU time 5.37 seconds
Started Jul 04 07:11:24 PM PDT 24
Finished Jul 04 07:11:30 PM PDT 24
Peak memory 209204 kb
Host smart-324220ed-6c08-4ec4-a4c8-15218af846b1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774842060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.3774842060
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.200913228
Short name T903
Test name
Test status
Simulation time 162921224 ps
CPU time 2.13 seconds
Started Jul 04 07:11:27 PM PDT 24
Finished Jul 04 07:11:30 PM PDT 24
Peak memory 210876 kb
Host smart-e457781a-ea4e-4516-8afd-b5cebb81bfad
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200913228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.200913228
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2193519876
Short name T905
Test name
Test status
Simulation time 587418894 ps
CPU time 7.54 seconds
Started Jul 04 07:11:24 PM PDT 24
Finished Jul 04 07:11:32 PM PDT 24
Peak memory 222876 kb
Host smart-735016d7-ac05-4f50-9130-086c1869001f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219351
9876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2193519876
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.339290317
Short name T967
Test name
Test status
Simulation time 130520773 ps
CPU time 1.03 seconds
Started Jul 04 07:11:24 PM PDT 24
Finished Jul 04 07:11:25 PM PDT 24
Peak memory 209152 kb
Host smart-0f6ea011-04bc-4d44-bc17-bff95b27ee53
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339290317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.339290317
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2574197824
Short name T921
Test name
Test status
Simulation time 34884559 ps
CPU time 0.94 seconds
Started Jul 04 07:11:24 PM PDT 24
Finished Jul 04 07:11:25 PM PDT 24
Peak memory 209316 kb
Host smart-c6ea7ff0-66c5-41ce-a106-de69d70112d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574197824 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.2574197824
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.803319852
Short name T974
Test name
Test status
Simulation time 20803352 ps
CPU time 1.18 seconds
Started Jul 04 07:11:31 PM PDT 24
Finished Jul 04 07:11:32 PM PDT 24
Peak memory 211396 kb
Host smart-54d3a2e5-58d9-4dc7-987f-5e1b23f1ffa5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803319852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
same_csr_outstanding.803319852
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.4149343858
Short name T133
Test name
Test status
Simulation time 89387572 ps
CPU time 3.79 seconds
Started Jul 04 07:11:23 PM PDT 24
Finished Jul 04 07:11:27 PM PDT 24
Peak memory 217552 kb
Host smart-fecbbba1-3e03-4cb4-be7f-e801c1b6174f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149343858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.4149343858
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2763247940
Short name T875
Test name
Test status
Simulation time 15251816 ps
CPU time 1.16 seconds
Started Jul 04 07:11:34 PM PDT 24
Finished Jul 04 07:11:35 PM PDT 24
Peak memory 209304 kb
Host smart-103e1f03-608d-434b-a9a3-fb226c776265
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763247940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.2763247940
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1552055683
Short name T944
Test name
Test status
Simulation time 636818061 ps
CPU time 2.06 seconds
Started Jul 04 07:11:34 PM PDT 24
Finished Jul 04 07:11:36 PM PDT 24
Peak memory 209240 kb
Host smart-2d5fbb97-9932-4bf5-8b75-22ca47fc0810
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552055683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.1552055683
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.4050148773
Short name T885
Test name
Test status
Simulation time 14934236 ps
CPU time 0.93 seconds
Started Jul 04 07:11:31 PM PDT 24
Finished Jul 04 07:11:32 PM PDT 24
Peak memory 209812 kb
Host smart-f980876f-7a01-4c2d-8b5c-3d1319317af7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050148773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.4050148773
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.2299557473
Short name T154
Test name
Test status
Simulation time 266356103 ps
CPU time 1.3 seconds
Started Jul 04 07:11:32 PM PDT 24
Finished Jul 04 07:11:33 PM PDT 24
Peak memory 222948 kb
Host smart-3681639f-1b01-4e9d-9198-13d2ecfc8903
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299557473 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.2299557473
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.168827245
Short name T989
Test name
Test status
Simulation time 45668481 ps
CPU time 1.05 seconds
Started Jul 04 07:11:29 PM PDT 24
Finished Jul 04 07:11:31 PM PDT 24
Peak memory 209044 kb
Host smart-bf4dee90-b8a8-47db-8a65-c2f0151996a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168827245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.168827245
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2952928869
Short name T956
Test name
Test status
Simulation time 51933210 ps
CPU time 1.24 seconds
Started Jul 04 07:11:33 PM PDT 24
Finished Jul 04 07:11:35 PM PDT 24
Peak memory 209100 kb
Host smart-b248588c-5c5b-47a5-a836-5de9c3a7b935
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952928869 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.2952928869
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.24550516
Short name T169
Test name
Test status
Simulation time 264458040 ps
CPU time 6.22 seconds
Started Jul 04 07:11:35 PM PDT 24
Finished Jul 04 07:11:42 PM PDT 24
Peak memory 209200 kb
Host smart-7961328b-20e8-463f-b3a5-f8e4e68dc99a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24550516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 4.lc_ctrl_jtag_csr_aliasing.24550516
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2999352107
Short name T892
Test name
Test status
Simulation time 2069935020 ps
CPU time 22.17 seconds
Started Jul 04 07:11:29 PM PDT 24
Finished Jul 04 07:11:51 PM PDT 24
Peak memory 209200 kb
Host smart-a09a4d99-1bd7-4033-89d5-2a63a2f0a061
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999352107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.2999352107
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.1568905382
Short name T942
Test name
Test status
Simulation time 50229125 ps
CPU time 1.84 seconds
Started Jul 04 07:11:36 PM PDT 24
Finished Jul 04 07:11:38 PM PDT 24
Peak memory 210740 kb
Host smart-9ef87079-e75f-442e-b071-74166ef44db2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568905382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.1568905382
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1183914365
Short name T958
Test name
Test status
Simulation time 254851253 ps
CPU time 1.76 seconds
Started Jul 04 07:11:32 PM PDT 24
Finished Jul 04 07:11:34 PM PDT 24
Peak memory 217664 kb
Host smart-3175116f-afb5-4d37-bd77-bd10a3e8dc9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118391
4365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1183914365
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.3144986639
Short name T957
Test name
Test status
Simulation time 63617362 ps
CPU time 1.06 seconds
Started Jul 04 07:11:30 PM PDT 24
Finished Jul 04 07:11:32 PM PDT 24
Peak memory 209024 kb
Host smart-3e97de5f-b702-4feb-bc93-cd219e2bc17c
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144986639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.3144986639
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1576745509
Short name T232
Test name
Test status
Simulation time 38835039 ps
CPU time 1.47 seconds
Started Jul 04 07:11:30 PM PDT 24
Finished Jul 04 07:11:32 PM PDT 24
Peak memory 217508 kb
Host smart-75411483-e766-4126-bfc2-4b30c033fc99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576745509 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.1576745509
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.874451668
Short name T227
Test name
Test status
Simulation time 96954153 ps
CPU time 1.06 seconds
Started Jul 04 07:11:28 PM PDT 24
Finished Jul 04 07:11:29 PM PDT 24
Peak memory 209292 kb
Host smart-e0247a65-5bcc-46dc-b952-a840d62eebaa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874451668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
same_csr_outstanding.874451668
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2293337447
Short name T978
Test name
Test status
Simulation time 433423645 ps
CPU time 4.61 seconds
Started Jul 04 07:11:31 PM PDT 24
Finished Jul 04 07:11:36 PM PDT 24
Peak memory 217472 kb
Host smart-cf7ed91e-5345-4aeb-b608-e09343ee8eda
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293337447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.2293337447
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2470986287
Short name T946
Test name
Test status
Simulation time 100867527 ps
CPU time 1.1 seconds
Started Jul 04 07:11:35 PM PDT 24
Finished Jul 04 07:11:37 PM PDT 24
Peak memory 217676 kb
Host smart-787a540b-1a73-4909-a345-119d0cf73b98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470986287 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.2470986287
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1077581905
Short name T142
Test name
Test status
Simulation time 13314380 ps
CPU time 0.84 seconds
Started Jul 04 07:11:34 PM PDT 24
Finished Jul 04 07:11:35 PM PDT 24
Peak memory 209232 kb
Host smart-b6cec39b-e4d6-4586-9d73-b6adfe443139
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077581905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.1077581905
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.3987799863
Short name T901
Test name
Test status
Simulation time 198838479 ps
CPU time 1.18 seconds
Started Jul 04 07:11:35 PM PDT 24
Finished Jul 04 07:11:37 PM PDT 24
Peak memory 208616 kb
Host smart-85378889-27d5-49d7-b8fb-6d01149dd797
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987799863 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.3987799863
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1183384565
Short name T914
Test name
Test status
Simulation time 1184925608 ps
CPU time 2.83 seconds
Started Jul 04 07:11:34 PM PDT 24
Finished Jul 04 07:11:37 PM PDT 24
Peak memory 209240 kb
Host smart-cb5c6670-bf4b-4ff2-beaf-0e4b0b577479
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183384565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.1183384565
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2808245468
Short name T992
Test name
Test status
Simulation time 2642473866 ps
CPU time 10.77 seconds
Started Jul 04 07:11:30 PM PDT 24
Finished Jul 04 07:11:42 PM PDT 24
Peak memory 217300 kb
Host smart-d7761952-350f-4e92-be37-b7b8661c47c4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808245468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.2808245468
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2512738836
Short name T963
Test name
Test status
Simulation time 80297289 ps
CPU time 1.68 seconds
Started Jul 04 07:11:33 PM PDT 24
Finished Jul 04 07:11:35 PM PDT 24
Peak memory 210940 kb
Host smart-cd847ac6-d2cc-41fc-8394-4c2b23dd8eb0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512738836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.2512738836
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.646545562
Short name T933
Test name
Test status
Simulation time 236379121 ps
CPU time 2.14 seconds
Started Jul 04 07:11:48 PM PDT 24
Finished Jul 04 07:11:51 PM PDT 24
Peak memory 217484 kb
Host smart-e97f7631-2e04-462a-b62e-79f81b5b2b9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646545
562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.646545562
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.851034139
Short name T913
Test name
Test status
Simulation time 142408731 ps
CPU time 1.24 seconds
Started Jul 04 07:11:30 PM PDT 24
Finished Jul 04 07:11:32 PM PDT 24
Peak memory 209136 kb
Host smart-376444f6-a05d-4d58-82fb-616b0994ef0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851034139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.851034139
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3494772534
Short name T985
Test name
Test status
Simulation time 53922659 ps
CPU time 2.14 seconds
Started Jul 04 07:11:28 PM PDT 24
Finished Jul 04 07:11:31 PM PDT 24
Peak memory 211396 kb
Host smart-56488737-defe-410b-944b-11d4b076c6bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494772534 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.3494772534
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.184598703
Short name T230
Test name
Test status
Simulation time 77295095 ps
CPU time 1.46 seconds
Started Jul 04 07:11:36 PM PDT 24
Finished Jul 04 07:11:38 PM PDT 24
Peak memory 211172 kb
Host smart-d63bccd8-b566-4e46-a8d4-08c66096cdfc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184598703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
same_csr_outstanding.184598703
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2200020370
Short name T150
Test name
Test status
Simulation time 27356838 ps
CPU time 2.06 seconds
Started Jul 04 07:11:38 PM PDT 24
Finished Jul 04 07:11:40 PM PDT 24
Peak memory 217780 kb
Host smart-ef1d0b68-6289-4a64-a695-14710613b2e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200020370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.2200020370
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1696346546
Short name T943
Test name
Test status
Simulation time 131528923 ps
CPU time 0.92 seconds
Started Jul 04 07:11:46 PM PDT 24
Finished Jul 04 07:11:47 PM PDT 24
Peak memory 217836 kb
Host smart-8fb4dea0-14a9-4e9b-ac8a-f908a08c655b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696346546 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.1696346546
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.295068567
Short name T224
Test name
Test status
Simulation time 60974035 ps
CPU time 1.16 seconds
Started Jul 04 07:11:36 PM PDT 24
Finished Jul 04 07:11:37 PM PDT 24
Peak memory 209104 kb
Host smart-23558ded-f536-4104-9958-fbe78954436f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295068567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.295068567
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.976874104
Short name T874
Test name
Test status
Simulation time 95608414 ps
CPU time 1.51 seconds
Started Jul 04 07:11:37 PM PDT 24
Finished Jul 04 07:11:38 PM PDT 24
Peak memory 209140 kb
Host smart-88441f7f-a3dc-407e-a14e-72a10d611c4b
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976874104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.lc_ctrl_jtag_alert_test.976874104
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3012369019
Short name T952
Test name
Test status
Simulation time 4437911806 ps
CPU time 15.65 seconds
Started Jul 04 07:11:48 PM PDT 24
Finished Jul 04 07:12:05 PM PDT 24
Peak memory 209232 kb
Host smart-9202c91f-21f9-470b-a54a-e0de629b9d2b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012369019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.3012369019
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3911457255
Short name T886
Test name
Test status
Simulation time 4701625173 ps
CPU time 10.56 seconds
Started Jul 04 07:11:35 PM PDT 24
Finished Jul 04 07:11:46 PM PDT 24
Peak memory 209284 kb
Host smart-abecaeb6-13c3-4d44-9658-ced3c92850a3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911457255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.3911457255
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2707034267
Short name T918
Test name
Test status
Simulation time 75130063 ps
CPU time 2.41 seconds
Started Jul 04 07:11:49 PM PDT 24
Finished Jul 04 07:11:52 PM PDT 24
Peak memory 210392 kb
Host smart-712b65dc-1d48-4280-86f6-a47121eceedf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707034267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.2707034267
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4049446796
Short name T984
Test name
Test status
Simulation time 208108988 ps
CPU time 5.44 seconds
Started Jul 04 07:11:37 PM PDT 24
Finished Jul 04 07:11:42 PM PDT 24
Peak memory 217720 kb
Host smart-0b8a20cf-1ab2-4028-94ea-52d7d7bc5fe7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404944
6796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4049446796
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1994979633
Short name T979
Test name
Test status
Simulation time 240594370 ps
CPU time 2.13 seconds
Started Jul 04 07:11:36 PM PDT 24
Finished Jul 04 07:11:39 PM PDT 24
Peak memory 209256 kb
Host smart-ca9c933c-3680-43b2-8559-08e0310b9643
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994979633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.1994979633
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3021062
Short name T934
Test name
Test status
Simulation time 91141831 ps
CPU time 1.09 seconds
Started Jul 04 07:11:37 PM PDT 24
Finished Jul 04 07:11:39 PM PDT 24
Peak memory 217568 kb
Host smart-42475610-aa6d-4362-a888-0e996bfdbd2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021062 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.3021062
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.619559265
Short name T959
Test name
Test status
Simulation time 21975255 ps
CPU time 1.5 seconds
Started Jul 04 07:11:38 PM PDT 24
Finished Jul 04 07:11:40 PM PDT 24
Peak memory 217520 kb
Host smart-499cdb3b-cbff-4faf-b2d4-31d1cca4a8ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619559265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
same_csr_outstanding.619559265
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2008865825
Short name T909
Test name
Test status
Simulation time 86052563 ps
CPU time 1.64 seconds
Started Jul 04 07:11:48 PM PDT 24
Finished Jul 04 07:11:51 PM PDT 24
Peak memory 218504 kb
Host smart-d67e1918-9f07-424d-8697-bccb5cec4000
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008865825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.2008865825
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.378024428
Short name T890
Test name
Test status
Simulation time 23507940 ps
CPU time 1.25 seconds
Started Jul 04 07:11:50 PM PDT 24
Finished Jul 04 07:11:52 PM PDT 24
Peak memory 217668 kb
Host smart-bdd0d06f-2484-4f97-913a-70bebc49240d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378024428 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.378024428
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.479930228
Short name T973
Test name
Test status
Simulation time 25471636 ps
CPU time 1.02 seconds
Started Jul 04 07:11:42 PM PDT 24
Finished Jul 04 07:11:43 PM PDT 24
Peak memory 209280 kb
Host smart-528ec96a-ec2a-4bf9-b7c2-c7c56a9f80aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479930228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.479930228
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3797380027
Short name T882
Test name
Test status
Simulation time 72109555 ps
CPU time 1.11 seconds
Started Jul 04 07:11:44 PM PDT 24
Finished Jul 04 07:11:46 PM PDT 24
Peak memory 209160 kb
Host smart-66249a97-24e1-4583-9b9e-df50af4e3685
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797380027 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.3797380027
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1500249793
Short name T889
Test name
Test status
Simulation time 1396693569 ps
CPU time 7.5 seconds
Started Jul 04 07:11:44 PM PDT 24
Finished Jul 04 07:11:51 PM PDT 24
Peak memory 209212 kb
Host smart-edccb452-f931-4fcb-9b00-b070149a8c69
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500249793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.1500249793
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.407415894
Short name T987
Test name
Test status
Simulation time 1661655641 ps
CPU time 21.68 seconds
Started Jul 04 07:11:40 PM PDT 24
Finished Jul 04 07:12:02 PM PDT 24
Peak memory 217136 kb
Host smart-05fc1d15-8ff9-498c-a4b6-e8c7d89ff550
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407415894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.407415894
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2323406833
Short name T954
Test name
Test status
Simulation time 234389372 ps
CPU time 1.76 seconds
Started Jul 04 07:11:45 PM PDT 24
Finished Jul 04 07:11:47 PM PDT 24
Peak memory 210872 kb
Host smart-b83d773b-c4e9-49b3-943b-bca849b510b3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323406833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.2323406833
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2945828490
Short name T168
Test name
Test status
Simulation time 587501768 ps
CPU time 2.63 seconds
Started Jul 04 07:11:42 PM PDT 24
Finished Jul 04 07:11:45 PM PDT 24
Peak memory 218968 kb
Host smart-f1654aee-e124-4dc2-afaf-9b13803cf0ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294582
8490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2945828490
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1189944552
Short name T881
Test name
Test status
Simulation time 39698474 ps
CPU time 1.55 seconds
Started Jul 04 07:11:43 PM PDT 24
Finished Jul 04 07:11:45 PM PDT 24
Peak memory 209148 kb
Host smart-2932af8c-769b-453d-b38b-cd01bd898a18
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189944552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.1189944552
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2430463833
Short name T945
Test name
Test status
Simulation time 23159742 ps
CPU time 1.5 seconds
Started Jul 04 07:11:46 PM PDT 24
Finished Jul 04 07:11:48 PM PDT 24
Peak memory 217776 kb
Host smart-fae5acb8-51a1-44d5-8539-a872397aaf1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430463833 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.2430463833
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3466552103
Short name T966
Test name
Test status
Simulation time 137660174 ps
CPU time 1.03 seconds
Started Jul 04 07:11:50 PM PDT 24
Finished Jul 04 07:11:52 PM PDT 24
Peak memory 209528 kb
Host smart-ed4b9bda-03dc-4d25-be9d-ff6b5f817d45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466552103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.3466552103
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.2384054493
Short name T986
Test name
Test status
Simulation time 101310719 ps
CPU time 2.29 seconds
Started Jul 04 07:11:45 PM PDT 24
Finished Jul 04 07:11:47 PM PDT 24
Peak memory 217724 kb
Host smart-eee52078-d05e-4d9e-afe8-30911a583c0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384054493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.2384054493
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.339496827
Short name T166
Test name
Test status
Simulation time 313219730 ps
CPU time 2.08 seconds
Started Jul 04 07:11:42 PM PDT 24
Finished Jul 04 07:11:44 PM PDT 24
Peak memory 221844 kb
Host smart-945bd17b-c820-4936-bcfc-255868cba817
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339496827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_e
rr.339496827
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.500089336
Short name T888
Test name
Test status
Simulation time 240072779 ps
CPU time 1.12 seconds
Started Jul 04 07:11:53 PM PDT 24
Finished Jul 04 07:11:54 PM PDT 24
Peak memory 217744 kb
Host smart-d26dedac-a9ce-4521-b434-d96b3c8a8be4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500089336 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.500089336
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.4248715925
Short name T221
Test name
Test status
Simulation time 37287390 ps
CPU time 1.09 seconds
Started Jul 04 07:11:49 PM PDT 24
Finished Jul 04 07:11:50 PM PDT 24
Peak memory 209444 kb
Host smart-dd85b6bc-a732-43e8-855d-efb0cfe5821d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248715925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.4248715925
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3180901738
Short name T949
Test name
Test status
Simulation time 55851340 ps
CPU time 0.98 seconds
Started Jul 04 07:11:55 PM PDT 24
Finished Jul 04 07:11:56 PM PDT 24
Peak memory 209124 kb
Host smart-4b9073cb-c03b-4b0f-a673-5422a6e176e9
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180901738 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.3180901738
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3822440773
Short name T927
Test name
Test status
Simulation time 527068678 ps
CPU time 6.67 seconds
Started Jul 04 07:11:49 PM PDT 24
Finished Jul 04 07:11:56 PM PDT 24
Peak memory 209116 kb
Host smart-80753176-5eeb-420d-8188-4db78187824a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822440773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.3822440773
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.243385781
Short name T910
Test name
Test status
Simulation time 18561054247 ps
CPU time 17.39 seconds
Started Jul 04 07:11:48 PM PDT 24
Finished Jul 04 07:12:06 PM PDT 24
Peak memory 209312 kb
Host smart-e956c336-b617-43cf-9d0a-d8871a98dc22
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243385781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.243385781
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2696552471
Short name T937
Test name
Test status
Simulation time 975344212 ps
CPU time 1.57 seconds
Started Jul 04 07:11:49 PM PDT 24
Finished Jul 04 07:11:51 PM PDT 24
Peak memory 210680 kb
Host smart-f6427850-d821-404f-8358-bbbb79990c2a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696552471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.2696552471
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.711045667
Short name T951
Test name
Test status
Simulation time 1575581877 ps
CPU time 3.19 seconds
Started Jul 04 07:11:52 PM PDT 24
Finished Jul 04 07:11:56 PM PDT 24
Peak memory 209256 kb
Host smart-2b92fe88-5642-42b0-b4bb-7bd058a2272c
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711045667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.711045667
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1076944981
Short name T915
Test name
Test status
Simulation time 136159551 ps
CPU time 1.37 seconds
Started Jul 04 07:11:51 PM PDT 24
Finished Jul 04 07:11:52 PM PDT 24
Peak memory 209448 kb
Host smart-0db61efa-f9b0-46c6-a922-8ce74dfd99ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076944981 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.1076944981
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1681714947
Short name T900
Test name
Test status
Simulation time 55482043 ps
CPU time 1.2 seconds
Started Jul 04 07:11:54 PM PDT 24
Finished Jul 04 07:11:55 PM PDT 24
Peak memory 217460 kb
Host smart-466de77e-1bae-4c88-b56c-3a89619a7741
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681714947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.1681714947
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3181813848
Short name T980
Test name
Test status
Simulation time 139526185 ps
CPU time 3.25 seconds
Started Jul 04 07:11:48 PM PDT 24
Finished Jul 04 07:11:52 PM PDT 24
Peak memory 217508 kb
Host smart-6182bbd5-e7e5-4846-b2c2-e001910ee54c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181813848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.3181813848
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2237678251
Short name T899
Test name
Test status
Simulation time 18747968 ps
CPU time 1.26 seconds
Started Jul 04 07:12:00 PM PDT 24
Finished Jul 04 07:12:01 PM PDT 24
Peak memory 217604 kb
Host smart-c1e17c4e-c9f6-4234-b885-8d56f7479491
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237678251 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.2237678251
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3414161164
Short name T876
Test name
Test status
Simulation time 26385732 ps
CPU time 1.04 seconds
Started Jul 04 07:11:48 PM PDT 24
Finished Jul 04 07:11:49 PM PDT 24
Peak memory 209276 kb
Host smart-9d3946bf-2331-40af-b099-37a8e7fdefa1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414161164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.3414161164
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.4104814655
Short name T994
Test name
Test status
Simulation time 80350866 ps
CPU time 2.39 seconds
Started Jul 04 07:11:51 PM PDT 24
Finished Jul 04 07:11:54 PM PDT 24
Peak memory 209228 kb
Host smart-005468be-964d-41c0-99f0-5549007643c9
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104814655 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.4104814655
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3063275952
Short name T167
Test name
Test status
Simulation time 880543927 ps
CPU time 11 seconds
Started Jul 04 07:11:49 PM PDT 24
Finished Jul 04 07:12:00 PM PDT 24
Peak memory 217056 kb
Host smart-103610be-948f-4039-b326-622d8f4e8aff
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063275952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.3063275952
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1485743250
Short name T924
Test name
Test status
Simulation time 3081399965 ps
CPU time 5.97 seconds
Started Jul 04 07:11:50 PM PDT 24
Finished Jul 04 07:11:56 PM PDT 24
Peak memory 209268 kb
Host smart-2408dab1-81d7-44e0-b5b9-013b246e27ed
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485743250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.1485743250
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.105205880
Short name T878
Test name
Test status
Simulation time 197549856 ps
CPU time 1.78 seconds
Started Jul 04 07:11:48 PM PDT 24
Finished Jul 04 07:11:51 PM PDT 24
Peak memory 210900 kb
Host smart-370eeab4-6194-4090-ac13-5dd89d6c49dc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105205880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.105205880
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2614850578
Short name T149
Test name
Test status
Simulation time 249135918 ps
CPU time 2.45 seconds
Started Jul 04 07:11:51 PM PDT 24
Finished Jul 04 07:11:53 PM PDT 24
Peak memory 223452 kb
Host smart-f955b131-261b-495c-a06a-2140c9272f86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261485
0578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2614850578
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3370980579
Short name T981
Test name
Test status
Simulation time 57710589 ps
CPU time 1.95 seconds
Started Jul 04 07:11:53 PM PDT 24
Finished Jul 04 07:11:55 PM PDT 24
Peak memory 217416 kb
Host smart-bd9eaef3-36c1-4333-a7d2-5d9bf18d3394
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370980579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.3370980579
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1383499298
Short name T950
Test name
Test status
Simulation time 172836919 ps
CPU time 1.01 seconds
Started Jul 04 07:11:47 PM PDT 24
Finished Jul 04 07:11:49 PM PDT 24
Peak memory 217556 kb
Host smart-f697936f-6250-4124-849f-82833367dc0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383499298 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.1383499298
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.111020699
Short name T991
Test name
Test status
Simulation time 20860173 ps
CPU time 1.03 seconds
Started Jul 04 07:11:55 PM PDT 24
Finished Jul 04 07:11:57 PM PDT 24
Peak memory 217512 kb
Host smart-8a25a724-fd48-45ca-84ca-4de5d2dc569b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111020699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
same_csr_outstanding.111020699
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.247133718
Short name T941
Test name
Test status
Simulation time 48155039 ps
CPU time 3.43 seconds
Started Jul 04 07:11:52 PM PDT 24
Finished Jul 04 07:11:55 PM PDT 24
Peak memory 218608 kb
Host smart-39d40bad-c2f7-4a02-a530-0a82aada0c01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247133718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.247133718
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.4142288849
Short name T143
Test name
Test status
Simulation time 338811190 ps
CPU time 3.91 seconds
Started Jul 04 07:11:50 PM PDT 24
Finished Jul 04 07:11:55 PM PDT 24
Peak memory 222304 kb
Host smart-f2e21475-e609-4f9b-956c-28e5ffb87f9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142288849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.4142288849
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.1935534140
Short name T620
Test name
Test status
Simulation time 31764927 ps
CPU time 0.95 seconds
Started Jul 04 07:12:03 PM PDT 24
Finished Jul 04 07:12:05 PM PDT 24
Peak memory 208536 kb
Host smart-8f435344-a928-4d5b-b7a3-a64a4ca63221
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935534140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.1935534140
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.1136977262
Short name T492
Test name
Test status
Simulation time 683919374 ps
CPU time 17.16 seconds
Started Jul 04 07:12:09 PM PDT 24
Finished Jul 04 07:12:28 PM PDT 24
Peak memory 217792 kb
Host smart-576bc756-7fbb-4ac3-8f56-79bcdb8493bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136977262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.1136977262
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.3016921600
Short name T546
Test name
Test status
Simulation time 5989832831 ps
CPU time 17.22 seconds
Started Jul 04 07:12:06 PM PDT 24
Finished Jul 04 07:12:25 PM PDT 24
Peak memory 217260 kb
Host smart-411b00f3-f326-4491-996b-3bcfb58692e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016921600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.3016921600
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.3704050294
Short name T722
Test name
Test status
Simulation time 14100067498 ps
CPU time 85.68 seconds
Started Jul 04 07:12:06 PM PDT 24
Finished Jul 04 07:13:33 PM PDT 24
Peak memory 217876 kb
Host smart-9ed21d0a-4434-4e95-9654-53489552c3fd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704050294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.3704050294
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.3563224148
Short name T384
Test name
Test status
Simulation time 592714975 ps
CPU time 4.16 seconds
Started Jul 04 07:12:04 PM PDT 24
Finished Jul 04 07:12:09 PM PDT 24
Peak memory 217332 kb
Host smart-ee966295-39a7-42d5-9474-5b0f9af1abd3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563224148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.3
563224148
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.1589398073
Short name T114
Test name
Test status
Simulation time 224178514 ps
CPU time 4.43 seconds
Started Jul 04 07:12:08 PM PDT 24
Finished Jul 04 07:12:15 PM PDT 24
Peak memory 217736 kb
Host smart-95f7c1f3-567b-4836-9032-a96523c34097
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589398073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.1589398073
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.1205680100
Short name T753
Test name
Test status
Simulation time 3049704317 ps
CPU time 9.36 seconds
Started Jul 04 07:12:09 PM PDT 24
Finished Jul 04 07:12:21 PM PDT 24
Peak memory 217200 kb
Host smart-c56550a0-55e1-4d5b-9e57-2e818d2e56a8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205680100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.1205680100
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.4123356777
Short name T308
Test name
Test status
Simulation time 474481718 ps
CPU time 7.7 seconds
Started Jul 04 07:12:03 PM PDT 24
Finished Jul 04 07:12:12 PM PDT 24
Peak memory 217152 kb
Host smart-2b31bf71-6868-4636-8a8b-bcaed52aa3d8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123356777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
4123356777
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.80922838
Short name T323
Test name
Test status
Simulation time 2166774393 ps
CPU time 61.43 seconds
Started Jul 04 07:12:05 PM PDT 24
Finished Jul 04 07:13:07 PM PDT 24
Peak memory 266928 kb
Host smart-764fee84-8084-459d-a4f7-d44f35132a90
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80922838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_
state_failure.80922838
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.2635678321
Short name T764
Test name
Test status
Simulation time 339564588 ps
CPU time 11.32 seconds
Started Jul 04 07:12:05 PM PDT 24
Finished Jul 04 07:12:17 PM PDT 24
Peak memory 250460 kb
Host smart-083c11d6-8095-49a3-b703-299a22eedaeb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635678321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.2635678321
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.1294114753
Short name T86
Test name
Test status
Simulation time 982884406 ps
CPU time 13.47 seconds
Started Jul 04 07:12:05 PM PDT 24
Finished Jul 04 07:12:20 PM PDT 24
Peak memory 214104 kb
Host smart-e9d8d0d4-e681-48ea-9ec9-a6dc4ef7bba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294114753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.1294114753
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.579161457
Short name T689
Test name
Test status
Simulation time 1631178448 ps
CPU time 15.83 seconds
Started Jul 04 07:12:03 PM PDT 24
Finished Jul 04 07:12:20 PM PDT 24
Peak memory 218428 kb
Host smart-fcfe6077-3937-4cb0-8e0d-48501f39cdd8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579161457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.579161457
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.1353620598
Short name T830
Test name
Test status
Simulation time 228507264 ps
CPU time 7.34 seconds
Started Jul 04 07:12:06 PM PDT 24
Finished Jul 04 07:12:16 PM PDT 24
Peak memory 225520 kb
Host smart-9ab0032f-c3e9-4052-9a9b-f43300184442
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353620598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.1353620598
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.3928095239
Short name T782
Test name
Test status
Simulation time 518174396 ps
CPU time 9.42 seconds
Started Jul 04 07:12:10 PM PDT 24
Finished Jul 04 07:12:22 PM PDT 24
Peak memory 217696 kb
Host smart-37d3767f-00e6-47d5-9e52-69394aec8d11
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928095239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.3
928095239
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.868331078
Short name T697
Test name
Test status
Simulation time 371907049 ps
CPU time 8.68 seconds
Started Jul 04 07:12:02 PM PDT 24
Finished Jul 04 07:12:11 PM PDT 24
Peak memory 217864 kb
Host smart-5ff9a951-fa11-42ec-8aa4-1a4acade79c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868331078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.868331078
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.1146804132
Short name T383
Test name
Test status
Simulation time 99446779 ps
CPU time 3.5 seconds
Started Jul 04 07:12:04 PM PDT 24
Finished Jul 04 07:12:08 PM PDT 24
Peak memory 217208 kb
Host smart-e4b4d92c-6448-4608-ad83-4ede9e1dad6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146804132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.1146804132
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.110623766
Short name T844
Test name
Test status
Simulation time 4979360644 ps
CPU time 30.55 seconds
Started Jul 04 07:12:04 PM PDT 24
Finished Jul 04 07:12:35 PM PDT 24
Peak memory 250576 kb
Host smart-123d66cf-65be-422f-80db-b565b2ed16b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110623766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.110623766
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.1876490982
Short name T372
Test name
Test status
Simulation time 335466168 ps
CPU time 7.91 seconds
Started Jul 04 07:12:05 PM PDT 24
Finished Jul 04 07:12:14 PM PDT 24
Peak memory 250496 kb
Host smart-6463955f-a6ee-47c7-aa92-74846ba2afb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876490982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.1876490982
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.4202905585
Short name T724
Test name
Test status
Simulation time 9265242543 ps
CPU time 240.34 seconds
Started Jul 04 07:12:09 PM PDT 24
Finished Jul 04 07:16:12 PM PDT 24
Peak memory 225648 kb
Host smart-b91fbe55-ff05-44c9-a2c0-34b9a3912692
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202905585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.4202905585
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.3017709640
Short name T476
Test name
Test status
Simulation time 142398908 ps
CPU time 0.98 seconds
Started Jul 04 07:12:09 PM PDT 24
Finished Jul 04 07:12:12 PM PDT 24
Peak memory 211396 kb
Host smart-6f6eefc4-fba6-4479-ac82-afd069b6ce1e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017709640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.3017709640
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.4034662189
Short name T95
Test name
Test status
Simulation time 19493901 ps
CPU time 0.92 seconds
Started Jul 04 07:12:11 PM PDT 24
Finished Jul 04 07:12:14 PM PDT 24
Peak memory 208524 kb
Host smart-c5a61854-dad5-45f6-9d66-8d1034d0be16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034662189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.4034662189
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.3428967162
Short name T665
Test name
Test status
Simulation time 507933483 ps
CPU time 14.72 seconds
Started Jul 04 07:12:01 PM PDT 24
Finished Jul 04 07:12:16 PM PDT 24
Peak memory 225600 kb
Host smart-3637717e-c8de-407c-a2f4-9d12ecb5be41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428967162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.3428967162
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.3789859880
Short name T29
Test name
Test status
Simulation time 632828411 ps
CPU time 7.94 seconds
Started Jul 04 07:12:10 PM PDT 24
Finished Jul 04 07:12:21 PM PDT 24
Peak memory 217192 kb
Host smart-f752bbed-b793-4e69-87f2-03cd1e218c03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789859880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.3789859880
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.405743472
Short name T848
Test name
Test status
Simulation time 6014776770 ps
CPU time 26.67 seconds
Started Jul 04 07:12:10 PM PDT 24
Finished Jul 04 07:12:40 PM PDT 24
Peak memory 218564 kb
Host smart-2db8c3a2-8054-4a0d-88ce-a159ef5d200a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405743472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_err
ors.405743472
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.3209684516
Short name T278
Test name
Test status
Simulation time 3084009095 ps
CPU time 5.48 seconds
Started Jul 04 07:12:11 PM PDT 24
Finished Jul 04 07:12:19 PM PDT 24
Peak memory 217328 kb
Host smart-350be626-ad70-4a7d-9764-5a9709b3dd8c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209684516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.3
209684516
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.3839194375
Short name T647
Test name
Test status
Simulation time 181131023 ps
CPU time 5.92 seconds
Started Jul 04 07:12:09 PM PDT 24
Finished Jul 04 07:12:18 PM PDT 24
Peak memory 221228 kb
Host smart-48cde62c-e7eb-4320-9cb0-241b37d9b65d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839194375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.3839194375
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.3708175414
Short name T347
Test name
Test status
Simulation time 2309194113 ps
CPU time 8.48 seconds
Started Jul 04 07:12:09 PM PDT 24
Finished Jul 04 07:12:19 PM PDT 24
Peak memory 217324 kb
Host smart-056cecdc-192b-4b29-8184-b86a9d2685ce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708175414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.3708175414
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.3019573356
Short name T3
Test name
Test status
Simulation time 794930736 ps
CPU time 4.1 seconds
Started Jul 04 07:12:09 PM PDT 24
Finished Jul 04 07:12:16 PM PDT 24
Peak memory 217260 kb
Host smart-9b5331a4-c907-47c9-b1c8-ee6569980e28
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019573356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
3019573356
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.3983035428
Short name T118
Test name
Test status
Simulation time 15286307130 ps
CPU time 114.61 seconds
Started Jul 04 07:12:08 PM PDT 24
Finished Jul 04 07:14:04 PM PDT 24
Peak memory 283280 kb
Host smart-51ef1443-7f56-43c1-9f9b-f88aa049427e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983035428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.3983035428
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.802322633
Short name T617
Test name
Test status
Simulation time 598713875 ps
CPU time 9.33 seconds
Started Jul 04 07:12:10 PM PDT 24
Finished Jul 04 07:12:22 PM PDT 24
Peak memory 222456 kb
Host smart-09975c11-6ec2-4ae8-9881-9d94e0357cae
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802322633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_j
tag_state_post_trans.802322633
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.873816520
Short name T356
Test name
Test status
Simulation time 30907669 ps
CPU time 2.09 seconds
Started Jul 04 07:12:05 PM PDT 24
Finished Jul 04 07:12:09 PM PDT 24
Peak memory 217676 kb
Host smart-3108ac19-ac76-4587-af8f-f9d3be6e50eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873816520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.873816520
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.3169500916
Short name T698
Test name
Test status
Simulation time 1132730907 ps
CPU time 14.02 seconds
Started Jul 04 07:12:03 PM PDT 24
Finished Jul 04 07:12:17 PM PDT 24
Peak memory 217212 kb
Host smart-732eb76d-90ff-43df-9e22-b750d139a246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169500916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.3169500916
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.1954331722
Short name T101
Test name
Test status
Simulation time 590735449 ps
CPU time 23.52 seconds
Started Jul 04 07:12:13 PM PDT 24
Finished Jul 04 07:12:39 PM PDT 24
Peak memory 269200 kb
Host smart-ba1e315b-7fbc-4066-8cb5-1a543f4cc9a9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954331722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.1954331722
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.3310493112
Short name T376
Test name
Test status
Simulation time 175379228 ps
CPU time 8.31 seconds
Started Jul 04 07:12:10 PM PDT 24
Finished Jul 04 07:12:21 PM PDT 24
Peak memory 225492 kb
Host smart-8099b544-5df0-418c-8122-239790277e40
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310493112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.3310493112
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.81577420
Short name T414
Test name
Test status
Simulation time 1501659976 ps
CPU time 8.56 seconds
Started Jul 04 07:12:09 PM PDT 24
Finished Jul 04 07:12:20 PM PDT 24
Peak memory 225560 kb
Host smart-ed140ab7-e712-440c-863c-d16c04cfdfad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81577420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.81577420
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.3760227888
Short name T657
Test name
Test status
Simulation time 341121770 ps
CPU time 3.32 seconds
Started Jul 04 07:12:05 PM PDT 24
Finished Jul 04 07:12:10 PM PDT 24
Peak memory 217172 kb
Host smart-5ed840d9-8c74-4c6e-b9c3-648023736513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760227888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.3760227888
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.3375268086
Short name T99
Test name
Test status
Simulation time 239862433 ps
CPU time 21.06 seconds
Started Jul 04 07:12:06 PM PDT 24
Finished Jul 04 07:12:29 PM PDT 24
Peak memory 250600 kb
Host smart-736bb408-9596-4b2f-8568-88a04145f4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375268086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.3375268086
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.2949273325
Short name T791
Test name
Test status
Simulation time 58313776 ps
CPU time 6.41 seconds
Started Jul 04 07:12:02 PM PDT 24
Finished Jul 04 07:12:08 PM PDT 24
Peak memory 250092 kb
Host smart-1a7eda8e-b276-40fe-aea2-0d2e1ebf434a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949273325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.2949273325
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.1659586482
Short name T121
Test name
Test status
Simulation time 18231703836 ps
CPU time 70.14 seconds
Started Jul 04 07:12:09 PM PDT 24
Finished Jul 04 07:13:22 PM PDT 24
Peak memory 225636 kb
Host smart-a72dbff3-1334-462d-a862-46e12c6ab1b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659586482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.1659586482
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2332133580
Short name T746
Test name
Test status
Simulation time 11466586 ps
CPU time 0.85 seconds
Started Jul 04 07:12:08 PM PDT 24
Finished Jul 04 07:12:11 PM PDT 24
Peak memory 207796 kb
Host smart-510d470d-a17c-4bad-8306-399d1713c46c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332133580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.2332133580
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.2905320207
Short name T562
Test name
Test status
Simulation time 28097134 ps
CPU time 1.02 seconds
Started Jul 04 07:12:41 PM PDT 24
Finished Jul 04 07:13:10 PM PDT 24
Peak memory 208496 kb
Host smart-7be1a23b-6637-4a6d-a3e4-531a5aac4ba3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905320207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.2905320207
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.353488044
Short name T508
Test name
Test status
Simulation time 270984497 ps
CPU time 10.32 seconds
Started Jul 04 07:12:40 PM PDT 24
Finished Jul 04 07:13:17 PM PDT 24
Peak memory 217776 kb
Host smart-4418b866-eab4-48fe-94e7-03145470bfde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353488044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.353488044
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.2057183142
Short name T593
Test name
Test status
Simulation time 239634415 ps
CPU time 5.23 seconds
Started Jul 04 07:12:42 PM PDT 24
Finished Jul 04 07:13:15 PM PDT 24
Peak memory 222816 kb
Host smart-c465c29e-8b33-4f3c-b547-cac435c65fc1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057183142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.2057183142
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.512113500
Short name T92
Test name
Test status
Simulation time 1339488460 ps
CPU time 3.96 seconds
Started Jul 04 07:12:41 PM PDT 24
Finished Jul 04 07:13:13 PM PDT 24
Peak memory 217164 kb
Host smart-86e1ae06-0d68-41d6-acb9-ac87e34ecea6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512113500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke.
512113500
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.47393536
Short name T38
Test name
Test status
Simulation time 18396674700 ps
CPU time 91.15 seconds
Started Jul 04 07:12:39 PM PDT 24
Finished Jul 04 07:14:38 PM PDT 24
Peak memory 283280 kb
Host smart-072e1a24-e555-4a87-9c10-5ca86baa0085
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47393536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag
_state_failure.47393536
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.815237427
Short name T422
Test name
Test status
Simulation time 813015557 ps
CPU time 15.53 seconds
Started Jul 04 07:12:38 PM PDT 24
Finished Jul 04 07:13:20 PM PDT 24
Peak memory 249848 kb
Host smart-5a0aadc2-e0dd-4c5c-a2c0-80469ea69afc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815237427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_
jtag_state_post_trans.815237427
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.3930823599
Short name T270
Test name
Test status
Simulation time 86199049 ps
CPU time 4.15 seconds
Started Jul 04 07:12:38 PM PDT 24
Finished Jul 04 07:13:08 PM PDT 24
Peak memory 217776 kb
Host smart-0a7917de-b7de-46a9-baa7-bd650b89dc14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930823599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.3930823599
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.3084674203
Short name T206
Test name
Test status
Simulation time 462731855 ps
CPU time 18.45 seconds
Started Jul 04 07:12:42 PM PDT 24
Finished Jul 04 07:13:28 PM PDT 24
Peak memory 225568 kb
Host smart-307f3ae0-de45-4e1c-9290-c1462018f5ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084674203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.3084674203
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.1324072008
Short name T859
Test name
Test status
Simulation time 1448017404 ps
CPU time 14.28 seconds
Started Jul 04 07:12:40 PM PDT 24
Finished Jul 04 07:13:22 PM PDT 24
Peak memory 217772 kb
Host smart-f95f5771-dea9-49ac-8ae3-945af1dc83e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324072008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.1324072008
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.1341383681
Short name T380
Test name
Test status
Simulation time 1473874389 ps
CPU time 10.93 seconds
Started Jul 04 07:12:40 PM PDT 24
Finished Jul 04 07:13:18 PM PDT 24
Peak memory 225524 kb
Host smart-f9b24e5f-4bd6-460a-afc2-70da63023397
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341383681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
1341383681
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.2246942632
Short name T797
Test name
Test status
Simulation time 5246501741 ps
CPU time 9.49 seconds
Started Jul 04 07:12:40 PM PDT 24
Finished Jul 04 07:13:17 PM PDT 24
Peak memory 225636 kb
Host smart-b5326cb4-cad7-437c-b36d-b27b1de0e350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246942632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.2246942632
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.1927897164
Short name T112
Test name
Test status
Simulation time 80084424 ps
CPU time 2.61 seconds
Started Jul 04 07:12:36 PM PDT 24
Finished Jul 04 07:13:04 PM PDT 24
Peak memory 217264 kb
Host smart-9a7e0dff-3eb8-4cee-8f53-bc9a1ebd11e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927897164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.1927897164
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.1939440607
Short name T622
Test name
Test status
Simulation time 202066990 ps
CPU time 24.53 seconds
Started Jul 04 07:12:38 PM PDT 24
Finished Jul 04 07:13:29 PM PDT 24
Peak memory 250400 kb
Host smart-daabb4a5-8956-4c1d-8285-70be6d1b186b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939440607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.1939440607
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.2724790571
Short name T291
Test name
Test status
Simulation time 321150684 ps
CPU time 4.11 seconds
Started Jul 04 07:12:42 PM PDT 24
Finished Jul 04 07:13:14 PM PDT 24
Peak memory 225964 kb
Host smart-076240ee-9038-4a6b-b3e0-85425063dbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724790571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.2724790571
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.1243330213
Short name T55
Test name
Test status
Simulation time 15719022887 ps
CPU time 395 seconds
Started Jul 04 07:12:41 PM PDT 24
Finished Jul 04 07:19:44 PM PDT 24
Peak memory 262836 kb
Host smart-68f4a578-13c8-4291-a1b4-5ac7dcf7019d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243330213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.1243330213
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.3464471968
Short name T618
Test name
Test status
Simulation time 24175740277 ps
CPU time 400.96 seconds
Started Jul 04 07:12:43 PM PDT 24
Finished Jul 04 07:19:51 PM PDT 24
Peak memory 316288 kb
Host smart-2edf085b-c761-423a-82dd-4495df0be4c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3464471968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.3464471968
Directory /workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.1964262915
Short name T377
Test name
Test status
Simulation time 15420547 ps
CPU time 1 seconds
Started Jul 04 07:12:40 PM PDT 24
Finished Jul 04 07:13:08 PM PDT 24
Peak memory 208464 kb
Host smart-4ae68577-408c-41a3-a021-a07ce4a5eac5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964262915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.1964262915
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.2266871686
Short name T84
Test name
Test status
Simulation time 70057055 ps
CPU time 1.03 seconds
Started Jul 04 07:12:49 PM PDT 24
Finished Jul 04 07:13:18 PM PDT 24
Peak memory 208476 kb
Host smart-16445025-cb17-487d-b3a5-2d864b677294
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266871686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.2266871686
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.3094589462
Short name T500
Test name
Test status
Simulation time 675812834 ps
CPU time 14.07 seconds
Started Jul 04 07:12:40 PM PDT 24
Finished Jul 04 07:13:21 PM PDT 24
Peak memory 217764 kb
Host smart-09944713-dec8-4440-8a6c-ff964c9c370b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094589462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.3094589462
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.2519864748
Short name T528
Test name
Test status
Simulation time 224714731 ps
CPU time 3.67 seconds
Started Jul 04 07:12:43 PM PDT 24
Finished Jul 04 07:13:14 PM PDT 24
Peak memory 217220 kb
Host smart-7d35e4b8-6ba1-480f-af36-c65ca3977836
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519864748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.2519864748
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.2800088140
Short name T416
Test name
Test status
Simulation time 9647840015 ps
CPU time 34.73 seconds
Started Jul 04 07:12:43 PM PDT 24
Finished Jul 04 07:13:45 PM PDT 24
Peak memory 218268 kb
Host smart-48bdb55a-5b1d-4683-9146-6c972a5bed77
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800088140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.2800088140
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.3008136852
Short name T385
Test name
Test status
Simulation time 309469011 ps
CPU time 8.77 seconds
Started Jul 04 07:12:41 PM PDT 24
Finished Jul 04 07:13:18 PM PDT 24
Peak memory 217768 kb
Host smart-dbceb8c3-98ae-4da8-8cf4-dd08522ef8d0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008136852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.3008136852
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.421017897
Short name T814
Test name
Test status
Simulation time 1232601047 ps
CPU time 4.16 seconds
Started Jul 04 07:12:42 PM PDT 24
Finished Jul 04 07:13:14 PM PDT 24
Peak memory 217084 kb
Host smart-d0e925e3-b216-40f3-bae1-b095274a47ab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421017897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke.
421017897
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.3235531767
Short name T686
Test name
Test status
Simulation time 4648344553 ps
CPU time 48.88 seconds
Started Jul 04 07:12:43 PM PDT 24
Finished Jul 04 07:13:59 PM PDT 24
Peak memory 283304 kb
Host smart-2087cf19-6543-4f5d-bf71-81d31fe22048
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235531767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.3235531767
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.3609865083
Short name T292
Test name
Test status
Simulation time 1783018764 ps
CPU time 18.49 seconds
Started Jul 04 07:12:42 PM PDT 24
Finished Jul 04 07:13:28 PM PDT 24
Peak memory 249724 kb
Host smart-e57b91d4-e541-4f1c-aed5-6942abaa586e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609865083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.3609865083
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.2065139156
Short name T311
Test name
Test status
Simulation time 122058781 ps
CPU time 2.2 seconds
Started Jul 04 07:12:41 PM PDT 24
Finished Jul 04 07:13:10 PM PDT 24
Peak memory 217792 kb
Host smart-bff33d34-1b23-4ad2-9f72-c0cc35bba585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065139156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.2065139156
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.1219586635
Short name T603
Test name
Test status
Simulation time 358213108 ps
CPU time 15.55 seconds
Started Jul 04 07:12:43 PM PDT 24
Finished Jul 04 07:13:26 PM PDT 24
Peak memory 225556 kb
Host smart-1eec8c50-365f-40ab-a47f-38baa2ad366a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219586635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.1219586635
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.2963793831
Short name T597
Test name
Test status
Simulation time 2004759016 ps
CPU time 13.57 seconds
Started Jul 04 07:12:42 PM PDT 24
Finished Jul 04 07:13:23 PM PDT 24
Peak memory 225460 kb
Host smart-6667e234-ac43-4e8a-b888-3083840661d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963793831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.2963793831
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.860418326
Short name T196
Test name
Test status
Simulation time 584096174 ps
CPU time 7.5 seconds
Started Jul 04 07:12:42 PM PDT 24
Finished Jul 04 07:13:17 PM PDT 24
Peak memory 225540 kb
Host smart-d83da103-773d-46cd-8b3d-5650da50d218
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860418326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.860418326
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.1326610301
Short name T541
Test name
Test status
Simulation time 182184441 ps
CPU time 8.08 seconds
Started Jul 04 07:12:42 PM PDT 24
Finished Jul 04 07:13:18 PM PDT 24
Peak memory 217812 kb
Host smart-e14ba563-6c55-4c58-b4ea-91a1f88f4675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326610301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.1326610301
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.3605645180
Short name T344
Test name
Test status
Simulation time 27039888 ps
CPU time 2.33 seconds
Started Jul 04 07:12:40 PM PDT 24
Finished Jul 04 07:13:10 PM PDT 24
Peak memory 213580 kb
Host smart-61849648-d911-4c45-a9f8-54f6dd03c55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605645180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.3605645180
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.1030218981
Short name T445
Test name
Test status
Simulation time 1247758109 ps
CPU time 26.93 seconds
Started Jul 04 07:12:41 PM PDT 24
Finished Jul 04 07:13:36 PM PDT 24
Peak memory 250520 kb
Host smart-c0acad61-717f-4570-8d1a-eeb1be187d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030218981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.1030218981
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.1570636667
Short name T47
Test name
Test status
Simulation time 401346046 ps
CPU time 11.27 seconds
Started Jul 04 07:12:41 PM PDT 24
Finished Jul 04 07:13:21 PM PDT 24
Peak memory 250592 kb
Host smart-d1996503-24e9-4bf3-9201-b0f7251e4e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570636667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.1570636667
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.1762440375
Short name T429
Test name
Test status
Simulation time 3081303949 ps
CPU time 117.36 seconds
Started Jul 04 07:12:41 PM PDT 24
Finished Jul 04 07:15:07 PM PDT 24
Peak memory 421560 kb
Host smart-83ddc717-3dac-4844-acfe-71e4d68ef4a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762440375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.1762440375
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.676622305
Short name T185
Test name
Test status
Simulation time 15303250 ps
CPU time 0.97 seconds
Started Jul 04 07:12:43 PM PDT 24
Finished Jul 04 07:13:11 PM PDT 24
Peak memory 208476 kb
Host smart-af114de4-0005-41a4-bcd4-2f370341a867
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676622305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ct
rl_volatile_unlock_smoke.676622305
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.2594066301
Short name T261
Test name
Test status
Simulation time 22844598 ps
CPU time 1.25 seconds
Started Jul 04 07:12:49 PM PDT 24
Finished Jul 04 07:13:20 PM PDT 24
Peak memory 208612 kb
Host smart-b703e180-02ec-453b-9f3c-55f1139c47bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594066301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.2594066301
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.3836045730
Short name T439
Test name
Test status
Simulation time 735681119 ps
CPU time 16.47 seconds
Started Jul 04 07:12:46 PM PDT 24
Finished Jul 04 07:13:31 PM PDT 24
Peak memory 225576 kb
Host smart-714fedc8-2d32-4a42-9329-0d7e2bb8af1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836045730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.3836045730
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.2656104528
Short name T736
Test name
Test status
Simulation time 72103112 ps
CPU time 2.51 seconds
Started Jul 04 07:12:49 PM PDT 24
Finished Jul 04 07:13:20 PM PDT 24
Peak memory 217208 kb
Host smart-449619cb-ac7b-4361-9052-168a1d8df5e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656104528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.2656104528
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.2633486175
Short name T712
Test name
Test status
Simulation time 6295519082 ps
CPU time 39.89 seconds
Started Jul 04 07:12:48 PM PDT 24
Finished Jul 04 07:13:57 PM PDT 24
Peak memory 218276 kb
Host smart-9fa15be3-aeb2-4efd-85d4-462a3fa492c3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633486175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.2633486175
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.1791894937
Short name T599
Test name
Test status
Simulation time 243690368 ps
CPU time 1.96 seconds
Started Jul 04 07:12:49 PM PDT 24
Finished Jul 04 07:13:19 PM PDT 24
Peak memory 217692 kb
Host smart-7922b405-4934-4367-be9d-696dd9cb5b30
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791894937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.1791894937
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.3275467635
Short name T287
Test name
Test status
Simulation time 307098789 ps
CPU time 5.09 seconds
Started Jul 04 07:12:49 PM PDT 24
Finished Jul 04 07:13:23 PM PDT 24
Peak memory 217116 kb
Host smart-e79797fb-4575-44d4-acf0-469f30594168
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275467635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.3275467635
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.1977981708
Short name T652
Test name
Test status
Simulation time 42468246488 ps
CPU time 100.6 seconds
Started Jul 04 07:12:49 PM PDT 24
Finished Jul 04 07:14:58 PM PDT 24
Peak memory 278048 kb
Host smart-99d9adf9-77c1-4557-8642-c547014191b0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977981708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.1977981708
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.3312823250
Short name T22
Test name
Test status
Simulation time 1543549913 ps
CPU time 11.82 seconds
Started Jul 04 07:12:48 PM PDT 24
Finished Jul 04 07:13:29 PM PDT 24
Peak memory 245936 kb
Host smart-b2561f4c-8a68-4e5e-bc5c-c0bf8430d618
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312823250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.3312823250
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.733089437
Short name T714
Test name
Test status
Simulation time 42703405 ps
CPU time 2.55 seconds
Started Jul 04 07:12:51 PM PDT 24
Finished Jul 04 07:13:22 PM PDT 24
Peak memory 217808 kb
Host smart-2cbae4e0-4125-499a-a446-6406c318c973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733089437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.733089437
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.494284882
Short name T534
Test name
Test status
Simulation time 699689685 ps
CPU time 17.69 seconds
Started Jul 04 07:12:55 PM PDT 24
Finished Jul 04 07:13:41 PM PDT 24
Peak memory 219516 kb
Host smart-d4207b54-d9e7-4620-83af-687f786fc27d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494284882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.494284882
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.497463600
Short name T786
Test name
Test status
Simulation time 970590224 ps
CPU time 9.55 seconds
Started Jul 04 07:12:49 PM PDT 24
Finished Jul 04 07:13:27 PM PDT 24
Peak memory 225520 kb
Host smart-e392be51-824e-4d58-a8d0-c250e3498acc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497463600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_di
gest.497463600
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.2368685267
Short name T775
Test name
Test status
Simulation time 487448424 ps
CPU time 9.4 seconds
Started Jul 04 07:12:51 PM PDT 24
Finished Jul 04 07:13:30 PM PDT 24
Peak memory 217728 kb
Host smart-442a7e60-c0f6-44c2-8ddd-7c67406460bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368685267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
2368685267
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.1904541747
Short name T760
Test name
Test status
Simulation time 606108895 ps
CPU time 9.55 seconds
Started Jul 04 07:12:55 PM PDT 24
Finished Jul 04 07:13:33 PM PDT 24
Peak memory 217832 kb
Host smart-327abab3-bec5-40f3-b5e9-399cc0530556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904541747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.1904541747
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.2169840882
Short name T766
Test name
Test status
Simulation time 26450432 ps
CPU time 1 seconds
Started Jul 04 07:12:49 PM PDT 24
Finished Jul 04 07:13:18 PM PDT 24
Peak memory 211488 kb
Host smart-a5b92d60-6c6e-41fb-aa7b-eb666b3ecfb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169840882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.2169840882
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.2868186136
Short name T692
Test name
Test status
Simulation time 166993965 ps
CPU time 19.06 seconds
Started Jul 04 07:12:57 PM PDT 24
Finished Jul 04 07:13:45 PM PDT 24
Peak memory 250584 kb
Host smart-a96bf6ed-ad90-4317-b2a2-ef4218b9743c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868186136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.2868186136
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.2484164514
Short name T819
Test name
Test status
Simulation time 612361917 ps
CPU time 8.34 seconds
Started Jul 04 07:12:48 PM PDT 24
Finished Jul 04 07:13:26 PM PDT 24
Peak memory 246648 kb
Host smart-e7b60a19-3095-4bca-b825-d8fad7fdc86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484164514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.2484164514
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.4019130628
Short name T856
Test name
Test status
Simulation time 11504864623 ps
CPU time 390.44 seconds
Started Jul 04 07:12:49 PM PDT 24
Finished Jul 04 07:19:48 PM PDT 24
Peak memory 267464 kb
Host smart-ecafc31e-870b-409a-8cb9-76cfbc3291c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019130628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.4019130628
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.3553828416
Short name T176
Test name
Test status
Simulation time 9333314287 ps
CPU time 214.29 seconds
Started Jul 04 07:12:50 PM PDT 24
Finished Jul 04 07:16:54 PM PDT 24
Peak memory 283500 kb
Host smart-315c456d-5076-4173-9980-10fb8227df75
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3553828416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all_with_rand_reset.3553828416
Directory /workspace/12.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.266063828
Short name T375
Test name
Test status
Simulation time 40982730 ps
CPU time 0.87 seconds
Started Jul 04 07:12:49 PM PDT 24
Finished Jul 04 07:13:18 PM PDT 24
Peak memory 207832 kb
Host smart-eff4d914-9ddf-42d6-bc0e-6754459a1219
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266063828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ct
rl_volatile_unlock_smoke.266063828
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.1731491599
Short name T79
Test name
Test status
Simulation time 83649887 ps
CPU time 0.86 seconds
Started Jul 04 07:12:55 PM PDT 24
Finished Jul 04 07:13:24 PM PDT 24
Peak memory 208560 kb
Host smart-d01831a7-6aa4-48ad-aa1d-be0b1495ccaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731491599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.1731491599
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.2062944486
Short name T305
Test name
Test status
Simulation time 313530051 ps
CPU time 10.78 seconds
Started Jul 04 07:12:53 PM PDT 24
Finished Jul 04 07:13:32 PM PDT 24
Peak memory 217776 kb
Host smart-5b15d450-e48a-458c-8355-a098f63e7bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062944486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.2062944486
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.2115694928
Short name T587
Test name
Test status
Simulation time 1681863692 ps
CPU time 11.69 seconds
Started Jul 04 07:12:57 PM PDT 24
Finished Jul 04 07:13:37 PM PDT 24
Peak memory 216844 kb
Host smart-d94decf0-8a52-448d-aba3-5306d757ff0b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115694928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.2115694928
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.278926190
Short name T322
Test name
Test status
Simulation time 8242928635 ps
CPU time 38.06 seconds
Started Jul 04 07:12:57 PM PDT 24
Finished Jul 04 07:14:04 PM PDT 24
Peak memory 217724 kb
Host smart-4d990a35-0d64-453e-827a-fbdf99a9c7c0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278926190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_er
rors.278926190
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.1119802035
Short name T358
Test name
Test status
Simulation time 78238944 ps
CPU time 2.16 seconds
Started Jul 04 07:12:54 PM PDT 24
Finished Jul 04 07:13:26 PM PDT 24
Peak memory 217704 kb
Host smart-1a9ba3c3-53cf-40dd-bca4-6ad5637e018c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119802035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.1119802035
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.3112893584
Short name T341
Test name
Test status
Simulation time 834735014 ps
CPU time 5.32 seconds
Started Jul 04 07:12:55 PM PDT 24
Finished Jul 04 07:13:29 PM PDT 24
Peak memory 217136 kb
Host smart-092e18f4-8acf-44c2-8055-4eb5a6abb3b9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112893584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.3112893584
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.3257959178
Short name T428
Test name
Test status
Simulation time 1019526894 ps
CPU time 40.27 seconds
Started Jul 04 07:12:56 PM PDT 24
Finished Jul 04 07:14:06 PM PDT 24
Peak memory 251216 kb
Host smart-7e50a945-004d-40ad-9c12-d61c68be3cf3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257959178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.3257959178
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.2164133268
Short name T495
Test name
Test status
Simulation time 1409439579 ps
CPU time 15.02 seconds
Started Jul 04 07:12:58 PM PDT 24
Finished Jul 04 07:13:41 PM PDT 24
Peak memory 250112 kb
Host smart-8652630c-96da-482a-9cb8-7da91a436357
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164133268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.2164133268
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.4110056521
Short name T402
Test name
Test status
Simulation time 50888579 ps
CPU time 2.5 seconds
Started Jul 04 07:12:49 PM PDT 24
Finished Jul 04 07:13:20 PM PDT 24
Peak memory 221956 kb
Host smart-990aa6bf-5898-4afb-8444-d489df3d823c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110056521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.4110056521
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.831012108
Short name T274
Test name
Test status
Simulation time 589487667 ps
CPU time 12.2 seconds
Started Jul 04 07:13:00 PM PDT 24
Finished Jul 04 07:13:41 PM PDT 24
Peak memory 225500 kb
Host smart-e2857908-62ea-43a7-ab03-a13928c7b875
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831012108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_di
gest.831012108
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.2490149416
Short name T566
Test name
Test status
Simulation time 382024331 ps
CPU time 13.16 seconds
Started Jul 04 07:12:55 PM PDT 24
Finished Jul 04 07:13:37 PM PDT 24
Peak memory 217756 kb
Host smart-92b64cf0-c3b0-4d4d-8110-5d405fdc99af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490149416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
2490149416
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.626838495
Short name T812
Test name
Test status
Simulation time 249907697 ps
CPU time 7.75 seconds
Started Jul 04 07:12:57 PM PDT 24
Finished Jul 04 07:13:34 PM PDT 24
Peak memory 224816 kb
Host smart-cb26ddc9-8589-4c37-8831-a01027790cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626838495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.626838495
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.1002262259
Short name T670
Test name
Test status
Simulation time 512356001 ps
CPU time 5.65 seconds
Started Jul 04 07:12:48 PM PDT 24
Finished Jul 04 07:13:23 PM PDT 24
Peak memory 217188 kb
Host smart-a027dfae-8f79-457d-991d-bb6c7c939409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002262259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.1002262259
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.3655867944
Short name T294
Test name
Test status
Simulation time 1489954232 ps
CPU time 26.73 seconds
Started Jul 04 07:12:51 PM PDT 24
Finished Jul 04 07:13:48 PM PDT 24
Peak memory 250556 kb
Host smart-cf5c8a6e-a315-40e6-aa13-14d219ab5fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655867944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.3655867944
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.2183313397
Short name T461
Test name
Test status
Simulation time 280339497 ps
CPU time 2.72 seconds
Started Jul 04 07:12:50 PM PDT 24
Finished Jul 04 07:13:22 PM PDT 24
Peak memory 217784 kb
Host smart-bbefca6a-a6b2-438e-b63e-6b490b279df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183313397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.2183313397
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.813933217
Short name T639
Test name
Test status
Simulation time 4729273993 ps
CPU time 108.35 seconds
Started Jul 04 07:12:58 PM PDT 24
Finished Jul 04 07:15:15 PM PDT 24
Peak memory 278572 kb
Host smart-5454ab72-5565-477d-8a03-91b06a053386
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813933217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.813933217
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.1573665397
Short name T70
Test name
Test status
Simulation time 30495596846 ps
CPU time 591.18 seconds
Started Jul 04 07:12:57 PM PDT 24
Finished Jul 04 07:23:17 PM PDT 24
Peak memory 332692 kb
Host smart-aa94854e-7344-47bf-8e12-35694646a394
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1573665397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.1573665397
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.437899570
Short name T773
Test name
Test status
Simulation time 27878818 ps
CPU time 0.78 seconds
Started Jul 04 07:12:49 PM PDT 24
Finished Jul 04 07:13:18 PM PDT 24
Peak memory 208564 kb
Host smart-712e2a33-7e29-4c5c-98d2-66a77547ea0e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437899570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ct
rl_volatile_unlock_smoke.437899570
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.1828796444
Short name T539
Test name
Test status
Simulation time 18707360 ps
CPU time 1.13 seconds
Started Jul 04 07:13:03 PM PDT 24
Finished Jul 04 07:13:33 PM PDT 24
Peak memory 208480 kb
Host smart-f7920e32-fec1-41e7-af86-ba7e674ae6e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828796444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.1828796444
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.1548387731
Short name T64
Test name
Test status
Simulation time 2178740505 ps
CPU time 13.26 seconds
Started Jul 04 07:12:57 PM PDT 24
Finished Jul 04 07:13:39 PM PDT 24
Peak memory 217832 kb
Host smart-1648c90e-63bf-4ef0-8c4c-2409c244755b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548387731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.1548387731
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.2228374343
Short name T510
Test name
Test status
Simulation time 4677957142 ps
CPU time 14.74 seconds
Started Jul 04 07:13:01 PM PDT 24
Finished Jul 04 07:13:44 PM PDT 24
Peak memory 217288 kb
Host smart-3c68d237-4869-4a72-a493-e12ec38c117c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228374343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.2228374343
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.2491176376
Short name T100
Test name
Test status
Simulation time 2056414389 ps
CPU time 34.39 seconds
Started Jul 04 07:13:05 PM PDT 24
Finished Jul 04 07:14:10 PM PDT 24
Peak memory 218716 kb
Host smart-32db1b8f-e439-4a7e-a703-325b42644ebb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491176376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.2491176376
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.2332582909
Short name T710
Test name
Test status
Simulation time 1768273137 ps
CPU time 15.25 seconds
Started Jul 04 07:12:55 PM PDT 24
Finished Jul 04 07:13:39 PM PDT 24
Peak memory 222832 kb
Host smart-7c56c9f3-fde0-4702-8d63-57ec778fb660
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332582909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.2332582909
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.976553211
Short name T470
Test name
Test status
Simulation time 1627982084 ps
CPU time 17.02 seconds
Started Jul 04 07:12:59 PM PDT 24
Finished Jul 04 07:13:46 PM PDT 24
Peak memory 217116 kb
Host smart-fa378b3f-c674-4aa0-9d0e-697c66e18bbf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976553211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke.
976553211
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.3465487850
Short name T723
Test name
Test status
Simulation time 1359022932 ps
CPU time 45.38 seconds
Started Jul 04 07:12:55 PM PDT 24
Finished Jul 04 07:14:09 PM PDT 24
Peak memory 275148 kb
Host smart-9a976d5f-e32f-4a03-8743-bc87c68245e6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465487850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.3465487850
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.2829553742
Short name T804
Test name
Test status
Simulation time 1938291965 ps
CPU time 14.93 seconds
Started Jul 04 07:12:57 PM PDT 24
Finished Jul 04 07:13:41 PM PDT 24
Peak memory 223816 kb
Host smart-3bc6b61b-567f-45ca-b0a5-cca3b65cc2f7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829553742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.2829553742
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.1282805130
Short name T779
Test name
Test status
Simulation time 24071073 ps
CPU time 1.56 seconds
Started Jul 04 07:12:57 PM PDT 24
Finished Jul 04 07:13:27 PM PDT 24
Peak memory 217772 kb
Host smart-1eec37a8-c4f5-452b-9ac2-f3f9d7f0f701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282805130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.1282805130
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.2244332676
Short name T590
Test name
Test status
Simulation time 331466328 ps
CPU time 14.51 seconds
Started Jul 04 07:13:02 PM PDT 24
Finished Jul 04 07:13:46 PM PDT 24
Peak memory 218424 kb
Host smart-665ba7be-08cf-4741-a8b2-9df629b10884
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244332676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.2244332676
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.3107563415
Short name T379
Test name
Test status
Simulation time 930744962 ps
CPU time 9.78 seconds
Started Jul 04 07:13:00 PM PDT 24
Finished Jul 04 07:13:39 PM PDT 24
Peak memory 225336 kb
Host smart-101b3bde-50ce-465f-b98b-79a6211c7117
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107563415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.3107563415
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.1629789927
Short name T834
Test name
Test status
Simulation time 353512844 ps
CPU time 9.4 seconds
Started Jul 04 07:13:01 PM PDT 24
Finished Jul 04 07:13:38 PM PDT 24
Peak memory 217740 kb
Host smart-c5fcb128-178e-4ab2-9d8e-125058f08984
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629789927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
1629789927
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.1965745576
Short name T778
Test name
Test status
Simulation time 1236420147 ps
CPU time 13.03 seconds
Started Jul 04 07:12:59 PM PDT 24
Finished Jul 04 07:13:42 PM PDT 24
Peak memory 217828 kb
Host smart-2553b75b-d911-4e5d-8936-f7dc83bc84cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965745576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.1965745576
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.1957153963
Short name T838
Test name
Test status
Simulation time 221699088 ps
CPU time 2.21 seconds
Started Jul 04 07:12:55 PM PDT 24
Finished Jul 04 07:13:26 PM PDT 24
Peak memory 213908 kb
Host smart-4ce329d4-701e-4133-ad91-4694d7b731e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957153963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.1957153963
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.2455304909
Short name T781
Test name
Test status
Simulation time 348760835 ps
CPU time 28.04 seconds
Started Jul 04 07:12:59 PM PDT 24
Finished Jul 04 07:13:57 PM PDT 24
Peak memory 250500 kb
Host smart-1a5fd707-a993-4ac8-90be-b538fd1d4476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455304909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.2455304909
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.2028569290
Short name T5
Test name
Test status
Simulation time 1229316437 ps
CPU time 7.22 seconds
Started Jul 04 07:12:55 PM PDT 24
Finished Jul 04 07:13:31 PM PDT 24
Peak memory 246788 kb
Host smart-8fd2d4f6-59d3-477a-b66d-1fbc4eb94303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028569290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.2028569290
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.3990055060
Short name T573
Test name
Test status
Simulation time 36558808489 ps
CPU time 192.36 seconds
Started Jul 04 07:13:02 PM PDT 24
Finished Jul 04 07:16:44 PM PDT 24
Peak memory 273168 kb
Host smart-6d52bbbf-1d7b-4386-9cf3-153e241d555f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990055060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.3990055060
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.3795641065
Short name T318
Test name
Test status
Simulation time 130249907 ps
CPU time 1.01 seconds
Started Jul 04 07:12:54 PM PDT 24
Finished Jul 04 07:13:25 PM PDT 24
Peak memory 217192 kb
Host smart-42118b4e-4d19-4826-bb27-eb1d04c6b630
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795641065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.3795641065
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.1911745479
Short name T449
Test name
Test status
Simulation time 29534936 ps
CPU time 0.92 seconds
Started Jul 04 07:13:10 PM PDT 24
Finished Jul 04 07:13:42 PM PDT 24
Peak memory 208492 kb
Host smart-64dbe15c-6e78-4fae-aef6-78a98a62c0e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911745479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.1911745479
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.558375598
Short name T408
Test name
Test status
Simulation time 704224321 ps
CPU time 8.79 seconds
Started Jul 04 07:13:03 PM PDT 24
Finished Jul 04 07:13:40 PM PDT 24
Peak memory 225584 kb
Host smart-cd0c0fd0-f728-4114-b675-4d6729b1f8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558375598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.558375598
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.50372387
Short name T8
Test name
Test status
Simulation time 848326435 ps
CPU time 11.46 seconds
Started Jul 04 07:13:01 PM PDT 24
Finished Jul 04 07:13:40 PM PDT 24
Peak memory 217188 kb
Host smart-fc6daa20-0a7c-4174-acd6-880d3ed9165e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50372387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.50372387
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.2504009262
Short name T755
Test name
Test status
Simulation time 4902461131 ps
CPU time 129.73 seconds
Started Jul 04 07:13:01 PM PDT 24
Finished Jul 04 07:15:39 PM PDT 24
Peak memory 219528 kb
Host smart-e7d3d364-799c-4b8e-99c3-c4b986dc91db
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504009262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.2504009262
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.4165067051
Short name T719
Test name
Test status
Simulation time 3178667272 ps
CPU time 10.91 seconds
Started Jul 04 07:13:01 PM PDT 24
Finished Jul 04 07:13:40 PM PDT 24
Peak memory 217788 kb
Host smart-6e720cb1-e813-4980-878e-194af90a6c6e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165067051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.4165067051
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.3617478458
Short name T77
Test name
Test status
Simulation time 119232244 ps
CPU time 2.49 seconds
Started Jul 04 07:13:01 PM PDT 24
Finished Jul 04 07:13:31 PM PDT 24
Peak memory 217156 kb
Host smart-2b8c856d-c50a-4422-a022-b3bf2d707ab5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617478458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.3617478458
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.1226379221
Short name T656
Test name
Test status
Simulation time 8617794849 ps
CPU time 42.09 seconds
Started Jul 04 07:13:03 PM PDT 24
Finished Jul 04 07:14:14 PM PDT 24
Peak memory 268380 kb
Host smart-55e032a5-22f8-4708-9c69-9ee43cf9c0d0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226379221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.1226379221
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.1790549965
Short name T747
Test name
Test status
Simulation time 533263764 ps
CPU time 11.91 seconds
Started Jul 04 07:13:00 PM PDT 24
Finished Jul 04 07:13:41 PM PDT 24
Peak memory 248140 kb
Host smart-b328cc4c-0c7a-4b7a-bdec-f7d98cad2efe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790549965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.1790549965
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.2212133987
Short name T607
Test name
Test status
Simulation time 860966328 ps
CPU time 3.32 seconds
Started Jul 04 07:13:02 PM PDT 24
Finished Jul 04 07:13:35 PM PDT 24
Peak memory 217764 kb
Host smart-b932b923-020e-430f-b614-9d0b0b6f0b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212133987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.2212133987
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.480038961
Short name T515
Test name
Test status
Simulation time 967011317 ps
CPU time 14.22 seconds
Started Jul 04 07:13:08 PM PDT 24
Finished Jul 04 07:13:53 PM PDT 24
Peak memory 225536 kb
Host smart-6d6af622-da40-428f-a6bd-c061534ecd4e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480038961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_di
gest.480038961
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.2317843470
Short name T674
Test name
Test status
Simulation time 243274589 ps
CPU time 9.27 seconds
Started Jul 04 07:13:12 PM PDT 24
Finished Jul 04 07:13:56 PM PDT 24
Peak memory 217752 kb
Host smart-3eb4345b-5140-45a3-ad29-4f4fe124bf12
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317843470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
2317843470
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.2148040785
Short name T842
Test name
Test status
Simulation time 45544322 ps
CPU time 1.79 seconds
Started Jul 04 07:13:01 PM PDT 24
Finished Jul 04 07:13:31 PM PDT 24
Peak memory 213484 kb
Host smart-3b96feba-ff04-4291-a330-39d713428c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148040785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.2148040785
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.1873607122
Short name T681
Test name
Test status
Simulation time 769381142 ps
CPU time 17.7 seconds
Started Jul 04 07:13:02 PM PDT 24
Finished Jul 04 07:13:49 PM PDT 24
Peak memory 250548 kb
Host smart-b9550284-31cf-4102-8d12-9a6f2988e906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873607122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.1873607122
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.4119991017
Short name T256
Test name
Test status
Simulation time 845324338 ps
CPU time 6.64 seconds
Started Jul 04 07:13:03 PM PDT 24
Finished Jul 04 07:13:38 PM PDT 24
Peak memory 246344 kb
Host smart-a6d87fe7-cdbc-4821-ba2d-c9cc230f3c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119991017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.4119991017
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.1939193301
Short name T400
Test name
Test status
Simulation time 19105161546 ps
CPU time 171.98 seconds
Started Jul 04 07:13:09 PM PDT 24
Finished Jul 04 07:16:33 PM PDT 24
Peak memory 275164 kb
Host smart-af1eb0f8-9210-49b5-86a8-31d187ac0177
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939193301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.1939193301
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.2821304560
Short name T87
Test name
Test status
Simulation time 251704372 ps
CPU time 0.89 seconds
Started Jul 04 07:13:00 PM PDT 24
Finished Jul 04 07:13:30 PM PDT 24
Peak memory 212364 kb
Host smart-ae2b3a9c-2449-41eb-af01-38ffbfb6e808
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821304560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.2821304560
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.2330764507
Short name T720
Test name
Test status
Simulation time 128089293 ps
CPU time 1.03 seconds
Started Jul 04 07:13:14 PM PDT 24
Finished Jul 04 07:13:48 PM PDT 24
Peak memory 208508 kb
Host smart-987a48fb-50e2-486c-9977-9b99eb52cda2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330764507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.2330764507
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.3729388410
Short name T638
Test name
Test status
Simulation time 378713828 ps
CPU time 9.95 seconds
Started Jul 04 07:13:09 PM PDT 24
Finished Jul 04 07:13:51 PM PDT 24
Peak memory 217748 kb
Host smart-3eca3371-c37b-4773-b2c4-bfff530a426e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729388410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.3729388410
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.3926696099
Short name T839
Test name
Test status
Simulation time 1559942475 ps
CPU time 7.45 seconds
Started Jul 04 07:13:08 PM PDT 24
Finished Jul 04 07:13:48 PM PDT 24
Peak memory 216924 kb
Host smart-6f69ab11-4bf7-47aa-a7a9-2553f11794ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926696099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.3926696099
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.1830887479
Short name T568
Test name
Test status
Simulation time 14225183876 ps
CPU time 36.46 seconds
Started Jul 04 07:13:10 PM PDT 24
Finished Jul 04 07:14:18 PM PDT 24
Peak memory 218444 kb
Host smart-cca76dd5-924d-47da-98a6-dde45fa639af
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830887479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.1830887479
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.2688489492
Short name T371
Test name
Test status
Simulation time 172971499 ps
CPU time 2.93 seconds
Started Jul 04 07:13:11 PM PDT 24
Finished Jul 04 07:13:47 PM PDT 24
Peak memory 217120 kb
Host smart-51b91c30-8d4b-46b7-9027-f2b7b3c86e61
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688489492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.2688489492
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.2666112803
Short name T23
Test name
Test status
Simulation time 2424574332 ps
CPU time 49.99 seconds
Started Jul 04 07:13:08 PM PDT 24
Finished Jul 04 07:14:31 PM PDT 24
Peak memory 269536 kb
Host smart-50aba692-d960-4746-aa73-87a2bb1c64b4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666112803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.2666112803
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.1778822317
Short name T296
Test name
Test status
Simulation time 1242864342 ps
CPU time 12.91 seconds
Started Jul 04 07:13:09 PM PDT 24
Finished Jul 04 07:13:54 PM PDT 24
Peak memory 250300 kb
Host smart-8eadbfaa-0027-4465-8b59-1953b2245b89
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778822317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.1778822317
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.1968232339
Short name T106
Test name
Test status
Simulation time 592463669 ps
CPU time 3.57 seconds
Started Jul 04 07:13:09 PM PDT 24
Finished Jul 04 07:13:45 PM PDT 24
Peak memory 217744 kb
Host smart-589cb01e-4f32-47f0-8021-2461252c9fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968232339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.1968232339
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.1328205623
Short name T403
Test name
Test status
Simulation time 1226858186 ps
CPU time 14.23 seconds
Started Jul 04 07:13:08 PM PDT 24
Finished Jul 04 07:13:53 PM PDT 24
Peak memory 225584 kb
Host smart-d4d6a093-c34c-41d9-ba18-12513d87fb62
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328205623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.1328205623
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.3869179613
Short name T460
Test name
Test status
Simulation time 458987163 ps
CPU time 17.13 seconds
Started Jul 04 07:13:16 PM PDT 24
Finished Jul 04 07:14:06 PM PDT 24
Peak memory 225500 kb
Host smart-ced82e89-e757-4ed4-9493-f530872defee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869179613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.3869179613
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.2229598740
Short name T682
Test name
Test status
Simulation time 1728517037 ps
CPU time 7.06 seconds
Started Jul 04 07:13:15 PM PDT 24
Finished Jul 04 07:13:56 PM PDT 24
Peak memory 224488 kb
Host smart-ab9402e8-cd52-45f7-8909-aa533f6f13da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229598740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
2229598740
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.1541310877
Short name T195
Test name
Test status
Simulation time 515523654 ps
CPU time 7.34 seconds
Started Jul 04 07:13:09 PM PDT 24
Finished Jul 04 07:13:48 PM PDT 24
Peak memory 224280 kb
Host smart-65ef66bb-1b5d-4448-8959-a895f1b388cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541310877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.1541310877
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.1389167329
Short name T795
Test name
Test status
Simulation time 32173206 ps
CPU time 2.1 seconds
Started Jul 04 07:13:12 PM PDT 24
Finished Jul 04 07:13:47 PM PDT 24
Peak memory 213696 kb
Host smart-cc81bc5a-7360-4e05-a709-60a0a34e61dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389167329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.1389167329
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.1331820412
Short name T350
Test name
Test status
Simulation time 303099280 ps
CPU time 31.16 seconds
Started Jul 04 07:13:11 PM PDT 24
Finished Jul 04 07:14:16 PM PDT 24
Peak memory 250520 kb
Host smart-ae6dd936-1e20-4254-b2ad-e7c63b2171bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331820412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.1331820412
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.782914356
Short name T799
Test name
Test status
Simulation time 65409901 ps
CPU time 6.11 seconds
Started Jul 04 07:13:08 PM PDT 24
Finished Jul 04 07:13:47 PM PDT 24
Peak memory 243988 kb
Host smart-2e61bd25-bab3-4ca5-959b-466173a62e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782914356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.782914356
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.1605977218
Short name T654
Test name
Test status
Simulation time 30488860879 ps
CPU time 532.36 seconds
Started Jul 04 07:13:14 PM PDT 24
Finished Jul 04 07:22:41 PM PDT 24
Peak memory 332524 kb
Host smart-6df3f454-ca89-499f-bc97-0cb7db1143e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605977218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.1605977218
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.3489389193
Short name T648
Test name
Test status
Simulation time 99355591163 ps
CPU time 748.53 seconds
Started Jul 04 07:13:14 PM PDT 24
Finished Jul 04 07:26:17 PM PDT 24
Peak memory 283420 kb
Host smart-0e4280a7-f564-4de0-ba63-e2070bdbd74d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3489389193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all_with_rand_reset.3489389193
Directory /workspace/16.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.1646095031
Short name T577
Test name
Test status
Simulation time 93486416 ps
CPU time 0.87 seconds
Started Jul 04 07:13:08 PM PDT 24
Finished Jul 04 07:13:40 PM PDT 24
Peak memory 208468 kb
Host smart-e06b6554-2cbe-491e-bab6-66b5f1caca3d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646095031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.1646095031
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.1645281727
Short name T738
Test name
Test status
Simulation time 84344282 ps
CPU time 0.91 seconds
Started Jul 04 07:13:20 PM PDT 24
Finished Jul 04 07:13:54 PM PDT 24
Peak memory 208496 kb
Host smart-d5943e2a-1051-47f6-82f1-17ed470fc1e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645281727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.1645281727
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.2702701156
Short name T581
Test name
Test status
Simulation time 706970671 ps
CPU time 15.01 seconds
Started Jul 04 07:13:16 PM PDT 24
Finished Jul 04 07:14:04 PM PDT 24
Peak memory 217808 kb
Host smart-87da9257-4d89-4a70-ac1f-d8c4fcd4b7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702701156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.2702701156
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.2355010213
Short name T699
Test name
Test status
Simulation time 453748434 ps
CPU time 4.58 seconds
Started Jul 04 07:13:20 PM PDT 24
Finished Jul 04 07:13:57 PM PDT 24
Peak memory 217220 kb
Host smart-76bbe3eb-ed08-4466-ad1e-0adbdd4c3391
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355010213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.2355010213
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.4287559212
Short name T487
Test name
Test status
Simulation time 5809053889 ps
CPU time 25.81 seconds
Started Jul 04 07:13:16 PM PDT 24
Finished Jul 04 07:14:15 PM PDT 24
Peak memory 218292 kb
Host smart-dd363e6c-12f9-4dee-b3a4-7254acd8e779
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287559212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.4287559212
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.2893312928
Short name T297
Test name
Test status
Simulation time 530177701 ps
CPU time 13.92 seconds
Started Jul 04 07:13:15 PM PDT 24
Finished Jul 04 07:14:03 PM PDT 24
Peak memory 217708 kb
Host smart-9ffbbad4-7c1f-43f1-a4da-3b037f9930b0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893312928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.2893312928
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.891141629
Short name T642
Test name
Test status
Simulation time 1407458392 ps
CPU time 4.16 seconds
Started Jul 04 07:13:12 PM PDT 24
Finished Jul 04 07:13:51 PM PDT 24
Peak memory 217164 kb
Host smart-c1d5d04d-18e8-408b-99ac-fc45cd1f1335
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891141629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke.
891141629
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.3307640741
Short name T673
Test name
Test status
Simulation time 2290350664 ps
CPU time 72.06 seconds
Started Jul 04 07:13:14 PM PDT 24
Finished Jul 04 07:14:59 PM PDT 24
Peak memory 272252 kb
Host smart-2bb2fde4-c3c9-4b9b-ae26-eec153cf9af2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307640741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.3307640741
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.2847910202
Short name T555
Test name
Test status
Simulation time 1564931513 ps
CPU time 9.18 seconds
Started Jul 04 07:13:14 PM PDT 24
Finished Jul 04 07:13:58 PM PDT 24
Peak memory 245808 kb
Host smart-b3dacf80-9b2f-4553-a487-209d8d8e9df6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847910202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.2847910202
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.703260364
Short name T109
Test name
Test status
Simulation time 612675618 ps
CPU time 3.66 seconds
Started Jul 04 07:13:20 PM PDT 24
Finished Jul 04 07:13:56 PM PDT 24
Peak memory 217776 kb
Host smart-670d571d-2c06-405b-a971-60b0ffe89fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703260364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.703260364
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.1846821729
Short name T108
Test name
Test status
Simulation time 1551721445 ps
CPU time 12.44 seconds
Started Jul 04 07:13:20 PM PDT 24
Finished Jul 04 07:14:05 PM PDT 24
Peak memory 217768 kb
Host smart-c0688a31-ba50-42a0-a37f-a98d5dee22ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846821729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.1846821729
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.2119664795
Short name T392
Test name
Test status
Simulation time 344923212 ps
CPU time 8.97 seconds
Started Jul 04 07:13:21 PM PDT 24
Finished Jul 04 07:14:02 PM PDT 24
Peak memory 225520 kb
Host smart-141cdb68-cd58-4f81-8c54-f63f44d06f2a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119664795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
2119664795
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.565629532
Short name T862
Test name
Test status
Simulation time 321428769 ps
CPU time 7.84 seconds
Started Jul 04 07:13:15 PM PDT 24
Finished Jul 04 07:13:57 PM PDT 24
Peak memory 225576 kb
Host smart-77356d0c-757f-4c40-9180-304164f5f5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565629532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.565629532
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.4162188076
Short name T73
Test name
Test status
Simulation time 187414263 ps
CPU time 1.55 seconds
Started Jul 04 07:13:17 PM PDT 24
Finished Jul 04 07:13:51 PM PDT 24
Peak memory 213404 kb
Host smart-001b8431-31a6-4da7-aa43-b87a32ae553f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162188076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.4162188076
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.3604639087
Short name T130
Test name
Test status
Simulation time 160273676 ps
CPU time 16.54 seconds
Started Jul 04 07:13:21 PM PDT 24
Finished Jul 04 07:14:09 PM PDT 24
Peak memory 250524 kb
Host smart-12e865b3-7669-4fed-baad-f5716eca642e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604639087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.3604639087
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.3368528121
Short name T752
Test name
Test status
Simulation time 59691108 ps
CPU time 7.47 seconds
Started Jul 04 07:13:16 PM PDT 24
Finished Jul 04 07:13:57 PM PDT 24
Peak memory 243120 kb
Host smart-11a3ff7c-dec7-46bf-baf2-8236d27b3e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368528121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.3368528121
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.3036970733
Short name T103
Test name
Test status
Simulation time 12546753426 ps
CPU time 45.4 seconds
Started Jul 04 07:13:20 PM PDT 24
Finished Jul 04 07:14:38 PM PDT 24
Peak memory 258628 kb
Host smart-c0641b01-707b-47c2-9eb2-a25c6c0ff55d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036970733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.3036970733
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.1724183000
Short name T171
Test name
Test status
Simulation time 84661974720 ps
CPU time 822.26 seconds
Started Jul 04 07:13:25 PM PDT 24
Finished Jul 04 07:27:40 PM PDT 24
Peak memory 283516 kb
Host smart-d4a5cf34-57a1-4f7a-8bca-e73c19545195
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1724183000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.1724183000
Directory /workspace/17.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.2501916162
Short name T836
Test name
Test status
Simulation time 50494895 ps
CPU time 0.91 seconds
Started Jul 04 07:13:15 PM PDT 24
Finished Jul 04 07:13:50 PM PDT 24
Peak memory 217372 kb
Host smart-f27fc6fe-1cba-497e-80bb-7eea1b6a7ff9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501916162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.2501916162
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.2194673167
Short name T512
Test name
Test status
Simulation time 145853461 ps
CPU time 1.16 seconds
Started Jul 04 07:13:20 PM PDT 24
Finished Jul 04 07:13:54 PM PDT 24
Peak memory 208576 kb
Host smart-9d2cdcfd-30cd-467c-9943-cbda9090c337
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194673167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.2194673167
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.3900668503
Short name T269
Test name
Test status
Simulation time 494211907 ps
CPU time 14.81 seconds
Started Jul 04 07:13:22 PM PDT 24
Finished Jul 04 07:14:10 PM PDT 24
Peak memory 217792 kb
Host smart-fb4d7f54-be81-4096-b48e-4dadd3dd4330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900668503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.3900668503
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.1969233699
Short name T543
Test name
Test status
Simulation time 680354703 ps
CPU time 2.74 seconds
Started Jul 04 07:13:20 PM PDT 24
Finished Jul 04 07:13:55 PM PDT 24
Peak memory 217284 kb
Host smart-4ed7dc00-b9a4-4164-93f4-f13a6ebeb9a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969233699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.1969233699
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.3147727080
Short name T475
Test name
Test status
Simulation time 3303642779 ps
CPU time 23.53 seconds
Started Jul 04 07:13:21 PM PDT 24
Finished Jul 04 07:14:19 PM PDT 24
Peak memory 218440 kb
Host smart-c0562ce5-427b-4da4-aadd-db5b2d68fbfb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147727080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.3147727080
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.3550639659
Short name T472
Test name
Test status
Simulation time 253391499 ps
CPU time 3.75 seconds
Started Jul 04 07:13:19 PM PDT 24
Finished Jul 04 07:13:55 PM PDT 24
Peak memory 217744 kb
Host smart-1ab3e345-b56c-4aa7-b568-c8ec5933bc5e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550639659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.3550639659
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.3852912732
Short name T584
Test name
Test status
Simulation time 52775446 ps
CPU time 2.15 seconds
Started Jul 04 07:13:20 PM PDT 24
Finished Jul 04 07:13:55 PM PDT 24
Peak memory 217148 kb
Host smart-dfb9e33c-c373-4139-816a-af7029f5415f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852912732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.3852912732
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.1790532644
Short name T763
Test name
Test status
Simulation time 5183106676 ps
CPU time 63.48 seconds
Started Jul 04 07:13:19 PM PDT 24
Finished Jul 04 07:14:56 PM PDT 24
Peak memory 283260 kb
Host smart-d7f2d666-f2e3-4a83-93a4-cf478a0381ab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790532644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.1790532644
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.572699910
Short name T336
Test name
Test status
Simulation time 449052990 ps
CPU time 15.17 seconds
Started Jul 04 07:13:22 PM PDT 24
Finished Jul 04 07:14:11 PM PDT 24
Peak memory 250596 kb
Host smart-363ce44d-e6b9-4150-96fe-d9be5d78d52d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572699910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_
jtag_state_post_trans.572699910
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.3531274762
Short name T248
Test name
Test status
Simulation time 86638567 ps
CPU time 3.87 seconds
Started Jul 04 07:13:22 PM PDT 24
Finished Jul 04 07:13:59 PM PDT 24
Peak memory 217776 kb
Host smart-723cfb01-85ae-4921-8b01-7d04b3aa10ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531274762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.3531274762
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.3327381386
Short name T831
Test name
Test status
Simulation time 1303588390 ps
CPU time 11 seconds
Started Jul 04 07:13:20 PM PDT 24
Finished Jul 04 07:14:04 PM PDT 24
Peak memory 218428 kb
Host smart-40bb747e-70a5-4607-a9b4-563a80c9518a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327381386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.3327381386
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.2190534578
Short name T600
Test name
Test status
Simulation time 751092320 ps
CPU time 11.44 seconds
Started Jul 04 07:13:22 PM PDT 24
Finished Jul 04 07:14:07 PM PDT 24
Peak memory 225536 kb
Host smart-00b5d57f-5910-48ed-ba74-758d6609cd64
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190534578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.2190534578
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.441199912
Short name T849
Test name
Test status
Simulation time 1050442089 ps
CPU time 11.18 seconds
Started Jul 04 07:13:20 PM PDT 24
Finished Jul 04 07:14:04 PM PDT 24
Peak memory 217712 kb
Host smart-f14f2639-722d-4878-9c83-df0eb6a39599
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441199912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.441199912
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.3745392876
Short name T695
Test name
Test status
Simulation time 280107583 ps
CPU time 11.31 seconds
Started Jul 04 07:13:21 PM PDT 24
Finished Jul 04 07:14:04 PM PDT 24
Peak memory 225388 kb
Host smart-a82fbbc2-fd9c-4eb9-837c-bf2bdca48075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745392876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.3745392876
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.2644795241
Short name T69
Test name
Test status
Simulation time 116432465 ps
CPU time 3.49 seconds
Started Jul 04 07:13:21 PM PDT 24
Finished Jul 04 07:13:56 PM PDT 24
Peak memory 217192 kb
Host smart-78bab34c-81b6-4d2e-96cd-968f109975b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644795241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.2644795241
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.2896156472
Short name T572
Test name
Test status
Simulation time 1915671509 ps
CPU time 23.03 seconds
Started Jul 04 07:13:21 PM PDT 24
Finished Jul 04 07:14:16 PM PDT 24
Peak memory 250528 kb
Host smart-d9b9242b-06c5-407d-9786-e0b9b187e41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896156472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.2896156472
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.3188188296
Short name T667
Test name
Test status
Simulation time 205102506 ps
CPU time 3.47 seconds
Started Jul 04 07:13:25 PM PDT 24
Finished Jul 04 07:14:01 PM PDT 24
Peak memory 222156 kb
Host smart-8df827a6-49eb-43df-a33e-5c1f9bb1fc3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188188296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.3188188296
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.3993718086
Short name T624
Test name
Test status
Simulation time 4967000415 ps
CPU time 94.46 seconds
Started Jul 04 07:13:20 PM PDT 24
Finished Jul 04 07:15:27 PM PDT 24
Peak memory 275816 kb
Host smart-88a9f14a-b165-4302-9f6e-8e780790aad9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993718086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.3993718086
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.761141330
Short name T739
Test name
Test status
Simulation time 168174013331 ps
CPU time 450.52 seconds
Started Jul 04 07:13:23 PM PDT 24
Finished Jul 04 07:21:26 PM PDT 24
Peak memory 263436 kb
Host smart-fa8fdcb0-e549-45fc-9296-b7a0f83c1528
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=761141330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.761141330
Directory /workspace/18.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.2249748331
Short name T413
Test name
Test status
Simulation time 54123381 ps
CPU time 1.07 seconds
Started Jul 04 07:13:22 PM PDT 24
Finished Jul 04 07:13:56 PM PDT 24
Peak memory 211384 kb
Host smart-09c5cb55-c914-40af-ba42-0da06cf9a265
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249748331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.2249748331
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.2337223454
Short name T705
Test name
Test status
Simulation time 46547476 ps
CPU time 0.89 seconds
Started Jul 04 07:13:26 PM PDT 24
Finished Jul 04 07:14:01 PM PDT 24
Peak memory 208500 kb
Host smart-3f93e9e9-8544-40fa-846c-5a31825ec2c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337223454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.2337223454
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.71886898
Short name T434
Test name
Test status
Simulation time 2020429725 ps
CPU time 14.78 seconds
Started Jul 04 07:13:27 PM PDT 24
Finished Jul 04 07:14:15 PM PDT 24
Peak memory 217812 kb
Host smart-19ec45d6-dc1d-4b02-b29f-7dd15f47d20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71886898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.71886898
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.2235181238
Short name T424
Test name
Test status
Simulation time 2773226427 ps
CPU time 4.09 seconds
Started Jul 04 07:13:27 PM PDT 24
Finished Jul 04 07:14:04 PM PDT 24
Peak memory 217260 kb
Host smart-96daa985-82f4-40bd-863c-0ce3247c6d04
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235181238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.2235181238
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.1003186101
Short name T20
Test name
Test status
Simulation time 21990147049 ps
CPU time 35.56 seconds
Started Jul 04 07:13:27 PM PDT 24
Finished Jul 04 07:14:35 PM PDT 24
Peak memory 218436 kb
Host smart-b13cb605-25b1-4884-9323-efd52343ff53
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003186101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.1003186101
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.2719787581
Short name T635
Test name
Test status
Simulation time 1026517845 ps
CPU time 7.74 seconds
Started Jul 04 07:13:29 PM PDT 24
Finished Jul 04 07:14:09 PM PDT 24
Peak memory 221544 kb
Host smart-438a2cf6-56ca-45b3-8737-cd4ecd73b3f3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719787581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.2719787581
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.3159289558
Short name T285
Test name
Test status
Simulation time 342564948 ps
CPU time 3.58 seconds
Started Jul 04 07:13:27 PM PDT 24
Finished Jul 04 07:14:03 PM PDT 24
Peak memory 217380 kb
Host smart-eeb0e8e4-c11f-4146-8987-2c172fc8614f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159289558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.3159289558
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.3036663767
Short name T548
Test name
Test status
Simulation time 1727027532 ps
CPU time 28.46 seconds
Started Jul 04 07:13:26 PM PDT 24
Finished Jul 04 07:14:28 PM PDT 24
Peak memory 250392 kb
Host smart-1c49ba0e-d239-4736-861f-7c8b98c76a74
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036663767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.3036663767
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.400936565
Short name T394
Test name
Test status
Simulation time 3002585132 ps
CPU time 22.64 seconds
Started Jul 04 07:13:28 PM PDT 24
Finished Jul 04 07:14:23 PM PDT 24
Peak memory 247304 kb
Host smart-0e6a175e-3b61-406b-bc85-754eb6aceaf7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400936565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_
jtag_state_post_trans.400936565
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.2934520938
Short name T619
Test name
Test status
Simulation time 86818411 ps
CPU time 1.69 seconds
Started Jul 04 07:13:21 PM PDT 24
Finished Jul 04 07:13:54 PM PDT 24
Peak memory 217776 kb
Host smart-8ec1da1d-42d5-482c-b16a-abddf4aedadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934520938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.2934520938
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.1105805854
Short name T299
Test name
Test status
Simulation time 300470277 ps
CPU time 13.14 seconds
Started Jul 04 07:13:27 PM PDT 24
Finished Jul 04 07:14:13 PM PDT 24
Peak memory 225820 kb
Host smart-a1bff40c-2094-46dc-bc65-d6f532323064
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105805854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.1105805854
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.1870988703
Short name T321
Test name
Test status
Simulation time 300870900 ps
CPU time 9.95 seconds
Started Jul 04 07:13:27 PM PDT 24
Finished Jul 04 07:14:10 PM PDT 24
Peak memory 225540 kb
Host smart-d09563e2-3c08-4311-a8ba-25dd6965cda9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870988703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.1870988703
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.2577326770
Short name T537
Test name
Test status
Simulation time 602297930 ps
CPU time 9.51 seconds
Started Jul 04 07:13:28 PM PDT 24
Finished Jul 04 07:14:09 PM PDT 24
Peak memory 225672 kb
Host smart-d600086e-a741-4009-8286-b304a72728c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577326770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
2577326770
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.3684791105
Short name T60
Test name
Test status
Simulation time 386560018 ps
CPU time 9.47 seconds
Started Jul 04 07:13:28 PM PDT 24
Finished Jul 04 07:14:09 PM PDT 24
Peak memory 225560 kb
Host smart-2b27c3e7-d6bc-4118-a42f-76e82fc11639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684791105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.3684791105
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.1659161721
Short name T107
Test name
Test status
Simulation time 1043101133 ps
CPU time 4.07 seconds
Started Jul 04 07:13:19 PM PDT 24
Finished Jul 04 07:13:55 PM PDT 24
Peak memory 217236 kb
Host smart-fe756751-0ae1-4d41-9f41-21d4863fb373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659161721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.1659161721
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.803851807
Short name T126
Test name
Test status
Simulation time 1001712499 ps
CPU time 25.36 seconds
Started Jul 04 07:13:20 PM PDT 24
Finished Jul 04 07:14:18 PM PDT 24
Peak memory 245592 kb
Host smart-e4b8e9b0-318f-4c3b-94af-7c777928b5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803851807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.803851807
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.3841142501
Short name T771
Test name
Test status
Simulation time 381830551914 ps
CPU time 416.35 seconds
Started Jul 04 07:13:28 PM PDT 24
Finished Jul 04 07:20:56 PM PDT 24
Peak memory 283376 kb
Host smart-d3e2eaa1-cc73-47d4-9e2d-b56d90d66963
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841142501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.3841142501
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.516228544
Short name T1
Test name
Test status
Simulation time 21275539 ps
CPU time 0.81 seconds
Started Jul 04 07:13:21 PM PDT 24
Finished Jul 04 07:13:56 PM PDT 24
Peak memory 208396 kb
Host smart-fbc0793c-1b7c-4f59-b819-878c7265c01d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516228544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ct
rl_volatile_unlock_smoke.516228544
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.3725780009
Short name T370
Test name
Test status
Simulation time 30967418 ps
CPU time 0.85 seconds
Started Jul 04 07:12:13 PM PDT 24
Finished Jul 04 07:12:17 PM PDT 24
Peak memory 208524 kb
Host smart-155cca1c-c513-4b4c-b796-fb59f1491b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725780009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.3725780009
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.3906706753
Short name T653
Test name
Test status
Simulation time 3594181238 ps
CPU time 11.67 seconds
Started Jul 04 07:12:09 PM PDT 24
Finished Jul 04 07:12:24 PM PDT 24
Peak memory 217860 kb
Host smart-4b136481-6f97-4093-b911-ab35c7e6381f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906706753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.3906706753
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.87074784
Short name T615
Test name
Test status
Simulation time 1945030866 ps
CPU time 6.7 seconds
Started Jul 04 07:12:12 PM PDT 24
Finished Jul 04 07:12:22 PM PDT 24
Peak memory 217200 kb
Host smart-44560745-e872-4977-9308-a230f0c6944c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87074784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.87074784
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.2931351814
Short name T664
Test name
Test status
Simulation time 20627734007 ps
CPU time 43.48 seconds
Started Jul 04 07:12:10 PM PDT 24
Finished Jul 04 07:12:57 PM PDT 24
Peak memory 218496 kb
Host smart-121c3405-66ba-41b8-b84b-6a6cd629e18c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931351814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.2931351814
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.2716703401
Short name T306
Test name
Test status
Simulation time 679998087 ps
CPU time 17.41 seconds
Started Jul 04 07:12:11 PM PDT 24
Finished Jul 04 07:12:31 PM PDT 24
Peak memory 217220 kb
Host smart-07da7db4-5a4b-4ff1-b1f4-490fd82ae7d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716703401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.2
716703401
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.829122252
Short name T415
Test name
Test status
Simulation time 344790689 ps
CPU time 5.72 seconds
Started Jul 04 07:12:12 PM PDT 24
Finished Jul 04 07:12:21 PM PDT 24
Peak memory 217756 kb
Host smart-8b96a0f3-e447-4e2e-8737-c892f3e5107d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829122252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_
prog_failure.829122252
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.1694257978
Short name T469
Test name
Test status
Simulation time 2778194746 ps
CPU time 19.06 seconds
Started Jul 04 07:12:17 PM PDT 24
Finished Jul 04 07:12:39 PM PDT 24
Peak memory 217208 kb
Host smart-8eb5ee6a-6177-4823-af8f-c76720142903
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694257978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.1694257978
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.1137014533
Short name T794
Test name
Test status
Simulation time 3381233761 ps
CPU time 7.49 seconds
Started Jul 04 07:12:09 PM PDT 24
Finished Jul 04 07:12:19 PM PDT 24
Peak memory 217216 kb
Host smart-140d3876-93f1-4386-9ff8-3d209c064965
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137014533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
1137014533
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.3836843245
Short name T588
Test name
Test status
Simulation time 6739421645 ps
CPU time 48.27 seconds
Started Jul 04 07:12:11 PM PDT 24
Finished Jul 04 07:13:02 PM PDT 24
Peak memory 266876 kb
Host smart-15dcd144-5ebe-4401-997c-d9745b202124
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836843245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.3836843245
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.3274468811
Short name T209
Test name
Test status
Simulation time 1626297871 ps
CPU time 28.6 seconds
Started Jul 04 07:12:12 PM PDT 24
Finished Jul 04 07:12:43 PM PDT 24
Peak memory 247228 kb
Host smart-3a94472f-336c-45d6-a2fa-515414cdb2d0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274468811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.3274468811
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.3891519289
Short name T245
Test name
Test status
Simulation time 67815747 ps
CPU time 1.61 seconds
Started Jul 04 07:12:09 PM PDT 24
Finished Jul 04 07:12:13 PM PDT 24
Peak memory 221240 kb
Host smart-cc66c0e4-2970-4cf5-92c5-81aa8241edbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891519289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.3891519289
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.800154104
Short name T89
Test name
Test status
Simulation time 2597684272 ps
CPU time 21.63 seconds
Started Jul 04 07:12:11 PM PDT 24
Finished Jul 04 07:12:35 PM PDT 24
Peak memory 214752 kb
Host smart-cf69e300-46fd-4bde-95bb-42524370a420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800154104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.800154104
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.2755350626
Short name T62
Test name
Test status
Simulation time 617161560 ps
CPU time 35.67 seconds
Started Jul 04 07:12:14 PM PDT 24
Finished Jul 04 07:12:52 PM PDT 24
Peak memory 270864 kb
Host smart-b8c17145-bb77-4550-b612-8d20440878df
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755350626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.2755350626
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.2775372205
Short name T636
Test name
Test status
Simulation time 1109648289 ps
CPU time 11.72 seconds
Started Jul 04 07:12:15 PM PDT 24
Finished Jul 04 07:12:30 PM PDT 24
Peak memory 225332 kb
Host smart-6547d8bb-eb1b-4046-93d4-19c664ccf132
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775372205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.2775372205
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.4254873148
Short name T662
Test name
Test status
Simulation time 193895401 ps
CPU time 9.38 seconds
Started Jul 04 07:12:18 PM PDT 24
Finished Jul 04 07:12:31 PM PDT 24
Peak memory 225516 kb
Host smart-aafc57a4-a23e-413b-a645-33baff3dbdea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254873148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.4254873148
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.167250281
Short name T349
Test name
Test status
Simulation time 377608017 ps
CPU time 7.31 seconds
Started Jul 04 07:12:18 PM PDT 24
Finished Jul 04 07:12:29 PM PDT 24
Peak memory 217684 kb
Host smart-65c04601-0b64-4dd3-890e-19581842c41d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167250281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.167250281
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.1184653511
Short name T65
Test name
Test status
Simulation time 331885718 ps
CPU time 10.25 seconds
Started Jul 04 07:12:09 PM PDT 24
Finished Jul 04 07:12:22 PM PDT 24
Peak memory 225600 kb
Host smart-4ecd7ac7-0aa3-4508-ac73-88dc3d7dbfb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184653511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.1184653511
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.3467915686
Short name T721
Test name
Test status
Simulation time 42240108 ps
CPU time 2.31 seconds
Started Jul 04 07:12:08 PM PDT 24
Finished Jul 04 07:12:13 PM PDT 24
Peak memory 217216 kb
Host smart-07206813-c3a3-4c83-b710-596fe3068e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467915686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.3467915686
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.3713911880
Short name T404
Test name
Test status
Simulation time 276911923 ps
CPU time 28.9 seconds
Started Jul 04 07:12:11 PM PDT 24
Finished Jul 04 07:12:43 PM PDT 24
Peak memory 247484 kb
Host smart-a1fff13f-ec58-47f2-8f2f-ef4e6fe33b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713911880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.3713911880
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.228697667
Short name T473
Test name
Test status
Simulation time 61482851 ps
CPU time 8.11 seconds
Started Jul 04 07:12:10 PM PDT 24
Finished Jul 04 07:12:21 PM PDT 24
Peak memory 250532 kb
Host smart-a3179e95-4ddd-4e76-88bb-6c0db4c5fbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228697667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.228697667
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.797510832
Short name T526
Test name
Test status
Simulation time 5615862205 ps
CPU time 122.52 seconds
Started Jul 04 07:12:18 PM PDT 24
Finished Jul 04 07:14:25 PM PDT 24
Peak memory 250616 kb
Host smart-4e38dea5-0018-4831-ad6d-152bfb8e57e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797510832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.797510832
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.128953091
Short name T131
Test name
Test status
Simulation time 90862172311 ps
CPU time 771.7 seconds
Started Jul 04 07:12:17 PM PDT 24
Finished Jul 04 07:25:11 PM PDT 24
Peak memory 421716 kb
Host smart-f633a225-6281-4561-9a4b-4ef9ec5a2133
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=128953091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.128953091
Directory /workspace/2.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.3828584931
Short name T41
Test name
Test status
Simulation time 30819622 ps
CPU time 1.02 seconds
Started Jul 04 07:12:10 PM PDT 24
Finished Jul 04 07:12:14 PM PDT 24
Peak memory 217180 kb
Host smart-fb118763-a903-4f37-ba04-142c5da556ac
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828584931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.3828584931
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.2737420870
Short name T259
Test name
Test status
Simulation time 46827279 ps
CPU time 0.83 seconds
Started Jul 04 07:13:33 PM PDT 24
Finished Jul 04 07:14:03 PM PDT 24
Peak memory 208392 kb
Host smart-8797cb9a-5e0e-464d-81df-af0840e2c1ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737420870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.2737420870
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.113614945
Short name T250
Test name
Test status
Simulation time 281995904 ps
CPU time 14.46 seconds
Started Jul 04 07:13:32 PM PDT 24
Finished Jul 04 07:14:16 PM PDT 24
Peak memory 225616 kb
Host smart-7dcbba22-2af6-4f07-9300-01d1c553eda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113614945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.113614945
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.2620170280
Short name T31
Test name
Test status
Simulation time 1692701075 ps
CPU time 5.57 seconds
Started Jul 04 07:13:33 PM PDT 24
Finished Jul 04 07:14:08 PM PDT 24
Peak memory 217196 kb
Host smart-cb4a7fd8-e1ee-4dbd-bb77-8e4babcc8f63
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620170280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.2620170280
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.2565984200
Short name T362
Test name
Test status
Simulation time 53939680 ps
CPU time 3.14 seconds
Started Jul 04 07:13:33 PM PDT 24
Finished Jul 04 07:14:05 PM PDT 24
Peak memory 217760 kb
Host smart-b9d34681-86fe-4b55-a3cd-bf22f43881f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565984200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.2565984200
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.371934659
Short name T677
Test name
Test status
Simulation time 298469794 ps
CPU time 10.46 seconds
Started Jul 04 07:13:33 PM PDT 24
Finished Jul 04 07:14:12 PM PDT 24
Peak memory 225588 kb
Host smart-4699f4a2-3d1d-4218-aea7-478b8e270b00
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371934659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.371934659
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.3717749129
Short name T690
Test name
Test status
Simulation time 633219609 ps
CPU time 13.22 seconds
Started Jul 04 07:13:35 PM PDT 24
Finished Jul 04 07:14:17 PM PDT 24
Peak memory 225528 kb
Host smart-e7e266a6-f9e1-4482-b549-36a2f1393281
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717749129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.3717749129
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.4132606876
Short name T733
Test name
Test status
Simulation time 1341527039 ps
CPU time 10.99 seconds
Started Jul 04 07:13:35 PM PDT 24
Finished Jul 04 07:14:14 PM PDT 24
Peak memory 217720 kb
Host smart-7b084b9e-3a1a-4223-9c9a-18dab515ce6c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132606876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
4132606876
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.2126620810
Short name T756
Test name
Test status
Simulation time 408878897 ps
CPU time 9.26 seconds
Started Jul 04 07:13:33 PM PDT 24
Finished Jul 04 07:14:11 PM PDT 24
Peak memory 225600 kb
Host smart-1ac25757-5731-4250-9a64-d03d6be9eb82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126620810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.2126620810
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.1009790957
Short name T81
Test name
Test status
Simulation time 263722323 ps
CPU time 3.32 seconds
Started Jul 04 07:13:25 PM PDT 24
Finished Jul 04 07:14:03 PM PDT 24
Peak memory 217216 kb
Host smart-8d75993a-1f48-4d3e-b7b6-50cd40054d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009790957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.1009790957
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.2268162719
Short name T411
Test name
Test status
Simulation time 525847728 ps
CPU time 28.52 seconds
Started Jul 04 07:13:36 PM PDT 24
Finished Jul 04 07:14:32 PM PDT 24
Peak memory 250508 kb
Host smart-2beadd52-0607-450b-ac81-bba5b586cfe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268162719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.2268162719
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.3456511031
Short name T281
Test name
Test status
Simulation time 122864604 ps
CPU time 5.48 seconds
Started Jul 04 07:13:36 PM PDT 24
Finished Jul 04 07:14:09 PM PDT 24
Peak memory 246284 kb
Host smart-7468817f-db97-4f0e-ba04-8c6dab1f43f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456511031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.3456511031
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.2375924933
Short name T180
Test name
Test status
Simulation time 8086177554 ps
CPU time 138.75 seconds
Started Jul 04 07:13:33 PM PDT 24
Finished Jul 04 07:16:21 PM PDT 24
Peak memory 250936 kb
Host smart-085ccbb6-ff10-4629-b8cd-fa912f7b666a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375924933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.2375924933
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.2501516200
Short name T255
Test name
Test status
Simulation time 13654279 ps
CPU time 0.91 seconds
Started Jul 04 07:13:28 PM PDT 24
Finished Jul 04 07:14:01 PM PDT 24
Peak memory 208164 kb
Host smart-5633ac69-fa7b-43a7-944b-049815d96d21
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501516200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.2501516200
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.127917348
Short name T467
Test name
Test status
Simulation time 32138801 ps
CPU time 0.89 seconds
Started Jul 04 07:13:40 PM PDT 24
Finished Jul 04 07:14:06 PM PDT 24
Peak memory 208516 kb
Host smart-43dff03d-533b-4d76-ae2d-3698e3a92e42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127917348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.127917348
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.676742404
Short name T438
Test name
Test status
Simulation time 523360775 ps
CPU time 10.57 seconds
Started Jul 04 07:13:34 PM PDT 24
Finished Jul 04 07:14:13 PM PDT 24
Peak memory 217748 kb
Host smart-32d36109-a3ea-4299-baed-1941f1fd1a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676742404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.676742404
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.2518586123
Short name T818
Test name
Test status
Simulation time 723929403 ps
CPU time 2.56 seconds
Started Jul 04 07:13:33 PM PDT 24
Finished Jul 04 07:14:05 PM PDT 24
Peak memory 217240 kb
Host smart-46ad3392-8876-4287-a31a-1efb0d4d58fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518586123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.2518586123
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.3304743963
Short name T78
Test name
Test status
Simulation time 53202332 ps
CPU time 2.57 seconds
Started Jul 04 07:13:33 PM PDT 24
Finished Jul 04 07:14:05 PM PDT 24
Peak memory 217768 kb
Host smart-e31aea87-7b79-4643-9d32-f2b3d49f96bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304743963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.3304743963
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.2911298878
Short name T117
Test name
Test status
Simulation time 1097235573 ps
CPU time 21.56 seconds
Started Jul 04 07:13:33 PM PDT 24
Finished Jul 04 07:14:24 PM PDT 24
Peak memory 225572 kb
Host smart-dd1dfbd5-d573-419a-bd55-36a56d919dfc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911298878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.2911298878
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.882073122
Short name T612
Test name
Test status
Simulation time 438415520 ps
CPU time 11.4 seconds
Started Jul 04 07:13:44 PM PDT 24
Finished Jul 04 07:14:17 PM PDT 24
Peak memory 225512 kb
Host smart-0797eaf9-2e68-47e9-81c3-5a96b6508118
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882073122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_di
gest.882073122
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.3106269957
Short name T520
Test name
Test status
Simulation time 5131542788 ps
CPU time 9.65 seconds
Started Jul 04 07:13:47 PM PDT 24
Finished Jul 04 07:14:16 PM PDT 24
Peak memory 217784 kb
Host smart-10370aee-3143-4ca5-9b3e-28521fbda979
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106269957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
3106269957
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.1354870543
Short name T711
Test name
Test status
Simulation time 1627123949 ps
CPU time 14.15 seconds
Started Jul 04 07:13:32 PM PDT 24
Finished Jul 04 07:14:16 PM PDT 24
Peak memory 225596 kb
Host smart-4d02bc52-a93d-4e9e-a657-33d4e9ef407f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354870543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.1354870543
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.309435470
Short name T499
Test name
Test status
Simulation time 47819696 ps
CPU time 2.84 seconds
Started Jul 04 07:13:35 PM PDT 24
Finished Jul 04 07:14:06 PM PDT 24
Peak memory 217212 kb
Host smart-43b1a696-f718-4874-b625-13d6d6c365aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309435470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.309435470
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.3757666318
Short name T552
Test name
Test status
Simulation time 1431670160 ps
CPU time 32.9 seconds
Started Jul 04 07:13:34 PM PDT 24
Finished Jul 04 07:14:35 PM PDT 24
Peak memory 250528 kb
Host smart-b087d6dd-6a93-4381-b4d5-83bde4f99f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757666318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.3757666318
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.1687318679
Short name T531
Test name
Test status
Simulation time 169954995 ps
CPU time 9.93 seconds
Started Jul 04 07:13:36 PM PDT 24
Finished Jul 04 07:14:14 PM PDT 24
Peak memory 250516 kb
Host smart-073d67cf-e139-412e-9222-d5c8489948b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687318679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.1687318679
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.3715970235
Short name T35
Test name
Test status
Simulation time 4588213157 ps
CPU time 84.78 seconds
Started Jul 04 07:13:39 PM PDT 24
Finished Jul 04 07:15:30 PM PDT 24
Peak memory 275696 kb
Host smart-9a1d4a2c-5244-4018-8328-ba5b40d1695d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715970235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.3715970235
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.3191712601
Short name T702
Test name
Test status
Simulation time 7098631199 ps
CPU time 274.76 seconds
Started Jul 04 07:13:48 PM PDT 24
Finished Jul 04 07:18:42 PM PDT 24
Peak memory 496420 kb
Host smart-a21fe0ec-e606-499c-920e-3bee96cf0641
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3191712601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all_with_rand_reset.3191712601
Directory /workspace/21.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.3432491710
Short name T672
Test name
Test status
Simulation time 25988536 ps
CPU time 0.96 seconds
Started Jul 04 07:13:35 PM PDT 24
Finished Jul 04 07:14:04 PM PDT 24
Peak memory 208432 kb
Host smart-8eff11bf-24fa-4d32-b83d-ca711219219c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432491710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.3432491710
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.1748491841
Short name T735
Test name
Test status
Simulation time 110314659 ps
CPU time 1.12 seconds
Started Jul 04 07:13:39 PM PDT 24
Finished Jul 04 07:14:06 PM PDT 24
Peak memory 208596 kb
Host smart-20c70551-e584-4e0f-bc4e-80e412b40c15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748491841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.1748491841
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.2363214985
Short name T727
Test name
Test status
Simulation time 1661078648 ps
CPU time 12.57 seconds
Started Jul 04 07:13:40 PM PDT 24
Finished Jul 04 07:14:18 PM PDT 24
Peak memory 217796 kb
Host smart-5b98f0c5-4a31-4937-893c-41b26259c471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363214985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.2363214985
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.1357017222
Short name T9
Test name
Test status
Simulation time 363141402 ps
CPU time 4.45 seconds
Started Jul 04 07:13:48 PM PDT 24
Finished Jul 04 07:14:12 PM PDT 24
Peak memory 217176 kb
Host smart-bd068539-0714-44bd-b2ef-ee3025cd7af3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357017222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.1357017222
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.2290884967
Short name T634
Test name
Test status
Simulation time 86669793 ps
CPU time 2.62 seconds
Started Jul 04 07:13:41 PM PDT 24
Finished Jul 04 07:14:08 PM PDT 24
Peak memory 217712 kb
Host smart-c2f65e78-01a8-4005-b7f6-12b99355cfa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290884967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.2290884967
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.687734060
Short name T446
Test name
Test status
Simulation time 1201026757 ps
CPU time 9.93 seconds
Started Jul 04 07:13:42 PM PDT 24
Finished Jul 04 07:14:16 PM PDT 24
Peak memory 225612 kb
Host smart-de9484cd-5a13-461d-8cc4-7e9240d437c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687734060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.687734060
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.1988871184
Short name T741
Test name
Test status
Simulation time 271335183 ps
CPU time 9.74 seconds
Started Jul 04 07:13:41 PM PDT 24
Finished Jul 04 07:14:15 PM PDT 24
Peak memory 225344 kb
Host smart-fb436f19-cfbd-4d43-8b87-83b52a0d5e25
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988871184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.1988871184
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.2294327579
Short name T816
Test name
Test status
Simulation time 1040761604 ps
CPU time 7.21 seconds
Started Jul 04 07:13:39 PM PDT 24
Finished Jul 04 07:14:12 PM PDT 24
Peak memory 217756 kb
Host smart-316ef797-2dfb-4e61-8b2e-c6b9649ed772
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294327579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
2294327579
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.1525848334
Short name T564
Test name
Test status
Simulation time 423785755 ps
CPU time 9.36 seconds
Started Jul 04 07:13:44 PM PDT 24
Finished Jul 04 07:14:15 PM PDT 24
Peak memory 225516 kb
Host smart-7f6182e1-6e4f-4a1d-9bf8-0463e3e62a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525848334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.1525848334
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.546475328
Short name T186
Test name
Test status
Simulation time 264687825 ps
CPU time 3.16 seconds
Started Jul 04 07:13:46 PM PDT 24
Finished Jul 04 07:14:10 PM PDT 24
Peak memory 217236 kb
Host smart-e050d640-5d2b-4a52-88d4-7cb7846eae58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546475328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.546475328
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.787179997
Short name T730
Test name
Test status
Simulation time 358241068 ps
CPU time 27.09 seconds
Started Jul 04 07:13:48 PM PDT 24
Finished Jul 04 07:14:34 PM PDT 24
Peak memory 250476 kb
Host smart-765250ab-8dd5-4b8c-8ca4-6d10a68538c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787179997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.787179997
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.2077494261
Short name T496
Test name
Test status
Simulation time 1088256078 ps
CPU time 6.69 seconds
Started Jul 04 07:13:41 PM PDT 24
Finished Jul 04 07:14:12 PM PDT 24
Peak memory 246764 kb
Host smart-b478e568-41dc-4cd2-b70d-c84811f901a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077494261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.2077494261
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.696392831
Short name T7
Test name
Test status
Simulation time 21854347609 ps
CPU time 63.94 seconds
Started Jul 04 07:13:49 PM PDT 24
Finished Jul 04 07:15:12 PM PDT 24
Peak memory 225628 kb
Host smart-96034876-2b94-42c8-bce4-8386ab8d5120
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696392831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.696392831
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.260698770
Short name T441
Test name
Test status
Simulation time 45588283 ps
CPU time 0.99 seconds
Started Jul 04 07:13:42 PM PDT 24
Finished Jul 04 07:14:07 PM PDT 24
Peak memory 211424 kb
Host smart-a35ffbd1-9788-4aa5-ae88-0f4731e20389
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260698770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ct
rl_volatile_unlock_smoke.260698770
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.3883549832
Short name T342
Test name
Test status
Simulation time 97618562 ps
CPU time 0.84 seconds
Started Jul 04 07:13:50 PM PDT 24
Finished Jul 04 07:14:09 PM PDT 24
Peak memory 208508 kb
Host smart-d840e787-d98b-4b6b-8a2c-9a0a468d1f55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883549832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.3883549832
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.1993126256
Short name T554
Test name
Test status
Simulation time 1325120769 ps
CPU time 10.13 seconds
Started Jul 04 07:13:43 PM PDT 24
Finished Jul 04 07:14:16 PM PDT 24
Peak memory 217748 kb
Host smart-e27b2850-4b84-49a1-bc1f-747e8442cad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993126256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.1993126256
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.918706976
Short name T213
Test name
Test status
Simulation time 772460174 ps
CPU time 2.63 seconds
Started Jul 04 07:13:49 PM PDT 24
Finished Jul 04 07:14:10 PM PDT 24
Peak memory 217208 kb
Host smart-4dfdebdf-757c-4e8c-a194-db97aa81b6b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918706976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.918706976
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.1061872484
Short name T346
Test name
Test status
Simulation time 220894525 ps
CPU time 4.79 seconds
Started Jul 04 07:13:40 PM PDT 24
Finished Jul 04 07:14:10 PM PDT 24
Peak memory 217780 kb
Host smart-9aa76dda-74f9-4d65-b07a-2789d0c8dd80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061872484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.1061872484
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.1260815153
Short name T273
Test name
Test status
Simulation time 1441678067 ps
CPU time 11.72 seconds
Started Jul 04 07:13:49 PM PDT 24
Finished Jul 04 07:14:19 PM PDT 24
Peak memory 225576 kb
Host smart-b68169de-c54c-4ddb-ba8b-125ce336cb05
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260815153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.1260815153
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.3899640828
Short name T595
Test name
Test status
Simulation time 319950724 ps
CPU time 14.61 seconds
Started Jul 04 07:13:50 PM PDT 24
Finished Jul 04 07:14:22 PM PDT 24
Peak memory 225536 kb
Host smart-24a007b8-74dd-46f9-9a17-8354268a2caf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899640828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.3899640828
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.655517616
Short name T272
Test name
Test status
Simulation time 278131417 ps
CPU time 11.17 seconds
Started Jul 04 07:13:50 PM PDT 24
Finished Jul 04 07:14:19 PM PDT 24
Peak memory 225520 kb
Host smart-008d41fa-6e19-485e-b6b9-b2b719cf4a11
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655517616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.655517616
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.4010136359
Short name T713
Test name
Test status
Simulation time 378024346 ps
CPU time 8.8 seconds
Started Jul 04 07:13:49 PM PDT 24
Finished Jul 04 07:14:16 PM PDT 24
Peak memory 224860 kb
Host smart-d705c147-1273-4b6f-a8fe-40994a52a34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010136359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.4010136359
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.3634838013
Short name T784
Test name
Test status
Simulation time 56280079 ps
CPU time 3.86 seconds
Started Jul 04 07:13:41 PM PDT 24
Finished Jul 04 07:14:09 PM PDT 24
Peak memory 217332 kb
Host smart-f6a1de3c-df0a-4401-ba24-4e4b4fa2d6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634838013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.3634838013
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.2341096707
Short name T312
Test name
Test status
Simulation time 313256058 ps
CPU time 29.3 seconds
Started Jul 04 07:13:40 PM PDT 24
Finished Jul 04 07:14:34 PM PDT 24
Peak memory 247852 kb
Host smart-48b68e74-9567-4485-b849-388ca049dfd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341096707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.2341096707
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.1379665267
Short name T125
Test name
Test status
Simulation time 91579047 ps
CPU time 6.42 seconds
Started Jul 04 07:13:40 PM PDT 24
Finished Jul 04 07:14:11 PM PDT 24
Peak memory 250020 kb
Host smart-454773fb-df23-4f13-84e2-165758047117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379665267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.1379665267
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.3869622017
Short name T608
Test name
Test status
Simulation time 26263852267 ps
CPU time 87.7 seconds
Started Jul 04 07:13:49 PM PDT 24
Finished Jul 04 07:15:35 PM PDT 24
Peak memory 266980 kb
Host smart-0ec7c745-6a87-418e-a21e-94851d6087ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869622017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.3869622017
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.1681110874
Short name T678
Test name
Test status
Simulation time 83086244129 ps
CPU time 525.11 seconds
Started Jul 04 07:13:49 PM PDT 24
Finished Jul 04 07:22:53 PM PDT 24
Peak memory 316248 kb
Host smart-995f003d-d582-44da-a79b-164c4bfb01ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1681110874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.1681110874
Directory /workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.4085728716
Short name T12
Test name
Test status
Simulation time 69694727 ps
CPU time 0.9 seconds
Started Jul 04 07:13:48 PM PDT 24
Finished Jul 04 07:14:09 PM PDT 24
Peak memory 208548 kb
Host smart-197723b3-df5b-46c9-8736-e722e37ae2e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085728716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.4085728716
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.2016816534
Short name T129
Test name
Test status
Simulation time 356140189 ps
CPU time 9.41 seconds
Started Jul 04 07:13:52 PM PDT 24
Finished Jul 04 07:14:17 PM PDT 24
Peak memory 217704 kb
Host smart-7c798942-2ffc-4270-874f-a4cfd35eb176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016816534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.2016816534
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.4291559998
Short name T832
Test name
Test status
Simulation time 259619920 ps
CPU time 7.08 seconds
Started Jul 04 07:13:52 PM PDT 24
Finished Jul 04 07:14:15 PM PDT 24
Peak memory 217184 kb
Host smart-7d635661-f7ce-4148-80e2-b9cbdb5dd593
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291559998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.4291559998
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.4104934042
Short name T334
Test name
Test status
Simulation time 157861609 ps
CPU time 3.98 seconds
Started Jul 04 07:13:50 PM PDT 24
Finished Jul 04 07:14:12 PM PDT 24
Peak memory 217756 kb
Host smart-0a525a3f-64b8-4231-9715-5fc48dfff85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104934042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.4104934042
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.1210658291
Short name T337
Test name
Test status
Simulation time 381335863 ps
CPU time 15.77 seconds
Started Jul 04 07:13:49 PM PDT 24
Finished Jul 04 07:14:23 PM PDT 24
Peak memory 225596 kb
Host smart-556f74a3-4676-44c5-ac7d-7ebed6d7c614
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210658291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.1210658291
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.2072996113
Short name T592
Test name
Test status
Simulation time 387613354 ps
CPU time 15.45 seconds
Started Jul 04 07:13:51 PM PDT 24
Finished Jul 04 07:14:23 PM PDT 24
Peak memory 217804 kb
Host smart-6ceb135e-681d-4096-9c01-a086b7f07504
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072996113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.2072996113
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.3576249516
Short name T72
Test name
Test status
Simulation time 340369477 ps
CPU time 11.86 seconds
Started Jul 04 07:13:48 PM PDT 24
Finished Jul 04 07:14:19 PM PDT 24
Peak memory 225596 kb
Host smart-9a38d199-b6af-448d-ba24-74e1cbb57f09
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576249516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
3576249516
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.3983865937
Short name T59
Test name
Test status
Simulation time 381978936 ps
CPU time 13.57 seconds
Started Jul 04 07:13:52 PM PDT 24
Finished Jul 04 07:14:22 PM PDT 24
Peak memory 217364 kb
Host smart-ae3b1d2e-77d1-4d3b-8c62-3124adf8c27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983865937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.3983865937
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.3993950354
Short name T298
Test name
Test status
Simulation time 66315359 ps
CPU time 2.68 seconds
Started Jul 04 07:13:49 PM PDT 24
Finished Jul 04 07:14:10 PM PDT 24
Peak memory 214284 kb
Host smart-b3d98cf1-904b-41f3-9ffb-ef844f5ca2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993950354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.3993950354
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.2695878414
Short name T207
Test name
Test status
Simulation time 1116722441 ps
CPU time 29.72 seconds
Started Jul 04 07:13:50 PM PDT 24
Finished Jul 04 07:14:38 PM PDT 24
Peak memory 250500 kb
Host smart-24bb0f7a-812f-4b53-a278-ae8c25b2db4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695878414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.2695878414
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.3445276760
Short name T855
Test name
Test status
Simulation time 267931274 ps
CPU time 7.71 seconds
Started Jul 04 07:13:51 PM PDT 24
Finished Jul 04 07:14:16 PM PDT 24
Peak memory 250520 kb
Host smart-e8156b93-1e39-4bba-b5e2-63658a750758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445276760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.3445276760
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.3345538464
Short name T863
Test name
Test status
Simulation time 8242142983 ps
CPU time 275.81 seconds
Started Jul 04 07:13:48 PM PDT 24
Finished Jul 04 07:18:43 PM PDT 24
Peak memory 267024 kb
Host smart-a7a49dee-4071-4e6f-bcce-320c80330419
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345538464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.3345538464
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.2945818031
Short name T175
Test name
Test status
Simulation time 750306023656 ps
CPU time 964.77 seconds
Started Jul 04 07:13:49 PM PDT 24
Finished Jul 04 07:30:13 PM PDT 24
Peak memory 372680 kb
Host smart-558b8740-7dac-4c6f-94e9-982311242730
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2945818031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all_with_rand_reset.2945818031
Directory /workspace/24.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.968926290
Short name T745
Test name
Test status
Simulation time 28588015 ps
CPU time 0.95 seconds
Started Jul 04 07:13:50 PM PDT 24
Finished Jul 04 07:14:09 PM PDT 24
Peak memory 211400 kb
Host smart-1d0bca1e-ffd4-4c4f-8c02-84bbbf0853c7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968926290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ct
rl_volatile_unlock_smoke.968926290
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.293175488
Short name T451
Test name
Test status
Simulation time 60317088 ps
CPU time 1.1 seconds
Started Jul 04 07:13:51 PM PDT 24
Finished Jul 04 07:14:09 PM PDT 24
Peak memory 208592 kb
Host smart-984d599d-1ba9-4f41-ab59-7edf46eb0340
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293175488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.293175488
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.1529550564
Short name T550
Test name
Test status
Simulation time 471113945 ps
CPU time 18.73 seconds
Started Jul 04 07:13:52 PM PDT 24
Finished Jul 04 07:14:27 PM PDT 24
Peak memory 217772 kb
Host smart-2e98501e-6d37-4beb-b348-853253acd7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529550564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.1529550564
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.1922595445
Short name T32
Test name
Test status
Simulation time 872680104 ps
CPU time 16.56 seconds
Started Jul 04 07:13:50 PM PDT 24
Finished Jul 04 07:14:24 PM PDT 24
Peak memory 217188 kb
Host smart-4a568beb-1517-48d4-8a5c-e63972a299b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922595445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.1922595445
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.3591100913
Short name T444
Test name
Test status
Simulation time 31650582 ps
CPU time 2.24 seconds
Started Jul 04 07:13:51 PM PDT 24
Finished Jul 04 07:14:10 PM PDT 24
Peak memory 217776 kb
Host smart-fac7fb2f-c81e-48a6-8b62-0554926c5f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591100913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.3591100913
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.3652183801
Short name T293
Test name
Test status
Simulation time 245391986 ps
CPU time 8.7 seconds
Started Jul 04 07:13:49 PM PDT 24
Finished Jul 04 07:14:16 PM PDT 24
Peak memory 225576 kb
Host smart-8c1c6eeb-9de4-4071-8a45-d287f35ef3b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652183801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.3652183801
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.633196480
Short name T447
Test name
Test status
Simulation time 2192887693 ps
CPU time 17.56 seconds
Started Jul 04 07:13:51 PM PDT 24
Finished Jul 04 07:14:26 PM PDT 24
Peak memory 225564 kb
Host smart-bf1cca17-b06b-48f7-b19e-06118e341604
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633196480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_di
gest.633196480
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.4103190307
Short name T421
Test name
Test status
Simulation time 370088385 ps
CPU time 10.06 seconds
Started Jul 04 07:13:51 PM PDT 24
Finished Jul 04 07:14:18 PM PDT 24
Peak memory 225484 kb
Host smart-fa162ab9-9ef3-49c1-9017-ebd09610126c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103190307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
4103190307
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.775695920
Short name T655
Test name
Test status
Simulation time 209806013 ps
CPU time 6.87 seconds
Started Jul 04 07:13:49 PM PDT 24
Finished Jul 04 07:14:15 PM PDT 24
Peak memory 217848 kb
Host smart-7a257c9f-949d-4d89-ab8e-d907b3e61973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775695920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.775695920
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.218835798
Short name T509
Test name
Test status
Simulation time 428250487 ps
CPU time 1.57 seconds
Started Jul 04 07:13:48 PM PDT 24
Finished Jul 04 07:14:09 PM PDT 24
Peak memory 213464 kb
Host smart-6483fd9b-9c4a-48f5-be3c-0740bfb3a19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218835798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.218835798
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.413616126
Short name T748
Test name
Test status
Simulation time 929489921 ps
CPU time 21.28 seconds
Started Jul 04 07:13:50 PM PDT 24
Finished Jul 04 07:14:29 PM PDT 24
Peak memory 250524 kb
Host smart-4846073b-5b1f-4c61-aff5-17b6cb912624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413616126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.413616126
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.2444310372
Short name T801
Test name
Test status
Simulation time 134239862 ps
CPU time 7.53 seconds
Started Jul 04 07:13:50 PM PDT 24
Finished Jul 04 07:14:15 PM PDT 24
Peak memory 250512 kb
Host smart-aaad2f1a-9fe9-4dbc-bb0b-c8cd6a3e5a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444310372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.2444310372
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.710717052
Short name T170
Test name
Test status
Simulation time 20263077973 ps
CPU time 334.71 seconds
Started Jul 04 07:13:50 PM PDT 24
Finished Jul 04 07:19:43 PM PDT 24
Peak memory 253404 kb
Host smart-c23d4385-5dfb-42e6-95bc-fb31054605d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=710717052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_stress_all_with_rand_reset.710717052
Directory /workspace/25.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.88023037
Short name T715
Test name
Test status
Simulation time 34504682 ps
CPU time 0.89 seconds
Started Jul 04 07:13:49 PM PDT 24
Finished Jul 04 07:14:08 PM PDT 24
Peak memory 211456 kb
Host smart-ca5e9b80-d1ca-46ee-8d0b-6a20769bce39
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88023037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctr
l_volatile_unlock_smoke.88023037
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.212091155
Short name T464
Test name
Test status
Simulation time 53774072 ps
CPU time 0.91 seconds
Started Jul 04 07:14:00 PM PDT 24
Finished Jul 04 07:14:10 PM PDT 24
Peak memory 208260 kb
Host smart-b16ad6a5-d826-4ceb-94a6-dbc3488f142e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212091155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.212091155
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.3957844972
Short name T864
Test name
Test status
Simulation time 1302090209 ps
CPU time 14.93 seconds
Started Jul 04 07:13:59 PM PDT 24
Finished Jul 04 07:14:24 PM PDT 24
Peak memory 217796 kb
Host smart-173a0c2f-a258-452f-ba4a-36e7a01f2307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957844972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.3957844972
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.2411424129
Short name T767
Test name
Test status
Simulation time 328226247 ps
CPU time 9.7 seconds
Started Jul 04 07:13:58 PM PDT 24
Finished Jul 04 07:14:19 PM PDT 24
Peak memory 216920 kb
Host smart-fe9bc013-5b6a-410e-9815-0b6f1e3c22e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411424129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.2411424129
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.3412671709
Short name T583
Test name
Test status
Simulation time 253202624 ps
CPU time 2.59 seconds
Started Jul 04 07:13:59 PM PDT 24
Finished Jul 04 07:14:12 PM PDT 24
Peak memory 217788 kb
Host smart-75c40147-38bb-4372-9cbd-f263f5250316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412671709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.3412671709
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.3543224003
Short name T663
Test name
Test status
Simulation time 431364075 ps
CPU time 17.28 seconds
Started Jul 04 07:13:59 PM PDT 24
Finished Jul 04 07:14:26 PM PDT 24
Peak memory 217912 kb
Host smart-30552af6-f948-46af-8f76-061946e38f37
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543224003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.3543224003
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.8859810
Short name T789
Test name
Test status
Simulation time 742466575 ps
CPU time 14.31 seconds
Started Jul 04 07:14:01 PM PDT 24
Finished Jul 04 07:14:24 PM PDT 24
Peak memory 225524 kb
Host smart-3a4adc91-e540-4a6f-b4ab-a5f72094e09f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8859810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dige
st_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_dige
st.8859810
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.1368795807
Short name T807
Test name
Test status
Simulation time 7307522028 ps
CPU time 19.05 seconds
Started Jul 04 07:13:58 PM PDT 24
Finished Jul 04 07:14:28 PM PDT 24
Peak memory 217768 kb
Host smart-33c74f92-a853-4f7e-aab2-e385bf53d009
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368795807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
1368795807
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.2846037387
Short name T465
Test name
Test status
Simulation time 1244249688 ps
CPU time 10.71 seconds
Started Jul 04 07:14:00 PM PDT 24
Finished Jul 04 07:14:20 PM PDT 24
Peak memory 217876 kb
Host smart-09ca8b73-ffa3-4401-b681-1c65c3945bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846037387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.2846037387
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.3717341054
Short name T82
Test name
Test status
Simulation time 95308713 ps
CPU time 1.17 seconds
Started Jul 04 07:13:52 PM PDT 24
Finished Jul 04 07:14:09 PM PDT 24
Peak memory 216600 kb
Host smart-0da0d986-da46-4476-b91a-4db5a57a4f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717341054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.3717341054
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.3830519792
Short name T440
Test name
Test status
Simulation time 830844880 ps
CPU time 28 seconds
Started Jul 04 07:14:01 PM PDT 24
Finished Jul 04 07:14:38 PM PDT 24
Peak memory 250508 kb
Host smart-ac231920-0587-4e83-a68e-7e3b06b8e3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830519792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.3830519792
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.4289578934
Short name T742
Test name
Test status
Simulation time 162476823 ps
CPU time 6.18 seconds
Started Jul 04 07:13:58 PM PDT 24
Finished Jul 04 07:14:15 PM PDT 24
Peak memory 246452 kb
Host smart-f3999131-f0b0-49f3-a9be-e2efe0eafa31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289578934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.4289578934
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.1358023560
Short name T843
Test name
Test status
Simulation time 9158150457 ps
CPU time 356.52 seconds
Started Jul 04 07:13:58 PM PDT 24
Finished Jul 04 07:20:06 PM PDT 24
Peak memory 273852 kb
Host smart-69e0eaef-8e12-4b7a-9ba0-2aab3546b045
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358023560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.1358023560
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.648352262
Short name T304
Test name
Test status
Simulation time 14438736 ps
CPU time 1.11 seconds
Started Jul 04 07:13:57 PM PDT 24
Finished Jul 04 07:14:10 PM PDT 24
Peak memory 211388 kb
Host smart-76abd9a8-e035-42f0-af8d-fb70cd5b4e70
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648352262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ct
rl_volatile_unlock_smoke.648352262
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.349304865
Short name T783
Test name
Test status
Simulation time 54738381 ps
CPU time 0.96 seconds
Started Jul 04 07:13:57 PM PDT 24
Finished Jul 04 07:14:10 PM PDT 24
Peak memory 208488 kb
Host smart-b87bc93d-73ab-4ff0-a5b4-c03f5c78b308
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349304865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.349304865
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.1464370620
Short name T193
Test name
Test status
Simulation time 343978584 ps
CPU time 11.75 seconds
Started Jul 04 07:13:59 PM PDT 24
Finished Jul 04 07:14:21 PM PDT 24
Peak memory 217808 kb
Host smart-1f9ebc79-5cae-4d8b-83e1-2a8ae8761522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464370620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.1464370620
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.2540190962
Short name T768
Test name
Test status
Simulation time 2132751494 ps
CPU time 12.8 seconds
Started Jul 04 07:13:59 PM PDT 24
Finished Jul 04 07:14:22 PM PDT 24
Peak memory 216908 kb
Host smart-db957780-6a53-4c57-96a3-485c0e46337a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540190962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.2540190962
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.3783942384
Short name T802
Test name
Test status
Simulation time 217895985 ps
CPU time 2.71 seconds
Started Jul 04 07:14:03 PM PDT 24
Finished Jul 04 07:14:13 PM PDT 24
Peak memory 217776 kb
Host smart-5d205b26-c973-43e6-9d54-e0585997c73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783942384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.3783942384
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.2120490187
Short name T809
Test name
Test status
Simulation time 420717805 ps
CPU time 15.59 seconds
Started Jul 04 07:14:00 PM PDT 24
Finished Jul 04 07:14:25 PM PDT 24
Peak memory 219436 kb
Host smart-dfc816cb-2813-42d5-8c57-afbd8ad6cd82
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120490187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.2120490187
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.193420451
Short name T331
Test name
Test status
Simulation time 341109366 ps
CPU time 13.48 seconds
Started Jul 04 07:14:01 PM PDT 24
Finished Jul 04 07:14:23 PM PDT 24
Peak memory 225400 kb
Host smart-f773be7a-3db5-4a74-a7bb-5eed1d18a92d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193420451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_di
gest.193420451
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.1796724509
Short name T504
Test name
Test status
Simulation time 670427673 ps
CPU time 8.05 seconds
Started Jul 04 07:14:00 PM PDT 24
Finished Jul 04 07:14:18 PM PDT 24
Peak memory 225508 kb
Host smart-8a40f6ba-32ef-4035-9e52-d0308609ae53
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796724509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
1796724509
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.2696374662
Short name T529
Test name
Test status
Simulation time 555967111 ps
CPU time 8.38 seconds
Started Jul 04 07:14:00 PM PDT 24
Finished Jul 04 07:14:18 PM PDT 24
Peak memory 217844 kb
Host smart-5c2a3240-f022-4a45-8cee-9c1003fffc1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696374662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.2696374662
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.427035236
Short name T257
Test name
Test status
Simulation time 190237636 ps
CPU time 1.43 seconds
Started Jul 04 07:13:57 PM PDT 24
Finished Jul 04 07:14:10 PM PDT 24
Peak memory 217180 kb
Host smart-3ab64b00-5fe3-41ce-bd86-3a7cfcbd8331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427035236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.427035236
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.1280512873
Short name T17
Test name
Test status
Simulation time 410058612 ps
CPU time 22.56 seconds
Started Jul 04 07:14:01 PM PDT 24
Finished Jul 04 07:14:32 PM PDT 24
Peak memory 250516 kb
Host smart-466389ed-81cb-4554-b7fe-39d9f98e5f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280512873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.1280512873
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.66107124
Short name T751
Test name
Test status
Simulation time 201975027 ps
CPU time 8.28 seconds
Started Jul 04 07:14:00 PM PDT 24
Finished Jul 04 07:14:18 PM PDT 24
Peak memory 250344 kb
Host smart-d5a9648a-68aa-493d-8800-113a5f38689b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66107124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.66107124
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.2127682790
Short name T56
Test name
Test status
Simulation time 153851288047 ps
CPU time 1460.22 seconds
Started Jul 04 07:14:00 PM PDT 24
Finished Jul 04 07:38:30 PM PDT 24
Peak memory 447384 kb
Host smart-d3969706-664d-418d-a8e1-8ba1dc7e0723
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2127682790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all_with_rand_reset.2127682790
Directory /workspace/27.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.819408102
Short name T627
Test name
Test status
Simulation time 13474993 ps
CPU time 0.98 seconds
Started Jul 04 07:13:59 PM PDT 24
Finished Jul 04 07:14:10 PM PDT 24
Peak memory 217180 kb
Host smart-afefafd7-5ba3-47e4-96bb-d9c7ac873ccf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819408102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ct
rl_volatile_unlock_smoke.819408102
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.1746959698
Short name T83
Test name
Test status
Simulation time 18435792 ps
CPU time 0.95 seconds
Started Jul 04 07:14:07 PM PDT 24
Finished Jul 04 07:14:12 PM PDT 24
Peak memory 208520 kb
Host smart-f7f4583c-2816-4e40-93c9-7ea9713db8c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746959698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.1746959698
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.3564571845
Short name T560
Test name
Test status
Simulation time 467316949 ps
CPU time 11.56 seconds
Started Jul 04 07:13:59 PM PDT 24
Finished Jul 04 07:14:21 PM PDT 24
Peak memory 217796 kb
Host smart-bc8262a1-4405-4e4e-b572-4a90b27dfc3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564571845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.3564571845
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.3729787457
Short name T580
Test name
Test status
Simulation time 329171572 ps
CPU time 2.86 seconds
Started Jul 04 07:13:59 PM PDT 24
Finished Jul 04 07:14:12 PM PDT 24
Peak memory 217200 kb
Host smart-9a49b1db-69c0-476e-8b72-d08edc97b85a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729787457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.3729787457
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.3649027424
Short name T111
Test name
Test status
Simulation time 124507041 ps
CPU time 3.31 seconds
Started Jul 04 07:14:02 PM PDT 24
Finished Jul 04 07:14:13 PM PDT 24
Peak memory 217864 kb
Host smart-80525a31-f40a-4816-bb8c-dc3a7120f67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649027424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.3649027424
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.1228361893
Short name T284
Test name
Test status
Simulation time 703966831 ps
CPU time 10.36 seconds
Started Jul 04 07:13:57 PM PDT 24
Finished Jul 04 07:14:19 PM PDT 24
Peak memory 225588 kb
Host smart-336ea484-912d-4bce-ac67-906bd455d153
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228361893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.1228361893
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.714874809
Short name T477
Test name
Test status
Simulation time 1396273564 ps
CPU time 10.21 seconds
Started Jul 04 07:14:00 PM PDT 24
Finished Jul 04 07:14:20 PM PDT 24
Peak memory 225500 kb
Host smart-f1818b4c-a575-4d31-a3bb-373b543cd0d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714874809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_di
gest.714874809
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.597173218
Short name T811
Test name
Test status
Simulation time 763107787 ps
CPU time 9.54 seconds
Started Jul 04 07:14:00 PM PDT 24
Finished Jul 04 07:14:19 PM PDT 24
Peak memory 217716 kb
Host smart-a49a66bf-0289-4738-b783-70984a4be844
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597173218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.597173218
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.3133803643
Short name T750
Test name
Test status
Simulation time 232293125 ps
CPU time 8.71 seconds
Started Jul 04 07:14:00 PM PDT 24
Finished Jul 04 07:14:18 PM PDT 24
Peak memory 225576 kb
Host smart-dacd7407-1dc2-4924-aff8-25d091e87e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133803643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.3133803643
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.10837074
Short name T866
Test name
Test status
Simulation time 259550682 ps
CPU time 3.91 seconds
Started Jul 04 07:14:02 PM PDT 24
Finished Jul 04 07:14:14 PM PDT 24
Peak memory 217164 kb
Host smart-2c49e53c-86f3-467f-b52e-b59dacf2b99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10837074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.10837074
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.3869492068
Short name T641
Test name
Test status
Simulation time 279409178 ps
CPU time 34.66 seconds
Started Jul 04 07:14:02 PM PDT 24
Finished Jul 04 07:14:45 PM PDT 24
Peak memory 250564 kb
Host smart-2a67f085-b099-4d2a-a757-e935ad5b76e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869492068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.3869492068
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.4232812636
Short name T466
Test name
Test status
Simulation time 378461225 ps
CPU time 6.61 seconds
Started Jul 04 07:14:02 PM PDT 24
Finished Jul 04 07:14:17 PM PDT 24
Peak memory 246372 kb
Host smart-230e1618-0c50-49ee-ab69-041df6b10051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232812636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.4232812636
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.1135262278
Short name T36
Test name
Test status
Simulation time 6826357604 ps
CPU time 111.06 seconds
Started Jul 04 07:14:07 PM PDT 24
Finished Jul 04 07:16:02 PM PDT 24
Peak memory 218732 kb
Host smart-74d109ec-8e41-4fa2-bdcb-85729e340619
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135262278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.1135262278
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.32274568
Short name T204
Test name
Test status
Simulation time 45778739 ps
CPU time 0.96 seconds
Started Jul 04 07:14:00 PM PDT 24
Finished Jul 04 07:14:10 PM PDT 24
Peak memory 217380 kb
Host smart-6753fad9-160e-42b2-b108-f7bc8352a1a4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32274568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctr
l_volatile_unlock_smoke.32274568
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.1857909873
Short name T605
Test name
Test status
Simulation time 18146361 ps
CPU time 0.93 seconds
Started Jul 04 07:14:15 PM PDT 24
Finished Jul 04 07:14:17 PM PDT 24
Peak memory 208552 kb
Host smart-4926acbb-871c-474d-8cc3-4d784708c396
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857909873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.1857909873
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.2898001176
Short name T551
Test name
Test status
Simulation time 298193697 ps
CPU time 9.16 seconds
Started Jul 04 07:14:05 PM PDT 24
Finished Jul 04 07:14:20 PM PDT 24
Peak memory 225600 kb
Host smart-145764a4-4aa5-4264-bb8b-4f48e2755113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898001176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.2898001176
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.2824462141
Short name T30
Test name
Test status
Simulation time 1493374348 ps
CPU time 7.25 seconds
Started Jul 04 07:14:05 PM PDT 24
Finished Jul 04 07:14:18 PM PDT 24
Peak memory 217176 kb
Host smart-1bad122f-6a78-4afd-8d45-f5b8b32b7865
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824462141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.2824462141
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.377919541
Short name T15
Test name
Test status
Simulation time 198922925 ps
CPU time 2.05 seconds
Started Jul 04 07:14:15 PM PDT 24
Finished Jul 04 07:14:19 PM PDT 24
Peak memory 221680 kb
Host smart-4fa6d6f6-9ad9-4e02-8ea5-77c26ac7a298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377919541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.377919541
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.189978706
Short name T364
Test name
Test status
Simulation time 806281783 ps
CPU time 10.15 seconds
Started Jul 04 07:14:06 PM PDT 24
Finished Jul 04 07:14:21 PM PDT 24
Peak memory 225560 kb
Host smart-761da7c2-79fb-453c-a311-9c98b061254e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189978706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.189978706
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.3806800380
Short name T734
Test name
Test status
Simulation time 2252440158 ps
CPU time 9.41 seconds
Started Jul 04 07:14:05 PM PDT 24
Finished Jul 04 07:14:20 PM PDT 24
Peak memory 225608 kb
Host smart-1daaa1e5-be47-49c5-9f71-b545a8b89b61
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806800380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.3806800380
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.114163287
Short name T486
Test name
Test status
Simulation time 994114693 ps
CPU time 9.49 seconds
Started Jul 04 07:14:15 PM PDT 24
Finished Jul 04 07:14:26 PM PDT 24
Peak memory 217736 kb
Host smart-0a4da629-09a1-4712-afa7-9df7505488da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114163287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.114163287
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.1205298367
Short name T352
Test name
Test status
Simulation time 2001928695 ps
CPU time 5.29 seconds
Started Jul 04 07:14:06 PM PDT 24
Finished Jul 04 07:14:16 PM PDT 24
Peak memory 217860 kb
Host smart-a14ba6b6-daa1-45e1-b4ba-90d0a00d8a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205298367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.1205298367
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.1338726576
Short name T88
Test name
Test status
Simulation time 593724942 ps
CPU time 4.24 seconds
Started Jul 04 07:14:06 PM PDT 24
Finished Jul 04 07:14:15 PM PDT 24
Peak memory 217220 kb
Host smart-dfa9d48c-1bb0-47a7-a9a9-80592cedfe31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338726576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.1338726576
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.3582497088
Short name T737
Test name
Test status
Simulation time 1068191141 ps
CPU time 28.78 seconds
Started Jul 04 07:14:06 PM PDT 24
Finished Jul 04 07:14:40 PM PDT 24
Peak memory 250568 kb
Host smart-cf91ea0e-8fb1-475d-8eba-0bb8eae6e236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582497088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.3582497088
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.3279035061
Short name T813
Test name
Test status
Simulation time 150180296 ps
CPU time 6.63 seconds
Started Jul 04 07:14:06 PM PDT 24
Finished Jul 04 07:14:18 PM PDT 24
Peak memory 249964 kb
Host smart-609a6bd2-55a4-42c3-bb65-16c7d4ce0142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279035061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.3279035061
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.954515604
Short name T233
Test name
Test status
Simulation time 14410187189 ps
CPU time 157 seconds
Started Jul 04 07:14:07 PM PDT 24
Finished Jul 04 07:16:48 PM PDT 24
Peak memory 250344 kb
Host smart-1a87a71a-e481-418b-953d-d6df1e10060d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954515604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.954515604
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.2169711067
Short name T182
Test name
Test status
Simulation time 10807770986 ps
CPU time 348.64 seconds
Started Jul 04 07:14:07 PM PDT 24
Finished Jul 04 07:20:00 PM PDT 24
Peak memory 283504 kb
Host smart-e442296a-b713-4444-a9cb-10055eb5c52e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2169711067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all_with_rand_reset.2169711067
Directory /workspace/29.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.2628176926
Short name T276
Test name
Test status
Simulation time 21585889 ps
CPU time 0.9 seconds
Started Jul 04 07:14:07 PM PDT 24
Finished Jul 04 07:14:12 PM PDT 24
Peak memory 211348 kb
Host smart-cc93fb1f-e0db-4e3f-9f29-f00249c904db
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628176926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.2628176926
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.2970970521
Short name T333
Test name
Test status
Simulation time 21787279 ps
CPU time 0.95 seconds
Started Jul 04 07:12:22 PM PDT 24
Finished Jul 04 07:12:33 PM PDT 24
Peak memory 208524 kb
Host smart-e9c6b445-455d-44f6-9c21-0c54b6601312
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970970521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.2970970521
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.1793601158
Short name T481
Test name
Test status
Simulation time 63459593 ps
CPU time 0.88 seconds
Started Jul 04 07:12:17 PM PDT 24
Finished Jul 04 07:12:20 PM PDT 24
Peak memory 208380 kb
Host smart-df4aee95-ed2f-4c1c-a927-235024e3fb18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793601158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.1793601158
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.2289512386
Short name T437
Test name
Test status
Simulation time 231720962 ps
CPU time 9.27 seconds
Started Jul 04 07:12:16 PM PDT 24
Finished Jul 04 07:12:28 PM PDT 24
Peak memory 225548 kb
Host smart-eabe9ee3-3c35-422c-b03a-32c11c35abd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289512386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.2289512386
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.3005939413
Short name T559
Test name
Test status
Simulation time 573720124 ps
CPU time 3.28 seconds
Started Jul 04 07:12:15 PM PDT 24
Finished Jul 04 07:12:21 PM PDT 24
Peak memory 217160 kb
Host smart-8a1a8f65-56df-4717-82b9-33a085e84ec0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005939413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.3005939413
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.181680755
Short name T448
Test name
Test status
Simulation time 11362257024 ps
CPU time 93.46 seconds
Started Jul 04 07:12:19 PM PDT 24
Finished Jul 04 07:13:57 PM PDT 24
Peak memory 219524 kb
Host smart-cf1e34cf-d33f-4810-b57d-09e741b4c86e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181680755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_err
ors.181680755
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.2023887428
Short name T76
Test name
Test status
Simulation time 373447559 ps
CPU time 4.75 seconds
Started Jul 04 07:12:15 PM PDT 24
Finished Jul 04 07:12:23 PM PDT 24
Peak memory 217212 kb
Host smart-5d1e63d3-c80f-4090-930a-8afb4ee62d8a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023887428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.2
023887428
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.2336369770
Short name T533
Test name
Test status
Simulation time 2282980477 ps
CPU time 16.3 seconds
Started Jul 04 07:12:17 PM PDT 24
Finished Jul 04 07:12:36 PM PDT 24
Peak memory 217772 kb
Host smart-d1a43e35-8093-454b-97d5-9e87a83b75f9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336369770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.2336369770
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.3014062782
Short name T567
Test name
Test status
Simulation time 1182988676 ps
CPU time 18.35 seconds
Started Jul 04 07:12:16 PM PDT 24
Finished Jul 04 07:12:37 PM PDT 24
Peak memory 217136 kb
Host smart-2b195b3a-64ca-48ba-b098-3d11fc37d821
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014062782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.3014062782
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.2450778004
Short name T264
Test name
Test status
Simulation time 82531679 ps
CPU time 2.04 seconds
Started Jul 04 07:12:18 PM PDT 24
Finished Jul 04 07:12:25 PM PDT 24
Peak memory 217100 kb
Host smart-4db1c6b7-663f-41f0-a00d-9e08b320fcc3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450778004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
2450778004
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.2265571930
Short name T517
Test name
Test status
Simulation time 15238084327 ps
CPU time 78.81 seconds
Started Jul 04 07:12:16 PM PDT 24
Finished Jul 04 07:13:38 PM PDT 24
Peak memory 266928 kb
Host smart-c037a07c-b766-4e69-8b6b-3f22e93d0f9f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265571930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.2265571930
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.3871259328
Short name T645
Test name
Test status
Simulation time 547146479 ps
CPU time 7.43 seconds
Started Jul 04 07:12:16 PM PDT 24
Finished Jul 04 07:12:26 PM PDT 24
Peak memory 222612 kb
Host smart-e33434f4-af05-4667-afcd-ab42e3ce364f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871259328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.3871259328
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.818352720
Short name T479
Test name
Test status
Simulation time 674017287 ps
CPU time 3.75 seconds
Started Jul 04 07:12:20 PM PDT 24
Finished Jul 04 07:12:31 PM PDT 24
Peak memory 217796 kb
Host smart-554125fd-5ead-404a-bb0f-4ef96d3645d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818352720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.818352720
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.550058084
Short name T13
Test name
Test status
Simulation time 1227138520 ps
CPU time 15.88 seconds
Started Jul 04 07:12:21 PM PDT 24
Finished Jul 04 07:12:46 PM PDT 24
Peak memory 214236 kb
Host smart-244682b1-0216-437c-bf4e-3ad2904da98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550058084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.550058084
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.935091772
Short name T102
Test name
Test status
Simulation time 232192284 ps
CPU time 44.41 seconds
Started Jul 04 07:12:22 PM PDT 24
Finished Jul 04 07:13:16 PM PDT 24
Peak memory 269520 kb
Host smart-1c7d7cd9-0ecc-4837-a060-4777a205c7f8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935091772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.935091772
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.4011191023
Short name T503
Test name
Test status
Simulation time 989539803 ps
CPU time 15.64 seconds
Started Jul 04 07:12:15 PM PDT 24
Finished Jul 04 07:12:34 PM PDT 24
Peak memory 218440 kb
Host smart-a095c27d-fcb0-4543-a1c9-ea0753db956a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011191023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.4011191023
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.4208768548
Short name T754
Test name
Test status
Simulation time 335363543 ps
CPU time 7.9 seconds
Started Jul 04 07:12:17 PM PDT 24
Finished Jul 04 07:12:28 PM PDT 24
Peak memory 225484 kb
Host smart-f9a7e0db-ae34-49bd-ad21-b3bdc3c58a58
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208768548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.4208768548
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.1509884072
Short name T417
Test name
Test status
Simulation time 374679102 ps
CPU time 11.59 seconds
Started Jul 04 07:12:16 PM PDT 24
Finished Jul 04 07:12:30 PM PDT 24
Peak memory 217752 kb
Host smart-5538a871-da06-4947-a7d8-ae490f058a8f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509884072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.1
509884072
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.1347956833
Short name T244
Test name
Test status
Simulation time 417689010 ps
CPU time 8.81 seconds
Started Jul 04 07:12:14 PM PDT 24
Finished Jul 04 07:12:25 PM PDT 24
Peak memory 217860 kb
Host smart-1642fef0-af5f-4b96-a46c-e1b1b9b77e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347956833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.1347956833
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.385620149
Short name T360
Test name
Test status
Simulation time 63090172 ps
CPU time 2.89 seconds
Started Jul 04 07:12:17 PM PDT 24
Finished Jul 04 07:12:23 PM PDT 24
Peak memory 214276 kb
Host smart-c729b573-9c90-42cd-be15-611d2212a6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385620149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.385620149
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.1039117136
Short name T327
Test name
Test status
Simulation time 357218588 ps
CPU time 30.97 seconds
Started Jul 04 07:12:19 PM PDT 24
Finished Jul 04 07:12:55 PM PDT 24
Peak memory 250488 kb
Host smart-ae24d572-8b57-443c-937c-002c932baf01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039117136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.1039117136
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.3644334042
Short name T521
Test name
Test status
Simulation time 66508083 ps
CPU time 3.1 seconds
Started Jul 04 07:12:22 PM PDT 24
Finished Jul 04 07:12:35 PM PDT 24
Peak memory 222260 kb
Host smart-45bf20a0-f822-48ca-bf16-fa099e633e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644334042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.3644334042
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.1546415812
Short name T860
Test name
Test status
Simulation time 8314537317 ps
CPU time 91.66 seconds
Started Jul 04 07:12:16 PM PDT 24
Finished Jul 04 07:13:51 PM PDT 24
Peak memory 275096 kb
Host smart-0464e057-8d72-4ec6-af9c-11309bcb029c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546415812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.1546415812
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.2885990945
Short name T869
Test name
Test status
Simulation time 137664308 ps
CPU time 0.98 seconds
Started Jul 04 07:12:16 PM PDT 24
Finished Jul 04 07:12:20 PM PDT 24
Peak memory 211412 kb
Host smart-7b8e5389-462e-476f-bb38-05ffcd940c31
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885990945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.2885990945
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.2972499591
Short name T575
Test name
Test status
Simulation time 27645080 ps
CPU time 1.1 seconds
Started Jul 04 07:14:07 PM PDT 24
Finished Jul 04 07:14:12 PM PDT 24
Peak memory 208624 kb
Host smart-1e10b26c-eecc-4b19-90f0-af7ae4666744
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972499591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.2972499591
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.3812969842
Short name T491
Test name
Test status
Simulation time 712453051 ps
CPU time 8.03 seconds
Started Jul 04 07:14:11 PM PDT 24
Finished Jul 04 07:14:20 PM PDT 24
Peak memory 218024 kb
Host smart-3467af04-ee0f-4424-9aab-a286a6542bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812969842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.3812969842
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.4020687373
Short name T454
Test name
Test status
Simulation time 584512087 ps
CPU time 3.67 seconds
Started Jul 04 07:14:09 PM PDT 24
Finished Jul 04 07:14:15 PM PDT 24
Peak memory 216684 kb
Host smart-c481f1a7-04d3-43b2-9617-79d389331d5e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020687373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.4020687373
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.4117069939
Short name T319
Test name
Test status
Simulation time 34646598 ps
CPU time 2.05 seconds
Started Jul 04 07:14:06 PM PDT 24
Finished Jul 04 07:14:13 PM PDT 24
Peak memory 217756 kb
Host smart-6566cd11-c2ad-475a-b292-76bb3fd6b5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117069939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.4117069939
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.668098276
Short name T289
Test name
Test status
Simulation time 180866032 ps
CPU time 9.55 seconds
Started Jul 04 07:14:07 PM PDT 24
Finished Jul 04 07:14:21 PM PDT 24
Peak memory 217524 kb
Host smart-baddc639-839d-40da-a887-1975023ae2fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668098276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.668098276
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.969641149
Short name T857
Test name
Test status
Simulation time 265022279 ps
CPU time 12.16 seconds
Started Jul 04 07:14:15 PM PDT 24
Finished Jul 04 07:14:29 PM PDT 24
Peak memory 225524 kb
Host smart-96a5342f-f82b-4c07-a360-7924725cd021
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969641149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_di
gest.969641149
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.40703901
Short name T396
Test name
Test status
Simulation time 1362332956 ps
CPU time 7.55 seconds
Started Jul 04 07:14:11 PM PDT 24
Finished Jul 04 07:14:20 PM PDT 24
Peak memory 217972 kb
Host smart-24b619bd-af02-4bbc-a07f-5fee77860a78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40703901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.40703901
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.1861541141
Short name T718
Test name
Test status
Simulation time 298725390 ps
CPU time 11.36 seconds
Started Jul 04 07:14:10 PM PDT 24
Finished Jul 04 07:14:23 PM PDT 24
Peak memory 225556 kb
Host smart-a6230e12-1b7f-40a4-a2cd-f3ee84c15ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861541141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.1861541141
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.2495832829
Short name T505
Test name
Test status
Simulation time 91738650 ps
CPU time 2.1 seconds
Started Jul 04 07:14:08 PM PDT 24
Finished Jul 04 07:14:13 PM PDT 24
Peak memory 213928 kb
Host smart-51d3d78d-2df0-4b3f-bd16-1af2d0d4d327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495832829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.2495832829
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.1084802281
Short name T98
Test name
Test status
Simulation time 1265668060 ps
CPU time 27.07 seconds
Started Jul 04 07:14:06 PM PDT 24
Finished Jul 04 07:14:38 PM PDT 24
Peak memory 250512 kb
Host smart-fc59e4ce-981d-4931-b148-e4dc97d9b761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084802281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.1084802281
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.1275741038
Short name T197
Test name
Test status
Simulation time 377772683 ps
CPU time 4.38 seconds
Started Jul 04 07:14:07 PM PDT 24
Finished Jul 04 07:14:16 PM PDT 24
Peak memory 217752 kb
Host smart-e18c0766-3610-4a41-8c08-1dab0a3dd740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275741038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.1275741038
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.2020546886
Short name T623
Test name
Test status
Simulation time 27320181603 ps
CPU time 159.12 seconds
Started Jul 04 07:14:08 PM PDT 24
Finished Jul 04 07:16:51 PM PDT 24
Peak memory 271900 kb
Host smart-a5b7591e-d09b-46da-a302-dd358f9614c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020546886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.2020546886
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.313820392
Short name T173
Test name
Test status
Simulation time 379807602995 ps
CPU time 311.97 seconds
Started Jul 04 07:14:07 PM PDT 24
Finished Jul 04 07:19:23 PM PDT 24
Peak memory 283460 kb
Host smart-d02d9b2c-e9d6-49b8-8402-fc1cde36ded7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=313820392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.313820392
Directory /workspace/30.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.868296965
Short name T328
Test name
Test status
Simulation time 15675220 ps
CPU time 0.98 seconds
Started Jul 04 07:14:15 PM PDT 24
Finished Jul 04 07:14:18 PM PDT 24
Peak memory 211408 kb
Host smart-9b40fff4-91a3-419d-8142-81ccdd838a94
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868296965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ct
rl_volatile_unlock_smoke.868296965
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.269219775
Short name T267
Test name
Test status
Simulation time 49761264 ps
CPU time 0.85 seconds
Started Jul 04 07:14:15 PM PDT 24
Finished Jul 04 07:14:17 PM PDT 24
Peak memory 208588 kb
Host smart-0caa869d-ece3-49dd-aed7-2586e14830d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269219775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.269219775
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.693002504
Short name T127
Test name
Test status
Simulation time 765956158 ps
CPU time 12.06 seconds
Started Jul 04 07:14:10 PM PDT 24
Finished Jul 04 07:14:24 PM PDT 24
Peak memory 217768 kb
Host smart-e56a32dc-583a-47b5-b84e-b596cbcd113b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693002504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.693002504
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.3853642979
Short name T28
Test name
Test status
Simulation time 482708914 ps
CPU time 12.39 seconds
Started Jul 04 07:14:05 PM PDT 24
Finished Jul 04 07:14:23 PM PDT 24
Peak memory 217152 kb
Host smart-1cfe7684-7ed1-42c7-97c4-6430910b2308
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853642979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.3853642979
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.2686782496
Short name T858
Test name
Test status
Simulation time 65138372 ps
CPU time 3.3 seconds
Started Jul 04 07:14:10 PM PDT 24
Finished Jul 04 07:14:15 PM PDT 24
Peak memory 217752 kb
Host smart-dd759dc0-a3c0-45b6-b641-ae748703b086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686782496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.2686782496
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.2944567885
Short name T646
Test name
Test status
Simulation time 521094324 ps
CPU time 8.07 seconds
Started Jul 04 07:14:09 PM PDT 24
Finished Jul 04 07:14:20 PM PDT 24
Peak memory 225552 kb
Host smart-541402a5-36d2-4df3-89f5-6369f83b92ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944567885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.2944567885
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.2465469551
Short name T661
Test name
Test status
Simulation time 1227573210 ps
CPU time 22.44 seconds
Started Jul 04 07:14:15 PM PDT 24
Finished Jul 04 07:14:39 PM PDT 24
Peak memory 225532 kb
Host smart-b47c0973-73b9-4e7a-8b6e-95962c8bef80
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465469551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.2465469551
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.2174208876
Short name T706
Test name
Test status
Simulation time 252184565 ps
CPU time 6.88 seconds
Started Jul 04 07:14:10 PM PDT 24
Finished Jul 04 07:14:19 PM PDT 24
Peak memory 217700 kb
Host smart-c7a5483c-0fea-4216-bba6-599a0fe6fe36
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174208876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
2174208876
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.638820173
Short name T480
Test name
Test status
Simulation time 539703231 ps
CPU time 9.35 seconds
Started Jul 04 07:14:06 PM PDT 24
Finished Jul 04 07:14:20 PM PDT 24
Peak memory 225544 kb
Host smart-6cd63120-c48f-4122-b11a-af7bc3990026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638820173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.638820173
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.2742002933
Short name T498
Test name
Test status
Simulation time 41118037 ps
CPU time 1.49 seconds
Started Jul 04 07:14:07 PM PDT 24
Finished Jul 04 07:14:13 PM PDT 24
Peak memory 217208 kb
Host smart-d156c4dd-8cf5-417d-9c7c-d334f033cde1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742002933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.2742002933
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.939601468
Short name T105
Test name
Test status
Simulation time 782505011 ps
CPU time 28.47 seconds
Started Jul 04 07:14:15 PM PDT 24
Finished Jul 04 07:14:45 PM PDT 24
Peak memory 250540 kb
Host smart-cff2eab5-0671-44df-ad64-4bda01547c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939601468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.939601468
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.3805139559
Short name T116
Test name
Test status
Simulation time 718317659 ps
CPU time 6.81 seconds
Started Jul 04 07:14:11 PM PDT 24
Finished Jul 04 07:14:19 PM PDT 24
Peak memory 250332 kb
Host smart-a88cbb04-b433-4ee9-af25-bd54bf6697c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805139559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.3805139559
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.1208194398
Short name T494
Test name
Test status
Simulation time 3402215902 ps
CPU time 133.5 seconds
Started Jul 04 07:14:13 PM PDT 24
Finished Jul 04 07:16:27 PM PDT 24
Peak memory 267076 kb
Host smart-bc36df8e-8908-4424-ab52-4097f8f79e0d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208194398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.1208194398
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.2207574442
Short name T530
Test name
Test status
Simulation time 15343449 ps
CPU time 0.93 seconds
Started Jul 04 07:14:05 PM PDT 24
Finished Jul 04 07:14:11 PM PDT 24
Peak memory 217504 kb
Host smart-8150e083-81b3-49af-b14d-ed1e6e8e992f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207574442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.2207574442
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.684437077
Short name T513
Test name
Test status
Simulation time 27946034 ps
CPU time 1.31 seconds
Started Jul 04 07:14:14 PM PDT 24
Finished Jul 04 07:14:15 PM PDT 24
Peak memory 208548 kb
Host smart-eff613be-5359-4b6c-af5d-4bd4072ac97a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684437077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.684437077
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.3872794325
Short name T365
Test name
Test status
Simulation time 416733790 ps
CPU time 9 seconds
Started Jul 04 07:14:14 PM PDT 24
Finished Jul 04 07:14:23 PM PDT 24
Peak memory 217776 kb
Host smart-683605a9-223d-418b-a281-d874b611eab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872794325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.3872794325
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.263284201
Short name T561
Test name
Test status
Simulation time 1101669578 ps
CPU time 3.39 seconds
Started Jul 04 07:14:13 PM PDT 24
Finished Jul 04 07:14:17 PM PDT 24
Peak memory 217208 kb
Host smart-45e84e3c-873a-448b-a4ea-f3cf125351e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263284201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.263284201
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.2437760137
Short name T247
Test name
Test status
Simulation time 48001069 ps
CPU time 2.23 seconds
Started Jul 04 07:14:13 PM PDT 24
Finished Jul 04 07:14:16 PM PDT 24
Peak memory 217724 kb
Host smart-6c87ec77-2999-4520-9264-ea19e7b5fb01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437760137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.2437760137
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.4026308161
Short name T808
Test name
Test status
Simulation time 261729243 ps
CPU time 9.95 seconds
Started Jul 04 07:14:14 PM PDT 24
Finished Jul 04 07:14:25 PM PDT 24
Peak memory 225572 kb
Host smart-0aa3c29a-278b-48d6-aac7-a0f4fa917edc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026308161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.4026308161
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.2240407994
Short name T658
Test name
Test status
Simulation time 304312109 ps
CPU time 12.05 seconds
Started Jul 04 07:14:15 PM PDT 24
Finished Jul 04 07:14:28 PM PDT 24
Peak memory 225532 kb
Host smart-bcdd02cd-d18c-41aa-b4f2-24799f3ae955
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240407994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.2240407994
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.413933157
Short name T774
Test name
Test status
Simulation time 1963252466 ps
CPU time 11.98 seconds
Started Jul 04 07:14:14 PM PDT 24
Finished Jul 04 07:14:26 PM PDT 24
Peak memory 217716 kb
Host smart-f836e2a9-a9be-4c99-804c-1d438d0328dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413933157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.413933157
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.2336873586
Short name T684
Test name
Test status
Simulation time 778281984 ps
CPU time 9.85 seconds
Started Jul 04 07:14:16 PM PDT 24
Finished Jul 04 07:14:26 PM PDT 24
Peak memory 224760 kb
Host smart-bd725681-e052-4869-b83d-1ebec31c626e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336873586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.2336873586
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.3025553205
Short name T426
Test name
Test status
Simulation time 201755257 ps
CPU time 5.83 seconds
Started Jul 04 07:14:13 PM PDT 24
Finished Jul 04 07:14:19 PM PDT 24
Peak memory 217188 kb
Host smart-8ad83ca7-d2c7-4166-a8ef-523bef5b733b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025553205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.3025553205
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.2701195554
Short name T732
Test name
Test status
Simulation time 719943244 ps
CPU time 18.65 seconds
Started Jul 04 07:14:15 PM PDT 24
Finished Jul 04 07:14:34 PM PDT 24
Peak memory 250516 kb
Host smart-3731d5dc-3598-47e0-ab6f-b081783aff2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701195554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.2701195554
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.692428114
Short name T637
Test name
Test status
Simulation time 112295249 ps
CPU time 6.6 seconds
Started Jul 04 07:14:16 PM PDT 24
Finished Jul 04 07:14:23 PM PDT 24
Peak memory 250516 kb
Host smart-a4231141-27ed-4998-b0d9-e057a3f47eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692428114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.692428114
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.89723594
Short name T338
Test name
Test status
Simulation time 3908428332 ps
CPU time 110.04 seconds
Started Jul 04 07:14:14 PM PDT 24
Finished Jul 04 07:16:04 PM PDT 24
Peak memory 250664 kb
Host smart-026f6ed7-1066-4c3a-b933-2e37a647285a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89723594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.lc_ctrl_stress_all.89723594
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.30237940
Short name T776
Test name
Test status
Simulation time 17414357426 ps
CPU time 618.44 seconds
Started Jul 04 07:14:14 PM PDT 24
Finished Jul 04 07:24:33 PM PDT 24
Peak memory 272636 kb
Host smart-806e1a3f-6a6a-48da-8343-66924c552add
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=30237940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.30237940
Directory /workspace/32.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.2946799046
Short name T390
Test name
Test status
Simulation time 13688990 ps
CPU time 0.95 seconds
Started Jul 04 07:14:16 PM PDT 24
Finished Jul 04 07:14:18 PM PDT 24
Peak memory 211424 kb
Host smart-1bea5c09-9bf1-4505-b52a-4317b92f2c06
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946799046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.2946799046
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.560851122
Short name T535
Test name
Test status
Simulation time 56355978 ps
CPU time 1.04 seconds
Started Jul 04 07:14:23 PM PDT 24
Finished Jul 04 07:14:26 PM PDT 24
Peak memory 208532 kb
Host smart-5cca841f-bb97-472d-8839-cd08e16f2ed6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560851122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.560851122
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.1496155560
Short name T586
Test name
Test status
Simulation time 206644109 ps
CPU time 10.35 seconds
Started Jul 04 07:14:20 PM PDT 24
Finished Jul 04 07:14:31 PM PDT 24
Peak memory 217804 kb
Host smart-407007b8-39f9-4d3a-9cd5-01cf06bd1e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496155560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.1496155560
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.2021342991
Short name T10
Test name
Test status
Simulation time 232924299 ps
CPU time 6.76 seconds
Started Jul 04 07:14:21 PM PDT 24
Finished Jul 04 07:14:28 PM PDT 24
Peak memory 217212 kb
Host smart-a433d4dd-6d79-4c27-a0f5-0de0458bf988
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021342991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.2021342991
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.2346955577
Short name T246
Test name
Test status
Simulation time 63553216 ps
CPU time 2.58 seconds
Started Jul 04 07:14:22 PM PDT 24
Finished Jul 04 07:14:25 PM PDT 24
Peak memory 217792 kb
Host smart-232f6828-619d-42a6-a8b6-39823ecce902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346955577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.2346955577
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.2804922119
Short name T183
Test name
Test status
Simulation time 1343530609 ps
CPU time 16.37 seconds
Started Jul 04 07:14:22 PM PDT 24
Finished Jul 04 07:14:39 PM PDT 24
Peak memory 225588 kb
Host smart-918b13e9-6492-4ba8-b16b-6076f2347514
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804922119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.2804922119
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.4110487831
Short name T249
Test name
Test status
Simulation time 723630864 ps
CPU time 12.47 seconds
Started Jul 04 07:14:22 PM PDT 24
Finished Jul 04 07:14:35 PM PDT 24
Peak memory 225480 kb
Host smart-59fb153c-366e-4793-a4eb-98f533f2a7f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110487831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.4110487831
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.866510818
Short name T792
Test name
Test status
Simulation time 990819832 ps
CPU time 6 seconds
Started Jul 04 07:14:23 PM PDT 24
Finished Jul 04 07:14:31 PM PDT 24
Peak memory 225500 kb
Host smart-090cc197-cd15-4cac-81d4-15730c0883ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866510818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.866510818
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.259017713
Short name T497
Test name
Test status
Simulation time 915515098 ps
CPU time 16.71 seconds
Started Jul 04 07:14:23 PM PDT 24
Finished Jul 04 07:14:41 PM PDT 24
Peak memory 217820 kb
Host smart-238119c3-f306-4066-979d-2424aecf3203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259017713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.259017713
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.2143437109
Short name T507
Test name
Test status
Simulation time 62520611 ps
CPU time 2.58 seconds
Started Jul 04 07:14:22 PM PDT 24
Finished Jul 04 07:14:26 PM PDT 24
Peak memory 214300 kb
Host smart-06d797ae-f9a3-4ef9-8751-d02eb080054e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143437109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.2143437109
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.1223771473
Short name T277
Test name
Test status
Simulation time 734992915 ps
CPU time 28.09 seconds
Started Jul 04 07:14:21 PM PDT 24
Finished Jul 04 07:14:50 PM PDT 24
Peak memory 250660 kb
Host smart-3c0e23fa-3c5f-47ac-8e13-90ad536e263d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223771473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.1223771473
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.644341520
Short name T731
Test name
Test status
Simulation time 64200019 ps
CPU time 7.84 seconds
Started Jul 04 07:14:21 PM PDT 24
Finished Jul 04 07:14:30 PM PDT 24
Peak memory 250564 kb
Host smart-2031529a-bdaa-4b5d-a8f7-01077c782678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644341520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.644341520
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.2611940500
Short name T538
Test name
Test status
Simulation time 5769736774 ps
CPU time 96.79 seconds
Started Jul 04 07:14:21 PM PDT 24
Finished Jul 04 07:15:59 PM PDT 24
Peak memory 275248 kb
Host smart-ff70e210-2847-438b-8902-24458c8ef393
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611940500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.2611940500
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.2261452962
Short name T407
Test name
Test status
Simulation time 53648307360 ps
CPU time 444.91 seconds
Started Jul 04 07:14:29 PM PDT 24
Finished Jul 04 07:21:55 PM PDT 24
Peak memory 267080 kb
Host smart-85cf1014-7eec-49ee-8d61-d09b216cdcec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2261452962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.2261452962
Directory /workspace/33.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.647151043
Short name T367
Test name
Test status
Simulation time 32846397 ps
CPU time 0.92 seconds
Started Jul 04 07:14:22 PM PDT 24
Finished Jul 04 07:14:23 PM PDT 24
Peak memory 208420 kb
Host smart-ebcf1bac-2cda-4d8a-9a35-c3f0d2c9d1fe
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647151043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ct
rl_volatile_unlock_smoke.647151043
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.3141388935
Short name T841
Test name
Test status
Simulation time 21677429 ps
CPU time 1.22 seconds
Started Jul 04 07:14:22 PM PDT 24
Finished Jul 04 07:14:24 PM PDT 24
Peak memory 208568 kb
Host smart-52c38493-6f16-4416-8c48-3baf3fe09373
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141388935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.3141388935
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.1892139171
Short name T357
Test name
Test status
Simulation time 343962958 ps
CPU time 14.26 seconds
Started Jul 04 07:14:28 PM PDT 24
Finished Jul 04 07:14:43 PM PDT 24
Peak memory 217768 kb
Host smart-e3090feb-f0e5-4dab-b7e6-515083e29dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892139171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.1892139171
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.4025397918
Short name T194
Test name
Test status
Simulation time 2611762058 ps
CPU time 7.03 seconds
Started Jul 04 07:14:21 PM PDT 24
Finished Jul 04 07:14:28 PM PDT 24
Peak memory 217224 kb
Host smart-ea0f4d1a-fae2-46e9-ad26-071dafc0070b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025397918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.4025397918
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.2022669397
Short name T570
Test name
Test status
Simulation time 194755504 ps
CPU time 2.47 seconds
Started Jul 04 07:14:21 PM PDT 24
Finished Jul 04 07:14:24 PM PDT 24
Peak memory 217744 kb
Host smart-1e8a9903-562c-4d20-94aa-3669ec0265be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022669397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.2022669397
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.3566056225
Short name T544
Test name
Test status
Simulation time 1262963672 ps
CPU time 10.84 seconds
Started Jul 04 07:14:27 PM PDT 24
Finished Jul 04 07:14:38 PM PDT 24
Peak memory 218440 kb
Host smart-a50691de-11fb-4d50-b110-fa23c43a1c1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566056225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.3566056225
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.436268336
Short name T265
Test name
Test status
Simulation time 1330614207 ps
CPU time 13.3 seconds
Started Jul 04 07:14:23 PM PDT 24
Finished Jul 04 07:14:37 PM PDT 24
Peak memory 225496 kb
Host smart-d891e6cd-99b9-4292-99d3-3507b4dba456
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436268336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_di
gest.436268336
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.2350802509
Short name T418
Test name
Test status
Simulation time 258076791 ps
CPU time 7.02 seconds
Started Jul 04 07:14:29 PM PDT 24
Finished Jul 04 07:14:37 PM PDT 24
Peak memory 217716 kb
Host smart-e07346a9-287d-4344-9fc6-f57f416ce4de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350802509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
2350802509
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.200990718
Short name T694
Test name
Test status
Simulation time 1103005222 ps
CPU time 6.89 seconds
Started Jul 04 07:14:21 PM PDT 24
Finished Jul 04 07:14:29 PM PDT 24
Peak memory 223852 kb
Host smart-7c6d4869-ce63-45d1-a573-0831df85c39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200990718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.200990718
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.2221575425
Short name T549
Test name
Test status
Simulation time 43462297 ps
CPU time 2.91 seconds
Started Jul 04 07:14:23 PM PDT 24
Finished Jul 04 07:14:28 PM PDT 24
Peak memory 214104 kb
Host smart-71ac9182-111d-4cd0-af3f-7534fe2559b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221575425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.2221575425
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.1710795001
Short name T749
Test name
Test status
Simulation time 576801754 ps
CPU time 18.52 seconds
Started Jul 04 07:14:20 PM PDT 24
Finished Jul 04 07:14:39 PM PDT 24
Peak memory 250584 kb
Host smart-b0b1b63a-267b-4d2f-8b48-724da6170e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710795001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.1710795001
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.1499026555
Short name T542
Test name
Test status
Simulation time 557236161 ps
CPU time 8.41 seconds
Started Jul 04 07:14:22 PM PDT 24
Finished Jul 04 07:14:31 PM PDT 24
Peak memory 249972 kb
Host smart-359db3f6-0b3c-489c-8b37-67b21e24e83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499026555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.1499026555
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.4011918873
Short name T483
Test name
Test status
Simulation time 5904816645 ps
CPU time 214.31 seconds
Started Jul 04 07:14:22 PM PDT 24
Finished Jul 04 07:17:57 PM PDT 24
Peak memory 283336 kb
Host smart-cb3b1375-c710-4a71-8e08-8d46148fb4b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011918873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.4011918873
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.3518250083
Short name T90
Test name
Test status
Simulation time 66602416 ps
CPU time 1.02 seconds
Started Jul 04 07:14:29 PM PDT 24
Finished Jul 04 07:14:31 PM PDT 24
Peak memory 217280 kb
Host smart-928848bb-b6fc-4de4-b493-5a04922c31dd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518250083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.3518250083
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.49312035
Short name T488
Test name
Test status
Simulation time 29358572 ps
CPU time 1.02 seconds
Started Jul 04 07:14:38 PM PDT 24
Finished Jul 04 07:14:40 PM PDT 24
Peak memory 208624 kb
Host smart-5d2fd2a3-7192-4fbc-a05d-b53487ae8b35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49312035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.49312035
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.4250771488
Short name T37
Test name
Test status
Simulation time 370988002 ps
CPU time 10.78 seconds
Started Jul 04 07:14:23 PM PDT 24
Finished Jul 04 07:14:35 PM PDT 24
Peak memory 217816 kb
Host smart-abb7ef63-7f98-42a6-9522-6a5a5f6de928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250771488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.4250771488
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.1732692026
Short name T26
Test name
Test status
Simulation time 430180425 ps
CPU time 5.87 seconds
Started Jul 04 07:14:21 PM PDT 24
Finished Jul 04 07:14:27 PM PDT 24
Peak memory 216692 kb
Host smart-48ac73db-978a-4d23-913b-3742a4d0f3f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732692026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.1732692026
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.4012530662
Short name T493
Test name
Test status
Simulation time 319318822 ps
CPU time 3.65 seconds
Started Jul 04 07:14:22 PM PDT 24
Finished Jul 04 07:14:26 PM PDT 24
Peak memory 221916 kb
Host smart-694f6bf1-9f03-45ea-9b99-249ff4ee6d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012530662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.4012530662
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.2963807657
Short name T343
Test name
Test status
Simulation time 1031960522 ps
CPU time 13.55 seconds
Started Jul 04 07:14:22 PM PDT 24
Finished Jul 04 07:14:37 PM PDT 24
Peak memory 218424 kb
Host smart-3c55f2ce-53d5-4ef5-82aa-652674e80252
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963807657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.2963807657
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.747186736
Short name T728
Test name
Test status
Simulation time 7882297912 ps
CPU time 30.36 seconds
Started Jul 04 07:14:34 PM PDT 24
Finished Jul 04 07:15:04 PM PDT 24
Peak memory 225528 kb
Host smart-1a47c289-2678-463e-80ad-cbe1c8deddbe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747186736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_di
gest.747186736
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.123065330
Short name T709
Test name
Test status
Simulation time 1437182440 ps
CPU time 13.73 seconds
Started Jul 04 07:14:32 PM PDT 24
Finished Jul 04 07:14:46 PM PDT 24
Peak memory 217688 kb
Host smart-98015013-2ca8-4801-b32e-d3e6ae4303cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123065330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.123065330
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.1703354162
Short name T33
Test name
Test status
Simulation time 484112312 ps
CPU time 10.95 seconds
Started Jul 04 07:14:30 PM PDT 24
Finished Jul 04 07:14:41 PM PDT 24
Peak memory 224692 kb
Host smart-5cb2a966-222b-4e93-8302-2ceb95777bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703354162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.1703354162
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.1877104161
Short name T354
Test name
Test status
Simulation time 16559745 ps
CPU time 1.13 seconds
Started Jul 04 07:14:21 PM PDT 24
Finished Jul 04 07:14:23 PM PDT 24
Peak memory 221224 kb
Host smart-8c33f40a-b847-4875-b8fe-d914ab1e8b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877104161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.1877104161
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.3981710713
Short name T455
Test name
Test status
Simulation time 455939497 ps
CPU time 24 seconds
Started Jul 04 07:14:24 PM PDT 24
Finished Jul 04 07:14:49 PM PDT 24
Peak memory 250540 kb
Host smart-f17e3ff2-9c87-4ae4-9547-ed674adac117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981710713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.3981710713
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.3477334726
Short name T463
Test name
Test status
Simulation time 146572108 ps
CPU time 7.56 seconds
Started Jul 04 07:14:24 PM PDT 24
Finished Jul 04 07:14:32 PM PDT 24
Peak memory 250532 kb
Host smart-a24ead0b-820d-40cb-86e6-e57e63d72eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477334726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.3477334726
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.1995772383
Short name T211
Test name
Test status
Simulation time 16583368810 ps
CPU time 139.86 seconds
Started Jul 04 07:14:37 PM PDT 24
Finished Jul 04 07:16:58 PM PDT 24
Peak memory 250604 kb
Host smart-e14cbbb6-164c-4fc0-810d-7b1253be2e21
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995772383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.1995772383
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.1497875362
Short name T660
Test name
Test status
Simulation time 15074130 ps
CPU time 1.05 seconds
Started Jul 04 07:14:23 PM PDT 24
Finished Jul 04 07:14:26 PM PDT 24
Peak memory 208472 kb
Host smart-8a261cea-9351-4607-b803-7b45744b3c8e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497875362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.1497875362
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.72203815
Short name T283
Test name
Test status
Simulation time 36481129 ps
CPU time 0.98 seconds
Started Jul 04 07:14:30 PM PDT 24
Finished Jul 04 07:14:31 PM PDT 24
Peak memory 208628 kb
Host smart-851a693d-9bc3-451b-a68c-77c6c586444e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72203815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.72203815
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.1416752609
Short name T462
Test name
Test status
Simulation time 471295521 ps
CPU time 10.77 seconds
Started Jul 04 07:14:31 PM PDT 24
Finished Jul 04 07:14:43 PM PDT 24
Peak memory 217756 kb
Host smart-63cdde3d-8ce4-4213-86f4-ce0db16ec087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416752609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.1416752609
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.1464318333
Short name T482
Test name
Test status
Simulation time 2189188963 ps
CPU time 14.43 seconds
Started Jul 04 07:14:30 PM PDT 24
Finished Jul 04 07:14:45 PM PDT 24
Peak memory 217104 kb
Host smart-531015ff-a63f-47ca-92c4-b9037b19f2eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464318333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.1464318333
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.2127694290
Short name T314
Test name
Test status
Simulation time 1493038563 ps
CPU time 2.84 seconds
Started Jul 04 07:14:32 PM PDT 24
Finished Jul 04 07:14:35 PM PDT 24
Peak memory 217740 kb
Host smart-f25cb4cf-777e-46e7-b388-8d9992f4aa6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127694290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.2127694290
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.2263731230
Short name T852
Test name
Test status
Simulation time 231634619 ps
CPU time 10.76 seconds
Started Jul 04 07:14:30 PM PDT 24
Finished Jul 04 07:14:41 PM PDT 24
Peak memory 225508 kb
Host smart-6e488159-4df5-4a70-871d-47c6bf4853d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263731230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.2263731230
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.4127613758
Short name T71
Test name
Test status
Simulation time 1272456964 ps
CPU time 7.91 seconds
Started Jul 04 07:14:31 PM PDT 24
Finished Jul 04 07:14:39 PM PDT 24
Peak memory 217720 kb
Host smart-20217c40-5013-4f62-abd6-e5ffe7c88e3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127613758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
4127613758
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.2943919333
Short name T189
Test name
Test status
Simulation time 412064353 ps
CPU time 10.49 seconds
Started Jul 04 07:14:37 PM PDT 24
Finished Jul 04 07:14:48 PM PDT 24
Peak memory 225488 kb
Host smart-9523fee4-961b-47f2-b07b-63446c3fc462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943919333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.2943919333
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.262334656
Short name T326
Test name
Test status
Simulation time 441457973 ps
CPU time 4.95 seconds
Started Jul 04 07:14:29 PM PDT 24
Finished Jul 04 07:14:35 PM PDT 24
Peak memory 217200 kb
Host smart-8a09fbee-4705-47ac-be3a-c96e5fa7b64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262334656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.262334656
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.1047913729
Short name T827
Test name
Test status
Simulation time 359616784 ps
CPU time 20.77 seconds
Started Jul 04 07:14:30 PM PDT 24
Finished Jul 04 07:14:52 PM PDT 24
Peak memory 250496 kb
Host smart-9b193feb-b44d-40d3-9d8e-a9eba35db533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047913729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.1047913729
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.3900865322
Short name T822
Test name
Test status
Simulation time 125776467 ps
CPU time 3.05 seconds
Started Jul 04 07:14:38 PM PDT 24
Finished Jul 04 07:14:41 PM PDT 24
Peak memory 222028 kb
Host smart-2836ef96-1dab-467d-ab6d-220cf9a67fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900865322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.3900865322
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.160163651
Short name T387
Test name
Test status
Simulation time 358260503 ps
CPU time 13.27 seconds
Started Jul 04 07:14:30 PM PDT 24
Finished Jul 04 07:14:44 PM PDT 24
Peak memory 225568 kb
Host smart-cc77a698-1d19-47f8-aa18-1e322a6101ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160163651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.160163651
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.2282233613
Short name T828
Test name
Test status
Simulation time 40354073 ps
CPU time 0.97 seconds
Started Jul 04 07:14:29 PM PDT 24
Finished Jul 04 07:14:31 PM PDT 24
Peak memory 211460 kb
Host smart-63eb4d7b-4f2f-4fdb-9aec-83f5233c886b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282233613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.2282233613
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.3130733721
Short name T489
Test name
Test status
Simulation time 105258859 ps
CPU time 0.95 seconds
Started Jul 04 07:14:39 PM PDT 24
Finished Jul 04 07:14:41 PM PDT 24
Peak memory 208572 kb
Host smart-47f25a8b-dff5-47f3-942c-3fba56684e6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130733721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.3130733721
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.3044687666
Short name T574
Test name
Test status
Simulation time 3089170946 ps
CPU time 20.84 seconds
Started Jul 04 07:14:41 PM PDT 24
Finished Jul 04 07:15:02 PM PDT 24
Peak memory 225668 kb
Host smart-52b69a6d-5f1f-4281-87d0-4dd5c3d9b417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044687666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.3044687666
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.2527554846
Short name T188
Test name
Test status
Simulation time 490641998 ps
CPU time 6.86 seconds
Started Jul 04 07:14:38 PM PDT 24
Finished Jul 04 07:14:46 PM PDT 24
Peak memory 217220 kb
Host smart-8cb552c1-1621-4a66-bd39-c53e52bc1de7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527554846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.2527554846
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.3735512995
Short name T644
Test name
Test status
Simulation time 246586428 ps
CPU time 4.21 seconds
Started Jul 04 07:14:39 PM PDT 24
Finished Jul 04 07:14:44 PM PDT 24
Peak memory 217776 kb
Host smart-93a4343d-d1ee-4eb2-abab-43658422fa2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735512995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.3735512995
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.1151694224
Short name T532
Test name
Test status
Simulation time 762657357 ps
CPU time 17.95 seconds
Started Jul 04 07:14:43 PM PDT 24
Finished Jul 04 07:15:02 PM PDT 24
Peak memory 218440 kb
Host smart-aef64c3a-d688-470d-b404-a8c2c9c9afac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151694224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.1151694224
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.35109994
Short name T456
Test name
Test status
Simulation time 317352664 ps
CPU time 12.32 seconds
Started Jul 04 07:14:42 PM PDT 24
Finished Jul 04 07:14:55 PM PDT 24
Peak memory 225448 kb
Host smart-69701f3b-34a1-4d67-819d-4f9af2a4893e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35109994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_dig
est.35109994
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.2777859294
Short name T596
Test name
Test status
Simulation time 590922032 ps
CPU time 9.83 seconds
Started Jul 04 07:14:39 PM PDT 24
Finished Jul 04 07:14:50 PM PDT 24
Peak memory 225468 kb
Host smart-766f4d39-dbde-4621-9837-9394298b5c5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777859294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
2777859294
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.3634780773
Short name T200
Test name
Test status
Simulation time 377554185 ps
CPU time 7.22 seconds
Started Jul 04 07:14:40 PM PDT 24
Finished Jul 04 07:14:48 PM PDT 24
Peak memory 224776 kb
Host smart-7273fda0-08a6-46f8-be56-05f0c854e91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634780773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.3634780773
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.1357340693
Short name T691
Test name
Test status
Simulation time 77050345 ps
CPU time 1.49 seconds
Started Jul 04 07:14:38 PM PDT 24
Finished Jul 04 07:14:40 PM PDT 24
Peak memory 217228 kb
Host smart-24bcfdf5-ee40-43be-87a3-6053c965ac05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357340693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.1357340693
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.2862453528
Short name T613
Test name
Test status
Simulation time 560422571 ps
CPU time 32.74 seconds
Started Jul 04 07:14:30 PM PDT 24
Finished Jul 04 07:15:03 PM PDT 24
Peak memory 250532 kb
Host smart-ece38a5e-1024-45e7-a597-76bcfa21906a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862453528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.2862453528
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.388143568
Short name T199
Test name
Test status
Simulation time 137606191 ps
CPU time 7.13 seconds
Started Jul 04 07:14:40 PM PDT 24
Finished Jul 04 07:14:47 PM PDT 24
Peak memory 249940 kb
Host smart-af416ffa-20db-41f1-836e-0ba4a63eeec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388143568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.388143568
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.1659123066
Short name T315
Test name
Test status
Simulation time 967706726 ps
CPU time 14.59 seconds
Started Jul 04 07:14:40 PM PDT 24
Finished Jul 04 07:14:55 PM PDT 24
Peak memory 246424 kb
Host smart-93e57f7e-1fe2-4446-ae7d-b4298e729eb9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659123066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.1659123066
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.108880404
Short name T835
Test name
Test status
Simulation time 16852954 ps
CPU time 1.2 seconds
Started Jul 04 07:14:31 PM PDT 24
Finished Jul 04 07:14:33 PM PDT 24
Peak memory 211428 kb
Host smart-9430111e-212d-4432-be1e-e3f228bf2873
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108880404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ct
rl_volatile_unlock_smoke.108880404
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.3379473020
Short name T266
Test name
Test status
Simulation time 25985329 ps
CPU time 1.04 seconds
Started Jul 04 07:14:40 PM PDT 24
Finished Jul 04 07:14:42 PM PDT 24
Peak memory 208500 kb
Host smart-a3b7bfdc-d6a9-4adb-a3d1-c21f215e0026
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379473020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.3379473020
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.658545303
Short name T557
Test name
Test status
Simulation time 724571036 ps
CPU time 11.71 seconds
Started Jul 04 07:14:38 PM PDT 24
Finished Jul 04 07:14:50 PM PDT 24
Peak memory 217780 kb
Host smart-d5475cee-88fe-47d5-828f-7e8d8878607b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658545303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.658545303
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.1939432502
Short name T203
Test name
Test status
Simulation time 1126981438 ps
CPU time 4.18 seconds
Started Jul 04 07:14:40 PM PDT 24
Finished Jul 04 07:14:44 PM PDT 24
Peak memory 217168 kb
Host smart-19f8c682-35f5-4153-8bab-6836df193f13
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939432502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.1939432502
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.4270212538
Short name T703
Test name
Test status
Simulation time 168125667 ps
CPU time 3.61 seconds
Started Jul 04 07:14:41 PM PDT 24
Finished Jul 04 07:14:45 PM PDT 24
Peak memory 217768 kb
Host smart-8188c9c1-0387-4665-952a-4d0fb87c5262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270212538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.4270212538
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.1497532312
Short name T701
Test name
Test status
Simulation time 212684390 ps
CPU time 8.46 seconds
Started Jul 04 07:14:40 PM PDT 24
Finished Jul 04 07:14:49 PM PDT 24
Peak memory 225532 kb
Host smart-ad4780e4-d482-4aca-98e4-3c627e3c8c4e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497532312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.1497532312
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.2602980256
Short name T442
Test name
Test status
Simulation time 1066252526 ps
CPU time 7.85 seconds
Started Jul 04 07:14:42 PM PDT 24
Finished Jul 04 07:14:50 PM PDT 24
Peak memory 217748 kb
Host smart-aca7d13f-09a4-4a46-9357-58f2906fea1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602980256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
2602980256
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.485960879
Short name T431
Test name
Test status
Simulation time 517793147 ps
CPU time 13.74 seconds
Started Jul 04 07:14:41 PM PDT 24
Finished Jul 04 07:14:55 PM PDT 24
Peak memory 225600 kb
Host smart-243bdc67-701b-4f00-8fca-37ccae7dbf95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485960879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.485960879
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.4137340379
Short name T853
Test name
Test status
Simulation time 27693769 ps
CPU time 2.03 seconds
Started Jul 04 07:14:40 PM PDT 24
Finished Jul 04 07:14:43 PM PDT 24
Peak memory 222728 kb
Host smart-56960ee8-c6eb-4820-ae8a-6d12e8c313c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137340379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.4137340379
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.3385126220
Short name T263
Test name
Test status
Simulation time 225846302 ps
CPU time 24.3 seconds
Started Jul 04 07:14:43 PM PDT 24
Finished Jul 04 07:15:07 PM PDT 24
Peak memory 250512 kb
Host smart-2f8b5c53-06fc-4688-9d16-8dc7241beb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385126220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.3385126220
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.3216322478
Short name T34
Test name
Test status
Simulation time 320317013 ps
CPU time 8.81 seconds
Started Jul 04 07:14:44 PM PDT 24
Finished Jul 04 07:14:53 PM PDT 24
Peak memory 250540 kb
Host smart-e6daa18a-bc74-4bff-b58a-f1a570297778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216322478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.3216322478
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.2076404152
Short name T625
Test name
Test status
Simulation time 23797278552 ps
CPU time 182.14 seconds
Started Jul 04 07:14:40 PM PDT 24
Finished Jul 04 07:17:43 PM PDT 24
Peak memory 268596 kb
Host smart-46033bfa-1e64-4be0-b87d-47ca32dfdc6b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076404152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.2076404152
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.3872693100
Short name T43
Test name
Test status
Simulation time 13347041 ps
CPU time 1.09 seconds
Started Jul 04 07:14:42 PM PDT 24
Finished Jul 04 07:14:43 PM PDT 24
Peak memory 208744 kb
Host smart-79211fbe-121e-46fc-a4c1-70f7318165c2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872693100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.3872693100
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.1931999185
Short name T525
Test name
Test status
Simulation time 185886802 ps
CPU time 1.07 seconds
Started Jul 04 07:14:49 PM PDT 24
Finished Jul 04 07:14:52 PM PDT 24
Peak memory 208596 kb
Host smart-aff087f0-f452-44f5-800d-681a7d42bc5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931999185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.1931999185
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.902512489
Short name T591
Test name
Test status
Simulation time 2896501302 ps
CPU time 7.11 seconds
Started Jul 04 07:14:47 PM PDT 24
Finished Jul 04 07:14:56 PM PDT 24
Peak memory 217860 kb
Host smart-04cb1c6e-1592-4836-a301-3ec492f35516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902512489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.902512489
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.1898381915
Short name T785
Test name
Test status
Simulation time 2206820665 ps
CPU time 5.98 seconds
Started Jul 04 07:14:46 PM PDT 24
Finished Jul 04 07:14:52 PM PDT 24
Peak memory 217024 kb
Host smart-41848e2a-8da7-43c8-a110-3ad97034583f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898381915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.1898381915
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.1977747401
Short name T332
Test name
Test status
Simulation time 77510678 ps
CPU time 3.89 seconds
Started Jul 04 07:14:47 PM PDT 24
Finished Jul 04 07:14:53 PM PDT 24
Peak memory 221924 kb
Host smart-db94cd46-4ed4-495d-9abd-72c55c1e88d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977747401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.1977747401
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.3277115658
Short name T54
Test name
Test status
Simulation time 338967136 ps
CPU time 15.25 seconds
Started Jul 04 07:14:48 PM PDT 24
Finished Jul 04 07:15:04 PM PDT 24
Peak memory 218384 kb
Host smart-3fca898e-8447-4daf-9711-237c482a598b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277115658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.3277115658
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.399768163
Short name T611
Test name
Test status
Simulation time 635304064 ps
CPU time 8.91 seconds
Started Jul 04 07:14:50 PM PDT 24
Finished Jul 04 07:15:01 PM PDT 24
Peak memory 225500 kb
Host smart-a202ae7c-d8cd-41a2-b69a-e60181376cf5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399768163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_di
gest.399768163
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.3453165009
Short name T668
Test name
Test status
Simulation time 210889903 ps
CPU time 6.67 seconds
Started Jul 04 07:14:46 PM PDT 24
Finished Jul 04 07:14:54 PM PDT 24
Peak memory 217716 kb
Host smart-5fc0be08-6b40-4ecf-819e-3329b781a311
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453165009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
3453165009
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.2749344852
Short name T398
Test name
Test status
Simulation time 438665605 ps
CPU time 6.88 seconds
Started Jul 04 07:14:46 PM PDT 24
Finished Jul 04 07:14:53 PM PDT 24
Peak memory 224012 kb
Host smart-aefda737-6329-45a6-8833-dfacfe1620e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749344852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.2749344852
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.76282532
Short name T268
Test name
Test status
Simulation time 191681549 ps
CPU time 2.74 seconds
Started Jul 04 07:14:40 PM PDT 24
Finished Jul 04 07:14:43 PM PDT 24
Peak memory 217336 kb
Host smart-5cb52a2c-e2b3-4faf-bbab-f9c456926e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76282532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.76282532
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.1691488365
Short name T629
Test name
Test status
Simulation time 437975258 ps
CPU time 20.95 seconds
Started Jul 04 07:14:38 PM PDT 24
Finished Jul 04 07:15:00 PM PDT 24
Peak memory 250524 kb
Host smart-b14c3954-28e1-44fa-abed-7a5ba4c1eed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691488365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.1691488365
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.2969462166
Short name T743
Test name
Test status
Simulation time 306737902 ps
CPU time 9.82 seconds
Started Jul 04 07:14:39 PM PDT 24
Finished Jul 04 07:14:50 PM PDT 24
Peak memory 250480 kb
Host smart-1b1b0d81-9f84-4395-91e7-001ec8b22a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969462166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.2969462166
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.2424984277
Short name T307
Test name
Test status
Simulation time 12216530311 ps
CPU time 446.77 seconds
Started Jul 04 07:14:50 PM PDT 24
Finished Jul 04 07:22:19 PM PDT 24
Peak memory 528924 kb
Host smart-bf492301-06c3-4dce-9274-9f9a034b884d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424984277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.2424984277
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.3803771493
Short name T174
Test name
Test status
Simulation time 55241829659 ps
CPU time 945.8 seconds
Started Jul 04 07:14:53 PM PDT 24
Finished Jul 04 07:30:42 PM PDT 24
Peak memory 496424 kb
Host smart-20643480-552f-4805-9972-4e7ae3e18f82
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3803771493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.3803771493
Directory /workspace/39.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.4294749130
Short name T717
Test name
Test status
Simulation time 23426297 ps
CPU time 0.92 seconds
Started Jul 04 07:14:42 PM PDT 24
Finished Jul 04 07:14:43 PM PDT 24
Peak memory 207820 kb
Host smart-88db7299-66a7-4fc4-bf74-10987aaa85fb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294749130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.4294749130
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.753912456
Short name T302
Test name
Test status
Simulation time 112531965 ps
CPU time 0.94 seconds
Started Jul 04 07:12:26 PM PDT 24
Finished Jul 04 07:12:42 PM PDT 24
Peak memory 208544 kb
Host smart-041c5b8d-4167-4628-8fbb-27dd8d195b13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753912456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.753912456
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.111876237
Short name T579
Test name
Test status
Simulation time 549174830 ps
CPU time 22.39 seconds
Started Jul 04 07:12:25 PM PDT 24
Finished Jul 04 07:13:01 PM PDT 24
Peak memory 217804 kb
Host smart-e6d7cd40-b851-4d61-bef4-ecefc409df16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111876237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.111876237
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.2177568631
Short name T471
Test name
Test status
Simulation time 335477332 ps
CPU time 7.42 seconds
Started Jul 04 07:12:26 PM PDT 24
Finished Jul 04 07:12:48 PM PDT 24
Peak memory 217128 kb
Host smart-0cb990bd-3d39-4987-9f2c-322e5813013d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177568631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.2177568631
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.1529208992
Short name T52
Test name
Test status
Simulation time 6817832955 ps
CPU time 44.98 seconds
Started Jul 04 07:12:25 PM PDT 24
Finished Jul 04 07:13:22 PM PDT 24
Peak memory 218432 kb
Host smart-af25b962-ae7d-4f50-aeae-15fd287b0c5d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529208992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.1529208992
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.2072606046
Short name T610
Test name
Test status
Simulation time 779883044 ps
CPU time 10.05 seconds
Started Jul 04 07:12:24 PM PDT 24
Finished Jul 04 07:12:46 PM PDT 24
Peak memory 217248 kb
Host smart-842585e6-9702-4ba9-be98-15814aa7e3c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072606046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.2
072606046
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.2897454884
Short name T614
Test name
Test status
Simulation time 3734917354 ps
CPU time 24.33 seconds
Started Jul 04 07:12:22 PM PDT 24
Finished Jul 04 07:12:57 PM PDT 24
Peak memory 225568 kb
Host smart-2a617b73-251f-471e-bdda-cd66fee4c349
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897454884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.2897454884
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.2064721148
Short name T80
Test name
Test status
Simulation time 685735065 ps
CPU time 19.59 seconds
Started Jul 04 07:12:25 PM PDT 24
Finished Jul 04 07:12:59 PM PDT 24
Peak memory 217100 kb
Host smart-01b43643-7a01-47b8-87ef-576334cf45f5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064721148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.2064721148
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.3681850152
Short name T609
Test name
Test status
Simulation time 299825339 ps
CPU time 8.53 seconds
Started Jul 04 07:12:24 PM PDT 24
Finished Jul 04 07:12:45 PM PDT 24
Peak memory 217144 kb
Host smart-2824c54b-90c5-40bd-9c44-5e4c5f4408d6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681850152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
3681850152
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.3631492225
Short name T540
Test name
Test status
Simulation time 2436079890 ps
CPU time 51.02 seconds
Started Jul 04 07:12:23 PM PDT 24
Finished Jul 04 07:13:25 PM PDT 24
Peak memory 267036 kb
Host smart-708dc20f-532a-4c60-9eab-180a2681a50b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631492225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.3631492225
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.4257092272
Short name T290
Test name
Test status
Simulation time 739754996 ps
CPU time 15.67 seconds
Started Jul 04 07:12:24 PM PDT 24
Finished Jul 04 07:12:51 PM PDT 24
Peak memory 249032 kb
Host smart-ec31543d-8fa6-4e60-a560-01d5f5a6d63f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257092272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.4257092272
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.3565862342
Short name T351
Test name
Test status
Simulation time 277021431 ps
CPU time 2.13 seconds
Started Jul 04 07:12:22 PM PDT 24
Finished Jul 04 07:12:35 PM PDT 24
Peak memory 221736 kb
Host smart-416389bb-2035-4b46-b970-aec35ad6d338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565862342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.3565862342
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.1375389616
Short name T401
Test name
Test status
Simulation time 770726293 ps
CPU time 20.08 seconds
Started Jul 04 07:12:24 PM PDT 24
Finished Jul 04 07:12:57 PM PDT 24
Peak memory 217188 kb
Host smart-fb1b24c4-ff7b-44ba-809c-c93a711ed39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375389616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.1375389616
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.3160700652
Short name T63
Test name
Test status
Simulation time 439680232 ps
CPU time 22.52 seconds
Started Jul 04 07:12:24 PM PDT 24
Finished Jul 04 07:12:59 PM PDT 24
Peak memory 283936 kb
Host smart-cb217543-d126-44d3-b364-b00dd91becc2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160700652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.3160700652
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.402988623
Short name T120
Test name
Test status
Simulation time 934260940 ps
CPU time 8.04 seconds
Started Jul 04 07:12:24 PM PDT 24
Finished Jul 04 07:12:44 PM PDT 24
Peak memory 225516 kb
Host smart-648eb638-19ce-4f86-a0b5-33e1b5574790
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402988623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_dig
est.402988623
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.3080986087
Short name T696
Test name
Test status
Simulation time 1481857019 ps
CPU time 8.98 seconds
Started Jul 04 07:12:23 PM PDT 24
Finished Jul 04 07:12:44 PM PDT 24
Peak memory 217712 kb
Host smart-a002a24e-817c-44f3-8508-147f365e88f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080986087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.3
080986087
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.903521052
Short name T66
Test name
Test status
Simulation time 211599470 ps
CPU time 5.54 seconds
Started Jul 04 07:12:22 PM PDT 24
Finished Jul 04 07:12:38 PM PDT 24
Peak memory 223508 kb
Host smart-e2ae28e1-3e63-4044-91ad-94b5e8a912c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903521052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.903521052
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.3792563093
Short name T316
Test name
Test status
Simulation time 146869686 ps
CPU time 2.25 seconds
Started Jul 04 07:12:22 PM PDT 24
Finished Jul 04 07:12:34 PM PDT 24
Peak memory 217224 kb
Host smart-12832c51-c633-46eb-ad7f-2cd5b30e34ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792563093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.3792563093
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.119890443
Short name T363
Test name
Test status
Simulation time 2761814269 ps
CPU time 23.04 seconds
Started Jul 04 07:12:16 PM PDT 24
Finished Jul 04 07:12:42 PM PDT 24
Peak memory 250616 kb
Host smart-7f5b4b43-e66f-4ae3-8ecb-35d428f9040c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119890443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.119890443
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.962570165
Short name T110
Test name
Test status
Simulation time 79846510 ps
CPU time 6.72 seconds
Started Jul 04 07:12:22 PM PDT 24
Finished Jul 04 07:12:38 PM PDT 24
Peak memory 249940 kb
Host smart-7c7c4984-c9e1-4aab-a5f6-f62abd1556a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962570165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.962570165
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.1747877399
Short name T282
Test name
Test status
Simulation time 1788219798 ps
CPU time 64.58 seconds
Started Jul 04 07:12:22 PM PDT 24
Finished Jul 04 07:13:37 PM PDT 24
Peak memory 225576 kb
Host smart-a80ad1e8-c5c4-4be0-95fc-975cb7e65a10
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747877399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.1747877399
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.1637360278
Short name T708
Test name
Test status
Simulation time 77740981 ps
CPU time 1.04 seconds
Started Jul 04 07:12:20 PM PDT 24
Finished Jul 04 07:12:27 PM PDT 24
Peak memory 211412 kb
Host smart-ae6e0877-8904-4f85-9d86-5d27ae5c4d6c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637360278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.1637360278
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.638790688
Short name T845
Test name
Test status
Simulation time 53112284 ps
CPU time 1.59 seconds
Started Jul 04 07:14:46 PM PDT 24
Finished Jul 04 07:14:47 PM PDT 24
Peak memory 208576 kb
Host smart-158ad912-b684-4b60-abae-f44be38f9ea4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638790688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.638790688
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.2334758133
Short name T450
Test name
Test status
Simulation time 412057907 ps
CPU time 14.77 seconds
Started Jul 04 07:14:48 PM PDT 24
Finished Jul 04 07:15:05 PM PDT 24
Peak memory 217788 kb
Host smart-acbbf913-24b1-4f81-aafe-fed1afc7f448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334758133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.2334758133
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.3572019358
Short name T373
Test name
Test status
Simulation time 728909941 ps
CPU time 6.85 seconds
Started Jul 04 07:14:52 PM PDT 24
Finished Jul 04 07:15:03 PM PDT 24
Peak memory 216664 kb
Host smart-2cf74734-a302-4b56-b0bf-3b5c78576fcf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572019358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.3572019358
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.750935324
Short name T740
Test name
Test status
Simulation time 85674551 ps
CPU time 2.98 seconds
Started Jul 04 07:14:47 PM PDT 24
Finished Jul 04 07:14:51 PM PDT 24
Peak memory 217784 kb
Host smart-ec61c3ca-9e87-40a1-a303-a88d834f9e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750935324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.750935324
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.4149572961
Short name T172
Test name
Test status
Simulation time 1443129396 ps
CPU time 15.17 seconds
Started Jul 04 07:14:47 PM PDT 24
Finished Jul 04 07:15:03 PM PDT 24
Peak memory 225556 kb
Host smart-8e15811b-9986-4b07-a6cd-a8cf6bc17def
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149572961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.4149572961
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.3548337084
Short name T826
Test name
Test status
Simulation time 907139849 ps
CPU time 7.95 seconds
Started Jul 04 07:14:47 PM PDT 24
Finished Jul 04 07:14:56 PM PDT 24
Peak memory 225516 kb
Host smart-9ba64530-472e-4ecc-a728-eeda87605342
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548337084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.3548337084
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.2256152647
Short name T759
Test name
Test status
Simulation time 301618614 ps
CPU time 7.2 seconds
Started Jul 04 07:14:45 PM PDT 24
Finished Jul 04 07:14:52 PM PDT 24
Peak memory 217732 kb
Host smart-1bc961c2-16a8-4db9-ae9b-4180c9b50dc9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256152647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
2256152647
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.2134257140
Short name T846
Test name
Test status
Simulation time 1221436629 ps
CPU time 7.69 seconds
Started Jul 04 07:14:55 PM PDT 24
Finished Jul 04 07:15:06 PM PDT 24
Peak memory 217828 kb
Host smart-80899b05-60ec-41f1-97ee-19cf7df7f92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134257140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.2134257140
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.406851529
Short name T770
Test name
Test status
Simulation time 85463374 ps
CPU time 1.56 seconds
Started Jul 04 07:14:51 PM PDT 24
Finished Jul 04 07:14:55 PM PDT 24
Peak memory 217216 kb
Host smart-33d3b21d-f758-4b0a-8708-05a873f984dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406851529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.406851529
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.237619787
Short name T632
Test name
Test status
Simulation time 2909505508 ps
CPU time 21.1 seconds
Started Jul 04 07:14:49 PM PDT 24
Finished Jul 04 07:15:12 PM PDT 24
Peak memory 250752 kb
Host smart-fb2410c5-f3fe-4241-9a90-116cf3addf15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237619787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.237619787
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.2998158233
Short name T201
Test name
Test status
Simulation time 303087875 ps
CPU time 2.72 seconds
Started Jul 04 07:14:47 PM PDT 24
Finished Jul 04 07:14:51 PM PDT 24
Peak memory 223476 kb
Host smart-d83c503d-225b-4926-8815-503a101d3124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998158233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.2998158233
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.597238900
Short name T861
Test name
Test status
Simulation time 18172952768 ps
CPU time 105.62 seconds
Started Jul 04 07:14:50 PM PDT 24
Finished Jul 04 07:16:37 PM PDT 24
Peak memory 268908 kb
Host smart-6daed6ed-f22d-4dbd-9066-7d6a8b22c2de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597238900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.597238900
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.709079415
Short name T310
Test name
Test status
Simulation time 79165290 ps
CPU time 0.91 seconds
Started Jul 04 07:14:50 PM PDT 24
Finished Jul 04 07:14:53 PM PDT 24
Peak memory 211392 kb
Host smart-cb3edbba-3d3e-4b12-9903-23520c637cf4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709079415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ct
rl_volatile_unlock_smoke.709079415
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.2940409418
Short name T558
Test name
Test status
Simulation time 92783919 ps
CPU time 1.1 seconds
Started Jul 04 07:14:49 PM PDT 24
Finished Jul 04 07:14:52 PM PDT 24
Peak memory 208548 kb
Host smart-11202688-fd4b-48ae-857a-b623b242ef0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940409418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.2940409418
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.1387132009
Short name T275
Test name
Test status
Simulation time 264313538 ps
CPU time 12.38 seconds
Started Jul 04 07:14:50 PM PDT 24
Finished Jul 04 07:15:05 PM PDT 24
Peak memory 217840 kb
Host smart-37fef399-1d4d-4355-9ab1-d90759bc4f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387132009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.1387132009
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.396598909
Short name T669
Test name
Test status
Simulation time 1860437455 ps
CPU time 6.11 seconds
Started Jul 04 07:14:47 PM PDT 24
Finished Jul 04 07:14:55 PM PDT 24
Peak memory 217200 kb
Host smart-17015c8a-80e3-405c-ade4-5b2fd9a403c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396598909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.396598909
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.2147963572
Short name T115
Test name
Test status
Simulation time 353929112 ps
CPU time 3.15 seconds
Started Jul 04 07:14:48 PM PDT 24
Finished Jul 04 07:14:52 PM PDT 24
Peak memory 217728 kb
Host smart-2cfae033-52b0-4fb4-b231-33428cd74c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147963572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.2147963572
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.900025817
Short name T253
Test name
Test status
Simulation time 2407596294 ps
CPU time 20.54 seconds
Started Jul 04 07:14:48 PM PDT 24
Finished Jul 04 07:15:10 PM PDT 24
Peak memory 225636 kb
Host smart-d0b8d6c1-6717-4343-b157-a809a891b528
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900025817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.900025817
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.2841525900
Short name T685
Test name
Test status
Simulation time 3549241261 ps
CPU time 11.55 seconds
Started Jul 04 07:14:50 PM PDT 24
Finished Jul 04 07:15:03 PM PDT 24
Peak memory 225556 kb
Host smart-a7e4cc0c-3139-4982-a56b-0d4da3731070
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841525900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.2841525900
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.4015499570
Short name T518
Test name
Test status
Simulation time 583708351 ps
CPU time 12.88 seconds
Started Jul 04 07:14:47 PM PDT 24
Finished Jul 04 07:15:01 PM PDT 24
Peak memory 225488 kb
Host smart-eadb0b68-1761-4bbf-845e-f0337e4b6006
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015499570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
4015499570
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.2314369880
Short name T823
Test name
Test status
Simulation time 65506506 ps
CPU time 1.69 seconds
Started Jul 04 07:14:50 PM PDT 24
Finished Jul 04 07:14:54 PM PDT 24
Peak memory 221720 kb
Host smart-cbc3184d-3dea-416f-849f-4ebd9905ce74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314369880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.2314369880
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.1704083759
Short name T630
Test name
Test status
Simulation time 1173370203 ps
CPU time 19.52 seconds
Started Jul 04 07:14:50 PM PDT 24
Finished Jul 04 07:15:11 PM PDT 24
Peak memory 250536 kb
Host smart-e8ff8d8d-caab-463e-9cb9-fdf8261ce7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704083759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.1704083759
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.2445616529
Short name T729
Test name
Test status
Simulation time 271966722 ps
CPU time 3.21 seconds
Started Jul 04 07:14:53 PM PDT 24
Finished Jul 04 07:15:00 PM PDT 24
Peak memory 221992 kb
Host smart-d2b308ba-bab6-47fe-a6a5-7c410758fbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445616529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.2445616529
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.1927699304
Short name T850
Test name
Test status
Simulation time 3946407894 ps
CPU time 31.62 seconds
Started Jul 04 07:14:54 PM PDT 24
Finished Jul 04 07:15:29 PM PDT 24
Peak memory 225624 kb
Host smart-e71afe67-77d9-4e29-9adf-fa10644a2d8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927699304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.1927699304
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.2065054420
Short name T700
Test name
Test status
Simulation time 13015838 ps
CPU time 0.98 seconds
Started Jul 04 07:14:46 PM PDT 24
Finished Jul 04 07:14:47 PM PDT 24
Peak memory 211356 kb
Host smart-0ce880df-1035-4273-a402-acd3d3b6fe82
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065054420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.2065054420
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.3642492125
Short name T303
Test name
Test status
Simulation time 26617990 ps
CPU time 0.98 seconds
Started Jul 04 07:14:53 PM PDT 24
Finished Jul 04 07:14:58 PM PDT 24
Peak memory 208656 kb
Host smart-53a55528-d35e-499b-9291-3ce3ec76876a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642492125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.3642492125
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.2717075325
Short name T51
Test name
Test status
Simulation time 1129457263 ps
CPU time 10.45 seconds
Started Jul 04 07:14:50 PM PDT 24
Finished Jul 04 07:15:02 PM PDT 24
Peak memory 225588 kb
Host smart-debed738-69bf-4ace-869d-3e4092a846f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717075325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.2717075325
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.4079930213
Short name T621
Test name
Test status
Simulation time 977853274 ps
CPU time 11 seconds
Started Jul 04 07:14:49 PM PDT 24
Finished Jul 04 07:15:02 PM PDT 24
Peak memory 216720 kb
Host smart-d11ea52a-09c9-4585-aa85-b7121b8133dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079930213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.4079930213
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.3029173604
Short name T435
Test name
Test status
Simulation time 80137453 ps
CPU time 2.61 seconds
Started Jul 04 07:14:50 PM PDT 24
Finished Jul 04 07:14:55 PM PDT 24
Peak memory 217760 kb
Host smart-d04ce785-44d3-4dd6-beec-2d8b4c084cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029173604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.3029173604
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.3388245793
Short name T254
Test name
Test status
Simulation time 2060880086 ps
CPU time 14.76 seconds
Started Jul 04 07:14:46 PM PDT 24
Finished Jul 04 07:15:01 PM PDT 24
Peak memory 218448 kb
Host smart-eea2d3f8-6c06-4da4-993f-97206541ef4e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388245793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.3388245793
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.1145597376
Short name T67
Test name
Test status
Simulation time 435568202 ps
CPU time 9.32 seconds
Started Jul 04 07:14:46 PM PDT 24
Finished Jul 04 07:14:57 PM PDT 24
Peak memory 225212 kb
Host smart-95a331af-b27f-46ec-9c86-64a2efdae153
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145597376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.1145597376
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.1722385882
Short name T459
Test name
Test status
Simulation time 393504026 ps
CPU time 14.72 seconds
Started Jul 04 07:14:47 PM PDT 24
Finished Jul 04 07:15:03 PM PDT 24
Peak memory 225508 kb
Host smart-93ed63e9-8855-407b-a92d-59cb890ccbd4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722385882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
1722385882
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.702863027
Short name T576
Test name
Test status
Simulation time 408314472 ps
CPU time 9.73 seconds
Started Jul 04 07:14:53 PM PDT 24
Finished Jul 04 07:15:06 PM PDT 24
Peak memory 224932 kb
Host smart-15423611-57a7-456f-9097-2478e2e9fcb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702863027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.702863027
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.3313219666
Short name T85
Test name
Test status
Simulation time 17607966 ps
CPU time 1.47 seconds
Started Jul 04 07:14:54 PM PDT 24
Finished Jul 04 07:14:59 PM PDT 24
Peak memory 213348 kb
Host smart-e99587fe-8ea5-4cd2-9577-40cf23939f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313219666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.3313219666
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.696381764
Short name T391
Test name
Test status
Simulation time 146122258 ps
CPU time 25.02 seconds
Started Jul 04 07:14:51 PM PDT 24
Finished Jul 04 07:15:20 PM PDT 24
Peak memory 250536 kb
Host smart-0924b8df-dd58-4ea5-93dc-53334508460a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696381764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.696381764
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.2568459531
Short name T854
Test name
Test status
Simulation time 73225957 ps
CPU time 7.38 seconds
Started Jul 04 07:14:48 PM PDT 24
Finished Jul 04 07:14:57 PM PDT 24
Peak memory 250536 kb
Host smart-11cdf404-fedf-4c30-9d1c-5315b7d2a16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568459531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.2568459531
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.3668109037
Short name T369
Test name
Test status
Simulation time 19258986494 ps
CPU time 132.02 seconds
Started Jul 04 07:14:48 PM PDT 24
Finished Jul 04 07:17:02 PM PDT 24
Peak memory 270132 kb
Host smart-cfb6d103-63cf-491c-9b24-a65fb95621f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668109037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.3668109037
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.2392166000
Short name T406
Test name
Test status
Simulation time 39895732 ps
CPU time 1.03 seconds
Started Jul 04 07:14:55 PM PDT 24
Finished Jul 04 07:14:59 PM PDT 24
Peak memory 208528 kb
Host smart-f6eefca6-de64-4b6d-97df-ef655f37c64d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392166000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.2392166000
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.1176106833
Short name T829
Test name
Test status
Simulation time 228179968 ps
CPU time 7.96 seconds
Started Jul 04 07:14:50 PM PDT 24
Finished Jul 04 07:15:00 PM PDT 24
Peak memory 217772 kb
Host smart-1a689420-15e1-4b8c-99e4-6320b2bfff1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176106833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.1176106833
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.1943302611
Short name T395
Test name
Test status
Simulation time 559064088 ps
CPU time 13.1 seconds
Started Jul 04 07:14:50 PM PDT 24
Finished Jul 04 07:15:05 PM PDT 24
Peak memory 217184 kb
Host smart-25946fcd-c4fa-4c11-af16-86174f9d61f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943302611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.1943302611
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.3761758954
Short name T777
Test name
Test status
Simulation time 145123069 ps
CPU time 2.84 seconds
Started Jul 04 07:14:47 PM PDT 24
Finished Jul 04 07:14:50 PM PDT 24
Peak memory 217780 kb
Host smart-d7618274-2db9-430c-a066-9e8cef15a474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761758954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.3761758954
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.3201667501
Short name T405
Test name
Test status
Simulation time 3198751221 ps
CPU time 21.97 seconds
Started Jul 04 07:14:49 PM PDT 24
Finished Jul 04 07:15:13 PM PDT 24
Peak memory 225512 kb
Host smart-49351cdd-92c7-42a4-b62d-206d8c4519a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201667501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.3201667501
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.1831801802
Short name T355
Test name
Test status
Simulation time 304488267 ps
CPU time 9.38 seconds
Started Jul 04 07:14:54 PM PDT 24
Finished Jul 04 07:15:07 PM PDT 24
Peak memory 217704 kb
Host smart-2a759766-b332-47a0-90c9-2c4949c9a5aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831801802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
1831801802
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.2715225502
Short name T666
Test name
Test status
Simulation time 820384575 ps
CPU time 10.35 seconds
Started Jul 04 07:14:48 PM PDT 24
Finished Jul 04 07:15:01 PM PDT 24
Peak memory 224976 kb
Host smart-027c58f1-924b-454d-8263-f0b9a52c821a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715225502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.2715225502
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.160296506
Short name T93
Test name
Test status
Simulation time 38549043 ps
CPU time 1.93 seconds
Started Jul 04 07:14:48 PM PDT 24
Finished Jul 04 07:14:51 PM PDT 24
Peak memory 213664 kb
Host smart-eadabf6c-9b20-41fb-8cd6-c9fac4fadf2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160296506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.160296506
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.257825224
Short name T97
Test name
Test status
Simulation time 428217623 ps
CPU time 19.21 seconds
Started Jul 04 07:14:50 PM PDT 24
Finished Jul 04 07:15:12 PM PDT 24
Peak memory 250512 kb
Host smart-0fb982b7-ec8e-411a-a809-5ccb150da6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257825224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.257825224
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.3088875503
Short name T640
Test name
Test status
Simulation time 299421212 ps
CPU time 4.98 seconds
Started Jul 04 07:14:50 PM PDT 24
Finished Jul 04 07:14:57 PM PDT 24
Peak memory 225936 kb
Host smart-5df2b24a-d917-479c-9beb-e09f33af630e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088875503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.3088875503
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.860155659
Short name T458
Test name
Test status
Simulation time 35053536210 ps
CPU time 257.22 seconds
Started Jul 04 07:14:49 PM PDT 24
Finished Jul 04 07:19:08 PM PDT 24
Peak memory 280512 kb
Host smart-1b3a35e8-9a9a-496f-981d-377612bbc9a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860155659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.860155659
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.1040256521
Short name T679
Test name
Test status
Simulation time 20869886252 ps
CPU time 681.49 seconds
Started Jul 04 07:14:50 PM PDT 24
Finished Jul 04 07:26:14 PM PDT 24
Peak memory 267072 kb
Host smart-2f9af728-d9c2-4cd4-a19b-8105998eddd3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1040256521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.1040256521
Directory /workspace/43.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.72908395
Short name T606
Test name
Test status
Simulation time 14999892 ps
CPU time 0.99 seconds
Started Jul 04 07:14:49 PM PDT 24
Finished Jul 04 07:14:53 PM PDT 24
Peak memory 211416 kb
Host smart-e1ddd272-82a5-4439-8334-759133816f3f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72908395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctr
l_volatile_unlock_smoke.72908395
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.73179298
Short name T523
Test name
Test status
Simulation time 181743258 ps
CPU time 1.07 seconds
Started Jul 04 07:14:53 PM PDT 24
Finished Jul 04 07:14:58 PM PDT 24
Peak memory 208604 kb
Host smart-cd697ae1-66ee-4029-a345-759d88dfb5a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73179298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.73179298
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.547778187
Short name T122
Test name
Test status
Simulation time 1326769222 ps
CPU time 8.61 seconds
Started Jul 04 07:14:52 PM PDT 24
Finished Jul 04 07:15:04 PM PDT 24
Peak memory 217800 kb
Host smart-8b2beaf9-9ab9-4898-bd4f-69897f55e36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547778187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.547778187
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.2369941816
Short name T519
Test name
Test status
Simulation time 5433971675 ps
CPU time 16.96 seconds
Started Jul 04 07:14:52 PM PDT 24
Finished Jul 04 07:15:13 PM PDT 24
Peak memory 217228 kb
Host smart-8682da30-9fa3-4d24-ac94-ef3c222f34df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369941816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.2369941816
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.3382577329
Short name T545
Test name
Test status
Simulation time 49554998 ps
CPU time 2.14 seconds
Started Jul 04 07:14:50 PM PDT 24
Finished Jul 04 07:14:55 PM PDT 24
Peak memory 217772 kb
Host smart-2b4a1483-9160-43a2-8400-8438dd32c46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382577329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.3382577329
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.494998439
Short name T397
Test name
Test status
Simulation time 409572616 ps
CPU time 8.53 seconds
Started Jul 04 07:14:52 PM PDT 24
Finished Jul 04 07:15:04 PM PDT 24
Peak memory 225592 kb
Host smart-68d3625a-dddb-4ccc-a282-0c05afa66616
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494998439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.494998439
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.1021925
Short name T651
Test name
Test status
Simulation time 4219867408 ps
CPU time 7.65 seconds
Started Jul 04 07:14:53 PM PDT 24
Finished Jul 04 07:15:05 PM PDT 24
Peak memory 225660 kb
Host smart-c4c93836-e444-4787-a509-ad8ecc95e065
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dige
st_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_dige
st.1021925
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.709219816
Short name T468
Test name
Test status
Simulation time 665866680 ps
CPU time 10.12 seconds
Started Jul 04 07:14:52 PM PDT 24
Finished Jul 04 07:15:06 PM PDT 24
Peak memory 225488 kb
Host smart-6b7e46b9-0a2e-4c04-b346-61e3f898f5bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709219816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.709219816
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.3510849384
Short name T242
Test name
Test status
Simulation time 438892135 ps
CPU time 11.92 seconds
Started Jul 04 07:14:54 PM PDT 24
Finished Jul 04 07:15:09 PM PDT 24
Peak memory 217864 kb
Host smart-e9af9a62-c655-4a95-8634-2a94c2105ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510849384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.3510849384
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.189004942
Short name T659
Test name
Test status
Simulation time 181709886 ps
CPU time 2.67 seconds
Started Jul 04 07:14:52 PM PDT 24
Finished Jul 04 07:14:58 PM PDT 24
Peak memory 214232 kb
Host smart-f3d7b4f8-0d7a-445e-96fa-9128c6a2cfd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189004942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.189004942
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.291727921
Short name T676
Test name
Test status
Simulation time 347576130 ps
CPU time 30.17 seconds
Started Jul 04 07:14:54 PM PDT 24
Finished Jul 04 07:15:28 PM PDT 24
Peak memory 250532 kb
Host smart-9248d1c2-1a93-4d58-a164-1ca15a9500c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291727921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.291727921
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.3661904387
Short name T602
Test name
Test status
Simulation time 286705857 ps
CPU time 7.79 seconds
Started Jul 04 07:14:52 PM PDT 24
Finished Jul 04 07:15:03 PM PDT 24
Peak memory 250372 kb
Host smart-01dff607-1272-460c-91ee-e06bb679d8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661904387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.3661904387
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.114001531
Short name T765
Test name
Test status
Simulation time 2900432735 ps
CPU time 37.95 seconds
Started Jul 04 07:14:55 PM PDT 24
Finished Jul 04 07:15:36 PM PDT 24
Peak memory 245656 kb
Host smart-f4f3d651-67c7-4399-a597-3044a3ab47bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114001531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.114001531
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.3510169212
Short name T787
Test name
Test status
Simulation time 173458019339 ps
CPU time 984.77 seconds
Started Jul 04 07:15:03 PM PDT 24
Finished Jul 04 07:31:28 PM PDT 24
Peak memory 518484 kb
Host smart-a5a37bc2-9b6c-4729-aa5a-ef9dad7c5ab0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3510169212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all_with_rand_reset.3510169212
Directory /workspace/44.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.1345018342
Short name T399
Test name
Test status
Simulation time 27245240 ps
CPU time 0.81 seconds
Started Jul 04 07:14:52 PM PDT 24
Finished Jul 04 07:14:57 PM PDT 24
Peak memory 208252 kb
Host smart-0ad84a5c-bef7-4272-965a-216ac52db510
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345018342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.1345018342
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.2819548378
Short name T430
Test name
Test status
Simulation time 58821738 ps
CPU time 1.1 seconds
Started Jul 04 07:14:55 PM PDT 24
Finished Jul 04 07:14:59 PM PDT 24
Peak memory 208592 kb
Host smart-5a9cddc7-6fa3-4e27-8d7c-3c47e93150ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819548378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.2819548378
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.635300011
Short name T506
Test name
Test status
Simulation time 2901352719 ps
CPU time 11.78 seconds
Started Jul 04 07:14:53 PM PDT 24
Finished Jul 04 07:15:09 PM PDT 24
Peak memory 217860 kb
Host smart-8a0d14e5-87a4-4411-ac7b-940daf9d9e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635300011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.635300011
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.3851088076
Short name T793
Test name
Test status
Simulation time 1154101535 ps
CPU time 11.25 seconds
Started Jul 04 07:14:53 PM PDT 24
Finished Jul 04 07:15:08 PM PDT 24
Peak memory 217292 kb
Host smart-0d405b9e-fb33-4394-9f26-813ca2e3e05f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851088076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.3851088076
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.683042350
Short name T803
Test name
Test status
Simulation time 53344206 ps
CPU time 2.26 seconds
Started Jul 04 07:14:52 PM PDT 24
Finished Jul 04 07:14:57 PM PDT 24
Peak memory 217776 kb
Host smart-e45cb7a3-0160-4255-835c-76690f26c269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683042350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.683042350
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.2978606535
Short name T393
Test name
Test status
Simulation time 1562775013 ps
CPU time 17.59 seconds
Started Jul 04 07:15:04 PM PDT 24
Finished Jul 04 07:15:22 PM PDT 24
Peak memory 219460 kb
Host smart-3ebd167d-c377-4bbd-9486-a26706ac668e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978606535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.2978606535
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.533762325
Short name T335
Test name
Test status
Simulation time 2435678049 ps
CPU time 15.18 seconds
Started Jul 04 07:14:54 PM PDT 24
Finished Jul 04 07:15:12 PM PDT 24
Peak memory 225564 kb
Host smart-bf8de776-955d-4bde-a546-3253ea7c63f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533762325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_di
gest.533762325
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.60768813
Short name T631
Test name
Test status
Simulation time 1350051146 ps
CPU time 12.51 seconds
Started Jul 04 07:14:57 PM PDT 24
Finished Jul 04 07:15:11 PM PDT 24
Peak memory 225440 kb
Host smart-7cb20052-395e-4370-8d2a-b6f0838e6170
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60768813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.60768813
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.1946125426
Short name T650
Test name
Test status
Simulation time 773571595 ps
CPU time 13.89 seconds
Started Jul 04 07:14:51 PM PDT 24
Finished Jul 04 07:15:07 PM PDT 24
Peak memory 225564 kb
Host smart-a49bb113-22ae-45d0-9f57-3a35ad0a1538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946125426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.1946125426
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.503967999
Short name T847
Test name
Test status
Simulation time 247384315 ps
CPU time 3.39 seconds
Started Jul 04 07:14:53 PM PDT 24
Finished Jul 04 07:15:00 PM PDT 24
Peak memory 214232 kb
Host smart-1586d168-f8a4-4451-ad76-59955840618e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503967999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.503967999
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.2583047236
Short name T522
Test name
Test status
Simulation time 537818024 ps
CPU time 31.1 seconds
Started Jul 04 07:14:53 PM PDT 24
Finished Jul 04 07:15:28 PM PDT 24
Peak memory 250516 kb
Host smart-7e231caa-6880-400d-9c63-a7ddd0946781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583047236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.2583047236
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.4104018881
Short name T628
Test name
Test status
Simulation time 187476267 ps
CPU time 3.18 seconds
Started Jul 04 07:14:53 PM PDT 24
Finished Jul 04 07:15:00 PM PDT 24
Peak memory 225932 kb
Host smart-e836ea64-2f12-4a4c-8110-f3609472016f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104018881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.4104018881
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.458262337
Short name T427
Test name
Test status
Simulation time 610965539 ps
CPU time 42.9 seconds
Started Jul 04 07:14:53 PM PDT 24
Finished Jul 04 07:15:39 PM PDT 24
Peak memory 250760 kb
Host smart-99f8b869-64a0-4afa-a831-964733696359
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458262337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.458262337
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.3182141027
Short name T198
Test name
Test status
Simulation time 18882097647 ps
CPU time 340.66 seconds
Started Jul 04 07:14:53 PM PDT 24
Finished Jul 04 07:20:38 PM PDT 24
Peak memory 314884 kb
Host smart-e7debcb8-85c0-4b53-a8eb-a7f72cea4394
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3182141027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all_with_rand_reset.3182141027
Directory /workspace/45.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1850302329
Short name T128
Test name
Test status
Simulation time 25493793 ps
CPU time 0.92 seconds
Started Jul 04 07:14:55 PM PDT 24
Finished Jul 04 07:14:59 PM PDT 24
Peak memory 208460 kb
Host smart-fe454e2f-c5c6-464b-a9ed-f6b59ae710f4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850302329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.1850302329
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.4014734031
Short name T815
Test name
Test status
Simulation time 13186884 ps
CPU time 1.1 seconds
Started Jul 04 07:14:54 PM PDT 24
Finished Jul 04 07:14:59 PM PDT 24
Peak memory 208512 kb
Host smart-072ca3b0-fa1e-44ed-a9e8-5e14607e37de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014734031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.4014734031
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.4286923088
Short name T124
Test name
Test status
Simulation time 625844480 ps
CPU time 18.64 seconds
Started Jul 04 07:14:51 PM PDT 24
Finished Jul 04 07:15:12 PM PDT 24
Peak memory 217728 kb
Host smart-41ff4727-fa43-446d-9db5-fb9906c08936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286923088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.4286923088
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.171688309
Short name T317
Test name
Test status
Simulation time 1238590539 ps
CPU time 8.39 seconds
Started Jul 04 07:14:51 PM PDT 24
Finished Jul 04 07:15:03 PM PDT 24
Peak memory 217212 kb
Host smart-0ff8a604-f724-4829-9459-6776eb1e0d3a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171688309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.171688309
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.1179256998
Short name T432
Test name
Test status
Simulation time 63975076 ps
CPU time 2.85 seconds
Started Jul 04 07:14:53 PM PDT 24
Finished Jul 04 07:15:00 PM PDT 24
Peak memory 217740 kb
Host smart-9328f787-a643-4b6e-9af8-a17f5ef962f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179256998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.1179256998
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.1007633108
Short name T601
Test name
Test status
Simulation time 216384195 ps
CPU time 10.71 seconds
Started Jul 04 07:14:52 PM PDT 24
Finished Jul 04 07:15:06 PM PDT 24
Peak memory 225536 kb
Host smart-347bdc95-d157-4fff-ad09-8cc07a2057d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007633108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.1007633108
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.1575020715
Short name T58
Test name
Test status
Simulation time 363524075 ps
CPU time 12.47 seconds
Started Jul 04 07:14:51 PM PDT 24
Finished Jul 04 07:15:05 PM PDT 24
Peak memory 217696 kb
Host smart-577a90bf-004e-481e-bf99-7f3f872aa3ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575020715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
1575020715
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.1652174797
Short name T626
Test name
Test status
Simulation time 235800604 ps
CPU time 9.47 seconds
Started Jul 04 07:14:54 PM PDT 24
Finished Jul 04 07:15:07 PM PDT 24
Peak memory 217832 kb
Host smart-418563a0-7226-4e91-a8ba-e6000b760bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652174797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.1652174797
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.4062843522
Short name T286
Test name
Test status
Simulation time 16996892 ps
CPU time 1.44 seconds
Started Jul 04 07:14:51 PM PDT 24
Finished Jul 04 07:14:56 PM PDT 24
Peak memory 222236 kb
Host smart-eda3f90f-ef01-43b3-a497-8b7bfae9ba8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062843522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.4062843522
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.944077020
Short name T547
Test name
Test status
Simulation time 483012733 ps
CPU time 28.44 seconds
Started Jul 04 07:14:52 PM PDT 24
Finished Jul 04 07:15:25 PM PDT 24
Peak memory 250572 kb
Host smart-e9a7ff97-5866-4873-9ff0-78a853893f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944077020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.944077020
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.1536819875
Short name T769
Test name
Test status
Simulation time 88475220 ps
CPU time 3.76 seconds
Started Jul 04 07:14:52 PM PDT 24
Finished Jul 04 07:15:00 PM PDT 24
Peak memory 221956 kb
Host smart-1be07a7b-15b7-45fe-ad69-bcc0604a8f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536819875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.1536819875
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.342277432
Short name T833
Test name
Test status
Simulation time 3093674240 ps
CPU time 74.66 seconds
Started Jul 04 07:14:59 PM PDT 24
Finished Jul 04 07:16:15 PM PDT 24
Peak memory 279616 kb
Host smart-bb379582-f9a9-4139-ac4b-45e488fa09da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342277432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.342277432
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.4179561239
Short name T744
Test name
Test status
Simulation time 22366689 ps
CPU time 0.92 seconds
Started Jul 04 07:14:54 PM PDT 24
Finished Jul 04 07:14:59 PM PDT 24
Peak memory 211376 kb
Host smart-5ef3fe76-6e3c-47ce-a0a8-50309e78eff0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179561239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.4179561239
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.2437822676
Short name T191
Test name
Test status
Simulation time 71430720 ps
CPU time 0.88 seconds
Started Jul 04 07:14:57 PM PDT 24
Finished Jul 04 07:14:59 PM PDT 24
Peak memory 208512 kb
Host smart-9e290fd9-9743-4b28-bdea-a9dd38e57b00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437822676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.2437822676
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.993685414
Short name T726
Test name
Test status
Simulation time 2211400766 ps
CPU time 9.54 seconds
Started Jul 04 07:14:51 PM PDT 24
Finished Jul 04 07:15:04 PM PDT 24
Peak memory 218088 kb
Host smart-eda26d58-de30-4771-aad8-38153e2b71a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993685414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.993685414
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.558091482
Short name T810
Test name
Test status
Simulation time 1979502537 ps
CPU time 13.57 seconds
Started Jul 04 07:15:03 PM PDT 24
Finished Jul 04 07:15:18 PM PDT 24
Peak memory 217128 kb
Host smart-42166c42-f1a9-4143-b1bd-df77aa5c9e7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558091482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.558091482
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.2259988915
Short name T474
Test name
Test status
Simulation time 342739239 ps
CPU time 3.6 seconds
Started Jul 04 07:15:03 PM PDT 24
Finished Jul 04 07:15:07 PM PDT 24
Peak memory 217772 kb
Host smart-1e85fb13-ce5d-42bf-bd1b-6ba0f5078712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259988915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.2259988915
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.3810719932
Short name T870
Test name
Test status
Simulation time 2141392146 ps
CPU time 14.8 seconds
Started Jul 04 07:14:57 PM PDT 24
Finished Jul 04 07:15:13 PM PDT 24
Peak memory 218432 kb
Host smart-c1b2d9eb-7a5b-4ab5-b8b1-d7a52ede931c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810719932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.3810719932
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.2858773104
Short name T527
Test name
Test status
Simulation time 9248487874 ps
CPU time 18.37 seconds
Started Jul 04 07:14:57 PM PDT 24
Finished Jul 04 07:15:17 PM PDT 24
Peak memory 225584 kb
Host smart-f8ae7166-e056-47f9-8d58-8dff528ac539
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858773104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.2858773104
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.2539785913
Short name T524
Test name
Test status
Simulation time 188717279 ps
CPU time 8.58 seconds
Started Jul 04 07:14:54 PM PDT 24
Finished Jul 04 07:15:06 PM PDT 24
Peak memory 217756 kb
Host smart-c7e9517b-994b-43c7-a9bf-2bc6521a984e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539785913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
2539785913
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.3148068431
Short name T633
Test name
Test status
Simulation time 479789404 ps
CPU time 9.45 seconds
Started Jul 04 07:14:55 PM PDT 24
Finished Jul 04 07:15:08 PM PDT 24
Peak memory 225800 kb
Host smart-be22603c-6f3b-48d1-9870-c661dc9e9414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148068431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.3148068431
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.1015146514
Short name T457
Test name
Test status
Simulation time 40077400 ps
CPU time 1.78 seconds
Started Jul 04 07:14:53 PM PDT 24
Finished Jul 04 07:14:59 PM PDT 24
Peak memory 213512 kb
Host smart-4f2bf44c-fd38-4094-a226-3c2e4e858109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015146514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.1015146514
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.4284032272
Short name T820
Test name
Test status
Simulation time 1135708397 ps
CPU time 25.21 seconds
Started Jul 04 07:14:52 PM PDT 24
Finished Jul 04 07:15:21 PM PDT 24
Peak memory 250596 kb
Host smart-3deea257-a2fc-4f33-84f8-10db0d8adf7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284032272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.4284032272
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.3606539565
Short name T309
Test name
Test status
Simulation time 78636736 ps
CPU time 7.52 seconds
Started Jul 04 07:14:53 PM PDT 24
Finished Jul 04 07:15:04 PM PDT 24
Peak memory 250544 kb
Host smart-17c9d608-2180-4074-97d1-31619b16c888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606539565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.3606539565
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.2134473419
Short name T616
Test name
Test status
Simulation time 45841990492 ps
CPU time 367.87 seconds
Started Jul 04 07:15:04 PM PDT 24
Finished Jul 04 07:21:12 PM PDT 24
Peak memory 250592 kb
Host smart-055e69ac-a229-46ae-88a0-62a0aa99dbe6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134473419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.2134473419
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.3093209760
Short name T181
Test name
Test status
Simulation time 10176041092 ps
CPU time 363.19 seconds
Started Jul 04 07:14:57 PM PDT 24
Finished Jul 04 07:21:02 PM PDT 24
Peak memory 282092 kb
Host smart-68de3668-ec0b-4d87-a08f-1db814a53068
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3093209760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all_with_rand_reset.3093209760
Directory /workspace/47.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.2213654421
Short name T345
Test name
Test status
Simulation time 40696915 ps
CPU time 0.89 seconds
Started Jul 04 07:14:54 PM PDT 24
Finished Jul 04 07:14:59 PM PDT 24
Peak memory 211428 kb
Host smart-5802091f-6fae-4f04-abae-66972ed799f8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213654421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.2213654421
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.3318502421
Short name T824
Test name
Test status
Simulation time 27501726 ps
CPU time 1.03 seconds
Started Jul 04 07:14:58 PM PDT 24
Finished Jul 04 07:15:00 PM PDT 24
Peak memory 208516 kb
Host smart-6eb22198-c47b-410b-99e0-96c9bc3189be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318502421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.3318502421
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.2331917365
Short name T44
Test name
Test status
Simulation time 3506230654 ps
CPU time 8.58 seconds
Started Jul 04 07:15:04 PM PDT 24
Finished Jul 04 07:15:13 PM PDT 24
Peak memory 225640 kb
Host smart-fd5f29e9-b948-4975-85b0-9e259803ce19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331917365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.2331917365
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.483598645
Short name T420
Test name
Test status
Simulation time 1465912118 ps
CPU time 14.35 seconds
Started Jul 04 07:15:03 PM PDT 24
Finished Jul 04 07:15:18 PM PDT 24
Peak memory 216852 kb
Host smart-0bca62cd-abf7-4d1c-a7f0-5cc048e24fba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483598645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.483598645
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.2396303
Short name T453
Test name
Test status
Simulation time 48020731 ps
CPU time 2.48 seconds
Started Jul 04 07:14:57 PM PDT 24
Finished Jul 04 07:15:01 PM PDT 24
Peak memory 217796 kb
Host smart-8d4bbc95-cb4d-4185-ba09-fd84b91188a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.2396303
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.3830804403
Short name T478
Test name
Test status
Simulation time 1684233850 ps
CPU time 17.49 seconds
Started Jul 04 07:14:56 PM PDT 24
Finished Jul 04 07:15:16 PM PDT 24
Peak memory 218648 kb
Host smart-dde07dc5-cc1b-422a-98d6-be028a4a2676
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830804403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.3830804403
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.2459580555
Short name T301
Test name
Test status
Simulation time 229454314 ps
CPU time 11.54 seconds
Started Jul 04 07:14:57 PM PDT 24
Finished Jul 04 07:15:10 PM PDT 24
Peak memory 225528 kb
Host smart-08a6acc6-b424-4214-96ef-2b640b40e143
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459580555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.2459580555
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.2711714957
Short name T553
Test name
Test status
Simulation time 7669348280 ps
CPU time 19.15 seconds
Started Jul 04 07:14:53 PM PDT 24
Finished Jul 04 07:15:16 PM PDT 24
Peak memory 225576 kb
Host smart-b6e7bd74-a719-4854-83ca-27a6eea7c446
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711714957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
2711714957
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.381360054
Short name T762
Test name
Test status
Simulation time 945679310 ps
CPU time 7.65 seconds
Started Jul 04 07:14:54 PM PDT 24
Finished Jul 04 07:15:05 PM PDT 24
Peak memory 224764 kb
Host smart-d3ea7353-3a7f-4a63-8fe9-7d18b6918269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381360054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.381360054
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.328492539
Short name T91
Test name
Test status
Simulation time 57884684 ps
CPU time 3.65 seconds
Started Jul 04 07:14:53 PM PDT 24
Finished Jul 04 07:15:00 PM PDT 24
Peak memory 214488 kb
Host smart-0b1d9498-3cb0-44f3-8776-f4435ae83c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328492539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.328492539
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.2632804485
Short name T252
Test name
Test status
Simulation time 202285963 ps
CPU time 20.7 seconds
Started Jul 04 07:14:55 PM PDT 24
Finished Jul 04 07:15:19 PM PDT 24
Peak memory 250584 kb
Host smart-7a32154f-52aa-41e4-a3af-8fee25ebd2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632804485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.2632804485
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.805072573
Short name T693
Test name
Test status
Simulation time 305883414 ps
CPU time 9.41 seconds
Started Jul 04 07:15:03 PM PDT 24
Finished Jul 04 07:15:13 PM PDT 24
Peak memory 250432 kb
Host smart-ce37c37f-ea8a-425a-a739-ced85dd34e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805072573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.805072573
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.3626689750
Short name T817
Test name
Test status
Simulation time 28580105443 ps
CPU time 419.67 seconds
Started Jul 04 07:14:55 PM PDT 24
Finished Jul 04 07:21:58 PM PDT 24
Peak memory 295084 kb
Host smart-59dfbeda-aaa2-4ac3-b8de-91f87a5fef3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626689750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.3626689750
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.1758122630
Short name T366
Test name
Test status
Simulation time 81772719 ps
CPU time 0.95 seconds
Started Jul 04 07:14:54 PM PDT 24
Finished Jul 04 07:14:58 PM PDT 24
Peak memory 217276 kb
Host smart-13346cae-2973-41a5-8f3d-436839b955b9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758122630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.1758122630
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.1616234907
Short name T501
Test name
Test status
Simulation time 90004290 ps
CPU time 1.13 seconds
Started Jul 04 07:15:00 PM PDT 24
Finished Jul 04 07:15:02 PM PDT 24
Peak memory 208528 kb
Host smart-f67ecd10-a81d-4c93-964b-22a08f6fce53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616234907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.1616234907
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.2001087566
Short name T683
Test name
Test status
Simulation time 432814485 ps
CPU time 16.7 seconds
Started Jul 04 07:14:59 PM PDT 24
Finished Jul 04 07:15:17 PM PDT 24
Peak memory 225608 kb
Host smart-5baf1987-0cbd-4b49-a15d-461370360f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001087566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.2001087566
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.2176027509
Short name T604
Test name
Test status
Simulation time 322253269 ps
CPU time 9.3 seconds
Started Jul 04 07:14:59 PM PDT 24
Finished Jul 04 07:15:09 PM PDT 24
Peak memory 217140 kb
Host smart-a616c836-d3e0-4809-a5d4-55d684e494c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176027509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.2176027509
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.3635358575
Short name T565
Test name
Test status
Simulation time 29228045 ps
CPU time 1.67 seconds
Started Jul 04 07:14:59 PM PDT 24
Finished Jul 04 07:15:01 PM PDT 24
Peak memory 217776 kb
Host smart-1adc59ec-ec39-494e-ab93-411f13628565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635358575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.3635358575
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.1446138532
Short name T192
Test name
Test status
Simulation time 308876936 ps
CPU time 13.59 seconds
Started Jul 04 07:14:59 PM PDT 24
Finished Jul 04 07:15:14 PM PDT 24
Peak memory 218380 kb
Host smart-ae120efa-bfde-4152-aa72-e5a8e523b90e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446138532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.1446138532
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.2872062430
Short name T325
Test name
Test status
Simulation time 227574971 ps
CPU time 9.61 seconds
Started Jul 04 07:15:00 PM PDT 24
Finished Jul 04 07:15:10 PM PDT 24
Peak memory 225540 kb
Host smart-d932daf3-5026-4dc3-8422-dff0be3055ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872062430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.2872062430
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.2909197011
Short name T594
Test name
Test status
Simulation time 278427868 ps
CPU time 10.99 seconds
Started Jul 04 07:14:59 PM PDT 24
Finished Jul 04 07:15:11 PM PDT 24
Peak memory 217724 kb
Host smart-5de35f08-7e1f-4308-9017-d82fa68e469e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909197011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
2909197011
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.3517089442
Short name T502
Test name
Test status
Simulation time 266908578 ps
CPU time 7.03 seconds
Started Jul 04 07:15:02 PM PDT 24
Finished Jul 04 07:15:09 PM PDT 24
Peak memory 224240 kb
Host smart-d365bb60-0679-465c-8f36-4b3e2a85f95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517089442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.3517089442
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.2077915205
Short name T374
Test name
Test status
Simulation time 38889987 ps
CPU time 2.93 seconds
Started Jul 04 07:15:04 PM PDT 24
Finished Jul 04 07:15:07 PM PDT 24
Peak memory 214512 kb
Host smart-2ba2eb96-3cc5-483a-9919-0762ee6b281e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077915205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.2077915205
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.3126716887
Short name T725
Test name
Test status
Simulation time 1560101304 ps
CPU time 23.61 seconds
Started Jul 04 07:15:03 PM PDT 24
Finished Jul 04 07:15:28 PM PDT 24
Peak memory 250532 kb
Host smart-246b4452-b3d7-41ab-a1ce-30b924549123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126716887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.3126716887
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.492947699
Short name T368
Test name
Test status
Simulation time 49555826 ps
CPU time 7.52 seconds
Started Jul 04 07:14:59 PM PDT 24
Finished Jul 04 07:15:07 PM PDT 24
Peak memory 250500 kb
Host smart-51b7a811-8fed-4542-bbeb-aa7571893877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492947699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.492947699
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.4002352069
Short name T865
Test name
Test status
Simulation time 4606982115 ps
CPU time 53.89 seconds
Started Jul 04 07:14:59 PM PDT 24
Finished Jul 04 07:15:54 PM PDT 24
Peak memory 250724 kb
Host smart-8b181e6c-d2c4-463a-a84f-dec420d36893
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002352069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.4002352069
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.3176310528
Short name T42
Test name
Test status
Simulation time 37749919 ps
CPU time 0.91 seconds
Started Jul 04 07:14:59 PM PDT 24
Finished Jul 04 07:15:01 PM PDT 24
Peak memory 208612 kb
Host smart-362c90da-9c67-4d99-9030-1089ad411570
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176310528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.3176310528
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.2318552688
Short name T300
Test name
Test status
Simulation time 173371645 ps
CPU time 1.09 seconds
Started Jul 04 07:12:40 PM PDT 24
Finished Jul 04 07:13:08 PM PDT 24
Peak memory 208520 kb
Host smart-4d806404-7fd2-4348-bae6-790ee68629ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318552688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.2318552688
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.1874700423
Short name T516
Test name
Test status
Simulation time 185955849 ps
CPU time 9.55 seconds
Started Jul 04 07:12:23 PM PDT 24
Finished Jul 04 07:12:43 PM PDT 24
Peak memory 217812 kb
Host smart-3304c85e-386a-452e-b648-ba1263abff22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874700423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.1874700423
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.710368645
Short name T806
Test name
Test status
Simulation time 263564611 ps
CPU time 7.17 seconds
Started Jul 04 07:12:24 PM PDT 24
Finished Jul 04 07:12:44 PM PDT 24
Peak memory 217208 kb
Host smart-05fa224f-a081-4d32-8971-1c9d457c506c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710368645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.710368645
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.1553935509
Short name T536
Test name
Test status
Simulation time 1232615878 ps
CPU time 19.19 seconds
Started Jul 04 07:12:23 PM PDT 24
Finished Jul 04 07:12:53 PM PDT 24
Peak memory 217812 kb
Host smart-069681f7-81e4-47a2-8515-f77560119905
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553935509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.1553935509
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.4001746521
Short name T119
Test name
Test status
Simulation time 644263507 ps
CPU time 7.38 seconds
Started Jul 04 07:12:26 PM PDT 24
Finished Jul 04 07:12:46 PM PDT 24
Peak memory 217208 kb
Host smart-9b7c17a3-2ceb-40c8-86f4-6315efd1ca4d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001746521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.4
001746521
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.2409016283
Short name T409
Test name
Test status
Simulation time 557430005 ps
CPU time 8.39 seconds
Started Jul 04 07:12:22 PM PDT 24
Finished Jul 04 07:12:41 PM PDT 24
Peak memory 217736 kb
Host smart-1c966c93-6841-4113-9909-0f105f5752d5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409016283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.2409016283
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.290443310
Short name T643
Test name
Test status
Simulation time 2652683152 ps
CPU time 10.68 seconds
Started Jul 04 07:12:22 PM PDT 24
Finished Jul 04 07:12:43 PM PDT 24
Peak memory 217208 kb
Host smart-ba9c9933-dd71-4295-a29e-baa7f78923d5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290443310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_regwen_during_op.290443310
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.2262628591
Short name T24
Test name
Test status
Simulation time 1322848098 ps
CPU time 8.8 seconds
Started Jul 04 07:12:23 PM PDT 24
Finished Jul 04 07:12:42 PM PDT 24
Peak memory 217120 kb
Host smart-21190030-840a-4c40-b940-0587d1b80c6f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262628591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
2262628591
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.3743903136
Short name T187
Test name
Test status
Simulation time 6195494985 ps
CPU time 112.51 seconds
Started Jul 04 07:12:23 PM PDT 24
Finished Jul 04 07:14:27 PM PDT 24
Peak memory 283248 kb
Host smart-5f2c5c8b-c9cb-4cb6-a71b-32c1b064a37c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743903136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.3743903136
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.413670294
Short name T386
Test name
Test status
Simulation time 2541739541 ps
CPU time 22.32 seconds
Started Jul 04 07:12:22 PM PDT 24
Finished Jul 04 07:12:55 PM PDT 24
Peak memory 250560 kb
Host smart-2e1c619e-46ac-48b3-bcf3-43831615ff00
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413670294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_state_post_trans.413670294
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.1769667228
Short name T851
Test name
Test status
Simulation time 123829151 ps
CPU time 1.59 seconds
Started Jul 04 07:12:25 PM PDT 24
Finished Jul 04 07:12:39 PM PDT 24
Peak memory 217776 kb
Host smart-8036f1c1-af73-416d-9e70-f50eb4fb4cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769667228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.1769667228
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.1830560628
Short name T433
Test name
Test status
Simulation time 373150655 ps
CPU time 24.6 seconds
Started Jul 04 07:12:23 PM PDT 24
Finished Jul 04 07:12:59 PM PDT 24
Peak memory 217140 kb
Host smart-8fc409c3-0749-4a0a-923f-524f6c69f334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830560628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.1830560628
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.1805771700
Short name T790
Test name
Test status
Simulation time 428407670 ps
CPU time 12.2 seconds
Started Jul 04 07:12:22 PM PDT 24
Finished Jul 04 07:12:44 PM PDT 24
Peak memory 217932 kb
Host smart-b165a0a2-7a24-4ee2-bc9a-b7f8cf6a6af2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805771700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.1805771700
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.360200146
Short name T46
Test name
Test status
Simulation time 597294629 ps
CPU time 12.91 seconds
Started Jul 04 07:12:31 PM PDT 24
Finished Jul 04 07:13:02 PM PDT 24
Peak memory 225468 kb
Host smart-b7cfad34-bb00-4c87-8519-e0c978c833c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360200146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_dig
est.360200146
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.450462588
Short name T340
Test name
Test status
Simulation time 994139848 ps
CPU time 7.22 seconds
Started Jul 04 07:12:33 PM PDT 24
Finished Jul 04 07:13:01 PM PDT 24
Peak memory 217688 kb
Host smart-d6076732-9b90-444a-9ab1-0d190e3926ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450462588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.450462588
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.1480867294
Short name T758
Test name
Test status
Simulation time 1818857726 ps
CPU time 8.61 seconds
Started Jul 04 07:12:22 PM PDT 24
Finished Jul 04 07:12:41 PM PDT 24
Peak memory 224720 kb
Host smart-ad6fe0ca-e4a3-47fe-97a2-85c3347f1410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480867294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.1480867294
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.1312753902
Short name T388
Test name
Test status
Simulation time 21991932 ps
CPU time 2.03 seconds
Started Jul 04 07:12:26 PM PDT 24
Finished Jul 04 07:12:43 PM PDT 24
Peak memory 213488 kb
Host smart-ec1e0a5e-cce6-4299-8852-6e3bedffc6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312753902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.1312753902
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.1510695155
Short name T484
Test name
Test status
Simulation time 369362967 ps
CPU time 34.26 seconds
Started Jul 04 07:12:24 PM PDT 24
Finished Jul 04 07:13:11 PM PDT 24
Peak memory 250540 kb
Host smart-a4b32bad-1887-4040-a7c0-653516e43cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510695155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.1510695155
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.4201901403
Short name T867
Test name
Test status
Simulation time 490968261 ps
CPU time 3.37 seconds
Started Jul 04 07:12:23 PM PDT 24
Finished Jul 04 07:12:38 PM PDT 24
Peak memory 222324 kb
Host smart-6ecc34e9-ec03-405b-8862-df9c830d37e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201901403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.4201901403
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.4047239880
Short name T212
Test name
Test status
Simulation time 4862538092 ps
CPU time 55.13 seconds
Started Jul 04 07:12:31 PM PDT 24
Finished Jul 04 07:13:45 PM PDT 24
Peak memory 273728 kb
Host smart-beb1054f-4811-4c7e-85f2-0decce1f04e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047239880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.4047239880
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.465472286
Short name T49
Test name
Test status
Simulation time 18576213 ps
CPU time 1.37 seconds
Started Jul 04 07:12:24 PM PDT 24
Finished Jul 04 07:12:38 PM PDT 24
Peak memory 217220 kb
Host smart-58d1b8c9-5d3c-4f3a-803b-97b677be3ea0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465472286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctr
l_volatile_unlock_smoke.465472286
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.2478098346
Short name T825
Test name
Test status
Simulation time 38852616 ps
CPU time 0.92 seconds
Started Jul 04 07:12:31 PM PDT 24
Finished Jul 04 07:12:50 PM PDT 24
Peak memory 208532 kb
Host smart-0d07473b-45d0-4dec-947a-22df1fa9d1c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478098346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.2478098346
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.759332209
Short name T688
Test name
Test status
Simulation time 18497946 ps
CPU time 0.93 seconds
Started Jul 04 07:12:28 PM PDT 24
Finished Jul 04 07:12:45 PM PDT 24
Peak memory 208720 kb
Host smart-401f6375-66f1-4727-9be5-15284d8d0d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759332209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.759332209
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.1469379583
Short name T582
Test name
Test status
Simulation time 1096152166 ps
CPU time 12.36 seconds
Started Jul 04 07:12:27 PM PDT 24
Finished Jul 04 07:12:55 PM PDT 24
Peak memory 217764 kb
Host smart-8d1cb262-a5c7-4d4e-943d-fa7dfbf632a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469379583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.1469379583
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.227662390
Short name T800
Test name
Test status
Simulation time 66647475 ps
CPU time 1.47 seconds
Started Jul 04 07:12:28 PM PDT 24
Finished Jul 04 07:12:46 PM PDT 24
Peak memory 216672 kb
Host smart-97b0aba2-2ed1-4484-a607-d86de790f415
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227662390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.227662390
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.2976191770
Short name T251
Test name
Test status
Simulation time 6687442955 ps
CPU time 52.34 seconds
Started Jul 04 07:12:32 PM PDT 24
Finished Jul 04 07:13:44 PM PDT 24
Peak memory 218452 kb
Host smart-06773680-586a-4bdf-98bf-598814a3bd2c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976191770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.2976191770
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.685896525
Short name T571
Test name
Test status
Simulation time 501939525 ps
CPU time 2.28 seconds
Started Jul 04 07:12:29 PM PDT 24
Finished Jul 04 07:12:50 PM PDT 24
Peak memory 217308 kb
Host smart-be92248c-3879-4873-9273-6a3177b303ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685896525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.685896525
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.1349242995
Short name T339
Test name
Test status
Simulation time 1386910516 ps
CPU time 15.23 seconds
Started Jul 04 07:12:34 PM PDT 24
Finished Jul 04 07:13:13 PM PDT 24
Peak memory 218608 kb
Host smart-1f3b265f-0a94-45a3-9ce2-7d50ddadcd78
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349242995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.1349242995
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.1435253705
Short name T707
Test name
Test status
Simulation time 946251605 ps
CPU time 6.53 seconds
Started Jul 04 07:12:31 PM PDT 24
Finished Jul 04 07:12:56 PM PDT 24
Peak memory 217140 kb
Host smart-cf680f15-3e00-4cec-8f74-db4c6bdf4a22
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435253705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
1435253705
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.3707432222
Short name T761
Test name
Test status
Simulation time 4647584646 ps
CPU time 43.7 seconds
Started Jul 04 07:12:29 PM PDT 24
Finished Jul 04 07:13:30 PM PDT 24
Peak memory 251660 kb
Host smart-68696041-9969-49d4-8a16-c9ef96d06e99
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707432222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.3707432222
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.2655171468
Short name T258
Test name
Test status
Simulation time 1450302399 ps
CPU time 14.88 seconds
Started Jul 04 07:12:33 PM PDT 24
Finished Jul 04 07:13:06 PM PDT 24
Peak memory 250204 kb
Host smart-0a45dd06-ab0c-4481-bb66-646522ca2c4b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655171468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.2655171468
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.3198316799
Short name T585
Test name
Test status
Simulation time 183459959 ps
CPU time 2.46 seconds
Started Jul 04 07:12:32 PM PDT 24
Finished Jul 04 07:12:54 PM PDT 24
Peak memory 217768 kb
Host smart-b762c1ba-2fcd-4184-9496-3fee2e4245cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198316799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.3198316799
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.3229625667
Short name T74
Test name
Test status
Simulation time 357144625 ps
CPU time 8.58 seconds
Started Jul 04 07:12:28 PM PDT 24
Finished Jul 04 07:12:51 PM PDT 24
Peak memory 217240 kb
Host smart-d75a5304-c66a-4151-b56e-2972a4284010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229625667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.3229625667
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.234494009
Short name T436
Test name
Test status
Simulation time 1042079718 ps
CPU time 12.59 seconds
Started Jul 04 07:12:29 PM PDT 24
Finished Jul 04 07:12:59 PM PDT 24
Peak memory 225300 kb
Host smart-d9d386b3-8600-476e-8c1d-9ae8acd0d63d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234494009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_dig
est.234494009
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.183069531
Short name T419
Test name
Test status
Simulation time 2286847888 ps
CPU time 18.08 seconds
Started Jul 04 07:12:28 PM PDT 24
Finished Jul 04 07:13:03 PM PDT 24
Peak memory 225580 kb
Host smart-8c6a8559-f0d1-4332-ba60-5621fdf1285d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183069531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.183069531
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.1178548178
Short name T202
Test name
Test status
Simulation time 436571376 ps
CPU time 14.97 seconds
Started Jul 04 07:12:28 PM PDT 24
Finished Jul 04 07:12:58 PM PDT 24
Peak memory 225572 kb
Host smart-c7519936-0d6d-427a-9144-8e6227c07e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178548178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.1178548178
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.1215391992
Short name T378
Test name
Test status
Simulation time 67851338 ps
CPU time 2.52 seconds
Started Jul 04 07:12:29 PM PDT 24
Finished Jul 04 07:12:49 PM PDT 24
Peak memory 223424 kb
Host smart-c21d0038-a312-4a80-87bf-7abf1c82d7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215391992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.1215391992
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.2176512307
Short name T788
Test name
Test status
Simulation time 205370369 ps
CPU time 29.01 seconds
Started Jul 04 07:12:31 PM PDT 24
Finished Jul 04 07:13:19 PM PDT 24
Peak memory 250388 kb
Host smart-5a04eff5-c040-4bf1-8b52-fac62ff3b7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176512307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.2176512307
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.2181245011
Short name T716
Test name
Test status
Simulation time 197141773 ps
CPU time 5.82 seconds
Started Jul 04 07:12:29 PM PDT 24
Finished Jul 04 07:12:50 PM PDT 24
Peak memory 246596 kb
Host smart-bbb0db76-4415-4055-9c17-10d3a81029cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181245011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.2181245011
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.2135691163
Short name T490
Test name
Test status
Simulation time 24679254691 ps
CPU time 686.14 seconds
Started Jul 04 07:12:30 PM PDT 24
Finished Jul 04 07:24:14 PM PDT 24
Peak memory 302036 kb
Host smart-e7585bb9-aed2-4368-9ddc-78c95f3a85e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135691163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.2135691163
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.1942030445
Short name T94
Test name
Test status
Simulation time 8502320609 ps
CPU time 174.82 seconds
Started Jul 04 07:12:33 PM PDT 24
Finished Jul 04 07:15:49 PM PDT 24
Peak memory 267456 kb
Host smart-82d341eb-bed9-40ae-b3c1-df932a999fa0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1942030445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.1942030445
Directory /workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.4165902410
Short name T75
Test name
Test status
Simulation time 37059927 ps
CPU time 0.86 seconds
Started Jul 04 07:12:29 PM PDT 24
Finished Jul 04 07:12:47 PM PDT 24
Peak memory 217220 kb
Host smart-1b83c9c8-704a-422e-b769-fbc5c61d4591
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165902410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.4165902410
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.1145227141
Short name T704
Test name
Test status
Simulation time 33727213 ps
CPU time 0.87 seconds
Started Jul 04 07:12:42 PM PDT 24
Finished Jul 04 07:13:10 PM PDT 24
Peak memory 208552 kb
Host smart-0f7129c2-1f50-40e3-ba18-ad47365eb2b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145227141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.1145227141
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.2689480726
Short name T279
Test name
Test status
Simulation time 1585016658 ps
CPU time 16.41 seconds
Started Jul 04 07:12:28 PM PDT 24
Finished Jul 04 07:13:01 PM PDT 24
Peak memory 217800 kb
Host smart-887014c1-ce2d-438b-ba01-ab1a286e50d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689480726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.2689480726
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.1251037343
Short name T123
Test name
Test status
Simulation time 89976158 ps
CPU time 1.9 seconds
Started Jul 04 07:12:27 PM PDT 24
Finished Jul 04 07:12:44 PM PDT 24
Peak memory 217232 kb
Host smart-5c2c0cf2-612d-42b1-9abe-38f2276091ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251037343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.1251037343
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.2400068659
Short name T381
Test name
Test status
Simulation time 2701992721 ps
CPU time 32.55 seconds
Started Jul 04 07:12:28 PM PDT 24
Finished Jul 04 07:13:15 PM PDT 24
Peak memory 218412 kb
Host smart-6bc1337a-9b88-467c-87f7-590cb72b3a3f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400068659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.2400068659
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.149174600
Short name T190
Test name
Test status
Simulation time 715245342 ps
CPU time 4 seconds
Started Jul 04 07:12:34 PM PDT 24
Finished Jul 04 07:13:01 PM PDT 24
Peak memory 217248 kb
Host smart-9008501b-f7d8-47ce-b662-cfcdc030d607
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149174600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.149174600
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.2845090254
Short name T389
Test name
Test status
Simulation time 257052688 ps
CPU time 7.78 seconds
Started Jul 04 07:12:30 PM PDT 24
Finished Jul 04 07:12:56 PM PDT 24
Peak memory 217632 kb
Host smart-f1fae8ad-5645-4301-b4c0-60753e17e684
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845090254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.2845090254
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.3829124137
Short name T329
Test name
Test status
Simulation time 2039160004 ps
CPU time 14.09 seconds
Started Jul 04 07:12:30 PM PDT 24
Finished Jul 04 07:13:02 PM PDT 24
Peak memory 217152 kb
Host smart-cd8d0e40-6e75-49ca-9ab0-2c0960f29e82
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829124137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.3829124137
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.2954964526
Short name T485
Test name
Test status
Simulation time 1614660711 ps
CPU time 6.08 seconds
Started Jul 04 07:12:30 PM PDT 24
Finished Jul 04 07:12:54 PM PDT 24
Peak memory 217172 kb
Host smart-fb699e0f-f8e3-468c-a05d-f17c71731f88
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954964526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
2954964526
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.1053015872
Short name T208
Test name
Test status
Simulation time 2570661331 ps
CPU time 97.45 seconds
Started Jul 04 07:12:31 PM PDT 24
Finished Jul 04 07:14:27 PM PDT 24
Peak memory 267060 kb
Host smart-2ef7e71f-3a7b-4d46-afdf-f3bdee9a771f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053015872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.1053015872
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.1956679140
Short name T840
Test name
Test status
Simulation time 938805366 ps
CPU time 8.9 seconds
Started Jul 04 07:12:30 PM PDT 24
Finished Jul 04 07:12:57 PM PDT 24
Peak memory 225880 kb
Host smart-d761f11c-f8b0-46a2-9d60-192d7c253849
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956679140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.1956679140
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.1012687531
Short name T39
Test name
Test status
Simulation time 96687410 ps
CPU time 4.2 seconds
Started Jul 04 07:12:36 PM PDT 24
Finished Jul 04 07:13:05 PM PDT 24
Peak memory 217780 kb
Host smart-e1cc7631-1a8e-42e0-9604-f4bd8c786808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012687531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.1012687531
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.2179417478
Short name T234
Test name
Test status
Simulation time 3584311428 ps
CPU time 14.26 seconds
Started Jul 04 07:12:33 PM PDT 24
Finished Jul 04 07:13:06 PM PDT 24
Peak memory 217096 kb
Host smart-713968af-6ab9-44ba-b188-97904c588d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179417478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.2179417478
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.2657752670
Short name T210
Test name
Test status
Simulation time 434622159 ps
CPU time 8.11 seconds
Started Jul 04 07:12:36 PM PDT 24
Finished Jul 04 07:13:09 PM PDT 24
Peak memory 225588 kb
Host smart-453083a7-0c97-4d9f-83df-c371154b2ccb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657752670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.2657752670
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.3227548244
Short name T313
Test name
Test status
Simulation time 1839372892 ps
CPU time 10.87 seconds
Started Jul 04 07:12:31 PM PDT 24
Finished Jul 04 07:13:01 PM PDT 24
Peak memory 225520 kb
Host smart-b6dea7f8-b415-4606-87a9-bf351039e4f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227548244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.3227548244
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.4069636994
Short name T443
Test name
Test status
Simulation time 992382834 ps
CPU time 9.48 seconds
Started Jul 04 07:12:36 PM PDT 24
Finished Jul 04 07:13:10 PM PDT 24
Peak memory 217736 kb
Host smart-f081c19f-4347-444c-80ff-50b07e77914e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069636994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.4
069636994
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.4075451558
Short name T382
Test name
Test status
Simulation time 2286870885 ps
CPU time 14.51 seconds
Started Jul 04 07:12:32 PM PDT 24
Finished Jul 04 07:13:06 PM PDT 24
Peak memory 225660 kb
Host smart-1742e943-723c-4b1b-b373-b9cf287f2399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075451558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.4075451558
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.3421420960
Short name T798
Test name
Test status
Simulation time 185188091 ps
CPU time 2.48 seconds
Started Jul 04 07:12:31 PM PDT 24
Finished Jul 04 07:12:52 PM PDT 24
Peak memory 217208 kb
Host smart-be652a0b-ac6f-4119-adb2-ec6760e1fbd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421420960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.3421420960
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.1432940320
Short name T348
Test name
Test status
Simulation time 621928498 ps
CPU time 20.36 seconds
Started Jul 04 07:12:34 PM PDT 24
Finished Jul 04 07:13:18 PM PDT 24
Peak memory 250516 kb
Host smart-2a17cbc4-df05-4062-aa64-d09add88074d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432940320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.1432940320
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.1574205007
Short name T598
Test name
Test status
Simulation time 60614694 ps
CPU time 7.82 seconds
Started Jul 04 07:12:30 PM PDT 24
Finished Jul 04 07:12:56 PM PDT 24
Peak memory 250544 kb
Host smart-e1783516-14eb-4a8f-8bb7-460e7acb1392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574205007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.1574205007
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.683995313
Short name T21
Test name
Test status
Simulation time 5777519792 ps
CPU time 31.33 seconds
Started Jul 04 07:12:36 PM PDT 24
Finished Jul 04 07:13:32 PM PDT 24
Peak memory 250608 kb
Host smart-65ae0748-ff81-470d-88e6-a753b5377eb9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683995313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.683995313
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.130666873
Short name T772
Test name
Test status
Simulation time 14522216 ps
CPU time 1.13 seconds
Started Jul 04 07:12:33 PM PDT 24
Finished Jul 04 07:12:55 PM PDT 24
Peak memory 211508 kb
Host smart-4ce01e97-9f30-4642-9364-3e36376e089d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130666873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctr
l_volatile_unlock_smoke.130666873
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.3352709787
Short name T425
Test name
Test status
Simulation time 92497712 ps
CPU time 0.95 seconds
Started Jul 04 07:12:40 PM PDT 24
Finished Jul 04 07:13:08 PM PDT 24
Peak memory 208428 kb
Host smart-743cc880-c632-4230-bf6a-012bbc0067f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352709787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.3352709787
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.4055011074
Short name T796
Test name
Test status
Simulation time 97866070 ps
CPU time 0.84 seconds
Started Jul 04 07:12:36 PM PDT 24
Finished Jul 04 07:13:02 PM PDT 24
Peak memory 208524 kb
Host smart-0d1ad68a-71a4-4c5c-af56-ac5073a7ed0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055011074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.4055011074
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.369451311
Short name T280
Test name
Test status
Simulation time 2262847674 ps
CPU time 16.75 seconds
Started Jul 04 07:12:35 PM PDT 24
Finished Jul 04 07:13:18 PM PDT 24
Peak memory 217844 kb
Host smart-095eade7-a1e9-4dc3-9744-b29a572c1907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369451311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.369451311
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.2792299154
Short name T556
Test name
Test status
Simulation time 2923439008 ps
CPU time 4.97 seconds
Started Jul 04 07:12:35 PM PDT 24
Finished Jul 04 07:13:06 PM PDT 24
Peak memory 217020 kb
Host smart-4c69d277-3112-4fe0-91b9-a93a2fb3dc2f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792299154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.2792299154
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.2714065860
Short name T514
Test name
Test status
Simulation time 7563617236 ps
CPU time 31.94 seconds
Started Jul 04 07:12:36 PM PDT 24
Finished Jul 04 07:13:33 PM PDT 24
Peak memory 218452 kb
Host smart-6f86b321-e8ec-463a-86a3-0ceca056c360
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714065860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.2714065860
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.4224562863
Short name T687
Test name
Test status
Simulation time 337692458 ps
CPU time 2.91 seconds
Started Jul 04 07:12:41 PM PDT 24
Finished Jul 04 07:13:12 PM PDT 24
Peak memory 217288 kb
Host smart-3fa89c11-806f-4bf4-9784-a6cc0349f100
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224562863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.4
224562863
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.3204415602
Short name T563
Test name
Test status
Simulation time 823600019 ps
CPU time 11.96 seconds
Started Jul 04 07:12:38 PM PDT 24
Finished Jul 04 07:13:17 PM PDT 24
Peak memory 217696 kb
Host smart-a0691084-9350-4626-8e43-38e3aa2573bf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204415602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.3204415602
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.1879662867
Short name T205
Test name
Test status
Simulation time 2517628735 ps
CPU time 34.79 seconds
Started Jul 04 07:12:36 PM PDT 24
Finished Jul 04 07:13:36 PM PDT 24
Peak memory 217236 kb
Host smart-9d2f36d2-0a30-4a63-a1a0-4387baedf870
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879662867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.1879662867
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.1894142083
Short name T569
Test name
Test status
Simulation time 1435522376 ps
CPU time 6.65 seconds
Started Jul 04 07:12:37 PM PDT 24
Finished Jul 04 07:13:09 PM PDT 24
Peak memory 217140 kb
Host smart-87bcc1c2-91e8-4975-a987-94829796b80f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894142083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
1894142083
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.2679167672
Short name T359
Test name
Test status
Simulation time 3006612989 ps
CPU time 65.35 seconds
Started Jul 04 07:12:36 PM PDT 24
Finished Jul 04 07:14:07 PM PDT 24
Peak memory 267432 kb
Host smart-1c2f2312-49eb-470c-bb48-2f0c715dcdb3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679167672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.2679167672
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.4025529787
Short name T184
Test name
Test status
Simulation time 15049894765 ps
CPU time 17.39 seconds
Started Jul 04 07:12:39 PM PDT 24
Finished Jul 04 07:13:24 PM PDT 24
Peak memory 250144 kb
Host smart-e15b4435-0303-4dcd-a42b-f74b667c9265
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025529787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.4025529787
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.2978082568
Short name T320
Test name
Test status
Simulation time 234621775 ps
CPU time 4.55 seconds
Started Jul 04 07:12:36 PM PDT 24
Finished Jul 04 07:13:07 PM PDT 24
Peak memory 217780 kb
Host smart-89b2f634-bb97-423f-a616-c01cae59d6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978082568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.2978082568
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.1546614937
Short name T649
Test name
Test status
Simulation time 1570437186 ps
CPU time 11.54 seconds
Started Jul 04 07:12:38 PM PDT 24
Finished Jul 04 07:13:16 PM PDT 24
Peak memory 217220 kb
Host smart-4590400a-0025-421d-932f-5794bdd57e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546614937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.1546614937
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.2917363760
Short name T452
Test name
Test status
Simulation time 352614407 ps
CPU time 9.75 seconds
Started Jul 04 07:12:36 PM PDT 24
Finished Jul 04 07:13:11 PM PDT 24
Peak memory 225492 kb
Host smart-e7b55b49-5a89-4b6f-b0cb-6556a5ede840
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917363760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.2917363760
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.707788332
Short name T757
Test name
Test status
Simulation time 374719446 ps
CPU time 12.67 seconds
Started Jul 04 07:12:35 PM PDT 24
Finished Jul 04 07:13:14 PM PDT 24
Peak memory 225508 kb
Host smart-e4890164-087c-4140-a456-35288dd102d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707788332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.707788332
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.3256463574
Short name T40
Test name
Test status
Simulation time 350330157 ps
CPU time 13.4 seconds
Started Jul 04 07:12:40 PM PDT 24
Finished Jul 04 07:13:21 PM PDT 24
Peak memory 217904 kb
Host smart-43011965-462b-45e2-a96e-e1e3134d04cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256463574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.3256463574
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.2854878459
Short name T423
Test name
Test status
Simulation time 123710238 ps
CPU time 1.45 seconds
Started Jul 04 07:12:38 PM PDT 24
Finished Jul 04 07:13:06 PM PDT 24
Peak memory 217212 kb
Host smart-ea3ba6b9-db8c-4ffc-a350-67dd365e929d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854878459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.2854878459
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.4237603506
Short name T330
Test name
Test status
Simulation time 591231799 ps
CPU time 30.17 seconds
Started Jul 04 07:12:36 PM PDT 24
Finished Jul 04 07:13:31 PM PDT 24
Peak memory 250384 kb
Host smart-84a0de52-acf6-46fc-9994-24a0d19bd069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237603506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.4237603506
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.2353994170
Short name T288
Test name
Test status
Simulation time 91874447 ps
CPU time 6.57 seconds
Started Jul 04 07:12:37 PM PDT 24
Finished Jul 04 07:13:09 PM PDT 24
Peak memory 250072 kb
Host smart-149a5a31-fc8c-44ff-84e7-08b95cc9d405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353994170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.2353994170
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.439019607
Short name T96
Test name
Test status
Simulation time 15403424 ps
CPU time 1.15 seconds
Started Jul 04 07:12:40 PM PDT 24
Finished Jul 04 07:13:08 PM PDT 24
Peak memory 211292 kb
Host smart-4e71e135-b379-4d9b-a8f3-91e6a5b30ee9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439019607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctr
l_volatile_unlock_smoke.439019607
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.382241807
Short name T271
Test name
Test status
Simulation time 76158104 ps
CPU time 1.11 seconds
Started Jul 04 07:12:35 PM PDT 24
Finished Jul 04 07:13:02 PM PDT 24
Peak memory 208516 kb
Host smart-4c1c9974-f92b-4288-8708-952f046734b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382241807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.382241807
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.2092061838
Short name T238
Test name
Test status
Simulation time 10508814 ps
CPU time 0.81 seconds
Started Jul 04 07:12:40 PM PDT 24
Finished Jul 04 07:13:08 PM PDT 24
Peak memory 208544 kb
Host smart-cbe18861-1e89-4c84-be86-946c754f7780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092061838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.2092061838
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.408704122
Short name T780
Test name
Test status
Simulation time 1596247787 ps
CPU time 13.96 seconds
Started Jul 04 07:12:41 PM PDT 24
Finished Jul 04 07:13:23 PM PDT 24
Peak memory 217808 kb
Host smart-395118d3-a349-44a1-a140-3f3731311efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408704122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.408704122
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.582484776
Short name T837
Test name
Test status
Simulation time 212482002 ps
CPU time 3.24 seconds
Started Jul 04 07:12:36 PM PDT 24
Finished Jul 04 07:13:04 PM PDT 24
Peak memory 216748 kb
Host smart-e25742ab-349e-4c60-89dc-4fd0c7f36aaa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582484776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.582484776
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.2438191332
Short name T410
Test name
Test status
Simulation time 1268472191 ps
CPU time 40.58 seconds
Started Jul 04 07:12:36 PM PDT 24
Finished Jul 04 07:13:42 PM PDT 24
Peak memory 217708 kb
Host smart-1c2bf1e2-d2c1-417e-a32e-641e379ab763
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438191332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.2438191332
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.3116713415
Short name T578
Test name
Test status
Simulation time 105740014 ps
CPU time 1.87 seconds
Started Jul 04 07:12:36 PM PDT 24
Finished Jul 04 07:13:03 PM PDT 24
Peak memory 217272 kb
Host smart-ca4abfb6-261a-4830-84cc-bf447795e057
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116713415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.3
116713415
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.2040469450
Short name T675
Test name
Test status
Simulation time 651492635 ps
CPU time 5.76 seconds
Started Jul 04 07:12:35 PM PDT 24
Finished Jul 04 07:13:07 PM PDT 24
Peak memory 217724 kb
Host smart-287ec575-8d6e-414a-9664-b4cecf6d3a39
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040469450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.2040469450
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.1349519439
Short name T361
Test name
Test status
Simulation time 888077654 ps
CPU time 24.15 seconds
Started Jul 04 07:12:36 PM PDT 24
Finished Jul 04 07:13:25 PM PDT 24
Peak memory 217140 kb
Host smart-10808f40-e260-45ab-8c0a-656fa280cfdf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349519439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.1349519439
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.2735245803
Short name T589
Test name
Test status
Simulation time 1002329443 ps
CPU time 4.29 seconds
Started Jul 04 07:12:40 PM PDT 24
Finished Jul 04 07:13:12 PM PDT 24
Peak memory 217188 kb
Host smart-93f75432-6572-4cf1-a96e-20998b518390
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735245803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
2735245803
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.1585493800
Short name T868
Test name
Test status
Simulation time 11863190855 ps
CPU time 88.25 seconds
Started Jul 04 07:12:37 PM PDT 24
Finished Jul 04 07:14:31 PM PDT 24
Peak memory 283288 kb
Host smart-f98283cb-fa6e-4d3b-b651-0741d194c881
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585493800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.1585493800
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.2627143799
Short name T805
Test name
Test status
Simulation time 6721849368 ps
CPU time 15.25 seconds
Started Jul 04 07:12:41 PM PDT 24
Finished Jul 04 07:13:25 PM PDT 24
Peak memory 223272 kb
Host smart-695d8901-e47f-42a9-ab02-62c627889712
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627143799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.2627143799
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.1096787847
Short name T262
Test name
Test status
Simulation time 362312491 ps
CPU time 2.99 seconds
Started Jul 04 07:12:38 PM PDT 24
Finished Jul 04 07:13:07 PM PDT 24
Peak memory 221640 kb
Host smart-e6325183-4ba7-440e-93b1-7361328247dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096787847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.1096787847
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.1926015529
Short name T511
Test name
Test status
Simulation time 243587755 ps
CPU time 7.13 seconds
Started Jul 04 07:12:35 PM PDT 24
Finished Jul 04 07:13:08 PM PDT 24
Peak memory 214040 kb
Host smart-17dbd753-3d17-49f7-9f30-b40ce3f8e420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926015529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.1926015529
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.68802389
Short name T353
Test name
Test status
Simulation time 868127704 ps
CPU time 6.51 seconds
Started Jul 04 07:12:37 PM PDT 24
Finished Jul 04 07:13:11 PM PDT 24
Peak memory 217716 kb
Host smart-586f62fc-21d6-48ea-a1f2-22d965fb1439
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68802389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.68802389
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.1668882154
Short name T821
Test name
Test status
Simulation time 149523192 ps
CPU time 2.54 seconds
Started Jul 04 07:12:36 PM PDT 24
Finished Jul 04 07:13:03 PM PDT 24
Peak memory 217208 kb
Host smart-5fae63a7-c39a-4806-a71e-8e045fcf618b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668882154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.1668882154
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.327866175
Short name T412
Test name
Test status
Simulation time 700880940 ps
CPU time 20.33 seconds
Started Jul 04 07:12:38 PM PDT 24
Finished Jul 04 07:13:25 PM PDT 24
Peak memory 250560 kb
Host smart-4d11ed79-536f-46de-9a67-e8a74b8d6043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327866175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.327866175
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.72713327
Short name T671
Test name
Test status
Simulation time 169814737 ps
CPU time 6.95 seconds
Started Jul 04 07:12:34 PM PDT 24
Finished Jul 04 07:13:05 PM PDT 24
Peak memory 250108 kb
Host smart-9459d0d4-c79e-4821-abde-1ff9634a41ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72713327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.72713327
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.1406815755
Short name T295
Test name
Test status
Simulation time 4292816500 ps
CPU time 169.43 seconds
Started Jul 04 07:12:36 PM PDT 24
Finished Jul 04 07:15:50 PM PDT 24
Peak memory 250576 kb
Host smart-4768bbaf-da2c-406d-a8c2-47f993c182b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406815755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.1406815755
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.33610978
Short name T680
Test name
Test status
Simulation time 19077903233 ps
CPU time 194.14 seconds
Started Jul 04 07:12:37 PM PDT 24
Finished Jul 04 07:16:17 PM PDT 24
Peak memory 273268 kb
Host smart-31ff6849-04d8-441c-9ff6-40fc0c620dc1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=33610978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all_with_rand_reset.33610978
Directory /workspace/9.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.1029242310
Short name T324
Test name
Test status
Simulation time 36764056 ps
CPU time 0.92 seconds
Started Jul 04 07:12:39 PM PDT 24
Finished Jul 04 07:13:08 PM PDT 24
Peak memory 211428 kb
Host smart-f0e851c5-5f30-4f20-9881-925a01498268
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029242310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.1029242310
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%