Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

85008741

1

T1

1643

T2

953

T3

17933

auto[1]

1279379

1

T3

396

T4

1188

T14

99

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

85007822

1

T1

1643

T2

953

T3

17735

auto[1]

1280298

1

T3

594

T4

1683

T14

396

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	6498958	1			T1	70		T2	73		T3	5098
auto[IdleSt]	20086425	1			T1	1573		T2	193		T3	1625
auto[ClkMuxSt]	32792	1			T3	54		T4	54		T5	18
auto[CntIncrSt]	32451	1			T3	54		T4	54		T5	18
auto[CntProgSt]	1984214	1			T3	84		T4	228		T5	36
auto[TransCheckSt]	25372	1			T3	38		T4	43		T5	18
auto[TokenHashSt]	29645855	1			T3	2575		T4	2203		T5	1124
auto[FlashRmaSt]	31638	1			T3	41		T4	96		T5	62
auto[TokenCheck0St]	11460	1			T3	14		T4	34		T5	18
auto[TokenCheck1St]	8503	1			T3	11		T4	24		T5	18
auto[TransProgSt]	504390	1			T3	21		T4	117		T5	36
auto[PostTransSt]	11590899	1			T2	687		T3	7366		T4	8104
auto[ScrapSt]	137371	1			T5	32		T7	1718		T20	24
auto[EscalateSt]	5949022	1			T3	1348		T4	3964		T14	695
auto[InvalidSt]	9747102	1			T4	2593		T15	798		T16	9647

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1668	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	9747102	1			T4	2593		T15	798		T16	9647
EscalateSt	5949022	1			T3	1348		T4	3964		T14	695
ScrapSt	137371	1			T5	32		T7	1718		T20	24
PostTransSt	11590899	1			T2	687		T3	7366		T4	8104
TransProgSt	504390	1			T3	21		T4	117		T5	36
TokenCheck1St	8503	1			T3	11		T4	24		T5	18
TokenCheck0St	11460	1			T3	14		T4	34		T5	18
FlashRmaSt	31638	1			T3	41		T4	96		T5	62
TokenHashSt	29645855	1			T3	2575		T4	2203		T5	1124
TransCheckSt	25372	1			T3	38		T4	43		T5	18
CntProgSt	1984214	1			T3	84		T4	228		T5	36
CntIncrSt	32451	1			T3	54		T4	54		T5	18
ClkMuxSt	32792	1			T3	54		T4	54		T5	18
IdleSt	20086425	1			T1	1573		T2	193		T3	1625
ResetSt	6498958	1			T1	70		T2	73		T3	5098
arcs[ResetSt=>IdleSt]	49114	1			T1	1		T2	1		T3	55
arcs[IdleSt=>ScrapSt]	270	1			T5	1		T7	2		T20	1
arcs[IdleSt=>ClkMuxSt]	32521	1			T3	54		T4	54		T5	18
arcs[ClkMuxSt=>CntIncrSt]	32451	1			T3	54		T4	54		T5	18
arcs[CntIncrSt=>PostTransSt]	1606	1			T3	8		T14	3		T6	13
arcs[CntIncrSt=>CntProgSt]	30789	1			T3	46		T4	54		T5	18
arcs[CntProgSt=>PostTransSt]	4298	1			T3	8		T4	11		T14	5
arcs[CntProgSt=>TransCheckSt]	25372	1			T3	38		T4	43		T5	18
arcs[TransCheckSt=>PostTransSt]	3620	1			T3	6		T14	7		T6	15
arcs[TransCheckSt=>TokenHashSt]	21658	1			T3	32		T4	43		T5	18
arcs[TokenHashSt=>PostTransSt]	9428	1			T3	17		T4	9		T12	86
arcs[TokenHashSt=>FlashRmaSt]	11556	1			T3	14		T4	34		T5	18
arcs[FlashRmaSt=>TokenCheck0St]	11460	1			T3	14		T4	34		T5	18
arcs[TokenCheck0St=>PostTransSt]	2930	1			T3	3		T4	10		T14	4
arcs[TokenCheck0St=>TokenCheck1St]	8503	1			T3	11		T4	24		T5	18
arcs[TokenCheck1St=>PostTransSt]	606	1			T6	2		T25	5		T26	11
arcs[TransProgSt=>PostTransSt]	6976	1			T3	11		T4	24		T5	18
arcs[IdleSt=>EscalateSt]	199	1			T63	6		T65	7		T64	4
arcs[ClkMuxSt=>EscalateSt]	70	1			T60	1		T61	2		T62	1
arcs[CntIncrSt=>EscalateSt]	56	1			T61	1		T63	1		T64	2
arcs[CntProgSt=>EscalateSt]	1119	1			T60	6		T61	37		T62	30
arcs[TransCheckSt=>EscalateSt]	94	1			T60	3		T65	3		T64	4
arcs[TokenHashSt=>EscalateSt]	674	1			T3	1		T60	30		T69	1
arcs[FlashRmaSt=>EscalateSt]	96	1			T61	4		T62	1		T63	2
arcs[TokenCheck0St=>EscalateSt]	27	1			T60	1		T63	1		T64	1
arcs[TokenCheck1St=>EscalateSt]	152	1			T60	3		T61	4		T62	2
arcs[TransProgSt=>EscalateSt]	769	1			T60	4		T61	14		T62	12
arcs[PostTransSt=>EscalateSt]	4525	1			T3	9		T4	11		T14	5
arcs[InvalidSt=>EscalateSt]	12244	1			T4	18		T15	10		T16	70

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6498783	1			T1	70		T2	73		T3	5098
auto[0]	auto[IdleSt]	20086300	1			T1	1573		T2	193		T3	1625
auto[0]	auto[ClkMuxSt]	32750	1			T3	54		T4	54		T5	18
auto[0]	auto[CntIncrSt]	32409	1			T3	54		T4	54		T5	18
auto[0]	auto[CntProgSt]	1983486	1			T3	84		T4	228		T5	36
auto[0]	auto[TransCheckSt]	25306	1			T3	38		T4	43		T5	18
auto[0]	auto[TokenHashSt]	29645404	1			T3	2575		T4	2203		T5	1124
auto[0]	auto[FlashRmaSt]	31574	1			T3	41		T4	96		T5	62
auto[0]	auto[TokenCheck0St]	11439	1			T3	14		T4	34		T5	18
auto[0]	auto[TokenCheck1St]	8403	1			T3	11		T4	24		T5	18
auto[0]	auto[TransProgSt]	503873	1			T3	21		T4	117		T5	36
auto[0]	auto[PostTransSt]	11588610	1			T2	687		T3	7362		T4	8099
auto[0]	auto[ScrapSt]	137325	1			T5	32		T7	1718		T20	24
auto[0]	auto[EscalateSt]	4680411	1			T3	956		T4	2788		T14	597
auto[0]	auto[InvalidSt]	9741000	1			T4	2586		T15	793		T16	9608
auto[1]	auto[ResetSt]	175	1			T60	4		T61	3		T62	2
auto[1]	auto[IdleSt]	125	1			T63	3		T65	4		T64	3
auto[1]	auto[ClkMuxSt]	42	1			T60	1		T61	1		T62	1
auto[1]	auto[CntIncrSt]	42	1			T61	1		T63	1		T64	2
auto[1]	auto[CntProgSt]	728	1			T60	5		T61	22		T62	20
auto[1]	auto[TransCheckSt]	66	1			T60	1		T65	2		T64	4
auto[1]	auto[TokenHashSt]	451	1			T60	18		T69	1		T61	8
auto[1]	auto[FlashRmaSt]	64	1			T61	2		T63	2		T65	4
auto[1]	auto[TokenCheck0St]	21	1			T60	1		T63	1		T64	1
auto[1]	auto[TokenCheck1St]	100	1			T60	3		T61	2		T62	2
auto[1]	auto[TransProgSt]	517	1			T60	2		T61	9		T62	9
auto[1]	auto[PostTransSt]	2289	1			T3	4		T4	5		T14	1
auto[1]	auto[ScrapSt]	46	1			T60	2		T63	2		T232	1
auto[1]	auto[EscalateSt]	1268611	1			T3	392		T4	1176		T14	98
auto[1]	auto[InvalidSt]	6102	1			T4	7		T15	5		T16	39

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6498790	1			T1	70		T2	73		T3	5098
auto[0]	auto[IdleSt]	20086289	1			T1	1573		T2	193		T3	1625
auto[0]	auto[ClkMuxSt]	32745	1			T3	54		T4	54		T5	18
auto[0]	auto[CntIncrSt]	32414	1			T3	54		T4	54		T5	18
auto[0]	auto[CntProgSt]	1983478	1			T3	84		T4	228		T5	36
auto[0]	auto[TransCheckSt]	25312	1			T3	38		T4	43		T5	18
auto[0]	auto[TokenHashSt]	29645427	1			T3	2574		T4	2203		T5	1124
auto[0]	auto[FlashRmaSt]	31578	1			T3	41		T4	96		T5	62
auto[0]	auto[TokenCheck0St]	11443	1			T3	14		T4	34		T5	18
auto[0]	auto[TokenCheck1St]	8399	1			T3	11		T4	24		T5	18
auto[0]	auto[TransProgSt]	503875	1			T3	21		T4	117		T5	36
auto[0]	auto[PostTransSt]	11588601	1			T2	687		T3	7361		T4	8098
auto[0]	auto[ScrapSt]	137329	1			T5	32		T7	1718		T20	24
auto[0]	auto[EscalateSt]	4679514	1			T3	760		T4	2298		T14	303
auto[0]	auto[InvalidSt]	9740960	1			T4	2582		T15	793		T16	9616
auto[1]	auto[ResetSt]	168	1			T60	7		T61	2		T62	2
auto[1]	auto[IdleSt]	136	1			T63	3		T65	3		T64	3
auto[1]	auto[ClkMuxSt]	47	1			T60	1		T61	2		T62	1
auto[1]	auto[CntIncrSt]	37	1			T233	1		T234	5		T235	1
auto[1]	auto[CntProgSt]	736	1			T60	4		T61	26		T62	19
auto[1]	auto[TransCheckSt]	60	1			T60	2		T65	2		T64	1
auto[1]	auto[TokenHashSt]	428	1			T3	1		T60	21		T61	7
auto[1]	auto[FlashRmaSt]	60	1			T61	3		T62	1		T63	2
auto[1]	auto[TokenCheck0St]	17	1			T60	1		T63	1		T236	1
auto[1]	auto[TokenCheck1St]	104	1			T60	1		T61	4		T62	2
auto[1]	auto[TransProgSt]	515	1			T60	3		T61	8		T62	7
auto[1]	auto[PostTransSt]	2298	1			T3	5		T4	6		T14	4
auto[1]	auto[ScrapSt]	42	1			T60	1		T63	3		T65	1
auto[1]	auto[EscalateSt]	1269508	1			T3	588		T4	1666		T14	392
auto[1]	auto[InvalidSt]	6142	1			T4	11		T15	5		T16	31