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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.17 97.99 95.41 93.38 100.00 98.55 98.76 96.11


Total test records in report: 985
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T817 /workspace/coverage/default/45.lc_ctrl_stress_all.2823211873 Jul 05 05:35:30 PM PDT 24 Jul 05 05:36:34 PM PDT 24 1799378887 ps
T818 /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1741715560 Jul 05 05:34:55 PM PDT 24 Jul 05 05:34:58 PM PDT 24 57303954 ps
T819 /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.3055844545 Jul 05 05:33:44 PM PDT 24 Jul 05 05:33:46 PM PDT 24 14564904 ps
T820 /workspace/coverage/default/19.lc_ctrl_sec_token_mux.1375506646 Jul 05 05:34:20 PM PDT 24 Jul 05 05:34:30 PM PDT 24 2012446856 ps
T821 /workspace/coverage/default/36.lc_ctrl_security_escalation.3973366806 Jul 05 05:35:03 PM PDT 24 Jul 05 05:35:21 PM PDT 24 3958774808 ps
T822 /workspace/coverage/default/42.lc_ctrl_sec_token_mux.3246440508 Jul 05 05:35:17 PM PDT 24 Jul 05 05:35:28 PM PDT 24 815491778 ps
T823 /workspace/coverage/default/41.lc_ctrl_errors.3987005575 Jul 05 05:35:11 PM PDT 24 Jul 05 05:35:20 PM PDT 24 767523103 ps
T824 /workspace/coverage/default/29.lc_ctrl_sec_token_mux.893690558 Jul 05 05:34:44 PM PDT 24 Jul 05 05:34:54 PM PDT 24 4974864853 ps
T825 /workspace/coverage/default/18.lc_ctrl_jtag_errors.3875999563 Jul 05 05:34:13 PM PDT 24 Jul 05 05:34:45 PM PDT 24 10066256388 ps
T826 /workspace/coverage/default/27.lc_ctrl_state_post_trans.1686834220 Jul 05 05:34:36 PM PDT 24 Jul 05 05:34:47 PM PDT 24 272814484 ps
T827 /workspace/coverage/default/38.lc_ctrl_jtag_access.2699006988 Jul 05 05:35:08 PM PDT 24 Jul 05 05:35:14 PM PDT 24 2856716002 ps
T828 /workspace/coverage/default/15.lc_ctrl_jtag_smoke.775726770 Jul 05 05:34:04 PM PDT 24 Jul 05 05:34:11 PM PDT 24 2213108850 ps
T829 /workspace/coverage/default/23.lc_ctrl_jtag_access.1762311274 Jul 05 05:34:30 PM PDT 24 Jul 05 05:34:34 PM PDT 24 324510932 ps
T830 /workspace/coverage/default/35.lc_ctrl_stress_all.105676833 Jul 05 05:35:03 PM PDT 24 Jul 05 05:37:43 PM PDT 24 32050963136 ps
T831 /workspace/coverage/default/37.lc_ctrl_stress_all.2927541217 Jul 05 05:35:00 PM PDT 24 Jul 05 05:44:01 PM PDT 24 144450646881 ps
T832 /workspace/coverage/default/29.lc_ctrl_stress_all.3284382599 Jul 05 05:34:43 PM PDT 24 Jul 05 05:41:24 PM PDT 24 13041644350 ps
T833 /workspace/coverage/default/17.lc_ctrl_state_failure.3172349612 Jul 05 05:34:08 PM PDT 24 Jul 05 05:34:39 PM PDT 24 961383731 ps
T834 /workspace/coverage/default/26.lc_ctrl_security_escalation.1490910271 Jul 05 05:34:36 PM PDT 24 Jul 05 05:34:45 PM PDT 24 262055275 ps
T835 /workspace/coverage/default/33.lc_ctrl_sec_token_mux.3056835507 Jul 05 05:34:55 PM PDT 24 Jul 05 05:35:06 PM PDT 24 1380135918 ps
T836 /workspace/coverage/default/5.lc_ctrl_prog_failure.274846844 Jul 05 05:33:14 PM PDT 24 Jul 05 05:33:18 PM PDT 24 418939384 ps
T837 /workspace/coverage/default/45.lc_ctrl_prog_failure.286736451 Jul 05 05:35:26 PM PDT 24 Jul 05 05:35:29 PM PDT 24 54207161 ps
T838 /workspace/coverage/default/16.lc_ctrl_alert_test.3692740689 Jul 05 05:34:19 PM PDT 24 Jul 05 05:34:21 PM PDT 24 65586701 ps
T839 /workspace/coverage/default/7.lc_ctrl_security_escalation.2938130822 Jul 05 05:33:23 PM PDT 24 Jul 05 05:33:34 PM PDT 24 662345806 ps
T840 /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.2263575551 Jul 05 05:33:29 PM PDT 24 Jul 05 05:34:26 PM PDT 24 36095825655 ps
T841 /workspace/coverage/default/37.lc_ctrl_errors.4158551239 Jul 05 05:35:03 PM PDT 24 Jul 05 05:35:20 PM PDT 24 1121456689 ps
T842 /workspace/coverage/default/3.lc_ctrl_regwen_during_op.1477392339 Jul 05 05:33:13 PM PDT 24 Jul 05 05:33:22 PM PDT 24 1168475189 ps
T843 /workspace/coverage/default/35.lc_ctrl_alert_test.3991315212 Jul 05 05:35:03 PM PDT 24 Jul 05 05:35:05 PM PDT 24 36853054 ps
T844 /workspace/coverage/default/14.lc_ctrl_errors.1286815337 Jul 05 05:33:52 PM PDT 24 Jul 05 05:34:12 PM PDT 24 417576847 ps
T845 /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.174419221 Jul 05 05:35:18 PM PDT 24 Jul 05 05:35:23 PM PDT 24 25856371 ps
T846 /workspace/coverage/default/8.lc_ctrl_prog_failure.1290508558 Jul 05 05:33:29 PM PDT 24 Jul 05 05:33:33 PM PDT 24 190820090 ps
T847 /workspace/coverage/default/17.lc_ctrl_sec_token_digest.1494207380 Jul 05 05:34:10 PM PDT 24 Jul 05 05:34:27 PM PDT 24 1272773664 ps
T848 /workspace/coverage/default/43.lc_ctrl_sec_token_mux.1560148504 Jul 05 05:35:17 PM PDT 24 Jul 05 05:35:30 PM PDT 24 492608758 ps
T849 /workspace/coverage/default/19.lc_ctrl_smoke.660865175 Jul 05 05:34:18 PM PDT 24 Jul 05 05:34:22 PM PDT 24 80874447 ps
T850 /workspace/coverage/default/24.lc_ctrl_security_escalation.991773864 Jul 05 05:34:29 PM PDT 24 Jul 05 05:34:41 PM PDT 24 314604492 ps
T851 /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.109346210 Jul 05 05:33:29 PM PDT 24 Jul 05 05:33:30 PM PDT 24 32676931 ps
T852 /workspace/coverage/default/14.lc_ctrl_state_post_trans.1574646165 Jul 05 05:33:53 PM PDT 24 Jul 05 05:33:56 PM PDT 24 47751951 ps
T853 /workspace/coverage/default/32.lc_ctrl_security_escalation.3870179814 Jul 05 05:34:55 PM PDT 24 Jul 05 05:35:11 PM PDT 24 1539943617 ps
T854 /workspace/coverage/default/19.lc_ctrl_sec_mubi.2855012408 Jul 05 05:34:19 PM PDT 24 Jul 05 05:34:33 PM PDT 24 850257478 ps
T855 /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.2034155206 Jul 05 05:35:17 PM PDT 24 Jul 05 05:35:21 PM PDT 24 14177630 ps
T856 /workspace/coverage/default/11.lc_ctrl_jtag_smoke.3439453572 Jul 05 05:33:46 PM PDT 24 Jul 05 05:34:01 PM PDT 24 1109035187 ps
T857 /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.2934833566 Jul 05 05:32:57 PM PDT 24 Jul 05 05:33:21 PM PDT 24 3170735655 ps
T858 /workspace/coverage/default/7.lc_ctrl_prog_failure.3215997299 Jul 05 05:33:26 PM PDT 24 Jul 05 05:33:29 PM PDT 24 113967432 ps
T859 /workspace/coverage/default/30.lc_ctrl_sec_mubi.1570992804 Jul 05 05:34:43 PM PDT 24 Jul 05 05:34:57 PM PDT 24 459045764 ps
T860 /workspace/coverage/default/14.lc_ctrl_smoke.170480749 Jul 05 05:33:55 PM PDT 24 Jul 05 05:33:58 PM PDT 24 47302648 ps
T861 /workspace/coverage/default/15.lc_ctrl_errors.617541339 Jul 05 05:34:01 PM PDT 24 Jul 05 05:34:13 PM PDT 24 298225061 ps
T862 /workspace/coverage/default/21.lc_ctrl_prog_failure.2566667378 Jul 05 05:34:19 PM PDT 24 Jul 05 05:34:22 PM PDT 24 32834427 ps
T863 /workspace/coverage/default/9.lc_ctrl_regwen_during_op.2057749326 Jul 05 05:33:33 PM PDT 24 Jul 05 05:33:45 PM PDT 24 660486804 ps
T864 /workspace/coverage/default/17.lc_ctrl_alert_test.3018272633 Jul 05 05:34:07 PM PDT 24 Jul 05 05:34:09 PM PDT 24 34716573 ps
T865 /workspace/coverage/default/25.lc_ctrl_jtag_access.4190661278 Jul 05 05:34:40 PM PDT 24 Jul 05 05:34:45 PM PDT 24 339658562 ps
T866 /workspace/coverage/default/23.lc_ctrl_security_escalation.1627406471 Jul 05 05:34:29 PM PDT 24 Jul 05 05:34:38 PM PDT 24 690069459 ps
T121 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1248633243 Jul 05 06:04:19 PM PDT 24 Jul 05 06:04:24 PM PDT 24 417001494 ps
T112 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.844056013 Jul 05 06:04:09 PM PDT 24 Jul 05 06:04:11 PM PDT 24 64775792 ps
T130 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.999797221 Jul 05 06:04:24 PM PDT 24 Jul 05 06:04:25 PM PDT 24 172964504 ps
T115 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2901058059 Jul 05 06:05:49 PM PDT 24 Jul 05 06:05:51 PM PDT 24 37741915 ps
T867 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3070687374 Jul 05 06:04:44 PM PDT 24 Jul 05 06:04:47 PM PDT 24 271607937 ps
T222 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.44316273 Jul 05 06:05:28 PM PDT 24 Jul 05 06:05:31 PM PDT 24 40714219 ps
T122 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2207227178 Jul 05 06:05:29 PM PDT 24 Jul 05 06:05:31 PM PDT 24 42141976 ps
T150 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.171172631 Jul 05 06:05:30 PM PDT 24 Jul 05 06:05:33 PM PDT 24 83849089 ps
T868 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.534729272 Jul 05 06:04:10 PM PDT 24 Jul 05 06:04:12 PM PDT 24 278501689 ps
T113 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.573356105 Jul 05 06:05:14 PM PDT 24 Jul 05 06:05:16 PM PDT 24 44385014 ps
T153 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.3147809083 Jul 05 06:04:17 PM PDT 24 Jul 05 06:04:20 PM PDT 24 65942291 ps
T164 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2431226022 Jul 05 06:05:13 PM PDT 24 Jul 05 06:05:15 PM PDT 24 13302427 ps
T152 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3977912721 Jul 05 06:04:02 PM PDT 24 Jul 05 06:04:06 PM PDT 24 422439631 ps
T117 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.652050110 Jul 05 06:04:57 PM PDT 24 Jul 05 06:05:00 PM PDT 24 484846989 ps
T151 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2231204553 Jul 05 06:05:08 PM PDT 24 Jul 05 06:05:14 PM PDT 24 1820370711 ps
T208 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3242805832 Jul 05 06:04:29 PM PDT 24 Jul 05 06:04:30 PM PDT 24 59764809 ps
T869 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.20983629 Jul 05 06:05:08 PM PDT 24 Jul 05 06:05:11 PM PDT 24 389423242 ps
T223 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3448792593 Jul 05 06:05:20 PM PDT 24 Jul 05 06:05:22 PM PDT 24 132033081 ps
T209 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1934084556 Jul 05 06:04:51 PM PDT 24 Jul 05 06:04:53 PM PDT 24 57757048 ps
T118 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2672196857 Jul 05 06:04:19 PM PDT 24 Jul 05 06:04:20 PM PDT 24 27270057 ps
T870 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.3675480244 Jul 05 06:05:19 PM PDT 24 Jul 05 06:05:20 PM PDT 24 22346572 ps
T132 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2862627307 Jul 05 06:04:37 PM PDT 24 Jul 05 06:04:38 PM PDT 24 21317064 ps
T871 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1131235924 Jul 05 06:05:07 PM PDT 24 Jul 05 06:05:09 PM PDT 24 414132592 ps
T210 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2933116647 Jul 05 06:05:27 PM PDT 24 Jul 05 06:05:28 PM PDT 24 23052435 ps
T872 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.442009457 Jul 05 06:04:46 PM PDT 24 Jul 05 06:04:54 PM PDT 24 13228538814 ps
T873 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3327024654 Jul 05 06:05:01 PM PDT 24 Jul 05 06:05:15 PM PDT 24 5203498634 ps
T114 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3017604705 Jul 05 06:04:41 PM PDT 24 Jul 05 06:04:43 PM PDT 24 251441421 ps
T141 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.645536207 Jul 05 06:05:14 PM PDT 24 Jul 05 06:05:21 PM PDT 24 966934430 ps
T874 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1438538745 Jul 05 06:04:51 PM PDT 24 Jul 05 06:04:53 PM PDT 24 193006396 ps
T875 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3253915407 Jul 05 06:04:19 PM PDT 24 Jul 05 06:04:35 PM PDT 24 4211660779 ps
T178 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3382879449 Jul 05 06:04:45 PM PDT 24 Jul 05 06:04:48 PM PDT 24 147067559 ps
T116 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1507700915 Jul 05 06:04:52 PM PDT 24 Jul 05 06:04:57 PM PDT 24 490101853 ps
T224 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1074707072 Jul 05 06:04:33 PM PDT 24 Jul 05 06:04:35 PM PDT 24 26504239 ps
T225 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.883059261 Jul 05 06:05:15 PM PDT 24 Jul 05 06:05:17 PM PDT 24 17953041 ps
T125 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3180279490 Jul 05 06:05:15 PM PDT 24 Jul 05 06:05:17 PM PDT 24 145126837 ps
T196 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1123391517 Jul 05 06:04:59 PM PDT 24 Jul 05 06:05:02 PM PDT 24 163957920 ps
T119 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.1013259406 Jul 05 06:05:29 PM PDT 24 Jul 05 06:05:31 PM PDT 24 55006582 ps
T120 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.2321765508 Jul 05 06:05:08 PM PDT 24 Jul 05 06:05:11 PM PDT 24 158175739 ps
T876 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3832999668 Jul 05 06:05:28 PM PDT 24 Jul 05 06:05:30 PM PDT 24 23328621 ps
T877 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.3633979005 Jul 05 06:04:46 PM PDT 24 Jul 05 06:04:48 PM PDT 24 55429034 ps
T878 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.775269275 Jul 05 06:04:54 PM PDT 24 Jul 05 06:04:56 PM PDT 24 2043963261 ps
T226 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1476116400 Jul 05 06:05:07 PM PDT 24 Jul 05 06:05:09 PM PDT 24 17175882 ps
T128 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1451606795 Jul 05 06:05:14 PM PDT 24 Jul 05 06:05:17 PM PDT 24 24098585 ps
T879 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2574284923 Jul 05 06:04:18 PM PDT 24 Jul 05 06:04:21 PM PDT 24 419192517 ps
T880 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.729905476 Jul 05 06:04:53 PM PDT 24 Jul 05 06:04:57 PM PDT 24 532083892 ps
T227 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.4120620785 Jul 05 06:04:11 PM PDT 24 Jul 05 06:04:13 PM PDT 24 51237470 ps
T881 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.4293753482 Jul 05 06:04:42 PM PDT 24 Jul 05 06:05:23 PM PDT 24 1925666013 ps
T882 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1432330013 Jul 05 06:04:30 PM PDT 24 Jul 05 06:04:31 PM PDT 24 51145466 ps
T124 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.4162606798 Jul 05 06:05:32 PM PDT 24 Jul 05 06:05:37 PM PDT 24 250106018 ps
T129 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.1922872077 Jul 05 06:05:31 PM PDT 24 Jul 05 06:05:36 PM PDT 24 1078411146 ps
T165 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1859495158 Jul 05 06:05:16 PM PDT 24 Jul 05 06:05:17 PM PDT 24 15954183 ps
T883 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.159346068 Jul 05 06:04:08 PM PDT 24 Jul 05 06:04:10 PM PDT 24 62078830 ps
T134 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.4019048863 Jul 05 06:05:12 PM PDT 24 Jul 05 06:05:14 PM PDT 24 16774248 ps
T166 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2555619246 Jul 05 06:04:23 PM PDT 24 Jul 05 06:04:25 PM PDT 24 71428390 ps
T884 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3123288330 Jul 05 06:04:59 PM PDT 24 Jul 05 06:05:00 PM PDT 24 140184877 ps
T885 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1277318154 Jul 05 06:04:53 PM PDT 24 Jul 05 06:04:54 PM PDT 24 17554111 ps
T886 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1803703477 Jul 05 06:04:19 PM PDT 24 Jul 05 06:04:22 PM PDT 24 102612479 ps
T887 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.757700151 Jul 05 06:04:56 PM PDT 24 Jul 05 06:05:13 PM PDT 24 2059976545 ps
T888 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4100658552 Jul 05 06:04:32 PM PDT 24 Jul 05 06:04:34 PM PDT 24 144902956 ps
T889 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1321201437 Jul 05 06:05:19 PM PDT 24 Jul 05 06:05:21 PM PDT 24 24103926 ps
T890 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3940418571 Jul 05 06:05:07 PM PDT 24 Jul 05 06:05:14 PM PDT 24 2042889760 ps
T211 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.871975465 Jul 05 06:05:09 PM PDT 24 Jul 05 06:05:10 PM PDT 24 11761694 ps
T891 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3749610750 Jul 05 06:04:06 PM PDT 24 Jul 05 06:04:07 PM PDT 24 14288620 ps
T167 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.67263546 Jul 05 06:04:16 PM PDT 24 Jul 05 06:04:17 PM PDT 24 96003057 ps
T892 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.1301848197 Jul 05 06:05:10 PM PDT 24 Jul 05 06:05:12 PM PDT 24 110616517 ps
T893 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2413194276 Jul 05 06:04:43 PM PDT 24 Jul 05 06:04:44 PM PDT 24 43046710 ps
T894 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2557393219 Jul 05 06:05:20 PM PDT 24 Jul 05 06:05:21 PM PDT 24 17641013 ps
T895 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2844241207 Jul 05 06:04:37 PM PDT 24 Jul 05 06:04:39 PM PDT 24 122678796 ps
T212 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3271396263 Jul 05 06:05:21 PM PDT 24 Jul 05 06:05:23 PM PDT 24 17446663 ps
T896 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1277480436 Jul 05 06:04:53 PM PDT 24 Jul 05 06:05:34 PM PDT 24 7478583936 ps
T897 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1115546396 Jul 05 06:04:24 PM PDT 24 Jul 05 06:04:26 PM PDT 24 54756702 ps
T898 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3791706865 Jul 05 06:05:28 PM PDT 24 Jul 05 06:05:30 PM PDT 24 21070279 ps
T135 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2788559413 Jul 05 06:04:19 PM PDT 24 Jul 05 06:04:25 PM PDT 24 145870635 ps
T137 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3689263192 Jul 05 06:05:15 PM PDT 24 Jul 05 06:05:18 PM PDT 24 63346924 ps
T899 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3220217096 Jul 05 06:04:51 PM PDT 24 Jul 05 06:04:52 PM PDT 24 56561507 ps
T900 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3572912421 Jul 05 06:04:52 PM PDT 24 Jul 05 06:04:54 PM PDT 24 14218715 ps
T213 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.4002839170 Jul 05 06:05:30 PM PDT 24 Jul 05 06:05:32 PM PDT 24 17099783 ps
T901 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1504671014 Jul 05 06:04:19 PM PDT 24 Jul 05 06:04:22 PM PDT 24 70580207 ps
T902 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1049498489 Jul 05 06:04:59 PM PDT 24 Jul 05 06:05:00 PM PDT 24 151571937 ps
T903 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.4212043444 Jul 05 06:04:53 PM PDT 24 Jul 05 06:04:55 PM PDT 24 96586561 ps
T904 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.819368829 Jul 05 06:05:20 PM PDT 24 Jul 05 06:05:22 PM PDT 24 101813335 ps
T905 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.558904212 Jul 05 06:05:16 PM PDT 24 Jul 05 06:05:18 PM PDT 24 39270446 ps
T906 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3840960020 Jul 05 06:04:59 PM PDT 24 Jul 05 06:05:01 PM PDT 24 49146317 ps
T907 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1530949550 Jul 05 06:04:55 PM PDT 24 Jul 05 06:04:58 PM PDT 24 42099220 ps
T908 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1944006337 Jul 05 06:04:24 PM PDT 24 Jul 05 06:04:25 PM PDT 24 26464192 ps
T909 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2223296307 Jul 05 06:05:08 PM PDT 24 Jul 05 06:05:10 PM PDT 24 183110052 ps
T910 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.4136383336 Jul 05 06:05:16 PM PDT 24 Jul 05 06:05:18 PM PDT 24 35061712 ps
T214 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2762301396 Jul 05 06:04:45 PM PDT 24 Jul 05 06:04:47 PM PDT 24 67245581 ps
T215 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1794365164 Jul 05 06:04:31 PM PDT 24 Jul 05 06:04:33 PM PDT 24 16463917 ps
T911 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.198589468 Jul 05 06:04:31 PM PDT 24 Jul 05 06:04:32 PM PDT 24 33439853 ps
T138 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3192333959 Jul 05 06:05:09 PM PDT 24 Jul 05 06:05:13 PM PDT 24 391287779 ps
T126 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2947307548 Jul 05 06:05:07 PM PDT 24 Jul 05 06:05:11 PM PDT 24 726804241 ps
T139 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3515141165 Jul 05 06:04:43 PM PDT 24 Jul 05 06:04:46 PM PDT 24 81390771 ps
T912 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3464750173 Jul 05 06:04:23 PM PDT 24 Jul 05 06:04:26 PM PDT 24 1939333911 ps
T146 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3110933716 Jul 05 06:05:14 PM PDT 24 Jul 05 06:05:17 PM PDT 24 66715162 ps
T913 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1407272651 Jul 05 06:04:10 PM PDT 24 Jul 05 06:04:13 PM PDT 24 413982042 ps
T914 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3079922112 Jul 05 06:04:57 PM PDT 24 Jul 05 06:05:01 PM PDT 24 180604290 ps
T915 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1310683785 Jul 05 06:04:37 PM PDT 24 Jul 05 06:04:38 PM PDT 24 44635159 ps
T216 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.3427055113 Jul 05 06:04:10 PM PDT 24 Jul 05 06:04:12 PM PDT 24 26285174 ps
T916 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3165046268 Jul 05 06:04:24 PM PDT 24 Jul 05 06:04:27 PM PDT 24 48900219 ps
T917 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2025900766 Jul 05 06:04:51 PM PDT 24 Jul 05 06:04:53 PM PDT 24 48930971 ps
T918 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.385504501 Jul 05 06:04:10 PM PDT 24 Jul 05 06:04:13 PM PDT 24 100178030 ps
T919 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.425056128 Jul 05 06:04:51 PM PDT 24 Jul 05 06:04:53 PM PDT 24 33818023 ps
T920 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.4248356509 Jul 05 06:04:40 PM PDT 24 Jul 05 06:04:42 PM PDT 24 86412563 ps
T921 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3545314598 Jul 05 06:04:30 PM PDT 24 Jul 05 06:04:31 PM PDT 24 40515198 ps
T922 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3504005466 Jul 05 06:04:38 PM PDT 24 Jul 05 06:04:40 PM PDT 24 47123671 ps
T136 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3105298341 Jul 05 06:05:28 PM PDT 24 Jul 05 06:05:31 PM PDT 24 404966709 ps
T923 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.703075211 Jul 05 06:05:29 PM PDT 24 Jul 05 06:05:31 PM PDT 24 20481837 ps
T924 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.327612428 Jul 05 06:05:29 PM PDT 24 Jul 05 06:05:31 PM PDT 24 193613043 ps
T925 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2282959024 Jul 05 06:04:40 PM PDT 24 Jul 05 06:04:44 PM PDT 24 547591884 ps
T926 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1585906930 Jul 05 06:04:35 PM PDT 24 Jul 05 06:04:48 PM PDT 24 2201168337 ps
T927 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.4192908771 Jul 05 06:04:23 PM PDT 24 Jul 05 06:04:26 PM PDT 24 531501740 ps
T140 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.234880786 Jul 05 06:05:16 PM PDT 24 Jul 05 06:05:19 PM PDT 24 178984489 ps
T928 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1011459080 Jul 05 06:05:09 PM PDT 24 Jul 05 06:05:11 PM PDT 24 27235862 ps
T217 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.4265955707 Jul 05 06:04:44 PM PDT 24 Jul 05 06:04:45 PM PDT 24 54434028 ps
T929 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3846242407 Jul 05 06:05:03 PM PDT 24 Jul 05 06:05:06 PM PDT 24 118012222 ps
T930 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.564945402 Jul 05 06:05:08 PM PDT 24 Jul 05 06:05:10 PM PDT 24 21909542 ps
T931 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.460552914 Jul 05 06:04:56 PM PDT 24 Jul 05 06:05:01 PM PDT 24 966318564 ps
T932 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1829889554 Jul 05 06:05:00 PM PDT 24 Jul 05 06:05:02 PM PDT 24 1099381290 ps
T144 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2513691331 Jul 05 06:04:58 PM PDT 24 Jul 05 06:05:01 PM PDT 24 175034765 ps
T933 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2246601718 Jul 05 06:05:28 PM PDT 24 Jul 05 06:05:30 PM PDT 24 13638886 ps
T934 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.283413170 Jul 05 06:04:09 PM PDT 24 Jul 05 06:04:11 PM PDT 24 208700138 ps
T935 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1799155892 Jul 05 06:05:07 PM PDT 24 Jul 05 06:05:09 PM PDT 24 77760822 ps
T936 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3894092047 Jul 05 06:04:31 PM PDT 24 Jul 05 06:04:33 PM PDT 24 56039267 ps
T937 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.661806588 Jul 05 06:05:30 PM PDT 24 Jul 05 06:05:31 PM PDT 24 19770098 ps
T938 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.3332574990 Jul 05 06:04:59 PM PDT 24 Jul 05 06:05:01 PM PDT 24 41693551 ps
T147 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1840596371 Jul 05 06:05:07 PM PDT 24 Jul 05 06:05:09 PM PDT 24 119571332 ps
T939 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.952223628 Jul 05 06:04:52 PM PDT 24 Jul 05 06:05:04 PM PDT 24 520454990 ps
T940 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3458654194 Jul 05 06:05:07 PM PDT 24 Jul 05 06:05:09 PM PDT 24 282850042 ps
T941 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3454878188 Jul 05 06:04:09 PM PDT 24 Jul 05 06:04:12 PM PDT 24 121712876 ps
T942 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.4055719833 Jul 05 06:05:02 PM PDT 24 Jul 05 06:05:03 PM PDT 24 134349345 ps
T943 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1659571260 Jul 05 06:05:26 PM PDT 24 Jul 05 06:05:28 PM PDT 24 28390781 ps
T944 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1736704684 Jul 05 06:05:30 PM PDT 24 Jul 05 06:05:31 PM PDT 24 51417869 ps
T945 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2120142784 Jul 05 06:04:52 PM PDT 24 Jul 05 06:04:54 PM PDT 24 47354424 ps
T946 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2346837989 Jul 05 06:04:24 PM PDT 24 Jul 05 06:04:26 PM PDT 24 100789016 ps
T947 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.83626116 Jul 05 06:05:14 PM PDT 24 Jul 05 06:05:15 PM PDT 24 76275877 ps
T948 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1154301720 Jul 05 06:05:13 PM PDT 24 Jul 05 06:05:16 PM PDT 24 65249674 ps
T127 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1002534274 Jul 05 06:04:17 PM PDT 24 Jul 05 06:04:23 PM PDT 24 223920927 ps
T949 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.3484954849 Jul 05 06:04:58 PM PDT 24 Jul 05 06:05:08 PM PDT 24 1598071652 ps
T950 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.111358320 Jul 05 06:04:46 PM PDT 24 Jul 05 06:04:48 PM PDT 24 85745629 ps
T951 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2290543524 Jul 05 06:04:24 PM PDT 24 Jul 05 06:04:25 PM PDT 24 14812153 ps
T952 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2953595151 Jul 05 06:04:02 PM PDT 24 Jul 05 06:04:05 PM PDT 24 199904554 ps
T953 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.375861389 Jul 05 06:05:19 PM PDT 24 Jul 05 06:05:21 PM PDT 24 41429732 ps
T954 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2101134784 Jul 05 06:05:31 PM PDT 24 Jul 05 06:05:32 PM PDT 24 94222945 ps
T955 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1836583975 Jul 05 06:04:49 PM PDT 24 Jul 05 06:04:51 PM PDT 24 74014506 ps
T133 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1828587369 Jul 05 06:05:27 PM PDT 24 Jul 05 06:05:30 PM PDT 24 78864771 ps
T956 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2954489457 Jul 05 06:05:20 PM PDT 24 Jul 05 06:05:23 PM PDT 24 263282766 ps
T957 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3426930061 Jul 05 06:04:03 PM PDT 24 Jul 05 06:04:06 PM PDT 24 380225606 ps
T958 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1094446700 Jul 05 06:05:07 PM PDT 24 Jul 05 06:05:09 PM PDT 24 40840385 ps
T959 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3725747441 Jul 05 06:05:07 PM PDT 24 Jul 05 06:05:13 PM PDT 24 167893306 ps
T218 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2091327919 Jul 05 06:04:45 PM PDT 24 Jul 05 06:04:46 PM PDT 24 14571008 ps
T960 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.3510082077 Jul 05 06:04:53 PM PDT 24 Jul 05 06:04:55 PM PDT 24 182582598 ps
T219 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3211631059 Jul 05 06:04:25 PM PDT 24 Jul 05 06:04:26 PM PDT 24 16664499 ps
T961 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1516075163 Jul 05 06:04:01 PM PDT 24 Jul 05 06:04:12 PM PDT 24 1040703443 ps
T962 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1879269474 Jul 05 06:04:49 PM PDT 24 Jul 05 06:04:59 PM PDT 24 1976733785 ps
T963 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1801869808 Jul 05 06:05:23 PM PDT 24 Jul 05 06:05:26 PM PDT 24 96911270 ps
T148 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3553985926 Jul 05 06:04:46 PM PDT 24 Jul 05 06:04:50 PM PDT 24 349932718 ps
T220 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1617771359 Jul 05 06:05:13 PM PDT 24 Jul 05 06:05:14 PM PDT 24 20380608 ps
T964 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2784838584 Jul 05 06:05:20 PM PDT 24 Jul 05 06:05:22 PM PDT 24 90297961 ps
T965 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2316494581 Jul 05 06:04:44 PM PDT 24 Jul 05 06:04:47 PM PDT 24 187631780 ps
T143 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.521273145 Jul 05 06:05:29 PM PDT 24 Jul 05 06:05:32 PM PDT 24 49343719 ps
T145 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2789959399 Jul 05 06:05:30 PM PDT 24 Jul 05 06:05:34 PM PDT 24 387317906 ps
T149 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.336526517 Jul 05 06:05:19 PM PDT 24 Jul 05 06:05:21 PM PDT 24 159820623 ps
T966 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.305072310 Jul 05 06:04:37 PM PDT 24 Jul 05 06:04:40 PM PDT 24 648448843 ps
T967 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3193286632 Jul 05 06:05:18 PM PDT 24 Jul 05 06:05:20 PM PDT 24 100995668 ps
T968 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.276316469 Jul 05 06:04:58 PM PDT 24 Jul 05 06:04:59 PM PDT 24 52443489 ps
T969 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.802958860 Jul 05 06:04:32 PM PDT 24 Jul 05 06:04:33 PM PDT 24 93734290 ps
T970 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3602114583 Jul 05 06:05:29 PM PDT 24 Jul 05 06:05:31 PM PDT 24 36457975 ps
T971 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1558939449 Jul 05 06:05:12 PM PDT 24 Jul 05 06:05:15 PM PDT 24 187917568 ps
T972 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3651636740 Jul 05 06:05:22 PM PDT 24 Jul 05 06:05:24 PM PDT 24 21112879 ps
T973 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.423329704 Jul 05 06:05:15 PM PDT 24 Jul 05 06:05:17 PM PDT 24 130857147 ps
T974 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1039519588 Jul 05 06:04:47 PM PDT 24 Jul 05 06:04:49 PM PDT 24 60005316 ps
T221 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.480330281 Jul 05 06:05:08 PM PDT 24 Jul 05 06:05:10 PM PDT 24 22412146 ps
T975 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.414299064 Jul 05 06:05:20 PM PDT 24 Jul 05 06:05:23 PM PDT 24 115006988 ps
T142 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3652433931 Jul 05 06:05:20 PM PDT 24 Jul 05 06:05:23 PM PDT 24 184419400 ps
T976 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.2619805487 Jul 05 06:09:29 PM PDT 24 Jul 05 06:09:39 PM PDT 24 1396014955 ps
T977 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.699756852 Jul 05 06:05:21 PM PDT 24 Jul 05 06:05:22 PM PDT 24 30916620 ps
T978 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.429166338 Jul 05 06:04:47 PM PDT 24 Jul 05 06:04:48 PM PDT 24 23799078 ps
T979 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1491457636 Jul 05 06:04:49 PM PDT 24 Jul 05 06:04:50 PM PDT 24 60804768 ps
T980 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.67977908 Jul 05 06:04:46 PM PDT 24 Jul 05 06:04:49 PM PDT 24 1325036635 ps
T981 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3571043335 Jul 05 06:04:57 PM PDT 24 Jul 05 06:05:00 PM PDT 24 59640190 ps
T982 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3896475659 Jul 05 06:05:04 PM PDT 24 Jul 05 06:05:15 PM PDT 24 2220105874 ps
T983 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1952267771 Jul 05 06:04:53 PM PDT 24 Jul 05 06:04:55 PM PDT 24 71303361 ps
T984 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3585673825 Jul 05 06:05:07 PM PDT 24 Jul 05 06:05:24 PM PDT 24 1455064325 ps
T985 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2689287730 Jul 05 06:04:54 PM PDT 24 Jul 05 06:04:56 PM PDT 24 91087506 ps

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.1847093227
Short name T15
Test name
Test status
Simulation time 247284881 ps
CPU time 10.28 seconds
Started Jul 05 05:33:13 PM PDT 24
Finished Jul 05 05:33:25 PM PDT 24
Peak memory 225560 kb
Host smart-ae618d45-74b1-4e45-a501-1fef6c06831e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847093227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.1847093227
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.3427966159
Short name T24
Test name
Test status
Simulation time 117353652238 ps
CPU time 665.96 seconds
Started Jul 05 05:33:06 PM PDT 24
Finished Jul 05 05:44:13 PM PDT 24
Peak memory 496148 kb
Host smart-406e7450-bc3e-48c2-bb2b-2affe455af57
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3427966159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.3427966159
Directory /workspace/2.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.2991832572
Short name T63
Test name
Test status
Simulation time 1171277271 ps
CPU time 10.72 seconds
Started Jul 05 05:34:05 PM PDT 24
Finished Jul 05 05:34:16 PM PDT 24
Peak memory 217812 kb
Host smart-96706413-eac4-4598-a044-abb30a4137fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991832572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.2991832572
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.2478565453
Short name T17
Test name
Test status
Simulation time 510197402 ps
CPU time 14.72 seconds
Started Jul 05 05:34:01 PM PDT 24
Finished Jul 05 05:34:17 PM PDT 24
Peak memory 225532 kb
Host smart-fa160a3d-67d9-4212-a436-f17bc92f97c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478565453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.2478565453
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2901058059
Short name T115
Test name
Test status
Simulation time 37741915 ps
CPU time 1.56 seconds
Started Jul 05 06:05:49 PM PDT 24
Finished Jul 05 06:05:51 PM PDT 24
Peak memory 218152 kb
Host smart-5bd4cfaa-64bb-4bd6-b135-601bc6afcb80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901058059 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.2901058059
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.2770820121
Short name T2
Test name
Test status
Simulation time 34078027 ps
CPU time 0.8 seconds
Started Jul 05 05:34:41 PM PDT 24
Finished Jul 05 05:34:42 PM PDT 24
Peak memory 208256 kb
Host smart-d0871888-c319-4c02-a560-a5f2740b743d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770820121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.2770820121
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.2118311432
Short name T66
Test name
Test status
Simulation time 928861200 ps
CPU time 36.52 seconds
Started Jul 05 05:32:50 PM PDT 24
Finished Jul 05 05:33:28 PM PDT 24
Peak memory 269856 kb
Host smart-1077f89b-018f-4085-b737-4cf3b122d34d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118311432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.2118311432
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.2928978934
Short name T163
Test name
Test status
Simulation time 18410438402 ps
CPU time 355.98 seconds
Started Jul 05 05:33:23 PM PDT 24
Finished Jul 05 05:39:20 PM PDT 24
Peak memory 267156 kb
Host smart-1f756a23-1128-4201-999b-f2412ef41786
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2928978934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.2928978934
Directory /workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.155197124
Short name T71
Test name
Test status
Simulation time 360761323 ps
CPU time 7.37 seconds
Started Jul 05 05:35:41 PM PDT 24
Finished Jul 05 05:35:50 PM PDT 24
Peak memory 217724 kb
Host smart-4eafe74b-937f-4d23-ae28-d19c32f2fa1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155197124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.155197124
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.2177801905
Short name T9
Test name
Test status
Simulation time 4180834867 ps
CPU time 9.31 seconds
Started Jul 05 05:35:33 PM PDT 24
Finished Jul 05 05:35:44 PM PDT 24
Peak memory 217180 kb
Host smart-d007c168-fc75-415a-a918-e0bcc97b6ffc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177801905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.2177801905
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.265989529
Short name T388
Test name
Test status
Simulation time 1271253264 ps
CPU time 13.74 seconds
Started Jul 05 05:35:00 PM PDT 24
Finished Jul 05 05:35:14 PM PDT 24
Peak memory 225080 kb
Host smart-6aaaea38-bf70-458f-b487-41f231ae146c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265989529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.265989529
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.72618275
Short name T1
Test name
Test status
Simulation time 33560570 ps
CPU time 0.95 seconds
Started Jul 05 05:35:05 PM PDT 24
Finished Jul 05 05:35:07 PM PDT 24
Peak memory 208544 kb
Host smart-ca1c51e9-37a4-42a5-9e7e-b46721d16898
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72618275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.72618275
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.2756620909
Short name T4
Test name
Test status
Simulation time 298450303 ps
CPU time 10.19 seconds
Started Jul 05 05:35:20 PM PDT 24
Finished Jul 05 05:35:33 PM PDT 24
Peak memory 218436 kb
Host smart-68703c94-6ed3-4ee9-b52d-614138d66dbf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756620909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.2756620909
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3105298341
Short name T136
Test name
Test status
Simulation time 404966709 ps
CPU time 2.78 seconds
Started Jul 05 06:05:28 PM PDT 24
Finished Jul 05 06:05:31 PM PDT 24
Peak memory 221616 kb
Host smart-78d41c72-ccf1-41e7-bd51-b17f1bf91b81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105298341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.3105298341
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2933116647
Short name T210
Test name
Test status
Simulation time 23052435 ps
CPU time 0.84 seconds
Started Jul 05 06:05:27 PM PDT 24
Finished Jul 05 06:05:28 PM PDT 24
Peak memory 209328 kb
Host smart-44e60e64-fe71-4d1c-a67f-9d435a9f5acc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933116647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.2933116647
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1248633243
Short name T121
Test name
Test status
Simulation time 417001494 ps
CPU time 5.37 seconds
Started Jul 05 06:04:19 PM PDT 24
Finished Jul 05 06:04:24 PM PDT 24
Peak memory 209244 kb
Host smart-32fbaaaf-e42d-4da1-8735-e310e5b6a0ed
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248633243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.1248633243
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.3698566090
Short name T20
Test name
Test status
Simulation time 21628140767 ps
CPU time 105.1 seconds
Started Jul 05 05:33:44 PM PDT 24
Finished Jul 05 05:35:30 PM PDT 24
Peak memory 283104 kb
Host smart-13b89795-7062-49da-8116-3bbd54be5ca8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698566090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.3698566090
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.4162606798
Short name T124
Test name
Test status
Simulation time 250106018 ps
CPU time 4.13 seconds
Started Jul 05 06:05:32 PM PDT 24
Finished Jul 05 06:05:37 PM PDT 24
Peak memory 217720 kb
Host smart-846ffa85-7b69-4125-b402-112042da8178
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162606798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.4162606798
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.2372491700
Short name T57
Test name
Test status
Simulation time 11891185977 ps
CPU time 427.62 seconds
Started Jul 05 05:34:08 PM PDT 24
Finished Jul 05 05:41:17 PM PDT 24
Peak memory 315364 kb
Host smart-1352991f-3764-493f-957b-28b561c82590
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2372491700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.2372491700
Directory /workspace/17.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.857768484
Short name T3
Test name
Test status
Simulation time 2036705065 ps
CPU time 8.14 seconds
Started Jul 05 05:35:29 PM PDT 24
Finished Jul 05 05:35:38 PM PDT 24
Peak memory 217772 kb
Host smart-7e90c1cf-3906-46cc-9cf4-e50ab5fe5346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857768484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.857768484
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.234880786
Short name T140
Test name
Test status
Simulation time 178984489 ps
CPU time 3.05 seconds
Started Jul 05 06:05:16 PM PDT 24
Finished Jul 05 06:05:19 PM PDT 24
Peak memory 222160 kb
Host smart-5642ff69-a42f-457a-ae38-fb456e2fa12c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234880786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg_
err.234880786
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2513691331
Short name T144
Test name
Test status
Simulation time 175034765 ps
CPU time 2.28 seconds
Started Jul 05 06:04:58 PM PDT 24
Finished Jul 05 06:05:01 PM PDT 24
Peak memory 221840 kb
Host smart-c7c6b468-8b8e-4f65-84f6-13c997f302ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513691331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.2513691331
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.2048745465
Short name T107
Test name
Test status
Simulation time 6847917392 ps
CPU time 74.77 seconds
Started Jul 05 05:34:11 PM PDT 24
Finished Jul 05 05:35:26 PM PDT 24
Peak memory 268596 kb
Host smart-47825663-0940-4ed2-951a-b6efd89518d4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048745465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.2048745465
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.285543704
Short name T75
Test name
Test status
Simulation time 56567578 ps
CPU time 2.57 seconds
Started Jul 05 05:34:09 PM PDT 24
Finished Jul 05 05:34:12 PM PDT 24
Peak memory 217868 kb
Host smart-8567f2f0-c606-4d73-970f-d24978b2df73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285543704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.285543704
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.336526517
Short name T149
Test name
Test status
Simulation time 159820623 ps
CPU time 1.73 seconds
Started Jul 05 06:05:19 PM PDT 24
Finished Jul 05 06:05:21 PM PDT 24
Peak memory 221996 kb
Host smart-4b18c288-b274-46ac-86bb-931a3827cc4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336526517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg_
err.336526517
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.4095792385
Short name T97
Test name
Test status
Simulation time 29604360730 ps
CPU time 556.89 seconds
Started Jul 05 05:34:45 PM PDT 24
Finished Jul 05 05:44:04 PM PDT 24
Peak memory 310324 kb
Host smart-7ae6e94d-7d3c-4646-a6e7-07ee32fa49b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4095792385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.4095792385
Directory /workspace/30.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.3688610849
Short name T131
Test name
Test status
Simulation time 55647695 ps
CPU time 0.89 seconds
Started Jul 05 05:33:28 PM PDT 24
Finished Jul 05 05:33:29 PM PDT 24
Peak memory 208364 kb
Host smart-a94ceb3d-0c15-45e2-bd9c-e913170c3e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688610849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.3688610849
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3652433931
Short name T142
Test name
Test status
Simulation time 184419400 ps
CPU time 1.77 seconds
Started Jul 05 06:05:20 PM PDT 24
Finished Jul 05 06:05:23 PM PDT 24
Peak memory 222080 kb
Host smart-36c38d1e-7120-46fd-ab86-5e2e8fd59614
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652433931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.3652433931
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2789959399
Short name T145
Test name
Test status
Simulation time 387317906 ps
CPU time 3.09 seconds
Started Jul 05 06:05:30 PM PDT 24
Finished Jul 05 06:05:34 PM PDT 24
Peak memory 222192 kb
Host smart-315aefe2-4c2c-4147-8b2d-2825cce04abb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789959399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.2789959399
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1828587369
Short name T133
Test name
Test status
Simulation time 78864771 ps
CPU time 3.48 seconds
Started Jul 05 06:05:27 PM PDT 24
Finished Jul 05 06:05:30 PM PDT 24
Peak memory 222280 kb
Host smart-84ec695d-8700-47b2-8254-523093601ab8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828587369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.1828587369
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.379453870
Short name T231
Test name
Test status
Simulation time 32223092 ps
CPU time 0.92 seconds
Started Jul 05 05:32:48 PM PDT 24
Finished Jul 05 05:32:50 PM PDT 24
Peak memory 208404 kb
Host smart-652d3345-6d67-41dc-88b3-a0d26cd50b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379453870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.379453870
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.518644045
Short name T172
Test name
Test status
Simulation time 11017864 ps
CPU time 0.89 seconds
Started Jul 05 05:33:13 PM PDT 24
Finished Jul 05 05:33:14 PM PDT 24
Peak memory 208268 kb
Host smart-ca9a9556-cca3-420b-8068-a017b394f45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518644045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.518644045
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3454878188
Short name T941
Test name
Test status
Simulation time 121712876 ps
CPU time 3.25 seconds
Started Jul 05 06:04:09 PM PDT 24
Finished Jul 05 06:04:12 PM PDT 24
Peak memory 217972 kb
Host smart-194a2f29-6969-4b53-abeb-f0d83d2a5456
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454878188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.3454878188
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.844056013
Short name T112
Test name
Test status
Simulation time 64775792 ps
CPU time 2.07 seconds
Started Jul 05 06:04:09 PM PDT 24
Finished Jul 05 06:04:11 PM PDT 24
Peak memory 221916 kb
Host smart-797ad972-f2f2-414f-ab3b-d6866e04ac38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844056013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_e
rr.844056013
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1002534274
Short name T127
Test name
Test status
Simulation time 223920927 ps
CPU time 4.99 seconds
Started Jul 05 06:04:17 PM PDT 24
Finished Jul 05 06:04:23 PM PDT 24
Peak memory 217504 kb
Host smart-1a2e7dca-229c-4715-9d96-d64d9f7fe55d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002534274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.1002534274
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3110933716
Short name T146
Test name
Test status
Simulation time 66715162 ps
CPU time 2.73 seconds
Started Jul 05 06:05:14 PM PDT 24
Finished Jul 05 06:05:17 PM PDT 24
Peak memory 217500 kb
Host smart-ed82ca6d-56bc-46e7-a2c6-74042a204a80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110933716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.3110933716
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.573356105
Short name T113
Test name
Test status
Simulation time 44385014 ps
CPU time 2.21 seconds
Started Jul 05 06:05:14 PM PDT 24
Finished Jul 05 06:05:16 PM PDT 24
Peak memory 222196 kb
Host smart-cd95e7c2-e1ae-425b-a208-5701d3d49153
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573356105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_e
rr.573356105
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.3284124472
Short name T5
Test name
Test status
Simulation time 59784820 ps
CPU time 2.9 seconds
Started Jul 05 05:32:49 PM PDT 24
Finished Jul 05 05:32:53 PM PDT 24
Peak memory 214496 kb
Host smart-b858e9d0-47a4-4374-aa70-0fcc481c7bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284124472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.3284124472
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.3039996186
Short name T50
Test name
Test status
Simulation time 1300030706 ps
CPU time 14.6 seconds
Started Jul 05 05:33:56 PM PDT 24
Finished Jul 05 05:34:11 PM PDT 24
Peak memory 225504 kb
Host smart-4da6b056-32ee-420d-a6b0-27ad2205d190
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039996186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.3039996186
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.534729272
Short name T868
Test name
Test status
Simulation time 278501689 ps
CPU time 1.26 seconds
Started Jul 05 06:04:10 PM PDT 24
Finished Jul 05 06:04:12 PM PDT 24
Peak memory 209216 kb
Host smart-f15c9644-3d2c-4479-a87e-0bcdd473d900
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534729272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasing
.534729272
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.385504501
Short name T918
Test name
Test status
Simulation time 100178030 ps
CPU time 2.06 seconds
Started Jul 05 06:04:10 PM PDT 24
Finished Jul 05 06:04:13 PM PDT 24
Peak memory 209260 kb
Host smart-2182c500-78b1-43ba-9146-990653ba7daf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385504501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bash
.385504501
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.3427055113
Short name T216
Test name
Test status
Simulation time 26285174 ps
CPU time 1 seconds
Started Jul 05 06:04:10 PM PDT 24
Finished Jul 05 06:04:12 PM PDT 24
Peak memory 210476 kb
Host smart-b4496699-466a-4928-bb51-3897682b63ee
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427055113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.3427055113
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2672196857
Short name T118
Test name
Test status
Simulation time 27270057 ps
CPU time 1.28 seconds
Started Jul 05 06:04:19 PM PDT 24
Finished Jul 05 06:04:20 PM PDT 24
Peak memory 218636 kb
Host smart-be3e827c-725b-4609-8e55-ae8631175aa6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672196857 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.2672196857
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3749610750
Short name T891
Test name
Test status
Simulation time 14288620 ps
CPU time 0.88 seconds
Started Jul 05 06:04:06 PM PDT 24
Finished Jul 05 06:04:07 PM PDT 24
Peak memory 209104 kb
Host smart-da005539-9ff4-48d6-a949-03f541263cea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749610750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.3749610750
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.283413170
Short name T934
Test name
Test status
Simulation time 208700138 ps
CPU time 1.27 seconds
Started Jul 05 06:04:09 PM PDT 24
Finished Jul 05 06:04:11 PM PDT 24
Peak memory 209120 kb
Host smart-98d45d99-ce6f-4e0d-9bc7-31ec52efe948
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283413170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.lc_ctrl_jtag_alert_test.283413170
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3426930061
Short name T957
Test name
Test status
Simulation time 380225606 ps
CPU time 2.64 seconds
Started Jul 05 06:04:03 PM PDT 24
Finished Jul 05 06:04:06 PM PDT 24
Peak memory 209236 kb
Host smart-f17a0a3d-8abb-4972-b029-12a6377ae687
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426930061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.3426930061
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1516075163
Short name T961
Test name
Test status
Simulation time 1040703443 ps
CPU time 10.16 seconds
Started Jul 05 06:04:01 PM PDT 24
Finished Jul 05 06:04:12 PM PDT 24
Peak memory 208760 kb
Host smart-3b3d4aaf-ef0d-404d-ba21-f27f59afdc4c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516075163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.1516075163
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3977912721
Short name T152
Test name
Test status
Simulation time 422439631 ps
CPU time 3.22 seconds
Started Jul 05 06:04:02 PM PDT 24
Finished Jul 05 06:04:06 PM PDT 24
Peak memory 217572 kb
Host smart-6eb8fd92-b260-423b-a741-ae980aca4a22
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977912721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.3977912721
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1407272651
Short name T913
Test name
Test status
Simulation time 413982042 ps
CPU time 3.46 seconds
Started Jul 05 06:04:10 PM PDT 24
Finished Jul 05 06:04:13 PM PDT 24
Peak memory 217540 kb
Host smart-ed8a7fef-51bb-4dfa-94e8-72e03d6df6e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140727
2651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1407272651
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2953595151
Short name T952
Test name
Test status
Simulation time 199904554 ps
CPU time 2.67 seconds
Started Jul 05 06:04:02 PM PDT 24
Finished Jul 05 06:04:05 PM PDT 24
Peak memory 209240 kb
Host smart-b28df8bf-0078-4c67-abec-2d3f54ea0f62
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953595151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.2953595151
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.159346068
Short name T883
Test name
Test status
Simulation time 62078830 ps
CPU time 1.18 seconds
Started Jul 05 06:04:08 PM PDT 24
Finished Jul 05 06:04:10 PM PDT 24
Peak memory 209284 kb
Host smart-2df2cf98-6a42-4877-9e29-c2dad5c715eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159346068 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.159346068
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.4120620785
Short name T227
Test name
Test status
Simulation time 51237470 ps
CPU time 1.11 seconds
Started Jul 05 06:04:11 PM PDT 24
Finished Jul 05 06:04:13 PM PDT 24
Peak memory 209360 kb
Host smart-2ae7a1dd-496a-4af4-a069-3f4f6c7519aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120620785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.4120620785
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3211631059
Short name T219
Test name
Test status
Simulation time 16664499 ps
CPU time 0.96 seconds
Started Jul 05 06:04:25 PM PDT 24
Finished Jul 05 06:04:26 PM PDT 24
Peak memory 209308 kb
Host smart-b7ae355c-6b20-4a9b-8b75-e81ab975b4c4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211631059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.3211631059
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3165046268
Short name T916
Test name
Test status
Simulation time 48900219 ps
CPU time 2.06 seconds
Started Jul 05 06:04:24 PM PDT 24
Finished Jul 05 06:04:27 PM PDT 24
Peak memory 217168 kb
Host smart-705a5079-ad27-40a7-8335-4c800ada541b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165046268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.3165046268
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1944006337
Short name T908
Test name
Test status
Simulation time 26464192 ps
CPU time 0.95 seconds
Started Jul 05 06:04:24 PM PDT 24
Finished Jul 05 06:04:25 PM PDT 24
Peak memory 209868 kb
Host smart-7db24e91-4495-4d76-a69e-7bcb53ee2961
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944006337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.1944006337
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1115546396
Short name T897
Test name
Test status
Simulation time 54756702 ps
CPU time 1.57 seconds
Started Jul 05 06:04:24 PM PDT 24
Finished Jul 05 06:04:26 PM PDT 24
Peak memory 217640 kb
Host smart-72f720ac-d1a2-42e5-9364-973334b72921
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115546396 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.1115546396
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2290543524
Short name T951
Test name
Test status
Simulation time 14812153 ps
CPU time 0.84 seconds
Started Jul 05 06:04:24 PM PDT 24
Finished Jul 05 06:04:25 PM PDT 24
Peak memory 209300 kb
Host smart-7883e30c-eb10-4d84-b12a-9d115ce22905
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290543524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.2290543524
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.3147809083
Short name T153
Test name
Test status
Simulation time 65942291 ps
CPU time 2.13 seconds
Started Jul 05 06:04:17 PM PDT 24
Finished Jul 05 06:04:20 PM PDT 24
Peak memory 209232 kb
Host smart-392b576b-7258-4774-aa07-f2e3045e931d
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147809083 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.3147809083
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3253915407
Short name T875
Test name
Test status
Simulation time 4211660779 ps
CPU time 14.94 seconds
Started Jul 05 06:04:19 PM PDT 24
Finished Jul 05 06:04:35 PM PDT 24
Peak memory 209312 kb
Host smart-226a0a5a-5f79-4bcd-a55e-363c5f17d39b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253915407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.3253915407
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2574284923
Short name T879
Test name
Test status
Simulation time 419192517 ps
CPU time 1.78 seconds
Started Jul 05 06:04:18 PM PDT 24
Finished Jul 05 06:04:21 PM PDT 24
Peak memory 210844 kb
Host smart-d4347923-dd92-46d9-a213-b9b5d4d613fb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574284923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.2574284923
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1803703477
Short name T886
Test name
Test status
Simulation time 102612479 ps
CPU time 2.2 seconds
Started Jul 05 06:04:19 PM PDT 24
Finished Jul 05 06:04:22 PM PDT 24
Peak memory 217544 kb
Host smart-6cd7f523-4475-410b-911e-a5ab8cc7571c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180370
3477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1803703477
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1504671014
Short name T901
Test name
Test status
Simulation time 70580207 ps
CPU time 2.17 seconds
Started Jul 05 06:04:19 PM PDT 24
Finished Jul 05 06:04:22 PM PDT 24
Peak memory 209244 kb
Host smart-c3f18228-cac0-4b53-b32d-cd995e523520
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504671014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.1504671014
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.67263546
Short name T167
Test name
Test status
Simulation time 96003057 ps
CPU time 1.02 seconds
Started Jul 05 06:04:16 PM PDT 24
Finished Jul 05 06:04:17 PM PDT 24
Peak memory 209240 kb
Host smart-4a67c5d4-1e28-4968-bcd6-2498d6498afe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67263546 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.67263546
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2555619246
Short name T166
Test name
Test status
Simulation time 71428390 ps
CPU time 1.39 seconds
Started Jul 05 06:04:23 PM PDT 24
Finished Jul 05 06:04:25 PM PDT 24
Peak memory 217628 kb
Host smart-5048eb1f-8564-4d3c-baef-557872002fd4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555619246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.2555619246
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2788559413
Short name T135
Test name
Test status
Simulation time 145870635 ps
CPU time 5.5 seconds
Started Jul 05 06:04:19 PM PDT 24
Finished Jul 05 06:04:25 PM PDT 24
Peak memory 217512 kb
Host smart-d72f373b-19ea-45b5-a88e-38958bb1d986
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788559413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.2788559413
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1321201437
Short name T889
Test name
Test status
Simulation time 24103926 ps
CPU time 1.49 seconds
Started Jul 05 06:05:19 PM PDT 24
Finished Jul 05 06:05:21 PM PDT 24
Peak memory 221360 kb
Host smart-7ac00109-69a8-4622-8116-0c666d25eeaf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321201437 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.1321201437
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2431226022
Short name T164
Test name
Test status
Simulation time 13302427 ps
CPU time 0.89 seconds
Started Jul 05 06:05:13 PM PDT 24
Finished Jul 05 06:05:15 PM PDT 24
Peak memory 209268 kb
Host smart-ec35ddfb-c46f-4363-8adf-929a7b7a9720
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431226022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.2431226022
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.423329704
Short name T973
Test name
Test status
Simulation time 130857147 ps
CPU time 1.27 seconds
Started Jul 05 06:05:15 PM PDT 24
Finished Jul 05 06:05:17 PM PDT 24
Peak memory 211340 kb
Host smart-af24d642-c3a6-43a4-96d4-884422addd34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423329704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_same_csr_outstanding.423329704
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1451606795
Short name T128
Test name
Test status
Simulation time 24098585 ps
CPU time 1.69 seconds
Started Jul 05 06:05:14 PM PDT 24
Finished Jul 05 06:05:17 PM PDT 24
Peak memory 218528 kb
Host smart-fa0134d0-55e5-4278-98ef-02688c7901f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451606795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.1451606795
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.4019048863
Short name T134
Test name
Test status
Simulation time 16774248 ps
CPU time 1.28 seconds
Started Jul 05 06:05:12 PM PDT 24
Finished Jul 05 06:05:14 PM PDT 24
Peak memory 217584 kb
Host smart-52b652a1-b58f-4259-8c4a-210dd0f0effa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019048863 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.4019048863
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1617771359
Short name T220
Test name
Test status
Simulation time 20380608 ps
CPU time 0.86 seconds
Started Jul 05 06:05:13 PM PDT 24
Finished Jul 05 06:05:14 PM PDT 24
Peak memory 209320 kb
Host smart-641eb707-8996-4d9b-8f04-02e90efe989c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617771359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.1617771359
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1011459080
Short name T928
Test name
Test status
Simulation time 27235862 ps
CPU time 1.07 seconds
Started Jul 05 06:05:09 PM PDT 24
Finished Jul 05 06:05:11 PM PDT 24
Peak memory 209356 kb
Host smart-c674c912-f93b-4343-9d78-748d99e99f8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011459080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.1011459080
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1154301720
Short name T948
Test name
Test status
Simulation time 65249674 ps
CPU time 1.9 seconds
Started Jul 05 06:05:13 PM PDT 24
Finished Jul 05 06:05:16 PM PDT 24
Peak memory 217512 kb
Host smart-14fae553-5259-47ec-a04f-427cda84c7d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154301720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.1154301720
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3180279490
Short name T125
Test name
Test status
Simulation time 145126837 ps
CPU time 1.92 seconds
Started Jul 05 06:05:15 PM PDT 24
Finished Jul 05 06:05:17 PM PDT 24
Peak memory 221992 kb
Host smart-897ce26f-da89-48a5-bb8a-52007e112ce2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180279490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.3180279490
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3651636740
Short name T972
Test name
Test status
Simulation time 21112879 ps
CPU time 1.07 seconds
Started Jul 05 06:05:22 PM PDT 24
Finished Jul 05 06:05:24 PM PDT 24
Peak memory 217536 kb
Host smart-4d9f9481-3a85-4842-8d98-6b11105c5076
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651636740 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.3651636740
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.83626116
Short name T947
Test name
Test status
Simulation time 76275877 ps
CPU time 1.04 seconds
Started Jul 05 06:05:14 PM PDT 24
Finished Jul 05 06:05:15 PM PDT 24
Peak memory 209304 kb
Host smart-252dedc6-e9a4-4d57-bfca-299300ff2641
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83626116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.83626116
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.4136383336
Short name T910
Test name
Test status
Simulation time 35061712 ps
CPU time 1.39 seconds
Started Jul 05 06:05:16 PM PDT 24
Finished Jul 05 06:05:18 PM PDT 24
Peak memory 209332 kb
Host smart-8d0eb6db-6691-4f7c-8390-63d10f189faa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136383336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.4136383336
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3193286632
Short name T967
Test name
Test status
Simulation time 100995668 ps
CPU time 1.66 seconds
Started Jul 05 06:05:18 PM PDT 24
Finished Jul 05 06:05:20 PM PDT 24
Peak memory 217968 kb
Host smart-424d904c-db45-4dd3-b166-50f28d68c60e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193286632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.3193286632
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.375861389
Short name T953
Test name
Test status
Simulation time 41429732 ps
CPU time 1.91 seconds
Started Jul 05 06:05:19 PM PDT 24
Finished Jul 05 06:05:21 PM PDT 24
Peak memory 219352 kb
Host smart-c9651673-3c81-4d84-b8f8-fe14b8aec990
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375861389 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.375861389
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.699756852
Short name T977
Test name
Test status
Simulation time 30916620 ps
CPU time 1 seconds
Started Jul 05 06:05:21 PM PDT 24
Finished Jul 05 06:05:22 PM PDT 24
Peak memory 208900 kb
Host smart-22318691-b5e8-4489-9f43-8edcf76e34f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699756852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.699756852
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3448792593
Short name T223
Test name
Test status
Simulation time 132033081 ps
CPU time 1.04 seconds
Started Jul 05 06:05:20 PM PDT 24
Finished Jul 05 06:05:22 PM PDT 24
Peak memory 209300 kb
Host smart-01cd87c3-f8eb-4302-929d-261687b09d9c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448792593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.3448792593
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2954489457
Short name T956
Test name
Test status
Simulation time 263282766 ps
CPU time 3.1 seconds
Started Jul 05 06:05:20 PM PDT 24
Finished Jul 05 06:05:23 PM PDT 24
Peak memory 217580 kb
Host smart-4f49b4e1-bc64-4ddd-9e06-1655b2f58267
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954489457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.2954489457
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.414299064
Short name T975
Test name
Test status
Simulation time 115006988 ps
CPU time 2.9 seconds
Started Jul 05 06:05:20 PM PDT 24
Finished Jul 05 06:05:23 PM PDT 24
Peak memory 222392 kb
Host smart-5dbd6597-6d7c-4ab9-ad5a-9aa3080fd217
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414299064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg_
err.414299064
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2557393219
Short name T894
Test name
Test status
Simulation time 17641013 ps
CPU time 1.36 seconds
Started Jul 05 06:05:20 PM PDT 24
Finished Jul 05 06:05:21 PM PDT 24
Peak memory 219512 kb
Host smart-00a4f59e-e83e-4e89-a8a7-4ca2239faf5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557393219 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.2557393219
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3271396263
Short name T212
Test name
Test status
Simulation time 17446663 ps
CPU time 0.91 seconds
Started Jul 05 06:05:21 PM PDT 24
Finished Jul 05 06:05:23 PM PDT 24
Peak memory 217320 kb
Host smart-912045d6-68d8-4edc-97c0-653ada92d8d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271396263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.3271396263
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2784838584
Short name T964
Test name
Test status
Simulation time 90297961 ps
CPU time 1.38 seconds
Started Jul 05 06:05:20 PM PDT 24
Finished Jul 05 06:05:22 PM PDT 24
Peak memory 217452 kb
Host smart-cadea2a4-f039-46da-8c45-93beaa3f3f8a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784838584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.2784838584
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.819368829
Short name T904
Test name
Test status
Simulation time 101813335 ps
CPU time 1.84 seconds
Started Jul 05 06:05:20 PM PDT 24
Finished Jul 05 06:05:22 PM PDT 24
Peak memory 217856 kb
Host smart-6d03ecdb-f033-4cc6-8338-37e72f465530
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819368829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.819368829
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.4002839170
Short name T213
Test name
Test status
Simulation time 17099783 ps
CPU time 0.87 seconds
Started Jul 05 06:05:30 PM PDT 24
Finished Jul 05 06:05:32 PM PDT 24
Peak memory 209236 kb
Host smart-9c8efda5-7cf6-4c65-b1ff-9875eb17dc34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002839170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.4002839170
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2101134784
Short name T954
Test name
Test status
Simulation time 94222945 ps
CPU time 1 seconds
Started Jul 05 06:05:31 PM PDT 24
Finished Jul 05 06:05:32 PM PDT 24
Peak memory 209344 kb
Host smart-694b63b7-f703-40e2-810b-4223be4cfc4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101134784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.2101134784
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1801869808
Short name T963
Test name
Test status
Simulation time 96911270 ps
CPU time 1.97 seconds
Started Jul 05 06:05:23 PM PDT 24
Finished Jul 05 06:05:26 PM PDT 24
Peak memory 217564 kb
Host smart-cd89226b-6472-4636-960d-f784dc773696
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801869808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.1801869808
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3791706865
Short name T898
Test name
Test status
Simulation time 21070279 ps
CPU time 1.31 seconds
Started Jul 05 06:05:28 PM PDT 24
Finished Jul 05 06:05:30 PM PDT 24
Peak memory 217768 kb
Host smart-4de0d897-4756-47e8-a3de-cb8ad0c21f16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791706865 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.3791706865
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1736704684
Short name T944
Test name
Test status
Simulation time 51417869 ps
CPU time 1.02 seconds
Started Jul 05 06:05:30 PM PDT 24
Finished Jul 05 06:05:31 PM PDT 24
Peak memory 209316 kb
Host smart-6c18a20a-134f-4ed5-b669-079fdb8a7ef4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736704684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.1736704684
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.171172631
Short name T150
Test name
Test status
Simulation time 83849089 ps
CPU time 1.24 seconds
Started Jul 05 06:05:30 PM PDT 24
Finished Jul 05 06:05:33 PM PDT 24
Peak memory 211276 kb
Host smart-8af5d993-8eac-4ef1-9a26-b8e30bc4686c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171172631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_same_csr_outstanding.171172631
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.521273145
Short name T143
Test name
Test status
Simulation time 49343719 ps
CPU time 1.84 seconds
Started Jul 05 06:05:29 PM PDT 24
Finished Jul 05 06:05:32 PM PDT 24
Peak memory 221840 kb
Host smart-43f38a09-164d-488f-932e-409cb06f56fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521273145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg_
err.521273145
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2246601718
Short name T933
Test name
Test status
Simulation time 13638886 ps
CPU time 1.16 seconds
Started Jul 05 06:05:28 PM PDT 24
Finished Jul 05 06:05:30 PM PDT 24
Peak memory 219476 kb
Host smart-b360349c-558d-4c99-a955-ad048988ca6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246601718 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.2246601718
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.703075211
Short name T923
Test name
Test status
Simulation time 20481837 ps
CPU time 0.86 seconds
Started Jul 05 06:05:29 PM PDT 24
Finished Jul 05 06:05:31 PM PDT 24
Peak memory 209304 kb
Host smart-d6a6d690-c69d-4cbf-8d1b-05c2b5ad6d64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703075211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.703075211
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.44316273
Short name T222
Test name
Test status
Simulation time 40714219 ps
CPU time 1.43 seconds
Started Jul 05 06:05:28 PM PDT 24
Finished Jul 05 06:05:31 PM PDT 24
Peak memory 217464 kb
Host smart-052c9bb7-f1a7-4b4b-85b2-7c65150fbb77
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44316273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_
same_csr_outstanding.44316273
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.1013259406
Short name T119
Test name
Test status
Simulation time 55006582 ps
CPU time 1.91 seconds
Started Jul 05 06:05:29 PM PDT 24
Finished Jul 05 06:05:31 PM PDT 24
Peak memory 218584 kb
Host smart-163ea393-740a-4688-9872-dcc1cca07323
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013259406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.1013259406
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.327612428
Short name T924
Test name
Test status
Simulation time 193613043 ps
CPU time 1.19 seconds
Started Jul 05 06:05:29 PM PDT 24
Finished Jul 05 06:05:31 PM PDT 24
Peak memory 221848 kb
Host smart-f818d651-605d-4261-b125-99dea4f3c84d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327612428 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.327612428
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3602114583
Short name T970
Test name
Test status
Simulation time 36457975 ps
CPU time 1.28 seconds
Started Jul 05 06:05:29 PM PDT 24
Finished Jul 05 06:05:31 PM PDT 24
Peak memory 209320 kb
Host smart-7779720b-08dc-4bca-9809-fcc58f86865a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602114583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.3602114583
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1659571260
Short name T943
Test name
Test status
Simulation time 28390781 ps
CPU time 1.67 seconds
Started Jul 05 06:05:26 PM PDT 24
Finished Jul 05 06:05:28 PM PDT 24
Peak memory 217536 kb
Host smart-2b9eee30-9c9c-4937-baf0-0d73750f3fbc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659571260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.1659571260
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3832999668
Short name T876
Test name
Test status
Simulation time 23328621 ps
CPU time 1.05 seconds
Started Jul 05 06:05:28 PM PDT 24
Finished Jul 05 06:05:30 PM PDT 24
Peak memory 217780 kb
Host smart-c0d30d73-d3aa-4d9d-8bd5-2d977281cce9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832999668 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.3832999668
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.661806588
Short name T937
Test name
Test status
Simulation time 19770098 ps
CPU time 0.95 seconds
Started Jul 05 06:05:30 PM PDT 24
Finished Jul 05 06:05:31 PM PDT 24
Peak memory 209008 kb
Host smart-47dfd94a-2bee-43ee-855d-6644b10a356a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661806588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.661806588
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2207227178
Short name T122
Test name
Test status
Simulation time 42141976 ps
CPU time 1 seconds
Started Jul 05 06:05:29 PM PDT 24
Finished Jul 05 06:05:31 PM PDT 24
Peak memory 209264 kb
Host smart-545ca9c1-74e0-49c9-8363-31ac8fb7a4f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207227178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.2207227178
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.1922872077
Short name T129
Test name
Test status
Simulation time 1078411146 ps
CPU time 3.97 seconds
Started Jul 05 06:05:31 PM PDT 24
Finished Jul 05 06:05:36 PM PDT 24
Peak memory 217520 kb
Host smart-975a0c9b-0a9e-442e-8ec9-df0e7dd5ba1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922872077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.1922872077
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3242805832
Short name T208
Test name
Test status
Simulation time 59764809 ps
CPU time 1.16 seconds
Started Jul 05 06:04:29 PM PDT 24
Finished Jul 05 06:04:30 PM PDT 24
Peak memory 209312 kb
Host smart-b3fc38f8-9755-4649-8046-c5435aff8313
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242805832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.3242805832
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.198589468
Short name T911
Test name
Test status
Simulation time 33439853 ps
CPU time 1.12 seconds
Started Jul 05 06:04:31 PM PDT 24
Finished Jul 05 06:04:32 PM PDT 24
Peak memory 209076 kb
Host smart-e0e64fe1-c1e8-4a09-85c5-a9ab7a4fbff4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198589468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bash
.198589468
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1794365164
Short name T215
Test name
Test status
Simulation time 16463917 ps
CPU time 1.17 seconds
Started Jul 05 06:04:31 PM PDT 24
Finished Jul 05 06:04:33 PM PDT 24
Peak memory 211500 kb
Host smart-2f38b7a3-1114-4ed2-ba65-0d6cf5ee0966
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794365164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.1794365164
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2862627307
Short name T132
Test name
Test status
Simulation time 21317064 ps
CPU time 1.39 seconds
Started Jul 05 06:04:37 PM PDT 24
Finished Jul 05 06:04:38 PM PDT 24
Peak memory 221468 kb
Host smart-2f94a461-307f-4f60-a0c6-307b8f7f60c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862627307 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.2862627307
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3545314598
Short name T921
Test name
Test status
Simulation time 40515198 ps
CPU time 0.8 seconds
Started Jul 05 06:04:30 PM PDT 24
Finished Jul 05 06:04:31 PM PDT 24
Peak memory 209168 kb
Host smart-f6a3ef7a-4ad0-4607-86d0-6f5726916a1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545314598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.3545314598
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1432330013
Short name T882
Test name
Test status
Simulation time 51145466 ps
CPU time 1.18 seconds
Started Jul 05 06:04:30 PM PDT 24
Finished Jul 05 06:04:31 PM PDT 24
Peak memory 209128 kb
Host smart-602f2c65-a8ea-40fc-a494-7ad54345a1e5
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432330013 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.1432330013
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3464750173
Short name T912
Test name
Test status
Simulation time 1939333911 ps
CPU time 3.08 seconds
Started Jul 05 06:04:23 PM PDT 24
Finished Jul 05 06:04:26 PM PDT 24
Peak memory 209228 kb
Host smart-3aafd62b-fb8f-4c65-ab1f-884d48655b10
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464750173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.3464750173
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.2619805487
Short name T976
Test name
Test status
Simulation time 1396014955 ps
CPU time 10.03 seconds
Started Jul 05 06:09:29 PM PDT 24
Finished Jul 05 06:09:39 PM PDT 24
Peak memory 209204 kb
Host smart-8b885c31-3b4f-4991-a260-91f15687467b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619805487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.2619805487
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.4192908771
Short name T927
Test name
Test status
Simulation time 531501740 ps
CPU time 3.03 seconds
Started Jul 05 06:04:23 PM PDT 24
Finished Jul 05 06:04:26 PM PDT 24
Peak memory 210860 kb
Host smart-cb7fd2d1-3df7-4abd-8496-8a5304f57c18
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192908771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.4192908771
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4100658552
Short name T888
Test name
Test status
Simulation time 144902956 ps
CPU time 1.91 seconds
Started Jul 05 06:04:32 PM PDT 24
Finished Jul 05 06:04:34 PM PDT 24
Peak memory 217668 kb
Host smart-a63d59bd-786a-4124-ad26-3f4bdff89400
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410065
8552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4100658552
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2346837989
Short name T946
Test name
Test status
Simulation time 100789016 ps
CPU time 1.4 seconds
Started Jul 05 06:04:24 PM PDT 24
Finished Jul 05 06:04:26 PM PDT 24
Peak memory 217228 kb
Host smart-e61ec2f5-c7ff-4fc7-bdf0-820731254eca
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346837989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.2346837989
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.999797221
Short name T130
Test name
Test status
Simulation time 172964504 ps
CPU time 1.19 seconds
Started Jul 05 06:04:24 PM PDT 24
Finished Jul 05 06:04:25 PM PDT 24
Peak memory 209400 kb
Host smart-b4bafcf6-51e1-41e4-b2c0-aa6f7bc66fd2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999797221 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.999797221
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1074707072
Short name T224
Test name
Test status
Simulation time 26504239 ps
CPU time 1.07 seconds
Started Jul 05 06:04:33 PM PDT 24
Finished Jul 05 06:04:35 PM PDT 24
Peak memory 217464 kb
Host smart-65aad34b-dbaf-4d86-8403-fa56f9ddcbf8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074707072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.1074707072
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.802958860
Short name T969
Test name
Test status
Simulation time 93734290 ps
CPU time 1.53 seconds
Started Jul 05 06:04:32 PM PDT 24
Finished Jul 05 06:04:33 PM PDT 24
Peak memory 217592 kb
Host smart-05917ff5-c1c0-4655-88a2-7a9a2d3d1ccd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802958860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.802958860
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3894092047
Short name T936
Test name
Test status
Simulation time 56039267 ps
CPU time 2.53 seconds
Started Jul 05 06:04:31 PM PDT 24
Finished Jul 05 06:04:33 PM PDT 24
Peak memory 222048 kb
Host smart-23b8c7ef-e3ac-41d6-84f3-7e137b7abdea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894092047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.3894092047
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2762301396
Short name T214
Test name
Test status
Simulation time 67245581 ps
CPU time 1.09 seconds
Started Jul 05 06:04:45 PM PDT 24
Finished Jul 05 06:04:47 PM PDT 24
Peak memory 217528 kb
Host smart-eadf838a-c12a-4d9e-8bf7-8dc7f55f33e2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762301396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.2762301396
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3070687374
Short name T867
Test name
Test status
Simulation time 271607937 ps
CPU time 2.42 seconds
Started Jul 05 06:04:44 PM PDT 24
Finished Jul 05 06:04:47 PM PDT 24
Peak memory 209392 kb
Host smart-29493de7-942c-4df3-be3f-10c5376d1224
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070687374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.3070687374
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1039519588
Short name T974
Test name
Test status
Simulation time 60005316 ps
CPU time 0.97 seconds
Started Jul 05 06:04:47 PM PDT 24
Finished Jul 05 06:04:49 PM PDT 24
Peak memory 210432 kb
Host smart-cebdf071-2c71-49a9-986b-047ee21a45da
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039519588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.1039519588
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.111358320
Short name T950
Test name
Test status
Simulation time 85745629 ps
CPU time 1.37 seconds
Started Jul 05 06:04:46 PM PDT 24
Finished Jul 05 06:04:48 PM PDT 24
Peak memory 218848 kb
Host smart-98b012c2-25b6-4b49-8e7b-79a198ab59b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111358320 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.111358320
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.4265955707
Short name T217
Test name
Test status
Simulation time 54434028 ps
CPU time 0.9 seconds
Started Jul 05 06:04:44 PM PDT 24
Finished Jul 05 06:04:45 PM PDT 24
Peak memory 209288 kb
Host smart-06c13fa0-d34d-4feb-9113-d7c1a54b0a06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265955707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.4265955707
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2844241207
Short name T895
Test name
Test status
Simulation time 122678796 ps
CPU time 1.04 seconds
Started Jul 05 06:04:37 PM PDT 24
Finished Jul 05 06:04:39 PM PDT 24
Peak memory 209108 kb
Host smart-579916f7-7090-492f-b3b5-2f1e48b956a8
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844241207 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.2844241207
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1585906930
Short name T926
Test name
Test status
Simulation time 2201168337 ps
CPU time 12.25 seconds
Started Jul 05 06:04:35 PM PDT 24
Finished Jul 05 06:04:48 PM PDT 24
Peak memory 209312 kb
Host smart-03a00f56-1076-43a0-8cfb-f435d1db7d8c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585906930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.1585906930
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.4293753482
Short name T881
Test name
Test status
Simulation time 1925666013 ps
CPU time 40.7 seconds
Started Jul 05 06:04:42 PM PDT 24
Finished Jul 05 06:05:23 PM PDT 24
Peak memory 217136 kb
Host smart-5d073f4c-9933-4989-b091-d53f6bc63ffe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293753482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.4293753482
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.4248356509
Short name T920
Test name
Test status
Simulation time 86412563 ps
CPU time 1.74 seconds
Started Jul 05 06:04:40 PM PDT 24
Finished Jul 05 06:04:42 PM PDT 24
Peak memory 210604 kb
Host smart-30f20de5-b7d3-4169-8374-cf14a55c7557
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248356509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.4248356509
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.305072310
Short name T966
Test name
Test status
Simulation time 648448843 ps
CPU time 2.96 seconds
Started Jul 05 06:04:37 PM PDT 24
Finished Jul 05 06:04:40 PM PDT 24
Peak memory 217648 kb
Host smart-44809180-8583-45d9-baab-93d62002ad4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305072
310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.305072310
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1310683785
Short name T915
Test name
Test status
Simulation time 44635159 ps
CPU time 1.12 seconds
Started Jul 05 06:04:37 PM PDT 24
Finished Jul 05 06:04:38 PM PDT 24
Peak memory 209056 kb
Host smart-f30af8c1-725a-4ed7-b6f0-ec96c8773d79
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310683785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.1310683785
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3504005466
Short name T922
Test name
Test status
Simulation time 47123671 ps
CPU time 1 seconds
Started Jul 05 06:04:38 PM PDT 24
Finished Jul 05 06:04:40 PM PDT 24
Peak memory 209276 kb
Host smart-869c83c5-bb5f-4d9a-aad8-db5ec1d94c11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504005466 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.3504005466
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2316494581
Short name T965
Test name
Test status
Simulation time 187631780 ps
CPU time 1.88 seconds
Started Jul 05 06:04:44 PM PDT 24
Finished Jul 05 06:04:47 PM PDT 24
Peak memory 209276 kb
Host smart-3abffb2b-5cdf-43a8-a52c-9723c11af150
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316494581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.2316494581
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2282959024
Short name T925
Test name
Test status
Simulation time 547591884 ps
CPU time 3.42 seconds
Started Jul 05 06:04:40 PM PDT 24
Finished Jul 05 06:04:44 PM PDT 24
Peak memory 217504 kb
Host smart-26a8c116-53a0-47ad-8190-41745afe70a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282959024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.2282959024
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3017604705
Short name T114
Test name
Test status
Simulation time 251441421 ps
CPU time 1.96 seconds
Started Jul 05 06:04:41 PM PDT 24
Finished Jul 05 06:04:43 PM PDT 24
Peak memory 222172 kb
Host smart-d5288164-fd7d-49c4-a5bc-d0ecd4236ec8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017604705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.3017604705
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1934084556
Short name T209
Test name
Test status
Simulation time 57757048 ps
CPU time 1.26 seconds
Started Jul 05 06:04:51 PM PDT 24
Finished Jul 05 06:04:53 PM PDT 24
Peak memory 217440 kb
Host smart-7f209da1-ba29-476d-8b99-0afef96f2d89
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934084556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.1934084556
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1836583975
Short name T955
Test name
Test status
Simulation time 74014506 ps
CPU time 1.27 seconds
Started Jul 05 06:04:49 PM PDT 24
Finished Jul 05 06:04:51 PM PDT 24
Peak memory 217280 kb
Host smart-f49c9665-9a56-4166-8a1b-c3bb71687261
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836583975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.1836583975
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2413194276
Short name T893
Test name
Test status
Simulation time 43046710 ps
CPU time 1 seconds
Started Jul 05 06:04:43 PM PDT 24
Finished Jul 05 06:04:44 PM PDT 24
Peak memory 209664 kb
Host smart-821edf1d-1900-40c9-8012-581392b21c67
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413194276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.2413194276
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.425056128
Short name T919
Test name
Test status
Simulation time 33818023 ps
CPU time 1.14 seconds
Started Jul 05 06:04:51 PM PDT 24
Finished Jul 05 06:04:53 PM PDT 24
Peak memory 219500 kb
Host smart-2ed9cb3e-54f4-49ec-a2bc-d0d503ecf908
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425056128 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.425056128
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2091327919
Short name T218
Test name
Test status
Simulation time 14571008 ps
CPU time 0.85 seconds
Started Jul 05 06:04:45 PM PDT 24
Finished Jul 05 06:04:46 PM PDT 24
Peak memory 209304 kb
Host smart-9c263935-e2de-4c90-a916-0ba4775b06ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091327919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.2091327919
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1491457636
Short name T979
Test name
Test status
Simulation time 60804768 ps
CPU time 0.88 seconds
Started Jul 05 06:04:49 PM PDT 24
Finished Jul 05 06:04:50 PM PDT 24
Peak memory 209100 kb
Host smart-3454b977-0d4f-41df-a707-30e4aedb328b
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491457636 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.1491457636
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1879269474
Short name T962
Test name
Test status
Simulation time 1976733785 ps
CPU time 9.69 seconds
Started Jul 05 06:04:49 PM PDT 24
Finished Jul 05 06:04:59 PM PDT 24
Peak memory 209240 kb
Host smart-0af7879b-0e2a-4b61-b39e-a9d8e649fe36
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879269474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.1879269474
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.442009457
Short name T872
Test name
Test status
Simulation time 13228538814 ps
CPU time 7.65 seconds
Started Jul 05 06:04:46 PM PDT 24
Finished Jul 05 06:04:54 PM PDT 24
Peak memory 217312 kb
Host smart-271e609c-3378-44cd-a174-f29c21cac085
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442009457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.442009457
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.67977908
Short name T980
Test name
Test status
Simulation time 1325036635 ps
CPU time 3.07 seconds
Started Jul 05 06:04:46 PM PDT 24
Finished Jul 05 06:04:49 PM PDT 24
Peak memory 210736 kb
Host smart-196ca6d9-7489-4bd7-863e-c2656b16a292
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67977908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.67977908
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3382879449
Short name T178
Test name
Test status
Simulation time 147067559 ps
CPU time 2.49 seconds
Started Jul 05 06:04:45 PM PDT 24
Finished Jul 05 06:04:48 PM PDT 24
Peak memory 217584 kb
Host smart-26ce5803-859a-4615-988c-481ba3b45484
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338287
9449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3382879449
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.3633979005
Short name T877
Test name
Test status
Simulation time 55429034 ps
CPU time 1.18 seconds
Started Jul 05 06:04:46 PM PDT 24
Finished Jul 05 06:04:48 PM PDT 24
Peak memory 209220 kb
Host smart-e0fbd690-9a8e-4239-84c8-9276ab51ade8
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633979005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.3633979005
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.429166338
Short name T978
Test name
Test status
Simulation time 23799078 ps
CPU time 1.04 seconds
Started Jul 05 06:04:47 PM PDT 24
Finished Jul 05 06:04:48 PM PDT 24
Peak memory 209340 kb
Host smart-ebf813e4-73c3-4adb-8016-3f405283a52c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429166338 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.429166338
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2120142784
Short name T945
Test name
Test status
Simulation time 47354424 ps
CPU time 1.3 seconds
Started Jul 05 06:04:52 PM PDT 24
Finished Jul 05 06:04:54 PM PDT 24
Peak memory 209296 kb
Host smart-26a71bd4-4e73-4930-871b-70779e80890a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120142784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.2120142784
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3515141165
Short name T139
Test name
Test status
Simulation time 81390771 ps
CPU time 2.39 seconds
Started Jul 05 06:04:43 PM PDT 24
Finished Jul 05 06:04:46 PM PDT 24
Peak memory 217440 kb
Host smart-f24b9499-e10a-4f51-90ba-d5f820884616
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515141165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.3515141165
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3553985926
Short name T148
Test name
Test status
Simulation time 349932718 ps
CPU time 2.97 seconds
Started Jul 05 06:04:46 PM PDT 24
Finished Jul 05 06:04:50 PM PDT 24
Peak memory 217504 kb
Host smart-d470f46c-935b-422e-86dd-48e0db6e05e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553985926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.3553985926
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1277318154
Short name T885
Test name
Test status
Simulation time 17554111 ps
CPU time 1.05 seconds
Started Jul 05 06:04:53 PM PDT 24
Finished Jul 05 06:04:54 PM PDT 24
Peak memory 219536 kb
Host smart-c13c4cbd-29f6-4306-8be1-f0a0bfb1d848
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277318154 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.1277318154
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3572912421
Short name T900
Test name
Test status
Simulation time 14218715 ps
CPU time 1.01 seconds
Started Jul 05 06:04:52 PM PDT 24
Finished Jul 05 06:04:54 PM PDT 24
Peak memory 209304 kb
Host smart-f0e09f8c-1af1-4518-9001-6e71eec4a7b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572912421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.3572912421
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2025900766
Short name T917
Test name
Test status
Simulation time 48930971 ps
CPU time 1.75 seconds
Started Jul 05 06:04:51 PM PDT 24
Finished Jul 05 06:04:53 PM PDT 24
Peak memory 208728 kb
Host smart-50856145-0362-440e-8d04-f2e98ccbf9e8
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025900766 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.2025900766
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.729905476
Short name T880
Test name
Test status
Simulation time 532083892 ps
CPU time 3.02 seconds
Started Jul 05 06:04:53 PM PDT 24
Finished Jul 05 06:04:57 PM PDT 24
Peak memory 216960 kb
Host smart-190249f7-8676-467a-86c1-cc0187a076c2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729905476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.729905476
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1277480436
Short name T896
Test name
Test status
Simulation time 7478583936 ps
CPU time 40.26 seconds
Started Jul 05 06:04:53 PM PDT 24
Finished Jul 05 06:05:34 PM PDT 24
Peak memory 209232 kb
Host smart-41d756bb-1f51-4a57-b3de-563fa9a82d5f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277480436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.1277480436
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.775269275
Short name T878
Test name
Test status
Simulation time 2043963261 ps
CPU time 1.89 seconds
Started Jul 05 06:04:54 PM PDT 24
Finished Jul 05 06:04:56 PM PDT 24
Peak memory 211000 kb
Host smart-c443d4d7-4909-4df6-afb5-18030a71a00f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775269275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.775269275
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.460552914
Short name T931
Test name
Test status
Simulation time 966318564 ps
CPU time 4.84 seconds
Started Jul 05 06:04:56 PM PDT 24
Finished Jul 05 06:05:01 PM PDT 24
Peak memory 217648 kb
Host smart-b4660b0b-94af-450c-b5a8-f7ddb3476b7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460552
914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.460552914
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2689287730
Short name T985
Test name
Test status
Simulation time 91087506 ps
CPU time 1.8 seconds
Started Jul 05 06:04:54 PM PDT 24
Finished Jul 05 06:04:56 PM PDT 24
Peak memory 209248 kb
Host smart-9653a44a-7a45-486f-9efe-3fea2f29485a
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689287730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.2689287730
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1952267771
Short name T983
Test name
Test status
Simulation time 71303361 ps
CPU time 1.04 seconds
Started Jul 05 06:04:53 PM PDT 24
Finished Jul 05 06:04:55 PM PDT 24
Peak memory 209288 kb
Host smart-3e567b6f-30ae-4671-a054-662abe6e6b34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952267771 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.1952267771
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3220217096
Short name T899
Test name
Test status
Simulation time 56561507 ps
CPU time 1.12 seconds
Started Jul 05 06:04:51 PM PDT 24
Finished Jul 05 06:04:52 PM PDT 24
Peak memory 217464 kb
Host smart-60dfd9dd-686e-4306-8380-192532b0fffa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220217096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.3220217096
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1530949550
Short name T907
Test name
Test status
Simulation time 42099220 ps
CPU time 1.6 seconds
Started Jul 05 06:04:55 PM PDT 24
Finished Jul 05 06:04:58 PM PDT 24
Peak memory 217588 kb
Host smart-cc7b7211-c726-442c-b0f2-93f95461f019
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530949550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.1530949550
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1507700915
Short name T116
Test name
Test status
Simulation time 490101853 ps
CPU time 3.85 seconds
Started Jul 05 06:04:52 PM PDT 24
Finished Jul 05 06:04:57 PM PDT 24
Peak memory 217468 kb
Host smart-6c20d0b4-05b2-4c67-ae6c-42efa2d5554b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507700915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.1507700915
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3571043335
Short name T981
Test name
Test status
Simulation time 59640190 ps
CPU time 1.22 seconds
Started Jul 05 06:04:57 PM PDT 24
Finished Jul 05 06:05:00 PM PDT 24
Peak memory 218916 kb
Host smart-a7c1fe45-983d-4457-bb7f-0797aea9ef6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571043335 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.3571043335
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.276316469
Short name T968
Test name
Test status
Simulation time 52443489 ps
CPU time 1.01 seconds
Started Jul 05 06:04:58 PM PDT 24
Finished Jul 05 06:04:59 PM PDT 24
Peak memory 209300 kb
Host smart-393d1c9c-0017-4950-ad75-77aeca7c6f80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276316469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.276316469
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1829889554
Short name T932
Test name
Test status
Simulation time 1099381290 ps
CPU time 1.32 seconds
Started Jul 05 06:05:00 PM PDT 24
Finished Jul 05 06:05:02 PM PDT 24
Peak memory 208604 kb
Host smart-4151206a-0b1d-4e4f-b3e3-4afb683236ee
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829889554 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.1829889554
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.952223628
Short name T939
Test name
Test status
Simulation time 520454990 ps
CPU time 11.54 seconds
Started Jul 05 06:04:52 PM PDT 24
Finished Jul 05 06:05:04 PM PDT 24
Peak memory 217028 kb
Host smart-d6073d4c-e4fd-4cd4-83c8-f6b3816d0aba
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952223628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.952223628
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.757700151
Short name T887
Test name
Test status
Simulation time 2059976545 ps
CPU time 16.46 seconds
Started Jul 05 06:04:56 PM PDT 24
Finished Jul 05 06:05:13 PM PDT 24
Peak memory 209228 kb
Host smart-f1a8c878-9ee1-4260-b32b-c1ca0437acbf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757700151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.757700151
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.3510082077
Short name T960
Test name
Test status
Simulation time 182582598 ps
CPU time 1.35 seconds
Started Jul 05 06:04:53 PM PDT 24
Finished Jul 05 06:04:55 PM PDT 24
Peak memory 217396 kb
Host smart-5e7c4330-0388-4415-a33f-7865a97645d6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510082077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.3510082077
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.652050110
Short name T117
Test name
Test status
Simulation time 484846989 ps
CPU time 1.98 seconds
Started Jul 05 06:04:57 PM PDT 24
Finished Jul 05 06:05:00 PM PDT 24
Peak memory 217592 kb
Host smart-3f42ec23-6d69-49c8-b225-796e616e3071
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652050
110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.652050110
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1438538745
Short name T874
Test name
Test status
Simulation time 193006396 ps
CPU time 1.48 seconds
Started Jul 05 06:04:51 PM PDT 24
Finished Jul 05 06:04:53 PM PDT 24
Peak memory 209256 kb
Host smart-0374dbc0-f9af-44fb-b8b4-c3d87aaa4d03
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438538745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.1438538745
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.4212043444
Short name T903
Test name
Test status
Simulation time 96586561 ps
CPU time 1.08 seconds
Started Jul 05 06:04:53 PM PDT 24
Finished Jul 05 06:04:55 PM PDT 24
Peak memory 209308 kb
Host smart-21091765-8da8-47f7-a1eb-07e2cef69118
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212043444 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.4212043444
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3123288330
Short name T884
Test name
Test status
Simulation time 140184877 ps
CPU time 1.27 seconds
Started Jul 05 06:04:59 PM PDT 24
Finished Jul 05 06:05:00 PM PDT 24
Peak memory 209316 kb
Host smart-13880de9-8760-41ff-99a8-8331bdf47fcf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123288330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.3123288330
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.3332574990
Short name T938
Test name
Test status
Simulation time 41693551 ps
CPU time 1.5 seconds
Started Jul 05 06:04:59 PM PDT 24
Finished Jul 05 06:05:01 PM PDT 24
Peak memory 218000 kb
Host smart-2ea5dee7-0405-431e-9634-f2a4877c516e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332574990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.3332574990
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1799155892
Short name T935
Test name
Test status
Simulation time 77760822 ps
CPU time 1.41 seconds
Started Jul 05 06:05:07 PM PDT 24
Finished Jul 05 06:05:09 PM PDT 24
Peak memory 217628 kb
Host smart-934adaab-227f-44c4-8513-6f10bd1c46f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799155892 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.1799155892
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.480330281
Short name T221
Test name
Test status
Simulation time 22412146 ps
CPU time 0.93 seconds
Started Jul 05 06:05:08 PM PDT 24
Finished Jul 05 06:05:10 PM PDT 24
Peak memory 209232 kb
Host smart-2634ae0c-2624-4938-8e11-cc11a63c5cc1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480330281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.480330281
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1049498489
Short name T902
Test name
Test status
Simulation time 151571937 ps
CPU time 1.18 seconds
Started Jul 05 06:04:59 PM PDT 24
Finished Jul 05 06:05:00 PM PDT 24
Peak memory 208592 kb
Host smart-ecbf3048-3018-41b2-89dd-a014b60c9548
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049498489 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.1049498489
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3327024654
Short name T873
Test name
Test status
Simulation time 5203498634 ps
CPU time 12.95 seconds
Started Jul 05 06:05:01 PM PDT 24
Finished Jul 05 06:05:15 PM PDT 24
Peak memory 209248 kb
Host smart-89a24278-1ef7-4a0a-841c-c7ed799cd13f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327024654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.3327024654
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.3484954849
Short name T949
Test name
Test status
Simulation time 1598071652 ps
CPU time 9.74 seconds
Started Jul 05 06:04:58 PM PDT 24
Finished Jul 05 06:05:08 PM PDT 24
Peak memory 208888 kb
Host smart-7e0330af-1260-45ff-a2b0-c4110a236b91
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484954849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.3484954849
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3079922112
Short name T914
Test name
Test status
Simulation time 180604290 ps
CPU time 2.91 seconds
Started Jul 05 06:04:57 PM PDT 24
Finished Jul 05 06:05:01 PM PDT 24
Peak memory 210964 kb
Host smart-643e8084-7a4d-4106-9021-8ca53564b8d5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079922112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.3079922112
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1123391517
Short name T196
Test name
Test status
Simulation time 163957920 ps
CPU time 2.55 seconds
Started Jul 05 06:04:59 PM PDT 24
Finished Jul 05 06:05:02 PM PDT 24
Peak memory 218076 kb
Host smart-1d57c42c-b9ec-45fa-8b14-ab8d0ef3f285
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112339
1517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1123391517
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3840960020
Short name T906
Test name
Test status
Simulation time 49146317 ps
CPU time 1.09 seconds
Started Jul 05 06:04:59 PM PDT 24
Finished Jul 05 06:05:01 PM PDT 24
Peak memory 209212 kb
Host smart-ca5bb492-d978-4f5c-9bfb-75627c7fce55
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840960020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.3840960020
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.4055719833
Short name T942
Test name
Test status
Simulation time 134349345 ps
CPU time 1.45 seconds
Started Jul 05 06:05:02 PM PDT 24
Finished Jul 05 06:05:03 PM PDT 24
Peak memory 209284 kb
Host smart-bbc0a5bf-6cc3-4a93-b5ac-000fdf643ea0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055719833 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.4055719833
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.564945402
Short name T930
Test name
Test status
Simulation time 21909542 ps
CPU time 0.98 seconds
Started Jul 05 06:05:08 PM PDT 24
Finished Jul 05 06:05:10 PM PDT 24
Peak memory 209292 kb
Host smart-8c921935-24db-488c-91ce-63c1d45f2437
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564945402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
same_csr_outstanding.564945402
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3192333959
Short name T138
Test name
Test status
Simulation time 391287779 ps
CPU time 3.21 seconds
Started Jul 05 06:05:09 PM PDT 24
Finished Jul 05 06:05:13 PM PDT 24
Peak memory 218452 kb
Host smart-a86d91e3-b82f-4566-9247-cd33850106c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192333959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.3192333959
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2947307548
Short name T126
Test name
Test status
Simulation time 726804241 ps
CPU time 2.78 seconds
Started Jul 05 06:05:07 PM PDT 24
Finished Jul 05 06:05:11 PM PDT 24
Peak memory 221880 kb
Host smart-d6901e5a-44df-45dc-ad8b-4c54f37dc244
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947307548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.2947307548
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3458654194
Short name T940
Test name
Test status
Simulation time 282850042 ps
CPU time 1.62 seconds
Started Jul 05 06:05:07 PM PDT 24
Finished Jul 05 06:05:09 PM PDT 24
Peak memory 221964 kb
Host smart-fb63214c-6ff8-4b06-b2d2-9879f98a0728
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458654194 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.3458654194
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.871975465
Short name T211
Test name
Test status
Simulation time 11761694 ps
CPU time 0.94 seconds
Started Jul 05 06:05:09 PM PDT 24
Finished Jul 05 06:05:10 PM PDT 24
Peak memory 209272 kb
Host smart-f1fffa42-f682-4cb5-87c6-3fdd4bdea13b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871975465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.871975465
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3846242407
Short name T929
Test name
Test status
Simulation time 118012222 ps
CPU time 2.05 seconds
Started Jul 05 06:05:03 PM PDT 24
Finished Jul 05 06:05:06 PM PDT 24
Peak memory 209064 kb
Host smart-69e35dc0-1cd9-454e-910c-f3c5de20e314
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846242407 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.3846242407
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3585673825
Short name T984
Test name
Test status
Simulation time 1455064325 ps
CPU time 15.36 seconds
Started Jul 05 06:05:07 PM PDT 24
Finished Jul 05 06:05:24 PM PDT 24
Peak memory 209232 kb
Host smart-289bbbac-34a6-441d-beae-4676b24b3200
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585673825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.3585673825
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3896475659
Short name T982
Test name
Test status
Simulation time 2220105874 ps
CPU time 11.27 seconds
Started Jul 05 06:05:04 PM PDT 24
Finished Jul 05 06:05:15 PM PDT 24
Peak memory 216976 kb
Host smart-e5c2bad5-2117-484e-8bce-c8bf28d7f577
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896475659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.3896475659
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.20983629
Short name T869
Test name
Test status
Simulation time 389423242 ps
CPU time 1.67 seconds
Started Jul 05 06:05:08 PM PDT 24
Finished Jul 05 06:05:11 PM PDT 24
Peak memory 210776 kb
Host smart-77f72dbf-2be0-46ab-8729-ce0558d4c294
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20983629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.20983629
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3725747441
Short name T959
Test name
Test status
Simulation time 167893306 ps
CPU time 4.62 seconds
Started Jul 05 06:05:07 PM PDT 24
Finished Jul 05 06:05:13 PM PDT 24
Peak memory 217656 kb
Host smart-5f686e32-def9-4b6e-951f-f0fc4651180f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372574
7441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3725747441
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.1301848197
Short name T892
Test name
Test status
Simulation time 110616517 ps
CPU time 1.95 seconds
Started Jul 05 06:05:10 PM PDT 24
Finished Jul 05 06:05:12 PM PDT 24
Peak memory 209368 kb
Host smart-5199de86-47f0-4436-b181-8976531e94dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301848197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.1301848197
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1476116400
Short name T226
Test name
Test status
Simulation time 17175882 ps
CPU time 1.16 seconds
Started Jul 05 06:05:07 PM PDT 24
Finished Jul 05 06:05:09 PM PDT 24
Peak memory 209272 kb
Host smart-c5d23268-8fe0-4ede-97a5-4128a9ed127a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476116400 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.1476116400
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1094446700
Short name T958
Test name
Test status
Simulation time 40840385 ps
CPU time 1.28 seconds
Started Jul 05 06:05:07 PM PDT 24
Finished Jul 05 06:05:09 PM PDT 24
Peak memory 217552 kb
Host smart-7f036d86-1aa5-4a4f-9409-805cfe1bf7ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094446700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.1094446700
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.2321765508
Short name T120
Test name
Test status
Simulation time 158175739 ps
CPU time 2.49 seconds
Started Jul 05 06:05:08 PM PDT 24
Finished Jul 05 06:05:11 PM PDT 24
Peak memory 219916 kb
Host smart-39d0b3e3-630b-4436-9e75-88d363e81009
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321765508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.2321765508
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1840596371
Short name T147
Test name
Test status
Simulation time 119571332 ps
CPU time 1.87 seconds
Started Jul 05 06:05:07 PM PDT 24
Finished Jul 05 06:05:09 PM PDT 24
Peak memory 213020 kb
Host smart-d1cd3156-ca85-4501-8523-4b7e4fb56bd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840596371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.1840596371
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3689263192
Short name T137
Test name
Test status
Simulation time 63346924 ps
CPU time 2.33 seconds
Started Jul 05 06:05:15 PM PDT 24
Finished Jul 05 06:05:18 PM PDT 24
Peak memory 217752 kb
Host smart-59fe75e6-61ec-4024-bf93-1673effdafb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689263192 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.3689263192
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1859495158
Short name T165
Test name
Test status
Simulation time 15954183 ps
CPU time 1.09 seconds
Started Jul 05 06:05:16 PM PDT 24
Finished Jul 05 06:05:17 PM PDT 24
Peak memory 209264 kb
Host smart-f889adc1-a901-4af0-b6ad-11e30b1bdf3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859495158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.1859495158
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.3675480244
Short name T870
Test name
Test status
Simulation time 22346572 ps
CPU time 1.29 seconds
Started Jul 05 06:05:19 PM PDT 24
Finished Jul 05 06:05:20 PM PDT 24
Peak memory 209128 kb
Host smart-2a4eb45c-9350-48d4-88fe-be6cc31921f4
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675480244 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.3675480244
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2231204553
Short name T151
Test name
Test status
Simulation time 1820370711 ps
CPU time 5.41 seconds
Started Jul 05 06:05:08 PM PDT 24
Finished Jul 05 06:05:14 PM PDT 24
Peak memory 209252 kb
Host smart-f78f93d0-858c-472e-9220-6807c84f98d0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231204553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.2231204553
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3940418571
Short name T890
Test name
Test status
Simulation time 2042889760 ps
CPU time 5.98 seconds
Started Jul 05 06:05:07 PM PDT 24
Finished Jul 05 06:05:14 PM PDT 24
Peak memory 216948 kb
Host smart-ebf67720-283d-4d4b-b881-245d754eaf42
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940418571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.3940418571
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2223296307
Short name T909
Test name
Test status
Simulation time 183110052 ps
CPU time 1.36 seconds
Started Jul 05 06:05:08 PM PDT 24
Finished Jul 05 06:05:10 PM PDT 24
Peak memory 210652 kb
Host smart-b214877f-72bf-4d25-8f6d-7569475cce07
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223296307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.2223296307
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.645536207
Short name T141
Test name
Test status
Simulation time 966934430 ps
CPU time 6.09 seconds
Started Jul 05 06:05:14 PM PDT 24
Finished Jul 05 06:05:21 PM PDT 24
Peak memory 221668 kb
Host smart-fb802a34-fe30-427c-9ec6-685437679b5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645536
207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.645536207
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1131235924
Short name T871
Test name
Test status
Simulation time 414132592 ps
CPU time 1.93 seconds
Started Jul 05 06:05:07 PM PDT 24
Finished Jul 05 06:05:09 PM PDT 24
Peak memory 217504 kb
Host smart-ff547ded-d369-421c-af99-93ed99afd897
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131235924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.1131235924
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1558939449
Short name T971
Test name
Test status
Simulation time 187917568 ps
CPU time 2 seconds
Started Jul 05 06:05:12 PM PDT 24
Finished Jul 05 06:05:15 PM PDT 24
Peak memory 217524 kb
Host smart-aebbda0b-255a-4dde-8bd7-54f280b985e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558939449 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.1558939449
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.883059261
Short name T225
Test name
Test status
Simulation time 17953041 ps
CPU time 1.17 seconds
Started Jul 05 06:05:15 PM PDT 24
Finished Jul 05 06:05:17 PM PDT 24
Peak memory 209196 kb
Host smart-b564bde3-5f59-4d40-8b9e-594adaf85b71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883059261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
same_csr_outstanding.883059261
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.558904212
Short name T905
Test name
Test status
Simulation time 39270446 ps
CPU time 1.31 seconds
Started Jul 05 06:05:16 PM PDT 24
Finished Jul 05 06:05:18 PM PDT 24
Peak memory 217520 kb
Host smart-69911136-cf75-4353-af99-bbf6db41561b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558904212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.558904212
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.1663735759
Short name T796
Test name
Test status
Simulation time 127265271 ps
CPU time 0.95 seconds
Started Jul 05 05:32:53 PM PDT 24
Finished Jul 05 05:32:54 PM PDT 24
Peak memory 208444 kb
Host smart-5825439d-a2da-4716-933a-a9670da5476f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663735759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.1663735759
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.1303130023
Short name T670
Test name
Test status
Simulation time 877116903 ps
CPU time 12.27 seconds
Started Jul 05 05:32:50 PM PDT 24
Finished Jul 05 05:33:03 PM PDT 24
Peak memory 217724 kb
Host smart-f043cdae-9969-4ee8-b455-f804685c242c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303130023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.1303130023
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.343888396
Short name T550
Test name
Test status
Simulation time 1473197014 ps
CPU time 9.23 seconds
Started Jul 05 05:32:50 PM PDT 24
Finished Jul 05 05:33:00 PM PDT 24
Peak memory 217224 kb
Host smart-06271639-72c7-4408-bcef-39adbe98111c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343888396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.343888396
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.3434358113
Short name T288
Test name
Test status
Simulation time 7734664848 ps
CPU time 21.9 seconds
Started Jul 05 05:32:48 PM PDT 24
Finished Jul 05 05:33:11 PM PDT 24
Peak memory 218440 kb
Host smart-bac7cd84-4719-4588-8cd8-15b47366893a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434358113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.3434358113
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.1882335757
Short name T578
Test name
Test status
Simulation time 344863249 ps
CPU time 1.52 seconds
Started Jul 05 05:32:49 PM PDT 24
Finished Jul 05 05:32:52 PM PDT 24
Peak memory 217276 kb
Host smart-12c79e64-d110-422d-b3e4-fb89b79c1599
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882335757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.1
882335757
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.99362732
Short name T22
Test name
Test status
Simulation time 770436670 ps
CPU time 12.5 seconds
Started Jul 05 05:32:48 PM PDT 24
Finished Jul 05 05:33:02 PM PDT 24
Peak memory 217700 kb
Host smart-1c69b378-c290-4bbb-aca6-82d63844ce4f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99362732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p
rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_p
rog_failure.99362732
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.3949204185
Short name T268
Test name
Test status
Simulation time 639842439 ps
CPU time 10.15 seconds
Started Jul 05 05:32:49 PM PDT 24
Finished Jul 05 05:33:01 PM PDT 24
Peak memory 217040 kb
Host smart-60fef9aa-096e-465a-84b1-1ffa3cc70e15
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949204185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.3949204185
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.3673243377
Short name T754
Test name
Test status
Simulation time 481793919 ps
CPU time 12.1 seconds
Started Jul 05 05:32:49 PM PDT 24
Finished Jul 05 05:33:02 PM PDT 24
Peak memory 217124 kb
Host smart-7f7114d8-5bea-4b34-8e25-b3d7f13bf987
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673243377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
3673243377
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.4130171275
Short name T746
Test name
Test status
Simulation time 891329494 ps
CPU time 29.57 seconds
Started Jul 05 05:32:48 PM PDT 24
Finished Jul 05 05:33:18 PM PDT 24
Peak memory 250472 kb
Host smart-5518843d-8a77-49d0-b024-d749cfd327ee
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130171275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.4130171275
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.2708200137
Short name T180
Test name
Test status
Simulation time 3792337613 ps
CPU time 19.24 seconds
Started Jul 05 05:32:49 PM PDT 24
Finished Jul 05 05:33:09 PM PDT 24
Peak memory 247056 kb
Host smart-0d264f3c-35d0-48a6-9efa-d8add8c978b3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708200137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.2708200137
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.210972208
Short name T436
Test name
Test status
Simulation time 142205428 ps
CPU time 2.4 seconds
Started Jul 05 05:32:49 PM PDT 24
Finished Jul 05 05:32:53 PM PDT 24
Peak memory 217720 kb
Host smart-0d179a44-35ce-456f-aee4-17a72d9f615a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210972208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.210972208
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.1038941291
Short name T108
Test name
Test status
Simulation time 1126218313 ps
CPU time 7.81 seconds
Started Jul 05 05:33:45 PM PDT 24
Finished Jul 05 05:33:54 PM PDT 24
Peak memory 213624 kb
Host smart-e873bb53-ffea-401e-943b-f74621aa17b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038941291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.1038941291
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.317339589
Short name T101
Test name
Test status
Simulation time 800835069 ps
CPU time 12.85 seconds
Started Jul 05 05:32:52 PM PDT 24
Finished Jul 05 05:33:06 PM PDT 24
Peak memory 225588 kb
Host smart-0994b40e-43cd-472e-bfbf-82ce8d709672
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317339589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.317339589
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.462400317
Short name T656
Test name
Test status
Simulation time 1543630084 ps
CPU time 9.85 seconds
Started Jul 05 05:32:54 PM PDT 24
Finished Jul 05 05:33:04 PM PDT 24
Peak memory 225328 kb
Host smart-c1fcd52a-6454-42bb-86e4-6b7d4d669883
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462400317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_dig
est.462400317
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.132978726
Short name T748
Test name
Test status
Simulation time 239326850 ps
CPU time 6.82 seconds
Started Jul 05 05:32:50 PM PDT 24
Finished Jul 05 05:32:58 PM PDT 24
Peak memory 217708 kb
Host smart-ae855bf7-01d0-4d73-a879-7a9a39339ab9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132978726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.132978726
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.2175864521
Short name T790
Test name
Test status
Simulation time 384787517 ps
CPU time 6.23 seconds
Started Jul 05 05:32:49 PM PDT 24
Finished Jul 05 05:32:57 PM PDT 24
Peak memory 225588 kb
Host smart-39a5a38d-981e-4cd1-b0a5-e072a78540dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175864521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.2175864521
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.1122578582
Short name T745
Test name
Test status
Simulation time 226732632 ps
CPU time 23.04 seconds
Started Jul 05 05:32:50 PM PDT 24
Finished Jul 05 05:33:14 PM PDT 24
Peak memory 250452 kb
Host smart-3592553d-88ba-468f-9a54-ae9b5f192aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122578582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.1122578582
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.554987371
Short name T485
Test name
Test status
Simulation time 69207906 ps
CPU time 7.5 seconds
Started Jul 05 05:32:51 PM PDT 24
Finished Jul 05 05:33:00 PM PDT 24
Peak memory 250476 kb
Host smart-41328783-5cc0-49e3-8491-aaf1dd1d5b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554987371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.554987371
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.531970956
Short name T283
Test name
Test status
Simulation time 2824988715 ps
CPU time 53.68 seconds
Started Jul 05 05:32:49 PM PDT 24
Finished Jul 05 05:33:44 PM PDT 24
Peak memory 250520 kb
Host smart-86c691a7-d8b7-4296-a565-a00422a732ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531970956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.531970956
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.1521708237
Short name T555
Test name
Test status
Simulation time 80408385 ps
CPU time 1.14 seconds
Started Jul 05 05:32:51 PM PDT 24
Finished Jul 05 05:32:53 PM PDT 24
Peak memory 211464 kb
Host smart-1f7f45f7-65e4-4830-895a-f71c5bf8faf5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521708237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.1521708237
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.4274560708
Short name T13
Test name
Test status
Simulation time 15242839 ps
CPU time 1.07 seconds
Started Jul 05 05:33:02 PM PDT 24
Finished Jul 05 05:33:04 PM PDT 24
Peak memory 208508 kb
Host smart-1168e873-a533-4ef0-a432-13a4b33c3415
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274560708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.4274560708
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.302726974
Short name T582
Test name
Test status
Simulation time 38868216 ps
CPU time 0.85 seconds
Started Jul 05 05:32:51 PM PDT 24
Finished Jul 05 05:32:53 PM PDT 24
Peak memory 208436 kb
Host smart-5ba45823-1bb3-4bef-899c-4791f99b5f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302726974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.302726974
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.631613174
Short name T204
Test name
Test status
Simulation time 592725372 ps
CPU time 14.86 seconds
Started Jul 05 05:32:50 PM PDT 24
Finished Jul 05 05:33:07 PM PDT 24
Peak memory 225496 kb
Host smart-1c61e7d8-03e5-4d7f-92d8-4f79803d7bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631613174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.631613174
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.2494811320
Short name T400
Test name
Test status
Simulation time 929449166 ps
CPU time 6.78 seconds
Started Jul 05 05:32:59 PM PDT 24
Finished Jul 05 05:33:06 PM PDT 24
Peak memory 216744 kb
Host smart-0d2bec89-7ccf-418e-b602-bc9eb7ebf256
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494811320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.2494811320
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.4072811994
Short name T687
Test name
Test status
Simulation time 5606589954 ps
CPU time 34.48 seconds
Started Jul 05 05:37:07 PM PDT 24
Finished Jul 05 05:37:43 PM PDT 24
Peak memory 218444 kb
Host smart-399f103c-15e8-4931-8dc9-4c26bae5ee4e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072811994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.4072811994
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.998908424
Short name T287
Test name
Test status
Simulation time 393020420 ps
CPU time 5.73 seconds
Started Jul 05 05:32:57 PM PDT 24
Finished Jul 05 05:33:03 PM PDT 24
Peak memory 217232 kb
Host smart-e22b48b7-1bfa-4f86-83d7-6502501c5dc5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998908424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.998908424
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.3028427120
Short name T19
Test name
Test status
Simulation time 183358432 ps
CPU time 3.59 seconds
Started Jul 05 05:32:49 PM PDT 24
Finished Jul 05 05:32:53 PM PDT 24
Peak memory 217736 kb
Host smart-7adb4bfa-3fd4-466e-a742-4c2399a41da2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028427120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.3028427120
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.2934833566
Short name T857
Test name
Test status
Simulation time 3170735655 ps
CPU time 23.68 seconds
Started Jul 05 05:32:57 PM PDT 24
Finished Jul 05 05:33:21 PM PDT 24
Peak memory 217132 kb
Host smart-c456d300-e02b-455c-b954-481202bcbf13
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934833566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.2934833566
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.2373855987
Short name T84
Test name
Test status
Simulation time 283161218 ps
CPU time 3.34 seconds
Started Jul 05 05:32:50 PM PDT 24
Finished Jul 05 05:32:54 PM PDT 24
Peak memory 217152 kb
Host smart-1e47b7a6-01bd-4ce4-b067-059263e12138
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373855987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
2373855987
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.181682698
Short name T266
Test name
Test status
Simulation time 6399080349 ps
CPU time 33.65 seconds
Started Jul 05 05:32:48 PM PDT 24
Finished Jul 05 05:33:22 PM PDT 24
Peak memory 250520 kb
Host smart-b135ee94-1ff9-4d65-be70-e38269cc63fc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181682698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_state_failure.181682698
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.2993486276
Short name T310
Test name
Test status
Simulation time 10518839805 ps
CPU time 22.38 seconds
Started Jul 05 05:32:52 PM PDT 24
Finished Jul 05 05:33:15 PM PDT 24
Peak memory 250460 kb
Host smart-a6997810-44da-4e5f-9369-215d93b3c5da
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993486276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.2993486276
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.631147287
Short name T187
Test name
Test status
Simulation time 108122250 ps
CPU time 4.12 seconds
Started Jul 05 05:32:50 PM PDT 24
Finished Jul 05 05:32:56 PM PDT 24
Peak memory 222096 kb
Host smart-92d2b783-6ace-4669-bedc-cf0bb9fa68b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631147287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.631147287
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.1264035364
Short name T359
Test name
Test status
Simulation time 796641859 ps
CPU time 13.49 seconds
Started Jul 05 05:32:52 PM PDT 24
Finished Jul 05 05:33:07 PM PDT 24
Peak memory 214108 kb
Host smart-53c013f1-eb26-4e7a-bf08-be466dee9409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264035364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.1264035364
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.63554072
Short name T82
Test name
Test status
Simulation time 604380708 ps
CPU time 26.21 seconds
Started Jul 05 05:32:55 PM PDT 24
Finished Jul 05 05:33:22 PM PDT 24
Peak memory 266712 kb
Host smart-9145c89d-e96e-4087-8eb5-146d675788b4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63554072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.63554072
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.3309910160
Short name T321
Test name
Test status
Simulation time 323484467 ps
CPU time 7.83 seconds
Started Jul 05 05:32:58 PM PDT 24
Finished Jul 05 05:33:07 PM PDT 24
Peak memory 225504 kb
Host smart-d27f312e-0b1b-408f-a8f9-62c1460fd17b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309910160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.3309910160
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.2452445539
Short name T729
Test name
Test status
Simulation time 171304921 ps
CPU time 5.65 seconds
Started Jul 05 05:33:00 PM PDT 24
Finished Jul 05 05:33:07 PM PDT 24
Peak memory 217740 kb
Host smart-a3a14ce9-7cb1-45e1-879d-dae0eefb1ab5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452445539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.2
452445539
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.4020445271
Short name T419
Test name
Test status
Simulation time 800887230 ps
CPU time 10.3 seconds
Started Jul 05 05:32:52 PM PDT 24
Finished Jul 05 05:33:03 PM PDT 24
Peak memory 224696 kb
Host smart-11e20f9d-02d4-442f-9876-ec9025a7c216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020445271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.4020445271
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.2511428962
Short name T280
Test name
Test status
Simulation time 40040775 ps
CPU time 2.39 seconds
Started Jul 05 05:32:50 PM PDT 24
Finished Jul 05 05:32:54 PM PDT 24
Peak memory 213956 kb
Host smart-bcce520a-be44-498d-afcd-ec507899a593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511428962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.2511428962
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.1678540354
Short name T598
Test name
Test status
Simulation time 175533562 ps
CPU time 21.9 seconds
Started Jul 05 05:32:52 PM PDT 24
Finished Jul 05 05:33:14 PM PDT 24
Peak memory 250520 kb
Host smart-2e089407-ef2c-46ad-a440-2be3dca67109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678540354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.1678540354
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.483863158
Short name T558
Test name
Test status
Simulation time 178665986 ps
CPU time 6.31 seconds
Started Jul 05 05:32:52 PM PDT 24
Finished Jul 05 05:32:59 PM PDT 24
Peak memory 250004 kb
Host smart-ef5ec595-53b4-4730-ab2e-adc9638d8860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483863158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.483863158
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.195774591
Short name T92
Test name
Test status
Simulation time 37417719852 ps
CPU time 157.23 seconds
Started Jul 05 05:32:59 PM PDT 24
Finished Jul 05 05:35:37 PM PDT 24
Peak memory 222276 kb
Host smart-10df1a57-49c7-4da5-883e-a105ddd09c8a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195774591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.195774591
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2251285880
Short name T609
Test name
Test status
Simulation time 41366073 ps
CPU time 1.08 seconds
Started Jul 05 05:32:49 PM PDT 24
Finished Jul 05 05:32:52 PM PDT 24
Peak memory 211432 kb
Host smart-9d6e11e2-18ff-4338-8f64-3fd251fcd89e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251285880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.2251285880
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.3506122643
Short name T201
Test name
Test status
Simulation time 44255569 ps
CPU time 1.23 seconds
Started Jul 05 05:33:43 PM PDT 24
Finished Jul 05 05:33:46 PM PDT 24
Peak memory 208472 kb
Host smart-89c91d73-b6cf-471e-ba1e-f94a844334e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506122643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.3506122643
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.1267888718
Short name T416
Test name
Test status
Simulation time 542245412 ps
CPU time 14.43 seconds
Started Jul 05 05:33:36 PM PDT 24
Finished Jul 05 05:33:51 PM PDT 24
Peak memory 217736 kb
Host smart-922b11e3-fedb-46fc-a102-c14d7d0869f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267888718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.1267888718
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.715932983
Short name T603
Test name
Test status
Simulation time 921927134 ps
CPU time 20.63 seconds
Started Jul 05 05:33:41 PM PDT 24
Finished Jul 05 05:34:03 PM PDT 24
Peak memory 217116 kb
Host smart-30b00cb6-9a2d-4b5a-88c8-c2f7991c63fd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715932983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.715932983
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.2149137422
Short name T458
Test name
Test status
Simulation time 19584864441 ps
CPU time 129.92 seconds
Started Jul 05 05:33:44 PM PDT 24
Finished Jul 05 05:35:55 PM PDT 24
Peak memory 219436 kb
Host smart-e4c8ce57-a7cd-48c0-8877-9f2fa7feac5b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149137422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.2149137422
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.4272232358
Short name T708
Test name
Test status
Simulation time 220091114 ps
CPU time 4.75 seconds
Started Jul 05 05:33:46 PM PDT 24
Finished Jul 05 05:33:52 PM PDT 24
Peak memory 222620 kb
Host smart-6ccaa7b9-45ae-4e23-b767-e69a78625f17
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272232358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.4272232358
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.4275148339
Short name T7
Test name
Test status
Simulation time 569595875 ps
CPU time 13.36 seconds
Started Jul 05 05:33:36 PM PDT 24
Finished Jul 05 05:33:50 PM PDT 24
Peak memory 217052 kb
Host smart-360c4c2d-2168-4a8c-8463-278a2a5f2be3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275148339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.4275148339
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.1062756583
Short name T664
Test name
Test status
Simulation time 2370030206 ps
CPU time 57.83 seconds
Started Jul 05 05:33:41 PM PDT 24
Finished Jul 05 05:34:39 PM PDT 24
Peak memory 283260 kb
Host smart-07a6c92d-4dd4-478c-9a82-9b0db4deb829
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062756583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.1062756583
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.3448179731
Short name T482
Test name
Test status
Simulation time 2066223281 ps
CPU time 11.41 seconds
Started Jul 05 05:33:41 PM PDT 24
Finished Jul 05 05:33:53 PM PDT 24
Peak memory 246968 kb
Host smart-fe81cbbe-3c40-4876-8ba9-98a7390d8c9d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448179731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.3448179731
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.3459638321
Short name T626
Test name
Test status
Simulation time 30740964 ps
CPU time 2.16 seconds
Started Jul 05 05:33:43 PM PDT 24
Finished Jul 05 05:33:46 PM PDT 24
Peak memory 217784 kb
Host smart-4f31db15-c83c-4892-9806-bf45a84cb319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459638321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.3459638321
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.129055185
Short name T270
Test name
Test status
Simulation time 406518983 ps
CPU time 9.21 seconds
Started Jul 05 05:33:44 PM PDT 24
Finished Jul 05 05:33:55 PM PDT 24
Peak memory 217860 kb
Host smart-23f42bc9-a302-4f4e-a3f6-3e5d5f4191aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129055185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.129055185
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.1661007470
Short name T350
Test name
Test status
Simulation time 497202016 ps
CPU time 10.99 seconds
Started Jul 05 05:33:43 PM PDT 24
Finished Jul 05 05:33:55 PM PDT 24
Peak memory 225532 kb
Host smart-0e72f6e7-ca29-4c84-9805-da152ed037a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661007470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.1661007470
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.3333760184
Short name T734
Test name
Test status
Simulation time 302523867 ps
CPU time 7.64 seconds
Started Jul 05 05:33:44 PM PDT 24
Finished Jul 05 05:33:53 PM PDT 24
Peak memory 225524 kb
Host smart-d037a55b-26d2-40ba-8e04-cdd259106d63
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333760184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
3333760184
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.1622358155
Short name T782
Test name
Test status
Simulation time 852639721 ps
CPU time 5.44 seconds
Started Jul 05 05:33:36 PM PDT 24
Finished Jul 05 05:33:41 PM PDT 24
Peak memory 217788 kb
Host smart-f039a63f-47c4-4fc5-b0ef-1cba9be73f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622358155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.1622358155
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.3069803438
Short name T76
Test name
Test status
Simulation time 92964230 ps
CPU time 1.77 seconds
Started Jul 05 05:33:39 PM PDT 24
Finished Jul 05 05:33:41 PM PDT 24
Peak memory 217324 kb
Host smart-9487ad13-f61a-4bbd-ab6c-8e150101fe92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069803438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.3069803438
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.3038670335
Short name T442
Test name
Test status
Simulation time 752590074 ps
CPU time 21.61 seconds
Started Jul 05 05:33:35 PM PDT 24
Finished Jul 05 05:33:57 PM PDT 24
Peak memory 250472 kb
Host smart-8396689f-44a2-49bc-863d-6e6485dac2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038670335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.3038670335
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.3841509061
Short name T398
Test name
Test status
Simulation time 286800486 ps
CPU time 3.33 seconds
Started Jul 05 05:33:41 PM PDT 24
Finished Jul 05 05:33:44 PM PDT 24
Peak memory 225952 kb
Host smart-b2064afe-9600-480e-9638-ca92431addc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841509061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.3841509061
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.2292343423
Short name T386
Test name
Test status
Simulation time 19173123667 ps
CPU time 90.27 seconds
Started Jul 05 05:33:44 PM PDT 24
Finished Jul 05 05:35:16 PM PDT 24
Peak memory 280352 kb
Host smart-5922cc63-4bec-4941-b2f0-56dc7516a731
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292343423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.2292343423
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.3498868598
Short name T42
Test name
Test status
Simulation time 47915302 ps
CPU time 1.02 seconds
Started Jul 05 05:33:37 PM PDT 24
Finished Jul 05 05:33:39 PM PDT 24
Peak memory 211128 kb
Host smart-b7235313-5353-4545-ae9b-c09dbef4cc6e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498868598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.3498868598
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.646080938
Short name T583
Test name
Test status
Simulation time 21051762 ps
CPU time 1.32 seconds
Started Jul 05 05:33:45 PM PDT 24
Finished Jul 05 05:33:48 PM PDT 24
Peak memory 208668 kb
Host smart-6de86b22-21f9-4ccc-9cb7-16614cd41f26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646080938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.646080938
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.2685467824
Short name T655
Test name
Test status
Simulation time 949468221 ps
CPU time 11.94 seconds
Started Jul 05 05:33:46 PM PDT 24
Finished Jul 05 05:33:59 PM PDT 24
Peak memory 225564 kb
Host smart-bfe2cd93-b5ad-48ae-98ac-ed8f265e2b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685467824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.2685467824
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.1070362933
Short name T206
Test name
Test status
Simulation time 882569842 ps
CPU time 3.52 seconds
Started Jul 05 05:33:44 PM PDT 24
Finished Jul 05 05:33:49 PM PDT 24
Peak memory 217208 kb
Host smart-7923481b-458d-436d-9e4a-e1b4d443b57e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070362933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.1070362933
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.1504787527
Short name T531
Test name
Test status
Simulation time 27768306281 ps
CPU time 39.41 seconds
Started Jul 05 05:33:44 PM PDT 24
Finished Jul 05 05:34:25 PM PDT 24
Peak memory 218196 kb
Host smart-dba37aa5-251d-47b4-86a3-d369fc2eabfd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504787527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.1504787527
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.624321423
Short name T389
Test name
Test status
Simulation time 1846851469 ps
CPU time 8.92 seconds
Started Jul 05 05:33:46 PM PDT 24
Finished Jul 05 05:33:56 PM PDT 24
Peak memory 217732 kb
Host smart-c5fa0052-f105-406a-a19b-1c2d7e5a28a4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624321423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag
_prog_failure.624321423
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.3439453572
Short name T856
Test name
Test status
Simulation time 1109035187 ps
CPU time 14 seconds
Started Jul 05 05:33:46 PM PDT 24
Finished Jul 05 05:34:01 PM PDT 24
Peak memory 217144 kb
Host smart-d77526f6-cdd3-4953-b4ce-9c35fc238730
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439453572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.3439453572
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.691867481
Short name T324
Test name
Test status
Simulation time 1357223296 ps
CPU time 54.81 seconds
Started Jul 05 05:33:44 PM PDT 24
Finished Jul 05 05:34:40 PM PDT 24
Peak memory 266864 kb
Host smart-47dffbb2-01de-4805-9e51-cf2f2b89b330
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691867481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_state_failure.691867481
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.3772136815
Short name T771
Test name
Test status
Simulation time 2219635060 ps
CPU time 34.52 seconds
Started Jul 05 05:33:43 PM PDT 24
Finished Jul 05 05:34:18 PM PDT 24
Peak memory 250548 kb
Host smart-f43972d6-4810-493b-b7de-7d30ae52fee5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772136815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.3772136815
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.2367821568
Short name T575
Test name
Test status
Simulation time 314592470 ps
CPU time 3.12 seconds
Started Jul 05 05:33:45 PM PDT 24
Finished Jul 05 05:33:49 PM PDT 24
Peak memory 217840 kb
Host smart-64e25f6f-1135-41fe-89a5-09f85c9d966f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367821568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.2367821568
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.4047071772
Short name T188
Test name
Test status
Simulation time 7788830355 ps
CPU time 19.05 seconds
Started Jul 05 05:33:45 PM PDT 24
Finished Jul 05 05:34:05 PM PDT 24
Peak memory 225648 kb
Host smart-b7bfa31e-a9e4-4a3f-abd1-ba59561be382
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047071772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.4047071772
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.3653728777
Short name T556
Test name
Test status
Simulation time 319825611 ps
CPU time 11.32 seconds
Started Jul 05 05:33:46 PM PDT 24
Finished Jul 05 05:33:58 PM PDT 24
Peak memory 225532 kb
Host smart-8d791457-545a-4abb-8e15-8266386b7bfa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653728777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.3653728777
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.3916820124
Short name T475
Test name
Test status
Simulation time 1545146443 ps
CPU time 10.32 seconds
Started Jul 05 05:33:44 PM PDT 24
Finished Jul 05 05:33:55 PM PDT 24
Peak memory 225524 kb
Host smart-67b03e5b-d328-4b0d-9efa-5017c80ad9b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916820124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
3916820124
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.4080022396
Short name T235
Test name
Test status
Simulation time 1697287385 ps
CPU time 10.07 seconds
Started Jul 05 05:33:43 PM PDT 24
Finished Jul 05 05:33:54 PM PDT 24
Peak memory 217852 kb
Host smart-1054fccf-84e3-4f1f-b320-69fb114b580a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080022396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.4080022396
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.2469083792
Short name T705
Test name
Test status
Simulation time 72360753 ps
CPU time 3.27 seconds
Started Jul 05 05:33:45 PM PDT 24
Finished Jul 05 05:33:50 PM PDT 24
Peak memory 217140 kb
Host smart-9f843e35-2d9e-4f12-9367-7c910b498334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469083792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.2469083792
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.3238203834
Short name T111
Test name
Test status
Simulation time 678384298 ps
CPU time 36.05 seconds
Started Jul 05 05:33:43 PM PDT 24
Finished Jul 05 05:34:20 PM PDT 24
Peak memory 250528 kb
Host smart-928bb740-f652-4d49-a81c-7e92c3af4aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238203834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.3238203834
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.3914930388
Short name T612
Test name
Test status
Simulation time 302120106 ps
CPU time 7.82 seconds
Started Jul 05 05:33:43 PM PDT 24
Finished Jul 05 05:33:52 PM PDT 24
Peak memory 250476 kb
Host smart-261dd79b-fd1f-4543-a52e-d1d221b284b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914930388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.3914930388
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.4125918368
Short name T335
Test name
Test status
Simulation time 43106229 ps
CPU time 0.79 seconds
Started Jul 05 05:33:45 PM PDT 24
Finished Jul 05 05:33:47 PM PDT 24
Peak memory 208348 kb
Host smart-ab8f3155-406d-4539-9420-eaa05de328b2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125918368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.4125918368
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.3301452398
Short name T642
Test name
Test status
Simulation time 19672346 ps
CPU time 1.19 seconds
Started Jul 05 05:33:54 PM PDT 24
Finished Jul 05 05:33:55 PM PDT 24
Peak memory 208516 kb
Host smart-053b4b0a-06d9-4e2a-9f3d-eb0fabc78a59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301452398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.3301452398
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.4258764350
Short name T679
Test name
Test status
Simulation time 268191245 ps
CPU time 12.82 seconds
Started Jul 05 05:33:42 PM PDT 24
Finished Jul 05 05:33:55 PM PDT 24
Peak memory 217680 kb
Host smart-5f838429-9158-41a4-b3e2-b4d0f01ab25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258764350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.4258764350
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.1218529861
Short name T587
Test name
Test status
Simulation time 237267552 ps
CPU time 2.2 seconds
Started Jul 05 05:33:54 PM PDT 24
Finished Jul 05 05:33:57 PM PDT 24
Peak memory 216668 kb
Host smart-02cbafac-6de7-4fc1-b667-c7b24cf92baa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218529861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.1218529861
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.3687945558
Short name T480
Test name
Test status
Simulation time 40056902686 ps
CPU time 94.5 seconds
Started Jul 05 05:33:52 PM PDT 24
Finished Jul 05 05:35:27 PM PDT 24
Peak memory 218560 kb
Host smart-1bc622fd-4b43-496f-9acc-aab41a861b21
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687945558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.3687945558
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.350112462
Short name T460
Test name
Test status
Simulation time 3618892395 ps
CPU time 7.78 seconds
Started Jul 05 05:33:57 PM PDT 24
Finished Jul 05 05:34:05 PM PDT 24
Peak memory 217772 kb
Host smart-63525373-92e8-4e0b-8faf-e053ea7385da
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350112462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag
_prog_failure.350112462
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.3918255418
Short name T282
Test name
Test status
Simulation time 940179850 ps
CPU time 4.29 seconds
Started Jul 05 05:33:45 PM PDT 24
Finished Jul 05 05:33:51 PM PDT 24
Peak memory 217212 kb
Host smart-4b9f916e-db95-4645-88b5-a1ae4977c6d7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918255418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.3918255418
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.1555426903
Short name T608
Test name
Test status
Simulation time 1332096293 ps
CPU time 42.8 seconds
Started Jul 05 05:33:46 PM PDT 24
Finished Jul 05 05:34:30 PM PDT 24
Peak memory 283244 kb
Host smart-7ba7d53d-c2f3-4c13-9d9b-8bfa680ab4e7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555426903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.1555426903
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.3970829665
Short name T568
Test name
Test status
Simulation time 534986392 ps
CPU time 15.15 seconds
Started Jul 05 05:33:54 PM PDT 24
Finished Jul 05 05:34:09 PM PDT 24
Peak memory 250196 kb
Host smart-bd481ac3-73a0-4904-ba6a-48ca52d057ea
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970829665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.3970829665
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.2289445910
Short name T433
Test name
Test status
Simulation time 226629389 ps
CPU time 3.53 seconds
Started Jul 05 05:33:45 PM PDT 24
Finished Jul 05 05:33:50 PM PDT 24
Peak memory 217784 kb
Host smart-1d672063-658b-4410-b155-8bb739237fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289445910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.2289445910
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.2793502601
Short name T39
Test name
Test status
Simulation time 3198976673 ps
CPU time 19.85 seconds
Started Jul 05 05:33:53 PM PDT 24
Finished Jul 05 05:34:13 PM PDT 24
Peak memory 225652 kb
Host smart-ab78add0-18e8-48e1-be59-7d26b11d6bb1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793502601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.2793502601
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.1542370956
Short name T363
Test name
Test status
Simulation time 424717488 ps
CPU time 10.98 seconds
Started Jul 05 05:33:53 PM PDT 24
Finished Jul 05 05:34:05 PM PDT 24
Peak memory 225596 kb
Host smart-198774b3-2edd-4e96-96ce-b240bc35e6c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542370956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
1542370956
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.71360759
Short name T755
Test name
Test status
Simulation time 307025836 ps
CPU time 10.22 seconds
Started Jul 05 05:33:45 PM PDT 24
Finished Jul 05 05:33:56 PM PDT 24
Peak memory 225556 kb
Host smart-e34e77be-98b6-4f40-9c48-6549b0a47373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71360759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.71360759
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.2528130301
Short name T706
Test name
Test status
Simulation time 412533035 ps
CPU time 6.46 seconds
Started Jul 05 05:33:42 PM PDT 24
Finished Jul 05 05:33:49 PM PDT 24
Peak memory 217288 kb
Host smart-d0065e2f-afae-400a-9447-908ba9a3e91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528130301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.2528130301
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.2205708932
Short name T680
Test name
Test status
Simulation time 4315246864 ps
CPU time 23.71 seconds
Started Jul 05 05:33:43 PM PDT 24
Finished Jul 05 05:34:08 PM PDT 24
Peak memory 246224 kb
Host smart-13a64781-7af8-4360-8606-dd1497043ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205708932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.2205708932
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.3863484972
Short name T372
Test name
Test status
Simulation time 432106525 ps
CPU time 6.98 seconds
Started Jul 05 05:33:45 PM PDT 24
Finished Jul 05 05:33:54 PM PDT 24
Peak memory 250536 kb
Host smart-566e8330-8f55-4f73-9d5c-7868019d1416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863484972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.3863484972
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.1854248465
Short name T633
Test name
Test status
Simulation time 64000083809 ps
CPU time 267.12 seconds
Started Jul 05 05:33:52 PM PDT 24
Finished Jul 05 05:38:19 PM PDT 24
Peak memory 283312 kb
Host smart-e500d8ec-f7c2-487c-9a6e-e7f1e0180405
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854248465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.1854248465
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.3055844545
Short name T819
Test name
Test status
Simulation time 14564904 ps
CPU time 1.26 seconds
Started Jul 05 05:33:44 PM PDT 24
Finished Jul 05 05:33:46 PM PDT 24
Peak memory 211404 kb
Host smart-b69e0e5b-94f5-4c7c-9756-00b063444654
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055844545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.3055844545
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.2480162921
Short name T38
Test name
Test status
Simulation time 14751755 ps
CPU time 0.88 seconds
Started Jul 05 05:33:52 PM PDT 24
Finished Jul 05 05:33:53 PM PDT 24
Peak memory 208460 kb
Host smart-e8f6027f-6c3a-4398-b23f-90e9b23964bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480162921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.2480162921
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.53246411
Short name T360
Test name
Test status
Simulation time 868298586 ps
CPU time 11.04 seconds
Started Jul 05 05:33:52 PM PDT 24
Finished Jul 05 05:34:04 PM PDT 24
Peak memory 217768 kb
Host smart-017dc0b6-43fd-467a-ad9b-34fcc85c71ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53246411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.53246411
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.33441090
Short name T553
Test name
Test status
Simulation time 242188137 ps
CPU time 2.2 seconds
Started Jul 05 05:33:54 PM PDT 24
Finished Jul 05 05:33:57 PM PDT 24
Peak memory 216672 kb
Host smart-841a7609-3324-4314-bc62-40fe9d9f84a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33441090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.33441090
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.2091812831
Short name T491
Test name
Test status
Simulation time 18104391008 ps
CPU time 31.09 seconds
Started Jul 05 05:33:55 PM PDT 24
Finished Jul 05 05:34:27 PM PDT 24
Peak memory 218464 kb
Host smart-32be6eac-3007-4971-93bd-a064b61d560a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091812831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.2091812831
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.2320569671
Short name T240
Test name
Test status
Simulation time 785058151 ps
CPU time 3.77 seconds
Started Jul 05 05:33:53 PM PDT 24
Finished Jul 05 05:33:57 PM PDT 24
Peak memory 221332 kb
Host smart-00072f02-888f-4468-84ea-2b995ea9f77e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320569671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.2320569671
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.1467724275
Short name T744
Test name
Test status
Simulation time 297722723 ps
CPU time 1.59 seconds
Started Jul 05 05:33:54 PM PDT 24
Finished Jul 05 05:33:56 PM PDT 24
Peak memory 217116 kb
Host smart-f974ab0e-073d-4e3a-9f79-6f72b1755f80
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467724275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.1467724275
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.92267862
Short name T162
Test name
Test status
Simulation time 2275629174 ps
CPU time 52.37 seconds
Started Jul 05 05:33:56 PM PDT 24
Finished Jul 05 05:34:49 PM PDT 24
Peak memory 250496 kb
Host smart-1f7d85d5-6e61-46fd-bc80-954fb62b60da
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92267862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag
_state_failure.92267862
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.125212766
Short name T532
Test name
Test status
Simulation time 542316971 ps
CPU time 14.77 seconds
Started Jul 05 05:33:57 PM PDT 24
Finished Jul 05 05:34:13 PM PDT 24
Peak memory 250484 kb
Host smart-8a4f2948-fe96-4574-892f-fb27b9ab91c1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125212766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_
jtag_state_post_trans.125212766
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.2499930244
Short name T427
Test name
Test status
Simulation time 111824383 ps
CPU time 1.84 seconds
Started Jul 05 05:33:54 PM PDT 24
Finished Jul 05 05:33:57 PM PDT 24
Peak memory 217740 kb
Host smart-43524432-e293-412a-98ba-46e904b0009e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499930244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.2499930244
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.3054011803
Short name T193
Test name
Test status
Simulation time 288664466 ps
CPU time 9.03 seconds
Started Jul 05 05:33:54 PM PDT 24
Finished Jul 05 05:34:03 PM PDT 24
Peak memory 225584 kb
Host smart-0f4e3d2e-749a-4a9a-aff2-f6bccf973cec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054011803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.3054011803
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.453706837
Short name T727
Test name
Test status
Simulation time 1033427407 ps
CPU time 11 seconds
Started Jul 05 05:33:57 PM PDT 24
Finished Jul 05 05:34:09 PM PDT 24
Peak memory 225504 kb
Host smart-00f7152b-3fb6-4bf1-9029-c90d2669dfc7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453706837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_di
gest.453706837
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.3250092965
Short name T730
Test name
Test status
Simulation time 1424018447 ps
CPU time 10.11 seconds
Started Jul 05 05:33:56 PM PDT 24
Finished Jul 05 05:34:06 PM PDT 24
Peak memory 217776 kb
Host smart-b59a6af7-3036-4f26-b749-a75d3f8256d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250092965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
3250092965
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.3996146773
Short name T233
Test name
Test status
Simulation time 2330270106 ps
CPU time 9.56 seconds
Started Jul 05 05:33:52 PM PDT 24
Finished Jul 05 05:34:02 PM PDT 24
Peak memory 225648 kb
Host smart-57c0695b-e2a1-4988-a7a5-08dedaeffc87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996146773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.3996146773
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.2373821452
Short name T559
Test name
Test status
Simulation time 153577698 ps
CPU time 2.43 seconds
Started Jul 05 05:33:56 PM PDT 24
Finished Jul 05 05:33:59 PM PDT 24
Peak memory 217208 kb
Host smart-10ecabbf-5e37-426b-ab06-4f5c85630acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373821452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.2373821452
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.1993630964
Short name T630
Test name
Test status
Simulation time 1032205805 ps
CPU time 28.29 seconds
Started Jul 05 05:33:57 PM PDT 24
Finished Jul 05 05:34:25 PM PDT 24
Peak memory 247220 kb
Host smart-56720ee8-05fa-4e7d-ace1-9997df17e4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993630964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.1993630964
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.2952669134
Short name T281
Test name
Test status
Simulation time 473217949 ps
CPU time 7.72 seconds
Started Jul 05 05:33:55 PM PDT 24
Finished Jul 05 05:34:04 PM PDT 24
Peak memory 250520 kb
Host smart-1ae677b8-2e15-4ab4-b39a-93fc2106738a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952669134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.2952669134
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.3501960563
Short name T392
Test name
Test status
Simulation time 27297907374 ps
CPU time 147.28 seconds
Started Jul 05 05:33:54 PM PDT 24
Finished Jul 05 05:36:22 PM PDT 24
Peak memory 267360 kb
Host smart-6d5b5917-f229-4183-9ecd-2260f1f8a3f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501960563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.3501960563
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.4156598375
Short name T158
Test name
Test status
Simulation time 48751747310 ps
CPU time 286.31 seconds
Started Jul 05 05:33:55 PM PDT 24
Finished Jul 05 05:38:42 PM PDT 24
Peak memory 283496 kb
Host smart-2331dedd-8074-434b-9abc-409a83ade92a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4156598375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.4156598375
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.1599008470
Short name T693
Test name
Test status
Simulation time 16824799 ps
CPU time 0.83 seconds
Started Jul 05 05:33:58 PM PDT 24
Finished Jul 05 05:33:59 PM PDT 24
Peak memory 207820 kb
Host smart-96b2bf10-3414-41ac-b00b-d64ed9a04784
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599008470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.1599008470
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.408979865
Short name T364
Test name
Test status
Simulation time 30268590 ps
CPU time 1.07 seconds
Started Jul 05 05:34:01 PM PDT 24
Finished Jul 05 05:34:02 PM PDT 24
Peak memory 208548 kb
Host smart-9ae901b1-ca1d-4389-b810-0b97aff8ea45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408979865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.408979865
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.1286815337
Short name T844
Test name
Test status
Simulation time 417576847 ps
CPU time 18.81 seconds
Started Jul 05 05:33:52 PM PDT 24
Finished Jul 05 05:34:12 PM PDT 24
Peak memory 225572 kb
Host smart-f6ccb35c-4413-491c-8ba9-19d6f2ce8c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286815337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.1286815337
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.3974902199
Short name T10
Test name
Test status
Simulation time 654142593 ps
CPU time 9.98 seconds
Started Jul 05 05:34:02 PM PDT 24
Finished Jul 05 05:34:14 PM PDT 24
Peak memory 217124 kb
Host smart-13fd6eca-46b2-478e-9e91-20ebf7cdffaa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974902199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.3974902199
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.3836544567
Short name T418
Test name
Test status
Simulation time 6141865384 ps
CPU time 29 seconds
Started Jul 05 05:34:01 PM PDT 24
Finished Jul 05 05:34:30 PM PDT 24
Peak memory 217804 kb
Host smart-205858b1-94c0-40fe-bead-0165e19d5e3c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836544567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.3836544567
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.3327297532
Short name T792
Test name
Test status
Simulation time 520662704 ps
CPU time 14.62 seconds
Started Jul 05 05:33:59 PM PDT 24
Finished Jul 05 05:34:14 PM PDT 24
Peak memory 223944 kb
Host smart-f406518e-40ef-46fa-b08b-8218bf7c63e4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327297532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.3327297532
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.1455606538
Short name T381
Test name
Test status
Simulation time 12201994007 ps
CPU time 15.21 seconds
Started Jul 05 05:34:02 PM PDT 24
Finished Jul 05 05:34:18 PM PDT 24
Peak memory 217124 kb
Host smart-04486714-6fc8-4b6a-ba83-35f07a486d92
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455606538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.1455606538
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.2885506766
Short name T379
Test name
Test status
Simulation time 2130308889 ps
CPU time 52.29 seconds
Started Jul 05 05:34:02 PM PDT 24
Finished Jul 05 05:34:56 PM PDT 24
Peak memory 266856 kb
Host smart-b54f671f-7987-45db-9bd2-40ab9f88e456
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885506766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.2885506766
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.2579823549
Short name T245
Test name
Test status
Simulation time 3388559782 ps
CPU time 15.27 seconds
Started Jul 05 05:34:02 PM PDT 24
Finished Jul 05 05:34:18 PM PDT 24
Peak memory 245884 kb
Host smart-d352b40a-2b20-4cdb-aa5e-d32fb981826f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579823549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.2579823549
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.3678765486
Short name T763
Test name
Test status
Simulation time 135118974 ps
CPU time 3.28 seconds
Started Jul 05 05:33:55 PM PDT 24
Finished Jul 05 05:33:59 PM PDT 24
Peak memory 217772 kb
Host smart-94737761-2479-4145-b476-2b11667a05b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678765486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.3678765486
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.1044539420
Short name T428
Test name
Test status
Simulation time 236881309 ps
CPU time 7.28 seconds
Started Jul 05 05:34:04 PM PDT 24
Finished Jul 05 05:34:13 PM PDT 24
Peak memory 225528 kb
Host smart-7177f6c6-68c6-4c03-bad4-9aa50c53fef7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044539420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.1044539420
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.681098744
Short name T662
Test name
Test status
Simulation time 3483177561 ps
CPU time 5.51 seconds
Started Jul 05 05:34:02 PM PDT 24
Finished Jul 05 05:34:09 PM PDT 24
Peak memory 217800 kb
Host smart-34ed95fc-1077-48c8-b5dd-45fc0d25a7c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681098744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.681098744
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.841897380
Short name T383
Test name
Test status
Simulation time 2549670870 ps
CPU time 7.77 seconds
Started Jul 05 05:33:52 PM PDT 24
Finished Jul 05 05:34:00 PM PDT 24
Peak memory 217852 kb
Host smart-0af693eb-125e-47dd-adc5-f457e036cbaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841897380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.841897380
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.170480749
Short name T860
Test name
Test status
Simulation time 47302648 ps
CPU time 2.06 seconds
Started Jul 05 05:33:55 PM PDT 24
Finished Jul 05 05:33:58 PM PDT 24
Peak memory 217204 kb
Host smart-34ac26f9-5a37-4ac3-b225-d9fa0c45f8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170480749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.170480749
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.721350091
Short name T16
Test name
Test status
Simulation time 1290349460 ps
CPU time 29.95 seconds
Started Jul 05 05:33:51 PM PDT 24
Finished Jul 05 05:34:22 PM PDT 24
Peak memory 250568 kb
Host smart-6d3d2153-69ff-4027-822c-b4a78e6f84da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721350091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.721350091
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.1574646165
Short name T852
Test name
Test status
Simulation time 47751951 ps
CPU time 3.04 seconds
Started Jul 05 05:33:53 PM PDT 24
Finished Jul 05 05:33:56 PM PDT 24
Peak memory 222124 kb
Host smart-43cdb4df-322d-4a31-852e-a91fc84d1adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574646165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.1574646165
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.659384645
Short name T750
Test name
Test status
Simulation time 6026278455 ps
CPU time 131.76 seconds
Started Jul 05 05:34:00 PM PDT 24
Finished Jul 05 05:36:13 PM PDT 24
Peak memory 220972 kb
Host smart-bc2ba7ab-4592-48e7-9a97-539381673825
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659384645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.659384645
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.3323697573
Short name T757
Test name
Test status
Simulation time 52413945 ps
CPU time 0.78 seconds
Started Jul 05 05:33:58 PM PDT 24
Finished Jul 05 05:34:00 PM PDT 24
Peak memory 208248 kb
Host smart-ae41cccc-a1c6-4a9b-b17f-a859a2ef14bf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323697573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.3323697573
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.3514251602
Short name T413
Test name
Test status
Simulation time 64840212 ps
CPU time 0.94 seconds
Started Jul 05 05:34:02 PM PDT 24
Finished Jul 05 05:34:05 PM PDT 24
Peak memory 208532 kb
Host smart-9660ce8c-cf36-440c-8172-8aede55e446b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514251602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.3514251602
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.617541339
Short name T861
Test name
Test status
Simulation time 298225061 ps
CPU time 11.58 seconds
Started Jul 05 05:34:01 PM PDT 24
Finished Jul 05 05:34:13 PM PDT 24
Peak memory 217684 kb
Host smart-2a5978b3-c49b-49e2-8135-71731e2f2530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617541339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.617541339
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.2835527395
Short name T207
Test name
Test status
Simulation time 497811594 ps
CPU time 3.69 seconds
Started Jul 05 05:34:00 PM PDT 24
Finished Jul 05 05:34:04 PM PDT 24
Peak memory 216672 kb
Host smart-d55cd951-664b-4e80-8e65-f11c4dfd1a29
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835527395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.2835527395
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.2526726554
Short name T6
Test name
Test status
Simulation time 2131461120 ps
CPU time 65.26 seconds
Started Jul 05 05:33:59 PM PDT 24
Finished Jul 05 05:35:05 PM PDT 24
Peak memory 217684 kb
Host smart-568bad3d-a8f9-42ba-86ca-b432c67bd7af
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526726554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.2526726554
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.1031295244
Short name T604
Test name
Test status
Simulation time 226635132 ps
CPU time 6.31 seconds
Started Jul 05 05:34:01 PM PDT 24
Finished Jul 05 05:34:08 PM PDT 24
Peak memory 217752 kb
Host smart-73a0f218-4c4d-4280-97f8-316c629460e3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031295244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.1031295244
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.775726770
Short name T828
Test name
Test status
Simulation time 2213108850 ps
CPU time 5.57 seconds
Started Jul 05 05:34:04 PM PDT 24
Finished Jul 05 05:34:11 PM PDT 24
Peak memory 217212 kb
Host smart-4e240744-9c6f-4494-8603-c367768790cf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775726770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke.
775726770
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.2461599206
Short name T171
Test name
Test status
Simulation time 1277169125 ps
CPU time 45.67 seconds
Started Jul 05 05:34:03 PM PDT 24
Finished Jul 05 05:34:51 PM PDT 24
Peak memory 252368 kb
Host smart-4c41698f-3d51-4543-bdfd-db662aebd914
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461599206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.2461599206
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.1376298654
Short name T607
Test name
Test status
Simulation time 1176917798 ps
CPU time 13.69 seconds
Started Jul 05 05:34:00 PM PDT 24
Finished Jul 05 05:34:14 PM PDT 24
Peak memory 247152 kb
Host smart-5c2b0b32-37ac-4d7d-b1db-011f552a8b7a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376298654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.1376298654
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.4147921821
Short name T45
Test name
Test status
Simulation time 453142168 ps
CPU time 3.78 seconds
Started Jul 05 05:34:01 PM PDT 24
Finished Jul 05 05:34:05 PM PDT 24
Peak memory 217784 kb
Host smart-4215da0b-f515-4f48-9db3-821e0964efce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147921821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.4147921821
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.4234970183
Short name T302
Test name
Test status
Simulation time 338917584 ps
CPU time 14.13 seconds
Started Jul 05 05:34:04 PM PDT 24
Finished Jul 05 05:34:20 PM PDT 24
Peak memory 225588 kb
Host smart-179b58af-6f43-442a-b3f3-68d10062899a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234970183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.4234970183
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.879867375
Short name T463
Test name
Test status
Simulation time 1761032578 ps
CPU time 10.22 seconds
Started Jul 05 05:34:02 PM PDT 24
Finished Jul 05 05:34:13 PM PDT 24
Peak memory 225516 kb
Host smart-5ac9f6d4-7047-488b-9228-9a2837140aea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879867375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.879867375
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.1172604430
Short name T685
Test name
Test status
Simulation time 41301740 ps
CPU time 3.26 seconds
Started Jul 05 05:34:02 PM PDT 24
Finished Jul 05 05:34:08 PM PDT 24
Peak memory 217204 kb
Host smart-e28fc425-7250-4d6d-9a2c-184bd83bfa38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172604430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.1172604430
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.1370082373
Short name T371
Test name
Test status
Simulation time 1491776186 ps
CPU time 25.59 seconds
Started Jul 05 05:34:04 PM PDT 24
Finished Jul 05 05:34:31 PM PDT 24
Peak memory 250540 kb
Host smart-369b3196-a9fe-4624-ba30-b90f42aeb1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370082373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.1370082373
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.2703729777
Short name T365
Test name
Test status
Simulation time 314034562 ps
CPU time 10.85 seconds
Started Jul 05 05:34:00 PM PDT 24
Finished Jul 05 05:34:12 PM PDT 24
Peak memory 250532 kb
Host smart-9f38ee5d-ff09-4675-9364-8c47eceba9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703729777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.2703729777
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.1090380039
Short name T174
Test name
Test status
Simulation time 5682665568 ps
CPU time 193.36 seconds
Started Jul 05 05:34:03 PM PDT 24
Finished Jul 05 05:37:18 PM PDT 24
Peak memory 294320 kb
Host smart-7f860e0e-8e5a-43b3-8c01-d99f2969e6d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090380039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.1090380039
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.2763974276
Short name T155
Test name
Test status
Simulation time 167464719965 ps
CPU time 1198.59 seconds
Started Jul 05 05:34:01 PM PDT 24
Finished Jul 05 05:54:01 PM PDT 24
Peak memory 522172 kb
Host smart-12c63107-de0e-4bf4-8358-a6f1141a7477
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2763974276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all_with_rand_reset.2763974276
Directory /workspace/15.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.2198182846
Short name T415
Test name
Test status
Simulation time 55666065 ps
CPU time 1.12 seconds
Started Jul 05 05:34:00 PM PDT 24
Finished Jul 05 05:34:01 PM PDT 24
Peak memory 211436 kb
Host smart-37304a38-de38-4599-88a8-0e381b678866
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198182846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.2198182846
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.3692740689
Short name T838
Test name
Test status
Simulation time 65586701 ps
CPU time 0.87 seconds
Started Jul 05 05:34:19 PM PDT 24
Finished Jul 05 05:34:21 PM PDT 24
Peak memory 208528 kb
Host smart-c73ddd5c-cd83-4cca-bf82-139150f9afbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692740689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.3692740689
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.1921301672
Short name T106
Test name
Test status
Simulation time 1283641004 ps
CPU time 8.6 seconds
Started Jul 05 05:34:02 PM PDT 24
Finished Jul 05 05:34:11 PM PDT 24
Peak memory 217792 kb
Host smart-93c06ddd-35c1-4ec5-99e3-ed3a635a1262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921301672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.1921301672
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.182852703
Short name T766
Test name
Test status
Simulation time 86475591 ps
CPU time 2.92 seconds
Started Jul 05 05:34:10 PM PDT 24
Finished Jul 05 05:34:14 PM PDT 24
Peak memory 217128 kb
Host smart-ba1d53ae-dcf8-4df4-8ed6-ca83fc759019
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182852703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.182852703
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.1750712400
Short name T326
Test name
Test status
Simulation time 1646090573 ps
CPU time 41.65 seconds
Started Jul 05 05:34:10 PM PDT 24
Finished Jul 05 05:34:52 PM PDT 24
Peak memory 217808 kb
Host smart-41e18bd8-aa07-4b71-a458-2061067cd4a0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750712400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.1750712400
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.2669213956
Short name T502
Test name
Test status
Simulation time 482175263 ps
CPU time 4.51 seconds
Started Jul 05 05:34:09 PM PDT 24
Finished Jul 05 05:34:15 PM PDT 24
Peak memory 221200 kb
Host smart-abf27222-2f1c-40a2-bfae-09f0bc87d672
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669213956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.2669213956
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.701399240
Short name T537
Test name
Test status
Simulation time 100727498 ps
CPU time 2.11 seconds
Started Jul 05 05:34:03 PM PDT 24
Finished Jul 05 05:34:06 PM PDT 24
Peak memory 217152 kb
Host smart-77573d0b-9862-4187-920f-82dc04c23259
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701399240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke.
701399240
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.2131855722
Short name T567
Test name
Test status
Simulation time 2835733697 ps
CPU time 69.48 seconds
Started Jul 05 05:34:08 PM PDT 24
Finished Jul 05 05:35:18 PM PDT 24
Peak memory 283244 kb
Host smart-ed6ac714-15ba-4cc8-9e3b-be42cd2b59c9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131855722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.2131855722
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.1667145816
Short name T725
Test name
Test status
Simulation time 392401752 ps
CPU time 13.48 seconds
Started Jul 05 05:34:10 PM PDT 24
Finished Jul 05 05:34:25 PM PDT 24
Peak memory 222656 kb
Host smart-6a5acbec-3e9f-4832-978e-fb71d6386b0a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667145816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.1667145816
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.4031502854
Short name T123
Test name
Test status
Simulation time 34351299 ps
CPU time 2.26 seconds
Started Jul 05 05:33:59 PM PDT 24
Finished Jul 05 05:34:02 PM PDT 24
Peak memory 221596 kb
Host smart-3a259523-3e10-452d-9c88-380cddb3e4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031502854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.4031502854
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.3536460931
Short name T510
Test name
Test status
Simulation time 1619463469 ps
CPU time 18.05 seconds
Started Jul 05 05:34:06 PM PDT 24
Finished Jul 05 05:34:25 PM PDT 24
Peak memory 225512 kb
Host smart-cb7007cb-798e-46cf-a0a3-016e5c7f69f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536460931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.3536460931
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.2219977731
Short name T806
Test name
Test status
Simulation time 1561973162 ps
CPU time 16.2 seconds
Started Jul 05 05:34:09 PM PDT 24
Finished Jul 05 05:34:26 PM PDT 24
Peak memory 225524 kb
Host smart-0c365ea2-000e-41e0-b6bf-3a4e3f26a12b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219977731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.2219977731
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.2361152557
Short name T382
Test name
Test status
Simulation time 584659222 ps
CPU time 12.79 seconds
Started Jul 05 05:34:08 PM PDT 24
Finished Jul 05 05:34:22 PM PDT 24
Peak memory 225488 kb
Host smart-c95ee86a-6206-4850-9478-17e661467900
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361152557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
2361152557
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.1210281926
Short name T494
Test name
Test status
Simulation time 251862412 ps
CPU time 10.64 seconds
Started Jul 05 05:34:04 PM PDT 24
Finished Jul 05 05:34:16 PM PDT 24
Peak memory 224824 kb
Host smart-d5539a97-02a9-4581-91c7-3373a72c6451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210281926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.1210281926
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.3585811848
Short name T692
Test name
Test status
Simulation time 340949194 ps
CPU time 1.78 seconds
Started Jul 05 05:34:03 PM PDT 24
Finished Jul 05 05:34:07 PM PDT 24
Peak memory 217204 kb
Host smart-f18354fb-fea8-4ca0-8acb-25dce2b0889f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585811848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.3585811848
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.3527453993
Short name T276
Test name
Test status
Simulation time 448623720 ps
CPU time 22.9 seconds
Started Jul 05 05:34:04 PM PDT 24
Finished Jul 05 05:34:28 PM PDT 24
Peak memory 250452 kb
Host smart-dc137351-7ea2-4e0a-80b3-714fd0842d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527453993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.3527453993
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.408674971
Short name T327
Test name
Test status
Simulation time 563308417 ps
CPU time 7.91 seconds
Started Jul 05 05:34:00 PM PDT 24
Finished Jul 05 05:34:08 PM PDT 24
Peak memory 250464 kb
Host smart-b53c2867-d470-4236-9bb8-c8c0b51c9997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408674971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.408674971
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.2187273635
Short name T446
Test name
Test status
Simulation time 18919936932 ps
CPU time 178.49 seconds
Started Jul 05 05:34:09 PM PDT 24
Finished Jul 05 05:37:09 PM PDT 24
Peak memory 283088 kb
Host smart-2fd76b56-d240-4264-91f1-0f127c7ab7f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187273635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.2187273635
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.2627495827
Short name T492
Test name
Test status
Simulation time 11982999 ps
CPU time 0.78 seconds
Started Jul 05 05:34:01 PM PDT 24
Finished Jul 05 05:34:03 PM PDT 24
Peak memory 208528 kb
Host smart-8437ea2e-6e18-4958-aba4-dfd92d899428
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627495827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.2627495827
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.3018272633
Short name T864
Test name
Test status
Simulation time 34716573 ps
CPU time 1.49 seconds
Started Jul 05 05:34:07 PM PDT 24
Finished Jul 05 05:34:09 PM PDT 24
Peak memory 208548 kb
Host smart-34c78c30-a573-4b44-b781-4f88de69e70e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018272633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.3018272633
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.3475839163
Short name T715
Test name
Test status
Simulation time 475805402 ps
CPU time 20.67 seconds
Started Jul 05 05:34:08 PM PDT 24
Finished Jul 05 05:34:30 PM PDT 24
Peak memory 217796 kb
Host smart-c006bdae-3db8-4cb8-8430-8a3bbbf8637b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475839163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.3475839163
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.932564500
Short name T319
Test name
Test status
Simulation time 487895429 ps
CPU time 12.41 seconds
Started Jul 05 05:34:19 PM PDT 24
Finished Jul 05 05:34:32 PM PDT 24
Peak memory 217208 kb
Host smart-b963fbf9-1645-4218-9218-b87c955df165
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932564500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.932564500
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.2545161594
Short name T647
Test name
Test status
Simulation time 31980716424 ps
CPU time 33.02 seconds
Started Jul 05 05:34:11 PM PDT 24
Finished Jul 05 05:34:44 PM PDT 24
Peak memory 218120 kb
Host smart-4b5b7c9a-4087-4040-bdee-440e68fdc5e3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545161594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.2545161594
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.419039944
Short name T414
Test name
Test status
Simulation time 2330648895 ps
CPU time 2.65 seconds
Started Jul 05 05:34:11 PM PDT 24
Finished Jul 05 05:34:14 PM PDT 24
Peak memory 221008 kb
Host smart-41c58d07-78d5-4757-acd7-9fdb215b5d34
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419039944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag
_prog_failure.419039944
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.313229803
Short name T538
Test name
Test status
Simulation time 164936120 ps
CPU time 6.06 seconds
Started Jul 05 05:34:06 PM PDT 24
Finished Jul 05 05:34:13 PM PDT 24
Peak memory 217148 kb
Host smart-3874d1b4-d935-4650-8300-5193b9e9c6af
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313229803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke.
313229803
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.698665700
Short name T407
Test name
Test status
Simulation time 2183765511 ps
CPU time 16.44 seconds
Started Jul 05 05:34:09 PM PDT 24
Finished Jul 05 05:34:26 PM PDT 24
Peak memory 225924 kb
Host smart-48ed9b3a-0c37-49ea-8876-526e0519b6d0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698665700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_
jtag_state_post_trans.698665700
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.1494207380
Short name T847
Test name
Test status
Simulation time 1272773664 ps
CPU time 16.93 seconds
Started Jul 05 05:34:10 PM PDT 24
Finished Jul 05 05:34:27 PM PDT 24
Peak memory 225508 kb
Host smart-388cfb86-ce71-4e05-9dca-8943d7a38b00
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494207380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.1494207380
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.2955561496
Short name T668
Test name
Test status
Simulation time 942187484 ps
CPU time 8.63 seconds
Started Jul 05 05:34:12 PM PDT 24
Finished Jul 05 05:34:21 PM PDT 24
Peak memory 223804 kb
Host smart-b5e76b02-e8ef-4b4b-9811-45854fbf600d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955561496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
2955561496
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.579022844
Short name T641
Test name
Test status
Simulation time 2518821519 ps
CPU time 8.98 seconds
Started Jul 05 05:34:13 PM PDT 24
Finished Jul 05 05:34:22 PM PDT 24
Peak memory 224896 kb
Host smart-dabb1185-84e6-4943-870b-18d6f1aff95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579022844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.579022844
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.4290536192
Short name T547
Test name
Test status
Simulation time 309839946 ps
CPU time 2.06 seconds
Started Jul 05 05:34:10 PM PDT 24
Finished Jul 05 05:34:13 PM PDT 24
Peak memory 213632 kb
Host smart-f5698a9d-1bca-455b-8481-21ba73b26ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290536192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.4290536192
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.3172349612
Short name T833
Test name
Test status
Simulation time 961383731 ps
CPU time 29.27 seconds
Started Jul 05 05:34:08 PM PDT 24
Finished Jul 05 05:34:39 PM PDT 24
Peak memory 250540 kb
Host smart-0f33eefe-ecba-402f-adb7-0cf1dd0873b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172349612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.3172349612
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.1969084975
Short name T586
Test name
Test status
Simulation time 201934153 ps
CPU time 8.86 seconds
Started Jul 05 05:34:10 PM PDT 24
Finished Jul 05 05:34:20 PM PDT 24
Peak memory 250536 kb
Host smart-8bea775f-92d4-4911-bdf9-2ea987990af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969084975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.1969084975
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.1592046482
Short name T497
Test name
Test status
Simulation time 208637180911 ps
CPU time 250.68 seconds
Started Jul 05 05:34:10 PM PDT 24
Finished Jul 05 05:38:22 PM PDT 24
Peak memory 299760 kb
Host smart-50732f3e-3ed2-4bee-ae41-fa4db36f6261
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592046482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.1592046482
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.2826359480
Short name T600
Test name
Test status
Simulation time 20410416 ps
CPU time 1.21 seconds
Started Jul 05 05:34:10 PM PDT 24
Finished Jul 05 05:34:12 PM PDT 24
Peak memory 217224 kb
Host smart-7df48d25-1672-4854-a2df-6d02497a4649
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826359480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.2826359480
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.458344883
Short name T716
Test name
Test status
Simulation time 55681474 ps
CPU time 0.89 seconds
Started Jul 05 05:34:18 PM PDT 24
Finished Jul 05 05:34:20 PM PDT 24
Peak memory 208452 kb
Host smart-70da7587-1a0a-4a26-9096-67eccc42b7ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458344883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.458344883
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.1700821540
Short name T574
Test name
Test status
Simulation time 1803550505 ps
CPU time 20.44 seconds
Started Jul 05 05:34:19 PM PDT 24
Finished Jul 05 05:34:40 PM PDT 24
Peak memory 225568 kb
Host smart-5d53dfbd-8e8a-4a48-9168-0c950b1f5567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700821540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.1700821540
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.3537552490
Short name T32
Test name
Test status
Simulation time 483011869 ps
CPU time 11.77 seconds
Started Jul 05 05:34:10 PM PDT 24
Finished Jul 05 05:34:22 PM PDT 24
Peak memory 217208 kb
Host smart-dda748ce-bdfd-49a0-b4a4-d2715ccd3df5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537552490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.3537552490
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.3875999563
Short name T825
Test name
Test status
Simulation time 10066256388 ps
CPU time 30.99 seconds
Started Jul 05 05:34:13 PM PDT 24
Finished Jul 05 05:34:45 PM PDT 24
Peak memory 218384 kb
Host smart-c46917c6-b3ff-4505-9ff6-5d5968769555
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875999563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.3875999563
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.1425893607
Short name T554
Test name
Test status
Simulation time 1146654593 ps
CPU time 9.39 seconds
Started Jul 05 05:34:12 PM PDT 24
Finished Jul 05 05:34:22 PM PDT 24
Peak memory 217268 kb
Host smart-0822b5c8-e5ba-4400-9b38-3ae7b36ac98b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425893607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.1425893607
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.3520707162
Short name T78
Test name
Test status
Simulation time 6907530718 ps
CPU time 12.93 seconds
Started Jul 05 05:34:13 PM PDT 24
Finished Jul 05 05:34:27 PM PDT 24
Peak memory 217148 kb
Host smart-0befcd73-a0aa-4c47-aa1c-dc6d344c1a15
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520707162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.3520707162
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.1443605654
Short name T161
Test name
Test status
Simulation time 9475120088 ps
CPU time 53.67 seconds
Started Jul 05 05:34:11 PM PDT 24
Finished Jul 05 05:35:06 PM PDT 24
Peak memory 278276 kb
Host smart-12615bc2-c158-49ce-9f60-0df348ed3b43
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443605654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.1443605654
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.1308689077
Short name T313
Test name
Test status
Simulation time 823089131 ps
CPU time 27.07 seconds
Started Jul 05 05:34:08 PM PDT 24
Finished Jul 05 05:34:36 PM PDT 24
Peak memory 247720 kb
Host smart-31c49148-1885-4db0-a8d9-b99161b1e401
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308689077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.1308689077
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.3256641089
Short name T759
Test name
Test status
Simulation time 286210318 ps
CPU time 2.85 seconds
Started Jul 05 05:34:08 PM PDT 24
Finished Jul 05 05:34:12 PM PDT 24
Peak memory 217788 kb
Host smart-cda038ff-ed94-48a1-a7fd-aae687ec96af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256641089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.3256641089
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.4011651980
Short name T737
Test name
Test status
Simulation time 335655918 ps
CPU time 7.02 seconds
Started Jul 05 05:34:09 PM PDT 24
Finished Jul 05 05:34:17 PM PDT 24
Peak memory 225548 kb
Host smart-90889052-7e55-4c51-85df-dd81dd88ddd6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011651980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.4011651980
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.94169303
Short name T533
Test name
Test status
Simulation time 824237225 ps
CPU time 15.58 seconds
Started Jul 05 05:34:08 PM PDT 24
Finished Jul 05 05:34:25 PM PDT 24
Peak memory 225452 kb
Host smart-cfe8a0b1-59bf-4241-b396-cb336bc0987a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94169303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_dig
est.94169303
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.938981035
Short name T798
Test name
Test status
Simulation time 1138851749 ps
CPU time 10.62 seconds
Started Jul 05 05:34:12 PM PDT 24
Finished Jul 05 05:34:23 PM PDT 24
Peak memory 217648 kb
Host smart-01242c4c-c705-46e2-b822-90a2fba2c116
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938981035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.938981035
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.2508446480
Short name T581
Test name
Test status
Simulation time 439259667 ps
CPU time 16.07 seconds
Started Jul 05 05:34:09 PM PDT 24
Finished Jul 05 05:34:26 PM PDT 24
Peak memory 224564 kb
Host smart-1cdd0a3f-03f0-4942-a35f-a8e6ab05b823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508446480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.2508446480
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.1492899830
Short name T291
Test name
Test status
Simulation time 110931950 ps
CPU time 3.36 seconds
Started Jul 05 05:34:09 PM PDT 24
Finished Jul 05 05:34:13 PM PDT 24
Peak memory 213916 kb
Host smart-9ef9ee35-2a76-4524-b494-81bc6adbf6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492899830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.1492899830
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.1328648416
Short name T342
Test name
Test status
Simulation time 1113238642 ps
CPU time 29.41 seconds
Started Jul 05 05:34:11 PM PDT 24
Finished Jul 05 05:34:41 PM PDT 24
Peak memory 250536 kb
Host smart-9170c508-34f3-480a-8576-388e131d4bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328648416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.1328648416
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.3531726625
Short name T432
Test name
Test status
Simulation time 192693231 ps
CPU time 8.7 seconds
Started Jul 05 05:34:08 PM PDT 24
Finished Jul 05 05:34:18 PM PDT 24
Peak memory 250532 kb
Host smart-7ea42fe3-d6c7-4b63-9ba7-62964363a700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531726625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.3531726625
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.2922490336
Short name T611
Test name
Test status
Simulation time 4330183641 ps
CPU time 97.94 seconds
Started Jul 05 05:34:19 PM PDT 24
Finished Jul 05 05:35:58 PM PDT 24
Peak memory 276784 kb
Host smart-0303dcf8-f477-4107-ba61-fd137d8222d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922490336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.2922490336
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.3380306996
Short name T303
Test name
Test status
Simulation time 23431970 ps
CPU time 0.95 seconds
Started Jul 05 05:34:09 PM PDT 24
Finished Jul 05 05:34:11 PM PDT 24
Peak memory 208452 kb
Host smart-76e72886-51ab-4565-ad71-3f6567000e69
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380306996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.3380306996
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.2988454992
Short name T238
Test name
Test status
Simulation time 138710165 ps
CPU time 0.83 seconds
Started Jul 05 05:34:16 PM PDT 24
Finished Jul 05 05:34:18 PM PDT 24
Peak memory 208356 kb
Host smart-90a8de23-4dff-4933-a79d-7b1e171be21e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988454992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.2988454992
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.2901347307
Short name T786
Test name
Test status
Simulation time 222460555 ps
CPU time 9.38 seconds
Started Jul 05 05:34:20 PM PDT 24
Finished Jul 05 05:34:30 PM PDT 24
Peak memory 217776 kb
Host smart-0ae563b3-f7b2-4643-a8ec-bc13d6f60404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901347307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.2901347307
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.3543048291
Short name T589
Test name
Test status
Simulation time 2208852726 ps
CPU time 7.64 seconds
Started Jul 05 05:34:21 PM PDT 24
Finished Jul 05 05:34:29 PM PDT 24
Peak memory 216912 kb
Host smart-5a83d49c-4c4d-41d9-b220-11fa100166dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543048291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.3543048291
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.282652567
Short name T186
Test name
Test status
Simulation time 4725192697 ps
CPU time 41.88 seconds
Started Jul 05 05:34:18 PM PDT 24
Finished Jul 05 05:35:01 PM PDT 24
Peak memory 217808 kb
Host smart-6a289943-cbaa-410c-a6d7-d57d7a3ea94c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282652567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_er
rors.282652567
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.785844782
Short name T809
Test name
Test status
Simulation time 756536781 ps
CPU time 4.32 seconds
Started Jul 05 05:34:15 PM PDT 24
Finished Jul 05 05:34:19 PM PDT 24
Peak memory 217716 kb
Host smart-78bb1fe0-44e5-4fa0-969f-54768b8306a5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785844782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag
_prog_failure.785844782
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.2349522025
Short name T591
Test name
Test status
Simulation time 179352290 ps
CPU time 2.33 seconds
Started Jul 05 05:34:22 PM PDT 24
Finished Jul 05 05:34:25 PM PDT 24
Peak memory 217152 kb
Host smart-136bcb47-ff03-41fd-ab7e-427d53460250
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349522025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.2349522025
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.2720124476
Short name T579
Test name
Test status
Simulation time 3676589481 ps
CPU time 38.87 seconds
Started Jul 05 05:34:16 PM PDT 24
Finished Jul 05 05:34:56 PM PDT 24
Peak memory 250528 kb
Host smart-29583e1c-3ea9-42b4-b86e-933256d0c9ef
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720124476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.2720124476
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.2563248861
Short name T424
Test name
Test status
Simulation time 8068708862 ps
CPU time 11.23 seconds
Started Jul 05 05:34:19 PM PDT 24
Finished Jul 05 05:34:31 PM PDT 24
Peak memory 217744 kb
Host smart-214a3316-14d9-4130-ade1-b94bac394c6d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563248861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.2563248861
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.2533999680
Short name T643
Test name
Test status
Simulation time 173677147 ps
CPU time 3.33 seconds
Started Jul 05 05:34:21 PM PDT 24
Finished Jul 05 05:34:25 PM PDT 24
Peak memory 222208 kb
Host smart-926c22e1-1ece-4a44-887d-5ae3292fe5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533999680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.2533999680
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.2855012408
Short name T854
Test name
Test status
Simulation time 850257478 ps
CPU time 13.66 seconds
Started Jul 05 05:34:19 PM PDT 24
Finished Jul 05 05:34:33 PM PDT 24
Peak memory 225504 kb
Host smart-fd8ed19e-7182-4cec-91e5-009787ce7717
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855012408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.2855012408
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.3185003966
Short name T264
Test name
Test status
Simulation time 460769995 ps
CPU time 9.68 seconds
Started Jul 05 05:34:16 PM PDT 24
Finished Jul 05 05:34:27 PM PDT 24
Peak memory 217792 kb
Host smart-3d222496-aea1-476d-addf-f9e222a1af81
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185003966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.3185003966
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.1375506646
Short name T820
Test name
Test status
Simulation time 2012446856 ps
CPU time 9.09 seconds
Started Jul 05 05:34:20 PM PDT 24
Finished Jul 05 05:34:30 PM PDT 24
Peak memory 217732 kb
Host smart-a2eb7db9-acdd-4834-b725-9a6a4e93be64
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375506646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
1375506646
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.1015394276
Short name T487
Test name
Test status
Simulation time 1093874182 ps
CPU time 7.32 seconds
Started Jul 05 05:34:16 PM PDT 24
Finished Jul 05 05:34:24 PM PDT 24
Peak memory 224504 kb
Host smart-949f3217-2f2b-4864-a431-92c956f49d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015394276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.1015394276
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.660865175
Short name T849
Test name
Test status
Simulation time 80874447 ps
CPU time 2.78 seconds
Started Jul 05 05:34:18 PM PDT 24
Finished Jul 05 05:34:22 PM PDT 24
Peak memory 214076 kb
Host smart-93409232-2ce6-4d2b-b74e-f2f8f1896e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660865175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.660865175
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.3883548610
Short name T810
Test name
Test status
Simulation time 806953866 ps
CPU time 27.67 seconds
Started Jul 05 05:34:16 PM PDT 24
Finished Jul 05 05:34:44 PM PDT 24
Peak memory 250476 kb
Host smart-067513d6-ef40-4ace-8fe4-21392a361d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883548610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.3883548610
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.1318576888
Short name T254
Test name
Test status
Simulation time 249053805 ps
CPU time 7.11 seconds
Started Jul 05 05:34:16 PM PDT 24
Finished Jul 05 05:34:24 PM PDT 24
Peak memory 249956 kb
Host smart-912d9ffc-8210-4383-9488-87263ecbdbb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318576888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.1318576888
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.1284673764
Short name T577
Test name
Test status
Simulation time 5615930084 ps
CPU time 74.34 seconds
Started Jul 05 05:34:22 PM PDT 24
Finished Jul 05 05:35:37 PM PDT 24
Peak memory 250092 kb
Host smart-a08cf425-14b3-467d-b9be-e38bc67f6e9f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284673764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.1284673764
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.3117383155
Short name T739
Test name
Test status
Simulation time 151116565 ps
CPU time 1.01 seconds
Started Jul 05 05:34:15 PM PDT 24
Finished Jul 05 05:34:16 PM PDT 24
Peak memory 211392 kb
Host smart-60b28b8c-5f61-4886-885e-258fbeffa0d4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117383155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.3117383155
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.3232763763
Short name T466
Test name
Test status
Simulation time 20764270 ps
CPU time 0.92 seconds
Started Jul 05 05:33:06 PM PDT 24
Finished Jul 05 05:33:07 PM PDT 24
Peak memory 208548 kb
Host smart-cf8a354f-43c4-4e58-bc71-02fd45a5b64a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232763763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.3232763763
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.19596404
Short name T229
Test name
Test status
Simulation time 12608214 ps
CPU time 0.88 seconds
Started Jul 05 05:33:01 PM PDT 24
Finished Jul 05 05:33:02 PM PDT 24
Peak memory 208260 kb
Host smart-979b1303-d089-4280-acee-4babc21ee7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19596404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.19596404
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.3087382706
Short name T521
Test name
Test status
Simulation time 270193483 ps
CPU time 12.22 seconds
Started Jul 05 05:33:03 PM PDT 24
Finished Jul 05 05:33:16 PM PDT 24
Peak memory 225592 kb
Host smart-d9c82d41-827d-45af-8c21-3625acea2f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087382706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.3087382706
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.3538569770
Short name T35
Test name
Test status
Simulation time 825388407 ps
CPU time 10.82 seconds
Started Jul 05 05:32:57 PM PDT 24
Finished Jul 05 05:33:08 PM PDT 24
Peak memory 217200 kb
Host smart-dc8a9604-2e7e-4e6c-b6ff-7741ed68f13b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538569770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.3538569770
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.3573100358
Short name T815
Test name
Test status
Simulation time 12018830261 ps
CPU time 40.34 seconds
Started Jul 05 05:33:02 PM PDT 24
Finished Jul 05 05:33:43 PM PDT 24
Peak memory 218444 kb
Host smart-6884e6de-0f1f-41dc-8f0b-823dfe6c5457
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573100358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.3573100358
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.1491509138
Short name T477
Test name
Test status
Simulation time 1041976806 ps
CPU time 4.7 seconds
Started Jul 05 05:33:01 PM PDT 24
Finished Jul 05 05:33:06 PM PDT 24
Peak memory 217188 kb
Host smart-e998a95d-f25b-44d7-8384-d51b55fa36dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491509138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.1
491509138
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.919277246
Short name T23
Test name
Test status
Simulation time 467411995 ps
CPU time 4.09 seconds
Started Jul 05 05:33:00 PM PDT 24
Finished Jul 05 05:33:05 PM PDT 24
Peak memory 217736 kb
Host smart-9cf0278f-1d4e-4c5d-8b68-3f136ee9d3da
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919277246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_
prog_failure.919277246
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.2658507101
Short name T756
Test name
Test status
Simulation time 16438773819 ps
CPU time 18.03 seconds
Started Jul 05 05:32:56 PM PDT 24
Finished Jul 05 05:33:15 PM PDT 24
Peak memory 217196 kb
Host smart-0044a1c4-8fd2-4c8b-8983-febb22a6ade0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658507101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.2658507101
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.2228095164
Short name T773
Test name
Test status
Simulation time 1332297253 ps
CPU time 6.89 seconds
Started Jul 05 05:32:58 PM PDT 24
Finished Jul 05 05:33:05 PM PDT 24
Peak memory 217124 kb
Host smart-92969ea9-18bc-49eb-ac18-c1b3d4371f7c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228095164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
2228095164
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.740651204
Short name T808
Test name
Test status
Simulation time 2120258445 ps
CPU time 45.46 seconds
Started Jul 05 05:32:58 PM PDT 24
Finished Jul 05 05:33:44 PM PDT 24
Peak memory 272688 kb
Host smart-5099f1bd-88e2-407b-9699-17298de92d36
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740651204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_state_failure.740651204
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.3180294176
Short name T322
Test name
Test status
Simulation time 360685134 ps
CPU time 12.01 seconds
Started Jul 05 05:33:00 PM PDT 24
Finished Jul 05 05:33:13 PM PDT 24
Peak memory 221724 kb
Host smart-f2961a86-0f7e-4bae-8642-1b11402bc87b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180294176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.3180294176
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.3933833293
Short name T695
Test name
Test status
Simulation time 92382713 ps
CPU time 2.15 seconds
Started Jul 05 05:33:00 PM PDT 24
Finished Jul 05 05:33:03 PM PDT 24
Peak memory 217904 kb
Host smart-133643c4-0817-43f9-80a0-b1b0b8c2c9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933833293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.3933833293
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.2931671020
Short name T622
Test name
Test status
Simulation time 1432883968 ps
CPU time 20.2 seconds
Started Jul 05 05:32:58 PM PDT 24
Finished Jul 05 05:33:19 PM PDT 24
Peak memory 217196 kb
Host smart-1868c2b1-b5f8-4ed0-87d0-a04fbafc7a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931671020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.2931671020
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.3302633700
Short name T87
Test name
Test status
Simulation time 198981542 ps
CPU time 38.1 seconds
Started Jul 05 05:33:06 PM PDT 24
Finished Jul 05 05:33:46 PM PDT 24
Peak memory 282352 kb
Host smart-5b371c2e-2bbe-4369-87e4-c40a4a81a66d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302633700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.3302633700
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.308965216
Short name T456
Test name
Test status
Simulation time 2257287326 ps
CPU time 14.22 seconds
Started Jul 05 05:33:06 PM PDT 24
Finished Jul 05 05:33:21 PM PDT 24
Peak memory 225572 kb
Host smart-41bab52c-d24c-4c5b-afc6-30691023d171
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308965216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_dig
est.308965216
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.2633173207
Short name T184
Test name
Test status
Simulation time 419021917 ps
CPU time 14.89 seconds
Started Jul 05 05:33:00 PM PDT 24
Finished Jul 05 05:33:16 PM PDT 24
Peak memory 217720 kb
Host smart-566c6ab0-5fc0-4212-9df9-f9ae4bf3526d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633173207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.2
633173207
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.324090128
Short name T314
Test name
Test status
Simulation time 312161900 ps
CPU time 7.57 seconds
Started Jul 05 05:32:59 PM PDT 24
Finished Jul 05 05:33:07 PM PDT 24
Peak memory 225532 kb
Host smart-fb6e44be-19b0-43c5-8911-a5fc13fc14f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324090128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.324090128
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.924287861
Short name T565
Test name
Test status
Simulation time 40275232 ps
CPU time 1.74 seconds
Started Jul 05 05:32:57 PM PDT 24
Finished Jul 05 05:33:00 PM PDT 24
Peak memory 213612 kb
Host smart-06c56e82-76df-4de0-b1cb-0ded895297ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924287861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.924287861
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.2186719185
Short name T689
Test name
Test status
Simulation time 392577500 ps
CPU time 22.76 seconds
Started Jul 05 05:33:01 PM PDT 24
Finished Jul 05 05:33:24 PM PDT 24
Peak memory 250476 kb
Host smart-13ab0fac-1b2e-4aec-81f0-5c7608176eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186719185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.2186719185
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.3946614572
Short name T104
Test name
Test status
Simulation time 368720197 ps
CPU time 8.38 seconds
Started Jul 05 05:33:00 PM PDT 24
Finished Jul 05 05:33:08 PM PDT 24
Peak memory 250536 kb
Host smart-7e2a2a6a-5bb7-4155-b4ff-9e8a97c663ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946614572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.3946614572
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.3363730550
Short name T325
Test name
Test status
Simulation time 3470950849 ps
CPU time 174.01 seconds
Started Jul 05 05:33:13 PM PDT 24
Finished Jul 05 05:36:09 PM PDT 24
Peak memory 251024 kb
Host smart-ddde2fc1-4560-498b-8938-41b5cb412663
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363730550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.3363730550
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.949077453
Short name T735
Test name
Test status
Simulation time 112888892 ps
CPU time 0.98 seconds
Started Jul 05 05:33:01 PM PDT 24
Finished Jul 05 05:33:02 PM PDT 24
Peak memory 217356 kb
Host smart-42a63f5e-fc2a-406e-b01d-d74dc83c71ae
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949077453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctr
l_volatile_unlock_smoke.949077453
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.656725667
Short name T194
Test name
Test status
Simulation time 27544874 ps
CPU time 1.4 seconds
Started Jul 05 05:34:17 PM PDT 24
Finished Jul 05 05:34:19 PM PDT 24
Peak memory 208640 kb
Host smart-863d0ae4-d757-41bb-bc15-cd4849609a21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656725667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.656725667
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.971338250
Short name T290
Test name
Test status
Simulation time 911272214 ps
CPU time 15.16 seconds
Started Jul 05 05:34:18 PM PDT 24
Finished Jul 05 05:34:34 PM PDT 24
Peak memory 217728 kb
Host smart-5e0fe868-5ab0-42a5-bad4-b72b1f7e24f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971338250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.971338250
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.2117273172
Short name T308
Test name
Test status
Simulation time 1223422220 ps
CPU time 4.48 seconds
Started Jul 05 05:34:18 PM PDT 24
Finished Jul 05 05:34:24 PM PDT 24
Peak memory 216852 kb
Host smart-5a6b6255-dfa5-4fa2-9850-237f6ab8f852
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117273172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.2117273172
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.601381411
Short name T295
Test name
Test status
Simulation time 46959778 ps
CPU time 1.97 seconds
Started Jul 05 05:34:18 PM PDT 24
Finished Jul 05 05:34:21 PM PDT 24
Peak memory 217668 kb
Host smart-7b1190ee-11c1-4093-a167-32ba7bf7943f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601381411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.601381411
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.427956287
Short name T258
Test name
Test status
Simulation time 443591803 ps
CPU time 7.99 seconds
Started Jul 05 05:34:16 PM PDT 24
Finished Jul 05 05:34:25 PM PDT 24
Peak memory 225708 kb
Host smart-7ff9e49d-a14a-4f82-83a7-d1396bbc58f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427956287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.427956287
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.2107859614
Short name T385
Test name
Test status
Simulation time 879304560 ps
CPU time 18.16 seconds
Started Jul 05 05:34:17 PM PDT 24
Finished Jul 05 05:34:36 PM PDT 24
Peak memory 225528 kb
Host smart-749912b0-af21-45c2-ab54-94fe954d2ca3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107859614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.2107859614
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.777240873
Short name T438
Test name
Test status
Simulation time 499490652 ps
CPU time 12.04 seconds
Started Jul 05 05:34:15 PM PDT 24
Finished Jul 05 05:34:27 PM PDT 24
Peak memory 217728 kb
Host smart-60852acd-ad73-4ca7-868b-a857b5f24e8f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777240873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.777240873
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.1848558950
Short name T232
Test name
Test status
Simulation time 1516866742 ps
CPU time 11.36 seconds
Started Jul 05 05:34:17 PM PDT 24
Finished Jul 05 05:34:29 PM PDT 24
Peak memory 225592 kb
Host smart-a6576aae-2538-4d70-9ceb-815e26649440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848558950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.1848558950
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.2205932815
Short name T634
Test name
Test status
Simulation time 166913342 ps
CPU time 1.18 seconds
Started Jul 05 05:34:17 PM PDT 24
Finished Jul 05 05:34:19 PM PDT 24
Peak memory 213312 kb
Host smart-793bc181-5e88-4453-a2dd-d74b1caeafc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205932815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.2205932815
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.1963965435
Short name T275
Test name
Test status
Simulation time 429377359 ps
CPU time 23.97 seconds
Started Jul 05 05:34:16 PM PDT 24
Finished Jul 05 05:34:40 PM PDT 24
Peak memory 250536 kb
Host smart-a11d2d78-63d4-4782-b44a-10f6e8e1284c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963965435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.1963965435
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.650381995
Short name T528
Test name
Test status
Simulation time 403081048 ps
CPU time 8.93 seconds
Started Jul 05 05:34:19 PM PDT 24
Finished Jul 05 05:34:29 PM PDT 24
Peak memory 250484 kb
Host smart-7f519522-679e-40a2-87a1-b558d667c4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650381995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.650381995
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.2133989307
Short name T69
Test name
Test status
Simulation time 13043917731 ps
CPU time 205.34 seconds
Started Jul 05 05:34:16 PM PDT 24
Finished Jul 05 05:37:43 PM PDT 24
Peak memory 250532 kb
Host smart-ee487b46-f23a-4fca-91e4-8350abe6a2cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133989307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.2133989307
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.4204086369
Short name T625
Test name
Test status
Simulation time 27809338 ps
CPU time 0.98 seconds
Started Jul 05 05:34:16 PM PDT 24
Finished Jul 05 05:34:17 PM PDT 24
Peak memory 208648 kb
Host smart-38fc4250-2459-4c98-b0ac-d48fb5324a46
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204086369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.4204086369
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.245699401
Short name T340
Test name
Test status
Simulation time 98745233 ps
CPU time 1.37 seconds
Started Jul 05 05:34:27 PM PDT 24
Finished Jul 05 05:34:29 PM PDT 24
Peak memory 208644 kb
Host smart-60c4a0a8-7465-4b10-8cbf-1327a22fc4ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245699401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.245699401
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.2381297711
Short name T688
Test name
Test status
Simulation time 2164731383 ps
CPU time 12.01 seconds
Started Jul 05 05:34:20 PM PDT 24
Finished Jul 05 05:34:33 PM PDT 24
Peak memory 217804 kb
Host smart-47d343e3-d517-4402-a0e5-df7b2fc810c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381297711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.2381297711
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.3271158375
Short name T31
Test name
Test status
Simulation time 698588034 ps
CPU time 2.53 seconds
Started Jul 05 05:34:17 PM PDT 24
Finished Jul 05 05:34:20 PM PDT 24
Peak memory 216680 kb
Host smart-461565c1-0071-47a8-ac24-f3d2b2aee53c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271158375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.3271158375
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.2566667378
Short name T862
Test name
Test status
Simulation time 32834427 ps
CPU time 1.89 seconds
Started Jul 05 05:34:19 PM PDT 24
Finished Jul 05 05:34:22 PM PDT 24
Peak memory 217760 kb
Host smart-18c764b3-8706-44cd-9f4d-be74ddf5b680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566667378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.2566667378
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.2381937126
Short name T606
Test name
Test status
Simulation time 484597982 ps
CPU time 12.99 seconds
Started Jul 05 05:34:17 PM PDT 24
Finished Jul 05 05:34:31 PM PDT 24
Peak memory 225588 kb
Host smart-42eee6b8-d26c-4b8a-a350-152294706e59
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381937126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.2381937126
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.2312584448
Short name T779
Test name
Test status
Simulation time 499319004 ps
CPU time 8.13 seconds
Started Jul 05 05:34:30 PM PDT 24
Finished Jul 05 05:34:39 PM PDT 24
Peak memory 225524 kb
Host smart-3f1902bd-8fcb-4c5a-b9cc-b29295196587
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312584448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.2312584448
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.1953713853
Short name T257
Test name
Test status
Simulation time 517590939 ps
CPU time 12.79 seconds
Started Jul 05 05:34:21 PM PDT 24
Finished Jul 05 05:34:35 PM PDT 24
Peak memory 217672 kb
Host smart-4f85e7ed-279a-4463-be4f-3adfaef6b35b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953713853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
1953713853
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.1180942365
Short name T675
Test name
Test status
Simulation time 375259123 ps
CPU time 13.03 seconds
Started Jul 05 05:34:19 PM PDT 24
Finished Jul 05 05:34:33 PM PDT 24
Peak memory 225588 kb
Host smart-3f283294-0059-494f-9434-b37074014362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180942365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.1180942365
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.65330057
Short name T562
Test name
Test status
Simulation time 154202015 ps
CPU time 2.56 seconds
Started Jul 05 05:34:20 PM PDT 24
Finished Jul 05 05:34:23 PM PDT 24
Peak memory 214332 kb
Host smart-02750b66-7833-4df2-8ffd-06072bcaf98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65330057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.65330057
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.1891554367
Short name T751
Test name
Test status
Simulation time 1076190341 ps
CPU time 33.31 seconds
Started Jul 05 05:34:16 PM PDT 24
Finished Jul 05 05:34:50 PM PDT 24
Peak memory 245312 kb
Host smart-3ed96368-1bb1-4efa-86ce-0a25c94041d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891554367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.1891554367
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.3916068924
Short name T617
Test name
Test status
Simulation time 70751785 ps
CPU time 7.9 seconds
Started Jul 05 05:34:18 PM PDT 24
Finished Jul 05 05:34:26 PM PDT 24
Peak memory 250524 kb
Host smart-6d942ac6-9885-4997-ae32-3e5a93680105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916068924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.3916068924
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.3246718529
Short name T711
Test name
Test status
Simulation time 3395668746 ps
CPU time 125.71 seconds
Started Jul 05 05:34:30 PM PDT 24
Finished Jul 05 05:36:37 PM PDT 24
Peak memory 273592 kb
Host smart-811f2887-77aa-491a-824b-e9479efa5f8f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246718529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.3246718529
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.2879925258
Short name T455
Test name
Test status
Simulation time 16382309 ps
CPU time 0.83 seconds
Started Jul 05 05:34:18 PM PDT 24
Finished Jul 05 05:34:19 PM PDT 24
Peak memory 208372 kb
Host smart-f7b17dbf-4cf8-4a0f-95f2-a537f063b785
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879925258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.2879925258
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.2062623128
Short name T720
Test name
Test status
Simulation time 21378410 ps
CPU time 1.2 seconds
Started Jul 05 05:34:34 PM PDT 24
Finished Jul 05 05:34:36 PM PDT 24
Peak memory 208188 kb
Host smart-84614f67-10ba-45a0-b2f5-8158b6ddecc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062623128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.2062623128
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.3183847289
Short name T644
Test name
Test status
Simulation time 1560136737 ps
CPU time 15.71 seconds
Started Jul 05 05:34:30 PM PDT 24
Finished Jul 05 05:34:47 PM PDT 24
Peak memory 217740 kb
Host smart-641530a9-7874-4573-bd1e-0dacdd988cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183847289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.3183847289
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.1204322735
Short name T36
Test name
Test status
Simulation time 446538727 ps
CPU time 6.48 seconds
Started Jul 05 05:34:28 PM PDT 24
Finished Jul 05 05:34:36 PM PDT 24
Peak memory 216908 kb
Host smart-a1ae2d29-ea91-4ab2-be98-63c7088cded1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204322735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.1204322735
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.2838569514
Short name T317
Test name
Test status
Simulation time 173229504 ps
CPU time 2.48 seconds
Started Jul 05 05:34:33 PM PDT 24
Finished Jul 05 05:34:36 PM PDT 24
Peak memory 221776 kb
Host smart-61696168-75cf-4dd3-8068-576bcace2631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838569514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.2838569514
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.1852131046
Short name T373
Test name
Test status
Simulation time 588937166 ps
CPU time 23.63 seconds
Started Jul 05 05:34:35 PM PDT 24
Finished Jul 05 05:35:00 PM PDT 24
Peak memory 225588 kb
Host smart-fc25922a-0c90-4fd6-8cdb-dd386e3f8286
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852131046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.1852131046
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.741551701
Short name T584
Test name
Test status
Simulation time 544698201 ps
CPU time 11.9 seconds
Started Jul 05 05:34:30 PM PDT 24
Finished Jul 05 05:34:43 PM PDT 24
Peak memory 217680 kb
Host smart-f5d08bc7-62f4-4390-9ad6-c8e000b35417
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741551701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_di
gest.741551701
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.1539981277
Short name T498
Test name
Test status
Simulation time 459016596 ps
CPU time 7.02 seconds
Started Jul 05 05:34:28 PM PDT 24
Finished Jul 05 05:34:36 PM PDT 24
Peak memory 217732 kb
Host smart-4c07e11d-d520-400a-91cb-86ef9097fa67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539981277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
1539981277
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.2200849660
Short name T65
Test name
Test status
Simulation time 976268106 ps
CPU time 7.86 seconds
Started Jul 05 05:35:55 PM PDT 24
Finished Jul 05 05:36:03 PM PDT 24
Peak memory 217804 kb
Host smart-a545e09a-517e-4938-bf38-c310fb584fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200849660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.2200849660
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.66166658
Short name T397
Test name
Test status
Simulation time 289509896 ps
CPU time 3.89 seconds
Started Jul 05 05:34:29 PM PDT 24
Finished Jul 05 05:34:34 PM PDT 24
Peak memory 217184 kb
Host smart-18e42d0b-1116-4ab2-88b4-046693639251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66166658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.66166658
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.1358527245
Short name T260
Test name
Test status
Simulation time 247155881 ps
CPU time 29.73 seconds
Started Jul 05 05:34:31 PM PDT 24
Finished Jul 05 05:35:01 PM PDT 24
Peak memory 250540 kb
Host smart-1064e9a8-36c6-4ad6-835e-d254a656d7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358527245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.1358527245
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.2925544449
Short name T512
Test name
Test status
Simulation time 182041787 ps
CPU time 5.92 seconds
Started Jul 05 05:34:26 PM PDT 24
Finished Jul 05 05:34:33 PM PDT 24
Peak memory 246440 kb
Host smart-8f7af674-fdff-41ba-9d6c-8e21340bd107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925544449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.2925544449
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.61013998
Short name T384
Test name
Test status
Simulation time 12738821065 ps
CPU time 101.46 seconds
Started Jul 05 05:34:30 PM PDT 24
Finished Jul 05 05:36:12 PM PDT 24
Peak memory 272276 kb
Host smart-083fb90f-ea6b-470f-95ad-6cfcefd2748f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61013998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.lc_ctrl_stress_all.61013998
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2987892793
Short name T499
Test name
Test status
Simulation time 39742721 ps
CPU time 0.87 seconds
Started Jul 05 05:34:28 PM PDT 24
Finished Jul 05 05:34:29 PM PDT 24
Peak memory 211344 kb
Host smart-6ea92547-c0f8-43f4-b6e8-f3c80985f340
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987892793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.2987892793
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.2481586832
Short name T88
Test name
Test status
Simulation time 19353949 ps
CPU time 1.17 seconds
Started Jul 05 05:34:27 PM PDT 24
Finished Jul 05 05:34:29 PM PDT 24
Peak memory 208536 kb
Host smart-d8dd62a6-fb58-4f27-8d46-fe974d462fa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481586832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.2481586832
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.2278895390
Short name T541
Test name
Test status
Simulation time 1521570247 ps
CPU time 8.44 seconds
Started Jul 05 05:34:28 PM PDT 24
Finished Jul 05 05:34:37 PM PDT 24
Peak memory 217796 kb
Host smart-762676f2-18ef-49cd-a2ba-4b99e47bdca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278895390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.2278895390
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.1762311274
Short name T829
Test name
Test status
Simulation time 324510932 ps
CPU time 2.6 seconds
Started Jul 05 05:34:30 PM PDT 24
Finished Jul 05 05:34:34 PM PDT 24
Peak memory 217168 kb
Host smart-2ebddb9c-852e-4312-9c90-4510fb0d1ab1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762311274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.1762311274
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.1549584566
Short name T526
Test name
Test status
Simulation time 223917044 ps
CPU time 2.92 seconds
Started Jul 05 05:34:28 PM PDT 24
Finished Jul 05 05:34:32 PM PDT 24
Peak memory 217792 kb
Host smart-a34b1535-ccff-46ca-bcae-49af20ba95fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549584566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.1549584566
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.3207284414
Short name T431
Test name
Test status
Simulation time 399851784 ps
CPU time 15.8 seconds
Started Jul 05 05:34:28 PM PDT 24
Finished Jul 05 05:34:45 PM PDT 24
Peak memory 218400 kb
Host smart-3cc1f3b1-b27f-4dd1-8822-e182adeb1ed6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207284414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.3207284414
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.2907636959
Short name T534
Test name
Test status
Simulation time 2425596065 ps
CPU time 10.9 seconds
Started Jul 05 05:34:29 PM PDT 24
Finished Jul 05 05:34:41 PM PDT 24
Peak memory 225596 kb
Host smart-007d2e61-7799-4788-b025-d82857828a19
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907636959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.2907636959
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.3673633041
Short name T405
Test name
Test status
Simulation time 2140558379 ps
CPU time 8.64 seconds
Started Jul 05 05:34:26 PM PDT 24
Finished Jul 05 05:34:34 PM PDT 24
Peak memory 225504 kb
Host smart-846a4513-275f-45ff-a2aa-a478adc20b88
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673633041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
3673633041
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.1627406471
Short name T866
Test name
Test status
Simulation time 690069459 ps
CPU time 7.84 seconds
Started Jul 05 05:34:29 PM PDT 24
Finished Jul 05 05:34:38 PM PDT 24
Peak memory 224316 kb
Host smart-36f1d99b-9a44-47bb-a268-5997b914e426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627406471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.1627406471
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.214788064
Short name T511
Test name
Test status
Simulation time 350913610 ps
CPU time 9.84 seconds
Started Jul 05 05:34:30 PM PDT 24
Finished Jul 05 05:34:41 PM PDT 24
Peak memory 217116 kb
Host smart-87e3500a-0f0c-4ffa-a940-ad5ea4beb4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214788064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.214788064
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.1616227075
Short name T285
Test name
Test status
Simulation time 233517274 ps
CPU time 24.7 seconds
Started Jul 05 05:34:28 PM PDT 24
Finished Jul 05 05:34:54 PM PDT 24
Peak memory 250428 kb
Host smart-99f010b4-0557-42b2-a08d-3b51db28a33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616227075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.1616227075
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.2849358384
Short name T650
Test name
Test status
Simulation time 167295157 ps
CPU time 6.73 seconds
Started Jul 05 05:34:30 PM PDT 24
Finished Jul 05 05:34:38 PM PDT 24
Peak memory 246172 kb
Host smart-055088b2-b1df-410e-bd23-90ed2df20d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849358384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.2849358384
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.1856118784
Short name T659
Test name
Test status
Simulation time 3659900883 ps
CPU time 109.44 seconds
Started Jul 05 05:34:27 PM PDT 24
Finished Jul 05 05:36:17 PM PDT 24
Peak memory 240856 kb
Host smart-ac07010c-4d24-4c97-8231-7cfa85d6bcb3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856118784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.1856118784
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.2099533126
Short name T700
Test name
Test status
Simulation time 19273291 ps
CPU time 0.98 seconds
Started Jul 05 05:34:31 PM PDT 24
Finished Jul 05 05:34:32 PM PDT 24
Peak memory 211464 kb
Host smart-883511d0-ac5c-4111-9214-305b7396a667
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099533126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.2099533126
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.3177530652
Short name T628
Test name
Test status
Simulation time 65260839 ps
CPU time 0.85 seconds
Started Jul 05 05:34:30 PM PDT 24
Finished Jul 05 05:34:31 PM PDT 24
Peak memory 208436 kb
Host smart-4d16ea17-34b1-4989-b87b-1a3d7c03177a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177530652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.3177530652
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.4097224628
Short name T173
Test name
Test status
Simulation time 938786589 ps
CPU time 8.88 seconds
Started Jul 05 05:34:29 PM PDT 24
Finished Jul 05 05:34:39 PM PDT 24
Peak memory 217792 kb
Host smart-7ec622ea-d42a-44f9-a7e7-a5f44d624f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097224628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.4097224628
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.1166553765
Short name T794
Test name
Test status
Simulation time 767586413 ps
CPU time 4.83 seconds
Started Jul 05 05:34:26 PM PDT 24
Finished Jul 05 05:34:32 PM PDT 24
Peak memory 217132 kb
Host smart-c9f26dc1-b31f-4ebb-9fea-c0a35c8b7d0f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166553765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.1166553765
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.3935897930
Short name T429
Test name
Test status
Simulation time 19809324 ps
CPU time 1.82 seconds
Started Jul 05 05:34:28 PM PDT 24
Finished Jul 05 05:34:30 PM PDT 24
Peak memory 217720 kb
Host smart-b21362aa-3684-4e1c-964a-dc4486113560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935897930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.3935897930
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.3430644618
Short name T721
Test name
Test status
Simulation time 1477228299 ps
CPU time 11.77 seconds
Started Jul 05 05:34:27 PM PDT 24
Finished Jul 05 05:34:39 PM PDT 24
Peak memory 225504 kb
Host smart-81eef31f-2851-4caa-a565-fe9dc45c1bdc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430644618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.3430644618
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.403551347
Short name T713
Test name
Test status
Simulation time 258537035 ps
CPU time 10.34 seconds
Started Jul 05 05:34:30 PM PDT 24
Finished Jul 05 05:34:41 PM PDT 24
Peak memory 217720 kb
Host smart-67726efa-463c-40de-925e-168e7bad3a90
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403551347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.403551347
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.991773864
Short name T850
Test name
Test status
Simulation time 314604492 ps
CPU time 11.83 seconds
Started Jul 05 05:34:29 PM PDT 24
Finished Jul 05 05:34:41 PM PDT 24
Peak memory 225248 kb
Host smart-11fd184a-5e86-4c0e-9525-01ef9e4c2b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991773864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.991773864
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.1034174759
Short name T306
Test name
Test status
Simulation time 129685490 ps
CPU time 3.28 seconds
Started Jul 05 05:34:34 PM PDT 24
Finished Jul 05 05:34:38 PM PDT 24
Peak memory 213660 kb
Host smart-3413696b-23b7-4282-aa1f-e1124d09b86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034174759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.1034174759
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.3971033946
Short name T469
Test name
Test status
Simulation time 205558215 ps
CPU time 22.1 seconds
Started Jul 05 05:34:33 PM PDT 24
Finished Jul 05 05:34:56 PM PDT 24
Peak memory 250524 kb
Host smart-129d52ba-bdcb-4193-8a8e-ab8ba651cbb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971033946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.3971033946
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.3600004972
Short name T760
Test name
Test status
Simulation time 85976983 ps
CPU time 3.34 seconds
Started Jul 05 05:34:27 PM PDT 24
Finished Jul 05 05:34:32 PM PDT 24
Peak memory 222068 kb
Host smart-f7ecdddb-43c9-452a-ad55-f693c73f840d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600004972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.3600004972
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.3014157927
Short name T776
Test name
Test status
Simulation time 7097773182 ps
CPU time 25.72 seconds
Started Jul 05 05:34:29 PM PDT 24
Finished Jul 05 05:34:55 PM PDT 24
Peak memory 225560 kb
Host smart-b8680937-6ee1-4a5b-96f9-30a2a6069352
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014157927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.3014157927
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.2429390447
Short name T618
Test name
Test status
Simulation time 10214731 ps
CPU time 0.9 seconds
Started Jul 05 05:34:27 PM PDT 24
Finished Jul 05 05:34:29 PM PDT 24
Peak memory 208096 kb
Host smart-1ce7783c-bc3b-4494-9e98-3fd8582efff6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429390447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.2429390447
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.1503807567
Short name T380
Test name
Test status
Simulation time 29086583 ps
CPU time 0.97 seconds
Started Jul 05 05:34:47 PM PDT 24
Finished Jul 05 05:34:50 PM PDT 24
Peak memory 208604 kb
Host smart-0c9f9e61-f11f-4cc7-b3cf-319d7ce47656
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503807567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.1503807567
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.3412763306
Short name T404
Test name
Test status
Simulation time 338459366 ps
CPU time 12.45 seconds
Started Jul 05 05:34:41 PM PDT 24
Finished Jul 05 05:34:54 PM PDT 24
Peak memory 217400 kb
Host smart-bded2185-1bbf-44ac-ae40-66efc667837e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412763306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.3412763306
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.4190661278
Short name T865
Test name
Test status
Simulation time 339658562 ps
CPU time 4.35 seconds
Started Jul 05 05:34:40 PM PDT 24
Finished Jul 05 05:34:45 PM PDT 24
Peak memory 217204 kb
Host smart-23023e89-67f1-48df-8803-b3578d197055
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190661278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.4190661278
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.3071951301
Short name T676
Test name
Test status
Simulation time 123091885 ps
CPU time 3.21 seconds
Started Jul 05 05:34:36 PM PDT 24
Finished Jul 05 05:34:41 PM PDT 24
Peak memory 217784 kb
Host smart-760b3ab7-cca0-41b2-9cff-67509043713f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071951301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.3071951301
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.3577782679
Short name T615
Test name
Test status
Simulation time 1283224202 ps
CPU time 24.52 seconds
Started Jul 05 05:34:44 PM PDT 24
Finished Jul 05 05:35:11 PM PDT 24
Peak memory 218400 kb
Host smart-c377cf46-e1e7-4563-87f0-f7ca4685a83b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577782679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.3577782679
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.4092056535
Short name T620
Test name
Test status
Simulation time 446429772 ps
CPU time 16.7 seconds
Started Jul 05 05:34:36 PM PDT 24
Finished Jul 05 05:34:55 PM PDT 24
Peak memory 225524 kb
Host smart-ee1ffba9-6810-4ef0-90aa-6910eb0bee92
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092056535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.4092056535
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.3572253149
Short name T25
Test name
Test status
Simulation time 2397605808 ps
CPU time 11.34 seconds
Started Jul 05 05:34:37 PM PDT 24
Finished Jul 05 05:34:50 PM PDT 24
Peak memory 217804 kb
Host smart-2ad38842-645c-4ba3-9e0a-ea3b92b990fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572253149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
3572253149
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.4241311416
Short name T548
Test name
Test status
Simulation time 207742905 ps
CPU time 8.41 seconds
Started Jul 05 05:34:37 PM PDT 24
Finished Jul 05 05:34:47 PM PDT 24
Peak memory 225540 kb
Host smart-73cf229f-ddb0-4bbf-abcb-7e625ce61ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241311416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.4241311416
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.3260008131
Short name T343
Test name
Test status
Simulation time 252124817 ps
CPU time 2.64 seconds
Started Jul 05 05:34:27 PM PDT 24
Finished Jul 05 05:34:30 PM PDT 24
Peak memory 217140 kb
Host smart-2501a4f5-2eeb-4ff5-91d2-65ec38ef6a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260008131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.3260008131
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.496755851
Short name T200
Test name
Test status
Simulation time 935178305 ps
CPU time 37.35 seconds
Started Jul 05 05:34:27 PM PDT 24
Finished Jul 05 05:35:05 PM PDT 24
Peak memory 250516 kb
Host smart-c1e5281e-cd20-44ab-ab03-a7fa4b59fb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496755851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.496755851
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.2813902751
Short name T355
Test name
Test status
Simulation time 106038164 ps
CPU time 6.93 seconds
Started Jul 05 05:34:48 PM PDT 24
Finished Jul 05 05:34:56 PM PDT 24
Peak memory 250500 kb
Host smart-e8e49e2b-11b6-4fba-b8b7-c1a523fd13d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813902751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.2813902751
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.341304185
Short name T176
Test name
Test status
Simulation time 15689385425 ps
CPU time 114.12 seconds
Started Jul 05 05:34:33 PM PDT 24
Finished Jul 05 05:36:28 PM PDT 24
Peak memory 225568 kb
Host smart-d9f56182-db30-4903-80e6-986db33ba8d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341304185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.341304185
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.574584480
Short name T279
Test name
Test status
Simulation time 14952712 ps
CPU time 1.06 seconds
Started Jul 05 05:34:30 PM PDT 24
Finished Jul 05 05:34:32 PM PDT 24
Peak memory 208732 kb
Host smart-1655443c-0c43-4c57-addf-6e9f8d0665c8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574584480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ct
rl_volatile_unlock_smoke.574584480
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.307590961
Short name T439
Test name
Test status
Simulation time 29760834 ps
CPU time 1.37 seconds
Started Jul 05 05:34:36 PM PDT 24
Finished Jul 05 05:34:39 PM PDT 24
Peak memory 208496 kb
Host smart-354bae23-953f-4383-b5b3-2f28af79ac44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307590961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.307590961
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.794181578
Short name T787
Test name
Test status
Simulation time 1035862575 ps
CPU time 21.81 seconds
Started Jul 05 05:34:42 PM PDT 24
Finished Jul 05 05:35:04 PM PDT 24
Peak memory 217748 kb
Host smart-b0fd3582-10bc-40aa-aa17-3d229db9421c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794181578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.794181578
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.1129010728
Short name T316
Test name
Test status
Simulation time 1407600484 ps
CPU time 3.91 seconds
Started Jul 05 05:34:37 PM PDT 24
Finished Jul 05 05:34:42 PM PDT 24
Peak memory 216704 kb
Host smart-2f572fd7-d264-4df5-a56e-23772c15ac09
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129010728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.1129010728
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.807517388
Short name T449
Test name
Test status
Simulation time 64660588 ps
CPU time 2.84 seconds
Started Jul 05 05:34:36 PM PDT 24
Finished Jul 05 05:34:41 PM PDT 24
Peak memory 217764 kb
Host smart-c4cbab5d-1449-42e7-8b55-fbac45607e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807517388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.807517388
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.3753213733
Short name T481
Test name
Test status
Simulation time 322387521 ps
CPU time 14.85 seconds
Started Jul 05 05:34:41 PM PDT 24
Finished Jul 05 05:34:57 PM PDT 24
Peak memory 218444 kb
Host smart-2a293cc5-c634-4115-bf77-731f784a7718
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753213733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.3753213733
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.3244036914
Short name T663
Test name
Test status
Simulation time 597222603 ps
CPU time 12.44 seconds
Started Jul 05 05:34:38 PM PDT 24
Finished Jul 05 05:34:52 PM PDT 24
Peak memory 225496 kb
Host smart-4b0a7a19-394c-4315-90be-5384026f0f68
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244036914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.3244036914
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.479817914
Short name T569
Test name
Test status
Simulation time 1436712345 ps
CPU time 9.35 seconds
Started Jul 05 05:34:36 PM PDT 24
Finished Jul 05 05:34:47 PM PDT 24
Peak memory 217736 kb
Host smart-eb1d6dcf-b902-45e5-9107-645d3e07b617
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479817914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.479817914
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.1490910271
Short name T834
Test name
Test status
Simulation time 262055275 ps
CPU time 7.24 seconds
Started Jul 05 05:34:36 PM PDT 24
Finished Jul 05 05:34:45 PM PDT 24
Peak memory 225496 kb
Host smart-df637232-28b4-4af9-86eb-0b08504b8318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490910271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.1490910271
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.1790616187
Short name T649
Test name
Test status
Simulation time 18152372 ps
CPU time 1.1 seconds
Started Jul 05 05:34:36 PM PDT 24
Finished Jul 05 05:34:39 PM PDT 24
Peak memory 221160 kb
Host smart-cf89eb30-a462-438c-9541-36cd9f4529c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790616187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.1790616187
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.1654852805
Short name T681
Test name
Test status
Simulation time 315502274 ps
CPU time 20.61 seconds
Started Jul 05 05:34:33 PM PDT 24
Finished Jul 05 05:34:55 PM PDT 24
Peak memory 250456 kb
Host smart-537dbd06-3d16-4c47-89bc-9ba4d442167b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654852805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.1654852805
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.356814955
Short name T412
Test name
Test status
Simulation time 152325408 ps
CPU time 3.25 seconds
Started Jul 05 05:34:36 PM PDT 24
Finished Jul 05 05:34:41 PM PDT 24
Peak memory 221756 kb
Host smart-122efe1c-566b-4739-aa40-032060d0e593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356814955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.356814955
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.1171649651
Short name T666
Test name
Test status
Simulation time 12016785759 ps
CPU time 188.47 seconds
Started Jul 05 05:34:44 PM PDT 24
Finished Jul 05 05:37:54 PM PDT 24
Peak memory 270524 kb
Host smart-293cce72-f49d-4bf5-929d-d57a022e3de1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171649651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.1171649651
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1899132278
Short name T437
Test name
Test status
Simulation time 29764514 ps
CPU time 0.99 seconds
Started Jul 05 05:34:46 PM PDT 24
Finished Jul 05 05:34:49 PM PDT 24
Peak memory 212376 kb
Host smart-0911c553-ece6-4c3c-8d12-3b5e722ad215
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899132278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.1899132278
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.3757214560
Short name T89
Test name
Test status
Simulation time 172915989 ps
CPU time 0.91 seconds
Started Jul 05 05:34:37 PM PDT 24
Finished Jul 05 05:34:40 PM PDT 24
Peak memory 208500 kb
Host smart-fbf0bfa4-bd19-4da4-ab01-88ba12567bf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757214560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.3757214560
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.2257160080
Short name T783
Test name
Test status
Simulation time 6179686453 ps
CPU time 15.71 seconds
Started Jul 05 05:34:47 PM PDT 24
Finished Jul 05 05:35:05 PM PDT 24
Peak memory 218508 kb
Host smart-9c0bf26a-fda3-4325-ad93-1123e79d5658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257160080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.2257160080
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.1659004187
Short name T543
Test name
Test status
Simulation time 81730467 ps
CPU time 2.53 seconds
Started Jul 05 05:34:48 PM PDT 24
Finished Jul 05 05:34:52 PM PDT 24
Peak memory 217208 kb
Host smart-0ff799a8-4ca4-4805-aac5-58f79246090a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659004187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.1659004187
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.3523327287
Short name T170
Test name
Test status
Simulation time 131488868 ps
CPU time 2.36 seconds
Started Jul 05 05:34:41 PM PDT 24
Finished Jul 05 05:34:44 PM PDT 24
Peak memory 217788 kb
Host smart-ad426af6-5c2d-4895-ac86-a9be5f6c0dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523327287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.3523327287
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.463926667
Short name T262
Test name
Test status
Simulation time 341119134 ps
CPU time 11.22 seconds
Started Jul 05 05:34:41 PM PDT 24
Finished Jul 05 05:34:53 PM PDT 24
Peak memory 225588 kb
Host smart-5fa58ef0-8274-4a9b-8f0a-a005709e34f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463926667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.463926667
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.1528784369
Short name T509
Test name
Test status
Simulation time 1132165253 ps
CPU time 11.25 seconds
Started Jul 05 05:34:46 PM PDT 24
Finished Jul 05 05:35:00 PM PDT 24
Peak memory 225368 kb
Host smart-55c4266d-330c-4299-a39b-a7c04b0f2630
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528784369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.1528784369
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.2297078167
Short name T698
Test name
Test status
Simulation time 511596859 ps
CPU time 6.69 seconds
Started Jul 05 05:34:37 PM PDT 24
Finished Jul 05 05:34:45 PM PDT 24
Peak memory 225524 kb
Host smart-2fe7f562-d25b-4333-b14d-1bd53a56d70d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297078167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
2297078167
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.1345683991
Short name T592
Test name
Test status
Simulation time 5172220429 ps
CPU time 10.49 seconds
Started Jul 05 05:34:48 PM PDT 24
Finished Jul 05 05:35:00 PM PDT 24
Peak memory 217924 kb
Host smart-df21eaa9-d5ab-4e0c-9c75-fc1c615ee68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345683991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.1345683991
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.4193012108
Short name T658
Test name
Test status
Simulation time 116837558 ps
CPU time 1.65 seconds
Started Jul 05 05:34:34 PM PDT 24
Finished Jul 05 05:34:37 PM PDT 24
Peak memory 222608 kb
Host smart-21ecbb61-3a01-4eda-8a64-ed328c6acd10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193012108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.4193012108
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.3842008969
Short name T672
Test name
Test status
Simulation time 979978853 ps
CPU time 26.13 seconds
Started Jul 05 05:34:33 PM PDT 24
Finished Jul 05 05:35:00 PM PDT 24
Peak memory 250536 kb
Host smart-ec704a73-570f-48c7-8118-3bb48180e3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842008969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.3842008969
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.1686834220
Short name T826
Test name
Test status
Simulation time 272814484 ps
CPU time 9.85 seconds
Started Jul 05 05:34:36 PM PDT 24
Finished Jul 05 05:34:47 PM PDT 24
Peak memory 250540 kb
Host smart-4285c76c-1795-4db6-beab-2fd96f4f09a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686834220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.1686834220
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.956778296
Short name T503
Test name
Test status
Simulation time 6931857848 ps
CPU time 137.36 seconds
Started Jul 05 05:34:35 PM PDT 24
Finished Jul 05 05:36:54 PM PDT 24
Peak memory 271788 kb
Host smart-a771f37e-6142-4b83-a239-10e10f93b72f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956778296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.956778296
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.913198430
Short name T156
Test name
Test status
Simulation time 27748016886 ps
CPU time 424.71 seconds
Started Jul 05 05:34:35 PM PDT 24
Finished Jul 05 05:41:42 PM PDT 24
Peak memory 267128 kb
Host smart-3e7af159-1ae0-4002-8f91-ab6455cee647
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=913198430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all_with_rand_reset.913198430
Directory /workspace/27.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.3206959676
Short name T517
Test name
Test status
Simulation time 16098419 ps
CPU time 1.04 seconds
Started Jul 05 05:34:44 PM PDT 24
Finished Jul 05 05:34:47 PM PDT 24
Peak memory 211408 kb
Host smart-6001b577-5404-4162-a416-429ddefc47fc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206959676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.3206959676
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.3292285066
Short name T256
Test name
Test status
Simulation time 18386995 ps
CPU time 1.18 seconds
Started Jul 05 05:34:36 PM PDT 24
Finished Jul 05 05:34:39 PM PDT 24
Peak memory 208608 kb
Host smart-8aa164c1-7e81-47c3-95be-43edadc0c4b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292285066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.3292285066
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.2005709936
Short name T813
Test name
Test status
Simulation time 197344837 ps
CPU time 7.87 seconds
Started Jul 05 05:34:38 PM PDT 24
Finished Jul 05 05:34:47 PM PDT 24
Peak memory 217764 kb
Host smart-2ca7929a-9e07-4ef4-b300-55a6e0039493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005709936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.2005709936
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.1880482960
Short name T37
Test name
Test status
Simulation time 359607899 ps
CPU time 1.89 seconds
Started Jul 05 05:34:35 PM PDT 24
Finished Jul 05 05:34:38 PM PDT 24
Peak memory 217140 kb
Host smart-e7470de7-b51b-4140-9d56-87e684f1c539
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880482960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.1880482960
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.1167568674
Short name T307
Test name
Test status
Simulation time 275659195 ps
CPU time 3.47 seconds
Started Jul 05 05:34:45 PM PDT 24
Finished Jul 05 05:34:50 PM PDT 24
Peak memory 217744 kb
Host smart-66f5b4b2-08bf-42a2-89ed-719e95db8cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167568674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.1167568674
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.2195513446
Short name T765
Test name
Test status
Simulation time 1640678409 ps
CPU time 13.15 seconds
Started Jul 05 05:34:34 PM PDT 24
Finished Jul 05 05:34:48 PM PDT 24
Peak memory 219520 kb
Host smart-e55d2b6c-43b4-47ed-b631-ce88847ae9b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195513446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.2195513446
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.2297817407
Short name T697
Test name
Test status
Simulation time 697842875 ps
CPU time 16.2 seconds
Started Jul 05 05:34:34 PM PDT 24
Finished Jul 05 05:34:51 PM PDT 24
Peak memory 225524 kb
Host smart-833556bc-731f-471a-8cdf-9244af25f014
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297817407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.2297817407
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.3908914878
Short name T168
Test name
Test status
Simulation time 349598549 ps
CPU time 12.66 seconds
Started Jul 05 05:34:42 PM PDT 24
Finished Jul 05 05:34:55 PM PDT 24
Peak memory 217708 kb
Host smart-6d7e3d86-5eea-48df-9aa7-94ea2c572ef3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908914878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
3908914878
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.580208318
Short name T328
Test name
Test status
Simulation time 336617319 ps
CPU time 9.18 seconds
Started Jul 05 05:34:41 PM PDT 24
Finished Jul 05 05:34:51 PM PDT 24
Peak memory 217676 kb
Host smart-1123d644-7047-42ab-b400-3c2045d561dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580208318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.580208318
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.419263765
Short name T767
Test name
Test status
Simulation time 44781004 ps
CPU time 3.56 seconds
Started Jul 05 05:34:34 PM PDT 24
Finished Jul 05 05:34:39 PM PDT 24
Peak memory 214488 kb
Host smart-24ce49cf-10e5-4445-b9d4-59fe83e4569b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419263765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.419263765
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.3494496613
Short name T616
Test name
Test status
Simulation time 346524691 ps
CPU time 28.59 seconds
Started Jul 05 05:34:39 PM PDT 24
Finished Jul 05 05:35:08 PM PDT 24
Peak memory 250540 kb
Host smart-6afc7a3f-b517-47b7-a2aa-16f844dbfe57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494496613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.3494496613
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.2674949917
Short name T443
Test name
Test status
Simulation time 82859255 ps
CPU time 6.84 seconds
Started Jul 05 05:34:46 PM PDT 24
Finished Jul 05 05:34:55 PM PDT 24
Peak memory 249948 kb
Host smart-5a51f947-bcbf-4fe3-9514-93b20f3d13ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674949917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.2674949917
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.2403567035
Short name T441
Test name
Test status
Simulation time 28892278263 ps
CPU time 274.22 seconds
Started Jul 05 05:34:35 PM PDT 24
Finished Jul 05 05:39:10 PM PDT 24
Peak memory 267848 kb
Host smart-fef67a8f-62f7-4dcf-b587-0d54611c244b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403567035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.2403567035
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.2807536246
Short name T453
Test name
Test status
Simulation time 3911118730 ps
CPU time 97.16 seconds
Started Jul 05 05:34:44 PM PDT 24
Finished Jul 05 05:36:23 PM PDT 24
Peak memory 278408 kb
Host smart-1ab5dd27-f8ad-4fe6-ac25-f6d5dbf4a13c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2807536246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all_with_rand_reset.2807536246
Directory /workspace/28.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.398951075
Short name T733
Test name
Test status
Simulation time 26489669 ps
CPU time 1.53 seconds
Started Jul 05 05:34:42 PM PDT 24
Finished Jul 05 05:34:44 PM PDT 24
Peak memory 217220 kb
Host smart-dedfdf13-5664-4167-8baf-e77674c3154d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398951075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ct
rl_volatile_unlock_smoke.398951075
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.2809137289
Short name T500
Test name
Test status
Simulation time 37486547 ps
CPU time 1.27 seconds
Started Jul 05 05:34:44 PM PDT 24
Finished Jul 05 05:34:47 PM PDT 24
Peak memory 208540 kb
Host smart-9c999d2f-4e92-4ea4-84c0-3dd730db0848
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809137289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.2809137289
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.3273477142
Short name T54
Test name
Test status
Simulation time 366469190 ps
CPU time 9.89 seconds
Started Jul 05 05:34:34 PM PDT 24
Finished Jul 05 05:34:44 PM PDT 24
Peak memory 217796 kb
Host smart-0183b75c-ae13-4540-a454-7f844adf9993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273477142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.3273477142
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.1693662702
Short name T336
Test name
Test status
Simulation time 1793714495 ps
CPU time 11.87 seconds
Started Jul 05 05:34:42 PM PDT 24
Finished Jul 05 05:34:54 PM PDT 24
Peak memory 216748 kb
Host smart-7ae39a11-184a-4e68-8036-33ae27aec7a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693662702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.1693662702
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.2168835197
Short name T250
Test name
Test status
Simulation time 92645998 ps
CPU time 3.63 seconds
Started Jul 05 05:34:35 PM PDT 24
Finished Jul 05 05:34:41 PM PDT 24
Peak memory 217784 kb
Host smart-e911f2b2-b1e5-43df-9834-df70b3075581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168835197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.2168835197
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.3691065519
Short name T447
Test name
Test status
Simulation time 2023580158 ps
CPU time 13.65 seconds
Started Jul 05 05:34:43 PM PDT 24
Finished Jul 05 05:34:58 PM PDT 24
Peak memory 225524 kb
Host smart-50738af6-800c-4e36-9c22-c121bc5d551d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691065519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.3691065519
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.893690558
Short name T824
Test name
Test status
Simulation time 4974864853 ps
CPU time 8.67 seconds
Started Jul 05 05:34:44 PM PDT 24
Finished Jul 05 05:34:54 PM PDT 24
Peak memory 217744 kb
Host smart-a185bbd2-d389-4da9-9114-7a06a0e53807
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893690558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.893690558
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.3115871843
Short name T596
Test name
Test status
Simulation time 380275056 ps
CPU time 6.9 seconds
Started Jul 05 05:34:36 PM PDT 24
Finished Jul 05 05:34:44 PM PDT 24
Peak memory 224380 kb
Host smart-cd5a5125-3cd0-47f4-933a-d99205b1fa09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115871843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.3115871843
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.2029441880
Short name T719
Test name
Test status
Simulation time 216817901 ps
CPU time 3.18 seconds
Started Jul 05 05:34:47 PM PDT 24
Finished Jul 05 05:34:52 PM PDT 24
Peak memory 217208 kb
Host smart-984d89f9-fac0-43d8-b287-24a7e11d08c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029441880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.2029441880
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.3975804763
Short name T514
Test name
Test status
Simulation time 2843089909 ps
CPU time 23.38 seconds
Started Jul 05 05:34:42 PM PDT 24
Finished Jul 05 05:35:06 PM PDT 24
Peak memory 250576 kb
Host smart-62ba08c0-4f3b-4cb6-96c6-7eab980e9138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975804763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.3975804763
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.3911117084
Short name T780
Test name
Test status
Simulation time 239347655 ps
CPU time 2.86 seconds
Started Jul 05 05:34:34 PM PDT 24
Finished Jul 05 05:34:38 PM PDT 24
Peak memory 222132 kb
Host smart-3e1e8e15-d2e3-4bea-b496-b6473af8d611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911117084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.3911117084
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.3284382599
Short name T832
Test name
Test status
Simulation time 13041644350 ps
CPU time 399.51 seconds
Started Jul 05 05:34:43 PM PDT 24
Finished Jul 05 05:41:24 PM PDT 24
Peak memory 283384 kb
Host smart-2a33e570-7251-4304-8f04-28acd8a9ca3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284382599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.3284382599
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.1135165304
Short name T356
Test name
Test status
Simulation time 33080453 ps
CPU time 0.9 seconds
Started Jul 05 05:33:07 PM PDT 24
Finished Jul 05 05:33:09 PM PDT 24
Peak memory 208568 kb
Host smart-e17e7aa2-7d8f-4c3b-827a-6ab9f88cacdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135165304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.1135165304
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.281846319
Short name T230
Test name
Test status
Simulation time 32954477 ps
CPU time 0.82 seconds
Started Jul 05 05:33:04 PM PDT 24
Finished Jul 05 05:33:06 PM PDT 24
Peak memory 208524 kb
Host smart-458ac10f-ca6f-469d-ae0d-d5e5491cecd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281846319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.281846319
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.2422830593
Short name T41
Test name
Test status
Simulation time 312935737 ps
CPU time 12.92 seconds
Started Jul 05 05:33:09 PM PDT 24
Finished Jul 05 05:33:23 PM PDT 24
Peak memory 225592 kb
Host smart-53d1e012-b96c-4cd5-9051-4e72d72ee44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422830593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.2422830593
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.3256725520
Short name T718
Test name
Test status
Simulation time 1400082873 ps
CPU time 32.05 seconds
Started Jul 05 05:33:09 PM PDT 24
Finished Jul 05 05:33:42 PM PDT 24
Peak memory 216992 kb
Host smart-c4e4d57a-c972-46c9-a47a-2f44c1e8b664
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256725520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.3256725520
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.2618396443
Short name T743
Test name
Test status
Simulation time 1350868286 ps
CPU time 21.63 seconds
Started Jul 05 05:33:07 PM PDT 24
Finished Jul 05 05:33:30 PM PDT 24
Peak memory 217792 kb
Host smart-7d9f7e30-30ee-4350-9b5f-e5973cfb3112
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618396443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.2618396443
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.1888612402
Short name T58
Test name
Test status
Simulation time 1362406654 ps
CPU time 9.59 seconds
Started Jul 05 05:33:10 PM PDT 24
Finished Jul 05 05:33:20 PM PDT 24
Peak memory 217168 kb
Host smart-d69e3465-770d-4de2-b67b-a3b0022e2787
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888612402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.1
888612402
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.2451733399
Short name T241
Test name
Test status
Simulation time 120628985 ps
CPU time 4.56 seconds
Started Jul 05 05:33:10 PM PDT 24
Finished Jul 05 05:33:15 PM PDT 24
Peak memory 217740 kb
Host smart-f9f7391f-a134-4eea-9e50-4cd909c5a783
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451733399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.2451733399
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.3283713494
Short name T93
Test name
Test status
Simulation time 1160669434 ps
CPU time 30.25 seconds
Started Jul 05 05:33:05 PM PDT 24
Finished Jul 05 05:33:36 PM PDT 24
Peak memory 217124 kb
Host smart-c99042e2-c47c-4cf4-9b4a-a3a0ac6cac4e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283713494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.3283713494
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.2769128541
Short name T651
Test name
Test status
Simulation time 165872327 ps
CPU time 3.25 seconds
Started Jul 05 05:33:11 PM PDT 24
Finished Jul 05 05:33:14 PM PDT 24
Peak memory 217268 kb
Host smart-a4b989e3-8830-4533-baa0-cdd4b70ad37b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769128541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
2769128541
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.2902630852
Short name T701
Test name
Test status
Simulation time 1090911765 ps
CPU time 31.97 seconds
Started Jul 05 05:33:06 PM PDT 24
Finished Jul 05 05:33:39 PM PDT 24
Peak memory 250480 kb
Host smart-6d9c0dfe-2cb9-4817-86de-8c5c0ba047a8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902630852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.2902630852
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.4231527606
Short name T195
Test name
Test status
Simulation time 386747674 ps
CPU time 11.04 seconds
Started Jul 05 05:33:11 PM PDT 24
Finished Jul 05 05:33:23 PM PDT 24
Peak memory 250056 kb
Host smart-c454532f-b48b-4b69-8d34-76c4ae834505
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231527606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.4231527606
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.1126548554
Short name T267
Test name
Test status
Simulation time 133572675 ps
CPU time 2.55 seconds
Started Jul 05 05:33:05 PM PDT 24
Finished Jul 05 05:33:08 PM PDT 24
Peak memory 217784 kb
Host smart-68a9c3d8-4460-445a-9db5-c88b485657ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126548554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.1126548554
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.1477392339
Short name T842
Test name
Test status
Simulation time 1168475189 ps
CPU time 8.18 seconds
Started Jul 05 05:33:13 PM PDT 24
Finished Jul 05 05:33:22 PM PDT 24
Peak memory 214028 kb
Host smart-0e9a1dbe-739e-467e-9987-2e72a61e13e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477392339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.1477392339
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.342307246
Short name T68
Test name
Test status
Simulation time 938715995 ps
CPU time 34.37 seconds
Started Jul 05 05:33:05 PM PDT 24
Finished Jul 05 05:33:40 PM PDT 24
Peak memory 284060 kb
Host smart-39494e8f-3628-4a80-ab59-0390bd846860
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342307246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.342307246
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.2719656597
Short name T677
Test name
Test status
Simulation time 2199792297 ps
CPU time 12.91 seconds
Started Jul 05 05:33:05 PM PDT 24
Finished Jul 05 05:33:19 PM PDT 24
Peak memory 225512 kb
Host smart-f6331451-0f26-41bf-bcbd-36e5a66d0d15
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719656597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.2719656597
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.2300043472
Short name T777
Test name
Test status
Simulation time 1769638756 ps
CPU time 10.39 seconds
Started Jul 05 05:33:06 PM PDT 24
Finished Jul 05 05:33:17 PM PDT 24
Peak memory 225476 kb
Host smart-86e4e45b-8924-49fa-b1e9-5b56e8a6f5c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300043472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.2
300043472
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.2503077100
Short name T236
Test name
Test status
Simulation time 255446832 ps
CPU time 7.28 seconds
Started Jul 05 05:33:11 PM PDT 24
Finished Jul 05 05:33:19 PM PDT 24
Peak memory 225592 kb
Host smart-4ee7ebda-9674-4ec2-bf8b-9c51e762bbf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503077100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.2503077100
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.453670242
Short name T74
Test name
Test status
Simulation time 213446466 ps
CPU time 2.59 seconds
Started Jul 05 05:33:07 PM PDT 24
Finished Jul 05 05:33:10 PM PDT 24
Peak memory 214124 kb
Host smart-e5ea49b8-70b2-44de-a944-3d42e404976d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453670242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.453670242
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.4257836106
Short name T544
Test name
Test status
Simulation time 877993506 ps
CPU time 24.11 seconds
Started Jul 05 05:33:05 PM PDT 24
Finished Jul 05 05:33:30 PM PDT 24
Peak memory 250396 kb
Host smart-245ce838-eb5a-4e36-a641-a7d6a33722ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257836106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.4257836106
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.1566598632
Short name T421
Test name
Test status
Simulation time 126017180 ps
CPU time 6.33 seconds
Started Jul 05 05:33:07 PM PDT 24
Finished Jul 05 05:33:15 PM PDT 24
Peak memory 246540 kb
Host smart-a873b68b-0be9-46a0-a205-12d296af84b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566598632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.1566598632
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.1150918311
Short name T56
Test name
Test status
Simulation time 2745869363 ps
CPU time 84.65 seconds
Started Jul 05 05:33:09 PM PDT 24
Finished Jul 05 05:34:34 PM PDT 24
Peak memory 249500 kb
Host smart-3dc22594-8056-4d1f-ae52-d0623093d2cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150918311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.1150918311
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.3479171872
Short name T309
Test name
Test status
Simulation time 44581721 ps
CPU time 0.81 seconds
Started Jul 05 05:33:11 PM PDT 24
Finished Jul 05 05:33:12 PM PDT 24
Peak memory 208384 kb
Host smart-e940e89b-a505-4f3f-904c-2741a156d81f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479171872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.3479171872
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.2230837060
Short name T758
Test name
Test status
Simulation time 15212891 ps
CPU time 0.83 seconds
Started Jul 05 05:34:45 PM PDT 24
Finished Jul 05 05:34:48 PM PDT 24
Peak memory 208556 kb
Host smart-c658f33e-fb2d-486c-a4ce-b99596774ec3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230837060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.2230837060
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.911524905
Short name T504
Test name
Test status
Simulation time 246157307 ps
CPU time 11.73 seconds
Started Jul 05 05:34:47 PM PDT 24
Finished Jul 05 05:35:01 PM PDT 24
Peak memory 217776 kb
Host smart-ca3dc752-cd35-4755-97c2-3a213c437ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911524905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.911524905
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.1633573171
Short name T34
Test name
Test status
Simulation time 3469246601 ps
CPU time 2.59 seconds
Started Jul 05 05:34:44 PM PDT 24
Finished Jul 05 05:34:48 PM PDT 24
Peak memory 216888 kb
Host smart-8d2db7b6-8aef-400f-9351-7dc332ac4611
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633573171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.1633573171
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.2791902677
Short name T564
Test name
Test status
Simulation time 32530257 ps
CPU time 1.95 seconds
Started Jul 05 05:34:44 PM PDT 24
Finished Jul 05 05:34:48 PM PDT 24
Peak memory 217788 kb
Host smart-c706fbd0-f4f3-4329-b15c-64b6d0accdd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791902677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.2791902677
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.1570992804
Short name T859
Test name
Test status
Simulation time 459045764 ps
CPU time 13.57 seconds
Started Jul 05 05:34:43 PM PDT 24
Finished Jul 05 05:34:57 PM PDT 24
Peak memory 218380 kb
Host smart-412ecc4c-a710-4951-9431-f615937e4a9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570992804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.1570992804
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.778454768
Short name T764
Test name
Test status
Simulation time 283784015 ps
CPU time 9.42 seconds
Started Jul 05 05:34:44 PM PDT 24
Finished Jul 05 05:34:55 PM PDT 24
Peak memory 225512 kb
Host smart-436891eb-10d8-443d-9439-d0a27f2e0536
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778454768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_di
gest.778454768
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.1895508357
Short name T811
Test name
Test status
Simulation time 4422691475 ps
CPU time 13.3 seconds
Started Jul 05 05:34:47 PM PDT 24
Finished Jul 05 05:35:02 PM PDT 24
Peak memory 225592 kb
Host smart-c3a080c9-572a-4069-95b5-63469cc0a72d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895508357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
1895508357
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.2313735116
Short name T704
Test name
Test status
Simulation time 522167640 ps
CPU time 8.4 seconds
Started Jul 05 05:34:47 PM PDT 24
Finished Jul 05 05:34:57 PM PDT 24
Peak memory 224376 kb
Host smart-544bf3f5-d9d0-4cee-9251-6deb6241c40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313735116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.2313735116
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.2023697892
Short name T661
Test name
Test status
Simulation time 101078937 ps
CPU time 3.49 seconds
Started Jul 05 05:34:47 PM PDT 24
Finished Jul 05 05:34:53 PM PDT 24
Peak memory 214460 kb
Host smart-cced62c9-fb08-4f03-9e18-e94d559520c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023697892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.2023697892
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.4263324487
Short name T247
Test name
Test status
Simulation time 221665024 ps
CPU time 24.43 seconds
Started Jul 05 05:34:45 PM PDT 24
Finished Jul 05 05:35:12 PM PDT 24
Peak memory 245492 kb
Host smart-9168cc81-f649-4aa3-aebe-036404e0d67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263324487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.4263324487
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.214523192
Short name T505
Test name
Test status
Simulation time 647779579 ps
CPU time 8.67 seconds
Started Jul 05 05:34:48 PM PDT 24
Finished Jul 05 05:34:58 PM PDT 24
Peak memory 250512 kb
Host smart-071003ef-5479-492e-bb13-e029eb65daba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214523192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.214523192
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.58568488
Short name T55
Test name
Test status
Simulation time 41600708707 ps
CPU time 273.63 seconds
Started Jul 05 05:34:45 PM PDT 24
Finished Jul 05 05:39:20 PM PDT 24
Peak memory 234216 kb
Host smart-3115da50-d593-43c0-b033-ac9cd1b0ef66
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58568488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.lc_ctrl_stress_all.58568488
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.3062403020
Short name T378
Test name
Test status
Simulation time 20471840 ps
CPU time 0.91 seconds
Started Jul 05 05:34:45 PM PDT 24
Finished Jul 05 05:34:48 PM PDT 24
Peak memory 208640 kb
Host smart-df9363db-6369-4d11-9767-a35e127362a9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062403020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.3062403020
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.664545396
Short name T27
Test name
Test status
Simulation time 23721981 ps
CPU time 1.09 seconds
Started Jul 05 05:34:46 PM PDT 24
Finished Jul 05 05:34:49 PM PDT 24
Peak memory 208564 kb
Host smart-362c5a11-6ae8-44e6-b9e1-018d6e228c9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664545396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.664545396
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.2722969070
Short name T369
Test name
Test status
Simulation time 3121776592 ps
CPU time 20.29 seconds
Started Jul 05 05:34:45 PM PDT 24
Finished Jul 05 05:35:08 PM PDT 24
Peak memory 225652 kb
Host smart-d843397a-5058-407e-9e87-527956489966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722969070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.2722969070
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.3947786482
Short name T478
Test name
Test status
Simulation time 368444233 ps
CPU time 5.63 seconds
Started Jul 05 05:34:44 PM PDT 24
Finished Jul 05 05:34:51 PM PDT 24
Peak memory 217180 kb
Host smart-b2e8dc56-61c9-43ef-85f9-3c0f23adced1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947786482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.3947786482
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.1837588862
Short name T540
Test name
Test status
Simulation time 231441402 ps
CPU time 6.45 seconds
Started Jul 05 05:34:45 PM PDT 24
Finished Jul 05 05:34:53 PM PDT 24
Peak memory 217752 kb
Host smart-f486bf02-332d-4224-8ada-fe4ae57f106e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837588862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.1837588862
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.1006939129
Short name T793
Test name
Test status
Simulation time 1134714290 ps
CPU time 13.81 seconds
Started Jul 05 05:34:46 PM PDT 24
Finished Jul 05 05:35:01 PM PDT 24
Peak memory 225508 kb
Host smart-0279d787-ad27-4f7d-8873-8028ebf8a639
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006939129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.1006939129
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.1285636508
Short name T401
Test name
Test status
Simulation time 1245249840 ps
CPU time 13.05 seconds
Started Jul 05 05:34:44 PM PDT 24
Finished Jul 05 05:34:59 PM PDT 24
Peak memory 217660 kb
Host smart-aa323eb5-ed6a-44df-9c63-1e4423bdc3a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285636508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
1285636508
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.3783919207
Short name T406
Test name
Test status
Simulation time 354461050 ps
CPU time 8.85 seconds
Started Jul 05 05:34:43 PM PDT 24
Finished Jul 05 05:34:53 PM PDT 24
Peak memory 224468 kb
Host smart-f88fc72b-f4f1-491c-a384-6a7448eca65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783919207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.3783919207
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.2417359477
Short name T452
Test name
Test status
Simulation time 23328410 ps
CPU time 1.33 seconds
Started Jul 05 05:34:44 PM PDT 24
Finished Jul 05 05:34:47 PM PDT 24
Peak memory 213168 kb
Host smart-0e12cc2c-91fb-4357-94a3-a0c10eec8413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417359477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.2417359477
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.4151104883
Short name T199
Test name
Test status
Simulation time 209819800 ps
CPU time 26.27 seconds
Started Jul 05 05:34:47 PM PDT 24
Finished Jul 05 05:35:15 PM PDT 24
Peak memory 250612 kb
Host smart-c3ac2e8d-c424-4359-8fb3-275f0711865a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151104883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.4151104883
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.3991195207
Short name T640
Test name
Test status
Simulation time 93011641 ps
CPU time 7.28 seconds
Started Jul 05 05:34:44 PM PDT 24
Finished Jul 05 05:34:53 PM PDT 24
Peak memory 246164 kb
Host smart-e8981f18-aa48-489b-beb8-beb406dc5c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991195207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.3991195207
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.1881390980
Short name T48
Test name
Test status
Simulation time 52228284264 ps
CPU time 736.06 seconds
Started Jul 05 05:34:46 PM PDT 24
Finished Jul 05 05:47:04 PM PDT 24
Peak memory 421624 kb
Host smart-190ead43-05ac-4178-ae29-5ee91bd8e7a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1881390980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all_with_rand_reset.1881390980
Directory /workspace/31.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.312309411
Short name T732
Test name
Test status
Simulation time 13237878 ps
CPU time 1.11 seconds
Started Jul 05 05:34:44 PM PDT 24
Finished Jul 05 05:34:47 PM PDT 24
Peak memory 211424 kb
Host smart-85e1b414-777b-49b3-ba52-cf00fc835e4f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312309411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ct
rl_volatile_unlock_smoke.312309411
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.3268436599
Short name T339
Test name
Test status
Simulation time 14476955 ps
CPU time 1.02 seconds
Started Jul 05 05:34:52 PM PDT 24
Finished Jul 05 05:34:55 PM PDT 24
Peak memory 208528 kb
Host smart-8881f59b-ddbf-480e-b8eb-31f1d3a40e94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268436599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.3268436599
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.4147620642
Short name T51
Test name
Test status
Simulation time 204413337 ps
CPU time 10.25 seconds
Started Jul 05 05:34:55 PM PDT 24
Finished Jul 05 05:35:06 PM PDT 24
Peak memory 225592 kb
Host smart-88f3b49e-6c31-4749-88d8-e66960bb5cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147620642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.4147620642
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.988390129
Short name T362
Test name
Test status
Simulation time 652579142 ps
CPU time 4.88 seconds
Started Jul 05 05:34:53 PM PDT 24
Finished Jul 05 05:34:59 PM PDT 24
Peak memory 217204 kb
Host smart-a5422ed8-3a1d-4334-bdc3-65606807bc1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988390129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.988390129
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.2222184521
Short name T585
Test name
Test status
Simulation time 20370384 ps
CPU time 1.53 seconds
Started Jul 05 05:34:55 PM PDT 24
Finished Jul 05 05:34:58 PM PDT 24
Peak memory 221224 kb
Host smart-ea4fd168-7fce-4c2e-b0ee-4e380c7af934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222184521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.2222184521
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.3599545856
Short name T72
Test name
Test status
Simulation time 1106390856 ps
CPU time 14.28 seconds
Started Jul 05 05:34:53 PM PDT 24
Finished Jul 05 05:35:09 PM PDT 24
Peak memory 218440 kb
Host smart-f0affcf7-ea45-44e6-b84c-8bd9755c5501
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599545856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.3599545856
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.1740799348
Short name T749
Test name
Test status
Simulation time 1325856421 ps
CPU time 13.74 seconds
Started Jul 05 05:34:52 PM PDT 24
Finished Jul 05 05:35:06 PM PDT 24
Peak memory 217708 kb
Host smart-41ddc45d-7677-4c7f-84eb-29c321a5bf0f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740799348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.1740799348
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.230924507
Short name T26
Test name
Test status
Simulation time 365921183 ps
CPU time 12.51 seconds
Started Jul 05 05:34:52 PM PDT 24
Finished Jul 05 05:35:05 PM PDT 24
Peak memory 217736 kb
Host smart-51579b67-6314-4573-92b9-51b6dc3f95d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230924507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.230924507
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.3870179814
Short name T853
Test name
Test status
Simulation time 1539943617 ps
CPU time 14.58 seconds
Started Jul 05 05:34:55 PM PDT 24
Finished Jul 05 05:35:11 PM PDT 24
Peak memory 225580 kb
Host smart-f2e0b543-7246-428b-882d-59e192663c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870179814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.3870179814
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.421659536
Short name T462
Test name
Test status
Simulation time 344332103 ps
CPU time 2.68 seconds
Started Jul 05 05:34:49 PM PDT 24
Finished Jul 05 05:34:53 PM PDT 24
Peak memory 213824 kb
Host smart-8fcbee4b-e5ca-4887-bbdb-c16b8178816c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421659536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.421659536
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.2988975661
Short name T197
Test name
Test status
Simulation time 443288708 ps
CPU time 19.58 seconds
Started Jul 05 05:34:43 PM PDT 24
Finished Jul 05 05:35:04 PM PDT 24
Peak memory 246048 kb
Host smart-38f9570d-127b-43dc-bd71-8d4000e6f3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988975661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.2988975661
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.1805340478
Short name T239
Test name
Test status
Simulation time 353692134 ps
CPU time 7.94 seconds
Started Jul 05 05:34:47 PM PDT 24
Finished Jul 05 05:34:57 PM PDT 24
Peak memory 250612 kb
Host smart-bca66e93-9280-4d60-ac5a-8efaee975d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805340478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.1805340478
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.1180547440
Short name T769
Test name
Test status
Simulation time 2633242679 ps
CPU time 67.98 seconds
Started Jul 05 05:34:52 PM PDT 24
Finished Jul 05 05:36:02 PM PDT 24
Peak memory 250540 kb
Host smart-2f68aac0-cb6e-4415-b6de-b7fdfd264968
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180547440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.1180547440
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.1244547662
Short name T573
Test name
Test status
Simulation time 35370491 ps
CPU time 0.96 seconds
Started Jul 05 05:34:46 PM PDT 24
Finished Jul 05 05:34:49 PM PDT 24
Peak memory 208440 kb
Host smart-e591e370-00db-48a3-aa19-2079d4649d4b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244547662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.1244547662
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.477839789
Short name T192
Test name
Test status
Simulation time 23648354 ps
CPU time 0.84 seconds
Started Jul 05 05:34:56 PM PDT 24
Finished Jul 05 05:34:57 PM PDT 24
Peak memory 208396 kb
Host smart-75053997-09bd-4c24-912f-766e69d9967d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477839789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.477839789
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.3665971793
Short name T496
Test name
Test status
Simulation time 190285161 ps
CPU time 9.5 seconds
Started Jul 05 05:34:52 PM PDT 24
Finished Jul 05 05:35:03 PM PDT 24
Peak memory 217708 kb
Host smart-9469be16-2103-40bc-b202-d4d46db21c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665971793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.3665971793
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.2286814447
Short name T394
Test name
Test status
Simulation time 995770881 ps
CPU time 3.48 seconds
Started Jul 05 05:34:56 PM PDT 24
Finished Jul 05 05:35:00 PM PDT 24
Peak memory 217208 kb
Host smart-87a5d56b-58dc-418a-a3d5-586a494e452c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286814447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.2286814447
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.2711079866
Short name T183
Test name
Test status
Simulation time 234532919 ps
CPU time 3.39 seconds
Started Jul 05 05:34:53 PM PDT 24
Finished Jul 05 05:34:58 PM PDT 24
Peak memory 217784 kb
Host smart-3d98b071-c003-4723-87e2-13b086114d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711079866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.2711079866
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.1912238409
Short name T159
Test name
Test status
Simulation time 402712362 ps
CPU time 9.28 seconds
Started Jul 05 05:34:54 PM PDT 24
Finished Jul 05 05:35:04 PM PDT 24
Peak memory 225480 kb
Host smart-16ed892e-93e3-406d-a352-c4eafad8b1a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912238409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.1912238409
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.2678060573
Short name T18
Test name
Test status
Simulation time 1066018957 ps
CPU time 8.42 seconds
Started Jul 05 05:34:55 PM PDT 24
Finished Jul 05 05:35:05 PM PDT 24
Peak memory 225516 kb
Host smart-b7531ba1-eb17-4a91-a646-5314c6157a2f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678060573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.2678060573
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.3056835507
Short name T835
Test name
Test status
Simulation time 1380135918 ps
CPU time 10.25 seconds
Started Jul 05 05:34:55 PM PDT 24
Finished Jul 05 05:35:06 PM PDT 24
Peak memory 217656 kb
Host smart-3321cfa4-53e8-413a-9f07-c00a8027eb4c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056835507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
3056835507
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.2879270333
Short name T399
Test name
Test status
Simulation time 5747965896 ps
CPU time 12.47 seconds
Started Jul 05 05:34:52 PM PDT 24
Finished Jul 05 05:35:06 PM PDT 24
Peak memory 225468 kb
Host smart-9fe90f52-1ec3-4fe1-a28b-d46b4a3238d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879270333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.2879270333
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.1122753048
Short name T181
Test name
Test status
Simulation time 170691964 ps
CPU time 2.9 seconds
Started Jul 05 05:34:50 PM PDT 24
Finished Jul 05 05:34:54 PM PDT 24
Peak memory 217112 kb
Host smart-63dde467-0d04-4b8d-828a-80be59abea4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122753048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.1122753048
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.1761896686
Short name T430
Test name
Test status
Simulation time 1353394349 ps
CPU time 27.81 seconds
Started Jul 05 05:34:53 PM PDT 24
Finished Jul 05 05:35:22 PM PDT 24
Peak memory 250484 kb
Host smart-e89169df-c0f8-497c-8284-36acf2d03095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761896686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.1761896686
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.453162648
Short name T530
Test name
Test status
Simulation time 73312868 ps
CPU time 8.51 seconds
Started Jul 05 05:34:52 PM PDT 24
Finished Jul 05 05:35:02 PM PDT 24
Peak memory 250512 kb
Host smart-3a30572a-9e35-4599-aad4-a000484bf9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453162648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.453162648
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.3303525528
Short name T665
Test name
Test status
Simulation time 41584102859 ps
CPU time 109.16 seconds
Started Jul 05 05:34:52 PM PDT 24
Finished Jul 05 05:36:42 PM PDT 24
Peak memory 283332 kb
Host smart-fc04cd59-472b-4439-a68c-de38b9eb356e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303525528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.3303525528
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.3036098868
Short name T457
Test name
Test status
Simulation time 26548378 ps
CPU time 0.95 seconds
Started Jul 05 05:35:04 PM PDT 24
Finished Jul 05 05:35:06 PM PDT 24
Peak memory 208476 kb
Host smart-7a30c8ab-5a1f-4428-bb81-0ab03b979154
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036098868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.3036098868
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.4022485031
Short name T489
Test name
Test status
Simulation time 20445242 ps
CPU time 1.25 seconds
Started Jul 05 05:35:04 PM PDT 24
Finished Jul 05 05:35:06 PM PDT 24
Peak memory 208612 kb
Host smart-9b50e887-056f-4511-8e30-bcc8975c2fdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022485031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.4022485031
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.2278670501
Short name T714
Test name
Test status
Simulation time 375770005 ps
CPU time 12.26 seconds
Started Jul 05 05:34:54 PM PDT 24
Finished Jul 05 05:35:07 PM PDT 24
Peak memory 217696 kb
Host smart-c466f438-6888-492e-a039-3d7da29d2ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278670501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.2278670501
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.3643267067
Short name T549
Test name
Test status
Simulation time 154219488 ps
CPU time 2.5 seconds
Started Jul 05 05:34:55 PM PDT 24
Finished Jul 05 05:34:58 PM PDT 24
Peak memory 216752 kb
Host smart-6741080e-39ab-4211-a6b3-60323939a80d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643267067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.3643267067
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.3821533710
Short name T802
Test name
Test status
Simulation time 43997619 ps
CPU time 2.2 seconds
Started Jul 05 05:35:04 PM PDT 24
Finished Jul 05 05:35:07 PM PDT 24
Peak memory 217784 kb
Host smart-7ed4ca8a-73d5-4df0-9d51-94283bcf7b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821533710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.3821533710
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.3372697221
Short name T674
Test name
Test status
Simulation time 1009896769 ps
CPU time 9.65 seconds
Started Jul 05 05:34:55 PM PDT 24
Finished Jul 05 05:35:05 PM PDT 24
Peak memory 225448 kb
Host smart-360f4470-06b0-4af0-b8ea-d165717d2f0f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372697221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.3372697221
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.545492329
Short name T707
Test name
Test status
Simulation time 240026023 ps
CPU time 7.08 seconds
Started Jul 05 05:34:52 PM PDT 24
Finished Jul 05 05:35:00 PM PDT 24
Peak memory 217656 kb
Host smart-eb1a2228-c123-4992-9351-5aeb71dc1b68
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545492329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.545492329
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.1370234792
Short name T623
Test name
Test status
Simulation time 641184500 ps
CPU time 14.33 seconds
Started Jul 05 05:34:55 PM PDT 24
Finished Jul 05 05:35:10 PM PDT 24
Peak memory 225612 kb
Host smart-81e1e53b-2ed6-41bd-bc02-590f47ba7e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370234792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.1370234792
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.2832411157
Short name T723
Test name
Test status
Simulation time 45133056 ps
CPU time 1.86 seconds
Started Jul 05 05:34:55 PM PDT 24
Finished Jul 05 05:34:57 PM PDT 24
Peak memory 217204 kb
Host smart-c1336756-2bc2-477f-a560-44e605c7520d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832411157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.2832411157
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.1129294630
Short name T519
Test name
Test status
Simulation time 864683526 ps
CPU time 37.39 seconds
Started Jul 05 05:34:55 PM PDT 24
Finished Jul 05 05:35:34 PM PDT 24
Peak memory 250516 kb
Host smart-ae63882e-8383-4e18-b066-112ba3525d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129294630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.1129294630
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.369335840
Short name T710
Test name
Test status
Simulation time 116696319 ps
CPU time 8.04 seconds
Started Jul 05 05:34:52 PM PDT 24
Finished Jul 05 05:35:01 PM PDT 24
Peak memory 250532 kb
Host smart-24d7998b-df3f-433a-90fe-69319a41ec03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369335840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.369335840
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.1876802226
Short name T348
Test name
Test status
Simulation time 7183815370 ps
CPU time 55.79 seconds
Started Jul 05 05:34:52 PM PDT 24
Finished Jul 05 05:35:49 PM PDT 24
Peak memory 254088 kb
Host smart-1f212f83-5f9b-4bef-aaf8-283d089e87cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876802226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.1876802226
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1741715560
Short name T818
Test name
Test status
Simulation time 57303954 ps
CPU time 1.75 seconds
Started Jul 05 05:34:55 PM PDT 24
Finished Jul 05 05:34:58 PM PDT 24
Peak memory 217212 kb
Host smart-b415f933-ee21-43f2-8ea1-2097c4bf82ac
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741715560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.1741715560
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.3991315212
Short name T843
Test name
Test status
Simulation time 36853054 ps
CPU time 0.99 seconds
Started Jul 05 05:35:03 PM PDT 24
Finished Jul 05 05:35:05 PM PDT 24
Peak memory 208604 kb
Host smart-43c2644c-b82c-42c2-97ed-79bc274836f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991315212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.3991315212
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.760177212
Short name T14
Test name
Test status
Simulation time 3433309498 ps
CPU time 11.82 seconds
Started Jul 05 05:35:03 PM PDT 24
Finished Jul 05 05:35:16 PM PDT 24
Peak memory 218592 kb
Host smart-0545bb3e-a2f2-4c14-a5fa-857688ad1fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760177212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.760177212
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.2826653136
Short name T11
Test name
Test status
Simulation time 1870564311 ps
CPU time 22.48 seconds
Started Jul 05 05:35:01 PM PDT 24
Finished Jul 05 05:35:25 PM PDT 24
Peak memory 217140 kb
Host smart-6525ba88-b372-4a62-bbdb-1bcdc99b69aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826653136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.2826653136
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.798181894
Short name T274
Test name
Test status
Simulation time 90017884 ps
CPU time 3.21 seconds
Started Jul 05 05:35:01 PM PDT 24
Finished Jul 05 05:35:05 PM PDT 24
Peak memory 217728 kb
Host smart-d5486eb6-4b32-4e99-aae1-48f4d96e3dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798181894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.798181894
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.2859296115
Short name T53
Test name
Test status
Simulation time 325102056 ps
CPU time 13.68 seconds
Started Jul 05 05:35:01 PM PDT 24
Finished Jul 05 05:35:16 PM PDT 24
Peak memory 219476 kb
Host smart-7cea9096-e7c1-4353-a7f0-97e9eb69945b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859296115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.2859296115
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.289155784
Short name T474
Test name
Test status
Simulation time 869979727 ps
CPU time 21.81 seconds
Started Jul 05 05:34:59 PM PDT 24
Finished Jul 05 05:35:21 PM PDT 24
Peak memory 225448 kb
Host smart-c4e6d5b4-f5e9-40a4-a3d5-dd3224b5b769
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289155784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_di
gest.289155784
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.286266969
Short name T351
Test name
Test status
Simulation time 969164148 ps
CPU time 17.5 seconds
Started Jul 05 05:35:00 PM PDT 24
Finished Jul 05 05:35:18 PM PDT 24
Peak memory 225528 kb
Host smart-5d4da01d-9023-43ef-bb1a-ffab60aea1fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286266969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.286266969
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.1293307398
Short name T448
Test name
Test status
Simulation time 127966385 ps
CPU time 1.17 seconds
Started Jul 05 05:34:52 PM PDT 24
Finished Jul 05 05:34:54 PM PDT 24
Peak memory 217116 kb
Host smart-064567a8-d3f8-4a8c-88dd-44528ea8a50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293307398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.1293307398
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.3153949038
Short name T563
Test name
Test status
Simulation time 2539292541 ps
CPU time 30.23 seconds
Started Jul 05 05:35:00 PM PDT 24
Finished Jul 05 05:35:32 PM PDT 24
Peak memory 244392 kb
Host smart-22560b86-b296-4570-94ff-5450f3095f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153949038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.3153949038
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.330102499
Short name T572
Test name
Test status
Simulation time 76763455 ps
CPU time 3.24 seconds
Started Jul 05 05:35:01 PM PDT 24
Finished Jul 05 05:35:06 PM PDT 24
Peak memory 222308 kb
Host smart-6a54a74e-830f-45af-a918-9a9f2e6363a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330102499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.330102499
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.105676833
Short name T830
Test name
Test status
Simulation time 32050963136 ps
CPU time 159.38 seconds
Started Jul 05 05:35:03 PM PDT 24
Finished Jul 05 05:37:43 PM PDT 24
Peak memory 283332 kb
Host smart-07a2933b-f9bf-4f98-aca1-269e3b7f20a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105676833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.105676833
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.3190864687
Short name T684
Test name
Test status
Simulation time 9046730946 ps
CPU time 292.83 seconds
Started Jul 05 05:35:01 PM PDT 24
Finished Jul 05 05:39:55 PM PDT 24
Peak memory 275900 kb
Host smart-5aed6f96-3611-4ea3-8dae-067d00dfb723
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3190864687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.3190864687
Directory /workspace/35.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.2404962104
Short name T588
Test name
Test status
Simulation time 42991668 ps
CPU time 0.91 seconds
Started Jul 05 05:34:53 PM PDT 24
Finished Jul 05 05:34:55 PM PDT 24
Peak memory 211364 kb
Host smart-94e6e38e-7161-462d-8832-e0e32042fe3f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404962104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.2404962104
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.3625314766
Short name T536
Test name
Test status
Simulation time 104278974 ps
CPU time 1.21 seconds
Started Jul 05 05:35:01 PM PDT 24
Finished Jul 05 05:35:04 PM PDT 24
Peak memory 208540 kb
Host smart-baef338a-abdf-4320-a8b9-c9f795393a59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625314766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.3625314766
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.3925393664
Short name T435
Test name
Test status
Simulation time 468619812 ps
CPU time 14.31 seconds
Started Jul 05 05:35:01 PM PDT 24
Finished Jul 05 05:35:16 PM PDT 24
Peak memory 225532 kb
Host smart-972d4c30-d3a4-4000-97d9-eb527125985c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925393664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.3925393664
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.1494947762
Short name T724
Test name
Test status
Simulation time 93731786 ps
CPU time 3.2 seconds
Started Jul 05 05:35:02 PM PDT 24
Finished Jul 05 05:35:06 PM PDT 24
Peak memory 216684 kb
Host smart-f6f3eb0d-e789-46f8-a3d9-f2b1cef3fb95
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494947762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.1494947762
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.3987412665
Short name T311
Test name
Test status
Simulation time 332976007 ps
CPU time 3.4 seconds
Started Jul 05 05:35:00 PM PDT 24
Finished Jul 05 05:35:04 PM PDT 24
Peak memory 217780 kb
Host smart-62f32cf7-1d1a-411b-9b36-6c6d0e15319e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987412665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.3987412665
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.3069411455
Short name T251
Test name
Test status
Simulation time 1277213359 ps
CPU time 11.37 seconds
Started Jul 05 05:35:01 PM PDT 24
Finished Jul 05 05:35:14 PM PDT 24
Peak memory 218440 kb
Host smart-78e3ae39-308c-44e3-80f9-8d04c88984dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069411455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.3069411455
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.2112460488
Short name T12
Test name
Test status
Simulation time 363729048 ps
CPU time 10.88 seconds
Started Jul 05 05:35:05 PM PDT 24
Finished Jul 05 05:35:17 PM PDT 24
Peak memory 225528 kb
Host smart-71d419fb-ede6-411c-93c0-7ef97bd431d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112460488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.2112460488
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.2852686513
Short name T803
Test name
Test status
Simulation time 361643131 ps
CPU time 12.27 seconds
Started Jul 05 05:35:01 PM PDT 24
Finished Jul 05 05:35:15 PM PDT 24
Peak memory 217676 kb
Host smart-fb77b7a7-88ae-407a-81c1-8c587c6766ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852686513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
2852686513
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.3973366806
Short name T821
Test name
Test status
Simulation time 3958774808 ps
CPU time 16.97 seconds
Started Jul 05 05:35:03 PM PDT 24
Finished Jul 05 05:35:21 PM PDT 24
Peak memory 225648 kb
Host smart-cb83003e-f992-44d9-87ea-0e1dee5004b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973366806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.3973366806
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.3080702301
Short name T83
Test name
Test status
Simulation time 41196760 ps
CPU time 2.94 seconds
Started Jul 05 05:35:01 PM PDT 24
Finished Jul 05 05:35:05 PM PDT 24
Peak memory 223012 kb
Host smart-fb550cb5-b418-4dc1-8404-e721cc6e523c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080702301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.3080702301
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.2144192809
Short name T243
Test name
Test status
Simulation time 258285034 ps
CPU time 23.26 seconds
Started Jul 05 05:35:00 PM PDT 24
Finished Jul 05 05:35:24 PM PDT 24
Peak memory 250540 kb
Host smart-a0d669c5-9f57-44a9-84b6-269c459fc9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144192809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.2144192809
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.4043736679
Short name T98
Test name
Test status
Simulation time 70277537 ps
CPU time 4.09 seconds
Started Jul 05 05:35:01 PM PDT 24
Finished Jul 05 05:35:06 PM PDT 24
Peak memory 222448 kb
Host smart-65cdede5-bf03-4be9-b84a-8698bdfe3893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043736679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.4043736679
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.1187467768
Short name T593
Test name
Test status
Simulation time 3844268899 ps
CPU time 113.88 seconds
Started Jul 05 05:35:00 PM PDT 24
Finished Jul 05 05:36:55 PM PDT 24
Peak memory 276368 kb
Host smart-977d790e-6f42-4d0d-9fa8-ed9e2a08749d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187467768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.1187467768
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.547886711
Short name T576
Test name
Test status
Simulation time 17208488 ps
CPU time 0.79 seconds
Started Jul 05 05:35:00 PM PDT 24
Finished Jul 05 05:35:01 PM PDT 24
Peak memory 208248 kb
Host smart-950e1ebf-636c-481e-b77d-c8bfe047a16e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547886711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ct
rl_volatile_unlock_smoke.547886711
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.4158551239
Short name T841
Test name
Test status
Simulation time 1121456689 ps
CPU time 15.77 seconds
Started Jul 05 05:35:03 PM PDT 24
Finished Jul 05 05:35:20 PM PDT 24
Peak memory 217680 kb
Host smart-480d3374-55d9-43db-8329-fa1cbdcca002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158551239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.4158551239
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.2290343934
Short name T205
Test name
Test status
Simulation time 589476103 ps
CPU time 3.81 seconds
Started Jul 05 05:35:01 PM PDT 24
Finished Jul 05 05:35:06 PM PDT 24
Peak memory 217108 kb
Host smart-939e0fb4-c548-4e60-aeac-6e1fa5149695
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290343934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.2290343934
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.996293455
Short name T330
Test name
Test status
Simulation time 69065811 ps
CPU time 1.58 seconds
Started Jul 05 05:35:02 PM PDT 24
Finished Jul 05 05:35:05 PM PDT 24
Peak memory 217716 kb
Host smart-7973c9b1-1e00-45f8-8bf3-6a48d97899a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996293455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.996293455
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.2988060139
Short name T43
Test name
Test status
Simulation time 627776507 ps
CPU time 8.94 seconds
Started Jul 05 05:35:05 PM PDT 24
Finished Jul 05 05:35:15 PM PDT 24
Peak memory 218436 kb
Host smart-afda4c38-ada4-4c56-8ef3-2fa31da15cec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988060139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.2988060139
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.2382467825
Short name T518
Test name
Test status
Simulation time 1039036400 ps
CPU time 7.89 seconds
Started Jul 05 05:34:59 PM PDT 24
Finished Jul 05 05:35:08 PM PDT 24
Peak memory 225524 kb
Host smart-bb6b2ff0-08c4-40dc-a6b5-86c2cd25e0a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382467825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.2382467825
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.316712144
Short name T334
Test name
Test status
Simulation time 1910221979 ps
CPU time 10.41 seconds
Started Jul 05 05:35:01 PM PDT 24
Finished Jul 05 05:35:13 PM PDT 24
Peak memory 225432 kb
Host smart-9b777e50-6efa-4d7f-8323-b2aa6a8842a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316712144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.316712144
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.4261417652
Short name T516
Test name
Test status
Simulation time 1359404204 ps
CPU time 11.67 seconds
Started Jul 05 05:35:00 PM PDT 24
Finished Jul 05 05:35:13 PM PDT 24
Peak memory 225584 kb
Host smart-47cfbc2a-c323-4756-a4b6-c7bf5c6a81ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261417652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.4261417652
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.1954975550
Short name T346
Test name
Test status
Simulation time 55806006 ps
CPU time 3.34 seconds
Started Jul 05 05:35:06 PM PDT 24
Finished Jul 05 05:35:10 PM PDT 24
Peak memory 214536 kb
Host smart-f98e0f6e-30d3-4809-80a9-b806c48a5d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954975550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.1954975550
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.3554346016
Short name T772
Test name
Test status
Simulation time 266618109 ps
CPU time 25.76 seconds
Started Jul 05 05:35:02 PM PDT 24
Finished Jul 05 05:35:29 PM PDT 24
Peak memory 250536 kb
Host smart-157c4c79-3fb4-428d-9ac0-a40340df7863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554346016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.3554346016
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.973371015
Short name T624
Test name
Test status
Simulation time 99980698 ps
CPU time 7.61 seconds
Started Jul 05 05:35:05 PM PDT 24
Finished Jul 05 05:35:14 PM PDT 24
Peak memory 250488 kb
Host smart-fb41a7d8-80d7-479e-9648-b65f27ef7b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973371015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.973371015
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.2927541217
Short name T831
Test name
Test status
Simulation time 144450646881 ps
CPU time 539.72 seconds
Started Jul 05 05:35:00 PM PDT 24
Finished Jul 05 05:44:01 PM PDT 24
Peak memory 227532 kb
Host smart-9a62607b-21ff-4e91-8111-4714ee69132f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927541217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.2927541217
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.2072008100
Short name T96
Test name
Test status
Simulation time 76081910486 ps
CPU time 607.3 seconds
Started Jul 05 05:35:01 PM PDT 24
Finished Jul 05 05:45:09 PM PDT 24
Peak memory 263692 kb
Host smart-c975488c-4304-423c-9c55-7f802caed4f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2072008100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.2072008100
Directory /workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.691654230
Short name T47
Test name
Test status
Simulation time 121000639 ps
CPU time 0.83 seconds
Started Jul 05 05:35:01 PM PDT 24
Finished Jul 05 05:35:04 PM PDT 24
Peak memory 208192 kb
Host smart-bb367d53-ad97-4e59-ae16-17fa6985443d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691654230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ct
rl_volatile_unlock_smoke.691654230
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.2804821847
Short name T560
Test name
Test status
Simulation time 17532846 ps
CPU time 0.87 seconds
Started Jul 05 05:35:09 PM PDT 24
Finished Jul 05 05:35:11 PM PDT 24
Peak memory 208532 kb
Host smart-cd3c3edf-2bcc-4d6d-a15a-5827164f1134
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804821847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.2804821847
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.1040684543
Short name T552
Test name
Test status
Simulation time 2673041064 ps
CPU time 14.63 seconds
Started Jul 05 05:35:12 PM PDT 24
Finished Jul 05 05:35:27 PM PDT 24
Peak memory 225624 kb
Host smart-87805da7-ccf7-41d0-baa0-4af451448b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040684543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.1040684543
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.2699006988
Short name T827
Test name
Test status
Simulation time 2856716002 ps
CPU time 5.47 seconds
Started Jul 05 05:35:08 PM PDT 24
Finished Jul 05 05:35:14 PM PDT 24
Peak memory 217268 kb
Host smart-1b16a9b0-df90-409b-b2c9-e35a80ad0ddd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699006988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.2699006988
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.3481383864
Short name T778
Test name
Test status
Simulation time 90125579 ps
CPU time 4.52 seconds
Started Jul 05 05:35:08 PM PDT 24
Finished Jul 05 05:35:13 PM PDT 24
Peak memory 217788 kb
Host smart-6d40f4dc-387e-4777-b24a-e32375c193de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481383864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.3481383864
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.848993552
Short name T160
Test name
Test status
Simulation time 554367578 ps
CPU time 8.49 seconds
Started Jul 05 05:35:12 PM PDT 24
Finished Jul 05 05:35:22 PM PDT 24
Peak memory 225584 kb
Host smart-87ff905d-1da4-4dc2-9c9d-90b170b2d532
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848993552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.848993552
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.3967876114
Short name T791
Test name
Test status
Simulation time 229674592 ps
CPU time 10.04 seconds
Started Jul 05 05:35:07 PM PDT 24
Finished Jul 05 05:35:18 PM PDT 24
Peak memory 225528 kb
Host smart-0cf6d499-199e-46e9-8580-22b993960a0a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967876114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.3967876114
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.411497991
Short name T627
Test name
Test status
Simulation time 785006085 ps
CPU time 10.09 seconds
Started Jul 05 05:35:12 PM PDT 24
Finished Jul 05 05:35:23 PM PDT 24
Peak memory 225548 kb
Host smart-fec0d53f-7558-4d41-8e4b-f136b04d6672
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411497991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.411497991
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.3233043344
Short name T461
Test name
Test status
Simulation time 454325316 ps
CPU time 12.13 seconds
Started Jul 05 05:35:09 PM PDT 24
Finished Jul 05 05:35:22 PM PDT 24
Peak memory 225008 kb
Host smart-d3e38da5-3cd7-4a7b-b75d-de967e6bdfce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233043344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.3233043344
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.153128849
Short name T203
Test name
Test status
Simulation time 26626876 ps
CPU time 2 seconds
Started Jul 05 05:35:01 PM PDT 24
Finished Jul 05 05:35:04 PM PDT 24
Peak memory 217164 kb
Host smart-2acc6329-b432-4df7-926f-1aeb9fcd5a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153128849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.153128849
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.1078641911
Short name T712
Test name
Test status
Simulation time 1212246286 ps
CPU time 33.19 seconds
Started Jul 05 05:35:08 PM PDT 24
Finished Jul 05 05:35:42 PM PDT 24
Peak memory 250512 kb
Host smart-b7a301c6-c2cd-4bdd-8ad3-7688ad898abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078641911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.1078641911
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.1341065734
Short name T467
Test name
Test status
Simulation time 99975555 ps
CPU time 7.21 seconds
Started Jul 05 05:35:09 PM PDT 24
Finished Jul 05 05:35:17 PM PDT 24
Peak memory 250028 kb
Host smart-f9f6e7f1-e942-42cb-a78e-c4e8d8e32c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341065734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.1341065734
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.2565715427
Short name T673
Test name
Test status
Simulation time 2509267451 ps
CPU time 83.96 seconds
Started Jul 05 05:35:08 PM PDT 24
Finished Jul 05 05:36:32 PM PDT 24
Peak memory 225656 kb
Host smart-07643361-3151-42b4-9c37-ba109439f483
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565715427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.2565715427
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.3772714146
Short name T686
Test name
Test status
Simulation time 12731289 ps
CPU time 0.86 seconds
Started Jul 05 05:35:08 PM PDT 24
Finished Jul 05 05:35:09 PM PDT 24
Peak memory 208588 kb
Host smart-53855fac-0cc3-4ce8-b881-f1023fcee739
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772714146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.3772714146
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.232461877
Short name T318
Test name
Test status
Simulation time 71413184 ps
CPU time 0.93 seconds
Started Jul 05 05:35:11 PM PDT 24
Finished Jul 05 05:35:13 PM PDT 24
Peak memory 208760 kb
Host smart-7214d8a3-6fc7-40fc-8eab-4c2ccecdde21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232461877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.232461877
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.2134788136
Short name T411
Test name
Test status
Simulation time 461773224 ps
CPU time 17.24 seconds
Started Jul 05 05:35:11 PM PDT 24
Finished Jul 05 05:35:29 PM PDT 24
Peak memory 218004 kb
Host smart-16797ef4-58d9-41f2-a20e-6f08df386615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134788136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.2134788136
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.471433711
Short name T408
Test name
Test status
Simulation time 1869721137 ps
CPU time 11.76 seconds
Started Jul 05 05:35:12 PM PDT 24
Finished Jul 05 05:35:25 PM PDT 24
Peak memory 217176 kb
Host smart-d88ca5ba-32cd-4668-8243-4c5027a840a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471433711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.471433711
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.3448517737
Short name T614
Test name
Test status
Simulation time 92411382 ps
CPU time 2.71 seconds
Started Jul 05 05:35:10 PM PDT 24
Finished Jul 05 05:35:14 PM PDT 24
Peak memory 217720 kb
Host smart-e8c547f6-3ed7-4d0d-9363-1da90fe18e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448517737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.3448517737
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.2904082894
Short name T100
Test name
Test status
Simulation time 610723363 ps
CPU time 15.9 seconds
Started Jul 05 05:35:12 PM PDT 24
Finished Jul 05 05:35:29 PM PDT 24
Peak memory 225588 kb
Host smart-9aff0451-9566-4c56-bfcf-0a2531ffa0e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904082894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.2904082894
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.3327983134
Short name T370
Test name
Test status
Simulation time 1444448235 ps
CPU time 11.81 seconds
Started Jul 05 05:35:14 PM PDT 24
Finished Jul 05 05:35:27 PM PDT 24
Peak memory 225524 kb
Host smart-959498e5-9f45-4001-a289-be3313171420
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327983134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.3327983134
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.1649119014
Short name T762
Test name
Test status
Simulation time 964058712 ps
CPU time 17.54 seconds
Started Jul 05 05:35:11 PM PDT 24
Finished Jul 05 05:35:29 PM PDT 24
Peak memory 225468 kb
Host smart-7448a47b-515b-4c55-8250-7effa3a448e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649119014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
1649119014
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.3292881976
Short name T349
Test name
Test status
Simulation time 398031170 ps
CPU time 9.89 seconds
Started Jul 05 05:35:10 PM PDT 24
Finished Jul 05 05:35:21 PM PDT 24
Peak memory 225588 kb
Host smart-f341447e-3f1e-497e-ba4c-7d45def2d812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292881976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.3292881976
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.376550853
Short name T376
Test name
Test status
Simulation time 453309303 ps
CPU time 2.04 seconds
Started Jul 05 05:35:09 PM PDT 24
Finished Jul 05 05:35:12 PM PDT 24
Peak memory 213896 kb
Host smart-322a2244-4764-4753-8f6e-9be0d44ee7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376550853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.376550853
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.2032343171
Short name T375
Test name
Test status
Simulation time 1946069165 ps
CPU time 24.81 seconds
Started Jul 05 05:35:11 PM PDT 24
Finished Jul 05 05:35:37 PM PDT 24
Peak memory 250516 kb
Host smart-fbcda9e8-0dd1-4d12-939c-eec384e2aaf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032343171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.2032343171
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.513480901
Short name T244
Test name
Test status
Simulation time 130159204 ps
CPU time 9.92 seconds
Started Jul 05 05:35:08 PM PDT 24
Finished Jul 05 05:35:18 PM PDT 24
Peak memory 250532 kb
Host smart-13eb30db-571d-4276-84ed-6c1287d54ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513480901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.513480901
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.4062654977
Short name T638
Test name
Test status
Simulation time 255036603 ps
CPU time 11.16 seconds
Started Jul 05 05:35:10 PM PDT 24
Finished Jul 05 05:35:22 PM PDT 24
Peak memory 243360 kb
Host smart-41579ef0-21c2-452a-b341-dbb9db15d764
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062654977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.4062654977
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.4180281995
Short name T91
Test name
Test status
Simulation time 84917925999 ps
CPU time 509.17 seconds
Started Jul 05 05:35:08 PM PDT 24
Finished Jul 05 05:43:38 PM PDT 24
Peak memory 438136 kb
Host smart-d5cc030e-3145-4568-9b30-a98fcf63dd49
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4180281995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.4180281995
Directory /workspace/39.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.4142643098
Short name T396
Test name
Test status
Simulation time 36454922 ps
CPU time 0.86 seconds
Started Jul 05 05:35:14 PM PDT 24
Finished Jul 05 05:35:15 PM PDT 24
Peak memory 208384 kb
Host smart-08bc8e3e-dca3-4172-8c14-e6e5d941beee
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142643098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.4142643098
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.3446517899
Short name T513
Test name
Test status
Simulation time 71862682 ps
CPU time 1.02 seconds
Started Jul 05 05:33:12 PM PDT 24
Finished Jul 05 05:33:14 PM PDT 24
Peak memory 208432 kb
Host smart-2f84eb1d-af03-4f5a-9f24-57015814a963
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446517899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.3446517899
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.379615255
Short name T599
Test name
Test status
Simulation time 11666368 ps
CPU time 0.87 seconds
Started Jul 05 05:33:09 PM PDT 24
Finished Jul 05 05:33:10 PM PDT 24
Peak memory 208308 kb
Host smart-e3af1cf3-b3c7-4aa8-92a7-7231a56fe03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379615255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.379615255
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.3004727723
Short name T255
Test name
Test status
Simulation time 254538379 ps
CPU time 7.72 seconds
Started Jul 05 05:33:07 PM PDT 24
Finished Jul 05 05:33:16 PM PDT 24
Peak memory 217792 kb
Host smart-6e7ccda6-4d02-43cc-9e10-eb261cc065ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004727723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.3004727723
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.3708065536
Short name T33
Test name
Test status
Simulation time 1820024711 ps
CPU time 5.58 seconds
Started Jul 05 05:33:06 PM PDT 24
Finished Jul 05 05:33:13 PM PDT 24
Peak memory 216748 kb
Host smart-9b3a1664-a5b9-454a-aabf-c85e928c0d2d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708065536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.3708065536
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.2672581846
Short name T495
Test name
Test status
Simulation time 1764269459 ps
CPU time 29.85 seconds
Started Jul 05 05:33:09 PM PDT 24
Finished Jul 05 05:33:39 PM PDT 24
Peak memory 217584 kb
Host smart-6913c827-1dce-407f-bfa3-5c649f2bef52
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672581846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.2672581846
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.2616726687
Short name T702
Test name
Test status
Simulation time 597129524 ps
CPU time 4.73 seconds
Started Jul 05 05:33:17 PM PDT 24
Finished Jul 05 05:33:22 PM PDT 24
Peak memory 217228 kb
Host smart-3e94af59-cded-4644-887c-088d7fe74a0f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616726687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.2
616726687
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.2555094204
Short name T632
Test name
Test status
Simulation time 368452038 ps
CPU time 6.86 seconds
Started Jul 05 05:33:09 PM PDT 24
Finished Jul 05 05:33:17 PM PDT 24
Peak memory 217660 kb
Host smart-ce967f9d-d480-47eb-a90a-4b367662d8e0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555094204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.2555094204
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.2422805778
Short name T741
Test name
Test status
Simulation time 5515917819 ps
CPU time 18.96 seconds
Started Jul 05 05:33:14 PM PDT 24
Finished Jul 05 05:33:34 PM PDT 24
Peak memory 217248 kb
Host smart-be7817c7-af94-493e-b8f2-888e57ebd5bd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422805778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.2422805778
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.958362403
Short name T393
Test name
Test status
Simulation time 720652334 ps
CPU time 17.68 seconds
Started Jul 05 05:33:11 PM PDT 24
Finished Jul 05 05:33:29 PM PDT 24
Peak memory 217148 kb
Host smart-b258d98d-a224-4f79-b2e8-a974ed8a1e5f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958362403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.958362403
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.441689309
Short name T357
Test name
Test status
Simulation time 5019694942 ps
CPU time 58.32 seconds
Started Jul 05 05:33:08 PM PDT 24
Finished Jul 05 05:34:07 PM PDT 24
Peak memory 283220 kb
Host smart-bbc4dc4d-e057-453f-b547-2585de6643d9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441689309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_state_failure.441689309
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.2726184064
Short name T301
Test name
Test status
Simulation time 447567399 ps
CPU time 13.96 seconds
Started Jul 05 05:33:10 PM PDT 24
Finished Jul 05 05:33:24 PM PDT 24
Peak memory 248652 kb
Host smart-18166f02-9384-47e2-8e43-47c76e935693
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726184064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.2726184064
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.3575548143
Short name T694
Test name
Test status
Simulation time 281086464 ps
CPU time 2.05 seconds
Started Jul 05 05:33:11 PM PDT 24
Finished Jul 05 05:33:14 PM PDT 24
Peak memory 217788 kb
Host smart-228059ba-efdd-4d99-8c37-41ccff5fd730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575548143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.3575548143
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.319664679
Short name T70
Test name
Test status
Simulation time 402546326 ps
CPU time 7.28 seconds
Started Jul 05 05:33:06 PM PDT 24
Finished Jul 05 05:33:14 PM PDT 24
Peak memory 217204 kb
Host smart-1665b9ad-e24f-4ac1-aaf1-c682bf2324b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319664679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.319664679
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.3341862833
Short name T67
Test name
Test status
Simulation time 469245351 ps
CPU time 24.1 seconds
Started Jul 05 05:33:15 PM PDT 24
Finished Jul 05 05:33:41 PM PDT 24
Peak memory 282096 kb
Host smart-de920217-25ce-4264-87a7-721b797dd6e5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341862833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.3341862833
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.479335703
Short name T286
Test name
Test status
Simulation time 313471607 ps
CPU time 9.65 seconds
Started Jul 05 05:33:15 PM PDT 24
Finished Jul 05 05:33:25 PM PDT 24
Peak memory 225380 kb
Host smart-9c1c1513-f282-4188-a02d-1c6828c7b8a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479335703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_dig
est.479335703
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.3334518772
Short name T551
Test name
Test status
Simulation time 2769260779 ps
CPU time 13.65 seconds
Started Jul 05 05:33:14 PM PDT 24
Finished Jul 05 05:33:29 PM PDT 24
Peak memory 217796 kb
Host smart-7c25b03e-00bb-4952-ad17-df08215bebdd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334518772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.3
334518772
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.2601185865
Short name T506
Test name
Test status
Simulation time 340863209 ps
CPU time 12.28 seconds
Started Jul 05 05:33:06 PM PDT 24
Finished Jul 05 05:33:19 PM PDT 24
Peak memory 217864 kb
Host smart-9f552aa6-8bd7-40f0-b127-379f4ff747b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601185865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.2601185865
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.4105614089
Short name T752
Test name
Test status
Simulation time 92477458 ps
CPU time 1.54 seconds
Started Jul 05 05:33:47 PM PDT 24
Finished Jul 05 05:33:49 PM PDT 24
Peak memory 213340 kb
Host smart-84ba0c07-5556-453e-bc68-478f1210823f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105614089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.4105614089
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.4002193981
Short name T331
Test name
Test status
Simulation time 1041371224 ps
CPU time 25.68 seconds
Started Jul 05 05:33:09 PM PDT 24
Finished Jul 05 05:33:35 PM PDT 24
Peak memory 250552 kb
Host smart-3f45c38b-4566-44eb-90d2-1d89fb27f2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002193981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.4002193981
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.1610236421
Short name T546
Test name
Test status
Simulation time 154971402 ps
CPU time 7.38 seconds
Started Jul 05 05:33:07 PM PDT 24
Finished Jul 05 05:33:15 PM PDT 24
Peak memory 250056 kb
Host smart-fc1af914-8350-4e6c-af66-ebd61f61d709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610236421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.1610236421
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.634603182
Short name T8
Test name
Test status
Simulation time 18906556926 ps
CPU time 115.83 seconds
Started Jul 05 05:33:12 PM PDT 24
Finished Jul 05 05:35:09 PM PDT 24
Peak memory 281580 kb
Host smart-a7d82fad-97fa-4ab5-b915-f8c7bdbd367c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634603182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.634603182
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.4273439647
Short name T353
Test name
Test status
Simulation time 34432262 ps
CPU time 1.14 seconds
Started Jul 05 05:33:13 PM PDT 24
Finished Jul 05 05:33:15 PM PDT 24
Peak memory 217184 kb
Host smart-f121120f-89c5-407e-b589-ddf3b677167a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273439647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.4273439647
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.3308842710
Short name T645
Test name
Test status
Simulation time 57034487 ps
CPU time 1.12 seconds
Started Jul 05 05:35:13 PM PDT 24
Finished Jul 05 05:35:15 PM PDT 24
Peak memory 208536 kb
Host smart-c72c9984-c107-4125-a30f-e2c8e3deb4c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308842710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.3308842710
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.2310752340
Short name T557
Test name
Test status
Simulation time 974950180 ps
CPU time 16.16 seconds
Started Jul 05 05:35:09 PM PDT 24
Finished Jul 05 05:35:26 PM PDT 24
Peak memory 217728 kb
Host smart-e50abab9-b5a0-463f-a027-c96493a90121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310752340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.2310752340
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.2841388497
Short name T79
Test name
Test status
Simulation time 231825371 ps
CPU time 6.17 seconds
Started Jul 05 05:35:12 PM PDT 24
Finished Jul 05 05:35:20 PM PDT 24
Peak memory 216756 kb
Host smart-1204b77e-18d1-4538-9f57-d830f9d89539
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841388497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.2841388497
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.1332516884
Short name T444
Test name
Test status
Simulation time 63876096 ps
CPU time 2.14 seconds
Started Jul 05 05:35:11 PM PDT 24
Finished Jul 05 05:35:15 PM PDT 24
Peak memory 217784 kb
Host smart-a47ac495-654d-41c6-8931-85fa3a72f1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332516884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.1332516884
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.253277632
Short name T298
Test name
Test status
Simulation time 1841464363 ps
CPU time 15.98 seconds
Started Jul 05 05:35:09 PM PDT 24
Finished Jul 05 05:35:26 PM PDT 24
Peak memory 218504 kb
Host smart-465573f6-d37a-4f86-9481-38da8d09ab2b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253277632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.253277632
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.1134077906
Short name T410
Test name
Test status
Simulation time 610749215 ps
CPU time 9.62 seconds
Started Jul 05 05:35:11 PM PDT 24
Finished Jul 05 05:35:21 PM PDT 24
Peak memory 225472 kb
Host smart-f33d5b58-fb8a-466a-9685-058fef436d00
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134077906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.1134077906
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.3743961944
Short name T417
Test name
Test status
Simulation time 1145782068 ps
CPU time 18.57 seconds
Started Jul 05 05:35:08 PM PDT 24
Finished Jul 05 05:35:27 PM PDT 24
Peak memory 217748 kb
Host smart-596dbed8-0037-4ba4-8efd-11a927c5ea38
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743961944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
3743961944
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.1585965835
Short name T471
Test name
Test status
Simulation time 1812893386 ps
CPU time 12.03 seconds
Started Jul 05 05:35:08 PM PDT 24
Finished Jul 05 05:35:21 PM PDT 24
Peak memory 224328 kb
Host smart-9c0871ee-f78b-4620-867a-651e3c866889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585965835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.1585965835
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.2778645137
Short name T323
Test name
Test status
Simulation time 495144570 ps
CPU time 8.28 seconds
Started Jul 05 05:35:09 PM PDT 24
Finished Jul 05 05:35:18 PM PDT 24
Peak memory 217208 kb
Host smart-c581ddd1-cc8e-4025-8284-e7d9ff1064c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778645137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.2778645137
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.4254178396
Short name T520
Test name
Test status
Simulation time 569426234 ps
CPU time 28.67 seconds
Started Jul 05 05:35:11 PM PDT 24
Finished Jul 05 05:35:40 PM PDT 24
Peak memory 250752 kb
Host smart-52e5eb02-dc90-45d3-9933-f32cbf31f842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254178396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.4254178396
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.2414800715
Short name T501
Test name
Test status
Simulation time 103987616 ps
CPU time 8.06 seconds
Started Jul 05 05:35:10 PM PDT 24
Finished Jul 05 05:35:19 PM PDT 24
Peak memory 247000 kb
Host smart-ad5d8759-eb0b-41a8-ac09-1c31d4c3a202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414800715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.2414800715
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.1897889246
Short name T493
Test name
Test status
Simulation time 2371460377 ps
CPU time 72.35 seconds
Started Jul 05 05:35:10 PM PDT 24
Finished Jul 05 05:36:23 PM PDT 24
Peak memory 268168 kb
Host smart-1447f848-d932-42da-af99-3ab6b0560fa6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897889246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.1897889246
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.1911396278
Short name T653
Test name
Test status
Simulation time 42678250 ps
CPU time 0.95 seconds
Started Jul 05 05:35:11 PM PDT 24
Finished Jul 05 05:35:13 PM PDT 24
Peak memory 211300 kb
Host smart-12fe6700-8214-40aa-a7f2-e3172f2a714e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911396278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.1911396278
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.2346751872
Short name T629
Test name
Test status
Simulation time 16255852 ps
CPU time 1.06 seconds
Started Jul 05 05:35:19 PM PDT 24
Finished Jul 05 05:35:24 PM PDT 24
Peak memory 208608 kb
Host smart-9dc7fd8c-3b8d-458d-ac75-1abf53ae7f6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346751872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.2346751872
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.3987005575
Short name T823
Test name
Test status
Simulation time 767523103 ps
CPU time 8.2 seconds
Started Jul 05 05:35:11 PM PDT 24
Finished Jul 05 05:35:20 PM PDT 24
Peak memory 225544 kb
Host smart-b3a5b55a-b661-4859-8359-b09702d0e898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987005575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.3987005575
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.2055747561
Short name T454
Test name
Test status
Simulation time 6317903285 ps
CPU time 4.57 seconds
Started Jul 05 05:35:15 PM PDT 24
Finished Jul 05 05:35:21 PM PDT 24
Peak memory 217248 kb
Host smart-53b90b9d-d056-4a59-a33f-ff4bc854e5ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055747561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.2055747561
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.3621602097
Short name T728
Test name
Test status
Simulation time 37039245 ps
CPU time 2.39 seconds
Started Jul 05 05:35:09 PM PDT 24
Finished Jul 05 05:35:12 PM PDT 24
Peak memory 217756 kb
Host smart-00779e33-7180-4de5-bdc4-3ea4d204f1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621602097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.3621602097
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.1792133286
Short name T434
Test name
Test status
Simulation time 385517397 ps
CPU time 14.45 seconds
Started Jul 05 05:35:20 PM PDT 24
Finished Jul 05 05:35:37 PM PDT 24
Peak memory 225560 kb
Host smart-cdd1ed89-1884-407f-8b9b-74b97b8d607f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792133286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.1792133286
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.208687511
Short name T542
Test name
Test status
Simulation time 1619979375 ps
CPU time 11.73 seconds
Started Jul 05 05:35:27 PM PDT 24
Finished Jul 05 05:35:39 PM PDT 24
Peak memory 225424 kb
Host smart-b8df82ce-88ad-4dc1-a9c6-556f50ef6578
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208687511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_di
gest.208687511
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.3540828206
Short name T726
Test name
Test status
Simulation time 174185379 ps
CPU time 6.24 seconds
Started Jul 05 05:35:21 PM PDT 24
Finished Jul 05 05:35:30 PM PDT 24
Peak memory 217720 kb
Host smart-2dce68c5-bb9e-452f-ac15-d3b71905b778
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540828206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
3540828206
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.2530211542
Short name T60
Test name
Test status
Simulation time 893247578 ps
CPU time 10.15 seconds
Started Jul 05 05:35:18 PM PDT 24
Finished Jul 05 05:35:31 PM PDT 24
Peak memory 217776 kb
Host smart-9d385963-2198-4b40-afe3-61a1cf4d38e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530211542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.2530211542
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.2159509555
Short name T367
Test name
Test status
Simulation time 248084618 ps
CPU time 2.16 seconds
Started Jul 05 05:35:09 PM PDT 24
Finished Jul 05 05:35:13 PM PDT 24
Peak memory 213752 kb
Host smart-f2d16982-e792-4eca-8176-23f5eba2b7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159509555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.2159509555
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.1054076002
Short name T278
Test name
Test status
Simulation time 256322049 ps
CPU time 26.34 seconds
Started Jul 05 05:35:07 PM PDT 24
Finished Jul 05 05:35:33 PM PDT 24
Peak memory 250476 kb
Host smart-7fd1294b-b628-4933-bb15-9aef5c005075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054076002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.1054076002
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.1698819251
Short name T169
Test name
Test status
Simulation time 131526718 ps
CPU time 6.94 seconds
Started Jul 05 05:35:11 PM PDT 24
Finished Jul 05 05:35:19 PM PDT 24
Peak memory 250048 kb
Host smart-d900f8b7-f22c-4e3a-b006-8bd66fe98686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698819251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.1698819251
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.3954635800
Short name T761
Test name
Test status
Simulation time 31061737996 ps
CPU time 279.08 seconds
Started Jul 05 05:35:18 PM PDT 24
Finished Jul 05 05:40:01 PM PDT 24
Peak memory 280860 kb
Host smart-c2e9bb41-8d07-42f0-b3e9-b5e33fada898
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954635800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.3954635800
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.543681438
Short name T484
Test name
Test status
Simulation time 47523637 ps
CPU time 0.8 seconds
Started Jul 05 05:35:09 PM PDT 24
Finished Jul 05 05:35:11 PM PDT 24
Peak memory 208536 kb
Host smart-b9bc1ebb-293b-4619-8f78-649dae4c19bb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543681438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ct
rl_volatile_unlock_smoke.543681438
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.1332658447
Short name T272
Test name
Test status
Simulation time 53918172 ps
CPU time 0.9 seconds
Started Jul 05 05:35:19 PM PDT 24
Finished Jul 05 05:35:23 PM PDT 24
Peak memory 208600 kb
Host smart-256cede8-15d6-405a-9286-6d9991a7fe4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332658447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.1332658447
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.1409155806
Short name T391
Test name
Test status
Simulation time 3608357093 ps
CPU time 25.28 seconds
Started Jul 05 05:35:18 PM PDT 24
Finished Jul 05 05:35:47 PM PDT 24
Peak memory 225660 kb
Host smart-9b97391f-17b1-47c2-8f34-54d57ba5e683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409155806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.1409155806
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.1853076568
Short name T610
Test name
Test status
Simulation time 734603539 ps
CPU time 8.32 seconds
Started Jul 05 05:35:19 PM PDT 24
Finished Jul 05 05:35:31 PM PDT 24
Peak memory 217208 kb
Host smart-9c945a8d-44f9-4c7a-ac2b-ffd197fb5eaf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853076568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.1853076568
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.3211962178
Short name T40
Test name
Test status
Simulation time 59348005 ps
CPU time 2.44 seconds
Started Jul 05 05:35:17 PM PDT 24
Finished Jul 05 05:35:21 PM PDT 24
Peak memory 217852 kb
Host smart-799e937b-edd5-4ce3-9aec-cf84d27d1a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211962178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.3211962178
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.2516980108
Short name T273
Test name
Test status
Simulation time 265139187 ps
CPU time 10.03 seconds
Started Jul 05 05:35:19 PM PDT 24
Finished Jul 05 05:35:32 PM PDT 24
Peak memory 218460 kb
Host smart-8b93c9f0-0ad5-47c9-ab6e-ea31553173b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516980108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.2516980108
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.2540502104
Short name T678
Test name
Test status
Simulation time 337352884 ps
CPU time 13.13 seconds
Started Jul 05 05:35:18 PM PDT 24
Finished Jul 05 05:35:34 PM PDT 24
Peak memory 225528 kb
Host smart-a6aded87-49d9-4fda-934d-87041d178ed7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540502104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.2540502104
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.3246440508
Short name T822
Test name
Test status
Simulation time 815491778 ps
CPU time 8.11 seconds
Started Jul 05 05:35:17 PM PDT 24
Finished Jul 05 05:35:28 PM PDT 24
Peak memory 217676 kb
Host smart-690cd15e-7994-417f-b465-901c734f4e1a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246440508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
3246440508
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.3948834174
Short name T561
Test name
Test status
Simulation time 750933930 ps
CPU time 8.15 seconds
Started Jul 05 05:35:16 PM PDT 24
Finished Jul 05 05:35:25 PM PDT 24
Peak memory 223988 kb
Host smart-5d653cc3-4c2a-4452-a0ba-4bb8347a4736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948834174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.3948834174
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.2758785404
Short name T312
Test name
Test status
Simulation time 412781740 ps
CPU time 2.14 seconds
Started Jul 05 05:35:17 PM PDT 24
Finished Jul 05 05:35:21 PM PDT 24
Peak memory 223008 kb
Host smart-6de6966c-7385-4cb0-aa75-427ad80d27ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758785404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.2758785404
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.1719137075
Short name T667
Test name
Test status
Simulation time 1038662183 ps
CPU time 21.79 seconds
Started Jul 05 05:35:18 PM PDT 24
Finished Jul 05 05:35:42 PM PDT 24
Peak memory 250536 kb
Host smart-51f76239-2876-4f61-86bb-d51eaa575d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719137075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.1719137075
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.2624917826
Short name T784
Test name
Test status
Simulation time 314481625 ps
CPU time 7.35 seconds
Started Jul 05 05:35:17 PM PDT 24
Finished Jul 05 05:35:27 PM PDT 24
Peak memory 250448 kb
Host smart-3c35d7e8-422e-4b99-9d85-e01b20c10b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624917826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.2624917826
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.1987922756
Short name T731
Test name
Test status
Simulation time 14158660224 ps
CPU time 66.03 seconds
Started Jul 05 05:35:17 PM PDT 24
Finished Jul 05 05:36:26 PM PDT 24
Peak memory 250368 kb
Host smart-a6877a64-905f-42a8-916d-702c17bf7686
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987922756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.1987922756
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.2034155206
Short name T855
Test name
Test status
Simulation time 14177630 ps
CPU time 0.82 seconds
Started Jul 05 05:35:17 PM PDT 24
Finished Jul 05 05:35:21 PM PDT 24
Peak memory 208356 kb
Host smart-9bfbf414-f453-48b5-ade2-a7147ec51802
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034155206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.2034155206
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.331351352
Short name T479
Test name
Test status
Simulation time 25643016 ps
CPU time 0.99 seconds
Started Jul 05 05:35:16 PM PDT 24
Finished Jul 05 05:35:19 PM PDT 24
Peak memory 208488 kb
Host smart-348a47ae-a355-4950-9941-3cbf08d118c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331351352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.331351352
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.3113294326
Short name T797
Test name
Test status
Simulation time 301425533 ps
CPU time 14.22 seconds
Started Jul 05 05:35:19 PM PDT 24
Finished Jul 05 05:35:37 PM PDT 24
Peak memory 217796 kb
Host smart-e20c5371-ce87-4086-b89b-3051d846285f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113294326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.3113294326
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.2251385056
Short name T21
Test name
Test status
Simulation time 61630257 ps
CPU time 1.3 seconds
Started Jul 05 05:35:19 PM PDT 24
Finished Jul 05 05:35:24 PM PDT 24
Peak memory 216628 kb
Host smart-94e00749-c43d-4508-b80d-6c5a19ada71b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251385056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.2251385056
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.128470525
Short name T682
Test name
Test status
Simulation time 173890093 ps
CPU time 3.27 seconds
Started Jul 05 05:35:16 PM PDT 24
Finished Jul 05 05:35:22 PM PDT 24
Peak memory 221960 kb
Host smart-49dc40a2-1edf-45f3-bf9a-17597bc90cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128470525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.128470525
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.2919230791
Short name T619
Test name
Test status
Simulation time 675503747 ps
CPU time 7.81 seconds
Started Jul 05 05:35:22 PM PDT 24
Finished Jul 05 05:35:31 PM PDT 24
Peak memory 225524 kb
Host smart-d47bc993-9b4a-465b-a138-e4d92dca1404
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919230791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.2919230791
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.1560148504
Short name T848
Test name
Test status
Simulation time 492608758 ps
CPU time 10.2 seconds
Started Jul 05 05:35:17 PM PDT 24
Finished Jul 05 05:35:30 PM PDT 24
Peak memory 217768 kb
Host smart-741d92e2-edbf-430a-9341-600f624580c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560148504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
1560148504
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.797322053
Short name T62
Test name
Test status
Simulation time 221965846 ps
CPU time 9.22 seconds
Started Jul 05 05:35:19 PM PDT 24
Finished Jul 05 05:35:32 PM PDT 24
Peak memory 224284 kb
Host smart-23f82179-a476-406b-815f-2f5f8e739510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797322053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.797322053
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.3828086645
Short name T249
Test name
Test status
Simulation time 138539847 ps
CPU time 1.54 seconds
Started Jul 05 05:35:20 PM PDT 24
Finished Jul 05 05:35:24 PM PDT 24
Peak memory 217176 kb
Host smart-bf8eb9c2-1311-4207-a6bd-b90454ec7f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828086645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.3828086645
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.700103077
Short name T807
Test name
Test status
Simulation time 1031225113 ps
CPU time 17.3 seconds
Started Jul 05 05:35:18 PM PDT 24
Finished Jul 05 05:35:38 PM PDT 24
Peak memory 250472 kb
Host smart-5d130727-00e7-40ea-9d9d-ac23024fad2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700103077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.700103077
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.1585374449
Short name T605
Test name
Test status
Simulation time 345269049 ps
CPU time 11.14 seconds
Started Jul 05 05:35:25 PM PDT 24
Finished Jul 05 05:35:37 PM PDT 24
Peak memory 250476 kb
Host smart-89b02b6b-3bfa-4740-82e4-32505ee56407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585374449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.1585374449
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.3991616729
Short name T781
Test name
Test status
Simulation time 3420491162 ps
CPU time 122.68 seconds
Started Jul 05 05:35:20 PM PDT 24
Finished Jul 05 05:37:26 PM PDT 24
Peak memory 283352 kb
Host smart-26a1533a-cbd5-4f4e-9e68-6130d6c811d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991616729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.3991616729
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.174419221
Short name T845
Test name
Test status
Simulation time 25856371 ps
CPU time 1 seconds
Started Jul 05 05:35:18 PM PDT 24
Finished Jul 05 05:35:23 PM PDT 24
Peak memory 217184 kb
Host smart-7436aada-b488-4a9c-98f9-c3c09ba0b8ec
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174419221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ct
rl_volatile_unlock_smoke.174419221
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.2269250430
Short name T289
Test name
Test status
Simulation time 16567753 ps
CPU time 0.89 seconds
Started Jul 05 05:35:21 PM PDT 24
Finished Jul 05 05:35:24 PM PDT 24
Peak memory 208512 kb
Host smart-bd6a7e48-ba53-4beb-831a-5ec8834dbf62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269250430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.2269250430
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.2139842728
Short name T753
Test name
Test status
Simulation time 1278099366 ps
CPU time 12.86 seconds
Started Jul 05 05:35:17 PM PDT 24
Finished Jul 05 05:35:33 PM PDT 24
Peak memory 217748 kb
Host smart-2a99c352-5427-494c-a3e6-e5015498ee90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139842728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.2139842728
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.3674294447
Short name T709
Test name
Test status
Simulation time 500968186 ps
CPU time 2.74 seconds
Started Jul 05 05:35:19 PM PDT 24
Finished Jul 05 05:35:24 PM PDT 24
Peak memory 217208 kb
Host smart-30b589b4-c15f-4a66-86cd-9307501fb326
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674294447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.3674294447
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.2403830324
Short name T459
Test name
Test status
Simulation time 99095157 ps
CPU time 3.33 seconds
Started Jul 05 05:35:17 PM PDT 24
Finished Jul 05 05:35:22 PM PDT 24
Peak memory 222240 kb
Host smart-0ee133a5-2d8a-4e23-848f-381fb8218fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403830324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.2403830324
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.2591277402
Short name T300
Test name
Test status
Simulation time 601892924 ps
CPU time 15.28 seconds
Started Jul 05 05:35:21 PM PDT 24
Finished Jul 05 05:35:39 PM PDT 24
Peak memory 225528 kb
Host smart-5d4c8cfb-b9e9-4a70-b7e1-048db64e7d9f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591277402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.2591277402
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.2867163574
Short name T265
Test name
Test status
Simulation time 879711644 ps
CPU time 8.84 seconds
Started Jul 05 05:35:21 PM PDT 24
Finished Jul 05 05:35:32 PM PDT 24
Peak memory 217712 kb
Host smart-51380b7f-f813-4cf6-b9e9-698f5bd1e95c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867163574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
2867163574
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.1448097231
Short name T635
Test name
Test status
Simulation time 448159440 ps
CPU time 10.9 seconds
Started Jul 05 05:35:21 PM PDT 24
Finished Jul 05 05:35:34 PM PDT 24
Peak memory 225544 kb
Host smart-337d4462-bbf4-4a79-9d6a-90207d55d394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448097231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.1448097231
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.2847533361
Short name T597
Test name
Test status
Simulation time 145251459 ps
CPU time 1.76 seconds
Started Jul 05 05:35:17 PM PDT 24
Finished Jul 05 05:35:20 PM PDT 24
Peak memory 217160 kb
Host smart-055ecc9f-474b-4271-998c-fddb12144ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847533361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.2847533361
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.2472101285
Short name T423
Test name
Test status
Simulation time 256032677 ps
CPU time 26.28 seconds
Started Jul 05 05:35:15 PM PDT 24
Finished Jul 05 05:35:43 PM PDT 24
Peak memory 250536 kb
Host smart-394efbc5-72c5-4c68-b874-3817b26e10cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472101285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.2472101285
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.2109974761
Short name T527
Test name
Test status
Simulation time 393548914 ps
CPU time 4.11 seconds
Started Jul 05 05:35:20 PM PDT 24
Finished Jul 05 05:35:27 PM PDT 24
Peak memory 222428 kb
Host smart-5d5e8455-429a-4735-af6f-85eeb40cb235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109974761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.2109974761
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.4167154483
Short name T566
Test name
Test status
Simulation time 3121430579 ps
CPU time 101.43 seconds
Started Jul 05 05:35:18 PM PDT 24
Finished Jul 05 05:37:02 PM PDT 24
Peak memory 404624 kb
Host smart-a03461ac-5e96-41f1-9a85-ff18f0424852
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167154483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.4167154483
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.651384874
Short name T198
Test name
Test status
Simulation time 64096103 ps
CPU time 0.88 seconds
Started Jul 05 05:35:19 PM PDT 24
Finished Jul 05 05:35:23 PM PDT 24
Peak memory 208456 kb
Host smart-521a12c8-97cd-448d-933f-953ca514b34c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651384874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ct
rl_volatile_unlock_smoke.651384874
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.4151594775
Short name T305
Test name
Test status
Simulation time 57034095 ps
CPU time 1.07 seconds
Started Jul 05 05:35:28 PM PDT 24
Finished Jul 05 05:35:30 PM PDT 24
Peak memory 208608 kb
Host smart-5e6e5405-83aa-4402-9b80-65d603b23f00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151594775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.4151594775
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.2190800486
Short name T648
Test name
Test status
Simulation time 2107928922 ps
CPU time 7.36 seconds
Started Jul 05 05:35:25 PM PDT 24
Finished Jul 05 05:35:33 PM PDT 24
Peak memory 217188 kb
Host smart-b06d419b-bad9-46c2-86ca-12ca3fae3564
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190800486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.2190800486
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.286736451
Short name T837
Test name
Test status
Simulation time 54207161 ps
CPU time 3.1 seconds
Started Jul 05 05:35:26 PM PDT 24
Finished Jul 05 05:35:29 PM PDT 24
Peak memory 217716 kb
Host smart-dd5f93cb-6ba3-46f2-921d-428ebd617305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286736451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.286736451
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.886759959
Short name T315
Test name
Test status
Simulation time 294643304 ps
CPU time 12.61 seconds
Started Jul 05 05:35:28 PM PDT 24
Finished Jul 05 05:35:41 PM PDT 24
Peak memory 217744 kb
Host smart-7261234b-0e85-46a6-b426-824fc6fdf48b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886759959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.886759959
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.833615084
Short name T252
Test name
Test status
Simulation time 690719498 ps
CPU time 7.39 seconds
Started Jul 05 05:35:28 PM PDT 24
Finished Jul 05 05:35:36 PM PDT 24
Peak memory 225508 kb
Host smart-e3ca4cf5-1fa1-4a03-b110-0ac4d9cd8af0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833615084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_di
gest.833615084
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.3161819731
Short name T742
Test name
Test status
Simulation time 1778798098 ps
CPU time 10.29 seconds
Started Jul 05 05:35:31 PM PDT 24
Finished Jul 05 05:35:42 PM PDT 24
Peak memory 217740 kb
Host smart-c1f15228-8336-404a-981d-93a17ad89682
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161819731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
3161819731
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.3748660034
Short name T64
Test name
Test status
Simulation time 1030955921 ps
CPU time 12.02 seconds
Started Jul 05 05:35:34 PM PDT 24
Finished Jul 05 05:35:47 PM PDT 24
Peak memory 225584 kb
Host smart-b6d0eed3-8ca1-4324-ada3-d8827ccf9b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748660034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.3748660034
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.1260970569
Short name T473
Test name
Test status
Simulation time 73918607 ps
CPU time 1.47 seconds
Started Jul 05 05:35:27 PM PDT 24
Finished Jul 05 05:35:29 PM PDT 24
Peak memory 221436 kb
Host smart-8d5e878d-2948-4dfe-b699-508e47b0c7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260970569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.1260970569
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.4176865154
Short name T352
Test name
Test status
Simulation time 296649442 ps
CPU time 28.31 seconds
Started Jul 05 05:35:26 PM PDT 24
Finished Jul 05 05:35:55 PM PDT 24
Peak memory 246964 kb
Host smart-da67ee40-a65d-448e-94f3-6c1798c1ea7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176865154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.4176865154
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.234310880
Short name T179
Test name
Test status
Simulation time 73461554 ps
CPU time 6.99 seconds
Started Jul 05 05:35:28 PM PDT 24
Finished Jul 05 05:35:36 PM PDT 24
Peak memory 246436 kb
Host smart-8000db61-9504-4cb4-8439-eee5ed4241cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234310880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.234310880
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.2823211873
Short name T817
Test name
Test status
Simulation time 1799378887 ps
CPU time 63.65 seconds
Started Jul 05 05:35:30 PM PDT 24
Finished Jul 05 05:36:34 PM PDT 24
Peak memory 274768 kb
Host smart-93928b78-ad98-4cdd-8705-8b265536984c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823211873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.2823211873
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.953028747
Short name T738
Test name
Test status
Simulation time 13086695 ps
CPU time 0.78 seconds
Started Jul 05 05:35:29 PM PDT 24
Finished Jul 05 05:35:30 PM PDT 24
Peak memory 208284 kb
Host smart-7a34599f-6bbf-44e5-9c55-59002d4a7b89
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953028747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ct
rl_volatile_unlock_smoke.953028747
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.1905157842
Short name T29
Test name
Test status
Simulation time 69607774 ps
CPU time 0.91 seconds
Started Jul 05 05:35:27 PM PDT 24
Finished Jul 05 05:35:28 PM PDT 24
Peak memory 208520 kb
Host smart-c1ebbcbd-50f3-4bc4-a70b-477ce2fdad7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905157842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.1905157842
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.3599948385
Short name T451
Test name
Test status
Simulation time 854923877 ps
CPU time 19.5 seconds
Started Jul 05 05:35:27 PM PDT 24
Finished Jul 05 05:35:48 PM PDT 24
Peak memory 217792 kb
Host smart-ee0c015f-c61a-4e47-86c0-6af4f929b404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599948385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.3599948385
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.921733623
Short name T347
Test name
Test status
Simulation time 268669515 ps
CPU time 6.3 seconds
Started Jul 05 05:35:26 PM PDT 24
Finished Jul 05 05:35:33 PM PDT 24
Peak memory 217184 kb
Host smart-4bdaea97-99e6-453f-b260-849c67dbb078
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921733623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.921733623
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.2795693787
Short name T292
Test name
Test status
Simulation time 102577569 ps
CPU time 3.54 seconds
Started Jul 05 05:35:36 PM PDT 24
Finished Jul 05 05:35:40 PM PDT 24
Peak memory 217652 kb
Host smart-8dcf2958-6241-4fda-95b7-809b4c15ec58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795693787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.2795693787
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.4269135492
Short name T483
Test name
Test status
Simulation time 1582114347 ps
CPU time 11.15 seconds
Started Jul 05 05:35:35 PM PDT 24
Finished Jul 05 05:35:47 PM PDT 24
Peak memory 218504 kb
Host smart-e320045a-f82b-46b6-b246-a50212664dee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269135492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.4269135492
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.3813872827
Short name T522
Test name
Test status
Simulation time 422322525 ps
CPU time 17 seconds
Started Jul 05 05:35:31 PM PDT 24
Finished Jul 05 05:35:48 PM PDT 24
Peak memory 225392 kb
Host smart-575bc564-c2cc-43ad-b3fc-66e13f72b26f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813872827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.3813872827
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.974674824
Short name T613
Test name
Test status
Simulation time 1268286151 ps
CPU time 10.95 seconds
Started Jul 05 05:35:27 PM PDT 24
Finished Jul 05 05:35:39 PM PDT 24
Peak memory 217736 kb
Host smart-5c86e6f5-3f37-4efa-8b05-490f1c863c66
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974674824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.974674824
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.2216912191
Short name T234
Test name
Test status
Simulation time 738616152 ps
CPU time 9.54 seconds
Started Jul 05 05:35:25 PM PDT 24
Finished Jul 05 05:35:35 PM PDT 24
Peak memory 225644 kb
Host smart-8f5e4a0d-8a76-47c9-9c44-5913759d8a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216912191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.2216912191
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.3385058360
Short name T699
Test name
Test status
Simulation time 72126276 ps
CPU time 2.92 seconds
Started Jul 05 05:35:29 PM PDT 24
Finished Jul 05 05:35:33 PM PDT 24
Peak memory 222728 kb
Host smart-7d29c446-0cf3-4ec9-bc6d-0854da22a152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385058360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.3385058360
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.2746253911
Short name T329
Test name
Test status
Simulation time 150358095 ps
CPU time 21.22 seconds
Started Jul 05 05:35:30 PM PDT 24
Finished Jul 05 05:35:52 PM PDT 24
Peak memory 250444 kb
Host smart-f00c4b57-6d8e-4327-9f3f-39ca3018472a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746253911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.2746253911
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.259108428
Short name T333
Test name
Test status
Simulation time 55744046 ps
CPU time 2.94 seconds
Started Jul 05 05:35:30 PM PDT 24
Finished Jul 05 05:35:33 PM PDT 24
Peak memory 225924 kb
Host smart-2af53586-9f5a-4cea-bc40-3cddf967b411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259108428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.259108428
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.3566132444
Short name T177
Test name
Test status
Simulation time 12265593599 ps
CPU time 189.83 seconds
Started Jul 05 05:35:27 PM PDT 24
Finished Jul 05 05:38:37 PM PDT 24
Peak memory 251940 kb
Host smart-d252dc6a-470b-49a5-8468-7040f911bbf5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566132444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.3566132444
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.3066058763
Short name T46
Test name
Test status
Simulation time 28830120 ps
CPU time 0.81 seconds
Started Jul 05 05:35:29 PM PDT 24
Finished Jul 05 05:35:31 PM PDT 24
Peak memory 208280 kb
Host smart-f709efc2-8c6a-4dad-9339-f6a729da579c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066058763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.3066058763
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.329648029
Short name T297
Test name
Test status
Simulation time 82138849 ps
CPU time 0.95 seconds
Started Jul 05 05:35:28 PM PDT 24
Finished Jul 05 05:35:29 PM PDT 24
Peak memory 208576 kb
Host smart-f2745a8c-b69a-402a-abda-323040ea0265
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329648029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.329648029
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.1612283098
Short name T637
Test name
Test status
Simulation time 341459340 ps
CPU time 13.07 seconds
Started Jul 05 05:35:27 PM PDT 24
Finished Jul 05 05:35:41 PM PDT 24
Peak memory 217792 kb
Host smart-0d2f5bd5-d9c2-4f8a-bf95-d173cd71bf39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612283098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.1612283098
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.2451439274
Short name T472
Test name
Test status
Simulation time 3701289333 ps
CPU time 8.74 seconds
Started Jul 05 05:35:28 PM PDT 24
Finished Jul 05 05:35:38 PM PDT 24
Peak memory 217324 kb
Host smart-790ad20b-5aeb-44a4-8948-edd7a41bb7fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451439274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.2451439274
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.1018373309
Short name T402
Test name
Test status
Simulation time 59229619 ps
CPU time 2.14 seconds
Started Jul 05 05:35:25 PM PDT 24
Finished Jul 05 05:35:27 PM PDT 24
Peak memory 221888 kb
Host smart-6e84ca1f-0f48-4fa0-9fd9-63e352043d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018373309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.1018373309
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.1035045911
Short name T646
Test name
Test status
Simulation time 1526249079 ps
CPU time 17 seconds
Started Jul 05 05:35:27 PM PDT 24
Finished Jul 05 05:35:44 PM PDT 24
Peak memory 219512 kb
Host smart-bc5401ad-c10d-4934-8673-e25adf678827
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035045911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.1035045911
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.1383336490
Short name T639
Test name
Test status
Simulation time 1005697571 ps
CPU time 8.09 seconds
Started Jul 05 05:35:31 PM PDT 24
Finished Jul 05 05:35:40 PM PDT 24
Peak memory 225532 kb
Host smart-c45e23e1-a137-422d-9bf4-c0bdf5330493
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383336490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.1383336490
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.1022932286
Short name T736
Test name
Test status
Simulation time 1232442443 ps
CPU time 11.21 seconds
Started Jul 05 05:35:34 PM PDT 24
Finished Jul 05 05:35:47 PM PDT 24
Peak memory 217800 kb
Host smart-a5072f51-6582-478d-ab99-a3e4dfe6ec7f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022932286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
1022932286
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.1721716389
Short name T774
Test name
Test status
Simulation time 296968163 ps
CPU time 10.18 seconds
Started Jul 05 05:35:26 PM PDT 24
Finished Jul 05 05:35:37 PM PDT 24
Peak memory 224608 kb
Host smart-3c3919d3-c7b3-4f78-b8df-71163f992385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721716389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.1721716389
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.360597237
Short name T182
Test name
Test status
Simulation time 62227278 ps
CPU time 4.56 seconds
Started Jul 05 05:35:28 PM PDT 24
Finished Jul 05 05:35:34 PM PDT 24
Peak memory 217208 kb
Host smart-defac45f-031c-4a70-98bf-fe9617b01602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360597237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.360597237
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.3408436425
Short name T30
Test name
Test status
Simulation time 1139548988 ps
CPU time 29.31 seconds
Started Jul 05 05:35:26 PM PDT 24
Finished Jul 05 05:35:56 PM PDT 24
Peak memory 250544 kb
Host smart-86fa8dc5-c73a-408e-b221-439ceb199416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408436425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.3408436425
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.4257534256
Short name T368
Test name
Test status
Simulation time 76559299 ps
CPU time 3.35 seconds
Started Jul 05 05:35:27 PM PDT 24
Finished Jul 05 05:35:31 PM PDT 24
Peak memory 222196 kb
Host smart-4bed1de6-15c1-4584-8f75-e53130b75ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257534256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.4257534256
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.660448679
Short name T95
Test name
Test status
Simulation time 1213266480 ps
CPU time 25.3 seconds
Started Jul 05 05:35:36 PM PDT 24
Finished Jul 05 05:36:02 PM PDT 24
Peak memory 225592 kb
Host smart-c3e86d79-a9ba-4933-86fa-d0105322a1e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660448679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.660448679
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.3502079351
Short name T770
Test name
Test status
Simulation time 41511794 ps
CPU time 0.99 seconds
Started Jul 05 05:35:26 PM PDT 24
Finished Jul 05 05:35:27 PM PDT 24
Peak memory 211388 kb
Host smart-53cb3b7a-5444-4c32-9e9d-519813fbd255
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502079351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.3502079351
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.2451606950
Short name T409
Test name
Test status
Simulation time 84976880 ps
CPU time 1.42 seconds
Started Jul 05 05:35:33 PM PDT 24
Finished Jul 05 05:35:36 PM PDT 24
Peak memory 208548 kb
Host smart-4dff7e44-0fba-49ec-bf00-75ce3be02a50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451606950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.2451606950
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.35367878
Short name T486
Test name
Test status
Simulation time 1260342054 ps
CPU time 11.82 seconds
Started Jul 05 05:35:32 PM PDT 24
Finished Jul 05 05:35:45 PM PDT 24
Peak memory 217760 kb
Host smart-e869c539-10e8-475b-a5e6-2a797e157490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35367878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.35367878
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.1784434184
Short name T261
Test name
Test status
Simulation time 65123167 ps
CPU time 2.64 seconds
Started Jul 05 05:35:36 PM PDT 24
Finished Jul 05 05:35:39 PM PDT 24
Peak memory 221536 kb
Host smart-01628336-efaf-4cc5-81f1-40dba37e0b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784434184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.1784434184
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.1967614820
Short name T337
Test name
Test status
Simulation time 5311348806 ps
CPU time 22.84 seconds
Started Jul 05 05:35:31 PM PDT 24
Finished Jul 05 05:35:55 PM PDT 24
Peak memory 219544 kb
Host smart-be7336f7-8a75-4fd3-abb6-6849f496fe04
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967614820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.1967614820
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.3985400721
Short name T470
Test name
Test status
Simulation time 318786312 ps
CPU time 10.52 seconds
Started Jul 05 05:35:38 PM PDT 24
Finished Jul 05 05:35:49 PM PDT 24
Peak memory 225528 kb
Host smart-0bab647f-4fa1-4f61-a2dd-4c433412aaae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985400721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.3985400721
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.2701390916
Short name T788
Test name
Test status
Simulation time 803442893 ps
CPU time 10.88 seconds
Started Jul 05 05:35:33 PM PDT 24
Finished Jul 05 05:35:45 PM PDT 24
Peak memory 217732 kb
Host smart-9f4f1682-660b-4e25-b08b-13d2eede4f6b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701390916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
2701390916
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.4073076338
Short name T812
Test name
Test status
Simulation time 302585790 ps
CPU time 9.37 seconds
Started Jul 05 05:35:31 PM PDT 24
Finished Jul 05 05:35:41 PM PDT 24
Peak memory 217792 kb
Host smart-d28a6a21-c3d7-4ea5-baf3-5339eba350fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073076338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.4073076338
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.2165295332
Short name T683
Test name
Test status
Simulation time 15045395 ps
CPU time 1.09 seconds
Started Jul 05 05:35:34 PM PDT 24
Finished Jul 05 05:35:36 PM PDT 24
Peak memory 211872 kb
Host smart-6b8563c3-91b9-4ede-a019-e0dfb05ba49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165295332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.2165295332
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.2021153639
Short name T28
Test name
Test status
Simulation time 212046753 ps
CPU time 19.56 seconds
Started Jul 05 05:35:28 PM PDT 24
Finished Jul 05 05:35:48 PM PDT 24
Peak memory 245192 kb
Host smart-b9856a6a-1360-4732-b086-437110801124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021153639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.2021153639
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.1919860509
Short name T525
Test name
Test status
Simulation time 194143652 ps
CPU time 3.2 seconds
Started Jul 05 05:35:29 PM PDT 24
Finished Jul 05 05:35:33 PM PDT 24
Peak memory 221936 kb
Host smart-cc89343c-4cc9-4e87-b799-8cfa8102df83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919860509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.1919860509
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.4089309613
Short name T73
Test name
Test status
Simulation time 16646019571 ps
CPU time 346.69 seconds
Started Jul 05 05:35:35 PM PDT 24
Finished Jul 05 05:41:23 PM PDT 24
Peak memory 273452 kb
Host smart-10df5d51-baa8-4603-b2a9-4536c74a2961
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089309613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.4089309613
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.1000408697
Short name T621
Test name
Test status
Simulation time 12753615 ps
CPU time 1 seconds
Started Jul 05 05:35:29 PM PDT 24
Finished Jul 05 05:35:31 PM PDT 24
Peak memory 208448 kb
Host smart-84ca1302-80fe-4d31-a2b9-c952faecb5d0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000408697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.1000408697
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.70522911
Short name T816
Test name
Test status
Simulation time 37938298 ps
CPU time 1.07 seconds
Started Jul 05 05:35:36 PM PDT 24
Finished Jul 05 05:35:38 PM PDT 24
Peak memory 208524 kb
Host smart-7ad4861b-8860-4e5c-beb3-10d320f034dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70522911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.70522911
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.3145083381
Short name T529
Test name
Test status
Simulation time 548096129 ps
CPU time 13.09 seconds
Started Jul 05 05:35:38 PM PDT 24
Finished Jul 05 05:35:52 PM PDT 24
Peak memory 217788 kb
Host smart-87812592-eeac-4615-882a-6f3c6e908c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145083381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.3145083381
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.1360819124
Short name T804
Test name
Test status
Simulation time 1762903448 ps
CPU time 6.4 seconds
Started Jul 05 05:35:34 PM PDT 24
Finished Jul 05 05:35:41 PM PDT 24
Peak memory 217180 kb
Host smart-4726436d-6b41-4bb0-984c-31fdf154a2ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360819124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.1360819124
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.3066835634
Short name T99
Test name
Test status
Simulation time 95393021 ps
CPU time 1.98 seconds
Started Jul 05 05:35:32 PM PDT 24
Finished Jul 05 05:35:35 PM PDT 24
Peak memory 217744 kb
Host smart-0f28e8cf-d52b-4b05-a73a-2cd753a834c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066835634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.3066835634
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.1261290964
Short name T263
Test name
Test status
Simulation time 347899925 ps
CPU time 17.12 seconds
Started Jul 05 05:35:36 PM PDT 24
Finished Jul 05 05:35:54 PM PDT 24
Peak memory 225584 kb
Host smart-b755379e-9760-4a95-a825-c8dbb1822010
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261290964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.1261290964
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.3621701908
Short name T476
Test name
Test status
Simulation time 296133000 ps
CPU time 11.13 seconds
Started Jul 05 05:35:35 PM PDT 24
Finished Jul 05 05:35:47 PM PDT 24
Peak memory 225452 kb
Host smart-b701a6cd-b525-47f5-be3b-1aab9987b166
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621701908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.3621701908
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.3398280546
Short name T654
Test name
Test status
Simulation time 557391085 ps
CPU time 8.92 seconds
Started Jul 05 05:35:34 PM PDT 24
Finished Jul 05 05:35:44 PM PDT 24
Peak memory 217860 kb
Host smart-bbc8b742-1ef2-4403-ad0e-0fae2fe46770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398280546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.3398280546
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.1659386661
Short name T103
Test name
Test status
Simulation time 53060128 ps
CPU time 2.5 seconds
Started Jul 05 05:35:35 PM PDT 24
Finished Jul 05 05:35:39 PM PDT 24
Peak memory 214120 kb
Host smart-ca28481f-8d09-4554-b74f-1f6f11b92dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659386661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.1659386661
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.3742563185
Short name T795
Test name
Test status
Simulation time 667634920 ps
CPU time 20.74 seconds
Started Jul 05 05:35:33 PM PDT 24
Finished Jul 05 05:35:54 PM PDT 24
Peak memory 250500 kb
Host smart-695d3f81-9916-4d06-9a27-7aacacf8cc89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742563185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.3742563185
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.3251825727
Short name T703
Test name
Test status
Simulation time 397320745 ps
CPU time 8.82 seconds
Started Jul 05 05:35:34 PM PDT 24
Finished Jul 05 05:35:44 PM PDT 24
Peak memory 250532 kb
Host smart-3ff697fd-8649-46c2-9fd6-01bf99c72b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251825727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.3251825727
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.498017447
Short name T341
Test name
Test status
Simulation time 8530443398 ps
CPU time 148.9 seconds
Started Jul 05 05:35:32 PM PDT 24
Finished Jul 05 05:38:02 PM PDT 24
Peak memory 253336 kb
Host smart-59e5ae86-7076-47f4-85e5-c49e220f8c2f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498017447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.498017447
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.4249844379
Short name T157
Test name
Test status
Simulation time 204895223212 ps
CPU time 820.45 seconds
Started Jul 05 05:35:32 PM PDT 24
Finished Jul 05 05:49:13 PM PDT 24
Peak memory 512840 kb
Host smart-6a6b8016-8032-42a7-83d1-3ca6ab24d646
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4249844379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all_with_rand_reset.4249844379
Directory /workspace/49.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.2441724387
Short name T320
Test name
Test status
Simulation time 29464820 ps
CPU time 0.91 seconds
Started Jul 05 05:35:34 PM PDT 24
Finished Jul 05 05:35:36 PM PDT 24
Peak memory 217128 kb
Host smart-dc8526fd-4498-4b5d-ac9c-0a04d9f1e2d9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441724387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.2441724387
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.4096889375
Short name T361
Test name
Test status
Simulation time 16138841 ps
CPU time 0.85 seconds
Started Jul 05 05:33:16 PM PDT 24
Finished Jul 05 05:33:18 PM PDT 24
Peak memory 208520 kb
Host smart-893462c8-4646-4e32-aad6-65e49362e399
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096889375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.4096889375
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.695786725
Short name T284
Test name
Test status
Simulation time 2967491838 ps
CPU time 15.65 seconds
Started Jul 05 05:33:13 PM PDT 24
Finished Jul 05 05:33:30 PM PDT 24
Peak memory 217836 kb
Host smart-dcaa1d53-e545-47e0-a4e0-5e3f0a1ba3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695786725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.695786725
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.1338027081
Short name T580
Test name
Test status
Simulation time 1574649824 ps
CPU time 7.75 seconds
Started Jul 05 05:33:18 PM PDT 24
Finished Jul 05 05:33:26 PM PDT 24
Peak memory 216808 kb
Host smart-8050e2bc-0f1d-4e6c-9d85-627394320e28
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338027081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.1338027081
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.700966829
Short name T52
Test name
Test status
Simulation time 4241636771 ps
CPU time 19.03 seconds
Started Jul 05 05:33:13 PM PDT 24
Finished Jul 05 05:33:33 PM PDT 24
Peak memory 217956 kb
Host smart-63b0d215-2999-47b7-ad18-b39da4784fc2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700966829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_err
ors.700966829
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.2074211254
Short name T228
Test name
Test status
Simulation time 1003790013 ps
CPU time 23.07 seconds
Started Jul 05 05:33:15 PM PDT 24
Finished Jul 05 05:33:39 PM PDT 24
Peak memory 217280 kb
Host smart-de4fd14f-ea79-41b2-becf-c0c7dd27b268
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074211254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.2
074211254
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.2979577304
Short name T246
Test name
Test status
Simulation time 751614521 ps
CPU time 11.38 seconds
Started Jul 05 05:33:12 PM PDT 24
Finished Jul 05 05:33:24 PM PDT 24
Peak memory 222696 kb
Host smart-bd367902-848e-4e26-8abe-d506a60e7a13
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979577304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.2979577304
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.1807265047
Short name T801
Test name
Test status
Simulation time 886938240 ps
CPU time 12.68 seconds
Started Jul 05 05:33:15 PM PDT 24
Finished Jul 05 05:33:29 PM PDT 24
Peak memory 217092 kb
Host smart-9daf0ebd-21ca-4a78-8807-7213a482f362
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807265047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.1807265047
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.1244679459
Short name T468
Test name
Test status
Simulation time 306567936 ps
CPU time 8.38 seconds
Started Jul 05 05:33:11 PM PDT 24
Finished Jul 05 05:33:20 PM PDT 24
Peak memory 217044 kb
Host smart-0eb835da-c730-43d0-bbb6-658ad7b929e2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244679459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
1244679459
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.3526821980
Short name T535
Test name
Test status
Simulation time 817794623 ps
CPU time 28.62 seconds
Started Jul 05 05:33:24 PM PDT 24
Finished Jul 05 05:33:53 PM PDT 24
Peak memory 250496 kb
Host smart-86ffb74c-456c-4215-a707-f6ffe203f902
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526821980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.3526821980
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.865605109
Short name T271
Test name
Test status
Simulation time 4638819166 ps
CPU time 19.75 seconds
Started Jul 05 05:33:16 PM PDT 24
Finished Jul 05 05:33:37 PM PDT 24
Peak memory 250116 kb
Host smart-6a5262e3-e7da-4ab5-a6a5-a528458ff6ce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865605109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_state_post_trans.865605109
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.274846844
Short name T836
Test name
Test status
Simulation time 418939384 ps
CPU time 2.9 seconds
Started Jul 05 05:33:14 PM PDT 24
Finished Jul 05 05:33:18 PM PDT 24
Peak memory 217736 kb
Host smart-491e5858-1e2b-4b15-9d93-7bd6002d6106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274846844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.274846844
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.593831289
Short name T110
Test name
Test status
Simulation time 189771565 ps
CPU time 11.49 seconds
Started Jul 05 05:33:17 PM PDT 24
Finished Jul 05 05:33:29 PM PDT 24
Peak memory 217204 kb
Host smart-b6dedf97-b0ac-41f9-ba99-39c895d28c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593831289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.593831289
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.1289807850
Short name T507
Test name
Test status
Simulation time 1227170049 ps
CPU time 12.23 seconds
Started Jul 05 05:33:15 PM PDT 24
Finished Jul 05 05:33:29 PM PDT 24
Peak memory 218520 kb
Host smart-68449407-d458-4423-b66e-b0dfc39d10d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289807850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.1289807850
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.2786469678
Short name T420
Test name
Test status
Simulation time 4460171081 ps
CPU time 14.14 seconds
Started Jul 05 05:33:23 PM PDT 24
Finished Jul 05 05:33:39 PM PDT 24
Peak memory 225572 kb
Host smart-e734b173-29c6-44cc-9270-b2f5863241ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786469678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.2786469678
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.2069548902
Short name T426
Test name
Test status
Simulation time 239218832 ps
CPU time 9.05 seconds
Started Jul 05 05:33:14 PM PDT 24
Finished Jul 05 05:33:25 PM PDT 24
Peak memory 217728 kb
Host smart-3e0956e3-8361-4bfb-835f-34ad92f87b24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069548902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.2
069548902
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.3043245726
Short name T190
Test name
Test status
Simulation time 209439479 ps
CPU time 9.9 seconds
Started Jul 05 05:33:15 PM PDT 24
Finished Jul 05 05:33:26 PM PDT 24
Peak memory 224580 kb
Host smart-dcd985ef-3055-4462-931e-934f21a888d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043245726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.3043245726
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.2259220238
Short name T294
Test name
Test status
Simulation time 223673586 ps
CPU time 3.18 seconds
Started Jul 05 05:33:15 PM PDT 24
Finished Jul 05 05:33:19 PM PDT 24
Peak memory 217168 kb
Host smart-382b50ce-17a9-4560-81ba-82062e754993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259220238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.2259220238
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.1414463015
Short name T248
Test name
Test status
Simulation time 1013089277 ps
CPU time 24.69 seconds
Started Jul 05 05:33:13 PM PDT 24
Finished Jul 05 05:33:38 PM PDT 24
Peak memory 250472 kb
Host smart-80227be8-e1a4-4691-b757-674afa8037e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414463015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.1414463015
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.1962040595
Short name T189
Test name
Test status
Simulation time 185885561 ps
CPU time 7.6 seconds
Started Jul 05 05:33:15 PM PDT 24
Finished Jul 05 05:33:24 PM PDT 24
Peak memory 250516 kb
Host smart-b964a54a-3646-4108-a872-e4732e9ff34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962040595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.1962040595
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.563435845
Short name T595
Test name
Test status
Simulation time 19127218376 ps
CPU time 195.49 seconds
Started Jul 05 05:33:15 PM PDT 24
Finished Jul 05 05:36:31 PM PDT 24
Peak memory 276644 kb
Host smart-089fe858-29fa-404f-9a0f-66181abdc5dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563435845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.563435845
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.1498822369
Short name T785
Test name
Test status
Simulation time 9496678547 ps
CPU time 155.75 seconds
Started Jul 05 05:33:15 PM PDT 24
Finished Jul 05 05:35:52 PM PDT 24
Peak memory 283428 kb
Host smart-f98afa66-3142-4ef9-ba9b-af5c3ba6ebb0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1498822369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all_with_rand_reset.1498822369
Directory /workspace/5.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.1809111626
Short name T464
Test name
Test status
Simulation time 14794867 ps
CPU time 0.98 seconds
Started Jul 05 05:33:13 PM PDT 24
Finished Jul 05 05:33:15 PM PDT 24
Peak memory 208488 kb
Host smart-71a44a0a-f710-41f8-91c5-feedd8b94fcc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809111626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.1809111626
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.2644378651
Short name T269
Test name
Test status
Simulation time 72513149 ps
CPU time 0.84 seconds
Started Jul 05 05:33:23 PM PDT 24
Finished Jul 05 05:33:24 PM PDT 24
Peak memory 208416 kb
Host smart-6ae78d36-d185-426a-8849-5c2a78de2fce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644378651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.2644378651
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.1341195547
Short name T44
Test name
Test status
Simulation time 34828564 ps
CPU time 0.82 seconds
Started Jul 05 05:33:21 PM PDT 24
Finished Jul 05 05:33:22 PM PDT 24
Peak memory 208476 kb
Host smart-6d8e30be-d343-417e-bcc6-9f96f94537b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341195547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.1341195547
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.4120202240
Short name T304
Test name
Test status
Simulation time 586978664 ps
CPU time 10.59 seconds
Started Jul 05 05:33:22 PM PDT 24
Finished Jul 05 05:33:34 PM PDT 24
Peak memory 217728 kb
Host smart-f5d4a7fc-8b37-4179-a429-bb591accb0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120202240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.4120202240
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.3106850275
Short name T488
Test name
Test status
Simulation time 632275962 ps
CPU time 6.63 seconds
Started Jul 05 05:33:23 PM PDT 24
Finished Jul 05 05:33:31 PM PDT 24
Peak memory 216692 kb
Host smart-4ad841ae-c8e7-4d27-8fa9-68832a0e809d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106850275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.3106850275
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.1250173808
Short name T425
Test name
Test status
Simulation time 3845513266 ps
CPU time 48.47 seconds
Started Jul 05 05:33:26 PM PDT 24
Finished Jul 05 05:34:14 PM PDT 24
Peak memory 218452 kb
Host smart-ede01e54-8c6c-4845-a583-3aadc0453b70
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250173808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.1250173808
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.4264484333
Short name T59
Test name
Test status
Simulation time 4743167747 ps
CPU time 17.61 seconds
Started Jul 05 05:33:26 PM PDT 24
Finished Jul 05 05:33:44 PM PDT 24
Peak memory 217332 kb
Host smart-d3d65b5c-1252-41d7-9c91-d562ed93796c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264484333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.4
264484333
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.706500303
Short name T345
Test name
Test status
Simulation time 2473697596 ps
CPU time 5.42 seconds
Started Jul 05 05:33:22 PM PDT 24
Finished Jul 05 05:33:29 PM PDT 24
Peak memory 217748 kb
Host smart-ce69a044-57fa-4a5f-84e8-158cf07416d1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706500303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_
prog_failure.706500303
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.3196321676
Short name T185
Test name
Test status
Simulation time 735614098 ps
CPU time 10.18 seconds
Started Jul 05 05:33:25 PM PDT 24
Finished Jul 05 05:33:36 PM PDT 24
Peak memory 217124 kb
Host smart-a0d1811f-fc0f-4dfa-95cc-0e1e436c98c0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196321676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.3196321676
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.1659472572
Short name T81
Test name
Test status
Simulation time 2691841500 ps
CPU time 5.92 seconds
Started Jul 05 05:33:20 PM PDT 24
Finished Jul 05 05:33:27 PM PDT 24
Peak memory 217172 kb
Host smart-0a6172ef-5dde-4795-8aa9-64a59243c3c7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659472572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
1659472572
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.804591534
Short name T465
Test name
Test status
Simulation time 7309455126 ps
CPU time 84.12 seconds
Started Jul 05 05:33:26 PM PDT 24
Finished Jul 05 05:34:50 PM PDT 24
Peak memory 283256 kb
Host smart-3e3ae327-0ae5-4cb2-98d5-837aa26bebd8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804591534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_state_failure.804591534
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.2908063605
Short name T395
Test name
Test status
Simulation time 2996807827 ps
CPU time 25.27 seconds
Started Jul 05 05:33:25 PM PDT 24
Finished Jul 05 05:33:51 PM PDT 24
Peak memory 245648 kb
Host smart-96fd76bc-30e4-4de7-be0a-1e48261c072b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908063605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.2908063605
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.3089586237
Short name T539
Test name
Test status
Simulation time 371174728 ps
CPU time 3.32 seconds
Started Jul 05 05:33:15 PM PDT 24
Finished Jul 05 05:33:20 PM PDT 24
Peak memory 217760 kb
Host smart-5ee112b7-3591-4180-8c7e-35eb6a452b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089586237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.3089586237
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.3713369238
Short name T445
Test name
Test status
Simulation time 283270126 ps
CPU time 16.37 seconds
Started Jul 05 05:33:21 PM PDT 24
Finished Jul 05 05:33:37 PM PDT 24
Peak memory 217140 kb
Host smart-ac8bedf8-6528-4b70-9da6-8067b3fbbd97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713369238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.3713369238
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.3175289525
Short name T490
Test name
Test status
Simulation time 308353036 ps
CPU time 11.62 seconds
Started Jul 05 05:33:22 PM PDT 24
Finished Jul 05 05:33:35 PM PDT 24
Peak memory 217944 kb
Host smart-42c2a5ed-af11-46c8-ac32-fab651de5fbb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175289525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.3175289525
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.588764003
Short name T669
Test name
Test status
Simulation time 306764152 ps
CPU time 13.12 seconds
Started Jul 05 05:33:23 PM PDT 24
Finished Jul 05 05:33:37 PM PDT 24
Peak memory 225516 kb
Host smart-ab3457b4-96a1-4b10-b63a-d9ef6eac1fb5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588764003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_dig
est.588764003
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.2117481630
Short name T570
Test name
Test status
Simulation time 953952580 ps
CPU time 7.29 seconds
Started Jul 05 05:33:26 PM PDT 24
Finished Jul 05 05:33:34 PM PDT 24
Peak memory 217748 kb
Host smart-44ba0e90-538c-4558-b0bd-c8ae7353c97b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117481630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.2
117481630
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.3205064445
Short name T61
Test name
Test status
Simulation time 1896038115 ps
CPU time 16.55 seconds
Started Jul 05 05:33:22 PM PDT 24
Finished Jul 05 05:33:40 PM PDT 24
Peak memory 217860 kb
Host smart-1808ce06-607e-45e0-97fd-8d79dcb637f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205064445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.3205064445
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.1704673451
Short name T86
Test name
Test status
Simulation time 222980795 ps
CPU time 3.08 seconds
Started Jul 05 05:33:23 PM PDT 24
Finished Jul 05 05:33:28 PM PDT 24
Peak memory 217176 kb
Host smart-31606e1d-1043-46c7-9fa2-60237b65c363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704673451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.1704673451
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.4228738784
Short name T450
Test name
Test status
Simulation time 986343136 ps
CPU time 24.74 seconds
Started Jul 05 05:33:16 PM PDT 24
Finished Jul 05 05:33:42 PM PDT 24
Peak memory 250536 kb
Host smart-cb489ad3-896f-4602-b125-f20b7c655374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228738784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.4228738784
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.40864543
Short name T105
Test name
Test status
Simulation time 198179135 ps
CPU time 7.77 seconds
Started Jul 05 05:33:17 PM PDT 24
Finished Jul 05 05:33:25 PM PDT 24
Peak memory 246244 kb
Host smart-ca0f4254-0527-4d68-b887-8162bf557536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40864543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.40864543
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.2448599263
Short name T191
Test name
Test status
Simulation time 11792766665 ps
CPU time 267.17 seconds
Started Jul 05 05:33:30 PM PDT 24
Finished Jul 05 05:37:58 PM PDT 24
Peak memory 273716 kb
Host smart-1d3d43a6-b809-49ea-aa48-64889af642ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448599263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.2448599263
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.223752789
Short name T293
Test name
Test status
Simulation time 85164856 ps
CPU time 1.07 seconds
Started Jul 05 05:33:14 PM PDT 24
Finished Jul 05 05:33:16 PM PDT 24
Peak memory 211476 kb
Host smart-a736640b-1293-4263-bef2-a2ad5cc5730b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223752789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctr
l_volatile_unlock_smoke.223752789
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.472814678
Short name T259
Test name
Test status
Simulation time 48239934 ps
CPU time 1.21 seconds
Started Jul 05 05:33:29 PM PDT 24
Finished Jul 05 05:33:32 PM PDT 24
Peak memory 208596 kb
Host smart-a02ea3dd-8c6d-4d76-a097-dc4ece53c22c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472814678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.472814678
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.3141300819
Short name T85
Test name
Test status
Simulation time 61508427 ps
CPU time 0.94 seconds
Started Jul 05 05:33:30 PM PDT 24
Finished Jul 05 05:33:32 PM PDT 24
Peak memory 208316 kb
Host smart-23ea0915-52e4-4a98-8d89-4ef4bbc5fdbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141300819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.3141300819
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.2353240691
Short name T660
Test name
Test status
Simulation time 1031764162 ps
CPU time 12.16 seconds
Started Jul 05 05:33:21 PM PDT 24
Finished Jul 05 05:33:34 PM PDT 24
Peak memory 217720 kb
Host smart-e3ce6293-35c3-4608-a70e-639f8655c8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353240691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.2353240691
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.255254153
Short name T545
Test name
Test status
Simulation time 278735865 ps
CPU time 2.2 seconds
Started Jul 05 05:33:22 PM PDT 24
Finished Jul 05 05:33:25 PM PDT 24
Peak memory 216624 kb
Host smart-6a18ecf5-cf17-48f3-8fc9-a75fae381aed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255254153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.255254153
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.3668962936
Short name T299
Test name
Test status
Simulation time 1233342161 ps
CPU time 21.62 seconds
Started Jul 05 05:33:21 PM PDT 24
Finished Jul 05 05:33:43 PM PDT 24
Peak memory 217744 kb
Host smart-4f7edf60-2ba7-4546-ba34-d13b1c10a3f5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668962936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.3668962936
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.2200963947
Short name T440
Test name
Test status
Simulation time 8239835553 ps
CPU time 22.52 seconds
Started Jul 05 05:33:23 PM PDT 24
Finished Jul 05 05:33:46 PM PDT 24
Peak memory 217340 kb
Host smart-5d58e26e-08a7-4a24-808d-08b4b9309c35
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200963947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.2
200963947
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.2272621111
Short name T175
Test name
Test status
Simulation time 814394872 ps
CPU time 11.46 seconds
Started Jul 05 05:33:21 PM PDT 24
Finished Jul 05 05:33:33 PM PDT 24
Peak memory 217736 kb
Host smart-c6088279-500c-414e-92f5-97457f758c75
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272621111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.2272621111
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.2672037641
Short name T366
Test name
Test status
Simulation time 1076198432 ps
CPU time 31.47 seconds
Started Jul 05 05:33:20 PM PDT 24
Finished Jul 05 05:33:52 PM PDT 24
Peak memory 217384 kb
Host smart-a6fa1f00-c4c9-40f3-9022-9c9d98c2ef11
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672037641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.2672037641
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.2482758457
Short name T90
Test name
Test status
Simulation time 1822256130 ps
CPU time 5.26 seconds
Started Jul 05 05:33:26 PM PDT 24
Finished Jul 05 05:33:32 PM PDT 24
Peak memory 217268 kb
Host smart-9eae834e-54f5-4b95-86ed-755e46faacb6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482758457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
2482758457
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.2931002235
Short name T691
Test name
Test status
Simulation time 10801851952 ps
CPU time 83.76 seconds
Started Jul 05 05:33:25 PM PDT 24
Finished Jul 05 05:34:49 PM PDT 24
Peak memory 280248 kb
Host smart-34570589-a122-4ea1-a8af-419deb788662
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931002235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.2931002235
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.718256126
Short name T253
Test name
Test status
Simulation time 1703968909 ps
CPU time 16.88 seconds
Started Jul 05 05:33:26 PM PDT 24
Finished Jul 05 05:33:44 PM PDT 24
Peak memory 250052 kb
Host smart-683f67c3-1bd4-4896-b509-a0bb2a98713e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718256126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_state_post_trans.718256126
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.3215997299
Short name T858
Test name
Test status
Simulation time 113967432 ps
CPU time 2.53 seconds
Started Jul 05 05:33:26 PM PDT 24
Finished Jul 05 05:33:29 PM PDT 24
Peak memory 221936 kb
Host smart-2e3434f2-e4af-48df-8e51-aa6fbc8b8a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215997299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.3215997299
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.2878980734
Short name T652
Test name
Test status
Simulation time 335149875 ps
CPU time 8.57 seconds
Started Jul 05 05:33:20 PM PDT 24
Finished Jul 05 05:33:29 PM PDT 24
Peak memory 214144 kb
Host smart-86ff0912-1e90-4be3-b133-b57450297195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878980734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.2878980734
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.3183456553
Short name T296
Test name
Test status
Simulation time 217925085 ps
CPU time 11.11 seconds
Started Jul 05 05:33:30 PM PDT 24
Finished Jul 05 05:33:42 PM PDT 24
Peak memory 217780 kb
Host smart-16fce427-3345-430a-a2d4-4c50793ea602
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183456553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.3183456553
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.1986454041
Short name T690
Test name
Test status
Simulation time 445409964 ps
CPU time 8.93 seconds
Started Jul 05 05:33:29 PM PDT 24
Finished Jul 05 05:33:40 PM PDT 24
Peak memory 225504 kb
Host smart-5b56330d-2c21-4d76-b37d-359f9df299f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986454041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.1986454041
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.1566407304
Short name T344
Test name
Test status
Simulation time 730776274 ps
CPU time 10.15 seconds
Started Jul 05 05:33:20 PM PDT 24
Finished Jul 05 05:33:31 PM PDT 24
Peak memory 217728 kb
Host smart-89283b41-8552-40d1-9b7f-d0a2c4683b8f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566407304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.1
566407304
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.2938130822
Short name T839
Test name
Test status
Simulation time 662345806 ps
CPU time 10.39 seconds
Started Jul 05 05:33:23 PM PDT 24
Finished Jul 05 05:33:34 PM PDT 24
Peak memory 217856 kb
Host smart-bf97f8a2-a6b1-4864-a819-0d1d14027b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938130822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.2938130822
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.1612217188
Short name T814
Test name
Test status
Simulation time 166218039 ps
CPU time 3.34 seconds
Started Jul 05 05:33:23 PM PDT 24
Finished Jul 05 05:33:28 PM PDT 24
Peak memory 214080 kb
Host smart-e68bd2ab-bdee-4584-982c-bc64eca9568a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612217188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.1612217188
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.170641894
Short name T805
Test name
Test status
Simulation time 387760341 ps
CPU time 35.13 seconds
Started Jul 05 05:33:26 PM PDT 24
Finished Jul 05 05:34:02 PM PDT 24
Peak memory 250548 kb
Host smart-453739dd-93b3-4b3b-ba3a-efda011cc8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170641894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.170641894
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.2335368611
Short name T524
Test name
Test status
Simulation time 246525547 ps
CPU time 4.68 seconds
Started Jul 05 05:33:22 PM PDT 24
Finished Jul 05 05:33:28 PM PDT 24
Peak memory 217740 kb
Host smart-7b4736a8-dbcc-4815-8c16-7ae0294f0c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335368611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.2335368611
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.1552861885
Short name T740
Test name
Test status
Simulation time 3506611060 ps
CPU time 62.74 seconds
Started Jul 05 05:33:32 PM PDT 24
Finished Jul 05 05:34:36 PM PDT 24
Peak memory 250600 kb
Host smart-cca55098-f16f-4b92-9f40-36a611f798cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552861885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.1552861885
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.4275850913
Short name T154
Test name
Test status
Simulation time 21633488886 ps
CPU time 6610.66 seconds
Started Jul 05 05:33:30 PM PDT 24
Finished Jul 05 07:23:42 PM PDT 24
Peak memory 1118156 kb
Host smart-9732b30e-ba33-46d4-b193-4cd6a3f7925a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4275850913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all_with_rand_reset.4275850913
Directory /workspace/7.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.245519197
Short name T387
Test name
Test status
Simulation time 26307079 ps
CPU time 1.12 seconds
Started Jul 05 05:33:22 PM PDT 24
Finished Jul 05 05:33:23 PM PDT 24
Peak memory 211348 kb
Host smart-8f40213e-aebe-43a8-b4ee-7157794727a3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245519197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctr
l_volatile_unlock_smoke.245519197
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.1853096219
Short name T768
Test name
Test status
Simulation time 59663954 ps
CPU time 1.01 seconds
Started Jul 05 05:33:29 PM PDT 24
Finished Jul 05 05:33:30 PM PDT 24
Peak memory 208496 kb
Host smart-82237b4c-8197-4f70-b685-4423556f4bfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853096219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.1853096219
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.2033145179
Short name T590
Test name
Test status
Simulation time 946570022 ps
CPU time 11.92 seconds
Started Jul 05 05:33:29 PM PDT 24
Finished Jul 05 05:33:42 PM PDT 24
Peak memory 217720 kb
Host smart-7b774fa1-239e-4d9d-8ef0-b29671652db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033145179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.2033145179
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.2051686587
Short name T631
Test name
Test status
Simulation time 449917805 ps
CPU time 3.35 seconds
Started Jul 05 05:33:31 PM PDT 24
Finished Jul 05 05:33:35 PM PDT 24
Peak memory 217208 kb
Host smart-c241ae78-3d9c-4a14-9dc3-625bd233c7fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051686587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.2051686587
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.155892562
Short name T657
Test name
Test status
Simulation time 6521047503 ps
CPU time 47.07 seconds
Started Jul 05 05:33:32 PM PDT 24
Finished Jul 05 05:34:20 PM PDT 24
Peak memory 218428 kb
Host smart-a84be28c-3f8e-4596-ba65-46ae9e8efce7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155892562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_err
ors.155892562
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.170747475
Short name T601
Test name
Test status
Simulation time 747031047 ps
CPU time 2.78 seconds
Started Jul 05 05:33:29 PM PDT 24
Finished Jul 05 05:33:34 PM PDT 24
Peak memory 217260 kb
Host smart-2f847a55-945c-43a3-bd2e-c0a5a8be4a7a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170747475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.170747475
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.2422276580
Short name T374
Test name
Test status
Simulation time 768927307 ps
CPU time 12.63 seconds
Started Jul 05 05:33:34 PM PDT 24
Finished Jul 05 05:33:47 PM PDT 24
Peak memory 217736 kb
Host smart-8f51c50d-092e-455c-8fd8-0f2c45f5ee74
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422276580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.2422276580
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.4122641115
Short name T775
Test name
Test status
Simulation time 2768931018 ps
CPU time 11.84 seconds
Started Jul 05 05:33:31 PM PDT 24
Finished Jul 05 05:33:44 PM PDT 24
Peak memory 217208 kb
Host smart-431ad4bd-5537-44cd-841a-10b8add20aa4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122641115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.4122641115
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.808709449
Short name T332
Test name
Test status
Simulation time 319376443 ps
CPU time 1.86 seconds
Started Jul 05 05:33:33 PM PDT 24
Finished Jul 05 05:33:36 PM PDT 24
Peak memory 217152 kb
Host smart-8360a8e3-0b54-4770-b843-d38ea4303b86
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808709449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.808709449
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.2263575551
Short name T840
Test name
Test status
Simulation time 36095825655 ps
CPU time 56.76 seconds
Started Jul 05 05:33:29 PM PDT 24
Finished Jul 05 05:34:26 PM PDT 24
Peak memory 283248 kb
Host smart-a417e8e5-8ec8-497d-8f31-96ffd8f1f98a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263575551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.2263575551
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.1847915691
Short name T717
Test name
Test status
Simulation time 3359360071 ps
CPU time 12.39 seconds
Started Jul 05 05:33:32 PM PDT 24
Finished Jul 05 05:33:46 PM PDT 24
Peak memory 217808 kb
Host smart-62445dbd-c04a-4913-8e78-af569d24098b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847915691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.1847915691
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.1290508558
Short name T846
Test name
Test status
Simulation time 190820090 ps
CPU time 2.58 seconds
Started Jul 05 05:33:29 PM PDT 24
Finished Jul 05 05:33:33 PM PDT 24
Peak memory 217756 kb
Host smart-fdcafab1-a968-4557-9956-ed69be009442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290508558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.1290508558
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.53734619
Short name T696
Test name
Test status
Simulation time 1764624257 ps
CPU time 19.96 seconds
Started Jul 05 05:33:29 PM PDT 24
Finished Jul 05 05:33:50 PM PDT 24
Peak memory 214156 kb
Host smart-ef8312eb-74cf-4ab0-9b2e-771ca934d396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53734619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.53734619
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.2916945777
Short name T354
Test name
Test status
Simulation time 317194018 ps
CPU time 9.41 seconds
Started Jul 05 05:33:30 PM PDT 24
Finished Jul 05 05:33:41 PM PDT 24
Peak memory 225588 kb
Host smart-2e4e02ad-6fba-4fa8-b6ea-f7d95fb7034e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916945777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.2916945777
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.986272701
Short name T277
Test name
Test status
Simulation time 465753340 ps
CPU time 16.48 seconds
Started Jul 05 05:33:32 PM PDT 24
Finished Jul 05 05:33:50 PM PDT 24
Peak memory 225292 kb
Host smart-4f0852c4-0326-47d7-a2d9-8ccda9533e5c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986272701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_dig
est.986272701
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.341891240
Short name T49
Test name
Test status
Simulation time 1306636109 ps
CPU time 12.27 seconds
Started Jul 05 05:33:27 PM PDT 24
Finished Jul 05 05:33:40 PM PDT 24
Peak memory 217724 kb
Host smart-83244fd8-f22c-4c46-b172-c9de12b673ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341891240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.341891240
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.143137278
Short name T799
Test name
Test status
Simulation time 2088741441 ps
CPU time 8.52 seconds
Started Jul 05 05:33:32 PM PDT 24
Finished Jul 05 05:33:42 PM PDT 24
Peak memory 225580 kb
Host smart-4101743a-1c87-4bd9-8a90-f0ee4c9e2457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143137278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.143137278
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.893972
Short name T77
Test name
Test status
Simulation time 158805047 ps
CPU time 2.03 seconds
Started Jul 05 05:33:44 PM PDT 24
Finished Jul 05 05:33:47 PM PDT 24
Peak memory 217204 kb
Host smart-2dc630ba-6acc-4e70-9e2b-acba82e4d008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.893972
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.1347602477
Short name T508
Test name
Test status
Simulation time 162263825 ps
CPU time 19.79 seconds
Started Jul 05 05:33:33 PM PDT 24
Finished Jul 05 05:33:54 PM PDT 24
Peak memory 250488 kb
Host smart-26cfc378-4d58-4f62-835b-a3bc9e969b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347602477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.1347602477
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.2457725789
Short name T602
Test name
Test status
Simulation time 157567719 ps
CPU time 7.77 seconds
Started Jul 05 05:33:30 PM PDT 24
Finished Jul 05 05:33:39 PM PDT 24
Peak memory 250100 kb
Host smart-d7ac444b-6e7b-46d0-91ef-5df4ba1ba556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457725789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.2457725789
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.745410151
Short name T403
Test name
Test status
Simulation time 1919813624 ps
CPU time 75.83 seconds
Started Jul 05 05:33:31 PM PDT 24
Finished Jul 05 05:34:47 PM PDT 24
Peak memory 266924 kb
Host smart-6150becc-f551-49be-8d15-b5c5b99781bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745410151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.745410151
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.2156273623
Short name T237
Test name
Test status
Simulation time 45288015331 ps
CPU time 517.26 seconds
Started Jul 05 05:33:30 PM PDT 24
Finished Jul 05 05:42:08 PM PDT 24
Peak memory 283488 kb
Host smart-df521137-5127-4f73-8231-b36b39021d1a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2156273623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.2156273623
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.3889225362
Short name T671
Test name
Test status
Simulation time 160681964 ps
CPU time 0.99 seconds
Started Jul 05 05:33:32 PM PDT 24
Finished Jul 05 05:33:34 PM PDT 24
Peak memory 217192 kb
Host smart-17d5717f-a200-4ecf-9231-bbadc436eb08
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889225362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.3889225362
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.3359971556
Short name T102
Test name
Test status
Simulation time 60433219 ps
CPU time 0.95 seconds
Started Jul 05 05:33:36 PM PDT 24
Finished Jul 05 05:33:37 PM PDT 24
Peak memory 208520 kb
Host smart-2cd93ca1-0c57-4b8b-ab0f-d64fa0bbe65c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359971556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.3359971556
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.4261509994
Short name T242
Test name
Test status
Simulation time 31326759 ps
CPU time 0.93 seconds
Started Jul 05 05:33:32 PM PDT 24
Finished Jul 05 05:33:34 PM PDT 24
Peak memory 208440 kb
Host smart-806ae07a-ffb3-4871-93c3-4d5390b0bc88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261509994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.4261509994
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.1404496855
Short name T109
Test name
Test status
Simulation time 2079841846 ps
CPU time 18.48 seconds
Started Jul 05 05:33:32 PM PDT 24
Finished Jul 05 05:33:51 PM PDT 24
Peak memory 217792 kb
Host smart-798b8528-4cd0-4214-a6a4-7fa951c24d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404496855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.1404496855
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.4073633350
Short name T80
Test name
Test status
Simulation time 1620380126 ps
CPU time 7.85 seconds
Started Jul 05 05:33:37 PM PDT 24
Finished Jul 05 05:33:46 PM PDT 24
Peak memory 217208 kb
Host smart-448e03b0-a707-4720-a73f-dee5a87f3ced
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073633350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.4073633350
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.925445820
Short name T747
Test name
Test status
Simulation time 7096302757 ps
CPU time 56.83 seconds
Started Jul 05 05:33:37 PM PDT 24
Finished Jul 05 05:34:35 PM PDT 24
Peak memory 218444 kb
Host smart-38d89cbb-52c4-41d4-a20d-d449f4a8a44d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925445820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_err
ors.925445820
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.2215109902
Short name T358
Test name
Test status
Simulation time 384289420 ps
CPU time 9.85 seconds
Started Jul 05 05:33:38 PM PDT 24
Finished Jul 05 05:33:48 PM PDT 24
Peak memory 217184 kb
Host smart-d1c28326-92d6-497c-a108-867d53c8b29a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215109902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.2
215109902
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.3721678007
Short name T594
Test name
Test status
Simulation time 2290902317 ps
CPU time 6.15 seconds
Started Jul 05 05:33:36 PM PDT 24
Finished Jul 05 05:33:43 PM PDT 24
Peak memory 217716 kb
Host smart-154ae52e-da7d-4a92-97b6-15db7dfea858
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721678007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.3721678007
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.933515048
Short name T800
Test name
Test status
Simulation time 2643756974 ps
CPU time 19.17 seconds
Started Jul 05 05:33:37 PM PDT 24
Finished Jul 05 05:33:57 PM PDT 24
Peak memory 216952 kb
Host smart-c10f0cbc-bb4a-43ac-9895-68836226a8d6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933515048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j
tag_regwen_during_op.933515048
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.3686701596
Short name T94
Test name
Test status
Simulation time 337125934 ps
CPU time 5.34 seconds
Started Jul 05 05:33:28 PM PDT 24
Finished Jul 05 05:33:34 PM PDT 24
Peak memory 217060 kb
Host smart-c502ea67-e3e9-41fd-9735-641af5e9318a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686701596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
3686701596
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.3798224243
Short name T789
Test name
Test status
Simulation time 11732251454 ps
CPU time 68.01 seconds
Started Jul 05 05:33:43 PM PDT 24
Finished Jul 05 05:34:51 PM PDT 24
Peak memory 267612 kb
Host smart-e89f764a-2762-48b8-8832-937ea1c37a35
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798224243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.3798224243
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.1466302887
Short name T515
Test name
Test status
Simulation time 429359426 ps
CPU time 12.26 seconds
Started Jul 05 05:33:41 PM PDT 24
Finished Jul 05 05:33:54 PM PDT 24
Peak memory 250464 kb
Host smart-be17d795-566b-40f0-ae4e-6a62d45fc45d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466302887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.1466302887
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.330000335
Short name T636
Test name
Test status
Simulation time 109074913 ps
CPU time 1.71 seconds
Started Jul 05 05:33:32 PM PDT 24
Finished Jul 05 05:33:35 PM PDT 24
Peak memory 217788 kb
Host smart-a6200d2d-2485-4cd1-91fc-191fa73ab9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330000335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.330000335
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.2057749326
Short name T863
Test name
Test status
Simulation time 660486804 ps
CPU time 10.75 seconds
Started Jul 05 05:33:33 PM PDT 24
Finished Jul 05 05:33:45 PM PDT 24
Peak memory 214060 kb
Host smart-87dc2617-0905-4013-9f07-14239a447133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057749326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.2057749326
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.1354437094
Short name T422
Test name
Test status
Simulation time 1645050772 ps
CPU time 18.85 seconds
Started Jul 05 05:33:41 PM PDT 24
Finished Jul 05 05:34:01 PM PDT 24
Peak memory 225584 kb
Host smart-931e083e-def3-4cad-8020-a2258a56cfaf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354437094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.1354437094
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.4146584366
Short name T722
Test name
Test status
Simulation time 1312840663 ps
CPU time 9.82 seconds
Started Jul 05 05:33:37 PM PDT 24
Finished Jul 05 05:33:47 PM PDT 24
Peak memory 225524 kb
Host smart-32b0fb9d-114d-41ca-b401-5c11303efd39
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146584366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.4146584366
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.2636880877
Short name T523
Test name
Test status
Simulation time 335379079 ps
CPU time 9.26 seconds
Started Jul 05 05:33:41 PM PDT 24
Finished Jul 05 05:33:51 PM PDT 24
Peak memory 217708 kb
Host smart-a0d4d4da-3d2e-497a-bfd0-1f7660bf2c2c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636880877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.2
636880877
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.3544020382
Short name T338
Test name
Test status
Simulation time 226333272 ps
CPU time 8.6 seconds
Started Jul 05 05:33:28 PM PDT 24
Finished Jul 05 05:33:37 PM PDT 24
Peak memory 217944 kb
Host smart-65c46bca-9b16-47a6-8357-f96a12ed2f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544020382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.3544020382
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.2420276404
Short name T202
Test name
Test status
Simulation time 124299356 ps
CPU time 3.13 seconds
Started Jul 05 05:33:33 PM PDT 24
Finished Jul 05 05:33:37 PM PDT 24
Peak memory 217212 kb
Host smart-151956d2-fee8-4544-91cc-62d98fb7bc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420276404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.2420276404
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.4287676204
Short name T571
Test name
Test status
Simulation time 1010674058 ps
CPU time 26.03 seconds
Started Jul 05 05:33:33 PM PDT 24
Finished Jul 05 05:34:00 PM PDT 24
Peak memory 247024 kb
Host smart-e4f07965-97a4-4fe1-80fc-b09c0319cb6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287676204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.4287676204
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.2754200632
Short name T390
Test name
Test status
Simulation time 95835299 ps
CPU time 3.97 seconds
Started Jul 05 05:33:32 PM PDT 24
Finished Jul 05 05:33:38 PM PDT 24
Peak memory 225956 kb
Host smart-0c416e9c-0970-4f9a-b6e6-3931359856b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754200632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.2754200632
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.3132077690
Short name T377
Test name
Test status
Simulation time 9720662079 ps
CPU time 179.3 seconds
Started Jul 05 05:33:37 PM PDT 24
Finished Jul 05 05:36:36 PM PDT 24
Peak memory 279196 kb
Host smart-31f27e62-6e06-44e2-bb4e-981ac424b9e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132077690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.3132077690
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.109346210
Short name T851
Test name
Test status
Simulation time 32676931 ps
CPU time 0.78 seconds
Started Jul 05 05:33:29 PM PDT 24
Finished Jul 05 05:33:30 PM PDT 24
Peak memory 208172 kb
Host smart-318de1c9-567c-4da6-80bc-2107dfc214d6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109346210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctr
l_volatile_unlock_smoke.109346210
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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