Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51290 |
1 |
|
|
T1 |
1 |
|
T3 |
85 |
|
T4 |
15 |
auto[1] |
1817 |
1 |
|
|
T36 |
7 |
|
T37 |
5 |
|
T38 |
11 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52493 |
1 |
|
|
T1 |
1 |
|
T3 |
85 |
|
T4 |
15 |
auto[1] |
614 |
1 |
|
|
T16 |
11 |
|
T65 |
11 |
|
T47 |
9 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51213 |
1 |
|
|
T1 |
1 |
|
T3 |
85 |
|
T4 |
13 |
auto[1] |
1894 |
1 |
|
|
T4 |
2 |
|
T45 |
1 |
|
T51 |
8 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51181 |
1 |
|
|
T1 |
1 |
|
T3 |
85 |
|
T4 |
14 |
auto[1] |
1926 |
1 |
|
|
T4 |
1 |
|
T12 |
1 |
|
T45 |
1 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51138 |
1 |
|
|
T1 |
1 |
|
T3 |
85 |
|
T4 |
15 |
auto[1] |
1969 |
1 |
|
|
T45 |
1 |
|
T51 |
12 |
|
T22 |
15 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
48851 |
1 |
|
|
T1 |
1 |
|
T3 |
85 |
|
T4 |
6 |
no_err_inj |
4256 |
1 |
|
|
T4 |
9 |
|
T12 |
8 |
|
T14 |
7 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51324 |
1 |
|
|
T1 |
1 |
|
T3 |
85 |
|
T4 |
15 |
auto[1] |
1783 |
1 |
|
|
T36 |
3 |
|
T37 |
8 |
|
T38 |
9 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52440 |
1 |
|
|
T1 |
1 |
|
T3 |
85 |
|
T4 |
15 |
auto[1] |
667 |
1 |
|
|
T16 |
14 |
|
T65 |
23 |
|
T47 |
12 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
38370 |
1 |
|
|
T1 |
1 |
|
T3 |
85 |
|
T12 |
14 |
auto[1] |
14737 |
1 |
|
|
T4 |
15 |
|
T9 |
5 |
|
T18 |
8 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51117 |
1 |
|
|
T1 |
1 |
|
T3 |
85 |
|
T4 |
15 |
auto[1] |
1990 |
1 |
|
|
T12 |
1 |
|
T51 |
11 |
|
T22 |
18 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51219 |
1 |
|
|
T1 |
1 |
|
T3 |
85 |
|
T4 |
15 |
auto[1] |
1888 |
1 |
|
|
T51 |
8 |
|
T22 |
17 |
|
T64 |
6 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51140 |
1 |
|
|
T1 |
1 |
|
T3 |
85 |
|
T4 |
13 |
auto[1] |
1967 |
1 |
|
|
T4 |
2 |
|
T12 |
3 |
|
T45 |
1 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51246 |
1 |
|
|
T1 |
1 |
|
T3 |
85 |
|
T4 |
15 |
auto[1] |
1861 |
1 |
|
|
T36 |
5 |
|
T37 |
2 |
|
T38 |
9 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50730 |
1 |
|
|
T3 |
85 |
|
T4 |
15 |
|
T12 |
14 |
auto[1] |
2377 |
1 |
|
|
T1 |
1 |
|
T9 |
5 |
|
T31 |
11 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52415 |
1 |
|
|
T1 |
1 |
|
T3 |
85 |
|
T4 |
15 |
auto[1] |
692 |
1 |
|
|
T16 |
15 |
|
T65 |
20 |
|
T47 |
17 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52445 |
1 |
|
|
T1 |
1 |
|
T3 |
85 |
|
T4 |
15 |
auto[1] |
662 |
1 |
|
|
T16 |
12 |
|
T65 |
23 |
|
T47 |
15 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52448 |
1 |
|
|
T1 |
1 |
|
T3 |
85 |
|
T4 |
15 |
auto[1] |
659 |
1 |
|
|
T16 |
9 |
|
T65 |
14 |
|
T47 |
19 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50645 |
1 |
|
|
T1 |
1 |
|
T3 |
85 |
|
T13 |
84 |
auto[1] |
2462 |
1 |
|
|
T4 |
15 |
|
T12 |
14 |
|
T45 |
12 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49355 |
1 |
|
|
T1 |
1 |
|
T3 |
85 |
|
T4 |
15 |
auto[1] |
3752 |
1 |
|
|
T17 |
99 |
|
T44 |
90 |
|
T39 |
99 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51210 |
1 |
|
|
T1 |
1 |
|
T3 |
85 |
|
T4 |
15 |
auto[1] |
1897 |
1 |
|
|
T12 |
1 |
|
T51 |
10 |
|
T22 |
17 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51112 |
1 |
|
|
T1 |
1 |
|
T3 |
85 |
|
T4 |
14 |
auto[1] |
1995 |
1 |
|
|
T4 |
1 |
|
T51 |
11 |
|
T22 |
15 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51186 |
1 |
|
|
T1 |
1 |
|
T3 |
85 |
|
T4 |
15 |
auto[1] |
1921 |
1 |
|
|
T45 |
2 |
|
T51 |
10 |
|
T22 |
22 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51294 |
1 |
|
|
T1 |
1 |
|
T3 |
85 |
|
T4 |
15 |
auto[1] |
1813 |
1 |
|
|
T36 |
6 |
|
T37 |
10 |
|
T38 |
11 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47593 |
1 |
|
|
T1 |
1 |
|
T4 |
15 |
|
T12 |
14 |
auto[1] |
5514 |
1 |
|
|
T3 |
85 |
|
T13 |
84 |
|
T15 |
52 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49364 |
1 |
|
|
T1 |
1 |
|
T3 |
85 |
|
T4 |
15 |
auto[1] |
3743 |
1 |
|
|
T30 |
92 |
|
T59 |
58 |
|
T42 |
97 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53107 |
1 |
|
|
T1 |
1 |
|
T3 |
85 |
|
T4 |
15 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51293 |
1 |
|
|
T1 |
1 |
|
T3 |
85 |
|
T4 |
15 |
auto[1] |
1814 |
1 |
|
|
T36 |
11 |
|
T37 |
8 |
|
T38 |
11 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51277 |
1 |
|
|
T1 |
1 |
|
T3 |
85 |
|
T4 |
15 |
auto[1] |
1830 |
1 |
|
|
T36 |
6 |
|
T37 |
14 |
|
T38 |
9 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51301 |
1 |
|
|
T1 |
1 |
|
T3 |
85 |
|
T4 |
15 |
auto[1] |
1806 |
1 |
|
|
T36 |
5 |
|
T37 |
16 |
|
T38 |
8 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
47598 |
1 |
|
|
T1 |
1 |
|
T3 |
85 |
|
T13 |
84 |
auto[0] |
no_err_inj |
3047 |
1 |
|
|
T14 |
7 |
|
T18 |
8 |
|
T60 |
6 |
auto[1] |
err_inj |
1253 |
1 |
|
|
T4 |
6 |
|
T12 |
6 |
|
T45 |
6 |
auto[1] |
no_err_inj |
1209 |
1 |
|
|
T4 |
9 |
|
T12 |
8 |
|
T45 |
6 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48798 |
1 |
|
|
T1 |
1 |
|
T3 |
85 |
|
T13 |
84 |
auto[0] |
auto[1] |
1847 |
1 |
|
|
T51 |
11 |
|
T22 |
15 |
|
T64 |
9 |
auto[1] |
auto[0] |
2314 |
1 |
|
|
T4 |
14 |
|
T12 |
14 |
|
T45 |
12 |
auto[1] |
auto[1] |
148 |
1 |
|
|
T4 |
1 |
|
T225 |
1 |
|
T226 |
2 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48876 |
1 |
|
|
T1 |
1 |
|
T3 |
85 |
|
T13 |
84 |
auto[0] |
auto[1] |
1769 |
1 |
|
|
T51 |
8 |
|
T22 |
17 |
|
T64 |
6 |
auto[1] |
auto[0] |
2343 |
1 |
|
|
T4 |
15 |
|
T12 |
14 |
|
T45 |
12 |
auto[1] |
auto[1] |
119 |
1 |
|
|
T96 |
2 |
|
T225 |
2 |
|
T226 |
1 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48865 |
1 |
|
|
T1 |
1 |
|
T3 |
85 |
|
T13 |
84 |
auto[0] |
auto[1] |
1780 |
1 |
|
|
T51 |
10 |
|
T22 |
22 |
|
T64 |
10 |
auto[1] |
auto[0] |
2321 |
1 |
|
|
T4 |
15 |
|
T12 |
14 |
|
T45 |
10 |
auto[1] |
auto[1] |
141 |
1 |
|
|
T45 |
2 |
|
T96 |
1 |
|
T94 |
2 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48848 |
1 |
|
|
T1 |
1 |
|
T3 |
85 |
|
T13 |
84 |
auto[0] |
auto[1] |
1797 |
1 |
|
|
T51 |
7 |
|
T22 |
13 |
|
T64 |
4 |
auto[1] |
auto[0] |
2333 |
1 |
|
|
T4 |
14 |
|
T12 |
13 |
|
T45 |
11 |
auto[1] |
auto[1] |
129 |
1 |
|
|
T4 |
1 |
|
T12 |
1 |
|
T45 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48833 |
1 |
|
|
T1 |
1 |
|
T3 |
85 |
|
T13 |
84 |
auto[0] |
auto[1] |
1812 |
1 |
|
|
T51 |
12 |
|
T22 |
15 |
|
T64 |
8 |
auto[1] |
auto[0] |
2305 |
1 |
|
|
T4 |
15 |
|
T12 |
14 |
|
T45 |
11 |
auto[1] |
auto[1] |
157 |
1 |
|
|
T45 |
1 |
|
T96 |
1 |
|
T225 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48900 |
1 |
|
|
T1 |
1 |
|
T3 |
85 |
|
T13 |
84 |
auto[0] |
auto[1] |
1745 |
1 |
|
|
T51 |
8 |
|
T22 |
28 |
|
T64 |
6 |
auto[1] |
auto[0] |
2313 |
1 |
|
|
T4 |
13 |
|
T12 |
14 |
|
T45 |
11 |
auto[1] |
auto[1] |
149 |
1 |
|
|
T4 |
2 |
|
T45 |
1 |
|
T94 |
2 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37203 |
1 |
|
|
T1 |
1 |
|
T3 |
85 |
|
T12 |
14 |
auto[0] |
auto[1] |
1167 |
1 |
|
|
T36 |
7 |
|
T37 |
5 |
|
T38 |
11 |
auto[1] |
auto[0] |
14087 |
1 |
|
|
T4 |
15 |
|
T9 |
5 |
|
T18 |
8 |
auto[1] |
auto[1] |
650 |
1 |
|
|
T22 |
12 |
|
T40 |
4 |
|
T97 |
13 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37216 |
1 |
|
|
T1 |
1 |
|
T3 |
85 |
|
T12 |
14 |
auto[0] |
auto[1] |
1154 |
1 |
|
|
T36 |
3 |
|
T37 |
8 |
|
T38 |
9 |
auto[1] |
auto[0] |
14108 |
1 |
|
|
T4 |
15 |
|
T9 |
5 |
|
T18 |
8 |
auto[1] |
auto[1] |
629 |
1 |
|
|
T22 |
11 |
|
T40 |
3 |
|
T97 |
9 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37009 |
1 |
|
|
T3 |
85 |
|
T12 |
14 |
|
T13 |
84 |
auto[0] |
auto[1] |
1361 |
1 |
|
|
T1 |
1 |
|
T31 |
11 |
|
T22 |
4 |
auto[1] |
auto[0] |
13721 |
1 |
|
|
T4 |
15 |
|
T18 |
8 |
|
T20 |
17 |
auto[1] |
auto[1] |
1016 |
1 |
|
|
T9 |
5 |
|
T22 |
20 |
|
T40 |
19 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37142 |
1 |
|
|
T1 |
1 |
|
T3 |
85 |
|
T12 |
14 |
auto[0] |
auto[1] |
1228 |
1 |
|
|
T36 |
5 |
|
T37 |
2 |
|
T38 |
9 |
auto[1] |
auto[0] |
14104 |
1 |
|
|
T4 |
15 |
|
T9 |
5 |
|
T18 |
8 |
auto[1] |
auto[1] |
633 |
1 |
|
|
T22 |
10 |
|
T40 |
5 |
|
T97 |
12 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33496 |
1 |
|
|
T1 |
1 |
|
T12 |
14 |
|
T14 |
7 |
auto[0] |
auto[1] |
4874 |
1 |
|
|
T3 |
85 |
|
T13 |
84 |
|
T15 |
52 |
auto[1] |
auto[0] |
14097 |
1 |
|
|
T4 |
15 |
|
T9 |
5 |
|
T18 |
8 |
auto[1] |
auto[1] |
640 |
1 |
|
|
T22 |
12 |
|
T40 |
7 |
|
T97 |
11 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37143 |
1 |
|
|
T1 |
1 |
|
T3 |
85 |
|
T12 |
14 |
auto[0] |
auto[1] |
1227 |
1 |
|
|
T51 |
11 |
|
T22 |
6 |
|
T64 |
9 |
auto[1] |
auto[0] |
13969 |
1 |
|
|
T4 |
14 |
|
T9 |
5 |
|
T18 |
8 |
auto[1] |
auto[1] |
768 |
1 |
|
|
T4 |
1 |
|
T22 |
9 |
|
T110 |
8 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37229 |
1 |
|
|
T1 |
1 |
|
T3 |
85 |
|
T12 |
13 |
auto[0] |
auto[1] |
1141 |
1 |
|
|
T12 |
1 |
|
T51 |
10 |
|
T22 |
10 |
auto[1] |
auto[0] |
13981 |
1 |
|
|
T4 |
15 |
|
T9 |
5 |
|
T18 |
8 |
auto[1] |
auto[1] |
756 |
1 |
|
|
T22 |
7 |
|
T110 |
10 |
|
T94 |
12 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37202 |
1 |
|
|
T1 |
1 |
|
T3 |
85 |
|
T12 |
14 |
auto[0] |
auto[1] |
1168 |
1 |
|
|
T51 |
8 |
|
T22 |
6 |
|
T64 |
6 |
auto[1] |
auto[0] |
14017 |
1 |
|
|
T4 |
15 |
|
T9 |
5 |
|
T18 |
8 |
auto[1] |
auto[1] |
720 |
1 |
|
|
T22 |
11 |
|
T110 |
4 |
|
T94 |
8 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37140 |
1 |
|
|
T1 |
1 |
|
T3 |
85 |
|
T12 |
13 |
auto[0] |
auto[1] |
1230 |
1 |
|
|
T12 |
1 |
|
T51 |
11 |
|
T22 |
5 |
auto[1] |
auto[0] |
13977 |
1 |
|
|
T4 |
15 |
|
T9 |
5 |
|
T18 |
8 |
auto[1] |
auto[1] |
760 |
1 |
|
|
T22 |
13 |
|
T110 |
8 |
|
T94 |
10 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37179 |
1 |
|
|
T1 |
1 |
|
T3 |
85 |
|
T12 |
13 |
auto[0] |
auto[1] |
1191 |
1 |
|
|
T12 |
1 |
|
T45 |
1 |
|
T51 |
7 |
auto[1] |
auto[0] |
14002 |
1 |
|
|
T4 |
14 |
|
T9 |
5 |
|
T18 |
8 |
auto[1] |
auto[1] |
735 |
1 |
|
|
T4 |
1 |
|
T22 |
6 |
|
T110 |
7 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37187 |
1 |
|
|
T1 |
1 |
|
T3 |
85 |
|
T12 |
14 |
auto[0] |
auto[1] |
1183 |
1 |
|
|
T45 |
1 |
|
T51 |
8 |
|
T22 |
9 |
auto[1] |
auto[0] |
14026 |
1 |
|
|
T4 |
13 |
|
T9 |
5 |
|
T18 |
8 |
auto[1] |
auto[1] |
711 |
1 |
|
|
T4 |
2 |
|
T22 |
19 |
|
T110 |
9 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37236 |
1 |
|
|
T1 |
1 |
|
T3 |
85 |
|
T12 |
14 |
auto[0] |
auto[1] |
1134 |
1 |
|
|
T36 |
5 |
|
T37 |
16 |
|
T38 |
8 |
auto[1] |
auto[0] |
14065 |
1 |
|
|
T4 |
15 |
|
T9 |
5 |
|
T18 |
8 |
auto[1] |
auto[1] |
672 |
1 |
|
|
T22 |
9 |
|
T40 |
12 |
|
T97 |
7 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37162 |
1 |
|
|
T1 |
1 |
|
T3 |
85 |
|
T12 |
14 |
auto[0] |
auto[1] |
1208 |
1 |
|
|
T36 |
6 |
|
T37 |
14 |
|
T38 |
9 |
auto[1] |
auto[0] |
14115 |
1 |
|
|
T4 |
15 |
|
T9 |
5 |
|
T18 |
8 |
auto[1] |
auto[1] |
622 |
1 |
|
|
T22 |
12 |
|
T40 |
3 |
|
T97 |
5 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36939 |
1 |
|
|
T1 |
1 |
|
T3 |
85 |
|
T13 |
84 |
auto[0] |
auto[1] |
1431 |
1 |
|
|
T12 |
14 |
|
T45 |
12 |
|
T96 |
12 |
auto[1] |
auto[0] |
13706 |
1 |
|
|
T9 |
5 |
|
T18 |
8 |
|
T20 |
17 |
auto[1] |
auto[1] |
1031 |
1 |
|
|
T4 |
15 |
|
T94 |
22 |
|
T61 |
15 |