Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

98419506

1

T1

1305

T2

853

T3

42339

auto[1]

1417581

1

T1

99

T4

98

T12

198

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

98420618

1

T1

1404

T2

853

T3

42339

auto[1]

1416469

1

T4

294

T12

99

T16

1089

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7128235	1			T1	226		T2	142		T3	8000
auto[IdleSt]	20630651	1			T1	989		T2	711		T3	7528
auto[ClkMuxSt]	34485	1			T1	1		T3	85		T4	9
auto[CntIncrSt]	34302	1			T1	1		T3	85		T4	9
auto[CntProgSt]	1405075	1			T1	12		T3	3121		T4	2370
auto[TransCheckSt]	26548	1			T3	85		T4	9		T12	8
auto[TokenHashSt]	40702663	1			T3	8640		T4	4374		T12	88
auto[FlashRmaSt]	33374	1			T4	31		T12	47		T14	7
auto[TokenCheck0St]	12086	1			T4	9		T12	8		T14	7
auto[TokenCheck1St]	8892	1			T4	9		T12	8		T14	7
auto[TransProgSt]	379653	1			T4	2097		T12	79		T14	642
auto[PostTransSt]	11842678	1			T1	65		T3	14795		T4	16043
auto[ScrapSt]	138132	1			T17	6		T44	12		T39	3
auto[EscalateSt]	6549679	1			T1	110		T4	4608		T12	710
auto[InvalidSt]	10908675	1			T4	4913		T12	427		T16	950

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1959	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	10908675	1			T4	4913		T12	427		T16	950
EscalateSt	6549679	1			T1	110		T4	4608		T12	710
ScrapSt	138132	1			T17	6		T44	12		T39	3
PostTransSt	11842678	1			T1	65		T3	14795		T4	16043
TransProgSt	379653	1			T4	2097		T12	79		T14	642
TokenCheck1St	8892	1			T4	9		T12	8		T14	7
TokenCheck0St	12086	1			T4	9		T12	8		T14	7
FlashRmaSt	33374	1			T4	31		T12	47		T14	7
TokenHashSt	40702663	1			T3	8640		T4	4374		T12	88
TransCheckSt	26548	1			T3	85		T4	9		T12	8
CntProgSt	1405075	1			T1	12		T3	3121		T4	2370
CntIncrSt	34302	1			T1	1		T3	85		T4	9
ClkMuxSt	34485	1			T1	1		T3	85		T4	9
IdleSt	20630651	1			T1	989		T2	711		T3	7528
ResetSt	7128235	1			T1	226		T2	142		T3	8000
arcs[ResetSt=>IdleSt]	53259	1			T1	2		T2	1		T3	86
arcs[IdleSt=>ScrapSt]	279	1			T17	2		T44	4		T39	1
arcs[IdleSt=>ClkMuxSt]	34363	1			T1	1		T3	85		T4	9
arcs[ClkMuxSt=>CntIncrSt]	34302	1			T1	1		T3	85		T4	9
arcs[CntIncrSt=>PostTransSt]	1832	1			T36	6		T37	14		T38	9
arcs[CntIncrSt=>CntProgSt]	32381	1			T1	1		T3	85		T4	9
arcs[CntProgSt=>PostTransSt]	4765	1			T1	1		T16	11		T9	5
arcs[CntProgSt=>TransCheckSt]	26548	1			T3	85		T4	9		T12	8
arcs[TransCheckSt=>PostTransSt]	3623	1			T30	46		T59	25		T36	5
arcs[TransCheckSt=>TokenHashSt]	22805	1			T3	85		T4	9		T12	8
arcs[TokenHashSt=>PostTransSt]	9952	1			T3	85		T13	84		T15	52
arcs[TokenHashSt=>FlashRmaSt]	12197	1			T4	9		T12	8		T14	7
arcs[FlashRmaSt=>TokenCheck0St]	12086	1			T4	9		T12	8		T14	7
arcs[TokenCheck0St=>PostTransSt]	3173	1			T16	14		T30	27		T59	16
arcs[TokenCheck0St=>TokenCheck1St]	8892	1			T4	9		T12	8		T14	7
arcs[TokenCheck1St=>PostTransSt]	664	1			T30	8		T59	9		T36	1
arcs[TransProgSt=>PostTransSt]	7342	1			T4	9		T12	8		T14	7
arcs[IdleSt=>EscalateSt]	211	1			T44	9		T53	11		T54	3
arcs[ClkMuxSt=>EscalateSt]	61	1			T52	2		T53	1		T54	1
arcs[CntIncrSt=>EscalateSt]	89	1			T17	2		T44	1		T39	2
arcs[CntProgSt=>EscalateSt]	1068	1			T17	16		T44	9		T39	43
arcs[TransCheckSt=>EscalateSt]	120	1			T17	10		T44	10		T52	4
arcs[TokenHashSt=>EscalateSt]	656	1			T17	28		T44	25		T39	11
arcs[FlashRmaSt=>EscalateSt]	111	1			T17	2		T44	2		T39	3
arcs[TokenCheck0St=>EscalateSt]	21	1			T17	2		T39	2		T58	1
arcs[TokenCheck1St=>EscalateSt]	155	1			T17	5		T44	3		T39	2
arcs[TransProgSt=>EscalateSt]	731	1			T17	13		T44	9		T39	22
arcs[PostTransSt=>EscalateSt]	5014	1			T1	1		T16	11		T17	15
arcs[InvalidSt=>EscalateSt]	14235	1			T4	4		T12	3		T16	12

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7128043	1			T1	226		T2	142		T3	8000
auto[0]	auto[IdleSt]	20630510	1			T1	989		T2	711		T3	7528
auto[0]	auto[ClkMuxSt]	34437	1			T1	1		T3	85		T4	9
auto[0]	auto[CntIncrSt]	34240	1			T1	1		T3	85		T4	9
auto[0]	auto[CntProgSt]	1404350	1			T1	12		T3	3121		T4	2370
auto[0]	auto[TransCheckSt]	26463	1			T3	85		T4	9		T12	8
auto[0]	auto[TokenHashSt]	40702238	1			T3	8640		T4	4374		T12	88
auto[0]	auto[FlashRmaSt]	33298	1			T4	31		T12	47		T14	7
auto[0]	auto[TokenCheck0St]	12074	1			T4	9		T12	8		T14	7
auto[0]	auto[TokenCheck1St]	8787	1			T4	9		T12	8		T14	7
auto[0]	auto[TransProgSt]	379195	1			T4	2097		T12	79		T14	642
auto[0]	auto[PostTransSt]	11840117	1			T1	64		T3	14795		T4	16043
auto[0]	auto[ScrapSt]	138084	1			T17	4		T44	10		T39	3
auto[0]	auto[EscalateSt]	5144136	1			T1	12		T4	4511		T12	514
auto[0]	auto[InvalidSt]	10901575	1			T4	4912		T12	425		T16	944
auto[1]	auto[ResetSt]	192	1			T17	4		T44	3		T39	11
auto[1]	auto[IdleSt]	141	1			T44	5		T53	9		T54	2
auto[1]	auto[ClkMuxSt]	48	1			T52	1		T53	1		T54	1
auto[1]	auto[CntIncrSt]	62	1			T44	1		T39	2		T52	3
auto[1]	auto[CntProgSt]	725	1			T17	12		T44	6		T39	27
auto[1]	auto[TransCheckSt]	85	1			T17	9		T44	7		T52	2
auto[1]	auto[TokenHashSt]	425	1			T17	22		T44	11		T39	10
auto[1]	auto[FlashRmaSt]	76	1			T17	1		T44	1		T39	3
auto[1]	auto[TokenCheck0St]	12	1			T17	1		T39	1		T223	1
auto[1]	auto[TokenCheck1St]	105	1			T17	5		T44	1		T39	1
auto[1]	auto[TransProgSt]	458	1			T17	7		T44	4		T39	15
auto[1]	auto[PostTransSt]	2561	1			T1	1		T16	6		T17	14
auto[1]	auto[ScrapSt]	48	1			T17	2		T44	2		T52	1
auto[1]	auto[EscalateSt]	1405543	1			T1	98		T4	97		T12	196
auto[1]	auto[InvalidSt]	7100	1			T4	1		T12	2		T16	6

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7128066	1			T1	226		T2	142		T3	8000
auto[0]	auto[IdleSt]	20630505	1			T1	989		T2	711		T3	7528
auto[0]	auto[ClkMuxSt]	34449	1			T1	1		T3	85		T4	9
auto[0]	auto[CntIncrSt]	34248	1			T1	1		T3	85		T4	9
auto[0]	auto[CntProgSt]	1404347	1			T1	12		T3	3121		T4	2370
auto[0]	auto[TransCheckSt]	26474	1			T3	85		T4	9		T12	8
auto[0]	auto[TokenHashSt]	40702222	1			T3	8640		T4	4374		T12	88
auto[0]	auto[FlashRmaSt]	33301	1			T4	31		T12	47		T14	7
auto[0]	auto[TokenCheck0St]	12073	1			T4	9		T12	8		T14	7
auto[0]	auto[TokenCheck1St]	8793	1			T4	9		T12	8		T14	7
auto[0]	auto[TransProgSt]	379147	1			T4	2097		T12	79		T14	642
auto[0]	auto[PostTransSt]	11840144	1			T1	65		T3	14795		T4	16043
auto[0]	auto[ScrapSt]	138095	1			T17	4		T44	10		T39	2
auto[0]	auto[EscalateSt]	5145255	1			T1	110		T4	4317		T12	612
auto[0]	auto[InvalidSt]	10901540	1			T4	4910		T12	426		T16	944
auto[1]	auto[ResetSt]	169	1			T17	1		T44	2		T39	7
auto[1]	auto[IdleSt]	146	1			T44	8		T53	8		T54	1
auto[1]	auto[ClkMuxSt]	36	1			T52	2		T53	1		T224	2
auto[1]	auto[CntIncrSt]	54	1			T17	2		T44	1		T52	1
auto[1]	auto[CntProgSt]	728	1			T17	10		T44	6		T39	31
auto[1]	auto[TransCheckSt]	74	1			T17	4		T44	8		T52	3
auto[1]	auto[TokenHashSt]	441	1			T17	16		T44	18		T39	4
auto[1]	auto[FlashRmaSt]	73	1			T17	2		T44	2		T39	1
auto[1]	auto[TokenCheck0St]	13	1			T17	1		T39	1		T58	1
auto[1]	auto[TokenCheck1St]	99	1			T17	4		T44	3		T39	2
auto[1]	auto[TransProgSt]	506	1			T17	7		T44	7		T39	16
auto[1]	auto[PostTransSt]	2534	1			T16	5		T17	7		T9	2
auto[1]	auto[ScrapSt]	37	1			T17	2		T44	2		T39	1
auto[1]	auto[EscalateSt]	1404424	1			T4	291		T12	98		T16	1078
auto[1]	auto[InvalidSt]	7135	1			T4	3		T12	1		T16	6