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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.17 97.99 95.68 93.38 100.00 98.55 98.51 96.11


Total test records in report: 991
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T819 /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.1547766487 Jul 06 07:16:08 PM PDT 24 Jul 06 07:17:31 PM PDT 24 15798800837 ps
T820 /workspace/coverage/default/4.lc_ctrl_smoke.3069895789 Jul 06 07:16:22 PM PDT 24 Jul 06 07:16:34 PM PDT 24 111319063 ps
T821 /workspace/coverage/default/3.lc_ctrl_alert_test.1267872934 Jul 06 07:16:20 PM PDT 24 Jul 06 07:16:26 PM PDT 24 20667365 ps
T822 /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.4097511397 Jul 06 07:15:06 PM PDT 24 Jul 06 07:16:20 PM PDT 24 1473371851 ps
T823 /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.3610126228 Jul 06 07:17:11 PM PDT 24 Jul 06 07:17:18 PM PDT 24 19426892 ps
T824 /workspace/coverage/default/12.lc_ctrl_sec_token_digest.3315116924 Jul 06 07:17:29 PM PDT 24 Jul 06 07:17:47 PM PDT 24 2078677586 ps
T825 /workspace/coverage/default/19.lc_ctrl_security_escalation.2740828643 Jul 06 07:18:06 PM PDT 24 Jul 06 07:18:18 PM PDT 24 619835020 ps
T167 /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.3260679690 Jul 06 07:19:16 PM PDT 24 Jul 06 07:38:14 PM PDT 24 180565040048 ps
T826 /workspace/coverage/default/21.lc_ctrl_smoke.158286718 Jul 06 07:18:12 PM PDT 24 Jul 06 07:18:16 PM PDT 24 142395359 ps
T91 /workspace/coverage/default/33.lc_ctrl_smoke.1900134445 Jul 06 07:18:57 PM PDT 24 Jul 06 07:19:00 PM PDT 24 88902695 ps
T827 /workspace/coverage/default/33.lc_ctrl_sec_token_mux.3773150778 Jul 06 07:18:58 PM PDT 24 Jul 06 07:19:11 PM PDT 24 848962166 ps
T828 /workspace/coverage/default/23.lc_ctrl_stress_all.3383709831 Jul 06 07:18:25 PM PDT 24 Jul 06 07:19:25 PM PDT 24 9703151285 ps
T829 /workspace/coverage/default/47.lc_ctrl_errors.3334850102 Jul 06 07:19:48 PM PDT 24 Jul 06 07:20:06 PM PDT 24 648020352 ps
T830 /workspace/coverage/default/16.lc_ctrl_stress_all.1648860918 Jul 06 07:17:54 PM PDT 24 Jul 06 07:21:50 PM PDT 24 15161011551 ps
T831 /workspace/coverage/default/43.lc_ctrl_prog_failure.3339695679 Jul 06 07:19:34 PM PDT 24 Jul 06 07:19:39 PM PDT 24 64869450 ps
T832 /workspace/coverage/default/47.lc_ctrl_sec_token_mux.3072061887 Jul 06 07:19:48 PM PDT 24 Jul 06 07:19:58 PM PDT 24 228195525 ps
T221 /workspace/coverage/default/7.lc_ctrl_claim_transition_if.2463273186 Jul 06 07:17:00 PM PDT 24 Jul 06 07:17:02 PM PDT 24 34882613 ps
T168 /workspace/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.2136966094 Jul 06 07:19:48 PM PDT 24 Jul 06 07:22:12 PM PDT 24 8252278860 ps
T833 /workspace/coverage/default/3.lc_ctrl_security_escalation.2958017164 Jul 06 07:16:00 PM PDT 24 Jul 06 07:16:29 PM PDT 24 1426836666 ps
T834 /workspace/coverage/default/44.lc_ctrl_smoke.2734029314 Jul 06 07:19:38 PM PDT 24 Jul 06 07:19:43 PM PDT 24 137972115 ps
T835 /workspace/coverage/default/27.lc_ctrl_security_escalation.1094661241 Jul 06 07:18:37 PM PDT 24 Jul 06 07:18:45 PM PDT 24 416522014 ps
T836 /workspace/coverage/default/3.lc_ctrl_sec_mubi.4066605574 Jul 06 07:16:14 PM PDT 24 Jul 06 07:16:34 PM PDT 24 293819477 ps
T837 /workspace/coverage/default/33.lc_ctrl_jtag_access.1975064742 Jul 06 07:18:57 PM PDT 24 Jul 06 07:19:07 PM PDT 24 431474086 ps
T838 /workspace/coverage/default/30.lc_ctrl_alert_test.46056003 Jul 06 07:18:54 PM PDT 24 Jul 06 07:18:56 PM PDT 24 123635698 ps
T839 /workspace/coverage/default/40.lc_ctrl_smoke.3112678344 Jul 06 07:19:24 PM PDT 24 Jul 06 07:19:27 PM PDT 24 24628082 ps
T840 /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.901888158 Jul 06 07:17:31 PM PDT 24 Jul 06 07:17:41 PM PDT 24 2732825669 ps
T841 /workspace/coverage/default/9.lc_ctrl_sec_mubi.1127329053 Jul 06 07:17:15 PM PDT 24 Jul 06 07:17:37 PM PDT 24 1551637335 ps
T180 /workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.4265354682 Jul 06 07:18:46 PM PDT 24 Jul 06 07:42:08 PM PDT 24 182087034862 ps
T842 /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.861992717 Jul 06 07:18:01 PM PDT 24 Jul 06 07:18:16 PM PDT 24 434386443 ps
T843 /workspace/coverage/default/48.lc_ctrl_errors.2962298030 Jul 06 07:19:55 PM PDT 24 Jul 06 07:20:10 PM PDT 24 421935187 ps
T844 /workspace/coverage/default/19.lc_ctrl_state_failure.140811525 Jul 06 07:18:09 PM PDT 24 Jul 06 07:18:28 PM PDT 24 2350065074 ps
T845 /workspace/coverage/default/43.lc_ctrl_state_failure.1377557250 Jul 06 07:19:37 PM PDT 24 Jul 06 07:20:05 PM PDT 24 373192656 ps
T846 /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.4234841946 Jul 06 07:18:09 PM PDT 24 Jul 06 07:19:19 PM PDT 24 2922192550 ps
T92 /workspace/coverage/default/29.lc_ctrl_stress_all.2262805241 Jul 06 07:18:52 PM PDT 24 Jul 06 07:19:46 PM PDT 24 2785390842 ps
T847 /workspace/coverage/default/0.lc_ctrl_sec_token_mux.1098027443 Jul 06 07:15:17 PM PDT 24 Jul 06 07:16:16 PM PDT 24 927534493 ps
T848 /workspace/coverage/default/31.lc_ctrl_jtag_access.2561726401 Jul 06 07:18:59 PM PDT 24 Jul 06 07:19:10 PM PDT 24 1224160164 ps
T849 /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.1964319715 Jul 06 07:19:40 PM PDT 24 Jul 06 07:19:42 PM PDT 24 35611592 ps
T850 /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.407719079 Jul 06 07:16:57 PM PDT 24 Jul 06 07:17:51 PM PDT 24 9399541013 ps
T851 /workspace/coverage/default/18.lc_ctrl_jtag_errors.2450981652 Jul 06 07:18:14 PM PDT 24 Jul 06 07:18:44 PM PDT 24 3487369312 ps
T852 /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.3085443338 Jul 06 07:18:30 PM PDT 24 Jul 06 07:18:32 PM PDT 24 15178143 ps
T853 /workspace/coverage/default/43.lc_ctrl_stress_all.888844486 Jul 06 07:19:36 PM PDT 24 Jul 06 07:20:20 PM PDT 24 3295470188 ps
T854 /workspace/coverage/default/3.lc_ctrl_prog_failure.1068591874 Jul 06 07:15:53 PM PDT 24 Jul 06 07:16:23 PM PDT 24 67915817 ps
T855 /workspace/coverage/default/16.lc_ctrl_state_failure.1754862546 Jul 06 07:17:47 PM PDT 24 Jul 06 07:18:25 PM PDT 24 707378308 ps
T856 /workspace/coverage/default/48.lc_ctrl_smoke.288426814 Jul 06 07:19:48 PM PDT 24 Jul 06 07:19:53 PM PDT 24 26450055 ps
T857 /workspace/coverage/default/45.lc_ctrl_sec_mubi.1040874030 Jul 06 07:19:49 PM PDT 24 Jul 06 07:20:03 PM PDT 24 317340156 ps
T858 /workspace/coverage/default/45.lc_ctrl_prog_failure.1213537055 Jul 06 07:19:41 PM PDT 24 Jul 06 07:19:44 PM PDT 24 36956373 ps
T859 /workspace/coverage/default/5.lc_ctrl_stress_all.853515824 Jul 06 07:16:46 PM PDT 24 Jul 06 07:17:57 PM PDT 24 992857270 ps
T860 /workspace/coverage/default/4.lc_ctrl_alert_test.1058053441 Jul 06 07:16:37 PM PDT 24 Jul 06 07:16:39 PM PDT 24 17630006 ps
T861 /workspace/coverage/default/22.lc_ctrl_jtag_access.57489136 Jul 06 07:18:28 PM PDT 24 Jul 06 07:18:34 PM PDT 24 177386628 ps
T862 /workspace/coverage/default/47.lc_ctrl_stress_all.3605552372 Jul 06 07:19:47 PM PDT 24 Jul 06 07:22:52 PM PDT 24 7939281156 ps
T863 /workspace/coverage/default/17.lc_ctrl_state_failure.2183524839 Jul 06 07:18:02 PM PDT 24 Jul 06 07:18:41 PM PDT 24 1062122128 ps
T864 /workspace/coverage/default/18.lc_ctrl_sec_token_mux.509483674 Jul 06 07:18:09 PM PDT 24 Jul 06 07:18:21 PM PDT 24 6099018386 ps
T865 /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.746625393 Jul 06 07:16:06 PM PDT 24 Jul 06 07:16:36 PM PDT 24 1478154096 ps
T866 /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.321319767 Jul 06 07:15:21 PM PDT 24 Jul 06 07:16:25 PM PDT 24 890503236 ps
T867 /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.2173673028 Jul 06 07:19:34 PM PDT 24 Jul 06 07:19:37 PM PDT 24 14330260 ps
T868 /workspace/coverage/default/1.lc_ctrl_jtag_errors.2182841162 Jul 06 07:15:23 PM PDT 24 Jul 06 07:17:11 PM PDT 24 4351416525 ps
T120 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.1538765867 Jul 06 07:10:40 PM PDT 24 Jul 06 07:10:42 PM PDT 24 19674110 ps
T121 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.61984184 Jul 06 07:10:13 PM PDT 24 Jul 06 07:10:20 PM PDT 24 51944408 ps
T113 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.4117932985 Jul 06 07:10:16 PM PDT 24 Jul 06 07:10:25 PM PDT 24 24210621 ps
T151 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2725468613 Jul 06 07:10:24 PM PDT 24 Jul 06 07:10:29 PM PDT 24 35552131 ps
T152 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3364045181 Jul 06 07:10:07 PM PDT 24 Jul 06 07:10:15 PM PDT 24 88900502 ps
T122 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2620209028 Jul 06 07:09:56 PM PDT 24 Jul 06 07:10:06 PM PDT 24 20912611 ps
T869 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1395768065 Jul 06 07:10:12 PM PDT 24 Jul 06 07:10:19 PM PDT 24 38364150 ps
T870 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1260633860 Jul 06 07:10:27 PM PDT 24 Jul 06 07:10:31 PM PDT 24 18023069 ps
T150 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2619262861 Jul 06 07:09:57 PM PDT 24 Jul 06 07:10:08 PM PDT 24 191898343 ps
T210 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.12009798 Jul 06 07:10:43 PM PDT 24 Jul 06 07:10:47 PM PDT 24 77056857 ps
T197 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.4052282580 Jul 06 07:10:16 PM PDT 24 Jul 06 07:10:24 PM PDT 24 20719733 ps
T198 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2037845743 Jul 06 07:10:07 PM PDT 24 Jul 06 07:10:15 PM PDT 24 57548408 ps
T211 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3488486125 Jul 06 07:10:20 PM PDT 24 Jul 06 07:10:27 PM PDT 24 19277482 ps
T114 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.407817826 Jul 06 07:10:17 PM PDT 24 Jul 06 07:10:25 PM PDT 24 243015394 ps
T146 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2310903455 Jul 06 07:10:08 PM PDT 24 Jul 06 07:10:16 PM PDT 24 458992508 ps
T212 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1549647790 Jul 06 07:10:17 PM PDT 24 Jul 06 07:10:24 PM PDT 24 15226433 ps
T147 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3447807506 Jul 06 07:09:56 PM PDT 24 Jul 06 07:10:18 PM PDT 24 1240893156 ps
T115 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1766410953 Jul 06 07:10:20 PM PDT 24 Jul 06 07:10:28 PM PDT 24 192562457 ps
T181 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.22475837 Jul 06 07:10:36 PM PDT 24 Jul 06 07:10:38 PM PDT 24 50300793 ps
T871 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.654768331 Jul 06 07:10:18 PM PDT 24 Jul 06 07:10:27 PM PDT 24 226985404 ps
T148 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.2487154047 Jul 06 07:10:20 PM PDT 24 Jul 06 07:10:29 PM PDT 24 973978914 ps
T213 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1540586840 Jul 06 07:10:42 PM PDT 24 Jul 06 07:10:46 PM PDT 24 18567972 ps
T116 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2870969727 Jul 06 07:10:23 PM PDT 24 Jul 06 07:10:30 PM PDT 24 286778668 ps
T118 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1125981405 Jul 06 07:10:42 PM PDT 24 Jul 06 07:10:45 PM PDT 24 61586177 ps
T214 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2283460539 Jul 06 07:09:59 PM PDT 24 Jul 06 07:10:08 PM PDT 24 354599107 ps
T125 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.4257542588 Jul 06 07:10:21 PM PDT 24 Jul 06 07:10:28 PM PDT 24 120566824 ps
T117 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3092837200 Jul 06 07:10:22 PM PDT 24 Jul 06 07:10:30 PM PDT 24 479549637 ps
T119 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2728866096 Jul 06 07:10:42 PM PDT 24 Jul 06 07:10:47 PM PDT 24 437439184 ps
T192 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3829288392 Jul 06 07:10:23 PM PDT 24 Jul 06 07:10:29 PM PDT 24 43670057 ps
T169 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1092482087 Jul 06 07:10:41 PM PDT 24 Jul 06 07:10:43 PM PDT 24 69875372 ps
T133 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1386126420 Jul 06 07:10:42 PM PDT 24 Jul 06 07:10:48 PM PDT 24 129158601 ps
T872 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.698939733 Jul 06 07:10:44 PM PDT 24 Jul 06 07:10:47 PM PDT 24 98749126 ps
T873 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.420919968 Jul 06 07:10:19 PM PDT 24 Jul 06 07:10:27 PM PDT 24 497046800 ps
T874 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1402558195 Jul 06 07:09:53 PM PDT 24 Jul 06 07:10:01 PM PDT 24 37001804 ps
T875 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1542049537 Jul 06 07:10:36 PM PDT 24 Jul 06 07:10:38 PM PDT 24 56685381 ps
T126 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2058487507 Jul 06 07:10:41 PM PDT 24 Jul 06 07:10:44 PM PDT 24 14791758 ps
T215 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.487168619 Jul 06 07:10:18 PM PDT 24 Jul 06 07:10:26 PM PDT 24 158233750 ps
T876 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2174228674 Jul 06 07:09:57 PM PDT 24 Jul 06 07:10:07 PM PDT 24 333569914 ps
T877 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3187379296 Jul 06 07:10:17 PM PDT 24 Jul 06 07:10:32 PM PDT 24 356042467 ps
T216 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2080455993 Jul 06 07:10:49 PM PDT 24 Jul 06 07:10:51 PM PDT 24 384616343 ps
T123 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2765137692 Jul 06 07:10:36 PM PDT 24 Jul 06 07:10:41 PM PDT 24 397542126 ps
T199 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2103701514 Jul 06 07:09:55 PM PDT 24 Jul 06 07:10:04 PM PDT 24 14264773 ps
T128 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3796904009 Jul 06 07:10:19 PM PDT 24 Jul 06 07:10:28 PM PDT 24 617517778 ps
T878 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3259516848 Jul 06 07:10:33 PM PDT 24 Jul 06 07:10:35 PM PDT 24 14971557 ps
T879 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.4052021134 Jul 06 07:10:08 PM PDT 24 Jul 06 07:10:27 PM PDT 24 588686521 ps
T880 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1492260232 Jul 06 07:10:42 PM PDT 24 Jul 06 07:10:46 PM PDT 24 84178049 ps
T881 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3633027721 Jul 06 07:10:29 PM PDT 24 Jul 06 07:10:36 PM PDT 24 4979943680 ps
T882 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1630689139 Jul 06 07:10:16 PM PDT 24 Jul 06 07:10:24 PM PDT 24 57413838 ps
T883 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3443342595 Jul 06 07:10:09 PM PDT 24 Jul 06 07:10:16 PM PDT 24 79269974 ps
T144 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.626202329 Jul 06 07:10:28 PM PDT 24 Jul 06 07:10:34 PM PDT 24 113598293 ps
T138 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.107539605 Jul 06 07:10:11 PM PDT 24 Jul 06 07:10:20 PM PDT 24 58796199 ps
T129 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1414729475 Jul 06 07:10:42 PM PDT 24 Jul 06 07:10:47 PM PDT 24 418960468 ps
T884 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.4216685268 Jul 06 07:09:52 PM PDT 24 Jul 06 07:10:00 PM PDT 24 82193757 ps
T885 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2076630928 Jul 06 07:09:54 PM PDT 24 Jul 06 07:10:03 PM PDT 24 35548648 ps
T886 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1106417709 Jul 06 07:10:13 PM PDT 24 Jul 06 07:10:22 PM PDT 24 189347161 ps
T887 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2351866299 Jul 06 07:10:01 PM PDT 24 Jul 06 07:10:11 PM PDT 24 92061857 ps
T200 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.625042995 Jul 06 07:09:56 PM PDT 24 Jul 06 07:10:05 PM PDT 24 11826028 ps
T143 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.4116638263 Jul 06 07:10:49 PM PDT 24 Jul 06 07:10:53 PM PDT 24 374138052 ps
T888 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2167444867 Jul 06 07:10:16 PM PDT 24 Jul 06 07:10:31 PM PDT 24 2201094718 ps
T889 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.3004022254 Jul 06 07:10:09 PM PDT 24 Jul 06 07:10:16 PM PDT 24 93783247 ps
T890 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2605135445 Jul 06 07:10:17 PM PDT 24 Jul 06 07:10:24 PM PDT 24 165087222 ps
T891 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.317602044 Jul 06 07:10:22 PM PDT 24 Jul 06 07:10:34 PM PDT 24 1611029924 ps
T124 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.948893259 Jul 06 07:10:43 PM PDT 24 Jul 06 07:10:48 PM PDT 24 544691652 ps
T134 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.472748308 Jul 06 07:09:54 PM PDT 24 Jul 06 07:10:04 PM PDT 24 529327837 ps
T892 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1022011993 Jul 06 07:10:09 PM PDT 24 Jul 06 07:10:28 PM PDT 24 8394905732 ps
T893 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3955790096 Jul 06 07:10:08 PM PDT 24 Jul 06 07:10:21 PM PDT 24 927065641 ps
T894 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.58810196 Jul 06 07:10:16 PM PDT 24 Jul 06 07:10:24 PM PDT 24 22280687 ps
T130 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3510140082 Jul 06 07:10:43 PM PDT 24 Jul 06 07:10:49 PM PDT 24 451472132 ps
T895 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1708685869 Jul 06 07:10:42 PM PDT 24 Jul 06 07:10:45 PM PDT 24 31211672 ps
T896 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1662998037 Jul 06 07:10:08 PM PDT 24 Jul 06 07:10:15 PM PDT 24 25416635 ps
T897 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.586678857 Jul 06 07:10:28 PM PDT 24 Jul 06 07:10:32 PM PDT 24 278405644 ps
T201 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1141879046 Jul 06 07:10:08 PM PDT 24 Jul 06 07:10:15 PM PDT 24 56290347 ps
T898 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3789196057 Jul 06 07:10:28 PM PDT 24 Jul 06 07:10:49 PM PDT 24 2204881704 ps
T899 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2065253168 Jul 06 07:10:13 PM PDT 24 Jul 06 07:10:24 PM PDT 24 528717084 ps
T202 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.4211534452 Jul 06 07:10:42 PM PDT 24 Jul 06 07:10:45 PM PDT 24 24640145 ps
T900 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3157511879 Jul 06 07:12:44 PM PDT 24 Jul 06 07:12:46 PM PDT 24 64635338 ps
T901 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3544640482 Jul 06 07:09:54 PM PDT 24 Jul 06 07:10:04 PM PDT 24 1121916400 ps
T902 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2157731082 Jul 06 07:09:53 PM PDT 24 Jul 06 07:10:03 PM PDT 24 975990194 ps
T903 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1174520409 Jul 06 07:10:23 PM PDT 24 Jul 06 07:10:29 PM PDT 24 676076020 ps
T904 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.770035398 Jul 06 07:09:52 PM PDT 24 Jul 06 07:10:00 PM PDT 24 36613325 ps
T905 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.223233882 Jul 06 07:10:41 PM PDT 24 Jul 06 07:10:43 PM PDT 24 15598341 ps
T906 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.830074705 Jul 06 07:10:30 PM PDT 24 Jul 06 07:10:33 PM PDT 24 42868853 ps
T907 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2513668960 Jul 06 07:10:15 PM PDT 24 Jul 06 07:10:26 PM PDT 24 161662568 ps
T203 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2716191419 Jul 06 07:09:59 PM PDT 24 Jul 06 07:10:09 PM PDT 24 30436036 ps
T908 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1938419626 Jul 06 07:09:54 PM PDT 24 Jul 06 07:10:03 PM PDT 24 69662287 ps
T137 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1875907269 Jul 06 07:09:57 PM PDT 24 Jul 06 07:10:08 PM PDT 24 65668425 ps
T127 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1921540501 Jul 06 07:10:44 PM PDT 24 Jul 06 07:10:49 PM PDT 24 740719130 ps
T909 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.729619449 Jul 06 07:10:33 PM PDT 24 Jul 06 07:10:36 PM PDT 24 93751627 ps
T910 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2509668546 Jul 06 07:10:23 PM PDT 24 Jul 06 07:10:38 PM PDT 24 5089869538 ps
T911 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1939586662 Jul 06 07:10:36 PM PDT 24 Jul 06 07:10:37 PM PDT 24 43563652 ps
T912 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3809642976 Jul 06 07:10:41 PM PDT 24 Jul 06 07:10:43 PM PDT 24 78240464 ps
T913 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1830526190 Jul 06 07:10:09 PM PDT 24 Jul 06 07:10:17 PM PDT 24 34921064 ps
T914 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.607743146 Jul 06 07:09:58 PM PDT 24 Jul 06 07:10:08 PM PDT 24 199746876 ps
T915 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1887759632 Jul 06 07:10:28 PM PDT 24 Jul 06 07:10:31 PM PDT 24 23767087 ps
T916 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3715792207 Jul 06 07:09:52 PM PDT 24 Jul 06 07:10:00 PM PDT 24 334931804 ps
T917 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.731496976 Jul 06 07:09:59 PM PDT 24 Jul 06 07:10:09 PM PDT 24 126428308 ps
T918 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1693912323 Jul 06 07:09:52 PM PDT 24 Jul 06 07:10:00 PM PDT 24 19763729 ps
T919 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3432041527 Jul 06 07:10:36 PM PDT 24 Jul 06 07:10:38 PM PDT 24 19677792 ps
T920 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2166173129 Jul 06 07:10:08 PM PDT 24 Jul 06 07:10:16 PM PDT 24 37141818 ps
T921 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.623270211 Jul 06 07:09:54 PM PDT 24 Jul 06 07:10:21 PM PDT 24 834149357 ps
T922 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.4076705369 Jul 06 07:10:18 PM PDT 24 Jul 06 07:10:25 PM PDT 24 73041292 ps
T204 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2011253633 Jul 06 07:10:42 PM PDT 24 Jul 06 07:10:45 PM PDT 24 16526356 ps
T923 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1245442721 Jul 06 07:10:29 PM PDT 24 Jul 06 07:10:32 PM PDT 24 239457786 ps
T924 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.234040398 Jul 06 07:10:09 PM PDT 24 Jul 06 07:10:16 PM PDT 24 45432045 ps
T925 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.4126895733 Jul 06 07:09:53 PM PDT 24 Jul 06 07:10:27 PM PDT 24 1246881589 ps
T926 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.2430033542 Jul 06 07:10:29 PM PDT 24 Jul 06 07:10:32 PM PDT 24 38745254 ps
T208 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.4069934372 Jul 06 07:10:23 PM PDT 24 Jul 06 07:10:28 PM PDT 24 39852715 ps
T927 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2496020069 Jul 06 07:10:28 PM PDT 24 Jul 06 07:10:34 PM PDT 24 44936263 ps
T205 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.4186847192 Jul 06 07:10:13 PM PDT 24 Jul 06 07:10:21 PM PDT 24 14618213 ps
T928 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3089997680 Jul 06 07:09:59 PM PDT 24 Jul 06 07:10:09 PM PDT 24 59614598 ps
T131 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2245466464 Jul 06 07:09:59 PM PDT 24 Jul 06 07:10:12 PM PDT 24 108525846 ps
T929 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.418715225 Jul 06 07:10:08 PM PDT 24 Jul 06 07:10:16 PM PDT 24 95826276 ps
T930 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2724136778 Jul 06 07:10:23 PM PDT 24 Jul 06 07:10:28 PM PDT 24 52496566 ps
T141 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2075883963 Jul 06 07:09:54 PM PDT 24 Jul 06 07:10:03 PM PDT 24 231831864 ps
T135 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.741510260 Jul 06 07:09:58 PM PDT 24 Jul 06 07:10:09 PM PDT 24 81997155 ps
T931 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.833838129 Jul 06 07:10:18 PM PDT 24 Jul 06 07:10:26 PM PDT 24 138352280 ps
T932 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1245158046 Jul 06 07:10:10 PM PDT 24 Jul 06 07:10:28 PM PDT 24 2207983615 ps
T206 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.277770662 Jul 06 07:09:58 PM PDT 24 Jul 06 07:10:08 PM PDT 24 35279684 ps
T933 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3233147033 Jul 06 07:10:29 PM PDT 24 Jul 06 07:10:32 PM PDT 24 43421932 ps
T934 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2936242106 Jul 06 07:10:16 PM PDT 24 Jul 06 07:10:24 PM PDT 24 81646658 ps
T935 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2708491614 Jul 06 07:09:59 PM PDT 24 Jul 06 07:10:19 PM PDT 24 1686617127 ps
T936 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.319475286 Jul 06 07:10:42 PM PDT 24 Jul 06 07:10:46 PM PDT 24 20015832 ps
T937 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3830484601 Jul 06 07:10:41 PM PDT 24 Jul 06 07:10:44 PM PDT 24 64235729 ps
T136 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3570067456 Jul 06 07:10:28 PM PDT 24 Jul 06 07:10:34 PM PDT 24 417981100 ps
T938 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2402121018 Jul 06 07:10:21 PM PDT 24 Jul 06 07:10:29 PM PDT 24 243832687 ps
T939 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3944144193 Jul 06 07:10:42 PM PDT 24 Jul 06 07:10:49 PM PDT 24 205374665 ps
T132 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2760575547 Jul 06 07:10:42 PM PDT 24 Jul 06 07:10:48 PM PDT 24 113916477 ps
T940 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.524675238 Jul 06 07:10:11 PM PDT 24 Jul 06 07:10:19 PM PDT 24 197356155 ps
T941 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.196481381 Jul 06 07:10:36 PM PDT 24 Jul 06 07:10:41 PM PDT 24 957732754 ps
T942 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.728922975 Jul 06 07:10:16 PM PDT 24 Jul 06 07:10:24 PM PDT 24 20550078 ps
T943 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1281348493 Jul 06 07:10:41 PM PDT 24 Jul 06 07:10:43 PM PDT 24 57648656 ps
T944 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1977980063 Jul 06 07:09:59 PM PDT 24 Jul 06 07:10:09 PM PDT 24 21737745 ps
T945 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2639951216 Jul 06 07:10:41 PM PDT 24 Jul 06 07:10:43 PM PDT 24 31326789 ps
T946 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2254538702 Jul 06 07:10:50 PM PDT 24 Jul 06 07:10:56 PM PDT 24 121008677 ps
T947 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2409905419 Jul 06 07:10:23 PM PDT 24 Jul 06 07:10:29 PM PDT 24 52433988 ps
T948 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2015231555 Jul 06 07:10:49 PM PDT 24 Jul 06 07:10:51 PM PDT 24 18292607 ps
T949 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.664687388 Jul 06 07:10:16 PM PDT 24 Jul 06 07:10:24 PM PDT 24 121696739 ps
T950 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2072997500 Jul 06 07:10:23 PM PDT 24 Jul 06 07:10:30 PM PDT 24 53560534 ps
T951 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1035383877 Jul 06 07:10:19 PM PDT 24 Jul 06 07:10:26 PM PDT 24 94474516 ps
T952 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.912465144 Jul 06 07:10:21 PM PDT 24 Jul 06 07:10:28 PM PDT 24 94227465 ps
T953 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3020727368 Jul 06 07:10:28 PM PDT 24 Jul 06 07:10:32 PM PDT 24 26812514 ps
T140 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1939426563 Jul 06 07:10:42 PM PDT 24 Jul 06 07:10:48 PM PDT 24 326273547 ps
T954 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3090389368 Jul 06 07:09:51 PM PDT 24 Jul 06 07:10:00 PM PDT 24 97495583 ps
T955 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.16772642 Jul 06 07:10:41 PM PDT 24 Jul 06 07:10:47 PM PDT 24 1486975402 ps
T956 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.313040801 Jul 06 07:10:41 PM PDT 24 Jul 06 07:10:44 PM PDT 24 86518941 ps
T957 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2992045667 Jul 06 07:10:21 PM PDT 24 Jul 06 07:10:31 PM PDT 24 2198830139 ps
T958 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3982304821 Jul 06 07:10:43 PM PDT 24 Jul 06 07:10:47 PM PDT 24 30248145 ps
T959 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.272288942 Jul 06 07:10:21 PM PDT 24 Jul 06 07:10:28 PM PDT 24 11901317 ps
T139 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.590186840 Jul 06 07:10:44 PM PDT 24 Jul 06 07:10:50 PM PDT 24 103849397 ps
T960 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.765079263 Jul 06 07:10:22 PM PDT 24 Jul 06 07:10:29 PM PDT 24 93906120 ps
T142 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.622592698 Jul 06 07:10:42 PM PDT 24 Jul 06 07:10:47 PM PDT 24 233963079 ps
T961 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2595091263 Jul 06 07:10:45 PM PDT 24 Jul 06 07:10:47 PM PDT 24 11705464 ps
T962 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1641859141 Jul 06 07:09:54 PM PDT 24 Jul 06 07:10:03 PM PDT 24 122941819 ps
T963 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3468671208 Jul 06 07:09:58 PM PDT 24 Jul 06 07:10:22 PM PDT 24 5004846434 ps
T964 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.834433364 Jul 06 07:10:08 PM PDT 24 Jul 06 07:10:15 PM PDT 24 35024996 ps
T965 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3715144969 Jul 06 07:10:17 PM PDT 24 Jul 06 07:10:24 PM PDT 24 33747712 ps
T966 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.709980854 Jul 06 07:10:30 PM PDT 24 Jul 06 07:10:33 PM PDT 24 195973733 ps
T967 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2543823064 Jul 06 07:10:09 PM PDT 24 Jul 06 07:10:16 PM PDT 24 17371473 ps
T968 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2561329248 Jul 06 07:09:52 PM PDT 24 Jul 06 07:10:00 PM PDT 24 193204835 ps
T209 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.272854847 Jul 06 07:10:41 PM PDT 24 Jul 06 07:10:43 PM PDT 24 53970641 ps
T969 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1851466784 Jul 06 07:10:50 PM PDT 24 Jul 06 07:10:55 PM PDT 24 47643029 ps
T145 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1562395147 Jul 06 07:10:18 PM PDT 24 Jul 06 07:10:26 PM PDT 24 40823232 ps
T970 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.736229963 Jul 06 07:10:41 PM PDT 24 Jul 06 07:10:44 PM PDT 24 181120951 ps
T971 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1758965780 Jul 06 07:10:06 PM PDT 24 Jul 06 07:10:14 PM PDT 24 61673780 ps
T972 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.829375747 Jul 06 07:10:28 PM PDT 24 Jul 06 07:10:32 PM PDT 24 18839509 ps
T973 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.4108142393 Jul 06 07:10:37 PM PDT 24 Jul 06 07:10:38 PM PDT 24 18029800 ps
T974 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.949279543 Jul 06 07:10:28 PM PDT 24 Jul 06 07:10:33 PM PDT 24 519656424 ps
T975 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3592211629 Jul 06 07:10:08 PM PDT 24 Jul 06 07:10:15 PM PDT 24 110649686 ps
T976 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1939556637 Jul 06 07:09:58 PM PDT 24 Jul 06 07:10:07 PM PDT 24 27581665 ps
T977 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3969946216 Jul 06 07:10:29 PM PDT 24 Jul 06 07:11:03 PM PDT 24 2948461931 ps
T207 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2945447304 Jul 06 07:10:08 PM PDT 24 Jul 06 07:10:15 PM PDT 24 150726583 ps
T978 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1694512797 Jul 06 07:10:20 PM PDT 24 Jul 06 07:10:27 PM PDT 24 13783780 ps
T979 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.4171807285 Jul 06 07:10:22 PM PDT 24 Jul 06 07:10:51 PM PDT 24 968752265 ps
T980 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2866406519 Jul 06 07:10:42 PM PDT 24 Jul 06 07:10:46 PM PDT 24 14246189 ps
T981 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.4222275139 Jul 06 07:10:16 PM PDT 24 Jul 06 07:10:24 PM PDT 24 224924884 ps
T982 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.2769763424 Jul 06 07:10:28 PM PDT 24 Jul 06 07:10:32 PM PDT 24 202131244 ps
T983 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2417362340 Jul 06 07:09:52 PM PDT 24 Jul 06 07:10:02 PM PDT 24 208191524 ps
T984 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3132808888 Jul 06 07:10:22 PM PDT 24 Jul 06 07:10:29 PM PDT 24 213756252 ps
T985 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1966463053 Jul 06 07:09:53 PM PDT 24 Jul 06 07:10:02 PM PDT 24 28553565 ps
T986 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1328149349 Jul 06 07:10:07 PM PDT 24 Jul 06 07:10:17 PM PDT 24 240364843 ps
T987 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3763157003 Jul 06 07:10:41 PM PDT 24 Jul 06 07:10:43 PM PDT 24 51775972 ps
T988 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1116227346 Jul 06 07:10:28 PM PDT 24 Jul 06 07:10:34 PM PDT 24 103933454 ps
T989 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3075655920 Jul 06 07:10:15 PM PDT 24 Jul 06 07:10:45 PM PDT 24 1305043091 ps
T990 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.542706420 Jul 06 07:09:52 PM PDT 24 Jul 06 07:10:00 PM PDT 24 199240578 ps
T991 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.93915000 Jul 06 07:10:41 PM PDT 24 Jul 06 07:10:45 PM PDT 24 213151105 ps

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.1754763115
Short name T12
Test name
Test status
Simulation time 74907141 ps
CPU time 7.43 seconds
Started Jul 06 07:18:38 PM PDT 24
Finished Jul 06 07:18:47 PM PDT 24
Peak memory 247032 kb
Host smart-438e363a-78fb-4b8d-a008-e8912d0dba2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754763115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.1754763115
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.2316738306
Short name T22
Test name
Test status
Simulation time 128831493487 ps
CPU time 226.1 seconds
Started Jul 06 07:19:26 PM PDT 24
Finished Jul 06 07:23:13 PM PDT 24
Peak memory 316000 kb
Host smart-c176d8fc-2722-4d46-9237-be0b324a3124
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316738306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.2316738306
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.906661748
Short name T17
Test name
Test status
Simulation time 316200379 ps
CPU time 9.69 seconds
Started Jul 06 07:17:53 PM PDT 24
Finished Jul 06 07:18:04 PM PDT 24
Peak memory 225576 kb
Host smart-4c43e516-4c9d-4156-92f3-e480f00963a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906661748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.906661748
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.1578527064
Short name T16
Test name
Test status
Simulation time 775837974 ps
CPU time 11.32 seconds
Started Jul 06 07:18:19 PM PDT 24
Finished Jul 06 07:18:32 PM PDT 24
Peak memory 225588 kb
Host smart-7c48cd25-05b9-42a3-93e9-84138712a913
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578527064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.1578527064
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.3761974698
Short name T46
Test name
Test status
Simulation time 41772704081 ps
CPU time 473.79 seconds
Started Jul 06 07:19:06 PM PDT 24
Finished Jul 06 07:27:01 PM PDT 24
Peak memory 421600 kb
Host smart-5369dc74-81b9-4a35-88dc-822a0e71a6d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3761974698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.3761974698
Directory /workspace/34.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.3816063161
Short name T53
Test name
Test status
Simulation time 1402408394 ps
CPU time 7.27 seconds
Started Jul 06 07:19:28 PM PDT 24
Finished Jul 06 07:19:36 PM PDT 24
Peak memory 224220 kb
Host smart-0f9fa442-bcd9-4842-9019-6f34f7a10553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816063161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.3816063161
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1842452443
Short name T32
Test name
Test status
Simulation time 34140028 ps
CPU time 0.77 seconds
Started Jul 06 07:19:42 PM PDT 24
Finished Jul 06 07:19:44 PM PDT 24
Peak memory 208232 kb
Host smart-2d787af7-2072-4d98-a081-fd64577eef81
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842452443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.1842452443
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.2256999425
Short name T56
Test name
Test status
Simulation time 221008029 ps
CPU time 39.91 seconds
Started Jul 06 07:15:34 PM PDT 24
Finished Jul 06 07:16:54 PM PDT 24
Peak memory 269264 kb
Host smart-07ce463b-e091-461d-916a-297a9b909fad
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256999425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.2256999425
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.4173057726
Short name T6
Test name
Test status
Simulation time 691781863 ps
CPU time 5.41 seconds
Started Jul 06 07:18:01 PM PDT 24
Finished Jul 06 07:18:08 PM PDT 24
Peak memory 217192 kb
Host smart-36e9c1df-def2-4dd2-b0b1-d51eab3be390
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173057726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.4173057726
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2728866096
Short name T119
Test name
Test status
Simulation time 437439184 ps
CPU time 2.7 seconds
Started Jul 06 07:10:42 PM PDT 24
Finished Jul 06 07:10:47 PM PDT 24
Peak memory 217600 kb
Host smart-472ee694-ec93-4fbf-a430-79de87e1f661
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728866096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.2728866096
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2037845743
Short name T198
Test name
Test status
Simulation time 57548408 ps
CPU time 1.02 seconds
Started Jul 06 07:10:07 PM PDT 24
Finished Jul 06 07:10:15 PM PDT 24
Peak memory 209300 kb
Host smart-f6d6835b-edac-443a-b245-2479234f8785
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037845743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.2037845743
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.103925262
Short name T48
Test name
Test status
Simulation time 353539378861 ps
CPU time 976.14 seconds
Started Jul 06 07:18:04 PM PDT 24
Finished Jul 06 07:34:22 PM PDT 24
Peak memory 285500 kb
Host smart-7cb2e11a-2bd7-4e2f-ae93-bc9ed3ca4a16
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=103925262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.103925262
Directory /workspace/17.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.52145410
Short name T42
Test name
Test status
Simulation time 1427541518 ps
CPU time 10.35 seconds
Started Jul 06 07:17:55 PM PDT 24
Finished Jul 06 07:18:06 PM PDT 24
Peak memory 217720 kb
Host smart-f656b2a9-9ca1-4594-8935-0e96d78d520b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52145410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.52145410
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.1840406131
Short name T178
Test name
Test status
Simulation time 909360081 ps
CPU time 14.63 seconds
Started Jul 06 07:18:26 PM PDT 24
Finished Jul 06 07:18:42 PM PDT 24
Peak memory 217876 kb
Host smart-80963c23-a10c-4f77-a4a2-fcbd586e8148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840406131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.1840406131
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3796904009
Short name T128
Test name
Test status
Simulation time 617517778 ps
CPU time 2.9 seconds
Started Jul 06 07:10:19 PM PDT 24
Finished Jul 06 07:10:28 PM PDT 24
Peak memory 221952 kb
Host smart-6a5fc54d-fadf-4fb5-b954-e01eb01f1761
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796904009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.3796904009
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.1211832528
Short name T2
Test name
Test status
Simulation time 29495643 ps
CPU time 0.79 seconds
Started Jul 06 07:19:12 PM PDT 24
Finished Jul 06 07:19:14 PM PDT 24
Peak memory 208556 kb
Host smart-82599874-993c-4bb4-9f92-f448ce55c83e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211832528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.1211832528
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.2798992796
Short name T272
Test name
Test status
Simulation time 7954467517 ps
CPU time 71.73 seconds
Started Jul 06 07:19:35 PM PDT 24
Finished Jul 06 07:20:50 PM PDT 24
Peak memory 271380 kb
Host smart-c1378836-f934-48b8-be05-537e42886018
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798992796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.2798992796
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3447807506
Short name T147
Test name
Test status
Simulation time 1240893156 ps
CPU time 14.27 seconds
Started Jul 06 07:09:56 PM PDT 24
Finished Jul 06 07:10:18 PM PDT 24
Peak memory 217124 kb
Host smart-4cdee5fd-8a4a-4e6e-9981-2bd78000ee01
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447807506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.3447807506
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2765137692
Short name T123
Test name
Test status
Simulation time 397542126 ps
CPU time 4.1 seconds
Started Jul 06 07:10:36 PM PDT 24
Finished Jul 06 07:10:41 PM PDT 24
Peak memory 217516 kb
Host smart-9feb4f12-eaf9-429a-a9d6-37b27c33b9a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765137692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.2765137692
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.2802407184
Short name T3
Test name
Test status
Simulation time 436497297 ps
CPU time 12.06 seconds
Started Jul 06 07:19:32 PM PDT 24
Finished Jul 06 07:19:45 PM PDT 24
Peak memory 225520 kb
Host smart-a8ff0ee4-3232-4225-8468-3ccd9f957c12
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802407184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.2802407184
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2245466464
Short name T131
Test name
Test status
Simulation time 108525846 ps
CPU time 3.9 seconds
Started Jul 06 07:09:59 PM PDT 24
Finished Jul 06 07:10:12 PM PDT 24
Peak memory 217588 kb
Host smart-d54895f0-3db9-41be-92fa-3d886db288cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245466464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.2245466464
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.3504212194
Short name T110
Test name
Test status
Simulation time 1311230447 ps
CPU time 38.78 seconds
Started Jul 06 07:17:03 PM PDT 24
Finished Jul 06 07:17:43 PM PDT 24
Peak memory 266812 kb
Host smart-6fc18444-b0f3-4fd7-b289-7422d5c1bc19
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504212194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.3504212194
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.1965011363
Short name T96
Test name
Test status
Simulation time 145659862 ps
CPU time 6.54 seconds
Started Jul 06 07:17:16 PM PDT 24
Finished Jul 06 07:17:27 PM PDT 24
Peak memory 244108 kb
Host smart-a3205aa5-2986-42b5-aad2-0d1c3e48c8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965011363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.1965011363
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.709025047
Short name T342
Test name
Test status
Simulation time 14199740 ps
CPU time 0.88 seconds
Started Jul 06 07:17:23 PM PDT 24
Finished Jul 06 07:17:25 PM PDT 24
Peak memory 208560 kb
Host smart-18fab3fe-6f9a-4452-852c-9d23e71f5d70
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709025047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ct
rl_volatile_unlock_smoke.709025047
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.472748308
Short name T134
Test name
Test status
Simulation time 529327837 ps
CPU time 3.5 seconds
Started Jul 06 07:09:54 PM PDT 24
Finished Jul 06 07:10:04 PM PDT 24
Peak memory 217516 kb
Host smart-63a347f0-1131-4254-b1f4-31ad2c960aed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472748308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.472748308
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1921540501
Short name T127
Test name
Test status
Simulation time 740719130 ps
CPU time 2.88 seconds
Started Jul 06 07:10:44 PM PDT 24
Finished Jul 06 07:10:49 PM PDT 24
Peak memory 217536 kb
Host smart-6010a22c-18d6-4dc9-b1fe-cef6e3cfeaae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921540501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.1921540501
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.3506549222
Short name T20
Test name
Test status
Simulation time 912894938 ps
CPU time 12.31 seconds
Started Jul 06 07:17:13 PM PDT 24
Finished Jul 06 07:17:31 PM PDT 24
Peak memory 217136 kb
Host smart-295b5e6d-7046-4153-8383-b9043072719b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506549222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.3506549222
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1875907269
Short name T137
Test name
Test status
Simulation time 65668425 ps
CPU time 2.03 seconds
Started Jul 06 07:09:57 PM PDT 24
Finished Jul 06 07:10:08 PM PDT 24
Peak memory 217436 kb
Host smart-3c6a61bc-ae35-456f-9568-e3af0e753925
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875907269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.1875907269
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1414729475
Short name T129
Test name
Test status
Simulation time 418960468 ps
CPU time 2.78 seconds
Started Jul 06 07:10:42 PM PDT 24
Finished Jul 06 07:10:47 PM PDT 24
Peak memory 217516 kb
Host smart-6f6f8f31-8466-4d43-93e1-82d7b6ace687
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414729475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.1414729475
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.748984327
Short name T65
Test name
Test status
Simulation time 2480364984 ps
CPU time 13.22 seconds
Started Jul 06 07:15:13 PM PDT 24
Finished Jul 06 07:16:21 PM PDT 24
Peak memory 225588 kb
Host smart-8bc7ee2d-15b0-430c-aa1d-8ff86cf8b5cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748984327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.748984327
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.2943861997
Short name T219
Test name
Test status
Simulation time 16703221 ps
CPU time 0.86 seconds
Started Jul 06 07:15:50 PM PDT 24
Finished Jul 06 07:16:19 PM PDT 24
Peak memory 208512 kb
Host smart-16fdc406-967a-4634-9d1b-dbcb8a8b972a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943861997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.2943861997
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.1971957989
Short name T222
Test name
Test status
Simulation time 12462015 ps
CPU time 0.98 seconds
Started Jul 06 07:16:54 PM PDT 24
Finished Jul 06 07:16:57 PM PDT 24
Peak memory 208448 kb
Host smart-c7de4470-e1ca-470f-8b51-1281934ebac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971957989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.1971957989
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.2463273186
Short name T221
Test name
Test status
Simulation time 34882613 ps
CPU time 0.81 seconds
Started Jul 06 07:17:00 PM PDT 24
Finished Jul 06 07:17:02 PM PDT 24
Peak memory 208552 kb
Host smart-cf39cff2-99cd-4cc1-9899-ba89791bb0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463273186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.2463273186
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2620209028
Short name T122
Test name
Test status
Simulation time 20912611 ps
CPU time 1.32 seconds
Started Jul 06 07:09:56 PM PDT 24
Finished Jul 06 07:10:06 PM PDT 24
Peak memory 209992 kb
Host smart-7358035c-b505-49f3-8fd2-6876d07e2c2c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620209028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.2620209028
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.4116638263
Short name T143
Test name
Test status
Simulation time 374138052 ps
CPU time 2.72 seconds
Started Jul 06 07:10:49 PM PDT 24
Finished Jul 06 07:10:53 PM PDT 24
Peak memory 217536 kb
Host smart-900fd642-b6ad-4095-81d5-9f1d80d69722
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116638263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.4116638263
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1386126420
Short name T133
Test name
Test status
Simulation time 129158601 ps
CPU time 4.08 seconds
Started Jul 06 07:10:42 PM PDT 24
Finished Jul 06 07:10:48 PM PDT 24
Peak memory 217524 kb
Host smart-224f2f34-5b7e-4b18-b6a3-ed4030d7ca93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386126420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.1386126420
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.590186840
Short name T139
Test name
Test status
Simulation time 103849397 ps
CPU time 4.26 seconds
Started Jul 06 07:10:44 PM PDT 24
Finished Jul 06 07:10:50 PM PDT 24
Peak memory 217516 kb
Host smart-ceddcdbc-88ed-4b13-84f8-5ab034336242
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590186840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg_
err.590186840
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3092837200
Short name T117
Test name
Test status
Simulation time 479549637 ps
CPU time 3.01 seconds
Started Jul 06 07:10:22 PM PDT 24
Finished Jul 06 07:10:30 PM PDT 24
Peak memory 222256 kb
Host smart-5b530d26-1d4e-4cfe-9b2e-5a30d0d2b4e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092837200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.3092837200
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.2778591801
Short name T13
Test name
Test status
Simulation time 417053265 ps
CPU time 11.57 seconds
Started Jul 06 07:19:54 PM PDT 24
Finished Jul 06 07:20:08 PM PDT 24
Peak memory 225532 kb
Host smart-5d617c83-d757-4715-9180-5ade0463cf0b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778591801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.2778591801
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.4199780607
Short name T9
Test name
Test status
Simulation time 1124441342 ps
CPU time 4.95 seconds
Started Jul 06 07:15:12 PM PDT 24
Finished Jul 06 07:16:13 PM PDT 24
Peak memory 217744 kb
Host smart-0495b07e-c815-4d11-9669-8941b8e8941c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199780607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.4199780607
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.542706420
Short name T990
Test name
Test status
Simulation time 199240578 ps
CPU time 1.33 seconds
Started Jul 06 07:09:52 PM PDT 24
Finished Jul 06 07:10:00 PM PDT 24
Peak memory 217476 kb
Host smart-90135bdf-4e30-4f47-9875-6c7998dc5566
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542706420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasing
.542706420
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1938419626
Short name T908
Test name
Test status
Simulation time 69662287 ps
CPU time 1.2 seconds
Started Jul 06 07:09:54 PM PDT 24
Finished Jul 06 07:10:03 PM PDT 24
Peak memory 209216 kb
Host smart-fd349b45-10a5-4a03-bad8-ae3b1434d3f1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938419626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.1938419626
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2103701514
Short name T199
Test name
Test status
Simulation time 14264773 ps
CPU time 1.08 seconds
Started Jul 06 07:09:55 PM PDT 24
Finished Jul 06 07:10:04 PM PDT 24
Peak memory 209976 kb
Host smart-c1e2a6e5-7993-4245-9ebd-6e68691a240c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103701514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.2103701514
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1966463053
Short name T985
Test name
Test status
Simulation time 28553565 ps
CPU time 2.13 seconds
Started Jul 06 07:09:53 PM PDT 24
Finished Jul 06 07:10:02 PM PDT 24
Peak memory 218524 kb
Host smart-cc41a26a-f60f-473a-8097-6a21a857b8d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966463053 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.1966463053
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.625042995
Short name T200
Test name
Test status
Simulation time 11826028 ps
CPU time 0.99 seconds
Started Jul 06 07:09:56 PM PDT 24
Finished Jul 06 07:10:05 PM PDT 24
Peak memory 208836 kb
Host smart-fddbdc58-015a-4b7c-940c-83de1422ed7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625042995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.625042995
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.4216685268
Short name T884
Test name
Test status
Simulation time 82193757 ps
CPU time 1.4 seconds
Started Jul 06 07:09:52 PM PDT 24
Finished Jul 06 07:10:00 PM PDT 24
Peak memory 209256 kb
Host smart-ac2c977d-868a-4d39-83e3-32f1ca2e6da4
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216685268 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.4216685268
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3544640482
Short name T901
Test name
Test status
Simulation time 1121916400 ps
CPU time 3.26 seconds
Started Jul 06 07:09:54 PM PDT 24
Finished Jul 06 07:10:04 PM PDT 24
Peak memory 216960 kb
Host smart-f3d8d721-7346-41ac-895c-4916498736b9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544640482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.3544640482
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.4126895733
Short name T925
Test name
Test status
Simulation time 1246881589 ps
CPU time 27.39 seconds
Started Jul 06 07:09:53 PM PDT 24
Finished Jul 06 07:10:27 PM PDT 24
Peak memory 209284 kb
Host smart-1173509d-7402-412a-9447-2e6fc5b9b950
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126895733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.4126895733
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3090389368
Short name T954
Test name
Test status
Simulation time 97495583 ps
CPU time 3.02 seconds
Started Jul 06 07:09:51 PM PDT 24
Finished Jul 06 07:10:00 PM PDT 24
Peak memory 210928 kb
Host smart-a36364c2-9ea4-4109-87cb-27054c975da6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090389368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.3090389368
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2417362340
Short name T983
Test name
Test status
Simulation time 208191524 ps
CPU time 2.84 seconds
Started Jul 06 07:09:52 PM PDT 24
Finished Jul 06 07:10:02 PM PDT 24
Peak memory 217564 kb
Host smart-7af77ab0-564a-4006-9459-76f7efe0db8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241736
2340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2417362340
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1402558195
Short name T874
Test name
Test status
Simulation time 37001804 ps
CPU time 1.09 seconds
Started Jul 06 07:09:53 PM PDT 24
Finished Jul 06 07:10:01 PM PDT 24
Peak memory 209216 kb
Host smart-e764c62f-0397-415d-872a-f759abc47b8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402558195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.1402558195
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1693912323
Short name T918
Test name
Test status
Simulation time 19763729 ps
CPU time 1.27 seconds
Started Jul 06 07:09:52 PM PDT 24
Finished Jul 06 07:10:00 PM PDT 24
Peak memory 211488 kb
Host smart-b5aebb65-d413-4f00-a5f1-3463f5d7fa45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693912323 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.1693912323
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2076630928
Short name T885
Test name
Test status
Simulation time 35548648 ps
CPU time 1.44 seconds
Started Jul 06 07:09:54 PM PDT 24
Finished Jul 06 07:10:03 PM PDT 24
Peak memory 211252 kb
Host smart-09621293-8fb8-4a96-a2d4-760d9ab2c5b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076630928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.2076630928
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2075883963
Short name T141
Test name
Test status
Simulation time 231831864 ps
CPU time 2.38 seconds
Started Jul 06 07:09:54 PM PDT 24
Finished Jul 06 07:10:03 PM PDT 24
Peak memory 221744 kb
Host smart-48ea504e-878d-4aa5-8f01-45a8f256f90d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075883963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.2075883963
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.277770662
Short name T206
Test name
Test status
Simulation time 35279684 ps
CPU time 1.37 seconds
Started Jul 06 07:09:58 PM PDT 24
Finished Jul 06 07:10:08 PM PDT 24
Peak memory 217420 kb
Host smart-090f8589-dc14-4f95-9a84-ae020de04ccf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277770662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasing
.277770662
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2351866299
Short name T887
Test name
Test status
Simulation time 92061857 ps
CPU time 1.99 seconds
Started Jul 06 07:10:01 PM PDT 24
Finished Jul 06 07:10:11 PM PDT 24
Peak memory 217296 kb
Host smart-b63221a6-7704-4401-8d01-39144daef297
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351866299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.2351866299
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1939556637
Short name T976
Test name
Test status
Simulation time 27581665 ps
CPU time 1.21 seconds
Started Jul 06 07:09:58 PM PDT 24
Finished Jul 06 07:10:07 PM PDT 24
Peak memory 217548 kb
Host smart-4713a042-1711-4960-b8ac-e1103e4bcdaf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939556637 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.1939556637
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2716191419
Short name T203
Test name
Test status
Simulation time 30436036 ps
CPU time 0.87 seconds
Started Jul 06 07:09:59 PM PDT 24
Finished Jul 06 07:10:09 PM PDT 24
Peak memory 209204 kb
Host smart-8fec13a5-b998-48bd-abec-e2c064c3c417
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716191419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.2716191419
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.770035398
Short name T904
Test name
Test status
Simulation time 36613325 ps
CPU time 1.58 seconds
Started Jul 06 07:09:52 PM PDT 24
Finished Jul 06 07:10:00 PM PDT 24
Peak memory 209156 kb
Host smart-ac524fce-b011-47e4-a8d0-3dc8483638ce
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770035398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.lc_ctrl_jtag_alert_test.770035398
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.623270211
Short name T921
Test name
Test status
Simulation time 834149357 ps
CPU time 20.62 seconds
Started Jul 06 07:09:54 PM PDT 24
Finished Jul 06 07:10:21 PM PDT 24
Peak memory 209208 kb
Host smart-78593250-1a31-4a04-9b91-f465ec8fc18c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623270211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.623270211
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3715792207
Short name T916
Test name
Test status
Simulation time 334931804 ps
CPU time 2.12 seconds
Started Jul 06 07:09:52 PM PDT 24
Finished Jul 06 07:10:00 PM PDT 24
Peak memory 210880 kb
Host smart-06d8bd80-55b9-463d-b8fc-464401763bc7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715792207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.3715792207
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2157731082
Short name T902
Test name
Test status
Simulation time 975990194 ps
CPU time 3.42 seconds
Started Jul 06 07:09:53 PM PDT 24
Finished Jul 06 07:10:03 PM PDT 24
Peak memory 218016 kb
Host smart-84e624bb-b2d3-4a7b-96c5-c5bfbbe767f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215773
1082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2157731082
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1641859141
Short name T962
Test name
Test status
Simulation time 122941819 ps
CPU time 1.36 seconds
Started Jul 06 07:09:54 PM PDT 24
Finished Jul 06 07:10:03 PM PDT 24
Peak memory 208852 kb
Host smart-847814e1-0ad0-4a84-ad76-b234215460fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641859141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.1641859141
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2561329248
Short name T968
Test name
Test status
Simulation time 193204835 ps
CPU time 1.48 seconds
Started Jul 06 07:09:52 PM PDT 24
Finished Jul 06 07:10:00 PM PDT 24
Peak memory 217532 kb
Host smart-51cdc14e-e874-472a-ac96-c484b0cbabc5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561329248 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.2561329248
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3089997680
Short name T928
Test name
Test status
Simulation time 59614598 ps
CPU time 1.33 seconds
Started Jul 06 07:09:59 PM PDT 24
Finished Jul 06 07:10:09 PM PDT 24
Peak memory 209300 kb
Host smart-8c76e6ab-0050-46df-9ba9-06488ba326b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089997680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.3089997680
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.741510260
Short name T135
Test name
Test status
Simulation time 81997155 ps
CPU time 3 seconds
Started Jul 06 07:09:58 PM PDT 24
Finished Jul 06 07:10:09 PM PDT 24
Peak memory 217588 kb
Host smart-6d763cc1-5a70-4004-b93e-b90454b14a1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741510260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.741510260
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.22475837
Short name T181
Test name
Test status
Simulation time 50300793 ps
CPU time 1.24 seconds
Started Jul 06 07:10:36 PM PDT 24
Finished Jul 06 07:10:38 PM PDT 24
Peak memory 219228 kb
Host smart-ee243ae5-f17b-4428-99ac-e28eec290bc5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22475837 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.22475837
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2595091263
Short name T961
Test name
Test status
Simulation time 11705464 ps
CPU time 1 seconds
Started Jul 06 07:10:45 PM PDT 24
Finished Jul 06 07:10:47 PM PDT 24
Peak memory 209172 kb
Host smart-07f257d4-02ad-4eaa-baf1-89d60bfeea99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595091263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.2595091263
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3432041527
Short name T919
Test name
Test status
Simulation time 19677792 ps
CPU time 1.43 seconds
Started Jul 06 07:10:36 PM PDT 24
Finished Jul 06 07:10:38 PM PDT 24
Peak memory 211396 kb
Host smart-6c68a05b-a47b-443d-a997-d94016c13584
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432041527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.3432041527
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2496020069
Short name T927
Test name
Test status
Simulation time 44936263 ps
CPU time 3.16 seconds
Started Jul 06 07:10:28 PM PDT 24
Finished Jul 06 07:10:34 PM PDT 24
Peak memory 217820 kb
Host smart-9402c400-b714-45dd-aa33-14e9359cec03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496020069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.2496020069
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1542049537
Short name T875
Test name
Test status
Simulation time 56685381 ps
CPU time 1.19 seconds
Started Jul 06 07:10:36 PM PDT 24
Finished Jul 06 07:10:38 PM PDT 24
Peak memory 218620 kb
Host smart-2dcd040a-9b21-4ff0-bbfb-befce510e39f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542049537 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.1542049537
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.4108142393
Short name T973
Test name
Test status
Simulation time 18029800 ps
CPU time 1.13 seconds
Started Jul 06 07:10:37 PM PDT 24
Finished Jul 06 07:10:38 PM PDT 24
Peak memory 209144 kb
Host smart-f098b936-7d30-44ca-8187-5ca566972a71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108142393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.4108142393
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1939586662
Short name T911
Test name
Test status
Simulation time 43563652 ps
CPU time 1.01 seconds
Started Jul 06 07:10:36 PM PDT 24
Finished Jul 06 07:10:37 PM PDT 24
Peak memory 209404 kb
Host smart-c5820552-97b3-46f4-b6a1-862b56738e21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939586662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.1939586662
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.196481381
Short name T941
Test name
Test status
Simulation time 957732754 ps
CPU time 3.46 seconds
Started Jul 06 07:10:36 PM PDT 24
Finished Jul 06 07:10:41 PM PDT 24
Peak memory 217968 kb
Host smart-81ef7de5-18b8-4c89-a744-87d6132ed978
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196481381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.196481381
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.698939733
Short name T872
Test name
Test status
Simulation time 98749126 ps
CPU time 1.2 seconds
Started Jul 06 07:10:44 PM PDT 24
Finished Jul 06 07:10:47 PM PDT 24
Peak memory 217660 kb
Host smart-9942e599-e77d-48ed-82dc-2292e437f565
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698939733 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.698939733
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.223233882
Short name T905
Test name
Test status
Simulation time 15598341 ps
CPU time 0.87 seconds
Started Jul 06 07:10:41 PM PDT 24
Finished Jul 06 07:10:43 PM PDT 24
Peak memory 209220 kb
Host smart-b9517386-ec36-41d3-9486-2f1b269999fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223233882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.223233882
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.12009798
Short name T210
Test name
Test status
Simulation time 77056857 ps
CPU time 1.05 seconds
Started Jul 06 07:10:43 PM PDT 24
Finished Jul 06 07:10:47 PM PDT 24
Peak memory 209388 kb
Host smart-c7033618-3454-41a3-807a-d982de9f360e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12009798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_
same_csr_outstanding.12009798
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.16772642
Short name T955
Test name
Test status
Simulation time 1486975402 ps
CPU time 3.12 seconds
Started Jul 06 07:10:41 PM PDT 24
Finished Jul 06 07:10:47 PM PDT 24
Peak memory 217520 kb
Host smart-ee6bd880-2620-4bb9-a53e-c2dc1db240ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16772642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.16772642
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.622592698
Short name T142
Test name
Test status
Simulation time 233963079 ps
CPU time 2.58 seconds
Started Jul 06 07:10:42 PM PDT 24
Finished Jul 06 07:10:47 PM PDT 24
Peak memory 217472 kb
Host smart-84245b77-fb33-48fd-ad1c-dc2501777de4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622592698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg_
err.622592698
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1708685869
Short name T895
Test name
Test status
Simulation time 31211672 ps
CPU time 1.2 seconds
Started Jul 06 07:10:42 PM PDT 24
Finished Jul 06 07:10:45 PM PDT 24
Peak memory 217712 kb
Host smart-ae39dd76-0a27-4bc5-9100-7f1cdeca6b39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708685869 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.1708685869
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2011253633
Short name T204
Test name
Test status
Simulation time 16526356 ps
CPU time 1.13 seconds
Started Jul 06 07:10:42 PM PDT 24
Finished Jul 06 07:10:45 PM PDT 24
Peak memory 209048 kb
Host smart-efd73f12-3e3c-44d1-9399-9ffffa49b150
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011253633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.2011253633
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.1538765867
Short name T120
Test name
Test status
Simulation time 19674110 ps
CPU time 1.17 seconds
Started Jul 06 07:10:40 PM PDT 24
Finished Jul 06 07:10:42 PM PDT 24
Peak memory 209404 kb
Host smart-13c36130-4c6e-49b9-9f7f-5a11a54c7126
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538765867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.1538765867
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.93915000
Short name T991
Test name
Test status
Simulation time 213151105 ps
CPU time 2.98 seconds
Started Jul 06 07:10:41 PM PDT 24
Finished Jul 06 07:10:45 PM PDT 24
Peak memory 217516 kb
Host smart-7f90028d-035e-4dd7-89b3-349fdab18029
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93915000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.93915000
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3510140082
Short name T130
Test name
Test status
Simulation time 451472132 ps
CPU time 3.09 seconds
Started Jul 06 07:10:43 PM PDT 24
Finished Jul 06 07:10:49 PM PDT 24
Peak memory 222244 kb
Host smart-096ac204-24b6-472f-b095-a06f91918fb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510140082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.3510140082
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2015231555
Short name T948
Test name
Test status
Simulation time 18292607 ps
CPU time 1.1 seconds
Started Jul 06 07:10:49 PM PDT 24
Finished Jul 06 07:10:51 PM PDT 24
Peak memory 217600 kb
Host smart-19536022-4d91-4c28-80cf-5e1cfa8b6b87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015231555 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.2015231555
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1092482087
Short name T169
Test name
Test status
Simulation time 69875372 ps
CPU time 1.03 seconds
Started Jul 06 07:10:41 PM PDT 24
Finished Jul 06 07:10:43 PM PDT 24
Peak memory 209300 kb
Host smart-f7ceab88-7c4e-40f8-a0ac-93a4862a722c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092482087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.1092482087
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3763157003
Short name T987
Test name
Test status
Simulation time 51775972 ps
CPU time 1.14 seconds
Started Jul 06 07:10:41 PM PDT 24
Finished Jul 06 07:10:43 PM PDT 24
Peak memory 217524 kb
Host smart-a3247eff-a66a-4935-b077-9364641670b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763157003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.3763157003
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3944144193
Short name T939
Test name
Test status
Simulation time 205374665 ps
CPU time 4.64 seconds
Started Jul 06 07:10:42 PM PDT 24
Finished Jul 06 07:10:49 PM PDT 24
Peak memory 217500 kb
Host smart-9f6a3bae-1e0c-4446-934c-289268218bfe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944144193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.3944144193
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3809642976
Short name T912
Test name
Test status
Simulation time 78240464 ps
CPU time 1.41 seconds
Started Jul 06 07:10:41 PM PDT 24
Finished Jul 06 07:10:43 PM PDT 24
Peak memory 218980 kb
Host smart-7586389e-2afe-4906-881a-17d4477d529d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809642976 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.3809642976
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.313040801
Short name T956
Test name
Test status
Simulation time 86518941 ps
CPU time 0.96 seconds
Started Jul 06 07:10:41 PM PDT 24
Finished Jul 06 07:10:44 PM PDT 24
Peak memory 209240 kb
Host smart-c9048ee3-6f02-4de5-aeab-80cb0e8db028
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313040801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.313040801
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2639951216
Short name T945
Test name
Test status
Simulation time 31326789 ps
CPU time 0.99 seconds
Started Jul 06 07:10:41 PM PDT 24
Finished Jul 06 07:10:43 PM PDT 24
Peak memory 217524 kb
Host smart-2eacbaa6-90e7-447b-af24-a956b0f39b3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639951216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.2639951216
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2254538702
Short name T946
Test name
Test status
Simulation time 121008677 ps
CPU time 4.57 seconds
Started Jul 06 07:10:50 PM PDT 24
Finished Jul 06 07:10:56 PM PDT 24
Peak memory 217420 kb
Host smart-d524ba15-50d2-4f3d-8ea8-8d274ac18255
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254538702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.2254538702
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1939426563
Short name T140
Test name
Test status
Simulation time 326273547 ps
CPU time 3.44 seconds
Started Jul 06 07:10:42 PM PDT 24
Finished Jul 06 07:10:48 PM PDT 24
Peak memory 217620 kb
Host smart-28559803-7ed5-428a-9ff8-d6e714f21d58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939426563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.1939426563
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1492260232
Short name T880
Test name
Test status
Simulation time 84178049 ps
CPU time 1.51 seconds
Started Jul 06 07:10:42 PM PDT 24
Finished Jul 06 07:10:46 PM PDT 24
Peak memory 217544 kb
Host smart-c34e3776-6147-427d-9689-becf9a681e88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492260232 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.1492260232
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1281348493
Short name T943
Test name
Test status
Simulation time 57648656 ps
CPU time 1.11 seconds
Started Jul 06 07:10:41 PM PDT 24
Finished Jul 06 07:10:43 PM PDT 24
Peak memory 209088 kb
Host smart-943bca3a-f5ae-4d83-80c7-f9ca4407e9c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281348493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.1281348493
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3830484601
Short name T937
Test name
Test status
Simulation time 64235729 ps
CPU time 1.08 seconds
Started Jul 06 07:10:41 PM PDT 24
Finished Jul 06 07:10:44 PM PDT 24
Peak memory 209304 kb
Host smart-dc59e47a-de49-4e2a-824f-26729f6db506
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830484601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.3830484601
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3982304821
Short name T958
Test name
Test status
Simulation time 30248145 ps
CPU time 2.35 seconds
Started Jul 06 07:10:43 PM PDT 24
Finished Jul 06 07:10:47 PM PDT 24
Peak memory 224308 kb
Host smart-d8070feb-15f8-4030-b5a2-77825f8b7b00
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982304821 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.3982304821
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.4211534452
Short name T202
Test name
Test status
Simulation time 24640145 ps
CPU time 0.9 seconds
Started Jul 06 07:10:42 PM PDT 24
Finished Jul 06 07:10:45 PM PDT 24
Peak memory 209304 kb
Host smart-a2cc3051-3e7f-4965-8f09-fc061fa6dd81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211534452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.4211534452
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2080455993
Short name T216
Test name
Test status
Simulation time 384616343 ps
CPU time 1.02 seconds
Started Jul 06 07:10:49 PM PDT 24
Finished Jul 06 07:10:51 PM PDT 24
Peak memory 209328 kb
Host smart-70f0b5c7-e1ee-4009-9d0c-866cafd03bb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080455993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.2080455993
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.948893259
Short name T124
Test name
Test status
Simulation time 544691652 ps
CPU time 3.5 seconds
Started Jul 06 07:10:43 PM PDT 24
Finished Jul 06 07:10:48 PM PDT 24
Peak memory 217500 kb
Host smart-f57d7f29-932a-4c6d-9a2c-246bca3fd100
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948893259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.948893259
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2760575547
Short name T132
Test name
Test status
Simulation time 113916477 ps
CPU time 4.12 seconds
Started Jul 06 07:10:42 PM PDT 24
Finished Jul 06 07:10:48 PM PDT 24
Peak memory 217496 kb
Host smart-f66525e4-4c3d-4610-92bf-ed1832aeae58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760575547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.2760575547
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1125981405
Short name T118
Test name
Test status
Simulation time 61586177 ps
CPU time 1.01 seconds
Started Jul 06 07:10:42 PM PDT 24
Finished Jul 06 07:10:45 PM PDT 24
Peak memory 218684 kb
Host smart-b4ef3591-39de-460a-ad5d-1975a0827789
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125981405 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.1125981405
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2866406519
Short name T980
Test name
Test status
Simulation time 14246189 ps
CPU time 1.04 seconds
Started Jul 06 07:10:42 PM PDT 24
Finished Jul 06 07:10:46 PM PDT 24
Peak memory 209272 kb
Host smart-77fa3955-c767-479d-9700-0553d152e236
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866406519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.2866406519
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.319475286
Short name T936
Test name
Test status
Simulation time 20015832 ps
CPU time 1.42 seconds
Started Jul 06 07:10:42 PM PDT 24
Finished Jul 06 07:10:46 PM PDT 24
Peak memory 209308 kb
Host smart-b31f7dfe-7133-45e9-9e08-b3fdd5bab60a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319475286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_same_csr_outstanding.319475286
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1851466784
Short name T969
Test name
Test status
Simulation time 47643029 ps
CPU time 3.2 seconds
Started Jul 06 07:10:50 PM PDT 24
Finished Jul 06 07:10:55 PM PDT 24
Peak memory 217868 kb
Host smart-fd4710e9-c68e-418f-9420-fd53884d4a9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851466784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.1851466784
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2058487507
Short name T126
Test name
Test status
Simulation time 14791758 ps
CPU time 1.08 seconds
Started Jul 06 07:10:41 PM PDT 24
Finished Jul 06 07:10:44 PM PDT 24
Peak memory 219064 kb
Host smart-be8d06b7-c444-4b1b-89af-fd9f4d97e59b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058487507 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.2058487507
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.272854847
Short name T209
Test name
Test status
Simulation time 53970641 ps
CPU time 1.03 seconds
Started Jul 06 07:10:41 PM PDT 24
Finished Jul 06 07:10:43 PM PDT 24
Peak memory 217456 kb
Host smart-1c427780-20df-49de-8161-acff1c062c5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272854847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.272854847
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1540586840
Short name T213
Test name
Test status
Simulation time 18567972 ps
CPU time 1.03 seconds
Started Jul 06 07:10:42 PM PDT 24
Finished Jul 06 07:10:46 PM PDT 24
Peak memory 209316 kb
Host smart-c777e2d9-3295-4dac-b365-d3490404967a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540586840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.1540586840
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.736229963
Short name T970
Test name
Test status
Simulation time 181120951 ps
CPU time 2.49 seconds
Started Jul 06 07:10:41 PM PDT 24
Finished Jul 06 07:10:44 PM PDT 24
Peak memory 217620 kb
Host smart-32b736ea-7456-4ea2-9895-3215cb05fdc6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736229963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.736229963
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2945447304
Short name T207
Test name
Test status
Simulation time 150726583 ps
CPU time 1.29 seconds
Started Jul 06 07:10:08 PM PDT 24
Finished Jul 06 07:10:15 PM PDT 24
Peak memory 217500 kb
Host smart-136f019c-c9dc-4495-82b1-ad6aa3980572
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945447304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.2945447304
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1106417709
Short name T886
Test name
Test status
Simulation time 189347161 ps
CPU time 2.25 seconds
Started Jul 06 07:10:13 PM PDT 24
Finished Jul 06 07:10:22 PM PDT 24
Peak memory 209384 kb
Host smart-b5cae231-171c-46f2-baef-4ac6d7eab4e7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106417709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.1106417709
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1830526190
Short name T913
Test name
Test status
Simulation time 34921064 ps
CPU time 0.99 seconds
Started Jul 06 07:10:09 PM PDT 24
Finished Jul 06 07:10:17 PM PDT 24
Peak memory 218052 kb
Host smart-72776105-052f-4365-9662-71a0c84623ac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830526190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.1830526190
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2543823064
Short name T967
Test name
Test status
Simulation time 17371473 ps
CPU time 1.09 seconds
Started Jul 06 07:10:09 PM PDT 24
Finished Jul 06 07:10:16 PM PDT 24
Peak memory 217560 kb
Host smart-d79b7400-c2f2-4cdb-89bc-39fb0c332a39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543823064 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.2543823064
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.731496976
Short name T917
Test name
Test status
Simulation time 126428308 ps
CPU time 1.6 seconds
Started Jul 06 07:09:59 PM PDT 24
Finished Jul 06 07:10:09 PM PDT 24
Peak memory 208696 kb
Host smart-decb14f7-ca89-4c2a-a188-8be1643761e0
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731496976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.lc_ctrl_jtag_alert_test.731496976
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2708491614
Short name T935
Test name
Test status
Simulation time 1686617127 ps
CPU time 11.54 seconds
Started Jul 06 07:09:59 PM PDT 24
Finished Jul 06 07:10:19 PM PDT 24
Peak memory 209256 kb
Host smart-b3779b1f-78e2-484f-8d69-a41da8f472ee
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708491614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.2708491614
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3468671208
Short name T963
Test name
Test status
Simulation time 5004846434 ps
CPU time 15.86 seconds
Started Jul 06 07:09:58 PM PDT 24
Finished Jul 06 07:10:22 PM PDT 24
Peak memory 209324 kb
Host smart-c74f3e60-09e3-455b-a319-ca22852ab4ed
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468671208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.3468671208
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2619262861
Short name T150
Test name
Test status
Simulation time 191898343 ps
CPU time 1.63 seconds
Started Jul 06 07:09:57 PM PDT 24
Finished Jul 06 07:10:08 PM PDT 24
Peak memory 217452 kb
Host smart-8ad86089-2e08-4fdb-8455-1860c1569247
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619262861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.2619262861
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2174228674
Short name T876
Test name
Test status
Simulation time 333569914 ps
CPU time 1.38 seconds
Started Jul 06 07:09:57 PM PDT 24
Finished Jul 06 07:10:07 PM PDT 24
Peak memory 217588 kb
Host smart-22c8f536-303b-432e-8ae7-ec2b627276cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217422
8674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2174228674
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.607743146
Short name T914
Test name
Test status
Simulation time 199746876 ps
CPU time 1.69 seconds
Started Jul 06 07:09:58 PM PDT 24
Finished Jul 06 07:10:08 PM PDT 24
Peak memory 209188 kb
Host smart-0ef130ff-72e5-4a40-bc36-5f807fac4e2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607743146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.607743146
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2283460539
Short name T214
Test name
Test status
Simulation time 354599107 ps
CPU time 1.42 seconds
Started Jul 06 07:09:59 PM PDT 24
Finished Jul 06 07:10:08 PM PDT 24
Peak memory 217528 kb
Host smart-6e40dd0b-feac-4963-a1f5-68029c63cee4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283460539 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.2283460539
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3592211629
Short name T975
Test name
Test status
Simulation time 110649686 ps
CPU time 1.15 seconds
Started Jul 06 07:10:08 PM PDT 24
Finished Jul 06 07:10:15 PM PDT 24
Peak memory 209380 kb
Host smart-7066dcec-fd97-4f76-bf8f-02f4b373979c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592211629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.3592211629
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1977980063
Short name T944
Test name
Test status
Simulation time 21737745 ps
CPU time 1.64 seconds
Started Jul 06 07:09:59 PM PDT 24
Finished Jul 06 07:10:09 PM PDT 24
Peak memory 217568 kb
Host smart-5e9decdd-4c56-4142-bb0c-dc2ac33d1eaf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977980063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.1977980063
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.4186847192
Short name T205
Test name
Test status
Simulation time 14618213 ps
CPU time 1.12 seconds
Started Jul 06 07:10:13 PM PDT 24
Finished Jul 06 07:10:21 PM PDT 24
Peak memory 209252 kb
Host smart-94026f8b-bcd7-44f8-b247-059097b6009a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186847192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.4186847192
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1758965780
Short name T971
Test name
Test status
Simulation time 61673780 ps
CPU time 1.13 seconds
Started Jul 06 07:10:06 PM PDT 24
Finished Jul 06 07:10:14 PM PDT 24
Peak memory 209268 kb
Host smart-3b28eff3-f034-43c6-a4bc-b73bb4d5e42c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758965780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.1758965780
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1395768065
Short name T869
Test name
Test status
Simulation time 38364150 ps
CPU time 1.02 seconds
Started Jul 06 07:10:12 PM PDT 24
Finished Jul 06 07:10:19 PM PDT 24
Peak memory 209916 kb
Host smart-c19b9ca9-b8ca-4ffc-934c-1d405ff1b021
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395768065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.1395768065
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.834433364
Short name T964
Test name
Test status
Simulation time 35024996 ps
CPU time 1.04 seconds
Started Jul 06 07:10:08 PM PDT 24
Finished Jul 06 07:10:15 PM PDT 24
Peak memory 217588 kb
Host smart-c1870e78-7800-41cb-ae54-80aeeb2eb7ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834433364 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.834433364
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1141879046
Short name T201
Test name
Test status
Simulation time 56290347 ps
CPU time 1.12 seconds
Started Jul 06 07:10:08 PM PDT 24
Finished Jul 06 07:10:15 PM PDT 24
Peak memory 209248 kb
Host smart-59f7b066-59c7-43a0-bbbf-28172c5e8674
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141879046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.1141879046
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3364045181
Short name T152
Test name
Test status
Simulation time 88900502 ps
CPU time 1.14 seconds
Started Jul 06 07:10:07 PM PDT 24
Finished Jul 06 07:10:15 PM PDT 24
Peak memory 209136 kb
Host smart-a0340dc0-3e53-4582-8d96-78e045f39fd3
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364045181 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.3364045181
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3955790096
Short name T893
Test name
Test status
Simulation time 927065641 ps
CPU time 6.92 seconds
Started Jul 06 07:10:08 PM PDT 24
Finished Jul 06 07:10:21 PM PDT 24
Peak memory 209208 kb
Host smart-ce9fe3d4-d12a-448f-880f-bab4de22bad5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955790096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.3955790096
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1245158046
Short name T932
Test name
Test status
Simulation time 2207983615 ps
CPU time 11.76 seconds
Started Jul 06 07:10:10 PM PDT 24
Finished Jul 06 07:10:28 PM PDT 24
Peak memory 208840 kb
Host smart-9454ced0-f4c4-4286-83b8-41c992aaea7e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245158046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.1245158046
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.418715225
Short name T929
Test name
Test status
Simulation time 95826276 ps
CPU time 1.77 seconds
Started Jul 06 07:10:08 PM PDT 24
Finished Jul 06 07:10:16 PM PDT 24
Peak memory 210896 kb
Host smart-ea1dc347-9164-4441-966a-94359b47fb65
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418715225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.418715225
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2310903455
Short name T146
Test name
Test status
Simulation time 458992508 ps
CPU time 2.23 seconds
Started Jul 06 07:10:08 PM PDT 24
Finished Jul 06 07:10:16 PM PDT 24
Peak memory 217568 kb
Host smart-04467c4a-f6bb-410b-8c15-c66b5cab6b73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231090
3455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2310903455
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.524675238
Short name T940
Test name
Test status
Simulation time 197356155 ps
CPU time 1.4 seconds
Started Jul 06 07:10:11 PM PDT 24
Finished Jul 06 07:10:19 PM PDT 24
Peak memory 209220 kb
Host smart-3e74e4dd-2884-489c-9950-4eec74692538
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524675238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.524675238
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2166173129
Short name T920
Test name
Test status
Simulation time 37141818 ps
CPU time 1.33 seconds
Started Jul 06 07:10:08 PM PDT 24
Finished Jul 06 07:10:16 PM PDT 24
Peak memory 209252 kb
Host smart-ef6bd210-7c10-4d96-a4ae-0a9f516835e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166173129 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.2166173129
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1662998037
Short name T896
Test name
Test status
Simulation time 25416635 ps
CPU time 1.33 seconds
Started Jul 06 07:10:08 PM PDT 24
Finished Jul 06 07:10:15 PM PDT 24
Peak memory 209264 kb
Host smart-11af9db7-7681-407f-9a98-9332f71d7c00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662998037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.1662998037
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1328149349
Short name T986
Test name
Test status
Simulation time 240364843 ps
CPU time 4.02 seconds
Started Jul 06 07:10:07 PM PDT 24
Finished Jul 06 07:10:17 PM PDT 24
Peak memory 217524 kb
Host smart-74271f4d-16d1-4c41-8430-ec1e75a862a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328149349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.1328149349
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.107539605
Short name T138
Test name
Test status
Simulation time 58796199 ps
CPU time 1.89 seconds
Started Jul 06 07:10:11 PM PDT 24
Finished Jul 06 07:10:20 PM PDT 24
Peak memory 217504 kb
Host smart-e527762d-f50c-4543-b239-d9a948cd6c09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107539605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_e
rr.107539605
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1694512797
Short name T978
Test name
Test status
Simulation time 13783780 ps
CPU time 1.2 seconds
Started Jul 06 07:10:20 PM PDT 24
Finished Jul 06 07:10:27 PM PDT 24
Peak memory 209236 kb
Host smart-f6428100-e1be-4854-b22b-973a2298bae6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694512797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.1694512797
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.664687388
Short name T949
Test name
Test status
Simulation time 121696739 ps
CPU time 1.6 seconds
Started Jul 06 07:10:16 PM PDT 24
Finished Jul 06 07:10:24 PM PDT 24
Peak memory 217448 kb
Host smart-388e2086-815a-42c5-98e2-1a324eea92ee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664687388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bash
.664687388
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.4052282580
Short name T197
Test name
Test status
Simulation time 20719733 ps
CPU time 1.39 seconds
Started Jul 06 07:10:16 PM PDT 24
Finished Jul 06 07:10:24 PM PDT 24
Peak memory 218228 kb
Host smart-6ebd0de0-91e6-41e0-84ab-9e0f2f19bab5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052282580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.4052282580
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3157511879
Short name T900
Test name
Test status
Simulation time 64635338 ps
CPU time 1.42 seconds
Started Jul 06 07:12:44 PM PDT 24
Finished Jul 06 07:12:46 PM PDT 24
Peak memory 217896 kb
Host smart-2bf9b49b-6d9f-4f96-b366-1146463076c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157511879 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.3157511879
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3715144969
Short name T965
Test name
Test status
Simulation time 33747712 ps
CPU time 0.81 seconds
Started Jul 06 07:10:17 PM PDT 24
Finished Jul 06 07:10:24 PM PDT 24
Peak memory 209100 kb
Host smart-62c5460b-ae6b-4dcc-92a9-3d4f9b2fc338
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715144969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.3715144969
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.234040398
Short name T924
Test name
Test status
Simulation time 45432045 ps
CPU time 1.12 seconds
Started Jul 06 07:10:09 PM PDT 24
Finished Jul 06 07:10:16 PM PDT 24
Peak memory 208900 kb
Host smart-bafb67ea-99de-4000-84bd-972aaa3b977e
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234040398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.lc_ctrl_jtag_alert_test.234040398
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.4052021134
Short name T879
Test name
Test status
Simulation time 588686521 ps
CPU time 13.69 seconds
Started Jul 06 07:10:08 PM PDT 24
Finished Jul 06 07:10:27 PM PDT 24
Peak memory 217120 kb
Host smart-03cfae80-df86-41e6-a199-dd396a05ffce
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052021134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.4052021134
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1022011993
Short name T892
Test name
Test status
Simulation time 8394905732 ps
CPU time 13.7 seconds
Started Jul 06 07:10:09 PM PDT 24
Finished Jul 06 07:10:28 PM PDT 24
Peak memory 209076 kb
Host smart-7d70fef7-9bc7-46ac-8a50-f3b0077ef39b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022011993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.1022011993
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3443342595
Short name T883
Test name
Test status
Simulation time 79269974 ps
CPU time 1.76 seconds
Started Jul 06 07:10:09 PM PDT 24
Finished Jul 06 07:10:16 PM PDT 24
Peak memory 210940 kb
Host smart-660d1312-0f6e-424d-b317-e763f48dd258
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443342595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.3443342595
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2065253168
Short name T899
Test name
Test status
Simulation time 528717084 ps
CPU time 4.47 seconds
Started Jul 06 07:10:13 PM PDT 24
Finished Jul 06 07:10:24 PM PDT 24
Peak memory 217676 kb
Host smart-88de6c44-894d-48a7-83eb-9f33bb49f488
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206525
3168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2065253168
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.3004022254
Short name T889
Test name
Test status
Simulation time 93783247 ps
CPU time 1.57 seconds
Started Jul 06 07:10:09 PM PDT 24
Finished Jul 06 07:10:16 PM PDT 24
Peak memory 217284 kb
Host smart-55930c0b-49df-4c8b-963d-2292dbfb685b
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004022254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.3004022254
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.61984184
Short name T121
Test name
Test status
Simulation time 51944408 ps
CPU time 1.04 seconds
Started Jul 06 07:10:13 PM PDT 24
Finished Jul 06 07:10:20 PM PDT 24
Peak memory 209400 kb
Host smart-0179b526-77f1-40fb-88ec-3d18c9f550eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61984184 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.61984184
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1630689139
Short name T882
Test name
Test status
Simulation time 57413838 ps
CPU time 1.33 seconds
Started Jul 06 07:10:16 PM PDT 24
Finished Jul 06 07:10:24 PM PDT 24
Peak memory 209412 kb
Host smart-99df0b52-be6f-4029-8af8-77d191dfb373
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630689139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.1630689139
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.833838129
Short name T931
Test name
Test status
Simulation time 138352280 ps
CPU time 2.48 seconds
Started Jul 06 07:10:18 PM PDT 24
Finished Jul 06 07:10:26 PM PDT 24
Peak memory 217600 kb
Host smart-2190d2bb-a310-497d-95fc-8b33b4403923
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833838129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.833838129
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.4076705369
Short name T922
Test name
Test status
Simulation time 73041292 ps
CPU time 1.09 seconds
Started Jul 06 07:10:18 PM PDT 24
Finished Jul 06 07:10:25 PM PDT 24
Peak memory 219192 kb
Host smart-4438854c-59e8-4b48-a140-8c73177366d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076705369 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.4076705369
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1549647790
Short name T212
Test name
Test status
Simulation time 15226433 ps
CPU time 1.09 seconds
Started Jul 06 07:10:17 PM PDT 24
Finished Jul 06 07:10:24 PM PDT 24
Peak memory 209280 kb
Host smart-4abb1aad-0904-49d1-a105-ce4c14843de2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549647790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.1549647790
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.58810196
Short name T894
Test name
Test status
Simulation time 22280687 ps
CPU time 1.01 seconds
Started Jul 06 07:10:16 PM PDT 24
Finished Jul 06 07:10:24 PM PDT 24
Peak memory 209104 kb
Host smart-f2a7e0ea-a571-4953-a4f7-1b227af4527d
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58810196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_alert_test.58810196
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3075655920
Short name T989
Test name
Test status
Simulation time 1305043091 ps
CPU time 23.22 seconds
Started Jul 06 07:10:15 PM PDT 24
Finished Jul 06 07:10:45 PM PDT 24
Peak memory 209256 kb
Host smart-630cb46a-c01d-429a-931a-f3d0103efd35
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075655920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.3075655920
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2167444867
Short name T888
Test name
Test status
Simulation time 2201094718 ps
CPU time 9.32 seconds
Started Jul 06 07:10:16 PM PDT 24
Finished Jul 06 07:10:31 PM PDT 24
Peak memory 209268 kb
Host smart-0126f00a-28bf-4b34-931e-5ef49ed2424f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167444867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.2167444867
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2513668960
Short name T907
Test name
Test status
Simulation time 161662568 ps
CPU time 4.61 seconds
Started Jul 06 07:10:15 PM PDT 24
Finished Jul 06 07:10:26 PM PDT 24
Peak memory 210968 kb
Host smart-37aab55f-1368-4e27-b1dd-47dba65212f8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513668960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.2513668960
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1035383877
Short name T951
Test name
Test status
Simulation time 94474516 ps
CPU time 1.53 seconds
Started Jul 06 07:10:19 PM PDT 24
Finished Jul 06 07:10:26 PM PDT 24
Peak memory 220856 kb
Host smart-26aaa4e0-55a6-4de7-b167-d2985b57c0d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103538
3877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1035383877
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.4222275139
Short name T981
Test name
Test status
Simulation time 224924884 ps
CPU time 1.42 seconds
Started Jul 06 07:10:16 PM PDT 24
Finished Jul 06 07:10:24 PM PDT 24
Peak memory 209264 kb
Host smart-e2d71c70-e6e0-4fd1-8680-a8436c40a5a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222275139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.4222275139
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.487168619
Short name T215
Test name
Test status
Simulation time 158233750 ps
CPU time 1.45 seconds
Started Jul 06 07:10:18 PM PDT 24
Finished Jul 06 07:10:26 PM PDT 24
Peak memory 217480 kb
Host smart-e9a4d7e7-dd5c-40d6-8380-6c1df8289f8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487168619 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.487168619
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3488486125
Short name T211
Test name
Test status
Simulation time 19277482 ps
CPU time 1.2 seconds
Started Jul 06 07:10:20 PM PDT 24
Finished Jul 06 07:10:27 PM PDT 24
Peak memory 217476 kb
Host smart-41b2a3ad-8f80-4a0c-86d6-66dc661de730
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488486125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.3488486125
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.4117932985
Short name T113
Test name
Test status
Simulation time 24210621 ps
CPU time 1.9 seconds
Started Jul 06 07:10:16 PM PDT 24
Finished Jul 06 07:10:25 PM PDT 24
Peak memory 217420 kb
Host smart-aa880352-ff21-47c1-910b-e2416fae1121
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117932985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.4117932985
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.407817826
Short name T114
Test name
Test status
Simulation time 243015394 ps
CPU time 2.5 seconds
Started Jul 06 07:10:17 PM PDT 24
Finished Jul 06 07:10:25 PM PDT 24
Peak memory 217348 kb
Host smart-c4053d05-6177-443f-a594-b7fa243c8e59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407817826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_e
rr.407817826
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.4257542588
Short name T125
Test name
Test status
Simulation time 120566824 ps
CPU time 1.46 seconds
Started Jul 06 07:10:21 PM PDT 24
Finished Jul 06 07:10:28 PM PDT 24
Peak memory 217644 kb
Host smart-25c20bff-67b0-4a42-81d8-002c52bf69b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257542588 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.4257542588
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.4069934372
Short name T208
Test name
Test status
Simulation time 39852715 ps
CPU time 0.84 seconds
Started Jul 06 07:10:23 PM PDT 24
Finished Jul 06 07:10:28 PM PDT 24
Peak memory 209176 kb
Host smart-8141199d-f552-46d3-9d98-ce12a8442d2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069934372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.4069934372
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2605135445
Short name T890
Test name
Test status
Simulation time 165087222 ps
CPU time 1.09 seconds
Started Jul 06 07:10:17 PM PDT 24
Finished Jul 06 07:10:24 PM PDT 24
Peak memory 209168 kb
Host smart-b0a96c86-d1e0-424b-9857-e88db0c78742
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605135445 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.2605135445
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.654768331
Short name T871
Test name
Test status
Simulation time 226985404 ps
CPU time 2.98 seconds
Started Jul 06 07:10:18 PM PDT 24
Finished Jul 06 07:10:27 PM PDT 24
Peak memory 209204 kb
Host smart-2989a603-4c77-4eed-8235-3e985f5fea2d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654768331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.654768331
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3187379296
Short name T877
Test name
Test status
Simulation time 356042467 ps
CPU time 9.09 seconds
Started Jul 06 07:10:17 PM PDT 24
Finished Jul 06 07:10:32 PM PDT 24
Peak memory 209252 kb
Host smart-daf19b95-0ee3-456d-97da-ca61fc9de7ca
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187379296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.3187379296
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2936242106
Short name T934
Test name
Test status
Simulation time 81646658 ps
CPU time 1.93 seconds
Started Jul 06 07:10:16 PM PDT 24
Finished Jul 06 07:10:24 PM PDT 24
Peak memory 210920 kb
Host smart-895446b0-6a9c-447c-9fc5-b13c741fd22b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936242106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.2936242106
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.420919968
Short name T873
Test name
Test status
Simulation time 497046800 ps
CPU time 2.23 seconds
Started Jul 06 07:10:19 PM PDT 24
Finished Jul 06 07:10:27 PM PDT 24
Peak memory 217568 kb
Host smart-7c4a8952-2a7c-47c7-98a4-cedbc5fbdef8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420919
968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.420919968
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.2487154047
Short name T148
Test name
Test status
Simulation time 973978914 ps
CPU time 3.06 seconds
Started Jul 06 07:10:20 PM PDT 24
Finished Jul 06 07:10:29 PM PDT 24
Peak memory 209096 kb
Host smart-68b2c1b3-c316-4bc1-aa6f-b601877f55b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487154047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.2487154047
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.728922975
Short name T942
Test name
Test status
Simulation time 20550078 ps
CPU time 1.23 seconds
Started Jul 06 07:10:16 PM PDT 24
Finished Jul 06 07:10:24 PM PDT 24
Peak memory 217396 kb
Host smart-7689f169-dad3-4781-aa3c-5279977ff416
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728922975 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.728922975
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.765079263
Short name T960
Test name
Test status
Simulation time 93906120 ps
CPU time 1.97 seconds
Started Jul 06 07:10:22 PM PDT 24
Finished Jul 06 07:10:29 PM PDT 24
Peak memory 211416 kb
Host smart-dfe5c155-5a14-4029-b80b-97adbc20d483
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765079263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
same_csr_outstanding.765079263
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1766410953
Short name T115
Test name
Test status
Simulation time 192562457 ps
CPU time 1.95 seconds
Started Jul 06 07:10:20 PM PDT 24
Finished Jul 06 07:10:28 PM PDT 24
Peak memory 217432 kb
Host smart-742fbabb-34a3-424b-99d4-5336baa19ebd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766410953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.1766410953
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1562395147
Short name T145
Test name
Test status
Simulation time 40823232 ps
CPU time 1.88 seconds
Started Jul 06 07:10:18 PM PDT 24
Finished Jul 06 07:10:26 PM PDT 24
Peak memory 221680 kb
Host smart-6e8c35d5-6464-4514-a6af-065aed15ae9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562395147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.1562395147
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3829288392
Short name T192
Test name
Test status
Simulation time 43670057 ps
CPU time 1.71 seconds
Started Jul 06 07:10:23 PM PDT 24
Finished Jul 06 07:10:29 PM PDT 24
Peak memory 217708 kb
Host smart-c51ffaa2-b965-4c9d-a18c-9a9d29aec365
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829288392 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.3829288392
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.272288942
Short name T959
Test name
Test status
Simulation time 11901317 ps
CPU time 0.93 seconds
Started Jul 06 07:10:21 PM PDT 24
Finished Jul 06 07:10:28 PM PDT 24
Peak memory 209300 kb
Host smart-0c36030c-8902-4df5-8977-78fbebcf4159
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272288942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.272288942
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2072997500
Short name T950
Test name
Test status
Simulation time 53560534 ps
CPU time 2.12 seconds
Started Jul 06 07:10:23 PM PDT 24
Finished Jul 06 07:10:30 PM PDT 24
Peak memory 209140 kb
Host smart-c3fc6d19-ec8b-442e-ac7f-046a7524a30e
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072997500 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.2072997500
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.317602044
Short name T891
Test name
Test status
Simulation time 1611029924 ps
CPU time 6.68 seconds
Started Jul 06 07:10:22 PM PDT 24
Finished Jul 06 07:10:34 PM PDT 24
Peak memory 209200 kb
Host smart-23467a73-1c8a-4b1a-b8be-ebe5696eeaf0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317602044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.317602044
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.4171807285
Short name T979
Test name
Test status
Simulation time 968752265 ps
CPU time 23.39 seconds
Started Jul 06 07:10:22 PM PDT 24
Finished Jul 06 07:10:51 PM PDT 24
Peak memory 209152 kb
Host smart-ebeab5fc-53c4-4723-9b7b-d3dde73d3495
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171807285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.4171807285
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3132808888
Short name T984
Test name
Test status
Simulation time 213756252 ps
CPU time 1.97 seconds
Started Jul 06 07:10:22 PM PDT 24
Finished Jul 06 07:10:29 PM PDT 24
Peak memory 210376 kb
Host smart-a9618fc9-cdb7-4e0d-8690-e5135fcc4742
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132808888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.3132808888
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.912465144
Short name T952
Test name
Test status
Simulation time 94227465 ps
CPU time 1.36 seconds
Started Jul 06 07:10:21 PM PDT 24
Finished Jul 06 07:10:28 PM PDT 24
Peak memory 217644 kb
Host smart-ac7ef962-122e-4c31-b2ab-a109b869a2c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912465
144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.912465144
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2402121018
Short name T938
Test name
Test status
Simulation time 243832687 ps
CPU time 1.82 seconds
Started Jul 06 07:10:21 PM PDT 24
Finished Jul 06 07:10:29 PM PDT 24
Peak memory 209164 kb
Host smart-041fa831-62c2-47d9-9142-03c6fa327eca
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402121018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.2402121018
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1887759632
Short name T915
Test name
Test status
Simulation time 23767087 ps
CPU time 0.99 seconds
Started Jul 06 07:10:28 PM PDT 24
Finished Jul 06 07:10:31 PM PDT 24
Peak memory 209328 kb
Host smart-09d02426-1956-4089-9f1f-4b1db4fdb098
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887759632 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.1887759632
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2409905419
Short name T947
Test name
Test status
Simulation time 52433988 ps
CPU time 1.38 seconds
Started Jul 06 07:10:23 PM PDT 24
Finished Jul 06 07:10:29 PM PDT 24
Peak memory 209328 kb
Host smart-4c0c5c64-bcc3-41b2-88d3-583f277a8c96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409905419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.2409905419
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1116227346
Short name T988
Test name
Test status
Simulation time 103933454 ps
CPU time 3.6 seconds
Started Jul 06 07:10:28 PM PDT 24
Finished Jul 06 07:10:34 PM PDT 24
Peak memory 218548 kb
Host smart-a668ed28-ebaf-40c1-8777-d7296671f1f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116227346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.1116227346
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2870969727
Short name T116
Test name
Test status
Simulation time 286778668 ps
CPU time 2.72 seconds
Started Jul 06 07:10:23 PM PDT 24
Finished Jul 06 07:10:30 PM PDT 24
Peak memory 217588 kb
Host smart-dc5d1277-c36e-4f74-bdaa-91a44e3e52e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870969727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.2870969727
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3020727368
Short name T953
Test name
Test status
Simulation time 26812514 ps
CPU time 1.17 seconds
Started Jul 06 07:10:28 PM PDT 24
Finished Jul 06 07:10:32 PM PDT 24
Peak memory 220288 kb
Host smart-4310a926-3bf1-4ab4-9d4d-b9d62f12acaa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020727368 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.3020727368
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3259516848
Short name T878
Test name
Test status
Simulation time 14971557 ps
CPU time 0.96 seconds
Started Jul 06 07:10:33 PM PDT 24
Finished Jul 06 07:10:35 PM PDT 24
Peak memory 209328 kb
Host smart-93fd9d66-67b6-4f54-9bcc-30e5eea26a4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259516848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.3259516848
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2725468613
Short name T151
Test name
Test status
Simulation time 35552131 ps
CPU time 1.54 seconds
Started Jul 06 07:10:24 PM PDT 24
Finished Jul 06 07:10:29 PM PDT 24
Peak memory 209276 kb
Host smart-af46830e-fcf4-4a72-9166-94c92b78dfc5
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725468613 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.2725468613
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2509668546
Short name T910
Test name
Test status
Simulation time 5089869538 ps
CPU time 10.44 seconds
Started Jul 06 07:10:23 PM PDT 24
Finished Jul 06 07:10:38 PM PDT 24
Peak memory 209508 kb
Host smart-c5961027-7f7d-42bf-95d0-aa2a228bc842
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509668546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.2509668546
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3789196057
Short name T898
Test name
Test status
Simulation time 2204881704 ps
CPU time 18.76 seconds
Started Jul 06 07:10:28 PM PDT 24
Finished Jul 06 07:10:49 PM PDT 24
Peak memory 209276 kb
Host smart-7ca5b356-8892-482b-a942-f1be8b71aae3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789196057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.3789196057
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1174520409
Short name T903
Test name
Test status
Simulation time 676076020 ps
CPU time 2.1 seconds
Started Jul 06 07:10:23 PM PDT 24
Finished Jul 06 07:10:29 PM PDT 24
Peak memory 217472 kb
Host smart-183f8d5b-4bf6-4724-966d-ea7bf0c3f0ee
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174520409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.1174520409
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.586678857
Short name T897
Test name
Test status
Simulation time 278405644 ps
CPU time 1.35 seconds
Started Jul 06 07:10:28 PM PDT 24
Finished Jul 06 07:10:32 PM PDT 24
Peak memory 219744 kb
Host smart-22808edf-071f-4d2d-b50f-51f2bb52c92d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586678
857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.586678857
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2992045667
Short name T957
Test name
Test status
Simulation time 2198830139 ps
CPU time 3.73 seconds
Started Jul 06 07:10:21 PM PDT 24
Finished Jul 06 07:10:31 PM PDT 24
Peak memory 209224 kb
Host smart-a0ae943e-1a74-4205-901d-16bf91413b8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992045667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.2992045667
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2724136778
Short name T930
Test name
Test status
Simulation time 52496566 ps
CPU time 1.14 seconds
Started Jul 06 07:10:23 PM PDT 24
Finished Jul 06 07:10:28 PM PDT 24
Peak memory 209312 kb
Host smart-86be7940-e472-47a3-82d4-4d1e697aa17e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724136778 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.2724136778
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.2430033542
Short name T926
Test name
Test status
Simulation time 38745254 ps
CPU time 1.32 seconds
Started Jul 06 07:10:29 PM PDT 24
Finished Jul 06 07:10:32 PM PDT 24
Peak memory 209292 kb
Host smart-1298c8dd-9dba-4a53-b0d9-cd902fd03719
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430033542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.2430033542
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.2769763424
Short name T982
Test name
Test status
Simulation time 202131244 ps
CPU time 1.79 seconds
Started Jul 06 07:10:28 PM PDT 24
Finished Jul 06 07:10:32 PM PDT 24
Peak memory 217604 kb
Host smart-e7030ecc-5c47-4e99-b0e9-0694a02cb7be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769763424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.2769763424
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.830074705
Short name T906
Test name
Test status
Simulation time 42868853 ps
CPU time 1.52 seconds
Started Jul 06 07:10:30 PM PDT 24
Finished Jul 06 07:10:33 PM PDT 24
Peak memory 217668 kb
Host smart-2d71134a-649c-4eb6-965e-38dc970d61a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830074705 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.830074705
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1260633860
Short name T870
Test name
Test status
Simulation time 18023069 ps
CPU time 1.11 seconds
Started Jul 06 07:10:27 PM PDT 24
Finished Jul 06 07:10:31 PM PDT 24
Peak memory 209272 kb
Host smart-1d1f70ea-5df9-4a73-9ce4-64ca95f880d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260633860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.1260633860
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.709980854
Short name T966
Test name
Test status
Simulation time 195973733 ps
CPU time 1.51 seconds
Started Jul 06 07:10:30 PM PDT 24
Finished Jul 06 07:10:33 PM PDT 24
Peak memory 208736 kb
Host smart-9af9ced1-8df0-4847-a94a-5e09b93b702d
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709980854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.lc_ctrl_jtag_alert_test.709980854
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3969946216
Short name T977
Test name
Test status
Simulation time 2948461931 ps
CPU time 32.24 seconds
Started Jul 06 07:10:29 PM PDT 24
Finished Jul 06 07:11:03 PM PDT 24
Peak memory 209260 kb
Host smart-553b27be-f985-4aa9-800f-30453815b406
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969946216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.3969946216
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3633027721
Short name T881
Test name
Test status
Simulation time 4979943680 ps
CPU time 4.94 seconds
Started Jul 06 07:10:29 PM PDT 24
Finished Jul 06 07:10:36 PM PDT 24
Peak memory 209276 kb
Host smart-d22d6e6d-ff16-4d64-9e90-81771dad652e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633027721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.3633027721
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.729619449
Short name T909
Test name
Test status
Simulation time 93751627 ps
CPU time 2.01 seconds
Started Jul 06 07:10:33 PM PDT 24
Finished Jul 06 07:10:36 PM PDT 24
Peak memory 210784 kb
Host smart-4d0209bb-c35e-4db3-9f5e-ece58ff60147
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729619449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.729619449
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.949279543
Short name T974
Test name
Test status
Simulation time 519656424 ps
CPU time 2.28 seconds
Started Jul 06 07:10:28 PM PDT 24
Finished Jul 06 07:10:33 PM PDT 24
Peak memory 218728 kb
Host smart-04bc0c9e-481c-4d0f-8e8c-b768fb42355b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949279
543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.949279543
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1245442721
Short name T923
Test name
Test status
Simulation time 239457786 ps
CPU time 1.26 seconds
Started Jul 06 07:10:29 PM PDT 24
Finished Jul 06 07:10:32 PM PDT 24
Peak memory 209464 kb
Host smart-61b92b3f-42e2-4c8e-9cbe-522ebf8a3fe9
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245442721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.1245442721
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.829375747
Short name T972
Test name
Test status
Simulation time 18839509 ps
CPU time 1.4 seconds
Started Jul 06 07:10:28 PM PDT 24
Finished Jul 06 07:10:32 PM PDT 24
Peak memory 209416 kb
Host smart-eac6f6e2-1eb3-4345-845d-f5342473bac9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829375747 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.829375747
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3233147033
Short name T933
Test name
Test status
Simulation time 43421932 ps
CPU time 0.94 seconds
Started Jul 06 07:10:29 PM PDT 24
Finished Jul 06 07:10:32 PM PDT 24
Peak memory 209388 kb
Host smart-d2b01426-e443-4517-b4a0-118d59aed35e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233147033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.3233147033
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3570067456
Short name T136
Test name
Test status
Simulation time 417981100 ps
CPU time 3.31 seconds
Started Jul 06 07:10:28 PM PDT 24
Finished Jul 06 07:10:34 PM PDT 24
Peak memory 218532 kb
Host smart-b01ae59e-b08e-4e72-a6a4-0bd6f701d30d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570067456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.3570067456
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.626202329
Short name T144
Test name
Test status
Simulation time 113598293 ps
CPU time 4.18 seconds
Started Jul 06 07:10:28 PM PDT 24
Finished Jul 06 07:10:34 PM PDT 24
Peak memory 217600 kb
Host smart-344bdb07-fb88-4813-9a50-6cd1a83de81b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626202329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_e
rr.626202329
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.339368008
Short name T618
Test name
Test status
Simulation time 21781597 ps
CPU time 1.19 seconds
Started Jul 06 07:15:19 PM PDT 24
Finished Jul 06 07:16:11 PM PDT 24
Peak memory 208560 kb
Host smart-1595ea98-a7bc-4597-80ea-a66cff43ea90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339368008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.339368008
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.2837790098
Short name T246
Test name
Test status
Simulation time 11363170 ps
CPU time 0.82 seconds
Started Jul 06 07:15:08 PM PDT 24
Finished Jul 06 07:16:09 PM PDT 24
Peak memory 208572 kb
Host smart-aef0b9d2-0b5d-4025-a853-001457832ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837790098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.2837790098
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.2524314831
Short name T260
Test name
Test status
Simulation time 3026683455 ps
CPU time 20.98 seconds
Started Jul 06 07:14:56 PM PDT 24
Finished Jul 06 07:16:29 PM PDT 24
Peak memory 218508 kb
Host smart-7baedce0-e123-46ba-abff-30f012ad5c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524314831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.2524314831
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.3222709121
Short name T613
Test name
Test status
Simulation time 1922264126 ps
CPU time 12.25 seconds
Started Jul 06 07:15:12 PM PDT 24
Finished Jul 06 07:16:20 PM PDT 24
Peak memory 217280 kb
Host smart-74cc55c8-6b62-4e2f-adb7-7c5ba668d587
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222709121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.3222709121
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.308218848
Short name T174
Test name
Test status
Simulation time 28993720616 ps
CPU time 49.5 seconds
Started Jul 06 07:15:12 PM PDT 24
Finished Jul 06 07:16:57 PM PDT 24
Peak memory 218428 kb
Host smart-07dee012-4421-44b8-9066-4d3a173a1c5e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308218848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_err
ors.308218848
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.3119645798
Short name T217
Test name
Test status
Simulation time 307454936 ps
CPU time 4.8 seconds
Started Jul 06 07:15:12 PM PDT 24
Finished Jul 06 07:16:13 PM PDT 24
Peak memory 217176 kb
Host smart-e867620e-af0b-4d05-a0af-080a73f31224
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119645798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.3
119645798
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.3634277391
Short name T722
Test name
Test status
Simulation time 828094344 ps
CPU time 25.22 seconds
Started Jul 06 07:15:10 PM PDT 24
Finished Jul 06 07:16:33 PM PDT 24
Peak memory 217256 kb
Host smart-efe5f503-82b7-4e25-93fb-7acf1429caae
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634277391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.3634277391
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.719006317
Short name T306
Test name
Test status
Simulation time 179922412 ps
CPU time 5.64 seconds
Started Jul 06 07:15:03 PM PDT 24
Finished Jul 06 07:16:12 PM PDT 24
Peak memory 217148 kb
Host smart-38cacd94-51ba-4ea0-b9ee-0eb7e66ec106
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719006317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.719006317
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.2191260695
Short name T689
Test name
Test status
Simulation time 73323841150 ps
CPU time 120.45 seconds
Started Jul 06 07:14:59 PM PDT 24
Finished Jul 06 07:18:06 PM PDT 24
Peak memory 281396 kb
Host smart-23325e5d-0d9b-4f0f-a2fb-5707ffb1f886
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191260695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.2191260695
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.4097511397
Short name T822
Test name
Test status
Simulation time 1473371851 ps
CPU time 12.2 seconds
Started Jul 06 07:15:06 PM PDT 24
Finished Jul 06 07:16:20 PM PDT 24
Peak memory 221600 kb
Host smart-84b98ff3-5076-4dfc-a10d-02d35cfabef1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097511397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.4097511397
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.2510576403
Short name T631
Test name
Test status
Simulation time 596793897 ps
CPU time 2.64 seconds
Started Jul 06 07:14:57 PM PDT 24
Finished Jul 06 07:16:08 PM PDT 24
Peak memory 217796 kb
Host smart-c13d9261-8f10-42d2-a8f1-f82cc4a7c806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510576403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.2510576403
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.3621404522
Short name T194
Test name
Test status
Simulation time 1216204891 ps
CPU time 15.86 seconds
Started Jul 06 07:14:59 PM PDT 24
Finished Jul 06 07:16:22 PM PDT 24
Peak memory 217196 kb
Host smart-ef9ee99b-912a-403e-960b-ff1f57f7cd28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621404522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.3621404522
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.4293938866
Short name T100
Test name
Test status
Simulation time 241814985 ps
CPU time 26.54 seconds
Started Jul 06 07:15:19 PM PDT 24
Finished Jul 06 07:16:36 PM PDT 24
Peak memory 284108 kb
Host smart-d5e4f16e-d03f-4a7b-b868-87dd853aaa53
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293938866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.4293938866
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.1473761035
Short name T764
Test name
Test status
Simulation time 277438530 ps
CPU time 7.83 seconds
Started Jul 06 07:15:18 PM PDT 24
Finished Jul 06 07:16:17 PM PDT 24
Peak memory 225528 kb
Host smart-5b63d7e8-319a-4494-9df4-5d9dbe160420
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473761035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.1473761035
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.1098027443
Short name T847
Test name
Test status
Simulation time 927534493 ps
CPU time 6.56 seconds
Started Jul 06 07:15:17 PM PDT 24
Finished Jul 06 07:16:16 PM PDT 24
Peak memory 217732 kb
Host smart-0baa88d1-97d9-4065-a7e0-166545ce3306
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098027443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.1
098027443
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.858291604
Short name T733
Test name
Test status
Simulation time 1210714177 ps
CPU time 10.16 seconds
Started Jul 06 07:15:02 PM PDT 24
Finished Jul 06 07:16:16 PM PDT 24
Peak memory 224100 kb
Host smart-f742f6ab-0828-42d0-9478-186ea8af98ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858291604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.858291604
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.3321569841
Short name T810
Test name
Test status
Simulation time 134872831 ps
CPU time 2.68 seconds
Started Jul 06 07:14:56 PM PDT 24
Finished Jul 06 07:16:10 PM PDT 24
Peak memory 217220 kb
Host smart-00580c55-581c-4bac-86d0-bce0ddbab659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321569841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.3321569841
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.2414061006
Short name T608
Test name
Test status
Simulation time 1011298881 ps
CPU time 30.85 seconds
Started Jul 06 07:14:58 PM PDT 24
Finished Jul 06 07:16:36 PM PDT 24
Peak memory 250548 kb
Host smart-f28b5ee9-9282-411b-88ac-a8d0f6989e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414061006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.2414061006
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.3094600139
Short name T568
Test name
Test status
Simulation time 379978821 ps
CPU time 7.7 seconds
Started Jul 06 07:14:58 PM PDT 24
Finished Jul 06 07:16:13 PM PDT 24
Peak memory 250548 kb
Host smart-01a7d98e-1f79-442e-a99f-d8a142d31d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094600139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.3094600139
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.2527528797
Short name T701
Test name
Test status
Simulation time 11960828862 ps
CPU time 200.24 seconds
Started Jul 06 07:15:19 PM PDT 24
Finished Jul 06 07:19:30 PM PDT 24
Peak memory 274648 kb
Host smart-8a313070-fe15-4127-af0e-d3dfd60960ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527528797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.2527528797
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.248738680
Short name T157
Test name
Test status
Simulation time 162651975385 ps
CPU time 1548.81 seconds
Started Jul 06 07:15:17 PM PDT 24
Finished Jul 06 07:41:59 PM PDT 24
Peak memory 528848 kb
Host smart-41909445-cd2d-4bf2-88fc-f9e60abce18e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=248738680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all_with_rand_reset.248738680
Directory /workspace/0.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.1650176570
Short name T85
Test name
Test status
Simulation time 15216306 ps
CPU time 1.16 seconds
Started Jul 06 07:14:51 PM PDT 24
Finished Jul 06 07:16:09 PM PDT 24
Peak memory 211488 kb
Host smart-4c95ea2a-16f6-4dbd-bf63-682b28aa646b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650176570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.1650176570
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.2653288568
Short name T249
Test name
Test status
Simulation time 119307929 ps
CPU time 1.19 seconds
Started Jul 06 07:15:37 PM PDT 24
Finished Jul 06 07:16:17 PM PDT 24
Peak memory 208604 kb
Host smart-e0a50635-2f81-416b-935e-5409b7113932
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653288568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.2653288568
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.2958215602
Short name T279
Test name
Test status
Simulation time 15200797 ps
CPU time 1.02 seconds
Started Jul 06 07:15:24 PM PDT 24
Finished Jul 06 07:16:13 PM PDT 24
Peak memory 208488 kb
Host smart-9dfaa69a-22e4-47cc-9332-894c1686b89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958215602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.2958215602
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.1119969077
Short name T748
Test name
Test status
Simulation time 1460063201 ps
CPU time 17.36 seconds
Started Jul 06 07:15:22 PM PDT 24
Finished Jul 06 07:16:29 PM PDT 24
Peak memory 225560 kb
Host smart-69c3b52f-838f-4e3b-bca6-e430c0cbce26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119969077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.1119969077
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.1187676565
Short name T5
Test name
Test status
Simulation time 70503184 ps
CPU time 1.6 seconds
Started Jul 06 07:15:23 PM PDT 24
Finished Jul 06 07:16:14 PM PDT 24
Peak memory 217308 kb
Host smart-bf1c6f92-196a-43cf-bd39-9eedc128707d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187676565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.1187676565
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.2182841162
Short name T868
Test name
Test status
Simulation time 4351416525 ps
CPU time 58.93 seconds
Started Jul 06 07:15:23 PM PDT 24
Finished Jul 06 07:17:11 PM PDT 24
Peak memory 220500 kb
Host smart-412550ed-c6a3-4583-91cd-dbf837fa3c65
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182841162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.2182841162
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.628861108
Short name T459
Test name
Test status
Simulation time 3414299332 ps
CPU time 9.09 seconds
Started Jul 06 07:15:22 PM PDT 24
Finished Jul 06 07:16:21 PM PDT 24
Peak memory 217304 kb
Host smart-cd054bab-ff62-4e22-8e4a-1337344ccc57
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628861108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.628861108
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.1256413494
Short name T719
Test name
Test status
Simulation time 156173778 ps
CPU time 3 seconds
Started Jul 06 07:15:23 PM PDT 24
Finished Jul 06 07:16:15 PM PDT 24
Peak memory 217748 kb
Host smart-4a7067dd-c1a6-42fe-9a6e-a5ef12ee1f82
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256413494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.1256413494
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.2758963453
Short name T83
Test name
Test status
Simulation time 8713538898 ps
CPU time 12.45 seconds
Started Jul 06 07:15:28 PM PDT 24
Finished Jul 06 07:16:28 PM PDT 24
Peak memory 217224 kb
Host smart-677cd61d-57a3-4e99-8bfb-b5bdd390dcab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758963453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.2758963453
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.3756415523
Short name T67
Test name
Test status
Simulation time 2000788608 ps
CPU time 13.74 seconds
Started Jul 06 07:15:23 PM PDT 24
Finished Jul 06 07:16:26 PM PDT 24
Peak memory 217076 kb
Host smart-b4f79fb6-fe8c-48d2-9020-647454525804
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756415523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
3756415523
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.297994506
Short name T582
Test name
Test status
Simulation time 5518850360 ps
CPU time 33.39 seconds
Started Jul 06 07:15:24 PM PDT 24
Finished Jul 06 07:16:45 PM PDT 24
Peak memory 283216 kb
Host smart-c46c055d-f24f-47c1-b777-3a93318f12d6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297994506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_state_failure.297994506
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.321319767
Short name T866
Test name
Test status
Simulation time 890503236 ps
CPU time 13.32 seconds
Started Jul 06 07:15:21 PM PDT 24
Finished Jul 06 07:16:25 PM PDT 24
Peak memory 250328 kb
Host smart-decd67bb-4ad6-4e78-9750-172247fc3ce8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321319767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_j
tag_state_post_trans.321319767
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.1102947065
Short name T738
Test name
Test status
Simulation time 729587430 ps
CPU time 2.11 seconds
Started Jul 06 07:15:24 PM PDT 24
Finished Jul 06 07:16:14 PM PDT 24
Peak memory 221820 kb
Host smart-7a89e7c1-be6f-476f-bfd2-472ea5be5786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102947065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.1102947065
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.2229469092
Short name T66
Test name
Test status
Simulation time 784592041 ps
CPU time 13.81 seconds
Started Jul 06 07:15:24 PM PDT 24
Finished Jul 06 07:16:26 PM PDT 24
Peak memory 214080 kb
Host smart-0422ed7f-0855-4273-87fe-6d0304190cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229469092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.2229469092
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.836646849
Short name T340
Test name
Test status
Simulation time 844318957 ps
CPU time 14.15 seconds
Started Jul 06 07:15:28 PM PDT 24
Finished Jul 06 07:16:28 PM PDT 24
Peak memory 225556 kb
Host smart-8929b970-2949-4a97-ac0c-8b9f6de0ab7c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836646849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.836646849
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.1187828512
Short name T676
Test name
Test status
Simulation time 3203462668 ps
CPU time 19.75 seconds
Started Jul 06 07:15:27 PM PDT 24
Finished Jul 06 07:16:36 PM PDT 24
Peak memory 225576 kb
Host smart-66c042ca-4b24-4684-87b2-b6c751e82a37
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187828512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.1187828512
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.4267818370
Short name T427
Test name
Test status
Simulation time 1001800533 ps
CPU time 9.4 seconds
Started Jul 06 07:15:35 PM PDT 24
Finished Jul 06 07:16:24 PM PDT 24
Peak memory 225524 kb
Host smart-4cf9fe82-c869-469d-bc55-70e767d2c885
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267818370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.4
267818370
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.1451453770
Short name T478
Test name
Test status
Simulation time 250726305 ps
CPU time 8.06 seconds
Started Jul 06 07:15:23 PM PDT 24
Finished Jul 06 07:16:20 PM PDT 24
Peak memory 224768 kb
Host smart-efb29379-e26a-4919-9e65-438c8b7a7263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451453770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.1451453770
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.1896020564
Short name T710
Test name
Test status
Simulation time 382960132 ps
CPU time 3.4 seconds
Started Jul 06 07:15:18 PM PDT 24
Finished Jul 06 07:16:13 PM PDT 24
Peak memory 217148 kb
Host smart-9a74ad93-fdd1-4d00-887c-c42e79f0f216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896020564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.1896020564
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.2774890990
Short name T393
Test name
Test status
Simulation time 549289103 ps
CPU time 30.32 seconds
Started Jul 06 07:15:18 PM PDT 24
Finished Jul 06 07:16:40 PM PDT 24
Peak memory 250516 kb
Host smart-d5c79de9-918a-4d68-ab9c-b811a689558f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774890990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.2774890990
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.2324934186
Short name T518
Test name
Test status
Simulation time 87178911 ps
CPU time 2.55 seconds
Started Jul 06 07:15:23 PM PDT 24
Finished Jul 06 07:16:15 PM PDT 24
Peak memory 221628 kb
Host smart-b0519334-dd4b-4330-95fc-c422b8b69968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324934186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.2324934186
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.1869916987
Short name T700
Test name
Test status
Simulation time 5659407894 ps
CPU time 194.71 seconds
Started Jul 06 07:15:27 PM PDT 24
Finished Jul 06 07:19:31 PM PDT 24
Peak memory 250836 kb
Host smart-57cf4d6c-f768-4093-9b62-f68c29fdef64
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869916987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.1869916987
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.3871376539
Short name T166
Test name
Test status
Simulation time 528164349510 ps
CPU time 6807.15 seconds
Started Jul 06 07:15:28 PM PDT 24
Finished Jul 06 09:09:44 PM PDT 24
Peak memory 758640 kb
Host smart-e16656d5-3a1e-4965-a3ea-f13f46a3f77b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3871376539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all_with_rand_reset.3871376539
Directory /workspace/1.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1368166076
Short name T808
Test name
Test status
Simulation time 12900143 ps
CPU time 0.95 seconds
Started Jul 06 07:15:17 PM PDT 24
Finished Jul 06 07:16:11 PM PDT 24
Peak memory 211404 kb
Host smart-e2317265-b727-47c4-9464-b61aba89dbab
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368166076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.1368166076
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.3633326611
Short name T815
Test name
Test status
Simulation time 23149389 ps
CPU time 1.22 seconds
Started Jul 06 07:17:15 PM PDT 24
Finished Jul 06 07:17:21 PM PDT 24
Peak memory 208524 kb
Host smart-6ab30e73-64fa-4a16-8c9f-118482c303c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633326611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.3633326611
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.666768522
Short name T440
Test name
Test status
Simulation time 268384694 ps
CPU time 10.99 seconds
Started Jul 06 07:17:12 PM PDT 24
Finished Jul 06 07:17:29 PM PDT 24
Peak memory 217808 kb
Host smart-383c049e-07ae-461a-ac13-0fb665e5c905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666768522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.666768522
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.463401393
Short name T415
Test name
Test status
Simulation time 3068520292 ps
CPU time 7.94 seconds
Started Jul 06 07:17:15 PM PDT 24
Finished Jul 06 07:17:28 PM PDT 24
Peak memory 217272 kb
Host smart-28f98b19-d195-4f4d-b81a-8a28fd831aef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463401393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.463401393
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.1037822388
Short name T520
Test name
Test status
Simulation time 11519706060 ps
CPU time 41.57 seconds
Started Jul 06 07:17:13 PM PDT 24
Finished Jul 06 07:18:00 PM PDT 24
Peak memory 219060 kb
Host smart-af4c1640-7a37-44d5-84bb-174367a6a6ed
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037822388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.1037822388
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.1715197445
Short name T634
Test name
Test status
Simulation time 368763125 ps
CPU time 11.74 seconds
Started Jul 06 07:17:15 PM PDT 24
Finished Jul 06 07:17:32 PM PDT 24
Peak memory 217708 kb
Host smart-47e51947-b91d-42ca-851c-69a828f39770
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715197445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.1715197445
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.453951584
Short name T171
Test name
Test status
Simulation time 1361021006 ps
CPU time 41.61 seconds
Started Jul 06 07:17:13 PM PDT 24
Finished Jul 06 07:18:00 PM PDT 24
Peak memory 275860 kb
Host smart-8585b791-3271-42a1-8930-331dc9cf915f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453951584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_state_failure.453951584
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.2827685520
Short name T484
Test name
Test status
Simulation time 426229937 ps
CPU time 17.84 seconds
Started Jul 06 07:17:18 PM PDT 24
Finished Jul 06 07:17:39 PM PDT 24
Peak memory 250428 kb
Host smart-afcd43bb-35f5-41e7-9830-05e019a01a04
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827685520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.2827685520
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.1435205993
Short name T184
Test name
Test status
Simulation time 454594981 ps
CPU time 3.02 seconds
Started Jul 06 07:17:12 PM PDT 24
Finished Jul 06 07:17:20 PM PDT 24
Peak memory 217796 kb
Host smart-24e8a7bb-a551-421a-8e0d-01d122998f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435205993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.1435205993
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.2870090974
Short name T536
Test name
Test status
Simulation time 1430296724 ps
CPU time 13.31 seconds
Started Jul 06 07:17:19 PM PDT 24
Finished Jul 06 07:17:34 PM PDT 24
Peak memory 225532 kb
Host smart-50b57792-c1b2-49a5-b20a-663cf6a8071f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870090974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.2870090974
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.157159784
Short name T265
Test name
Test status
Simulation time 1415554371 ps
CPU time 28.14 seconds
Started Jul 06 07:17:13 PM PDT 24
Finished Jul 06 07:17:47 PM PDT 24
Peak memory 225480 kb
Host smart-d7b51f7c-8f64-4715-bcaf-413b9fcb090d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157159784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_di
gest.157159784
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.3495831108
Short name T667
Test name
Test status
Simulation time 2260268934 ps
CPU time 13.29 seconds
Started Jul 06 07:17:12 PM PDT 24
Finished Jul 06 07:17:31 PM PDT 24
Peak memory 217772 kb
Host smart-640f3905-340d-4445-9128-71df737881a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495831108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
3495831108
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.4264914296
Short name T162
Test name
Test status
Simulation time 298268662 ps
CPU time 7.76 seconds
Started Jul 06 07:17:15 PM PDT 24
Finished Jul 06 07:17:27 PM PDT 24
Peak memory 217872 kb
Host smart-8c06d101-c517-476d-9505-c4592761984e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264914296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.4264914296
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.3216689546
Short name T289
Test name
Test status
Simulation time 17256397 ps
CPU time 1.47 seconds
Started Jul 06 07:17:13 PM PDT 24
Finished Jul 06 07:17:19 PM PDT 24
Peak memory 213172 kb
Host smart-2f52503b-2cd6-4333-aaf1-c348ec4e9986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216689546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.3216689546
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.989328171
Short name T108
Test name
Test status
Simulation time 223830276 ps
CPU time 27.7 seconds
Started Jul 06 07:17:18 PM PDT 24
Finished Jul 06 07:17:48 PM PDT 24
Peak memory 250488 kb
Host smart-fad9d6c4-d709-47b3-a23f-7f5a78607689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989328171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.989328171
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.55589523
Short name T651
Test name
Test status
Simulation time 1526588514 ps
CPU time 47.4 seconds
Started Jul 06 07:17:18 PM PDT 24
Finished Jul 06 07:18:08 PM PDT 24
Peak memory 269728 kb
Host smart-7d68c446-9657-462c-841e-9690060beb0b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55589523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.lc_ctrl_stress_all.55589523
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.3610126228
Short name T823
Test name
Test status
Simulation time 19426892 ps
CPU time 1.05 seconds
Started Jul 06 07:17:11 PM PDT 24
Finished Jul 06 07:17:18 PM PDT 24
Peak memory 212432 kb
Host smart-038deb21-a24d-40e7-b5e0-860f7b42e66c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610126228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.3610126228
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.2463156885
Short name T230
Test name
Test status
Simulation time 47843996 ps
CPU time 0.85 seconds
Started Jul 06 07:17:24 PM PDT 24
Finished Jul 06 07:17:26 PM PDT 24
Peak memory 208428 kb
Host smart-d9f60ba2-53ff-4fcb-afc2-b660fc6b5483
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463156885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.2463156885
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.1431920567
Short name T780
Test name
Test status
Simulation time 981321230 ps
CPU time 12.46 seconds
Started Jul 06 07:17:19 PM PDT 24
Finished Jul 06 07:17:34 PM PDT 24
Peak memory 217804 kb
Host smart-20ed9ec7-ec2e-48fc-be98-1c1a0bb469ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431920567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.1431920567
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.27314162
Short name T563
Test name
Test status
Simulation time 3058567063 ps
CPU time 7.83 seconds
Started Jul 06 07:17:27 PM PDT 24
Finished Jul 06 07:17:36 PM PDT 24
Peak memory 217284 kb
Host smart-fdeab489-aa89-46eb-b3ff-ed9606137409
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27314162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.27314162
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.2419692685
Short name T326
Test name
Test status
Simulation time 1429299497 ps
CPU time 24.25 seconds
Started Jul 06 07:17:23 PM PDT 24
Finished Jul 06 07:17:48 PM PDT 24
Peak memory 218388 kb
Host smart-b5f3140b-bd4b-414a-b31e-4d830b431092
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419692685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.2419692685
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.1524586051
Short name T293
Test name
Test status
Simulation time 213129157 ps
CPU time 4.09 seconds
Started Jul 06 07:17:24 PM PDT 24
Finished Jul 06 07:17:29 PM PDT 24
Peak memory 217692 kb
Host smart-27fc16c4-0547-421f-8d7d-80a7281e415a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524586051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.1524586051
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.3885245266
Short name T635
Test name
Test status
Simulation time 1316032223 ps
CPU time 2.71 seconds
Started Jul 06 07:17:20 PM PDT 24
Finished Jul 06 07:17:24 PM PDT 24
Peak memory 217132 kb
Host smart-2f9dfa9a-5e32-4cc4-a4fe-0ad728f8fe19
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885245266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.3885245266
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.464909776
Short name T460
Test name
Test status
Simulation time 5025672721 ps
CPU time 83.22 seconds
Started Jul 06 07:17:20 PM PDT 24
Finished Jul 06 07:18:45 PM PDT 24
Peak memory 283272 kb
Host smart-24f55598-9576-45d3-8847-6c38354f7250
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464909776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_state_failure.464909776
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.2001590735
Short name T312
Test name
Test status
Simulation time 824963205 ps
CPU time 7.78 seconds
Started Jul 06 07:17:24 PM PDT 24
Finished Jul 06 07:17:33 PM PDT 24
Peak memory 222444 kb
Host smart-3e5ee736-c0f8-4c06-a5f2-b8d0a23c621e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001590735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.2001590735
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.4169603921
Short name T362
Test name
Test status
Simulation time 227976782 ps
CPU time 3.39 seconds
Started Jul 06 07:17:20 PM PDT 24
Finished Jul 06 07:17:25 PM PDT 24
Peak memory 217736 kb
Host smart-e5237368-82ce-4523-aac6-26bbf3b617d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169603921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.4169603921
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.2514121406
Short name T677
Test name
Test status
Simulation time 470342667 ps
CPU time 13.49 seconds
Started Jul 06 07:17:27 PM PDT 24
Finished Jul 06 07:17:41 PM PDT 24
Peak memory 225560 kb
Host smart-b0f92e1b-12cc-4565-8310-6b0154dfccf1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514121406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.2514121406
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.2911379709
Short name T15
Test name
Test status
Simulation time 500232611 ps
CPU time 10.49 seconds
Started Jul 06 07:17:26 PM PDT 24
Finished Jul 06 07:17:37 PM PDT 24
Peak memory 225524 kb
Host smart-d4f94d42-e5cc-4123-9e05-dc2e67b571e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911379709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.2911379709
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.1677050737
Short name T760
Test name
Test status
Simulation time 329951426 ps
CPU time 10.43 seconds
Started Jul 06 07:17:27 PM PDT 24
Finished Jul 06 07:17:38 PM PDT 24
Peak memory 217752 kb
Host smart-5c749fba-90e3-4e5d-8e00-cdfd808f7fc5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677050737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
1677050737
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.931583583
Short name T54
Test name
Test status
Simulation time 442081038 ps
CPU time 9.6 seconds
Started Jul 06 07:17:20 PM PDT 24
Finished Jul 06 07:17:31 PM PDT 24
Peak memory 225596 kb
Host smart-3e67662d-6c0e-49b6-a6de-6faa936bdd54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931583583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.931583583
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.1986019154
Short name T549
Test name
Test status
Simulation time 56614514 ps
CPU time 3.58 seconds
Started Jul 06 07:17:13 PM PDT 24
Finished Jul 06 07:17:22 PM PDT 24
Peak memory 217228 kb
Host smart-c37a3304-b74e-4eef-bd63-96308cd123c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986019154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.1986019154
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.522360142
Short name T775
Test name
Test status
Simulation time 1052705600 ps
CPU time 21.18 seconds
Started Jul 06 07:17:15 PM PDT 24
Finished Jul 06 07:17:41 PM PDT 24
Peak memory 250504 kb
Host smart-51f525de-34d2-4b69-a24a-26c427dd4ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522360142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.522360142
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.1583756929
Short name T510
Test name
Test status
Simulation time 89053650 ps
CPU time 4.61 seconds
Started Jul 06 07:17:19 PM PDT 24
Finished Jul 06 07:17:26 PM PDT 24
Peak memory 222272 kb
Host smart-dd4eeaad-16f7-4e98-b00c-f953f5230238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583756929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.1583756929
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.2767446749
Short name T190
Test name
Test status
Simulation time 7372475751 ps
CPU time 108.05 seconds
Started Jul 06 07:17:23 PM PDT 24
Finished Jul 06 07:19:12 PM PDT 24
Peak memory 283228 kb
Host smart-30a8878f-067b-4d93-a519-7da4115ed8d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767446749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.2767446749
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.2201436983
Short name T792
Test name
Test status
Simulation time 14526918 ps
CPU time 1 seconds
Started Jul 06 07:17:14 PM PDT 24
Finished Jul 06 07:17:20 PM PDT 24
Peak memory 208728 kb
Host smart-4929ec8f-9974-46a6-8744-e8140c53d332
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201436983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.2201436983
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.1149658952
Short name T761
Test name
Test status
Simulation time 16710114 ps
CPU time 0.98 seconds
Started Jul 06 07:17:33 PM PDT 24
Finished Jul 06 07:17:35 PM PDT 24
Peak memory 208556 kb
Host smart-7e157a21-5090-4ace-81fe-90a2c677625e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149658952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.1149658952
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.2225286128
Short name T796
Test name
Test status
Simulation time 454525005 ps
CPU time 9.13 seconds
Started Jul 06 07:17:32 PM PDT 24
Finished Jul 06 07:17:43 PM PDT 24
Peak memory 225596 kb
Host smart-e8e25d3f-dbde-4ba0-aa36-18b04c3b7a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225286128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.2225286128
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.3006092684
Short name T816
Test name
Test status
Simulation time 124144841 ps
CPU time 1.5 seconds
Started Jul 06 07:17:28 PM PDT 24
Finished Jul 06 07:17:31 PM PDT 24
Peak memory 217176 kb
Host smart-3edc5901-eed8-4116-9bd6-14956c34a417
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006092684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.3006092684
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.1698608351
Short name T565
Test name
Test status
Simulation time 2310737253 ps
CPU time 35.95 seconds
Started Jul 06 07:17:32 PM PDT 24
Finished Jul 06 07:18:09 PM PDT 24
Peak memory 218420 kb
Host smart-65851eac-8135-4d6b-854f-47fb56860be1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698608351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.1698608351
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.901888158
Short name T840
Test name
Test status
Simulation time 2732825669 ps
CPU time 9.13 seconds
Started Jul 06 07:17:31 PM PDT 24
Finished Jul 06 07:17:41 PM PDT 24
Peak memory 225028 kb
Host smart-d105b744-3a99-47fd-8ed1-bd10332f1c2d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901888158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag
_prog_failure.901888158
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.3964657262
Short name T516
Test name
Test status
Simulation time 84099845 ps
CPU time 1.9 seconds
Started Jul 06 07:17:30 PM PDT 24
Finished Jul 06 07:17:33 PM PDT 24
Peak memory 217088 kb
Host smart-314384c3-6dd9-446a-a381-4675a8fcf565
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964657262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.3964657262
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.981191998
Short name T493
Test name
Test status
Simulation time 88307883203 ps
CPU time 84.49 seconds
Started Jul 06 07:17:29 PM PDT 24
Finished Jul 06 07:18:55 PM PDT 24
Peak memory 283248 kb
Host smart-308c4d19-7c78-456b-98e7-650064fcb56b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981191998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_state_failure.981191998
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.4136034535
Short name T684
Test name
Test status
Simulation time 3133895062 ps
CPU time 18.82 seconds
Started Jul 06 07:17:32 PM PDT 24
Finished Jul 06 07:17:53 PM PDT 24
Peak memory 250540 kb
Host smart-98afed2b-11d0-4491-9b2c-b261fc674f41
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136034535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.4136034535
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.1302702087
Short name T525
Test name
Test status
Simulation time 320221982 ps
CPU time 4.82 seconds
Started Jul 06 07:17:29 PM PDT 24
Finished Jul 06 07:17:35 PM PDT 24
Peak memory 217740 kb
Host smart-41e52336-9a81-40f4-8b2e-d214f283b6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302702087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.1302702087
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.1685671942
Short name T507
Test name
Test status
Simulation time 256216287 ps
CPU time 8.63 seconds
Started Jul 06 07:17:34 PM PDT 24
Finished Jul 06 07:17:44 PM PDT 24
Peak memory 217816 kb
Host smart-1398b327-948b-4ca8-aaa0-c4d2b6c19298
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685671942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.1685671942
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.3315116924
Short name T824
Test name
Test status
Simulation time 2078677586 ps
CPU time 17.56 seconds
Started Jul 06 07:17:29 PM PDT 24
Finished Jul 06 07:17:47 PM PDT 24
Peak memory 225472 kb
Host smart-bd8059b6-6aa1-4fed-ae2b-b48cc5c91bdc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315116924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.3315116924
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.3029173407
Short name T413
Test name
Test status
Simulation time 390669103 ps
CPU time 10.99 seconds
Started Jul 06 07:17:30 PM PDT 24
Finished Jul 06 07:17:42 PM PDT 24
Peak memory 225512 kb
Host smart-b48fe703-1ceb-4adc-8f46-d1d7a2adbce9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029173407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
3029173407
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.1089652059
Short name T397
Test name
Test status
Simulation time 461912685 ps
CPU time 12.94 seconds
Started Jul 06 07:17:32 PM PDT 24
Finished Jul 06 07:17:47 PM PDT 24
Peak memory 225592 kb
Host smart-7a667f6b-a24b-4fda-b14d-9855588f11b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089652059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.1089652059
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.425165570
Short name T513
Test name
Test status
Simulation time 17032799 ps
CPU time 1.29 seconds
Started Jul 06 07:17:27 PM PDT 24
Finished Jul 06 07:17:29 PM PDT 24
Peak memory 213008 kb
Host smart-61c975c4-a217-493c-94c8-41fc723d5ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425165570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.425165570
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.4220342490
Short name T291
Test name
Test status
Simulation time 892627718 ps
CPU time 25.04 seconds
Started Jul 06 07:17:26 PM PDT 24
Finished Jul 06 07:17:51 PM PDT 24
Peak memory 250536 kb
Host smart-ff114ce1-6316-46c7-9ce0-233530d8920e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220342490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.4220342490
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.1498475219
Short name T798
Test name
Test status
Simulation time 424408366 ps
CPU time 8.41 seconds
Started Jul 06 07:17:25 PM PDT 24
Finished Jul 06 07:17:34 PM PDT 24
Peak memory 250520 kb
Host smart-b624c48f-f7a9-4d6f-b566-4df2d0389c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498475219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.1498475219
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.2912669979
Short name T717
Test name
Test status
Simulation time 5159001591 ps
CPU time 41.56 seconds
Started Jul 06 07:17:29 PM PDT 24
Finished Jul 06 07:18:11 PM PDT 24
Peak memory 250624 kb
Host smart-4efc9776-3140-4815-8b74-6378b7327304
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912669979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.2912669979
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.3773058643
Short name T690
Test name
Test status
Simulation time 60077648 ps
CPU time 0.92 seconds
Started Jul 06 07:17:43 PM PDT 24
Finished Jul 06 07:17:45 PM PDT 24
Peak memory 208548 kb
Host smart-fec0fdbb-a35f-482d-8e5a-196e767c43bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773058643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.3773058643
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.2712741742
Short name T528
Test name
Test status
Simulation time 1072725427 ps
CPU time 10.4 seconds
Started Jul 06 07:17:36 PM PDT 24
Finished Jul 06 07:17:48 PM PDT 24
Peak memory 217792 kb
Host smart-c01f4328-14cf-43b6-8991-f08d10a173f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712741742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.2712741742
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.2571174648
Short name T446
Test name
Test status
Simulation time 334025601 ps
CPU time 9.63 seconds
Started Jul 06 07:17:35 PM PDT 24
Finished Jul 06 07:17:46 PM PDT 24
Peak memory 217188 kb
Host smart-1dead3ab-1886-4556-a40d-c5555f5ef1b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571174648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.2571174648
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.2421053994
Short name T615
Test name
Test status
Simulation time 1827397004 ps
CPU time 29.85 seconds
Started Jul 06 07:17:35 PM PDT 24
Finished Jul 06 07:18:06 PM PDT 24
Peak memory 217720 kb
Host smart-1782f4f6-73a6-433e-8800-a062da1040c5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421053994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.2421053994
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.812545768
Short name T637
Test name
Test status
Simulation time 296588033 ps
CPU time 5.37 seconds
Started Jul 06 07:17:36 PM PDT 24
Finished Jul 06 07:17:43 PM PDT 24
Peak memory 222508 kb
Host smart-f25a4759-36c8-4f5e-a78b-fbef4ed88aae
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812545768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag
_prog_failure.812545768
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.2250439608
Short name T585
Test name
Test status
Simulation time 776973213 ps
CPU time 5.04 seconds
Started Jul 06 07:17:36 PM PDT 24
Finished Jul 06 07:17:42 PM PDT 24
Peak memory 217164 kb
Host smart-217ddd0d-afd5-48e4-879f-cbe503f8a662
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250439608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.2250439608
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.3665655059
Short name T731
Test name
Test status
Simulation time 5541825336 ps
CPU time 35.28 seconds
Started Jul 06 07:17:35 PM PDT 24
Finished Jul 06 07:18:12 PM PDT 24
Peak memory 250508 kb
Host smart-95bade6e-8021-414d-a53b-31433cf760d2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665655059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.3665655059
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.1516125155
Short name T356
Test name
Test status
Simulation time 1850628085 ps
CPU time 16.79 seconds
Started Jul 06 07:17:35 PM PDT 24
Finished Jul 06 07:17:54 PM PDT 24
Peak memory 250472 kb
Host smart-97fd0b20-bcf7-446c-93a5-bc2e2b646da5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516125155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.1516125155
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.2079579828
Short name T31
Test name
Test status
Simulation time 105629707 ps
CPU time 2.51 seconds
Started Jul 06 07:17:34 PM PDT 24
Finished Jul 06 07:17:38 PM PDT 24
Peak memory 217800 kb
Host smart-32d199e2-a908-48c0-947f-b5aa02b65029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079579828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.2079579828
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.3182895631
Short name T600
Test name
Test status
Simulation time 1569925628 ps
CPU time 13.93 seconds
Started Jul 06 07:17:37 PM PDT 24
Finished Jul 06 07:17:52 PM PDT 24
Peak memory 225456 kb
Host smart-107d66bf-081a-4fce-b9f7-c7541baee03d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182895631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.3182895631
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.3795867649
Short name T292
Test name
Test status
Simulation time 3032660998 ps
CPU time 19.75 seconds
Started Jul 06 07:17:36 PM PDT 24
Finished Jul 06 07:17:57 PM PDT 24
Peak memory 225556 kb
Host smart-fd6ec72c-5f15-4828-b10e-b4d7d9964871
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795867649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.3795867649
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.1320807746
Short name T567
Test name
Test status
Simulation time 260975936 ps
CPU time 7.22 seconds
Started Jul 06 07:17:35 PM PDT 24
Finished Jul 06 07:17:43 PM PDT 24
Peak memory 217752 kb
Host smart-27943eb1-fbcf-4c82-9cb2-e40c0f05d48f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320807746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
1320807746
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.2811598276
Short name T379
Test name
Test status
Simulation time 849064781 ps
CPU time 8.61 seconds
Started Jul 06 07:17:36 PM PDT 24
Finished Jul 06 07:17:46 PM PDT 24
Peak memory 217824 kb
Host smart-abe9373d-545c-4521-aa85-384fca330320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811598276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.2811598276
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.889604602
Short name T68
Test name
Test status
Simulation time 92274012 ps
CPU time 5.66 seconds
Started Jul 06 07:17:33 PM PDT 24
Finished Jul 06 07:17:40 PM PDT 24
Peak memory 222872 kb
Host smart-81db4693-8f53-4325-9366-1fbf39b689ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889604602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.889604602
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.2661791026
Short name T335
Test name
Test status
Simulation time 858836483 ps
CPU time 19.2 seconds
Started Jul 06 07:17:52 PM PDT 24
Finished Jul 06 07:18:13 PM PDT 24
Peak memory 250528 kb
Host smart-6031469c-e003-4955-a9a2-c74e47cb78f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661791026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.2661791026
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.3959811783
Short name T329
Test name
Test status
Simulation time 875219909 ps
CPU time 7.22 seconds
Started Jul 06 07:17:36 PM PDT 24
Finished Jul 06 07:17:45 PM PDT 24
Peak memory 245652 kb
Host smart-de10287e-1516-4f30-9909-8593b4c161ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959811783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.3959811783
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.1061987589
Short name T814
Test name
Test status
Simulation time 8451195974 ps
CPU time 154.04 seconds
Started Jul 06 07:17:35 PM PDT 24
Finished Jul 06 07:20:10 PM PDT 24
Peak memory 283240 kb
Host smart-e18b02d9-b6fd-4aea-ab9b-a1cd23dc4420
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061987589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.1061987589
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.2958647269
Short name T153
Test name
Test status
Simulation time 82385506769 ps
CPU time 2213.49 seconds
Started Jul 06 07:17:36 PM PDT 24
Finished Jul 06 07:54:31 PM PDT 24
Peak memory 578408 kb
Host smart-ab33e87a-ff58-4290-9a9e-9b3cbbd19407
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2958647269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.2958647269
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.3603162979
Short name T617
Test name
Test status
Simulation time 13796908 ps
CPU time 0.93 seconds
Started Jul 06 07:17:34 PM PDT 24
Finished Jul 06 07:17:36 PM PDT 24
Peak memory 208452 kb
Host smart-d0a6d963-0915-4671-a8e8-6d31d9f19c94
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603162979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.3603162979
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.2212482829
Short name T560
Test name
Test status
Simulation time 69557337 ps
CPU time 1.24 seconds
Started Jul 06 07:17:41 PM PDT 24
Finished Jul 06 07:17:44 PM PDT 24
Peak memory 208616 kb
Host smart-942c68ad-e266-43e5-b6b7-e955cfdab911
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212482829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.2212482829
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.2874851984
Short name T547
Test name
Test status
Simulation time 302015740 ps
CPU time 14.56 seconds
Started Jul 06 07:17:43 PM PDT 24
Finished Jul 06 07:17:59 PM PDT 24
Peak memory 217732 kb
Host smart-0ce33b87-fdbd-4424-a8c3-eca4db162ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874851984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.2874851984
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.2492261726
Short name T231
Test name
Test status
Simulation time 105534232 ps
CPU time 1.68 seconds
Started Jul 06 07:17:42 PM PDT 24
Finished Jul 06 07:17:45 PM PDT 24
Peak memory 217180 kb
Host smart-919696bb-e05e-4711-aa83-3edac8961247
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492261726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.2492261726
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.2134153316
Short name T577
Test name
Test status
Simulation time 1974670907 ps
CPU time 63 seconds
Started Jul 06 07:17:43 PM PDT 24
Finished Jul 06 07:18:47 PM PDT 24
Peak memory 217748 kb
Host smart-85295aa7-1fa8-49ee-91ac-b18f6dce7aae
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134153316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.2134153316
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.2938369607
Short name T411
Test name
Test status
Simulation time 104286140 ps
CPU time 2.54 seconds
Started Jul 06 07:17:44 PM PDT 24
Finished Jul 06 07:17:47 PM PDT 24
Peak memory 221156 kb
Host smart-3e3f275c-556e-423a-a86f-543beb7057c6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938369607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.2938369607
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.1905011198
Short name T294
Test name
Test status
Simulation time 821995112 ps
CPU time 6.21 seconds
Started Jul 06 07:17:41 PM PDT 24
Finished Jul 06 07:17:48 PM PDT 24
Peak memory 217104 kb
Host smart-af0dfbff-a068-4900-b99b-87da989c0db5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905011198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.1905011198
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.1709426392
Short name T349
Test name
Test status
Simulation time 2501441667 ps
CPU time 84.7 seconds
Started Jul 06 07:17:41 PM PDT 24
Finished Jul 06 07:19:06 PM PDT 24
Peak memory 283256 kb
Host smart-0a57b47c-0e74-4278-b8f9-854988ee28bc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709426392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.1709426392
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.57861683
Short name T449
Test name
Test status
Simulation time 549582364 ps
CPU time 21.7 seconds
Started Jul 06 07:17:42 PM PDT 24
Finished Jul 06 07:18:05 PM PDT 24
Peak memory 250492 kb
Host smart-6986c6cf-5c2e-4724-80cb-019a6a917257
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57861683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_j
tag_state_post_trans.57861683
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.2778778253
Short name T344
Test name
Test status
Simulation time 114814615 ps
CPU time 2.55 seconds
Started Jul 06 07:17:42 PM PDT 24
Finished Jul 06 07:17:46 PM PDT 24
Peak memory 221928 kb
Host smart-41c5c09d-4438-45d0-a505-f5a216aa850b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778778253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.2778778253
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.2720264408
Short name T590
Test name
Test status
Simulation time 1721703250 ps
CPU time 13.85 seconds
Started Jul 06 07:17:42 PM PDT 24
Finished Jul 06 07:17:57 PM PDT 24
Peak memory 218444 kb
Host smart-101a7846-569f-4138-a974-f2265dddfcd4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720264408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.2720264408
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.2622327887
Short name T280
Test name
Test status
Simulation time 345277174 ps
CPU time 12.9 seconds
Started Jul 06 07:17:44 PM PDT 24
Finished Jul 06 07:17:59 PM PDT 24
Peak memory 225532 kb
Host smart-6e410fdd-f67b-4525-ba72-dd66e98e4478
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622327887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.2622327887
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.86910878
Short name T658
Test name
Test status
Simulation time 4574084733 ps
CPU time 11.38 seconds
Started Jul 06 07:17:41 PM PDT 24
Finished Jul 06 07:17:54 PM PDT 24
Peak memory 217776 kb
Host smart-56d54d3a-9c87-4739-b4ec-71250be6406c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86910878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.86910878
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.2780218392
Short name T745
Test name
Test status
Simulation time 315569084 ps
CPU time 9.82 seconds
Started Jul 06 07:17:41 PM PDT 24
Finished Jul 06 07:17:52 PM PDT 24
Peak memory 225604 kb
Host smart-a160bd04-6bc5-4fd3-b624-e2aa93583ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780218392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.2780218392
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.2427408290
Short name T14
Test name
Test status
Simulation time 66571285 ps
CPU time 2.46 seconds
Started Jul 06 07:17:41 PM PDT 24
Finished Jul 06 07:17:45 PM PDT 24
Peak memory 217172 kb
Host smart-87e6b29f-8c28-4d16-a467-bf8cf24b3559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427408290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.2427408290
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.1133602967
Short name T683
Test name
Test status
Simulation time 168103464 ps
CPU time 20.13 seconds
Started Jul 06 07:17:43 PM PDT 24
Finished Jul 06 07:18:04 PM PDT 24
Peak memory 245356 kb
Host smart-abeab5f0-aa91-46e1-8e7e-2d2739577140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133602967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.1133602967
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.3619252309
Short name T779
Test name
Test status
Simulation time 258255083 ps
CPU time 7.75 seconds
Started Jul 06 07:17:41 PM PDT 24
Finished Jul 06 07:17:50 PM PDT 24
Peak memory 250532 kb
Host smart-c686d25d-4eec-43a2-9596-d5433f08dbb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619252309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.3619252309
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.4200446635
Short name T188
Test name
Test status
Simulation time 3757697406 ps
CPU time 148.84 seconds
Started Jul 06 07:17:44 PM PDT 24
Finished Jul 06 07:20:14 PM PDT 24
Peak memory 266964 kb
Host smart-74d04a56-5582-4c66-adcc-b409bc498f06
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200446635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.4200446635
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.3824329786
Short name T662
Test name
Test status
Simulation time 34278994 ps
CPU time 0.86 seconds
Started Jul 06 07:17:42 PM PDT 24
Finished Jul 06 07:17:44 PM PDT 24
Peak memory 208440 kb
Host smart-cde01d03-b50e-4827-a74c-aab52be7e0f8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824329786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.3824329786
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.756744926
Short name T321
Test name
Test status
Simulation time 19552017 ps
CPU time 1.22 seconds
Started Jul 06 07:17:48 PM PDT 24
Finished Jul 06 07:17:52 PM PDT 24
Peak memory 208600 kb
Host smart-ee4ca23b-1903-4094-b7ec-233bebb11955
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756744926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.756744926
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.897082557
Short name T771
Test name
Test status
Simulation time 776903218 ps
CPU time 28.67 seconds
Started Jul 06 07:17:46 PM PDT 24
Finished Jul 06 07:18:18 PM PDT 24
Peak memory 217792 kb
Host smart-7a7a2bcb-52ce-440b-a733-7b658559eb88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897082557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.897082557
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.3412169383
Short name T797
Test name
Test status
Simulation time 1442512998 ps
CPU time 5.82 seconds
Started Jul 06 07:17:47 PM PDT 24
Finished Jul 06 07:17:56 PM PDT 24
Peak memory 216680 kb
Host smart-580181b4-8569-4ee1-835d-4f0708d30436
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412169383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.3412169383
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.2211131341
Short name T450
Test name
Test status
Simulation time 3077959749 ps
CPU time 38.02 seconds
Started Jul 06 07:17:46 PM PDT 24
Finished Jul 06 07:18:28 PM PDT 24
Peak memory 218452 kb
Host smart-0512452d-e886-41f1-8b0f-ee2945052350
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211131341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.2211131341
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.346173315
Short name T500
Test name
Test status
Simulation time 292244506 ps
CPU time 9.7 seconds
Started Jul 06 07:17:48 PM PDT 24
Finished Jul 06 07:18:01 PM PDT 24
Peak memory 222736 kb
Host smart-43344961-bf37-44ae-908b-a7b0281ffd8e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346173315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag
_prog_failure.346173315
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.769274462
Short name T619
Test name
Test status
Simulation time 268407609 ps
CPU time 4.95 seconds
Started Jul 06 07:17:49 PM PDT 24
Finished Jul 06 07:17:56 PM PDT 24
Peak memory 217164 kb
Host smart-a945d4c4-2c42-49af-9f6e-ef7342030257
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769274462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke.
769274462
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.1297291358
Short name T239
Test name
Test status
Simulation time 3109413534 ps
CPU time 66.2 seconds
Started Jul 06 07:17:49 PM PDT 24
Finished Jul 06 07:18:58 PM PDT 24
Peak memory 275084 kb
Host smart-d0c9a4e5-d667-470c-9a97-8739c19959dd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297291358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.1297291358
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.793944085
Short name T747
Test name
Test status
Simulation time 784985958 ps
CPU time 13.35 seconds
Started Jul 06 07:17:47 PM PDT 24
Finished Jul 06 07:18:04 PM PDT 24
Peak memory 246120 kb
Host smart-9acb81e6-7c4e-425b-a969-e217071abae8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793944085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_
jtag_state_post_trans.793944085
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.48586637
Short name T696
Test name
Test status
Simulation time 42425094 ps
CPU time 1.57 seconds
Started Jul 06 07:17:47 PM PDT 24
Finished Jul 06 07:17:52 PM PDT 24
Peak memory 217852 kb
Host smart-444a509e-b896-4d8d-800f-2462921a1a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48586637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.48586637
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.1894490739
Short name T511
Test name
Test status
Simulation time 506681741 ps
CPU time 13.49 seconds
Started Jul 06 07:17:46 PM PDT 24
Finished Jul 06 07:18:03 PM PDT 24
Peak memory 225592 kb
Host smart-0419c694-5c07-4e1a-a21c-124c4a473ee1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894490739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.1894490739
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.2162351128
Short name T243
Test name
Test status
Simulation time 462518337 ps
CPU time 18.14 seconds
Started Jul 06 07:17:46 PM PDT 24
Finished Jul 06 07:18:07 PM PDT 24
Peak memory 225552 kb
Host smart-7633648e-953a-4fe6-8b9a-305366088048
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162351128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.2162351128
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.1301235162
Short name T182
Test name
Test status
Simulation time 1020157977 ps
CPU time 9.91 seconds
Started Jul 06 07:17:47 PM PDT 24
Finished Jul 06 07:18:00 PM PDT 24
Peak memory 217736 kb
Host smart-4ef93486-8db4-41c0-88dc-7bddca24ba9e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301235162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
1301235162
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.211943109
Short name T223
Test name
Test status
Simulation time 176252132 ps
CPU time 8.41 seconds
Started Jul 06 07:17:45 PM PDT 24
Finished Jul 06 07:17:56 PM PDT 24
Peak memory 217860 kb
Host smart-0d2e4cd2-fcd4-4e97-bf49-2c5feb37e526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211943109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.211943109
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.3833929291
Short name T63
Test name
Test status
Simulation time 117039723 ps
CPU time 2.19 seconds
Started Jul 06 07:17:41 PM PDT 24
Finished Jul 06 07:17:43 PM PDT 24
Peak memory 217344 kb
Host smart-0cf91f04-1fbd-487c-b6bb-10f88691e75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833929291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.3833929291
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.3741149289
Short name T244
Test name
Test status
Simulation time 278232633 ps
CPU time 31.58 seconds
Started Jul 06 07:17:49 PM PDT 24
Finished Jul 06 07:18:23 PM PDT 24
Peak memory 250548 kb
Host smart-e06bbb84-6ad2-416e-9948-ef80d3767319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741149289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.3741149289
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.2809967892
Short name T327
Test name
Test status
Simulation time 114092743 ps
CPU time 6.54 seconds
Started Jul 06 07:17:46 PM PDT 24
Finished Jul 06 07:17:56 PM PDT 24
Peak memory 246716 kb
Host smart-6daee5c9-525a-484e-87be-f9e371228122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809967892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.2809967892
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.287513710
Short name T782
Test name
Test status
Simulation time 55881362235 ps
CPU time 181.71 seconds
Started Jul 06 07:18:18 PM PDT 24
Finished Jul 06 07:21:21 PM PDT 24
Peak memory 275172 kb
Host smart-1fff8c10-f1a0-434e-89d0-fc22825b9cd3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287513710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.287513710
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.2961232548
Short name T33
Test name
Test status
Simulation time 38496946 ps
CPU time 1.04 seconds
Started Jul 06 07:17:46 PM PDT 24
Finished Jul 06 07:17:50 PM PDT 24
Peak memory 212568 kb
Host smart-b150deda-f25c-47ec-a96f-bc250da318b1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961232548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.2961232548
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.3464472684
Short name T730
Test name
Test status
Simulation time 21439246 ps
CPU time 1.24 seconds
Started Jul 06 07:17:53 PM PDT 24
Finished Jul 06 07:17:56 PM PDT 24
Peak memory 208516 kb
Host smart-78f0f0cf-545f-4155-873f-6fb38dd2c1b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464472684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.3464472684
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.245021545
Short name T741
Test name
Test status
Simulation time 385493965 ps
CPU time 17.03 seconds
Started Jul 06 07:17:52 PM PDT 24
Finished Jul 06 07:18:11 PM PDT 24
Peak memory 225588 kb
Host smart-b86ed2f6-d666-43cc-804c-de12f7cb511c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245021545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.245021545
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.1633713803
Short name T794
Test name
Test status
Simulation time 149001012 ps
CPU time 4.52 seconds
Started Jul 06 07:17:54 PM PDT 24
Finished Jul 06 07:18:00 PM PDT 24
Peak memory 216752 kb
Host smart-1429039e-88f7-4cf0-b20e-9461276ee268
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633713803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.1633713803
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.2006912090
Short name T319
Test name
Test status
Simulation time 3857847537 ps
CPU time 50.54 seconds
Started Jul 06 07:17:54 PM PDT 24
Finished Jul 06 07:18:46 PM PDT 24
Peak memory 218432 kb
Host smart-14de8b4e-825c-43f8-aee4-7770c69d2116
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006912090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.2006912090
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1977318378
Short name T762
Test name
Test status
Simulation time 1920214052 ps
CPU time 24.84 seconds
Started Jul 06 07:17:52 PM PDT 24
Finished Jul 06 07:18:18 PM PDT 24
Peak memory 224868 kb
Host smart-8a623ce5-1120-4b89-9011-ed78a44eb763
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977318378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.1977318378
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.915754158
Short name T818
Test name
Test status
Simulation time 363106487 ps
CPU time 9.34 seconds
Started Jul 06 07:17:53 PM PDT 24
Finished Jul 06 07:18:04 PM PDT 24
Peak memory 217136 kb
Host smart-24e5ea7d-5d42-4ba2-952a-a948052ef233
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915754158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke.
915754158
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.3793529411
Short name T375
Test name
Test status
Simulation time 1268255317 ps
CPU time 31.07 seconds
Started Jul 06 07:17:53 PM PDT 24
Finished Jul 06 07:18:26 PM PDT 24
Peak memory 250460 kb
Host smart-6f390a58-8807-49cd-939a-9bfbcc53d6a8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793529411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.3793529411
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.3149304598
Short name T474
Test name
Test status
Simulation time 1587829832 ps
CPU time 8.16 seconds
Started Jul 06 07:17:55 PM PDT 24
Finished Jul 06 07:18:04 PM PDT 24
Peak memory 222588 kb
Host smart-9cd4059b-4bc1-4417-aa74-b7275416ece9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149304598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.3149304598
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.79381408
Short name T737
Test name
Test status
Simulation time 345013119 ps
CPU time 3.79 seconds
Started Jul 06 07:17:52 PM PDT 24
Finished Jul 06 07:17:58 PM PDT 24
Peak memory 217752 kb
Host smart-7cb50ef2-524e-44ff-bf79-2c0b0b3a3776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79381408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.79381408
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.3825215356
Short name T47
Test name
Test status
Simulation time 524575953 ps
CPU time 10.68 seconds
Started Jul 06 07:17:52 PM PDT 24
Finished Jul 06 07:18:04 PM PDT 24
Peak memory 225588 kb
Host smart-5b737c1b-6804-4549-8dda-1361339536ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825215356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.3825215356
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.56769184
Short name T380
Test name
Test status
Simulation time 648412855 ps
CPU time 14.21 seconds
Started Jul 06 07:17:55 PM PDT 24
Finished Jul 06 07:18:10 PM PDT 24
Peak memory 225516 kb
Host smart-807a9e77-4389-4cd9-a026-646fef67ff28
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56769184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_dig
est.56769184
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.2524654676
Short name T304
Test name
Test status
Simulation time 250121591 ps
CPU time 2.94 seconds
Started Jul 06 07:17:46 PM PDT 24
Finished Jul 06 07:17:53 PM PDT 24
Peak memory 214268 kb
Host smart-d0dc9e9f-06d6-4842-abfd-c9226c25f9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524654676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.2524654676
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.1754862546
Short name T855
Test name
Test status
Simulation time 707378308 ps
CPU time 34.47 seconds
Started Jul 06 07:17:47 PM PDT 24
Finished Jul 06 07:18:25 PM PDT 24
Peak memory 250544 kb
Host smart-b2a04dc3-1f75-46c3-933f-7c71fdd076de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754862546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.1754862546
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.3118730492
Short name T290
Test name
Test status
Simulation time 200434934 ps
CPU time 2.92 seconds
Started Jul 06 07:17:55 PM PDT 24
Finished Jul 06 07:17:59 PM PDT 24
Peak memory 221856 kb
Host smart-0b6fdd02-f9c2-4eda-9f97-5f3f158b8d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118730492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.3118730492
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.1648860918
Short name T830
Test name
Test status
Simulation time 15161011551 ps
CPU time 235.33 seconds
Started Jul 06 07:17:54 PM PDT 24
Finished Jul 06 07:21:50 PM PDT 24
Peak memory 250608 kb
Host smart-4b178134-8fad-4003-b51a-cba5929a9957
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648860918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.1648860918
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.3505022800
Short name T570
Test name
Test status
Simulation time 10743421 ps
CPU time 0.88 seconds
Started Jul 06 07:17:47 PM PDT 24
Finished Jul 06 07:17:51 PM PDT 24
Peak memory 207844 kb
Host smart-009eb852-264d-4999-b746-db185fccfd2f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505022800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.3505022800
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.937770886
Short name T107
Test name
Test status
Simulation time 182517119 ps
CPU time 0.91 seconds
Started Jul 06 07:18:02 PM PDT 24
Finished Jul 06 07:18:04 PM PDT 24
Peak memory 208560 kb
Host smart-8bf2be57-92b0-467b-a786-ce0a46059044
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937770886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.937770886
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.475152195
Short name T337
Test name
Test status
Simulation time 2320946308 ps
CPU time 14.67 seconds
Started Jul 06 07:18:03 PM PDT 24
Finished Jul 06 07:18:19 PM PDT 24
Peak memory 217840 kb
Host smart-fbcf375d-e919-4c4e-bbe0-4adf9523daa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475152195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.475152195
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.1517523993
Short name T311
Test name
Test status
Simulation time 2300501756 ps
CPU time 48.97 seconds
Started Jul 06 07:18:02 PM PDT 24
Finished Jul 06 07:18:53 PM PDT 24
Peak memory 218432 kb
Host smart-6f38f345-646e-46ca-950c-c53059e309a3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517523993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.1517523993
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.861992717
Short name T842
Test name
Test status
Simulation time 434386443 ps
CPU time 13.77 seconds
Started Jul 06 07:18:01 PM PDT 24
Finished Jul 06 07:18:16 PM PDT 24
Peak memory 217748 kb
Host smart-45f9693b-3731-4962-8a8d-bc898c367e97
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861992717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag
_prog_failure.861992717
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.1154236730
Short name T347
Test name
Test status
Simulation time 1676525413 ps
CPU time 9.88 seconds
Started Jul 06 07:18:01 PM PDT 24
Finished Jul 06 07:18:12 PM PDT 24
Peak memory 217112 kb
Host smart-43425b9b-eb9d-41f5-8679-23ba4107552e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154236730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.1154236730
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.633921905
Short name T574
Test name
Test status
Simulation time 10696591054 ps
CPU time 55.4 seconds
Started Jul 06 07:18:04 PM PDT 24
Finished Jul 06 07:19:01 PM PDT 24
Peak memory 283296 kb
Host smart-197cf6d4-ea80-4254-8da6-100205883bb9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633921905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_state_failure.633921905
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.4169558618
Short name T398
Test name
Test status
Simulation time 1754978069 ps
CPU time 15.74 seconds
Started Jul 06 07:18:03 PM PDT 24
Finished Jul 06 07:18:20 PM PDT 24
Peak memory 245904 kb
Host smart-40726c97-6e01-41f4-8638-2fc61ebccf51
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169558618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.4169558618
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.1534525850
Short name T588
Test name
Test status
Simulation time 151605777 ps
CPU time 1.53 seconds
Started Jul 06 07:18:01 PM PDT 24
Finished Jul 06 07:18:04 PM PDT 24
Peak memory 217788 kb
Host smart-c76145bd-2f5f-4664-8745-af6594e83827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534525850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.1534525850
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.370207045
Short name T390
Test name
Test status
Simulation time 348180125 ps
CPU time 10.94 seconds
Started Jul 06 07:18:01 PM PDT 24
Finished Jul 06 07:18:14 PM PDT 24
Peak memory 225588 kb
Host smart-f688ffa0-5347-4a78-a545-e7a054cd3a4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370207045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.370207045
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.3366724651
Short name T237
Test name
Test status
Simulation time 603407862 ps
CPU time 8.7 seconds
Started Jul 06 07:18:02 PM PDT 24
Finished Jul 06 07:18:12 PM PDT 24
Peak memory 217788 kb
Host smart-37eb39db-21b5-41e2-8d49-da03e4ac2e78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366724651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.3366724651
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.84178425
Short name T654
Test name
Test status
Simulation time 1656621222 ps
CPU time 10.9 seconds
Started Jul 06 07:18:01 PM PDT 24
Finished Jul 06 07:18:13 PM PDT 24
Peak memory 225460 kb
Host smart-3c48cedf-45d3-498d-b5f8-033db9433264
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84178425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.84178425
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.480429879
Short name T52
Test name
Test status
Simulation time 205548119 ps
CPU time 8.83 seconds
Started Jul 06 07:18:03 PM PDT 24
Finished Jul 06 07:18:13 PM PDT 24
Peak memory 225684 kb
Host smart-c5536db2-6b40-44cf-bbfc-6871e71cf184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480429879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.480429879
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.3622363347
Short name T656
Test name
Test status
Simulation time 284958338 ps
CPU time 1.97 seconds
Started Jul 06 07:17:54 PM PDT 24
Finished Jul 06 07:17:57 PM PDT 24
Peak memory 217212 kb
Host smart-960cc49f-4b08-4a17-8a33-e25c7dea4a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622363347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.3622363347
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.2183524839
Short name T863
Test name
Test status
Simulation time 1062122128 ps
CPU time 37.74 seconds
Started Jul 06 07:18:02 PM PDT 24
Finished Jul 06 07:18:41 PM PDT 24
Peak memory 250544 kb
Host smart-5b7a3303-c729-4f25-8ded-06b68f1106e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183524839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.2183524839
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.998170641
Short name T225
Test name
Test status
Simulation time 81048879 ps
CPU time 4.08 seconds
Started Jul 06 07:18:03 PM PDT 24
Finished Jul 06 07:18:09 PM PDT 24
Peak memory 222168 kb
Host smart-c29fa470-dfbb-4243-8831-a9043697570f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998170641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.998170641
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.1602723693
Short name T482
Test name
Test status
Simulation time 4490500556 ps
CPU time 115.3 seconds
Started Jul 06 07:18:07 PM PDT 24
Finished Jul 06 07:20:03 PM PDT 24
Peak memory 253940 kb
Host smart-936f8e5c-3a08-48a7-adf1-733f5f64ef69
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602723693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.1602723693
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.3483870180
Short name T813
Test name
Test status
Simulation time 29555777 ps
CPU time 0.75 seconds
Started Jul 06 07:17:59 PM PDT 24
Finished Jul 06 07:18:00 PM PDT 24
Peak memory 206696 kb
Host smart-6b209c7a-de76-40dc-8e53-a9703ce8f830
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483870180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.3483870180
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.335762563
Short name T401
Test name
Test status
Simulation time 74196569 ps
CPU time 0.9 seconds
Started Jul 06 07:18:08 PM PDT 24
Finished Jul 06 07:18:10 PM PDT 24
Peak memory 208516 kb
Host smart-575e0d68-3b99-49a0-82a1-37c5a51ee95a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335762563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.335762563
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.3709934175
Short name T442
Test name
Test status
Simulation time 567589862 ps
CPU time 11.87 seconds
Started Jul 06 07:18:02 PM PDT 24
Finished Jul 06 07:18:15 PM PDT 24
Peak memory 217760 kb
Host smart-c3a1ecd7-0eaa-450a-9c8a-25e68a8f467b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709934175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.3709934175
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.871770492
Short name T28
Test name
Test status
Simulation time 293370946 ps
CPU time 8.52 seconds
Started Jul 06 07:18:08 PM PDT 24
Finished Jul 06 07:18:18 PM PDT 24
Peak memory 216900 kb
Host smart-a72b0bfd-0592-41ae-bbbe-17d3ae2e80f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871770492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.871770492
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.2450981652
Short name T851
Test name
Test status
Simulation time 3487369312 ps
CPU time 27.52 seconds
Started Jul 06 07:18:14 PM PDT 24
Finished Jul 06 07:18:44 PM PDT 24
Peak memory 225520 kb
Host smart-a69341c1-a3ea-47a0-b70b-57490bd370b4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450981652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.2450981652
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.623576114
Short name T302
Test name
Test status
Simulation time 703371703 ps
CPU time 10.15 seconds
Started Jul 06 07:18:09 PM PDT 24
Finished Jul 06 07:18:20 PM PDT 24
Peak memory 217744 kb
Host smart-895b80a4-5dad-4b63-9122-f89377e24abf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623576114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag
_prog_failure.623576114
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.726741566
Short name T421
Test name
Test status
Simulation time 648050154 ps
CPU time 4.18 seconds
Started Jul 06 07:18:03 PM PDT 24
Finished Jul 06 07:18:08 PM PDT 24
Peak memory 217128 kb
Host smart-8e0ab0ea-590a-4035-927b-37e0d2fc77d5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726741566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke.
726741566
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.2013618823
Short name T793
Test name
Test status
Simulation time 1443290513 ps
CPU time 36.63 seconds
Started Jul 06 07:18:04 PM PDT 24
Finished Jul 06 07:18:42 PM PDT 24
Peak memory 276868 kb
Host smart-f3d74a61-5d46-4e90-8e9a-34fb81a7a48f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013618823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.2013618823
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.1057653553
Short name T504
Test name
Test status
Simulation time 416070788 ps
CPU time 19.57 seconds
Started Jul 06 07:18:00 PM PDT 24
Finished Jul 06 07:18:21 PM PDT 24
Peak memory 250464 kb
Host smart-52ca2f02-b2a9-482e-a006-9be8a5289d71
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057653553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.1057653553
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.3759889477
Short name T235
Test name
Test status
Simulation time 47074482 ps
CPU time 2.99 seconds
Started Jul 06 07:18:00 PM PDT 24
Finished Jul 06 07:18:05 PM PDT 24
Peak memory 221908 kb
Host smart-4723d971-9a4b-4596-8414-fadd2039a7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759889477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.3759889477
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.1897523154
Short name T444
Test name
Test status
Simulation time 1927190015 ps
CPU time 20.08 seconds
Started Jul 06 07:18:08 PM PDT 24
Finished Jul 06 07:18:29 PM PDT 24
Peak memory 218492 kb
Host smart-4f57ccd0-5d03-4378-a340-bb886306dbe7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897523154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.1897523154
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.4212770223
Short name T328
Test name
Test status
Simulation time 1939226417 ps
CPU time 13.44 seconds
Started Jul 06 07:18:07 PM PDT 24
Finished Jul 06 07:18:22 PM PDT 24
Peak memory 225536 kb
Host smart-9f2ca578-2a0b-4476-a2db-2f06cbeeff22
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212770223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.4212770223
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.509483674
Short name T864
Test name
Test status
Simulation time 6099018386 ps
CPU time 10.23 seconds
Started Jul 06 07:18:09 PM PDT 24
Finished Jul 06 07:18:21 PM PDT 24
Peak memory 217784 kb
Host smart-2ed06fe9-549d-4d9e-866f-442d1498de35
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509483674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.509483674
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.2016051679
Short name T455
Test name
Test status
Simulation time 350433894 ps
CPU time 14.07 seconds
Started Jul 06 07:18:01 PM PDT 24
Finished Jul 06 07:18:17 PM PDT 24
Peak memory 225580 kb
Host smart-668fccfa-fa07-4213-b837-f3d5aa2c891b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016051679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.2016051679
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.3025613473
Short name T558
Test name
Test status
Simulation time 63022892 ps
CPU time 2.1 seconds
Started Jul 06 07:18:01 PM PDT 24
Finished Jul 06 07:18:05 PM PDT 24
Peak memory 217216 kb
Host smart-306c7181-b674-424b-8e19-073471b6b290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025613473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.3025613473
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.3000417217
Short name T781
Test name
Test status
Simulation time 654207515 ps
CPU time 22.06 seconds
Started Jul 06 07:18:01 PM PDT 24
Finished Jul 06 07:18:25 PM PDT 24
Peak memory 250580 kb
Host smart-cc83f4fb-fe32-43ce-8578-39ab995d2a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000417217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.3000417217
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.213732413
Short name T266
Test name
Test status
Simulation time 282663578 ps
CPU time 8.41 seconds
Started Jul 06 07:18:01 PM PDT 24
Finished Jul 06 07:18:11 PM PDT 24
Peak memory 250548 kb
Host smart-86fd6741-8b97-4d90-b540-5499eb2a7896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213732413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.213732413
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.3415242568
Short name T40
Test name
Test status
Simulation time 3931615660 ps
CPU time 70.07 seconds
Started Jul 06 07:18:14 PM PDT 24
Finished Jul 06 07:19:26 PM PDT 24
Peak memory 250556 kb
Host smart-ffcf5351-bf7e-4764-80ca-1d257491b584
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415242568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.3415242568
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.3542075468
Short name T191
Test name
Test status
Simulation time 31600437661 ps
CPU time 441.72 seconds
Started Jul 06 07:18:09 PM PDT 24
Finished Jul 06 07:25:32 PM PDT 24
Peak memory 283588 kb
Host smart-560e941d-0f28-4aed-a64c-e087c226713f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3542075468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.3542075468
Directory /workspace/18.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.3730481446
Short name T70
Test name
Test status
Simulation time 74442093 ps
CPU time 1.03 seconds
Started Jul 06 07:18:03 PM PDT 24
Finished Jul 06 07:18:06 PM PDT 24
Peak memory 211432 kb
Host smart-e98a9222-e93c-427a-a399-ff971992d073
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730481446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.3730481446
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.1535812661
Short name T234
Test name
Test status
Simulation time 59568828 ps
CPU time 0.9 seconds
Started Jul 06 07:18:07 PM PDT 24
Finished Jul 06 07:18:09 PM PDT 24
Peak memory 208528 kb
Host smart-e6073266-ed53-487a-8406-53f8693f2966
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535812661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.1535812661
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.2459847692
Short name T281
Test name
Test status
Simulation time 1742399720 ps
CPU time 12.34 seconds
Started Jul 06 07:18:08 PM PDT 24
Finished Jul 06 07:18:22 PM PDT 24
Peak memory 217780 kb
Host smart-20c144bd-d3ab-4862-8441-8b6373a8155c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459847692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.2459847692
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.205535712
Short name T770
Test name
Test status
Simulation time 771291419 ps
CPU time 5.53 seconds
Started Jul 06 07:18:15 PM PDT 24
Finished Jul 06 07:18:22 PM PDT 24
Peak memory 216908 kb
Host smart-530c6068-e8a4-4ec4-b892-8513385aa68c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205535712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.205535712
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.427629577
Short name T396
Test name
Test status
Simulation time 2044676615 ps
CPU time 59.04 seconds
Started Jul 06 07:18:06 PM PDT 24
Finished Jul 06 07:19:07 PM PDT 24
Peak memory 217724 kb
Host smart-1b5d478b-9fef-4d6e-9f32-1c5feb02c586
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427629577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_er
rors.427629577
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.960117362
Short name T363
Test name
Test status
Simulation time 259074701 ps
CPU time 3.2 seconds
Started Jul 06 07:18:06 PM PDT 24
Finished Jul 06 07:18:10 PM PDT 24
Peak memory 217756 kb
Host smart-a65c0091-cfdc-4235-b519-c5c7dae668f1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960117362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag
_prog_failure.960117362
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.352963783
Short name T247
Test name
Test status
Simulation time 1516362619 ps
CPU time 8.91 seconds
Started Jul 06 07:18:04 PM PDT 24
Finished Jul 06 07:18:14 PM PDT 24
Peak memory 217096 kb
Host smart-787fad76-6e6a-4682-8d6f-e179d3d73b87
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352963783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke.
352963783
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.4234841946
Short name T846
Test name
Test status
Simulation time 2922192550 ps
CPU time 68.27 seconds
Started Jul 06 07:18:09 PM PDT 24
Finished Jul 06 07:19:19 PM PDT 24
Peak memory 269916 kb
Host smart-c287cb19-0a7c-45d4-930c-6f8ee0573033
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234841946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.4234841946
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.2441714287
Short name T492
Test name
Test status
Simulation time 1812699625 ps
CPU time 12.5 seconds
Started Jul 06 07:18:06 PM PDT 24
Finished Jul 06 07:18:19 PM PDT 24
Peak memory 250008 kb
Host smart-ab1732e1-a968-49ed-85a4-e59499386346
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441714287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.2441714287
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.4158189721
Short name T742
Test name
Test status
Simulation time 308066733 ps
CPU time 3.17 seconds
Started Jul 06 07:18:15 PM PDT 24
Finished Jul 06 07:18:20 PM PDT 24
Peak memory 217740 kb
Host smart-46d87817-5b28-40b2-9f3a-6fc11e7bc93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158189721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.4158189721
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.4077878286
Short name T691
Test name
Test status
Simulation time 526525229 ps
CPU time 12.02 seconds
Started Jul 06 07:18:08 PM PDT 24
Finished Jul 06 07:18:21 PM PDT 24
Peak memory 225508 kb
Host smart-87830d1c-2fb6-46fb-8e1a-067e231b2ddd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077878286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.4077878286
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.1415670843
Short name T382
Test name
Test status
Simulation time 328470906 ps
CPU time 7.14 seconds
Started Jul 06 07:18:10 PM PDT 24
Finished Jul 06 07:18:18 PM PDT 24
Peak memory 217708 kb
Host smart-d2c88f83-c2e9-4aa8-9baa-b8682882180b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415670843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
1415670843
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.2740828643
Short name T825
Test name
Test status
Simulation time 619835020 ps
CPU time 11.38 seconds
Started Jul 06 07:18:06 PM PDT 24
Finished Jul 06 07:18:18 PM PDT 24
Peak memory 225548 kb
Host smart-782c93cb-8f67-4af4-8154-bacc58c05dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740828643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.2740828643
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.4113286489
Short name T788
Test name
Test status
Simulation time 464176328 ps
CPU time 2.79 seconds
Started Jul 06 07:18:06 PM PDT 24
Finished Jul 06 07:18:09 PM PDT 24
Peak memory 217192 kb
Host smart-ca34f3fa-4ac3-4bf9-82ac-32e1f934995a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113286489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.4113286489
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.140811525
Short name T844
Test name
Test status
Simulation time 2350065074 ps
CPU time 17.43 seconds
Started Jul 06 07:18:09 PM PDT 24
Finished Jul 06 07:18:28 PM PDT 24
Peak memory 250616 kb
Host smart-fced03b5-2040-46bf-9cfd-df010c582fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140811525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.140811525
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.982895523
Short name T45
Test name
Test status
Simulation time 320206625 ps
CPU time 7.84 seconds
Started Jul 06 07:18:10 PM PDT 24
Finished Jul 06 07:18:19 PM PDT 24
Peak memory 250032 kb
Host smart-cc9ed991-bdcc-400b-ac58-b029b0910f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982895523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.982895523
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.1561545934
Short name T434
Test name
Test status
Simulation time 1739639777 ps
CPU time 26.67 seconds
Started Jul 06 07:18:16 PM PDT 24
Finished Jul 06 07:18:44 PM PDT 24
Peak memory 217168 kb
Host smart-f70e75e3-292c-4880-847a-fdd812e794cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561545934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.1561545934
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.4019401995
Short name T584
Test name
Test status
Simulation time 45258512 ps
CPU time 1.05 seconds
Started Jul 06 07:18:05 PM PDT 24
Finished Jul 06 07:18:07 PM PDT 24
Peak memory 211388 kb
Host smart-b853c65d-68be-4a1b-a18a-ed608ee3a3cc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019401995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.4019401995
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.746769314
Short name T628
Test name
Test status
Simulation time 29632930 ps
CPU time 1.11 seconds
Started Jul 06 07:16:00 PM PDT 24
Finished Jul 06 07:16:22 PM PDT 24
Peak memory 208528 kb
Host smart-da5f7a4f-1c0e-46af-ad3a-af00f1205058
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746769314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.746769314
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.1119369428
Short name T476
Test name
Test status
Simulation time 891912246 ps
CPU time 13.55 seconds
Started Jul 06 07:15:43 PM PDT 24
Finished Jul 06 07:16:30 PM PDT 24
Peak memory 217772 kb
Host smart-c255724e-5d46-4065-a88c-ebef0fc2e7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119369428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.1119369428
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.4171178105
Short name T707
Test name
Test status
Simulation time 155383771 ps
CPU time 1.54 seconds
Started Jul 06 07:16:00 PM PDT 24
Finished Jul 06 07:16:23 PM PDT 24
Peak memory 217204 kb
Host smart-13e231b3-3d12-403c-9baa-21a16869326c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171178105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.4171178105
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.1603948872
Short name T529
Test name
Test status
Simulation time 1170842534 ps
CPU time 16.99 seconds
Started Jul 06 07:15:54 PM PDT 24
Finished Jul 06 07:16:37 PM PDT 24
Peak memory 217156 kb
Host smart-cb8e1af0-229f-4d36-93c0-6a5495c72fc6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603948872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.1
603948872
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.4160375647
Short name T238
Test name
Test status
Simulation time 551973823 ps
CPU time 4.73 seconds
Started Jul 06 07:15:48 PM PDT 24
Finished Jul 06 07:16:23 PM PDT 24
Peak memory 217872 kb
Host smart-31fbe8ba-1d4b-4826-83ca-5c46995b124d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160375647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.4160375647
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.1771251907
Short name T149
Test name
Test status
Simulation time 1518199633 ps
CPU time 10.63 seconds
Started Jul 06 07:16:00 PM PDT 24
Finished Jul 06 07:16:31 PM PDT 24
Peak memory 217124 kb
Host smart-10feab77-c789-4654-b85c-5d43a2988db0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771251907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.1771251907
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.1961369243
Short name T71
Test name
Test status
Simulation time 412910355 ps
CPU time 11.41 seconds
Started Jul 06 07:15:49 PM PDT 24
Finished Jul 06 07:16:30 PM PDT 24
Peak memory 217104 kb
Host smart-5793ebba-05b6-4487-84b7-b08ebe266ba3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961369243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
1961369243
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.2660854118
Short name T642
Test name
Test status
Simulation time 3954435657 ps
CPU time 42.4 seconds
Started Jul 06 07:15:48 PM PDT 24
Finished Jul 06 07:17:01 PM PDT 24
Peak memory 250664 kb
Host smart-2f05cba2-3464-4c98-89e7-1661e2ad98b4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660854118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.2660854118
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.3883410482
Short name T4
Test name
Test status
Simulation time 526921320 ps
CPU time 14.55 seconds
Started Jul 06 07:15:48 PM PDT 24
Finished Jul 06 07:16:33 PM PDT 24
Peak memory 250460 kb
Host smart-29bf46b3-82a3-4453-ba14-c1d9fb8d5b03
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883410482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.3883410482
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.1853293244
Short name T267
Test name
Test status
Simulation time 116219102 ps
CPU time 4.01 seconds
Started Jul 06 07:15:42 PM PDT 24
Finished Jul 06 07:16:20 PM PDT 24
Peak memory 217780 kb
Host smart-b8a5f790-966c-4624-b2b0-098694ba06d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853293244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.1853293244
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.4078823364
Short name T195
Test name
Test status
Simulation time 281560469 ps
CPU time 10.87 seconds
Started Jul 06 07:15:43 PM PDT 24
Finished Jul 06 07:16:27 PM PDT 24
Peak memory 217188 kb
Host smart-50e5618a-5ee4-486c-a817-fa4cb11ba8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078823364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.4078823364
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.3554435062
Short name T57
Test name
Test status
Simulation time 1161145512 ps
CPU time 37.06 seconds
Started Jul 06 07:16:00 PM PDT 24
Finished Jul 06 07:16:58 PM PDT 24
Peak memory 281688 kb
Host smart-2251bddb-23ad-4cfb-99c6-f11d507cbedc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554435062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.3554435062
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.2353455581
Short name T461
Test name
Test status
Simulation time 219478892 ps
CPU time 11.03 seconds
Started Jul 06 07:15:53 PM PDT 24
Finished Jul 06 07:16:31 PM PDT 24
Peak memory 219456 kb
Host smart-9a6cead7-7817-4510-a10e-37f498d21e5f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353455581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.2353455581
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.2068264075
Short name T569
Test name
Test status
Simulation time 1428321766 ps
CPU time 15.09 seconds
Started Jul 06 07:15:53 PM PDT 24
Finished Jul 06 07:16:35 PM PDT 24
Peak memory 225524 kb
Host smart-260700a1-9342-4ab3-83fc-3093ccfea371
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068264075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.2068264075
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.2206398451
Short name T629
Test name
Test status
Simulation time 2804277416 ps
CPU time 12.06 seconds
Started Jul 06 07:16:01 PM PDT 24
Finished Jul 06 07:16:33 PM PDT 24
Peak memory 217788 kb
Host smart-610358d9-e86a-4f90-b247-b2cfaf18e3e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206398451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.2
206398451
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.1334052875
Short name T703
Test name
Test status
Simulation time 365893100 ps
CPU time 10.03 seconds
Started Jul 06 07:15:42 PM PDT 24
Finished Jul 06 07:16:26 PM PDT 24
Peak memory 225596 kb
Host smart-8b1b7985-d0fb-437b-b0e1-ca12f27bdb3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334052875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.1334052875
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.3833064965
Short name T273
Test name
Test status
Simulation time 408603944 ps
CPU time 3.49 seconds
Started Jul 06 07:15:36 PM PDT 24
Finished Jul 06 07:16:19 PM PDT 24
Peak memory 217220 kb
Host smart-c6141d66-7b6d-4b74-8d76-ea22ab8e0df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833064965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.3833064965
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.453422893
Short name T564
Test name
Test status
Simulation time 639401611 ps
CPU time 22.04 seconds
Started Jul 06 07:15:43 PM PDT 24
Finished Jul 06 07:16:39 PM PDT 24
Peak memory 250548 kb
Host smart-ae24dc0f-d3ea-47ca-a81f-51c698d12664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453422893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.453422893
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.1443846067
Short name T665
Test name
Test status
Simulation time 298014758 ps
CPU time 7.94 seconds
Started Jul 06 07:15:42 PM PDT 24
Finished Jul 06 07:16:24 PM PDT 24
Peak memory 250524 kb
Host smart-b9d1ad3b-03c0-41c8-9617-11136c2591d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443846067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.1443846067
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.3068157689
Short name T196
Test name
Test status
Simulation time 56299660016 ps
CPU time 484.8 seconds
Started Jul 06 07:15:54 PM PDT 24
Finished Jul 06 07:24:25 PM PDT 24
Peak memory 274320 kb
Host smart-8695af27-1f6e-4d6b-806b-e0e62cb3e882
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068157689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.3068157689
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.494660203
Short name T711
Test name
Test status
Simulation time 30785294 ps
CPU time 0.86 seconds
Started Jul 06 07:15:39 PM PDT 24
Finished Jul 06 07:16:17 PM PDT 24
Peak memory 208448 kb
Host smart-8e3519ef-d1ad-457f-81a4-f83895e05a5e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494660203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctr
l_volatile_unlock_smoke.494660203
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.447487750
Short name T172
Test name
Test status
Simulation time 36359533 ps
CPU time 0.91 seconds
Started Jul 06 07:18:14 PM PDT 24
Finished Jul 06 07:18:17 PM PDT 24
Peak memory 208520 kb
Host smart-7bb29d5b-a2ad-4df2-950c-49cc1722bdb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447487750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.447487750
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.3778830263
Short name T526
Test name
Test status
Simulation time 1465793828 ps
CPU time 17.35 seconds
Started Jul 06 07:18:13 PM PDT 24
Finished Jul 06 07:18:33 PM PDT 24
Peak memory 217756 kb
Host smart-11894a5e-9558-433f-b19b-b73cf47e151e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778830263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.3778830263
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.1808004739
Short name T432
Test name
Test status
Simulation time 216984985 ps
CPU time 4.05 seconds
Started Jul 06 07:18:13 PM PDT 24
Finished Jul 06 07:18:18 PM PDT 24
Peak memory 217216 kb
Host smart-ad0f0f8e-9087-4e5e-bb9e-d4aaf796563e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808004739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.1808004739
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.2978854141
Short name T685
Test name
Test status
Simulation time 62201847 ps
CPU time 2.45 seconds
Started Jul 06 07:18:13 PM PDT 24
Finished Jul 06 07:18:18 PM PDT 24
Peak memory 217876 kb
Host smart-8c5b0c5b-ec61-4517-ab55-68cfc9d1d20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978854141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.2978854141
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.2896862891
Short name T404
Test name
Test status
Simulation time 255021549 ps
CPU time 11.5 seconds
Started Jul 06 07:18:12 PM PDT 24
Finished Jul 06 07:18:25 PM PDT 24
Peak memory 218448 kb
Host smart-fea118aa-e891-430d-a084-00c2d5bdfdc1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896862891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.2896862891
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.1311209037
Short name T756
Test name
Test status
Simulation time 429406225 ps
CPU time 12.57 seconds
Started Jul 06 07:18:14 PM PDT 24
Finished Jul 06 07:18:28 PM PDT 24
Peak memory 225536 kb
Host smart-d956871b-f9c0-4eea-be68-ac0f1a66a471
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311209037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.1311209037
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.3457080270
Short name T454
Test name
Test status
Simulation time 201718742 ps
CPU time 7.98 seconds
Started Jul 06 07:18:15 PM PDT 24
Finished Jul 06 07:18:25 PM PDT 24
Peak memory 217688 kb
Host smart-da9c8b47-75fd-401c-b0c6-9199a227c6a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457080270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
3457080270
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.2010726567
Short name T726
Test name
Test status
Simulation time 700612453 ps
CPU time 7.65 seconds
Started Jul 06 07:18:13 PM PDT 24
Finished Jul 06 07:18:22 PM PDT 24
Peak memory 224512 kb
Host smart-31018318-bb92-4c87-ac23-096eab64a904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010726567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.2010726567
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.502564394
Short name T360
Test name
Test status
Simulation time 35534436 ps
CPU time 2.62 seconds
Started Jul 06 07:18:07 PM PDT 24
Finished Jul 06 07:18:11 PM PDT 24
Peak memory 214240 kb
Host smart-8006beb7-c0c6-467d-bbf4-8b8cfafd452a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502564394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.502564394
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.1286624613
Short name T736
Test name
Test status
Simulation time 486194663 ps
CPU time 35.37 seconds
Started Jul 06 07:18:14 PM PDT 24
Finished Jul 06 07:18:51 PM PDT 24
Peak memory 250624 kb
Host smart-db641679-ed45-4f11-a3b5-851038563127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286624613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.1286624613
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.2574795395
Short name T435
Test name
Test status
Simulation time 52223248 ps
CPU time 3.05 seconds
Started Jul 06 07:18:14 PM PDT 24
Finished Jul 06 07:18:19 PM PDT 24
Peak memory 221936 kb
Host smart-9a249c24-ae4e-4ffd-86ba-214fbf1e97f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574795395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.2574795395
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.910104337
Short name T298
Test name
Test status
Simulation time 12421507311 ps
CPU time 207.59 seconds
Started Jul 06 07:18:13 PM PDT 24
Finished Jul 06 07:21:42 PM PDT 24
Peak memory 250300 kb
Host smart-2f3cced7-51d5-44eb-bf49-5cc801ab6dd3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910104337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.910104337
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.3740677843
Short name T90
Test name
Test status
Simulation time 29936230 ps
CPU time 1.03 seconds
Started Jul 06 07:18:15 PM PDT 24
Finished Jul 06 07:18:17 PM PDT 24
Peak memory 217300 kb
Host smart-e537d16f-54a2-4ee0-adc0-6cc29084150f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740677843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.3740677843
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.1562714856
Short name T75
Test name
Test status
Simulation time 53137514 ps
CPU time 1.09 seconds
Started Jul 06 07:18:28 PM PDT 24
Finished Jul 06 07:18:30 PM PDT 24
Peak memory 208564 kb
Host smart-e0856ca9-2e5d-4c84-9272-83050cd4b64f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562714856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.1562714856
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.876779689
Short name T38
Test name
Test status
Simulation time 396172899 ps
CPU time 14.86 seconds
Started Jul 06 07:18:12 PM PDT 24
Finished Jul 06 07:18:28 PM PDT 24
Peak memory 217780 kb
Host smart-21bdc5a7-cf36-4d8f-8a9c-0cab5228e9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876779689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.876779689
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.3662418609
Short name T581
Test name
Test status
Simulation time 1460759245 ps
CPU time 17.66 seconds
Started Jul 06 07:18:22 PM PDT 24
Finished Jul 06 07:18:40 PM PDT 24
Peak memory 217220 kb
Host smart-1d1168b4-6634-4c2d-a200-95f1e13c388b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662418609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.3662418609
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.3142572118
Short name T392
Test name
Test status
Simulation time 85212511 ps
CPU time 4.31 seconds
Started Jul 06 07:18:15 PM PDT 24
Finished Jul 06 07:18:21 PM PDT 24
Peak memory 217800 kb
Host smart-a653cb66-419d-4d31-8d02-e6dc28b8f3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142572118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.3142572118
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.2938237608
Short name T552
Test name
Test status
Simulation time 246794234 ps
CPU time 9.28 seconds
Started Jul 06 07:18:18 PM PDT 24
Finished Jul 06 07:18:28 PM PDT 24
Peak memory 217696 kb
Host smart-bb44d886-b54c-4e44-b580-2cb91b280584
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938237608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.2938237608
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.2315847065
Short name T416
Test name
Test status
Simulation time 423335671 ps
CPU time 9.55 seconds
Started Jul 06 07:18:17 PM PDT 24
Finished Jul 06 07:18:27 PM PDT 24
Peak memory 217748 kb
Host smart-e72f2c0a-3529-4688-9e58-6182a44e47bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315847065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
2315847065
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.4053138797
Short name T548
Test name
Test status
Simulation time 337881289 ps
CPU time 7.31 seconds
Started Jul 06 07:18:19 PM PDT 24
Finished Jul 06 07:18:27 PM PDT 24
Peak memory 224752 kb
Host smart-5b3f7a05-9eba-44e9-b972-11bfb1e02204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053138797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.4053138797
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.158286718
Short name T826
Test name
Test status
Simulation time 142395359 ps
CPU time 2.49 seconds
Started Jul 06 07:18:12 PM PDT 24
Finished Jul 06 07:18:16 PM PDT 24
Peak memory 214008 kb
Host smart-8d6dddfb-4e9f-4c5c-aadb-9ba463068fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158286718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.158286718
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.1933058698
Short name T647
Test name
Test status
Simulation time 204055640 ps
CPU time 24.77 seconds
Started Jul 06 07:18:13 PM PDT 24
Finished Jul 06 07:18:40 PM PDT 24
Peak memory 250620 kb
Host smart-61a072ab-a8ab-417d-981f-48479120f05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933058698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.1933058698
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.2850196136
Short name T242
Test name
Test status
Simulation time 220567778 ps
CPU time 5.72 seconds
Started Jul 06 07:18:14 PM PDT 24
Finished Jul 06 07:18:21 PM PDT 24
Peak memory 246548 kb
Host smart-c7e07c74-6622-4032-9e41-c0068fe70476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850196136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.2850196136
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.1128989427
Short name T111
Test name
Test status
Simulation time 10327091556 ps
CPU time 97.63 seconds
Started Jul 06 07:18:27 PM PDT 24
Finished Jul 06 07:20:05 PM PDT 24
Peak memory 267308 kb
Host smart-4e79655a-0781-4a71-8ba4-7216f22396c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128989427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.1128989427
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.360368680
Short name T704
Test name
Test status
Simulation time 25645023116 ps
CPU time 1007.21 seconds
Started Jul 06 07:18:19 PM PDT 24
Finished Jul 06 07:35:07 PM PDT 24
Peak memory 269184 kb
Host smart-f5d5613d-3428-46ff-bade-29a16ca9ecad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=360368680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all_with_rand_reset.360368680
Directory /workspace/21.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.3995099201
Short name T805
Test name
Test status
Simulation time 10956588 ps
CPU time 0.91 seconds
Started Jul 06 07:18:13 PM PDT 24
Finished Jul 06 07:18:16 PM PDT 24
Peak memory 208192 kb
Host smart-65ebcc80-3257-4dbf-99a9-c356f65cd2ed
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995099201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.3995099201
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.257185242
Short name T331
Test name
Test status
Simulation time 35616004 ps
CPU time 0.94 seconds
Started Jul 06 07:18:28 PM PDT 24
Finished Jul 06 07:18:30 PM PDT 24
Peak memory 208448 kb
Host smart-c1942d4f-c24e-4fba-aafd-3cc8d2d309a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257185242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.257185242
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.3767141637
Short name T278
Test name
Test status
Simulation time 458089076 ps
CPU time 11.7 seconds
Started Jul 06 07:18:17 PM PDT 24
Finished Jul 06 07:18:30 PM PDT 24
Peak memory 217812 kb
Host smart-acc66301-e274-413c-bcbc-2083ade4c0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767141637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.3767141637
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.57489136
Short name T861
Test name
Test status
Simulation time 177386628 ps
CPU time 5.26 seconds
Started Jul 06 07:18:28 PM PDT 24
Finished Jul 06 07:18:34 PM PDT 24
Peak memory 217136 kb
Host smart-641d9dd8-6003-4b9f-8c01-34370d214b9c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57489136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.57489136
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.3957210528
Short name T489
Test name
Test status
Simulation time 61827141 ps
CPU time 3.37 seconds
Started Jul 06 07:18:17 PM PDT 24
Finished Jul 06 07:18:22 PM PDT 24
Peak memory 217740 kb
Host smart-11cea413-061a-4031-8e30-69acc26a9886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957210528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.3957210528
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.4139631488
Short name T227
Test name
Test status
Simulation time 1047491110 ps
CPU time 13.61 seconds
Started Jul 06 07:18:28 PM PDT 24
Finished Jul 06 07:18:42 PM PDT 24
Peak memory 217728 kb
Host smart-5e41135a-2827-46a8-a22f-6f65adb4f8f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139631488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.4139631488
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.2783911894
Short name T643
Test name
Test status
Simulation time 172928191 ps
CPU time 8.25 seconds
Started Jul 06 07:18:28 PM PDT 24
Finished Jul 06 07:18:37 PM PDT 24
Peak memory 225456 kb
Host smart-ea152f3f-822a-4948-90cc-bfe551ec0e8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783911894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.2783911894
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.164638182
Short name T456
Test name
Test status
Simulation time 1264268147 ps
CPU time 8.36 seconds
Started Jul 06 07:18:20 PM PDT 24
Finished Jul 06 07:18:29 PM PDT 24
Peak memory 225508 kb
Host smart-19df0943-96c5-43d4-8de7-27299e50df73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164638182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.164638182
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.2906429200
Short name T296
Test name
Test status
Simulation time 1017118388 ps
CPU time 8.08 seconds
Started Jul 06 07:18:19 PM PDT 24
Finished Jul 06 07:18:29 PM PDT 24
Peak memory 225596 kb
Host smart-2f54633c-670c-44bb-a500-93da53d43d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906429200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.2906429200
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.3511508529
Short name T669
Test name
Test status
Simulation time 44923987 ps
CPU time 1.24 seconds
Started Jul 06 07:18:19 PM PDT 24
Finished Jul 06 07:18:22 PM PDT 24
Peak memory 217208 kb
Host smart-e1dd3af1-2760-475e-8065-ea8a00bcdd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511508529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.3511508529
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.550915957
Short name T783
Test name
Test status
Simulation time 677973722 ps
CPU time 23.98 seconds
Started Jul 06 07:18:17 PM PDT 24
Finished Jul 06 07:18:43 PM PDT 24
Peak memory 250556 kb
Host smart-7d2bf1a6-8b0e-4be6-ab52-15d67295171d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550915957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.550915957
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.4278007045
Short name T104
Test name
Test status
Simulation time 350246393 ps
CPU time 6.81 seconds
Started Jul 06 07:18:19 PM PDT 24
Finished Jul 06 07:18:27 PM PDT 24
Peak memory 247104 kb
Host smart-72e3f51c-d94c-4c76-b065-5986f5394515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278007045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.4278007045
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.1304879607
Short name T94
Test name
Test status
Simulation time 4494461904 ps
CPU time 168.29 seconds
Started Jul 06 07:18:19 PM PDT 24
Finished Jul 06 07:21:09 PM PDT 24
Peak memory 279272 kb
Host smart-6a45f1a9-4e33-4151-b633-b0990e33e1d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304879607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.1304879607
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.3436199840
Short name T72
Test name
Test status
Simulation time 13568934 ps
CPU time 0.95 seconds
Started Jul 06 07:18:19 PM PDT 24
Finished Jul 06 07:18:22 PM PDT 24
Peak memory 211420 kb
Host smart-10801318-4d91-47a6-8cab-c1d712bda49e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436199840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.3436199840
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.4781080
Short name T622
Test name
Test status
Simulation time 17757988 ps
CPU time 1.14 seconds
Started Jul 06 07:18:24 PM PDT 24
Finished Jul 06 07:18:26 PM PDT 24
Peak memory 208560 kb
Host smart-9529f8cc-289b-4a5a-bae1-35281f701117
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4781080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.4781080
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.883887564
Short name T37
Test name
Test status
Simulation time 295491832 ps
CPU time 10.11 seconds
Started Jul 06 07:18:25 PM PDT 24
Finished Jul 06 07:18:36 PM PDT 24
Peak memory 217772 kb
Host smart-3c093aa5-66c1-48c2-b33a-1fba3f5a3d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883887564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.883887564
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.3701545932
Short name T681
Test name
Test status
Simulation time 371542137 ps
CPU time 2.39 seconds
Started Jul 06 07:18:24 PM PDT 24
Finished Jul 06 07:18:27 PM PDT 24
Peak memory 216636 kb
Host smart-d760f040-4a12-4e0f-92ba-1381f3d7c095
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701545932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.3701545932
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.616110926
Short name T680
Test name
Test status
Simulation time 83361806 ps
CPU time 3.09 seconds
Started Jul 06 07:18:25 PM PDT 24
Finished Jul 06 07:18:29 PM PDT 24
Peak memory 217788 kb
Host smart-d894bde9-ea86-4d7a-a352-9dbdd33e112e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616110926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.616110926
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.3404858815
Short name T551
Test name
Test status
Simulation time 224739706 ps
CPU time 10.52 seconds
Started Jul 06 07:18:25 PM PDT 24
Finished Jul 06 07:18:37 PM PDT 24
Peak memory 225600 kb
Host smart-cd189a50-5f71-4789-b7c6-255879c6b128
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404858815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.3404858815
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.498008798
Short name T763
Test name
Test status
Simulation time 2216738791 ps
CPU time 11.65 seconds
Started Jul 06 07:18:27 PM PDT 24
Finished Jul 06 07:18:39 PM PDT 24
Peak memory 225516 kb
Host smart-9307c31a-5215-4639-b629-215738e363e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498008798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_di
gest.498008798
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.2603102960
Short name T388
Test name
Test status
Simulation time 578393202 ps
CPU time 7.93 seconds
Started Jul 06 07:18:28 PM PDT 24
Finished Jul 06 07:18:36 PM PDT 24
Peak memory 217756 kb
Host smart-c4b80574-04e1-4a3d-bd77-6444ecc37efa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603102960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
2603102960
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.3099575661
Short name T44
Test name
Test status
Simulation time 2530265825 ps
CPU time 14.03 seconds
Started Jul 06 07:18:25 PM PDT 24
Finished Jul 06 07:18:40 PM PDT 24
Peak memory 217896 kb
Host smart-30fe5558-e05a-46d0-9b7d-b069cc6f4030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099575661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.3099575661
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.232601448
Short name T74
Test name
Test status
Simulation time 184804467 ps
CPU time 4.56 seconds
Started Jul 06 07:18:18 PM PDT 24
Finished Jul 06 07:18:24 PM PDT 24
Peak memory 217220 kb
Host smart-7880c7db-50d2-4995-8ac6-07270f6ca559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232601448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.232601448
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.1167494960
Short name T420
Test name
Test status
Simulation time 2335596679 ps
CPU time 24.86 seconds
Started Jul 06 07:18:29 PM PDT 24
Finished Jul 06 07:18:54 PM PDT 24
Peak memory 246624 kb
Host smart-585f812d-a088-41e0-b9c5-b3b525945dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167494960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.1167494960
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.3091069457
Short name T802
Test name
Test status
Simulation time 393907141 ps
CPU time 2.86 seconds
Started Jul 06 07:18:28 PM PDT 24
Finished Jul 06 07:18:32 PM PDT 24
Peak memory 222104 kb
Host smart-448854fc-f46a-4cca-a608-998b0ddec4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091069457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.3091069457
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.3383709831
Short name T828
Test name
Test status
Simulation time 9703151285 ps
CPU time 58.81 seconds
Started Jul 06 07:18:25 PM PDT 24
Finished Jul 06 07:19:25 PM PDT 24
Peak memory 250588 kb
Host smart-a3249db1-4a58-4895-9405-cdfd989bdf7a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383709831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.3383709831
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.2293371093
Short name T649
Test name
Test status
Simulation time 18110531 ps
CPU time 0.77 seconds
Started Jul 06 07:19:44 PM PDT 24
Finished Jul 06 07:19:45 PM PDT 24
Peak memory 208428 kb
Host smart-60a70056-873e-4395-8d54-627d294a656c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293371093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.2293371093
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.3771932260
Short name T263
Test name
Test status
Simulation time 30858196 ps
CPU time 1.03 seconds
Started Jul 06 07:18:33 PM PDT 24
Finished Jul 06 07:18:35 PM PDT 24
Peak memory 208620 kb
Host smart-ff6562c5-be1f-47f7-aa16-80847d48d208
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771932260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.3771932260
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.2929359593
Short name T627
Test name
Test status
Simulation time 174685797 ps
CPU time 5.25 seconds
Started Jul 06 07:18:30 PM PDT 24
Finished Jul 06 07:18:36 PM PDT 24
Peak memory 217208 kb
Host smart-f1644234-79d5-46d1-9f45-a8fb75660abb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929359593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.2929359593
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.3441519933
Short name T275
Test name
Test status
Simulation time 160556501 ps
CPU time 1.98 seconds
Started Jul 06 07:18:24 PM PDT 24
Finished Jul 06 07:18:27 PM PDT 24
Peak memory 221752 kb
Host smart-519953cf-a922-4199-9675-dc3024fdbe3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441519933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.3441519933
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.2143993008
Short name T448
Test name
Test status
Simulation time 446731153 ps
CPU time 16.23 seconds
Started Jul 06 07:18:37 PM PDT 24
Finished Jul 06 07:18:55 PM PDT 24
Peak memory 217780 kb
Host smart-ab462527-9b43-4fd5-9a16-0fd49f2f8a7c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143993008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.2143993008
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.493223723
Short name T317
Test name
Test status
Simulation time 605601533 ps
CPU time 12.96 seconds
Started Jul 06 07:18:32 PM PDT 24
Finished Jul 06 07:18:46 PM PDT 24
Peak memory 217712 kb
Host smart-2f91aeee-fd84-4e91-8a1e-49a2ee7c84c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493223723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_di
gest.493223723
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.1792215931
Short name T616
Test name
Test status
Simulation time 275069803 ps
CPU time 7.61 seconds
Started Jul 06 07:18:34 PM PDT 24
Finished Jul 06 07:18:42 PM PDT 24
Peak memory 217756 kb
Host smart-c7e09d6f-098f-4076-8e56-e62f1f15ad91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792215931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
1792215931
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.1273490850
Short name T542
Test name
Test status
Simulation time 992761560 ps
CPU time 10.29 seconds
Started Jul 06 07:18:26 PM PDT 24
Finished Jul 06 07:18:37 PM PDT 24
Peak memory 225568 kb
Host smart-26d8bee3-aecd-42a8-bb49-083a9da2a462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273490850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.1273490850
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.1181234779
Short name T389
Test name
Test status
Simulation time 476327952 ps
CPU time 7.44 seconds
Started Jul 06 07:18:25 PM PDT 24
Finished Jul 06 07:18:33 PM PDT 24
Peak memory 217296 kb
Host smart-84615e35-e7c6-4790-b45f-2d9feb984642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181234779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.1181234779
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.1670560423
Short name T325
Test name
Test status
Simulation time 1189436436 ps
CPU time 26.57 seconds
Started Jul 06 07:18:24 PM PDT 24
Finished Jul 06 07:18:52 PM PDT 24
Peak memory 250640 kb
Host smart-b4f8a6e0-9994-4acf-8e3a-4053d2c1cfe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670560423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.1670560423
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.3201665127
Short name T784
Test name
Test status
Simulation time 88959219 ps
CPU time 7.6 seconds
Started Jul 06 07:18:24 PM PDT 24
Finished Jul 06 07:18:33 PM PDT 24
Peak memory 244136 kb
Host smart-966c2264-27d1-4835-a69e-24dee14ccb21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201665127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.3201665127
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.3109911480
Short name T258
Test name
Test status
Simulation time 92702414996 ps
CPU time 360.29 seconds
Started Jul 06 07:18:31 PM PDT 24
Finished Jul 06 07:24:32 PM PDT 24
Peak memory 250576 kb
Host smart-755c6501-b139-46a9-87ed-e735795f805d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109911480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.3109911480
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.3440371191
Short name T155
Test name
Test status
Simulation time 95918906173 ps
CPU time 592.04 seconds
Started Jul 06 07:18:31 PM PDT 24
Finished Jul 06 07:28:24 PM PDT 24
Peak memory 463808 kb
Host smart-6842eeb4-1ea8-4da7-a4d5-d27e319a0998
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3440371191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all_with_rand_reset.3440371191
Directory /workspace/24.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.2207080627
Short name T579
Test name
Test status
Simulation time 13954849 ps
CPU time 0.97 seconds
Started Jul 06 07:18:26 PM PDT 24
Finished Jul 06 07:18:28 PM PDT 24
Peak memory 211316 kb
Host smart-f6ccfd96-9b92-4fcc-99f8-8457458b203f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207080627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.2207080627
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.858100273
Short name T572
Test name
Test status
Simulation time 19517668 ps
CPU time 1.16 seconds
Started Jul 06 07:18:32 PM PDT 24
Finished Jul 06 07:18:34 PM PDT 24
Peak memory 208520 kb
Host smart-108a598c-4402-4755-a1b9-8de2f027fd30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858100273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.858100273
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.3915877966
Short name T36
Test name
Test status
Simulation time 195509137 ps
CPU time 8.2 seconds
Started Jul 06 07:18:31 PM PDT 24
Finished Jul 06 07:18:40 PM PDT 24
Peak memory 217800 kb
Host smart-96e304cc-3280-4a8c-a0df-32e547c2476e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915877966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.3915877966
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.3318476342
Short name T473
Test name
Test status
Simulation time 5766188708 ps
CPU time 11.37 seconds
Started Jul 06 07:18:32 PM PDT 24
Finished Jul 06 07:18:45 PM PDT 24
Peak memory 217296 kb
Host smart-0d80c52b-5088-4c0e-b397-cdcd9c64bec0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318476342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.3318476342
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.1500128142
Short name T257
Test name
Test status
Simulation time 148060983 ps
CPU time 4.04 seconds
Started Jul 06 07:18:31 PM PDT 24
Finished Jul 06 07:18:36 PM PDT 24
Peak memory 217796 kb
Host smart-f24da7ca-e8be-439c-82de-a3c1ab4a116a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500128142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.1500128142
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.4072666574
Short name T640
Test name
Test status
Simulation time 350915479 ps
CPU time 11.4 seconds
Started Jul 06 07:18:31 PM PDT 24
Finished Jul 06 07:18:44 PM PDT 24
Peak memory 225528 kb
Host smart-2eabd37e-e900-4924-bb5e-11a469828422
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072666574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.4072666574
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.3418503116
Short name T175
Test name
Test status
Simulation time 524427464 ps
CPU time 10.64 seconds
Started Jul 06 07:18:31 PM PDT 24
Finished Jul 06 07:18:43 PM PDT 24
Peak memory 225492 kb
Host smart-f1a24b34-0a75-46d9-ad77-4eaa4dd69dc5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418503116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
3418503116
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.2756821558
Short name T566
Test name
Test status
Simulation time 4159466272 ps
CPU time 13.83 seconds
Started Jul 06 07:18:32 PM PDT 24
Finished Jul 06 07:18:47 PM PDT 24
Peak memory 225640 kb
Host smart-6469cf9c-f589-43f6-af41-effc066ea2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756821558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.2756821558
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.2075854253
Short name T609
Test name
Test status
Simulation time 32550697 ps
CPU time 2.67 seconds
Started Jul 06 07:18:30 PM PDT 24
Finished Jul 06 07:18:34 PM PDT 24
Peak memory 214176 kb
Host smart-ca889101-6ad5-4692-b1b5-f259e99d924a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075854253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.2075854253
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.3783110502
Short name T620
Test name
Test status
Simulation time 611539490 ps
CPU time 21.17 seconds
Started Jul 06 07:18:37 PM PDT 24
Finished Jul 06 07:18:59 PM PDT 24
Peak memory 250468 kb
Host smart-eb1dece8-eb66-46a2-a2e2-fe6ffc5ef304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783110502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.3783110502
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.4250880614
Short name T410
Test name
Test status
Simulation time 100597434 ps
CPU time 6.14 seconds
Started Jul 06 07:18:31 PM PDT 24
Finished Jul 06 07:18:39 PM PDT 24
Peak memory 246340 kb
Host smart-d0a2e6ab-f963-46cb-bee5-d48b6596cb33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250880614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.4250880614
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.2328415050
Short name T436
Test name
Test status
Simulation time 12554351299 ps
CPU time 127.64 seconds
Started Jul 06 07:18:30 PM PDT 24
Finished Jul 06 07:20:39 PM PDT 24
Peak memory 250620 kb
Host smart-bab10443-bedc-4083-a7e0-df38335f3f56
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328415050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.2328415050
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.2631073326
Short name T301
Test name
Test status
Simulation time 65059255 ps
CPU time 0.79 seconds
Started Jul 06 07:18:31 PM PDT 24
Finished Jul 06 07:18:33 PM PDT 24
Peak memory 208244 kb
Host smart-09b279b3-56be-4300-8a60-c56701c94b24
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631073326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.2631073326
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.1641767678
Short name T695
Test name
Test status
Simulation time 108387524 ps
CPU time 0.88 seconds
Started Jul 06 07:18:42 PM PDT 24
Finished Jul 06 07:18:43 PM PDT 24
Peak memory 208408 kb
Host smart-6ae15d3c-113d-40c9-8de3-5255d773c453
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641767678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.1641767678
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.368315665
Short name T468
Test name
Test status
Simulation time 993970847 ps
CPU time 12 seconds
Started Jul 06 07:18:38 PM PDT 24
Finished Jul 06 07:18:52 PM PDT 24
Peak memory 217760 kb
Host smart-9c491498-8dd2-48c7-90f6-c03638b3ad1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368315665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.368315665
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.3367595778
Short name T496
Test name
Test status
Simulation time 534172597 ps
CPU time 13.14 seconds
Started Jul 06 07:18:39 PM PDT 24
Finished Jul 06 07:18:53 PM PDT 24
Peak memory 217188 kb
Host smart-3a00b3ea-1859-401e-bb0c-e5e3a92117e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367595778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.3367595778
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.612501738
Short name T575
Test name
Test status
Simulation time 55206877 ps
CPU time 3.02 seconds
Started Jul 06 07:18:37 PM PDT 24
Finished Jul 06 07:18:42 PM PDT 24
Peak memory 221768 kb
Host smart-82908792-025f-4d2f-8f49-b0c322f37490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612501738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.612501738
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.349148534
Short name T159
Test name
Test status
Simulation time 282690860 ps
CPU time 14.66 seconds
Started Jul 06 07:18:39 PM PDT 24
Finished Jul 06 07:18:55 PM PDT 24
Peak memory 218432 kb
Host smart-615a9933-7f3d-406d-bae6-57f3a277db2f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349148534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.349148534
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.2978199858
Short name T186
Test name
Test status
Simulation time 1143064212 ps
CPU time 9.31 seconds
Started Jul 06 07:18:38 PM PDT 24
Finished Jul 06 07:18:48 PM PDT 24
Peak memory 225524 kb
Host smart-904571c9-69ce-47e6-85b9-91e72e5bb45c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978199858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.2978199858
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.1117676368
Short name T768
Test name
Test status
Simulation time 358314978 ps
CPU time 7.5 seconds
Started Jul 06 07:18:42 PM PDT 24
Finished Jul 06 07:18:50 PM PDT 24
Peak memory 217744 kb
Host smart-a95cd435-73ac-4d62-b053-a1dd579cf3d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117676368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
1117676368
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.1980229752
Short name T179
Test name
Test status
Simulation time 1502487262 ps
CPU time 9.8 seconds
Started Jul 06 07:18:37 PM PDT 24
Finished Jul 06 07:18:48 PM PDT 24
Peak memory 224652 kb
Host smart-b8b5d22e-c1c2-49c8-b86c-cc680fe3297d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980229752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.1980229752
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.1355543805
Short name T479
Test name
Test status
Simulation time 87054085 ps
CPU time 2.27 seconds
Started Jul 06 07:18:32 PM PDT 24
Finished Jul 06 07:18:35 PM PDT 24
Peak memory 213636 kb
Host smart-37ec8018-2a43-4ea3-9dc9-3491bc3b0f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355543805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.1355543805
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.3832900814
Short name T283
Test name
Test status
Simulation time 250654108 ps
CPU time 22 seconds
Started Jul 06 07:18:30 PM PDT 24
Finished Jul 06 07:18:53 PM PDT 24
Peak memory 250532 kb
Host smart-97f412c5-14e0-49e7-9fbd-4c74d98b15a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832900814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.3832900814
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.4019138840
Short name T366
Test name
Test status
Simulation time 61714473 ps
CPU time 8.21 seconds
Started Jul 06 07:18:37 PM PDT 24
Finished Jul 06 07:18:46 PM PDT 24
Peak memory 250504 kb
Host smart-8e8c2f03-c340-413a-b758-5a9b23b018e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019138840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.4019138840
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.3236686458
Short name T80
Test name
Test status
Simulation time 15451204164 ps
CPU time 135.09 seconds
Started Jul 06 07:18:40 PM PDT 24
Finished Jul 06 07:20:56 PM PDT 24
Peak memory 280192 kb
Host smart-eb08e73a-2a34-4db8-b4aa-9b284a9d9222
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236686458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.3236686458
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.279991382
Short name T99
Test name
Test status
Simulation time 6667791602 ps
CPU time 229.78 seconds
Started Jul 06 07:18:38 PM PDT 24
Finished Jul 06 07:22:29 PM PDT 24
Peak memory 447344 kb
Host smart-3c4df4cb-48c8-4478-9bcc-5c092cfe571f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=279991382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all_with_rand_reset.279991382
Directory /workspace/26.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.3085443338
Short name T852
Test name
Test status
Simulation time 15178143 ps
CPU time 1.02 seconds
Started Jul 06 07:18:30 PM PDT 24
Finished Jul 06 07:18:32 PM PDT 24
Peak memory 211396 kb
Host smart-a2efdaca-cb81-4e42-9245-14e860709ce6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085443338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.3085443338
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.3368583613
Short name T725
Test name
Test status
Simulation time 63475738 ps
CPU time 0.92 seconds
Started Jul 06 07:18:45 PM PDT 24
Finished Jul 06 07:18:47 PM PDT 24
Peak memory 208532 kb
Host smart-2288f85a-d457-4078-855d-99f6b68efa4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368583613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.3368583613
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.470231683
Short name T727
Test name
Test status
Simulation time 2394389460 ps
CPU time 19.39 seconds
Started Jul 06 07:18:37 PM PDT 24
Finished Jul 06 07:18:58 PM PDT 24
Peak memory 217844 kb
Host smart-c2c8cf21-4c86-4ffd-b6cb-c7c810fe9fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470231683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.470231683
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.3269850722
Short name T555
Test name
Test status
Simulation time 837484085 ps
CPU time 2.71 seconds
Started Jul 06 07:18:41 PM PDT 24
Finished Jul 06 07:18:45 PM PDT 24
Peak memory 216564 kb
Host smart-e29fd666-82ef-47e2-95da-cd58f2d02578
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269850722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.3269850722
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.3402037171
Short name T645
Test name
Test status
Simulation time 110525806 ps
CPU time 2.03 seconds
Started Jul 06 07:18:40 PM PDT 24
Finished Jul 06 07:18:43 PM PDT 24
Peak memory 221656 kb
Host smart-4f1bd192-7ab8-447a-8f36-c0a716e9f84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402037171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.3402037171
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.1312309926
Short name T554
Test name
Test status
Simulation time 1206164038 ps
CPU time 9.82 seconds
Started Jul 06 07:19:31 PM PDT 24
Finished Jul 06 07:19:42 PM PDT 24
Peak memory 225496 kb
Host smart-1cd9cdd2-eaa6-4cde-96ec-754a21bf442d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312309926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.1312309926
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.2273718007
Short name T772
Test name
Test status
Simulation time 728266654 ps
CPU time 13.68 seconds
Started Jul 06 07:18:38 PM PDT 24
Finished Jul 06 07:18:54 PM PDT 24
Peak memory 225504 kb
Host smart-953d1e4a-330d-4e1d-a8ef-4710db6b9651
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273718007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
2273718007
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.1094661241
Short name T835
Test name
Test status
Simulation time 416522014 ps
CPU time 7.16 seconds
Started Jul 06 07:18:37 PM PDT 24
Finished Jul 06 07:18:45 PM PDT 24
Peak memory 225568 kb
Host smart-b5794c21-d674-4fe1-8bd4-ecbdab6d3bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094661241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.1094661241
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.3150397181
Short name T79
Test name
Test status
Simulation time 259830425 ps
CPU time 2.38 seconds
Started Jul 06 07:18:41 PM PDT 24
Finished Jul 06 07:18:44 PM PDT 24
Peak memory 213880 kb
Host smart-dd04b2b6-b1dc-41d5-8514-3602525d5698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150397181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.3150397181
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.3551347336
Short name T269
Test name
Test status
Simulation time 291394748 ps
CPU time 26.22 seconds
Started Jul 06 07:18:38 PM PDT 24
Finished Jul 06 07:19:06 PM PDT 24
Peak memory 250504 kb
Host smart-ace3e794-167d-4356-8add-590011900b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551347336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.3551347336
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.1637481298
Short name T789
Test name
Test status
Simulation time 4912665483 ps
CPU time 159.61 seconds
Started Jul 06 07:18:36 PM PDT 24
Finished Jul 06 07:21:17 PM PDT 24
Peak memory 251004 kb
Host smart-6e492e1a-158c-4157-a258-c6c8df69e787
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637481298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.1637481298
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.4265354682
Short name T180
Test name
Test status
Simulation time 182087034862 ps
CPU time 1400.79 seconds
Started Jul 06 07:18:46 PM PDT 24
Finished Jul 06 07:42:08 PM PDT 24
Peak memory 375804 kb
Host smart-d69b9e79-87c2-4667-b880-b397abab8bd5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4265354682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all_with_rand_reset.4265354682
Directory /workspace/27.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.2919521656
Short name T358
Test name
Test status
Simulation time 165043256 ps
CPU time 0.8 seconds
Started Jul 06 07:18:37 PM PDT 24
Finished Jul 06 07:18:38 PM PDT 24
Peak memory 208248 kb
Host smart-fe559b8e-e690-4691-a4db-3260d923249a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919521656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.2919521656
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.2975466585
Short name T804
Test name
Test status
Simulation time 22687347 ps
CPU time 1.03 seconds
Started Jul 06 07:18:44 PM PDT 24
Finished Jul 06 07:18:46 PM PDT 24
Peak memory 208600 kb
Host smart-f0654da9-35e3-455a-acbc-d2a989cea6d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975466585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.2975466585
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.3063524348
Short name T399
Test name
Test status
Simulation time 231219477 ps
CPU time 9.26 seconds
Started Jul 06 07:18:48 PM PDT 24
Finished Jul 06 07:18:59 PM PDT 24
Peak memory 225536 kb
Host smart-47fa665c-7a7d-4d03-979b-e0632f83620e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063524348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.3063524348
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.3717369962
Short name T729
Test name
Test status
Simulation time 2002006901 ps
CPU time 5.68 seconds
Started Jul 06 07:18:48 PM PDT 24
Finished Jul 06 07:18:55 PM PDT 24
Peak memory 216836 kb
Host smart-4cc00cd8-a2fd-4e70-8b39-e5a134f5bf9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717369962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.3717369962
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.2950943036
Short name T163
Test name
Test status
Simulation time 184011199 ps
CPU time 4.53 seconds
Started Jul 06 07:18:46 PM PDT 24
Finished Jul 06 07:18:52 PM PDT 24
Peak memory 222324 kb
Host smart-ef271b3e-7aec-4440-b122-e944893c1ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950943036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.2950943036
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.1950890459
Short name T370
Test name
Test status
Simulation time 271072192 ps
CPU time 10.12 seconds
Started Jul 06 07:18:44 PM PDT 24
Finished Jul 06 07:18:56 PM PDT 24
Peak memory 219492 kb
Host smart-da12f2c3-9aa6-4d71-910c-eb5c5715cd3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950890459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.1950890459
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.85608426
Short name T611
Test name
Test status
Simulation time 377595673 ps
CPU time 7.94 seconds
Started Jul 06 07:18:48 PM PDT 24
Finished Jul 06 07:18:57 PM PDT 24
Peak memory 225496 kb
Host smart-aeebff7c-b897-44ab-b31d-77d699ed0134
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85608426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_dig
est.85608426
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.2859927386
Short name T675
Test name
Test status
Simulation time 355609956 ps
CPU time 12.71 seconds
Started Jul 06 07:18:46 PM PDT 24
Finished Jul 06 07:19:00 PM PDT 24
Peak memory 217744 kb
Host smart-c2a63983-aa1e-496d-867a-563897e47ebd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859927386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
2859927386
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.2545166835
Short name T539
Test name
Test status
Simulation time 1403645589 ps
CPU time 8.51 seconds
Started Jul 06 07:18:43 PM PDT 24
Finished Jul 06 07:18:53 PM PDT 24
Peak memory 224512 kb
Host smart-51c6605d-f621-40d4-805c-57a12a66cbf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545166835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.2545166835
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.4053420121
Short name T377
Test name
Test status
Simulation time 62178131 ps
CPU time 2.41 seconds
Started Jul 06 07:18:44 PM PDT 24
Finished Jul 06 07:18:48 PM PDT 24
Peak memory 217188 kb
Host smart-41e417b5-fd18-4a75-a74f-f1aa9d9927bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053420121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.4053420121
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.3912104371
Short name T64
Test name
Test status
Simulation time 179576698 ps
CPU time 24.4 seconds
Started Jul 06 07:18:44 PM PDT 24
Finished Jul 06 07:19:10 PM PDT 24
Peak memory 250492 kb
Host smart-4344bc35-9db9-4069-b980-189f16c5007c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912104371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.3912104371
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.3491852341
Short name T341
Test name
Test status
Simulation time 170683000 ps
CPU time 3.29 seconds
Started Jul 06 07:18:46 PM PDT 24
Finished Jul 06 07:18:51 PM PDT 24
Peak memory 221820 kb
Host smart-4d11c04b-9fa6-431f-a339-5f3245fa326e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491852341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.3491852341
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.3520559643
Short name T49
Test name
Test status
Simulation time 3513350189 ps
CPU time 96.38 seconds
Started Jul 06 07:18:47 PM PDT 24
Finished Jul 06 07:20:24 PM PDT 24
Peak memory 275276 kb
Host smart-5aec6001-a35b-4655-b048-c1e5db5b71ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520559643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.3520559643
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.2843561038
Short name T732
Test name
Test status
Simulation time 15028577 ps
CPU time 1.01 seconds
Started Jul 06 07:18:46 PM PDT 24
Finished Jul 06 07:18:48 PM PDT 24
Peak memory 208540 kb
Host smart-6648093e-6ff0-41da-bf57-2c00679ace18
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843561038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.2843561038
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.4013251718
Short name T417
Test name
Test status
Simulation time 42529340 ps
CPU time 1.26 seconds
Started Jul 06 07:18:55 PM PDT 24
Finished Jul 06 07:18:57 PM PDT 24
Peak memory 208640 kb
Host smart-59795ce3-be75-407c-8c6b-e87c8f3ccd9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013251718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.4013251718
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.2794278304
Short name T752
Test name
Test status
Simulation time 202745337 ps
CPU time 8.69 seconds
Started Jul 06 07:18:46 PM PDT 24
Finished Jul 06 07:18:56 PM PDT 24
Peak memory 217876 kb
Host smart-d101ba69-5d03-4f13-b9be-40b9219c6318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794278304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.2794278304
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.1801181315
Short name T8
Test name
Test status
Simulation time 1826367726 ps
CPU time 6.76 seconds
Started Jul 06 07:18:47 PM PDT 24
Finished Jul 06 07:18:55 PM PDT 24
Peak memory 217212 kb
Host smart-a99c9376-0110-41af-87b6-458d2b505326
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801181315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.1801181315
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.915387753
Short name T614
Test name
Test status
Simulation time 159083100 ps
CPU time 3.36 seconds
Started Jul 06 07:18:43 PM PDT 24
Finished Jul 06 07:18:48 PM PDT 24
Peak memory 221932 kb
Host smart-536a6c4f-0cdb-4c0c-94d7-25e789f89b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915387753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.915387753
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.959695861
Short name T310
Test name
Test status
Simulation time 565665678 ps
CPU time 14.97 seconds
Started Jul 06 07:18:49 PM PDT 24
Finished Jul 06 07:19:05 PM PDT 24
Peak memory 218532 kb
Host smart-de6da024-a27f-494a-8b72-b4890ba06ecf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959695861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.959695861
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.3258222669
Short name T509
Test name
Test status
Simulation time 460716662 ps
CPU time 8.07 seconds
Started Jul 06 07:18:52 PM PDT 24
Finished Jul 06 07:19:02 PM PDT 24
Peak memory 225524 kb
Host smart-cd1ddfc6-729f-4d53-b8ef-b51ee54bda10
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258222669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.3258222669
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.3732351276
Short name T383
Test name
Test status
Simulation time 1240559612 ps
CPU time 7.81 seconds
Started Jul 06 07:18:51 PM PDT 24
Finished Jul 06 07:19:00 PM PDT 24
Peak memory 217676 kb
Host smart-70782bd4-f7c7-46b4-8e18-5ceb907d0f53
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732351276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
3732351276
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.3467193987
Short name T799
Test name
Test status
Simulation time 255485184 ps
CPU time 9.62 seconds
Started Jul 06 07:18:44 PM PDT 24
Finished Jul 06 07:18:55 PM PDT 24
Peak memory 217860 kb
Host smart-575573a0-aa7d-4571-80aa-0a79381bed25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467193987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.3467193987
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.3057712843
Short name T387
Test name
Test status
Simulation time 205853883 ps
CPU time 12.02 seconds
Started Jul 06 07:18:47 PM PDT 24
Finished Jul 06 07:19:00 PM PDT 24
Peak memory 217200 kb
Host smart-38e02008-2378-492e-bc04-0734d8db3369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057712843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.3057712843
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.2217315084
Short name T599
Test name
Test status
Simulation time 199199603 ps
CPU time 14.27 seconds
Started Jul 06 07:18:46 PM PDT 24
Finished Jul 06 07:19:01 PM PDT 24
Peak memory 250540 kb
Host smart-1e715dd3-7091-42bf-a215-c2697e9ab55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217315084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.2217315084
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.3805809213
Short name T300
Test name
Test status
Simulation time 295894035 ps
CPU time 9.84 seconds
Started Jul 06 07:18:45 PM PDT 24
Finished Jul 06 07:18:56 PM PDT 24
Peak memory 250508 kb
Host smart-c08bc754-8a90-482a-8d15-8ee7cb83598d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805809213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.3805809213
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.2262805241
Short name T92
Test name
Test status
Simulation time 2785390842 ps
CPU time 52.97 seconds
Started Jul 06 07:18:52 PM PDT 24
Finished Jul 06 07:19:46 PM PDT 24
Peak memory 250988 kb
Host smart-5fff4d6c-8670-4128-976f-78c2f1728323
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262805241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.2262805241
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.3279568855
Short name T154
Test name
Test status
Simulation time 31886881737 ps
CPU time 546.63 seconds
Started Jul 06 07:18:51 PM PDT 24
Finished Jul 06 07:27:59 PM PDT 24
Peak memory 275336 kb
Host smart-b7eeed01-4e2f-4546-b2a4-4eb5458654d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3279568855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all_with_rand_reset.3279568855
Directory /workspace/29.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.2198885393
Short name T378
Test name
Test status
Simulation time 24329082 ps
CPU time 1.09 seconds
Started Jul 06 07:18:45 PM PDT 24
Finished Jul 06 07:18:47 PM PDT 24
Peak memory 211448 kb
Host smart-eaf7dfe9-1aef-4114-a934-30de714cee0a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198885393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.2198885393
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.1267872934
Short name T821
Test name
Test status
Simulation time 20667365 ps
CPU time 0.89 seconds
Started Jul 06 07:16:20 PM PDT 24
Finished Jul 06 07:16:26 PM PDT 24
Peak memory 208568 kb
Host smart-1105a50f-0e23-4112-974f-52101edb38ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267872934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.1267872934
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.3250939326
Short name T787
Test name
Test status
Simulation time 53753447 ps
CPU time 0.9 seconds
Started Jul 06 07:15:59 PM PDT 24
Finished Jul 06 07:16:22 PM PDT 24
Peak memory 208720 kb
Host smart-7c34d463-d1e7-46b4-a75c-429bcdf637b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250939326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.3250939326
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.1028572100
Short name T367
Test name
Test status
Simulation time 969545686 ps
CPU time 11.94 seconds
Started Jul 06 07:16:02 PM PDT 24
Finished Jul 06 07:16:33 PM PDT 24
Peak memory 225576 kb
Host smart-8562510b-8633-486d-85bd-cdd7b9488966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028572100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.1028572100
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.1098483918
Short name T630
Test name
Test status
Simulation time 434418972 ps
CPU time 2.73 seconds
Started Jul 06 07:16:07 PM PDT 24
Finished Jul 06 07:16:26 PM PDT 24
Peak memory 217192 kb
Host smart-065d219c-26a4-45d1-aad3-f24b5687bfa7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098483918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.1098483918
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.4257106736
Short name T187
Test name
Test status
Simulation time 7944892279 ps
CPU time 35.13 seconds
Started Jul 06 07:16:08 PM PDT 24
Finished Jul 06 07:16:58 PM PDT 24
Peak memory 218396 kb
Host smart-8401e426-a8f9-44bf-9d43-caf732300ee6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257106736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.4257106736
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.2032632076
Short name T185
Test name
Test status
Simulation time 2106558515 ps
CPU time 13.27 seconds
Started Jul 06 07:16:06 PM PDT 24
Finished Jul 06 07:16:36 PM PDT 24
Peak memory 217224 kb
Host smart-a9d817cf-b262-4d24-9b3c-b0aa621bf7e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032632076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.2
032632076
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.746625393
Short name T865
Test name
Test status
Simulation time 1478154096 ps
CPU time 13.38 seconds
Started Jul 06 07:16:06 PM PDT 24
Finished Jul 06 07:16:36 PM PDT 24
Peak memory 222848 kb
Host smart-d2cd0497-498f-41c2-a1e8-5e5353153c25
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746625393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_
prog_failure.746625393
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1545004181
Short name T82
Test name
Test status
Simulation time 3396977209 ps
CPU time 21.51 seconds
Started Jul 06 07:16:12 PM PDT 24
Finished Jul 06 07:16:46 PM PDT 24
Peak memory 217176 kb
Host smart-a12d16ae-c44a-43eb-b916-5a71ad7dcab0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545004181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.1545004181
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.1812019946
Short name T89
Test name
Test status
Simulation time 571657253 ps
CPU time 4.74 seconds
Started Jul 06 07:16:08 PM PDT 24
Finished Jul 06 07:16:28 PM PDT 24
Peak memory 217160 kb
Host smart-155422c5-a33e-44e6-9eb6-47446f83184b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812019946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
1812019946
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.1547766487
Short name T819
Test name
Test status
Simulation time 15798800837 ps
CPU time 67.69 seconds
Started Jul 06 07:16:08 PM PDT 24
Finished Jul 06 07:17:31 PM PDT 24
Peak memory 282892 kb
Host smart-15d089e4-e173-4dd3-b4d7-a75357626bb9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547766487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.1547766487
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.3563968818
Short name T431
Test name
Test status
Simulation time 7606912218 ps
CPU time 14.3 seconds
Started Jul 06 07:16:07 PM PDT 24
Finished Jul 06 07:16:37 PM PDT 24
Peak memory 225912 kb
Host smart-5328ecab-c57d-467a-a122-0de86cb79a4c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563968818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.3563968818
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.1068591874
Short name T854
Test name
Test status
Simulation time 67915817 ps
CPU time 2.98 seconds
Started Jul 06 07:15:53 PM PDT 24
Finished Jul 06 07:16:23 PM PDT 24
Peak memory 217756 kb
Host smart-df80f2d3-fe7b-4d3f-9ff5-240345848176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068591874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.1068591874
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.964329581
Short name T556
Test name
Test status
Simulation time 290817625 ps
CPU time 10.36 seconds
Started Jul 06 07:16:00 PM PDT 24
Finished Jul 06 07:16:31 PM PDT 24
Peak memory 217216 kb
Host smart-63eb3ceb-ed27-45cd-8703-17745231c869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964329581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.964329581
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.3383981410
Short name T55
Test name
Test status
Simulation time 124959900 ps
CPU time 27.62 seconds
Started Jul 06 07:16:21 PM PDT 24
Finished Jul 06 07:16:53 PM PDT 24
Peak memory 268256 kb
Host smart-dd50f667-e006-4728-8f88-a0c5121e76c9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383981410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.3383981410
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.4066605574
Short name T836
Test name
Test status
Simulation time 293819477 ps
CPU time 9.32 seconds
Started Jul 06 07:16:14 PM PDT 24
Finished Jul 06 07:16:34 PM PDT 24
Peak memory 218436 kb
Host smart-6e882072-2f26-499b-9094-2df9079af123
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066605574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.4066605574
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.3831345800
Short name T233
Test name
Test status
Simulation time 831097500 ps
CPU time 9.26 seconds
Started Jul 06 07:16:13 PM PDT 24
Finished Jul 06 07:16:33 PM PDT 24
Peak memory 225512 kb
Host smart-6e68218a-c325-46c8-991a-d85108b1d2b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831345800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.3831345800
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.709956481
Short name T646
Test name
Test status
Simulation time 688042511 ps
CPU time 13.45 seconds
Started Jul 06 07:16:12 PM PDT 24
Finished Jul 06 07:16:38 PM PDT 24
Peak memory 225528 kb
Host smart-8b15e48d-92b5-45df-aca1-c265d2b63874
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709956481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.709956481
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.2958017164
Short name T833
Test name
Test status
Simulation time 1426836666 ps
CPU time 8.08 seconds
Started Jul 06 07:16:00 PM PDT 24
Finished Jul 06 07:16:29 PM PDT 24
Peak memory 225596 kb
Host smart-9b1b8f90-efbf-4aae-807a-f417761f0a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958017164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.2958017164
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.844236017
Short name T60
Test name
Test status
Simulation time 159952043 ps
CPU time 1.9 seconds
Started Jul 06 07:15:55 PM PDT 24
Finished Jul 06 07:16:22 PM PDT 24
Peak memory 217192 kb
Host smart-aab09a83-44c0-4af8-b8a3-6321e715e671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844236017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.844236017
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.2969352131
Short name T385
Test name
Test status
Simulation time 219233856 ps
CPU time 27.8 seconds
Started Jul 06 07:15:53 PM PDT 24
Finished Jul 06 07:16:47 PM PDT 24
Peak memory 250520 kb
Host smart-37d0160f-5c11-44d4-bb65-bb2b481e25bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969352131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.2969352131
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.3990693615
Short name T333
Test name
Test status
Simulation time 80010067 ps
CPU time 10.83 seconds
Started Jul 06 07:15:54 PM PDT 24
Finished Jul 06 07:16:31 PM PDT 24
Peak memory 244896 kb
Host smart-2674a910-e653-47d5-9e52-e3f8730bd142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990693615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.3990693615
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.4116567755
Short name T419
Test name
Test status
Simulation time 5437522280 ps
CPU time 34.12 seconds
Started Jul 06 07:16:13 PM PDT 24
Finished Jul 06 07:16:58 PM PDT 24
Peak memory 225668 kb
Host smart-264cbcb0-3a22-4dbe-8dbd-e81c85b8cec3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116567755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.4116567755
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.103678879
Short name T156
Test name
Test status
Simulation time 28067034290 ps
CPU time 1007.87 seconds
Started Jul 06 07:16:20 PM PDT 24
Finished Jul 06 07:33:13 PM PDT 24
Peak memory 316120 kb
Host smart-34ff70a3-b929-4552-934f-3c7585c6f7a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=103678879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all_with_rand_reset.103678879
Directory /workspace/3.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.660680012
Short name T625
Test name
Test status
Simulation time 35702958 ps
CPU time 0.72 seconds
Started Jul 06 07:15:52 PM PDT 24
Finished Jul 06 07:16:20 PM PDT 24
Peak memory 206668 kb
Host smart-99491bda-f1b4-4ccb-a7d2-471bd35d32a9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660680012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctr
l_volatile_unlock_smoke.660680012
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.46056003
Short name T838
Test name
Test status
Simulation time 123635698 ps
CPU time 1.13 seconds
Started Jul 06 07:18:54 PM PDT 24
Finished Jul 06 07:18:56 PM PDT 24
Peak memory 208604 kb
Host smart-81c93703-58a8-43c8-914a-9ea31ed536a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46056003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.46056003
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.171932399
Short name T508
Test name
Test status
Simulation time 260621229 ps
CPU time 9.34 seconds
Started Jul 06 07:18:55 PM PDT 24
Finished Jul 06 07:19:05 PM PDT 24
Peak memory 217744 kb
Host smart-2f43b96a-fc81-4c11-a47b-233f8873a32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171932399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.171932399
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.3793572417
Short name T801
Test name
Test status
Simulation time 547460341 ps
CPU time 3.24 seconds
Started Jul 06 07:18:53 PM PDT 24
Finished Jul 06 07:18:58 PM PDT 24
Peak memory 217140 kb
Host smart-3c42e514-4f30-4837-b097-bf78781da7ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793572417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.3793572417
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.2562066912
Short name T501
Test name
Test status
Simulation time 78109079 ps
CPU time 2.28 seconds
Started Jul 06 07:18:50 PM PDT 24
Finished Jul 06 07:18:53 PM PDT 24
Peak memory 221660 kb
Host smart-044703e9-5eda-4a77-b794-825668c9d61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562066912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.2562066912
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.3751459963
Short name T339
Test name
Test status
Simulation time 1570025581 ps
CPU time 13.46 seconds
Started Jul 06 07:18:50 PM PDT 24
Finished Jul 06 07:19:05 PM PDT 24
Peak memory 219452 kb
Host smart-78a4b2bd-9ffe-4bb4-86a3-03926bf8a6a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751459963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.3751459963
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.3568025397
Short name T177
Test name
Test status
Simulation time 414995203 ps
CPU time 7.74 seconds
Started Jul 06 07:18:53 PM PDT 24
Finished Jul 06 07:19:03 PM PDT 24
Peak memory 225484 kb
Host smart-426d6c42-3227-4b09-a0eb-5bba5421cbc6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568025397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.3568025397
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.2354567115
Short name T766
Test name
Test status
Simulation time 712113246 ps
CPU time 12.63 seconds
Started Jul 06 07:18:51 PM PDT 24
Finished Jul 06 07:19:05 PM PDT 24
Peak memory 217724 kb
Host smart-ab4a7ada-a026-437d-9282-968bde9f36b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354567115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
2354567115
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.3497550830
Short name T606
Test name
Test status
Simulation time 528104330 ps
CPU time 13 seconds
Started Jul 06 07:18:51 PM PDT 24
Finished Jul 06 07:19:06 PM PDT 24
Peak memory 225528 kb
Host smart-860f14b4-2b75-4bfb-8011-dd4019336521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497550830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.3497550830
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.2662518127
Short name T713
Test name
Test status
Simulation time 280794288 ps
CPU time 3.5 seconds
Started Jul 06 07:18:51 PM PDT 24
Finished Jul 06 07:18:56 PM PDT 24
Peak memory 217184 kb
Host smart-38f6a1b5-b517-449f-bd77-d49b8982a4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662518127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.2662518127
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.284970475
Short name T774
Test name
Test status
Simulation time 938105350 ps
CPU time 21.44 seconds
Started Jul 06 07:18:51 PM PDT 24
Finished Jul 06 07:19:15 PM PDT 24
Peak memory 250616 kb
Host smart-6c6d83b0-0adf-4f12-9011-b8393a9558a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284970475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.284970475
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.3889350548
Short name T447
Test name
Test status
Simulation time 190831169 ps
CPU time 8.65 seconds
Started Jul 06 07:18:51 PM PDT 24
Finished Jul 06 07:19:01 PM PDT 24
Peak memory 250496 kb
Host smart-0caacd62-373c-446b-862b-0e132e7b8454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889350548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.3889350548
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.2341798941
Short name T61
Test name
Test status
Simulation time 91376647731 ps
CPU time 122.57 seconds
Started Jul 06 07:18:51 PM PDT 24
Finished Jul 06 07:20:55 PM PDT 24
Peak memory 270716 kb
Host smart-fee8b562-ff76-4d01-8473-b95672aa7df5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341798941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.2341798941
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.1681084011
Short name T88
Test name
Test status
Simulation time 44632730 ps
CPU time 0.99 seconds
Started Jul 06 07:18:51 PM PDT 24
Finished Jul 06 07:18:54 PM PDT 24
Peak memory 211388 kb
Host smart-2131597d-74a2-4c15-9c18-1191529337fe
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681084011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.1681084011
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.2703721767
Short name T466
Test name
Test status
Simulation time 76691698 ps
CPU time 1.07 seconds
Started Jul 06 07:18:58 PM PDT 24
Finished Jul 06 07:19:02 PM PDT 24
Peak memory 208496 kb
Host smart-90d41f1d-e1e4-47ad-a8b0-966d00518dcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703721767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.2703721767
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.825676684
Short name T376
Test name
Test status
Simulation time 243633023 ps
CPU time 11.05 seconds
Started Jul 06 07:18:53 PM PDT 24
Finished Jul 06 07:19:06 PM PDT 24
Peak memory 217780 kb
Host smart-aa6b527a-b264-45ed-8844-892292f073fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825676684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.825676684
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.2561726401
Short name T848
Test name
Test status
Simulation time 1224160164 ps
CPU time 7.89 seconds
Started Jul 06 07:18:59 PM PDT 24
Finished Jul 06 07:19:10 PM PDT 24
Peak memory 217148 kb
Host smart-daa091ea-f51a-44fb-8273-20014d5a00e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561726401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.2561726401
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.98660644
Short name T336
Test name
Test status
Simulation time 67987815 ps
CPU time 2.98 seconds
Started Jul 06 07:18:53 PM PDT 24
Finished Jul 06 07:18:57 PM PDT 24
Peak memory 217792 kb
Host smart-58d5250f-43ae-4624-8792-bac4964db850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98660644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.98660644
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.2957774720
Short name T452
Test name
Test status
Simulation time 724565127 ps
CPU time 19 seconds
Started Jul 06 07:18:59 PM PDT 24
Finished Jul 06 07:19:21 PM PDT 24
Peak memory 219412 kb
Host smart-cbf762c2-745b-4e2f-ac0e-0b332b573763
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957774720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.2957774720
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.2258562681
Short name T557
Test name
Test status
Simulation time 2035768036 ps
CPU time 10.77 seconds
Started Jul 06 07:18:59 PM PDT 24
Finished Jul 06 07:19:13 PM PDT 24
Peak memory 225300 kb
Host smart-164457ca-cc3a-4c91-8a5f-e7693b4d6914
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258562681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.2258562681
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.1675842774
Short name T699
Test name
Test status
Simulation time 288521123 ps
CPU time 7.23 seconds
Started Jul 06 07:19:01 PM PDT 24
Finished Jul 06 07:19:10 PM PDT 24
Peak memory 225532 kb
Host smart-3c722a3e-22a0-4a5d-a1da-04381e9261c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675842774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
1675842774
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.1682738190
Short name T697
Test name
Test status
Simulation time 1258101257 ps
CPU time 13.05 seconds
Started Jul 06 07:18:52 PM PDT 24
Finished Jul 06 07:19:07 PM PDT 24
Peak memory 225600 kb
Host smart-4272d2bb-e5e9-4478-8376-1677fbaa821b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682738190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.1682738190
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.743491356
Short name T228
Test name
Test status
Simulation time 21740087 ps
CPU time 1.51 seconds
Started Jul 06 07:18:53 PM PDT 24
Finished Jul 06 07:18:57 PM PDT 24
Peak memory 217224 kb
Host smart-92643427-0634-47cb-91c7-26a6914c2fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743491356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.743491356
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.735427733
Short name T712
Test name
Test status
Simulation time 317115343 ps
CPU time 22.39 seconds
Started Jul 06 07:18:52 PM PDT 24
Finished Jul 06 07:19:17 PM PDT 24
Peak memory 250508 kb
Host smart-72327820-3493-49ef-a44a-105b3e06fac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735427733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.735427733
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.2212613796
Short name T723
Test name
Test status
Simulation time 117852773 ps
CPU time 9.2 seconds
Started Jul 06 07:18:51 PM PDT 24
Finished Jul 06 07:19:02 PM PDT 24
Peak memory 250532 kb
Host smart-3aa688aa-5ee1-4cca-bf3f-cd3e7ddec526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212613796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.2212613796
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.982014147
Short name T803
Test name
Test status
Simulation time 1547665809 ps
CPU time 28.92 seconds
Started Jul 06 07:18:57 PM PDT 24
Finished Jul 06 07:19:28 PM PDT 24
Peak memory 227744 kb
Host smart-0188c6aa-8d40-49f5-98f0-6d2df69dc15a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982014147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.982014147
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.3305959828
Short name T740
Test name
Test status
Simulation time 81383293 ps
CPU time 0.92 seconds
Started Jul 06 07:18:50 PM PDT 24
Finished Jul 06 07:18:52 PM PDT 24
Peak memory 211420 kb
Host smart-a3d9a764-2532-4b14-9ce0-1faddaa804ad
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305959828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.3305959828
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.4090253447
Short name T437
Test name
Test status
Simulation time 89637368 ps
CPU time 1.54 seconds
Started Jul 06 07:18:57 PM PDT 24
Finished Jul 06 07:19:02 PM PDT 24
Peak memory 208520 kb
Host smart-78dc79ee-d9a6-495e-960b-40dc0a0d742a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090253447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.4090253447
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.991300512
Short name T165
Test name
Test status
Simulation time 1428960237 ps
CPU time 10.69 seconds
Started Jul 06 07:18:58 PM PDT 24
Finished Jul 06 07:19:12 PM PDT 24
Peak memory 217776 kb
Host smart-476b046c-9749-4cc9-9714-b0a5e88519de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991300512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.991300512
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.2556434754
Short name T24
Test name
Test status
Simulation time 262729829 ps
CPU time 7.26 seconds
Started Jul 06 07:18:57 PM PDT 24
Finished Jul 06 07:19:08 PM PDT 24
Peak memory 217172 kb
Host smart-b0b9887b-028d-40a1-b3cf-0bf6743e7b67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556434754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.2556434754
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.3396136638
Short name T486
Test name
Test status
Simulation time 74472756 ps
CPU time 1.62 seconds
Started Jul 06 07:18:59 PM PDT 24
Finished Jul 06 07:19:03 PM PDT 24
Peak memory 217796 kb
Host smart-e74dcb84-9398-442a-b380-35787c07ec24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396136638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.3396136638
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.951723645
Short name T359
Test name
Test status
Simulation time 342820402 ps
CPU time 15.12 seconds
Started Jul 06 07:18:59 PM PDT 24
Finished Jul 06 07:19:17 PM PDT 24
Peak memory 218448 kb
Host smart-80536a80-3992-48de-afd4-8333775b40e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951723645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.951723645
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.3889647413
Short name T728
Test name
Test status
Simulation time 921356092 ps
CPU time 11.76 seconds
Started Jul 06 07:18:59 PM PDT 24
Finished Jul 06 07:19:14 PM PDT 24
Peak memory 225524 kb
Host smart-f8140872-883e-41b3-8a2c-ad4d30d4b7f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889647413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.3889647413
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.3148098134
Short name T811
Test name
Test status
Simulation time 1829436296 ps
CPU time 13.22 seconds
Started Jul 06 07:18:56 PM PDT 24
Finished Jul 06 07:19:11 PM PDT 24
Peak memory 217760 kb
Host smart-e42bb130-c7ac-4ea5-8cc6-3fe9d7627cd6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148098134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
3148098134
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.2035007780
Short name T533
Test name
Test status
Simulation time 1683761320 ps
CPU time 11.1 seconds
Started Jul 06 07:18:59 PM PDT 24
Finished Jul 06 07:19:13 PM PDT 24
Peak memory 225248 kb
Host smart-c0f566aa-c548-4763-9e35-a6c9f6dbf316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035007780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.2035007780
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.3647388667
Short name T488
Test name
Test status
Simulation time 96280600 ps
CPU time 1.98 seconds
Started Jul 06 07:18:59 PM PDT 24
Finished Jul 06 07:19:04 PM PDT 24
Peak memory 213608 kb
Host smart-6b54702a-1c5f-4bd3-b407-261fce7c4134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647388667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.3647388667
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.4286934370
Short name T778
Test name
Test status
Simulation time 326538958 ps
CPU time 31.16 seconds
Started Jul 06 07:18:59 PM PDT 24
Finished Jul 06 07:19:34 PM PDT 24
Peak memory 250588 kb
Host smart-8d05f09e-f65d-42b3-91d2-af314e7010bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286934370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.4286934370
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.2470102212
Short name T538
Test name
Test status
Simulation time 462993725 ps
CPU time 7.32 seconds
Started Jul 06 07:18:56 PM PDT 24
Finished Jul 06 07:19:05 PM PDT 24
Peak memory 246480 kb
Host smart-1561162d-b329-4d55-868a-4df188b25672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470102212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.2470102212
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.3084251489
Short name T759
Test name
Test status
Simulation time 14595394808 ps
CPU time 106.56 seconds
Started Jul 06 07:18:58 PM PDT 24
Finished Jul 06 07:20:47 PM PDT 24
Peak memory 250372 kb
Host smart-88007df4-75eb-4148-bb7e-c21183b96677
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084251489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.3084251489
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.1686322863
Short name T368
Test name
Test status
Simulation time 30610910 ps
CPU time 0.95 seconds
Started Jul 06 07:19:00 PM PDT 24
Finished Jul 06 07:19:04 PM PDT 24
Peak memory 217224 kb
Host smart-dc20c266-4f80-4775-b8bb-6e9166660a25
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686322863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.1686322863
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.3126948181
Short name T248
Test name
Test status
Simulation time 69318829 ps
CPU time 1.16 seconds
Started Jul 06 07:19:06 PM PDT 24
Finished Jul 06 07:19:09 PM PDT 24
Peak memory 208552 kb
Host smart-40d60bb2-439d-4d79-9fe1-b2cbce95a644
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126948181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.3126948181
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.3878607950
Short name T458
Test name
Test status
Simulation time 293821069 ps
CPU time 13.52 seconds
Started Jul 06 07:18:57 PM PDT 24
Finished Jul 06 07:19:12 PM PDT 24
Peak memory 225588 kb
Host smart-cc2d28d5-ad13-46be-beef-08027f28c548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878607950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.3878607950
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.1975064742
Short name T837
Test name
Test status
Simulation time 431474086 ps
CPU time 6.3 seconds
Started Jul 06 07:18:57 PM PDT 24
Finished Jul 06 07:19:07 PM PDT 24
Peak memory 216964 kb
Host smart-2b551844-5237-4bc4-b635-54c85f004202
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975064742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.1975064742
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.642650326
Short name T573
Test name
Test status
Simulation time 50055350 ps
CPU time 2.57 seconds
Started Jul 06 07:18:57 PM PDT 24
Finished Jul 06 07:19:03 PM PDT 24
Peak memory 217760 kb
Host smart-239a8962-ea67-4576-9427-f3740ce6b640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642650326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.642650326
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.1232009680
Short name T322
Test name
Test status
Simulation time 275889823 ps
CPU time 13.63 seconds
Started Jul 06 07:18:58 PM PDT 24
Finished Jul 06 07:19:14 PM PDT 24
Peak memory 225540 kb
Host smart-2ea854dc-967b-4c0f-8b77-4665a49661c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232009680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.1232009680
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.3773150778
Short name T827
Test name
Test status
Simulation time 848962166 ps
CPU time 9.46 seconds
Started Jul 06 07:18:58 PM PDT 24
Finished Jul 06 07:19:11 PM PDT 24
Peak memory 217728 kb
Host smart-5f5dfaad-5b87-4372-8eb7-6d9a0362faeb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773150778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
3773150778
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.1547477462
Short name T481
Test name
Test status
Simulation time 629600050 ps
CPU time 12.53 seconds
Started Jul 06 07:18:59 PM PDT 24
Finished Jul 06 07:19:14 PM PDT 24
Peak memory 225572 kb
Host smart-5261f854-1942-4315-86d5-1a08e1a82b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547477462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.1547477462
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.1900134445
Short name T91
Test name
Test status
Simulation time 88902695 ps
CPU time 1.33 seconds
Started Jul 06 07:18:57 PM PDT 24
Finished Jul 06 07:19:00 PM PDT 24
Peak memory 213196 kb
Host smart-e1f21faa-8ebd-4adb-90fe-ac47e4402173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900134445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.1900134445
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.614750524
Short name T603
Test name
Test status
Simulation time 846979244 ps
CPU time 22.81 seconds
Started Jul 06 07:19:01 PM PDT 24
Finished Jul 06 07:19:26 PM PDT 24
Peak memory 250532 kb
Host smart-9276758a-e88a-478b-848d-a476604339d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614750524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.614750524
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.3390782071
Short name T663
Test name
Test status
Simulation time 101823497 ps
CPU time 9.98 seconds
Started Jul 06 07:18:59 PM PDT 24
Finished Jul 06 07:19:12 PM PDT 24
Peak memory 250544 kb
Host smart-52f9080c-1d32-4296-a0dd-65eacefc1d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390782071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.3390782071
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.1509125256
Short name T544
Test name
Test status
Simulation time 4336575302 ps
CPU time 94.12 seconds
Started Jul 06 07:18:58 PM PDT 24
Finished Jul 06 07:20:35 PM PDT 24
Peak memory 267180 kb
Host smart-7ed4e959-d8d1-4d9b-a2a6-249a5056a478
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509125256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.1509125256
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.3172679458
Short name T666
Test name
Test status
Simulation time 8932363327 ps
CPU time 224.44 seconds
Started Jul 06 07:18:57 PM PDT 24
Finished Jul 06 07:22:45 PM PDT 24
Peak memory 278488 kb
Host smart-4d5fcbe0-e267-4214-a703-fcddc2620227
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3172679458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.3172679458
Directory /workspace/33.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.489198324
Short name T34
Test name
Test status
Simulation time 32881903 ps
CPU time 0.92 seconds
Started Jul 06 07:18:59 PM PDT 24
Finished Jul 06 07:19:03 PM PDT 24
Peak memory 208652 kb
Host smart-b111446f-431d-4036-8990-2d5b109005be
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489198324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ct
rl_volatile_unlock_smoke.489198324
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.3254802554
Short name T78
Test name
Test status
Simulation time 17542538 ps
CPU time 0.96 seconds
Started Jul 06 07:19:03 PM PDT 24
Finished Jul 06 07:19:06 PM PDT 24
Peak memory 208496 kb
Host smart-aa2bda88-38e2-416f-8e71-4ef93a96dfa5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254802554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.3254802554
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.1259671419
Short name T288
Test name
Test status
Simulation time 6109664617 ps
CPU time 17.67 seconds
Started Jul 06 07:19:05 PM PDT 24
Finished Jul 06 07:19:24 PM PDT 24
Peak memory 218220 kb
Host smart-9e649791-2be1-43a1-82f8-1c8ae101ea10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259671419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.1259671419
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.132498198
Short name T19
Test name
Test status
Simulation time 394674095 ps
CPU time 3.33 seconds
Started Jul 06 07:19:05 PM PDT 24
Finished Jul 06 07:19:09 PM PDT 24
Peak memory 217220 kb
Host smart-4162a246-c879-4377-beda-366b841cd1ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132498198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.132498198
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.1006814439
Short name T708
Test name
Test status
Simulation time 109509819 ps
CPU time 3.42 seconds
Started Jul 06 07:19:04 PM PDT 24
Finished Jul 06 07:19:09 PM PDT 24
Peak memory 221904 kb
Host smart-74f5cef6-ead4-466a-a624-be60dbc309d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006814439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.1006814439
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.1141085861
Short name T425
Test name
Test status
Simulation time 2918238735 ps
CPU time 20.04 seconds
Started Jul 06 07:19:03 PM PDT 24
Finished Jul 06 07:19:25 PM PDT 24
Peak memory 219532 kb
Host smart-c97586a0-43c3-4de0-9cc3-d45d2ed65f42
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141085861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.1141085861
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.2272061311
Short name T776
Test name
Test status
Simulation time 897250653 ps
CPU time 17.59 seconds
Started Jul 06 07:19:06 PM PDT 24
Finished Jul 06 07:19:24 PM PDT 24
Peak memory 225516 kb
Host smart-cdc00307-8266-45ff-8374-ec34431bfeee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272061311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.2272061311
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.3112084180
Short name T324
Test name
Test status
Simulation time 1282519473 ps
CPU time 8.06 seconds
Started Jul 06 07:19:04 PM PDT 24
Finished Jul 06 07:19:13 PM PDT 24
Peak memory 217748 kb
Host smart-70abe736-3bb7-40e7-9f07-83e5ce293063
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112084180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
3112084180
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.3944468435
Short name T346
Test name
Test status
Simulation time 2494554236 ps
CPU time 12.64 seconds
Started Jul 06 07:19:06 PM PDT 24
Finished Jul 06 07:19:20 PM PDT 24
Peak memory 225664 kb
Host smart-27572cc5-11d4-4330-a0b6-3f675a9bc578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944468435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.3944468435
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.2393022240
Short name T429
Test name
Test status
Simulation time 59329394 ps
CPU time 1.5 seconds
Started Jul 06 07:19:03 PM PDT 24
Finished Jul 06 07:19:06 PM PDT 24
Peak memory 213300 kb
Host smart-ea350a92-72b5-46b1-8fab-27b0491b7502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393022240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.2393022240
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.2873840067
Short name T546
Test name
Test status
Simulation time 1130008653 ps
CPU time 21.87 seconds
Started Jul 06 07:19:04 PM PDT 24
Finished Jul 06 07:19:27 PM PDT 24
Peak memory 250500 kb
Host smart-6891578c-8ff4-40a1-854b-252214b1399d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873840067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.2873840067
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.3563639921
Short name T512
Test name
Test status
Simulation time 71545045 ps
CPU time 7.78 seconds
Started Jul 06 07:19:05 PM PDT 24
Finished Jul 06 07:19:14 PM PDT 24
Peak memory 250544 kb
Host smart-6725c3ce-f0d6-4b91-b437-2826bb0bdc63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563639921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.3563639921
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.3411735944
Short name T650
Test name
Test status
Simulation time 6108526366 ps
CPU time 63.91 seconds
Started Jul 06 07:19:03 PM PDT 24
Finished Jul 06 07:20:08 PM PDT 24
Peak memory 269848 kb
Host smart-08dcfb91-a71b-4dea-b843-fa1337ff5fec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411735944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.3411735944
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1962748636
Short name T451
Test name
Test status
Simulation time 217550343 ps
CPU time 0.78 seconds
Started Jul 06 07:19:03 PM PDT 24
Finished Jul 06 07:19:06 PM PDT 24
Peak memory 208252 kb
Host smart-016419d9-cd93-4b60-85f2-9de6f5abe619
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962748636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.1962748636
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.1069041236
Short name T76
Test name
Test status
Simulation time 112593463 ps
CPU time 1.17 seconds
Started Jul 06 07:19:10 PM PDT 24
Finished Jul 06 07:19:13 PM PDT 24
Peak memory 208544 kb
Host smart-7b16ab1e-9155-4967-9d36-118e3b149b5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069041236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.1069041236
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.3320318910
Short name T426
Test name
Test status
Simulation time 2443375658 ps
CPU time 18.73 seconds
Started Jul 06 07:19:03 PM PDT 24
Finished Jul 06 07:19:23 PM PDT 24
Peak memory 217864 kb
Host smart-b1e7a2e1-ada4-4a54-b13a-0c3f10cf274a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320318910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.3320318910
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.2333957617
Short name T23
Test name
Test status
Simulation time 1626202323 ps
CPU time 8.31 seconds
Started Jul 06 07:19:03 PM PDT 24
Finished Jul 06 07:19:12 PM PDT 24
Peak memory 217076 kb
Host smart-1757d9ec-383b-4fd7-b448-47ec5a578c8c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333957617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.2333957617
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.2143011791
Short name T268
Test name
Test status
Simulation time 379857447 ps
CPU time 4.39 seconds
Started Jul 06 07:19:05 PM PDT 24
Finished Jul 06 07:19:10 PM PDT 24
Peak memory 222204 kb
Host smart-70aa4a43-3ca7-4575-b642-1b5d179b817f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143011791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.2143011791
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.2255228460
Short name T655
Test name
Test status
Simulation time 896034303 ps
CPU time 12.74 seconds
Started Jul 06 07:19:07 PM PDT 24
Finished Jul 06 07:19:20 PM PDT 24
Peak memory 218448 kb
Host smart-9dbc8fdb-c9a1-4850-938d-9ee53a4008bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255228460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.2255228460
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.3988908772
Short name T189
Test name
Test status
Simulation time 244240663 ps
CPU time 11.27 seconds
Started Jul 06 07:19:09 PM PDT 24
Finished Jul 06 07:19:21 PM PDT 24
Peak memory 225516 kb
Host smart-f101e4c6-8eaa-45f7-bc9b-9f6deadd8149
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988908772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.3988908772
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.1433109198
Short name T406
Test name
Test status
Simulation time 961965594 ps
CPU time 6.81 seconds
Started Jul 06 07:19:05 PM PDT 24
Finished Jul 06 07:19:13 PM PDT 24
Peak memory 225544 kb
Host smart-afdd4cc7-1051-4ad4-a683-71edb8ce16cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433109198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
1433109198
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.3008597600
Short name T589
Test name
Test status
Simulation time 1434925570 ps
CPU time 13.46 seconds
Started Jul 06 07:19:05 PM PDT 24
Finished Jul 06 07:19:20 PM PDT 24
Peak memory 217868 kb
Host smart-92e888a4-72f2-429a-81e7-a462792fb6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008597600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.3008597600
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.2648566519
Short name T318
Test name
Test status
Simulation time 36232150 ps
CPU time 2.17 seconds
Started Jul 06 07:19:03 PM PDT 24
Finished Jul 06 07:19:07 PM PDT 24
Peak memory 217212 kb
Host smart-a16ea719-10ea-486c-826f-f7d42e1dbb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648566519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.2648566519
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.3384423844
Short name T464
Test name
Test status
Simulation time 205557932 ps
CPU time 23.56 seconds
Started Jul 06 07:19:03 PM PDT 24
Finished Jul 06 07:19:28 PM PDT 24
Peak memory 250432 kb
Host smart-0df2e634-8e0e-4eec-9650-82ad3d8f0b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384423844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.3384423844
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.2047143257
Short name T678
Test name
Test status
Simulation time 68640092 ps
CPU time 6.35 seconds
Started Jul 06 07:19:03 PM PDT 24
Finished Jul 06 07:19:10 PM PDT 24
Peak memory 246348 kb
Host smart-be53ce13-c4f5-4192-879d-a592fc49d848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047143257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.2047143257
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.3338856297
Short name T480
Test name
Test status
Simulation time 15877172239 ps
CPU time 143.63 seconds
Started Jul 06 07:19:11 PM PDT 24
Finished Jul 06 07:21:36 PM PDT 24
Peak memory 274404 kb
Host smart-d34ae462-3b76-4180-b7fc-1ab7dda09a75
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338856297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.3338856297
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.1941869304
Short name T598
Test name
Test status
Simulation time 49457466865 ps
CPU time 474.41 seconds
Started Jul 06 07:19:11 PM PDT 24
Finished Jul 06 07:27:07 PM PDT 24
Peak memory 283572 kb
Host smart-66f84430-7fa8-4a11-b3e2-314ee95c80f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1941869304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.1941869304
Directory /workspace/35.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.2465577774
Short name T670
Test name
Test status
Simulation time 194059594 ps
CPU time 0.89 seconds
Started Jul 06 07:19:06 PM PDT 24
Finished Jul 06 07:19:08 PM PDT 24
Peak memory 211448 kb
Host smart-3dad7407-d025-45bd-98c9-22c32bb9bf3d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465577774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.2465577774
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.1281698362
Short name T532
Test name
Test status
Simulation time 2739087481 ps
CPU time 13.81 seconds
Started Jul 06 07:19:10 PM PDT 24
Finished Jul 06 07:19:25 PM PDT 24
Peak memory 217868 kb
Host smart-a64c8c76-ad9f-44db-afb5-4956a86962f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281698362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.1281698362
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.258854296
Short name T817
Test name
Test status
Simulation time 2856097731 ps
CPU time 10.61 seconds
Started Jul 06 07:19:11 PM PDT 24
Finished Jul 06 07:19:23 PM PDT 24
Peak memory 217276 kb
Host smart-cf66ec1a-5491-440a-b408-5a6bc34618b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258854296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.258854296
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.2264441224
Short name T251
Test name
Test status
Simulation time 73264702 ps
CPU time 2.35 seconds
Started Jul 06 07:19:09 PM PDT 24
Finished Jul 06 07:19:12 PM PDT 24
Peak memory 217736 kb
Host smart-3cc866ef-7764-435b-81b4-4a22d4ae12e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264441224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.2264441224
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.484918609
Short name T758
Test name
Test status
Simulation time 1188668788 ps
CPU time 16.58 seconds
Started Jul 06 07:19:09 PM PDT 24
Finished Jul 06 07:19:26 PM PDT 24
Peak memory 218440 kb
Host smart-0c210360-804e-4840-938c-9d3267c5c78a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484918609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.484918609
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.3950237569
Short name T284
Test name
Test status
Simulation time 5955188973 ps
CPU time 11.65 seconds
Started Jul 06 07:19:10 PM PDT 24
Finished Jul 06 07:19:24 PM PDT 24
Peak memory 225600 kb
Host smart-15cec14b-2fd6-4d00-9548-8bd6b22d6128
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950237569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.3950237569
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.2832991071
Short name T494
Test name
Test status
Simulation time 614674566 ps
CPU time 20.08 seconds
Started Jul 06 07:19:10 PM PDT 24
Finished Jul 06 07:19:31 PM PDT 24
Peak memory 225504 kb
Host smart-b699c3fa-e0b5-45c4-b7b3-906ce5068ea2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832991071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
2832991071
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.1205844035
Short name T453
Test name
Test status
Simulation time 352363751 ps
CPU time 12.58 seconds
Started Jul 06 07:19:11 PM PDT 24
Finished Jul 06 07:19:25 PM PDT 24
Peak memory 225564 kb
Host smart-390ba230-67d5-451f-9e1b-1a1c00779928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205844035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.1205844035
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.281195171
Short name T709
Test name
Test status
Simulation time 280303654 ps
CPU time 1.43 seconds
Started Jul 06 07:19:10 PM PDT 24
Finished Jul 06 07:19:13 PM PDT 24
Peak memory 217296 kb
Host smart-42c92a22-21fd-4f2f-bf02-7856baea2c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281195171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.281195171
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.3328191931
Short name T659
Test name
Test status
Simulation time 514976603 ps
CPU time 28.15 seconds
Started Jul 06 07:19:11 PM PDT 24
Finished Jul 06 07:19:40 PM PDT 24
Peak memory 250556 kb
Host smart-d7bcaf15-e6fd-4027-a678-86d6c648ae1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328191931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.3328191931
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.1307676522
Short name T357
Test name
Test status
Simulation time 282231608 ps
CPU time 7.17 seconds
Started Jul 06 07:19:13 PM PDT 24
Finished Jul 06 07:19:21 PM PDT 24
Peak memory 246820 kb
Host smart-8cc54702-37a4-467c-a526-cf7e68009b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307676522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.1307676522
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.3327067983
Short name T470
Test name
Test status
Simulation time 28151822090 ps
CPU time 151.31 seconds
Started Jul 06 07:19:08 PM PDT 24
Finished Jul 06 07:21:40 PM PDT 24
Peak memory 219740 kb
Host smart-0b61a40e-5bd7-4f96-90b5-fdd269514211
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327067983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.3327067983
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.1377468821
Short name T571
Test name
Test status
Simulation time 44834584 ps
CPU time 1 seconds
Started Jul 06 07:19:10 PM PDT 24
Finished Jul 06 07:19:13 PM PDT 24
Peak memory 211500 kb
Host smart-71308616-2130-4eb0-8ffd-3392d6b09a29
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377468821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.1377468821
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.3442020257
Short name T10
Test name
Test status
Simulation time 17537723 ps
CPU time 1.12 seconds
Started Jul 06 07:19:18 PM PDT 24
Finished Jul 06 07:19:20 PM PDT 24
Peak memory 208516 kb
Host smart-9fe2e503-7d86-4146-a4ff-6150ebaefefd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442020257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.3442020257
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.2890327641
Short name T559
Test name
Test status
Simulation time 343058348 ps
CPU time 12.03 seconds
Started Jul 06 07:19:09 PM PDT 24
Finished Jul 06 07:19:23 PM PDT 24
Peak memory 217812 kb
Host smart-82b72314-101e-4b4e-ab9b-25e14001b6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890327641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.2890327641
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.387967320
Short name T638
Test name
Test status
Simulation time 801538221 ps
CPU time 8.95 seconds
Started Jul 06 07:19:17 PM PDT 24
Finished Jul 06 07:19:27 PM PDT 24
Peak memory 217176 kb
Host smart-609830db-1fdc-46f6-9ec6-1eabf6198419
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387967320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.387967320
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.3547443085
Short name T698
Test name
Test status
Simulation time 459520140 ps
CPU time 3.96 seconds
Started Jul 06 07:19:09 PM PDT 24
Finished Jul 06 07:19:14 PM PDT 24
Peak memory 217792 kb
Host smart-596c05f9-8630-4dc3-a42a-66dea184308f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547443085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.3547443085
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.2652875538
Short name T515
Test name
Test status
Simulation time 557864104 ps
CPU time 12.34 seconds
Started Jul 06 07:19:20 PM PDT 24
Finished Jul 06 07:19:33 PM PDT 24
Peak memory 218124 kb
Host smart-baa6483d-52e1-480b-aee7-b690ad37cf52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652875538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.2652875538
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.2689151642
Short name T386
Test name
Test status
Simulation time 1204985832 ps
CPU time 18.44 seconds
Started Jul 06 07:19:18 PM PDT 24
Finished Jul 06 07:19:38 PM PDT 24
Peak memory 225536 kb
Host smart-014fd81d-9d11-4ab6-ae2d-9f2d7cd461b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689151642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.2689151642
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.2223056864
Short name T531
Test name
Test status
Simulation time 7252321642 ps
CPU time 13.9 seconds
Started Jul 06 07:19:17 PM PDT 24
Finished Jul 06 07:19:32 PM PDT 24
Peak memory 217800 kb
Host smart-e1db5daf-0268-44e0-a205-001a8ca8aa11
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223056864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
2223056864
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.327402852
Short name T550
Test name
Test status
Simulation time 259195991 ps
CPU time 9.09 seconds
Started Jul 06 07:19:17 PM PDT 24
Finished Jul 06 07:19:27 PM PDT 24
Peak memory 217860 kb
Host smart-d723f929-25e0-442c-90eb-0b2fb8cdbdc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327402852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.327402852
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.981488378
Short name T724
Test name
Test status
Simulation time 593467036 ps
CPU time 3.3 seconds
Started Jul 06 07:19:09 PM PDT 24
Finished Jul 06 07:19:14 PM PDT 24
Peak memory 217200 kb
Host smart-f7174748-a202-493e-878b-3e2c31cd98fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981488378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.981488378
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.1739155980
Short name T785
Test name
Test status
Simulation time 384130228 ps
CPU time 32.2 seconds
Started Jul 06 07:19:20 PM PDT 24
Finished Jul 06 07:19:54 PM PDT 24
Peak memory 250520 kb
Host smart-fd26317d-7435-4253-b1d5-c000a358268e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739155980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.1739155980
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.3363287636
Short name T694
Test name
Test status
Simulation time 102291056 ps
CPU time 9.4 seconds
Started Jul 06 07:19:13 PM PDT 24
Finished Jul 06 07:19:24 PM PDT 24
Peak memory 250564 kb
Host smart-20837f9f-0959-4363-96ef-571c3fe611c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363287636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.3363287636
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.1275172680
Short name T623
Test name
Test status
Simulation time 10878216994 ps
CPU time 176.23 seconds
Started Jul 06 07:19:18 PM PDT 24
Finished Jul 06 07:22:15 PM PDT 24
Peak memory 283384 kb
Host smart-b76db567-2610-4d89-bf69-a82115f97974
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275172680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.1275172680
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.3260679690
Short name T167
Test name
Test status
Simulation time 180565040048 ps
CPU time 1136.72 seconds
Started Jul 06 07:19:16 PM PDT 24
Finished Jul 06 07:38:14 PM PDT 24
Peak memory 372540 kb
Host smart-bcbe98bd-bec0-4629-bc93-84ce64bb8188
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3260679690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.3260679690
Directory /workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.1231062415
Short name T692
Test name
Test status
Simulation time 12943479 ps
CPU time 0.81 seconds
Started Jul 06 07:19:09 PM PDT 24
Finished Jul 06 07:19:12 PM PDT 24
Peak memory 208384 kb
Host smart-539c8b07-d890-430e-bca1-96a99201b2a8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231062415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.1231062415
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.1446227707
Short name T11
Test name
Test status
Simulation time 23790376 ps
CPU time 0.97 seconds
Started Jul 06 07:19:19 PM PDT 24
Finished Jul 06 07:19:21 PM PDT 24
Peak memory 208548 kb
Host smart-1cafa36f-0d3b-4812-a0b3-c6d300c14696
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446227707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.1446227707
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.821000323
Short name T652
Test name
Test status
Simulation time 333374105 ps
CPU time 16.21 seconds
Started Jul 06 07:19:21 PM PDT 24
Finished Jul 06 07:19:38 PM PDT 24
Peak memory 217776 kb
Host smart-4d0f38ff-13c9-49fd-bc76-7cc11c3b6d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821000323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.821000323
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.3932151744
Short name T354
Test name
Test status
Simulation time 1864599067 ps
CPU time 6.14 seconds
Started Jul 06 07:19:16 PM PDT 24
Finished Jul 06 07:19:23 PM PDT 24
Peak memory 216908 kb
Host smart-f395ab8c-1136-4c12-a182-b5417087e58d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932151744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.3932151744
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.364655246
Short name T660
Test name
Test status
Simulation time 61802901 ps
CPU time 1.65 seconds
Started Jul 06 07:19:16 PM PDT 24
Finished Jul 06 07:19:19 PM PDT 24
Peak memory 217756 kb
Host smart-280c7b23-458d-476d-81b7-23bf2c158046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364655246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.364655246
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.2684445306
Short name T578
Test name
Test status
Simulation time 1357983996 ps
CPU time 13.61 seconds
Started Jul 06 07:19:18 PM PDT 24
Finished Jul 06 07:19:32 PM PDT 24
Peak memory 225584 kb
Host smart-666bbcd3-ee46-49dd-a6a2-df3f1134d9e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684445306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.2684445306
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.3742504707
Short name T41
Test name
Test status
Simulation time 374412683 ps
CPU time 11.43 seconds
Started Jul 06 07:19:19 PM PDT 24
Finished Jul 06 07:19:32 PM PDT 24
Peak memory 225536 kb
Host smart-d798cf8d-0dfb-407f-a63b-ca7d9ba481d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742504707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.3742504707
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.452360684
Short name T59
Test name
Test status
Simulation time 305286160 ps
CPU time 8.54 seconds
Started Jul 06 07:19:21 PM PDT 24
Finished Jul 06 07:19:31 PM PDT 24
Peak memory 217712 kb
Host smart-0dcb0ebc-ec8a-4c2d-9fee-aa17f842d5c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452360684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.452360684
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.1147713569
Short name T58
Test name
Test status
Simulation time 1752895672 ps
CPU time 10.65 seconds
Started Jul 06 07:19:17 PM PDT 24
Finished Jul 06 07:19:28 PM PDT 24
Peak memory 225588 kb
Host smart-c65b06ba-8e47-48f8-a2fb-9fa7f113eb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147713569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.1147713569
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.2350665518
Short name T641
Test name
Test status
Simulation time 77393900 ps
CPU time 1.33 seconds
Started Jul 06 07:19:18 PM PDT 24
Finished Jul 06 07:19:20 PM PDT 24
Peak memory 217188 kb
Host smart-7a00fb76-0968-4e8a-b5d6-c106daffce80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350665518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.2350665518
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.3599289704
Short name T305
Test name
Test status
Simulation time 222831271 ps
CPU time 27.44 seconds
Started Jul 06 07:19:20 PM PDT 24
Finished Jul 06 07:19:48 PM PDT 24
Peak memory 250560 kb
Host smart-90b7109c-2d8d-4898-83b1-f18ccb4f2529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599289704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.3599289704
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.3224402408
Short name T338
Test name
Test status
Simulation time 362067852 ps
CPU time 4.39 seconds
Started Jul 06 07:19:21 PM PDT 24
Finished Jul 06 07:19:26 PM PDT 24
Peak memory 222016 kb
Host smart-07e9e8c1-fe5b-4af0-b62c-fb293e90a190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224402408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.3224402408
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.4039716751
Short name T343
Test name
Test status
Simulation time 46617755897 ps
CPU time 292.52 seconds
Started Jul 06 07:19:19 PM PDT 24
Finished Jul 06 07:24:13 PM PDT 24
Peak memory 268932 kb
Host smart-ecbb8b7c-6572-4227-8c5c-9415635ceb1e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039716751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.4039716751
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.2132575311
Short name T400
Test name
Test status
Simulation time 43177740 ps
CPU time 0.89 seconds
Started Jul 06 07:19:17 PM PDT 24
Finished Jul 06 07:19:18 PM PDT 24
Peak memory 208680 kb
Host smart-da67d8b8-62e9-4a3c-8cda-0c3ba103e79c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132575311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.2132575311
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.1971225195
Short name T95
Test name
Test status
Simulation time 56868868 ps
CPU time 1 seconds
Started Jul 06 07:19:28 PM PDT 24
Finished Jul 06 07:19:29 PM PDT 24
Peak memory 208556 kb
Host smart-6de9d6f4-509e-44af-8d9c-c50c993a20b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971225195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.1971225195
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.432225138
Short name T541
Test name
Test status
Simulation time 2358703456 ps
CPU time 18.4 seconds
Started Jul 06 07:19:23 PM PDT 24
Finished Jul 06 07:19:43 PM PDT 24
Peak memory 217812 kb
Host smart-ff2c2f5d-ef52-4f21-b2b0-9c3e3f400d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432225138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.432225138
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.1389349452
Short name T467
Test name
Test status
Simulation time 508269308 ps
CPU time 6.45 seconds
Started Jul 06 07:19:24 PM PDT 24
Finished Jul 06 07:19:32 PM PDT 24
Peak memory 217216 kb
Host smart-3086ad58-2c5a-49d5-a56a-7181a3b78560
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389349452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.1389349452
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.2875109501
Short name T679
Test name
Test status
Simulation time 82484631 ps
CPU time 3.05 seconds
Started Jul 06 07:19:22 PM PDT 24
Finished Jul 06 07:19:27 PM PDT 24
Peak memory 217752 kb
Host smart-2986e98f-cdb4-4f82-a8d9-e0875ab8ffc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875109501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.2875109501
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.3324543889
Short name T800
Test name
Test status
Simulation time 1086802705 ps
CPU time 8.87 seconds
Started Jul 06 07:19:23 PM PDT 24
Finished Jul 06 07:19:33 PM PDT 24
Peak memory 217820 kb
Host smart-9adeec57-8b15-486f-9de6-5c28dbf1d18f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324543889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.3324543889
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.352188541
Short name T332
Test name
Test status
Simulation time 1699826010 ps
CPU time 17.77 seconds
Started Jul 06 07:19:23 PM PDT 24
Finished Jul 06 07:19:42 PM PDT 24
Peak memory 225452 kb
Host smart-605fdda6-2f48-429e-b772-ca94d1448a13
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352188541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_di
gest.352188541
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.2364189595
Short name T295
Test name
Test status
Simulation time 1001851879 ps
CPU time 11.9 seconds
Started Jul 06 07:19:24 PM PDT 24
Finished Jul 06 07:19:37 PM PDT 24
Peak memory 225536 kb
Host smart-02b03071-f041-4e5a-a1ab-99b4956ce799
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364189595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
2364189595
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.3413297145
Short name T806
Test name
Test status
Simulation time 602883893 ps
CPU time 13.17 seconds
Started Jul 06 07:19:23 PM PDT 24
Finished Jul 06 07:19:38 PM PDT 24
Peak memory 225592 kb
Host smart-28c37c8c-7354-4080-b385-fb08fc88d965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413297145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.3413297145
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.1303218679
Short name T361
Test name
Test status
Simulation time 161450731 ps
CPU time 1.89 seconds
Started Jul 06 07:19:18 PM PDT 24
Finished Jul 06 07:19:21 PM PDT 24
Peak memory 217184 kb
Host smart-6bf22556-d929-4e43-910b-6c5e6b1f418e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303218679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.1303218679
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.631344340
Short name T522
Test name
Test status
Simulation time 344981762 ps
CPU time 31.87 seconds
Started Jul 06 07:19:22 PM PDT 24
Finished Jul 06 07:19:55 PM PDT 24
Peak memory 250528 kb
Host smart-a964373a-7410-4a38-b880-9334b75b31b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631344340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.631344340
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.713353490
Short name T812
Test name
Test status
Simulation time 66656615 ps
CPU time 7.14 seconds
Started Jul 06 07:19:28 PM PDT 24
Finished Jul 06 07:19:36 PM PDT 24
Peak memory 246652 kb
Host smart-afd0cbd3-b649-41e6-831b-d4e86682ce34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713353490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.713353490
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.1571416121
Short name T503
Test name
Test status
Simulation time 11915995070 ps
CPU time 203.37 seconds
Started Jul 06 07:19:21 PM PDT 24
Finished Jul 06 07:22:46 PM PDT 24
Peak memory 225628 kb
Host smart-333989a1-e0af-4306-b504-6ba835d30aaf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571416121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.1571416121
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.1442375582
Short name T158
Test name
Test status
Simulation time 96058411106 ps
CPU time 566.64 seconds
Started Jul 06 07:19:22 PM PDT 24
Finished Jul 06 07:28:50 PM PDT 24
Peak memory 372584 kb
Host smart-8452c907-fc59-48ce-825f-ffa11d5091f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1442375582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.1442375582
Directory /workspace/39.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.234809637
Short name T253
Test name
Test status
Simulation time 18968688 ps
CPU time 0.81 seconds
Started Jul 06 07:19:19 PM PDT 24
Finished Jul 06 07:19:21 PM PDT 24
Peak memory 208528 kb
Host smart-c9ef9e02-f7f5-4652-9676-a87f9ffe1fee
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234809637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ct
rl_volatile_unlock_smoke.234809637
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.1058053441
Short name T860
Test name
Test status
Simulation time 17630006 ps
CPU time 1.07 seconds
Started Jul 06 07:16:37 PM PDT 24
Finished Jul 06 07:16:39 PM PDT 24
Peak memory 208756 kb
Host smart-990b2150-98a8-4d50-a67b-d28bdd45ef7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058053441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.1058053441
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.4264040922
Short name T103
Test name
Test status
Simulation time 42621279 ps
CPU time 0.79 seconds
Started Jul 06 07:16:23 PM PDT 24
Finished Jul 06 07:16:27 PM PDT 24
Peak memory 208512 kb
Host smart-3d869ebd-b77d-4a64-b568-48eb999d6606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264040922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.4264040922
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.1807704958
Short name T285
Test name
Test status
Simulation time 316250893 ps
CPU time 15.78 seconds
Started Jul 06 07:16:21 PM PDT 24
Finished Jul 06 07:16:41 PM PDT 24
Peak memory 217808 kb
Host smart-89621c26-6c6c-48db-b168-36bcadad1f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807704958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.1807704958
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.1940073141
Short name T624
Test name
Test status
Simulation time 312067665 ps
CPU time 7.18 seconds
Started Jul 06 07:16:30 PM PDT 24
Finished Jul 06 07:16:38 PM PDT 24
Peak memory 217036 kb
Host smart-61aebf7f-d501-4a9d-a502-17e18ce04f89
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940073141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.1940073141
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.1650564291
Short name T350
Test name
Test status
Simulation time 11044993813 ps
CPU time 28.46 seconds
Started Jul 06 07:16:26 PM PDT 24
Finished Jul 06 07:16:56 PM PDT 24
Peak memory 217780 kb
Host smart-7b2fadf0-b76f-4bc4-a017-a60380066752
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650564291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.1650564291
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.426211430
Short name T751
Test name
Test status
Simulation time 10560676041 ps
CPU time 59.37 seconds
Started Jul 06 07:16:35 PM PDT 24
Finished Jul 06 07:17:36 PM PDT 24
Peak memory 217348 kb
Host smart-add9d9bb-84d3-439b-a0ff-3a86f2be4e72
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426211430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.426211430
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.164662555
Short name T462
Test name
Test status
Simulation time 771548700 ps
CPU time 9.97 seconds
Started Jul 06 07:16:26 PM PDT 24
Finished Jul 06 07:16:37 PM PDT 24
Peak memory 224788 kb
Host smart-34cc62a1-3b9c-4db1-91f2-b7d4129ec02c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164662555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_
prog_failure.164662555
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.2701968598
Short name T106
Test name
Test status
Simulation time 1492324994 ps
CPU time 39.52 seconds
Started Jul 06 07:16:37 PM PDT 24
Finished Jul 06 07:17:18 PM PDT 24
Peak memory 217388 kb
Host smart-4a1f5394-9d98-4efd-8c9f-907630cba0be
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701968598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.2701968598
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.2246366439
Short name T256
Test name
Test status
Simulation time 213648787 ps
CPU time 4.26 seconds
Started Jul 06 07:16:25 PM PDT 24
Finished Jul 06 07:16:31 PM PDT 24
Peak memory 217160 kb
Host smart-2a333211-d47c-4689-841e-2ca1e4789037
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246366439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
2246366439
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.115018989
Short name T593
Test name
Test status
Simulation time 3089048632 ps
CPU time 85.09 seconds
Started Jul 06 07:16:24 PM PDT 24
Finished Jul 06 07:17:52 PM PDT 24
Peak memory 278952 kb
Host smart-a6f15933-b3e7-41fc-af17-ec7e5b751d6b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115018989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_state_failure.115018989
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.805517333
Short name T757
Test name
Test status
Simulation time 1972432791 ps
CPU time 14.53 seconds
Started Jul 06 07:16:30 PM PDT 24
Finished Jul 06 07:16:45 PM PDT 24
Peak memory 245936 kb
Host smart-56217492-f7bc-4b30-ba78-15b968eba7b5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805517333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_j
tag_state_post_trans.805517333
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.2881571348
Short name T607
Test name
Test status
Simulation time 390054944 ps
CPU time 3.97 seconds
Started Jul 06 07:16:22 PM PDT 24
Finished Jul 06 07:16:30 PM PDT 24
Peak memory 217784 kb
Host smart-50dc6e63-396a-4fae-8398-031b81ccdc56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881571348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.2881571348
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.1262015132
Short name T255
Test name
Test status
Simulation time 277346201 ps
CPU time 8.18 seconds
Started Jul 06 07:16:21 PM PDT 24
Finished Jul 06 07:16:34 PM PDT 24
Peak memory 214112 kb
Host smart-a1b8e0de-5bc0-4de3-bbc2-f15316b2b72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262015132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.1262015132
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.811853407
Short name T98
Test name
Test status
Simulation time 214279132 ps
CPU time 27.49 seconds
Started Jul 06 07:16:34 PM PDT 24
Finished Jul 06 07:17:03 PM PDT 24
Peak memory 282116 kb
Host smart-17345b99-899c-4ea8-a3ec-c0a54ed92195
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811853407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.811853407
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.205157994
Short name T543
Test name
Test status
Simulation time 1248381309 ps
CPU time 16.29 seconds
Started Jul 06 07:16:36 PM PDT 24
Finished Jul 06 07:16:54 PM PDT 24
Peak memory 218488 kb
Host smart-b7edfb85-0f9b-4955-9e88-071f1aa9fa03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205157994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.205157994
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.3256900872
Short name T487
Test name
Test status
Simulation time 1038375493 ps
CPU time 11.43 seconds
Started Jul 06 07:16:35 PM PDT 24
Finished Jul 06 07:16:48 PM PDT 24
Peak memory 225452 kb
Host smart-2c181cd8-cd32-473a-bf6b-7d18ecd1a73b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256900872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.3256900872
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.3996360171
Short name T506
Test name
Test status
Simulation time 226786766 ps
CPU time 6.96 seconds
Started Jul 06 07:16:37 PM PDT 24
Finished Jul 06 07:16:45 PM PDT 24
Peak memory 217972 kb
Host smart-38e589d0-ae3d-45a8-8886-b1300933c3d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996360171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.3
996360171
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.3108158923
Short name T109
Test name
Test status
Simulation time 316983596 ps
CPU time 12.67 seconds
Started Jul 06 07:16:21 PM PDT 24
Finished Jul 06 07:16:38 PM PDT 24
Peak memory 217844 kb
Host smart-6bb6ab59-2b16-4864-8a68-4df352231e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108158923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.3108158923
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.3069895789
Short name T820
Test name
Test status
Simulation time 111319063 ps
CPU time 7.86 seconds
Started Jul 06 07:16:22 PM PDT 24
Finished Jul 06 07:16:34 PM PDT 24
Peak memory 217188 kb
Host smart-c47c0cf3-8b21-4df1-bc2f-eca890547ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069895789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.3069895789
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.771202495
Short name T262
Test name
Test status
Simulation time 291324712 ps
CPU time 23.41 seconds
Started Jul 06 07:16:22 PM PDT 24
Finished Jul 06 07:16:49 PM PDT 24
Peak memory 250488 kb
Host smart-2be670c3-d263-46e8-9194-d767cd126ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771202495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.771202495
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.2053969383
Short name T688
Test name
Test status
Simulation time 378436618 ps
CPU time 8.52 seconds
Started Jul 06 07:16:21 PM PDT 24
Finished Jul 06 07:16:34 PM PDT 24
Peak memory 250548 kb
Host smart-91b2c46c-2c9a-4303-8bec-879e5ae539e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053969383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.2053969383
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.561053319
Short name T521
Test name
Test status
Simulation time 5838736111 ps
CPU time 65.61 seconds
Started Jul 06 07:16:36 PM PDT 24
Finished Jul 06 07:17:43 PM PDT 24
Peak memory 267008 kb
Host smart-3ec702dc-f18a-43ff-aa23-cfefce443edb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561053319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.561053319
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.1385374999
Short name T472
Test name
Test status
Simulation time 30871760 ps
CPU time 0.99 seconds
Started Jul 06 07:16:20 PM PDT 24
Finished Jul 06 07:16:26 PM PDT 24
Peak memory 217156 kb
Host smart-62066a24-a478-4177-bf45-8b67b369eba0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385374999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.1385374999
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.2063862159
Short name T653
Test name
Test status
Simulation time 33270758 ps
CPU time 1.15 seconds
Started Jul 06 07:19:23 PM PDT 24
Finished Jul 06 07:19:26 PM PDT 24
Peak memory 208560 kb
Host smart-869cae8b-d7a5-4f42-93f7-fde0228a7373
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063862159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.2063862159
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.2886374940
Short name T718
Test name
Test status
Simulation time 282969932 ps
CPU time 11.5 seconds
Started Jul 06 07:19:22 PM PDT 24
Finished Jul 06 07:19:35 PM PDT 24
Peak memory 225664 kb
Host smart-72d999d5-5e38-4b0f-8f28-6067f2c8651f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886374940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.2886374940
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.3620075184
Short name T769
Test name
Test status
Simulation time 781228565 ps
CPU time 12.34 seconds
Started Jul 06 07:19:26 PM PDT 24
Finished Jul 06 07:19:39 PM PDT 24
Peak memory 217220 kb
Host smart-8ad30cea-0bb6-441a-8955-607a23f084d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620075184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.3620075184
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.2943542849
Short name T371
Test name
Test status
Simulation time 41489522 ps
CPU time 2.82 seconds
Started Jul 06 07:19:24 PM PDT 24
Finished Jul 06 07:19:28 PM PDT 24
Peak memory 217788 kb
Host smart-b346fb3a-ef8c-4cb5-a103-19bb5bd89237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943542849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.2943542849
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.3785095485
Short name T807
Test name
Test status
Simulation time 332916308 ps
CPU time 17.62 seconds
Started Jul 06 07:19:24 PM PDT 24
Finished Jul 06 07:19:43 PM PDT 24
Peak memory 218544 kb
Host smart-a68f2b5d-d54a-4013-a3a1-5fa774a509ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785095485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.3785095485
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.8446696
Short name T457
Test name
Test status
Simulation time 992714239 ps
CPU time 15.68 seconds
Started Jul 06 07:19:27 PM PDT 24
Finished Jul 06 07:19:44 PM PDT 24
Peak memory 225520 kb
Host smart-e3e9f176-4860-4b38-bdfa-b2cf64f4b8df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8446696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dige
st_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_dige
st.8446696
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.2338911422
Short name T443
Test name
Test status
Simulation time 2108147505 ps
CPU time 10.95 seconds
Started Jul 06 07:19:23 PM PDT 24
Finished Jul 06 07:19:35 PM PDT 24
Peak memory 217684 kb
Host smart-4390d238-4d5f-4630-b6da-3f7b834b3d53
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338911422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
2338911422
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.4027841931
Short name T345
Test name
Test status
Simulation time 505216906 ps
CPU time 9.32 seconds
Started Jul 06 07:19:22 PM PDT 24
Finished Jul 06 07:19:33 PM PDT 24
Peak memory 217856 kb
Host smart-5b2df47b-3c67-4b2c-a94a-c79e942ff3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027841931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.4027841931
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.3112678344
Short name T839
Test name
Test status
Simulation time 24628082 ps
CPU time 2.01 seconds
Started Jul 06 07:19:24 PM PDT 24
Finished Jul 06 07:19:27 PM PDT 24
Peak memory 217248 kb
Host smart-24204909-71c0-4ba7-bef3-f8f179fd90bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112678344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.3112678344
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.594971598
Short name T765
Test name
Test status
Simulation time 1861826338 ps
CPU time 33.46 seconds
Started Jul 06 07:19:22 PM PDT 24
Finished Jul 06 07:19:56 PM PDT 24
Peak memory 250520 kb
Host smart-4acbadeb-9cc3-4353-8130-d6b1919e09e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594971598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.594971598
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.487450027
Short name T673
Test name
Test status
Simulation time 71274625 ps
CPU time 9.14 seconds
Started Jul 06 07:19:24 PM PDT 24
Finished Jul 06 07:19:35 PM PDT 24
Peak memory 250548 kb
Host smart-aa406c1f-1713-45a9-b17b-f1cf17865001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487450027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.487450027
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.2382715097
Short name T545
Test name
Test status
Simulation time 15777609 ps
CPU time 0.81 seconds
Started Jul 06 07:19:23 PM PDT 24
Finished Jul 06 07:19:25 PM PDT 24
Peak memory 208372 kb
Host smart-68f96157-83d7-4230-9b85-54b648144531
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382715097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.2382715097
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.446656243
Short name T170
Test name
Test status
Simulation time 84880857 ps
CPU time 0.86 seconds
Started Jul 06 07:19:32 PM PDT 24
Finished Jul 06 07:19:34 PM PDT 24
Peak memory 208396 kb
Host smart-e186de80-282d-4352-835b-28449268b0e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446656243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.446656243
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.1708587265
Short name T430
Test name
Test status
Simulation time 1399896145 ps
CPU time 14.67 seconds
Started Jul 06 07:19:29 PM PDT 24
Finished Jul 06 07:19:45 PM PDT 24
Peak memory 217780 kb
Host smart-23d974ea-f8f8-4dbf-b907-9262ae7335b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708587265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.1708587265
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.3583758478
Short name T505
Test name
Test status
Simulation time 877272004 ps
CPU time 8.36 seconds
Started Jul 06 07:19:31 PM PDT 24
Finished Jul 06 07:19:41 PM PDT 24
Peak memory 217160 kb
Host smart-3ac5979d-62ed-45d0-ade9-9781828bbccd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583758478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.3583758478
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.2267202164
Short name T423
Test name
Test status
Simulation time 95531201 ps
CPU time 2.97 seconds
Started Jul 06 07:19:23 PM PDT 24
Finished Jul 06 07:19:28 PM PDT 24
Peak memory 217740 kb
Host smart-22741e4c-e0e7-4f1f-82d4-9c0df63ae1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267202164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.2267202164
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.2094723282
Short name T587
Test name
Test status
Simulation time 1916891152 ps
CPU time 14.02 seconds
Started Jul 06 07:19:34 PM PDT 24
Finished Jul 06 07:19:49 PM PDT 24
Peak memory 225536 kb
Host smart-afbfdf5d-a9bf-4480-89c3-969f7004ed86
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094723282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.2094723282
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.2718149879
Short name T686
Test name
Test status
Simulation time 591364955 ps
CPU time 11.87 seconds
Started Jul 06 07:19:32 PM PDT 24
Finished Jul 06 07:19:46 PM PDT 24
Peak memory 225532 kb
Host smart-cfe32c02-a8aa-4eb9-bd03-30f7fd401daf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718149879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
2718149879
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.1821959198
Short name T373
Test name
Test status
Simulation time 182219191 ps
CPU time 2.41 seconds
Started Jul 06 07:19:24 PM PDT 24
Finished Jul 06 07:19:28 PM PDT 24
Peak memory 217156 kb
Host smart-658c7db8-32f6-45c0-a8ac-2607d9e69903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821959198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.1821959198
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.2929040463
Short name T51
Test name
Test status
Simulation time 790986442 ps
CPU time 27.87 seconds
Started Jul 06 07:19:22 PM PDT 24
Finished Jul 06 07:19:52 PM PDT 24
Peak memory 245740 kb
Host smart-0aaecdd2-134e-4f09-a8a7-112a9e5f6069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929040463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.2929040463
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.3297283196
Short name T672
Test name
Test status
Simulation time 880501913 ps
CPU time 3.65 seconds
Started Jul 06 07:19:25 PM PDT 24
Finished Jul 06 07:19:30 PM PDT 24
Peak memory 217772 kb
Host smart-f545e2f6-9d13-456e-8228-82efc9cbc7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297283196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.3297283196
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.1141761434
Short name T597
Test name
Test status
Simulation time 42926839535 ps
CPU time 354.11 seconds
Started Jul 06 07:19:32 PM PDT 24
Finished Jul 06 07:25:28 PM PDT 24
Peak memory 227912 kb
Host smart-c5788ef2-17f3-4760-89ee-516de712e008
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141761434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.1141761434
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.3146063351
Short name T553
Test name
Test status
Simulation time 37206634 ps
CPU time 0.88 seconds
Started Jul 06 07:19:22 PM PDT 24
Finished Jul 06 07:19:25 PM PDT 24
Peak memory 208480 kb
Host smart-3d47a513-c3fe-4559-8168-55be87d73b1e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146063351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.3146063351
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.2363840362
Short name T734
Test name
Test status
Simulation time 67091728 ps
CPU time 1.12 seconds
Started Jul 06 07:19:36 PM PDT 24
Finished Jul 06 07:19:39 PM PDT 24
Peak memory 208624 kb
Host smart-f80746bb-084a-4c02-b575-e5e44377a87f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363840362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.2363840362
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.2844522551
Short name T514
Test name
Test status
Simulation time 1152340414 ps
CPU time 9.51 seconds
Started Jul 06 07:19:33 PM PDT 24
Finished Jul 06 07:19:44 PM PDT 24
Peak memory 225540 kb
Host smart-bbe96724-f058-4221-af34-9e7beb67f03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844522551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.2844522551
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.2886688857
Short name T7
Test name
Test status
Simulation time 330120112 ps
CPU time 5 seconds
Started Jul 06 07:19:32 PM PDT 24
Finished Jul 06 07:19:38 PM PDT 24
Peak memory 217212 kb
Host smart-892a99b0-1c72-4d0a-9e05-01fc7a16d51f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886688857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.2886688857
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.2873365143
Short name T1
Test name
Test status
Simulation time 19530218 ps
CPU time 1.5 seconds
Started Jul 06 07:19:31 PM PDT 24
Finished Jul 06 07:19:34 PM PDT 24
Peak memory 221180 kb
Host smart-aa9ca81c-099c-4a71-8175-6109012c7af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873365143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.2873365143
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.3603645160
Short name T418
Test name
Test status
Simulation time 1471594495 ps
CPU time 10.4 seconds
Started Jul 06 07:19:31 PM PDT 24
Finished Jul 06 07:19:43 PM PDT 24
Peak memory 225524 kb
Host smart-53b4460f-77e6-48ed-acf9-c23b8777a7cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603645160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.3603645160
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.946362608
Short name T240
Test name
Test status
Simulation time 679392713 ps
CPU time 12.64 seconds
Started Jul 06 07:19:33 PM PDT 24
Finished Jul 06 07:19:47 PM PDT 24
Peak memory 217688 kb
Host smart-b56e2265-7b36-4268-a524-a451732b59c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946362608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.946362608
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.570137597
Short name T716
Test name
Test status
Simulation time 4341593618 ps
CPU time 8.53 seconds
Started Jul 06 07:19:29 PM PDT 24
Finished Jul 06 07:19:39 PM PDT 24
Peak memory 225636 kb
Host smart-b4b06583-4d1c-4e7d-ad0e-efbb627acc93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570137597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.570137597
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.3363581343
Short name T534
Test name
Test status
Simulation time 59624363 ps
CPU time 3.03 seconds
Started Jul 06 07:19:29 PM PDT 24
Finished Jul 06 07:19:33 PM PDT 24
Peak memory 217176 kb
Host smart-ab8e59b3-a575-4511-aeaf-69ba475a9e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363581343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.3363581343
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.1134850722
Short name T674
Test name
Test status
Simulation time 713977577 ps
CPU time 33.73 seconds
Started Jul 06 07:19:28 PM PDT 24
Finished Jul 06 07:20:03 PM PDT 24
Peak memory 250520 kb
Host smart-6f98b347-4a33-48f2-bd51-4cb34e83a8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134850722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.1134850722
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.3774613850
Short name T755
Test name
Test status
Simulation time 205477976 ps
CPU time 6.62 seconds
Started Jul 06 07:19:28 PM PDT 24
Finished Jul 06 07:19:36 PM PDT 24
Peak memory 246460 kb
Host smart-c4a2f1f7-fbf4-4c9c-948b-3fe09465250f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774613850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.3774613850
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.2350363287
Short name T112
Test name
Test status
Simulation time 454121768 ps
CPU time 31.94 seconds
Started Jul 06 07:19:34 PM PDT 24
Finished Jul 06 07:20:08 PM PDT 24
Peak memory 250576 kb
Host smart-a0244295-94a4-4691-98fc-7fc1eed27c41
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350363287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.2350363287
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.2083192533
Short name T491
Test name
Test status
Simulation time 20567012 ps
CPU time 0.9 seconds
Started Jul 06 07:19:28 PM PDT 24
Finished Jul 06 07:19:30 PM PDT 24
Peak memory 211340 kb
Host smart-75803856-50a5-4216-9fde-8e980439d0a0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083192533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.2083192533
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.1081682989
Short name T352
Test name
Test status
Simulation time 15417056 ps
CPU time 1.13 seconds
Started Jul 06 07:19:35 PM PDT 24
Finished Jul 06 07:19:38 PM PDT 24
Peak memory 208532 kb
Host smart-caf6bb40-0d9a-4016-a6b1-fa57892519fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081682989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.1081682989
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.4003195102
Short name T245
Test name
Test status
Simulation time 354038039 ps
CPU time 10.65 seconds
Started Jul 06 07:19:34 PM PDT 24
Finished Jul 06 07:19:47 PM PDT 24
Peak memory 217796 kb
Host smart-36928042-b638-4b3a-89ef-e63fb28a6a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003195102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.4003195102
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.3635187138
Short name T596
Test name
Test status
Simulation time 390190364 ps
CPU time 4.75 seconds
Started Jul 06 07:19:36 PM PDT 24
Finished Jul 06 07:19:43 PM PDT 24
Peak memory 216684 kb
Host smart-a4d1ed64-db18-4c2b-be50-1388a307ecb5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635187138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.3635187138
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.3339695679
Short name T831
Test name
Test status
Simulation time 64869450 ps
CPU time 3.08 seconds
Started Jul 06 07:19:34 PM PDT 24
Finished Jul 06 07:19:39 PM PDT 24
Peak memory 217672 kb
Host smart-2562d15f-ecee-49a7-8926-eaba1f9a8e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339695679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.3339695679
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.846686968
Short name T307
Test name
Test status
Simulation time 482474572 ps
CPU time 14.34 seconds
Started Jul 06 07:19:35 PM PDT 24
Finished Jul 06 07:19:52 PM PDT 24
Peak memory 225532 kb
Host smart-1cb31d72-488d-425b-ad96-1bd6c642200f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846686968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.846686968
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.1237325274
Short name T271
Test name
Test status
Simulation time 2260068259 ps
CPU time 11.87 seconds
Started Jul 06 07:19:37 PM PDT 24
Finished Jul 06 07:19:51 PM PDT 24
Peak memory 225564 kb
Host smart-11f348f4-07e7-49b0-8b2f-264c785fd49b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237325274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.1237325274
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.3181904671
Short name T402
Test name
Test status
Simulation time 999294792 ps
CPU time 7.12 seconds
Started Jul 06 07:19:36 PM PDT 24
Finished Jul 06 07:19:45 PM PDT 24
Peak memory 217756 kb
Host smart-e1ad3468-5f83-4962-9118-457d6deb2570
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181904671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
3181904671
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.3777982249
Short name T351
Test name
Test status
Simulation time 829232289 ps
CPU time 9.02 seconds
Started Jul 06 07:19:35 PM PDT 24
Finished Jul 06 07:19:46 PM PDT 24
Peak memory 225548 kb
Host smart-f44842fc-64e1-40ba-ba32-f23670e48e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777982249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.3777982249
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.3594388758
Short name T795
Test name
Test status
Simulation time 233474488 ps
CPU time 3.57 seconds
Started Jul 06 07:19:35 PM PDT 24
Finished Jul 06 07:19:41 PM PDT 24
Peak memory 217212 kb
Host smart-a3ab198f-5435-4f68-9db5-e988ae64e823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594388758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.3594388758
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.1377557250
Short name T845
Test name
Test status
Simulation time 373192656 ps
CPU time 25.84 seconds
Started Jul 06 07:19:37 PM PDT 24
Finished Jul 06 07:20:05 PM PDT 24
Peak memory 250500 kb
Host smart-8a49e23e-419a-4990-a545-8f433d8b0834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377557250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.1377557250
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.1446398178
Short name T287
Test name
Test status
Simulation time 137028887 ps
CPU time 3.89 seconds
Started Jul 06 07:19:36 PM PDT 24
Finished Jul 06 07:19:43 PM PDT 24
Peak memory 222100 kb
Host smart-b7734d02-8eae-4109-b9ab-b538a7c1649f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446398178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.1446398178
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.888844486
Short name T853
Test name
Test status
Simulation time 3295470188 ps
CPU time 41.42 seconds
Started Jul 06 07:19:36 PM PDT 24
Finished Jul 06 07:20:20 PM PDT 24
Peak memory 220456 kb
Host smart-9b8ed214-ca96-41df-9338-60db2485ee75
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888844486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.888844486
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.2173673028
Short name T867
Test name
Test status
Simulation time 14330260 ps
CPU time 0.96 seconds
Started Jul 06 07:19:34 PM PDT 24
Finished Jul 06 07:19:37 PM PDT 24
Peak memory 208724 kb
Host smart-729798df-6875-467c-9dac-a3d0cf51cdb9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173673028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.2173673028
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.195720396
Short name T394
Test name
Test status
Simulation time 20944687 ps
CPU time 0.82 seconds
Started Jul 06 07:19:39 PM PDT 24
Finished Jul 06 07:19:40 PM PDT 24
Peak memory 208380 kb
Host smart-ba85f84b-23a4-4deb-825a-8b11258e4b66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195720396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.195720396
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.2723404715
Short name T412
Test name
Test status
Simulation time 1232853059 ps
CPU time 11.78 seconds
Started Jul 06 07:19:34 PM PDT 24
Finished Jul 06 07:19:47 PM PDT 24
Peak memory 217728 kb
Host smart-8c6aa1f1-0b52-4ce8-b624-7115f2ec9446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723404715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.2723404715
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.2589352024
Short name T29
Test name
Test status
Simulation time 636076502 ps
CPU time 6.89 seconds
Started Jul 06 07:19:35 PM PDT 24
Finished Jul 06 07:19:44 PM PDT 24
Peak memory 217188 kb
Host smart-97ccc4f2-92d9-46a7-b4b7-f2fc1c59c34c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589352024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.2589352024
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.1647365539
Short name T164
Test name
Test status
Simulation time 47650756 ps
CPU time 2.45 seconds
Started Jul 06 07:19:36 PM PDT 24
Finished Jul 06 07:19:41 PM PDT 24
Peak memory 217760 kb
Host smart-31d0b3c4-d7ad-4446-b605-caa31a806429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647365539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.1647365539
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.2032866204
Short name T229
Test name
Test status
Simulation time 898497654 ps
CPU time 12.9 seconds
Started Jul 06 07:19:35 PM PDT 24
Finished Jul 06 07:19:50 PM PDT 24
Peak memory 225512 kb
Host smart-59bd6d16-456c-4e8a-85ea-a4e843f83848
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032866204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.2032866204
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.200272812
Short name T465
Test name
Test status
Simulation time 543545092 ps
CPU time 8.59 seconds
Started Jul 06 07:19:37 PM PDT 24
Finished Jul 06 07:19:48 PM PDT 24
Peak memory 225528 kb
Host smart-4932f944-e807-49ec-b074-0312947926cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200272812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.200272812
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.597586494
Short name T583
Test name
Test status
Simulation time 1045406158 ps
CPU time 10.44 seconds
Started Jul 06 07:19:35 PM PDT 24
Finished Jul 06 07:19:48 PM PDT 24
Peak memory 224528 kb
Host smart-511d212b-1feb-4bde-8254-9833a61c8859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597586494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.597586494
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.2734029314
Short name T834
Test name
Test status
Simulation time 137972115 ps
CPU time 3.3 seconds
Started Jul 06 07:19:38 PM PDT 24
Finished Jul 06 07:19:43 PM PDT 24
Peak memory 217272 kb
Host smart-894eb713-44d9-4aa5-ad31-6017db33d269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734029314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.2734029314
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.3857910461
Short name T633
Test name
Test status
Simulation time 479127740 ps
CPU time 20.94 seconds
Started Jul 06 07:19:37 PM PDT 24
Finished Jul 06 07:20:00 PM PDT 24
Peak memory 250512 kb
Host smart-8730b862-402c-4888-a056-e3b2acc14286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857910461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.3857910461
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.1269513838
Short name T282
Test name
Test status
Simulation time 70449133 ps
CPU time 6.87 seconds
Started Jul 06 07:19:36 PM PDT 24
Finished Jul 06 07:19:45 PM PDT 24
Peak memory 246336 kb
Host smart-4ea9127a-2f9f-4204-ba69-894eec82be7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269513838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.1269513838
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.819613334
Short name T35
Test name
Test status
Simulation time 21024401 ps
CPU time 0.81 seconds
Started Jul 06 07:19:36 PM PDT 24
Finished Jul 06 07:19:39 PM PDT 24
Peak memory 208288 kb
Host smart-89cf7144-98b5-450d-b388-afe1c180adab
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819613334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ct
rl_volatile_unlock_smoke.819613334
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.2132583150
Short name T374
Test name
Test status
Simulation time 57984612 ps
CPU time 1.05 seconds
Started Jul 06 07:19:42 PM PDT 24
Finished Jul 06 07:19:45 PM PDT 24
Peak memory 208544 kb
Host smart-0ca05332-2285-41cc-974d-f34366bfc048
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132583150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.2132583150
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.2016342044
Short name T297
Test name
Test status
Simulation time 277284646 ps
CPU time 7.98 seconds
Started Jul 06 07:19:44 PM PDT 24
Finished Jul 06 07:19:52 PM PDT 24
Peak memory 217740 kb
Host smart-979c9dcf-db3f-43aa-bcc4-07abeaffafc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016342044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.2016342044
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.4018935777
Short name T27
Test name
Test status
Simulation time 5324366211 ps
CPU time 29.86 seconds
Started Jul 06 07:19:42 PM PDT 24
Finished Jul 06 07:20:13 PM PDT 24
Peak memory 217256 kb
Host smart-cccc013d-2d1f-4193-8030-610cc5cfcc07
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018935777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.4018935777
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.1213537055
Short name T858
Test name
Test status
Simulation time 36956373 ps
CPU time 2 seconds
Started Jul 06 07:19:41 PM PDT 24
Finished Jul 06 07:19:44 PM PDT 24
Peak memory 221644 kb
Host smart-ff1dfa83-fb6b-49cf-8a95-063bf90ffc87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213537055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.1213537055
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.1040874030
Short name T857
Test name
Test status
Simulation time 317340156 ps
CPU time 11.65 seconds
Started Jul 06 07:19:49 PM PDT 24
Finished Jul 06 07:20:03 PM PDT 24
Peak memory 218388 kb
Host smart-569a8f6f-47c6-44a4-a37d-6b7a802ccfa8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040874030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.1040874030
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.1534083930
Short name T409
Test name
Test status
Simulation time 750899850 ps
CPU time 11.27 seconds
Started Jul 06 07:19:49 PM PDT 24
Finished Jul 06 07:20:03 PM PDT 24
Peak memory 225408 kb
Host smart-eb09419f-0404-4690-8279-8d9e086dbd16
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534083930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.1534083930
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.2003190506
Short name T313
Test name
Test status
Simulation time 985012605 ps
CPU time 10 seconds
Started Jul 06 07:19:42 PM PDT 24
Finished Jul 06 07:19:54 PM PDT 24
Peak memory 217720 kb
Host smart-3a4d87dc-7ad5-47d9-b6a0-0664098d25ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003190506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
2003190506
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.3474607044
Short name T299
Test name
Test status
Simulation time 1631540996 ps
CPU time 8.3 seconds
Started Jul 06 07:19:49 PM PDT 24
Finished Jul 06 07:20:00 PM PDT 24
Peak memory 225532 kb
Host smart-55cfe04b-3e7e-4a9f-b488-7a36939f4e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474607044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.3474607044
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.3048106617
Short name T241
Test name
Test status
Simulation time 20973595 ps
CPU time 1.51 seconds
Started Jul 06 07:19:39 PM PDT 24
Finished Jul 06 07:19:41 PM PDT 24
Peak memory 217212 kb
Host smart-7fbb166b-7ffd-4d8e-81e4-89782f24ff0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048106617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.3048106617
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.2909782586
Short name T469
Test name
Test status
Simulation time 277032554 ps
CPU time 22.94 seconds
Started Jul 06 07:19:42 PM PDT 24
Finished Jul 06 07:20:06 PM PDT 24
Peak memory 250540 kb
Host smart-b9cf6ad5-79fa-41c7-a0d8-5203387c972f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909782586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.2909782586
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.2513222972
Short name T499
Test name
Test status
Simulation time 53609784 ps
CPU time 7.9 seconds
Started Jul 06 07:19:40 PM PDT 24
Finished Jul 06 07:19:49 PM PDT 24
Peak memory 250552 kb
Host smart-d16e4883-42eb-4664-9818-c4d649b28e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513222972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.2513222972
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.4225406484
Short name T193
Test name
Test status
Simulation time 11520173542 ps
CPU time 228.23 seconds
Started Jul 06 07:19:41 PM PDT 24
Finished Jul 06 07:23:30 PM PDT 24
Peak memory 283392 kb
Host smart-fc0a5d91-0399-4918-971f-458eb32248de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225406484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.4225406484
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.2390217157
Short name T315
Test name
Test status
Simulation time 21069419 ps
CPU time 1.24 seconds
Started Jul 06 07:19:50 PM PDT 24
Finished Jul 06 07:19:54 PM PDT 24
Peak memory 208256 kb
Host smart-cbff47c1-9f90-4d10-8824-92eb900a645d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390217157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.2390217157
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.1583357430
Short name T176
Test name
Test status
Simulation time 174682600 ps
CPU time 9.53 seconds
Started Jul 06 07:19:40 PM PDT 24
Finished Jul 06 07:19:50 PM PDT 24
Peak memory 217772 kb
Host smart-13ee7b5a-dcb9-482f-9bb3-fb07d97acff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583357430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.1583357430
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.3208179927
Short name T395
Test name
Test status
Simulation time 2698549419 ps
CPU time 6.68 seconds
Started Jul 06 07:19:41 PM PDT 24
Finished Jul 06 07:19:49 PM PDT 24
Peak memory 217220 kb
Host smart-3d9762d8-f3ee-44c4-b57d-03b163f76132
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208179927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.3208179927
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.2299943196
Short name T592
Test name
Test status
Simulation time 20631810 ps
CPU time 1.68 seconds
Started Jul 06 07:19:43 PM PDT 24
Finished Jul 06 07:19:46 PM PDT 24
Peak memory 217872 kb
Host smart-38a7009c-08e8-4123-96d2-4b328a7c7565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299943196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.2299943196
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.1495780644
Short name T264
Test name
Test status
Simulation time 455260779 ps
CPU time 10.17 seconds
Started Jul 06 07:19:47 PM PDT 24
Finished Jul 06 07:19:59 PM PDT 24
Peak memory 225524 kb
Host smart-e65b1ff4-ad20-4bb1-9839-5a5866e98c17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495780644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.1495780644
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.502938065
Short name T502
Test name
Test status
Simulation time 4563457823 ps
CPU time 9.25 seconds
Started Jul 06 07:19:48 PM PDT 24
Finished Jul 06 07:19:59 PM PDT 24
Peak memory 217784 kb
Host smart-892868ea-6b63-49c3-b336-b687d79be8ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502938065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.502938065
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.351004442
Short name T706
Test name
Test status
Simulation time 791229731 ps
CPU time 10.2 seconds
Started Jul 06 07:19:44 PM PDT 24
Finished Jul 06 07:19:55 PM PDT 24
Peak memory 225128 kb
Host smart-117dd8d1-5c02-4a60-bb7e-eebf61af2ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351004442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.351004442
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.1454058533
Short name T384
Test name
Test status
Simulation time 21627881 ps
CPU time 1.62 seconds
Started Jul 06 07:19:43 PM PDT 24
Finished Jul 06 07:19:45 PM PDT 24
Peak memory 217196 kb
Host smart-16ac2589-e7c3-406b-a395-0993c88eec76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454058533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.1454058533
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.3085846155
Short name T767
Test name
Test status
Simulation time 259603368 ps
CPU time 28.35 seconds
Started Jul 06 07:19:45 PM PDT 24
Finished Jul 06 07:20:14 PM PDT 24
Peak memory 250548 kb
Host smart-e4007a23-1222-4f10-8a3f-06932ccecee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085846155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.3085846155
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.3557953935
Short name T739
Test name
Test status
Simulation time 100838854 ps
CPU time 5.89 seconds
Started Jul 06 07:19:44 PM PDT 24
Finished Jul 06 07:19:50 PM PDT 24
Peak memory 246536 kb
Host smart-68f1f835-d21f-464a-9bb8-f8d3179c8022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557953935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.3557953935
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.758274794
Short name T483
Test name
Test status
Simulation time 16492273752 ps
CPU time 98.36 seconds
Started Jul 06 07:19:49 PM PDT 24
Finished Jul 06 07:21:30 PM PDT 24
Peak memory 245892 kb
Host smart-1a7683ad-da87-45dc-9113-cd23308f9273
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758274794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.758274794
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.1964319715
Short name T849
Test name
Test status
Simulation time 35611592 ps
CPU time 0.87 seconds
Started Jul 06 07:19:40 PM PDT 24
Finished Jul 06 07:19:42 PM PDT 24
Peak memory 208456 kb
Host smart-638e350f-37c2-4183-9036-9bb176ab84d9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964319715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.1964319715
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.500797725
Short name T602
Test name
Test status
Simulation time 33370160 ps
CPU time 1.15 seconds
Started Jul 06 07:19:49 PM PDT 24
Finished Jul 06 07:19:52 PM PDT 24
Peak memory 208468 kb
Host smart-6888c573-c357-4cdc-9759-9bc7245aefb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500797725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.500797725
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.3334850102
Short name T829
Test name
Test status
Simulation time 648020352 ps
CPU time 15.78 seconds
Started Jul 06 07:19:48 PM PDT 24
Finished Jul 06 07:20:06 PM PDT 24
Peak memory 225580 kb
Host smart-44267e55-5f44-4a12-9dc9-9c260fada762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334850102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.3334850102
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.1729714823
Short name T25
Test name
Test status
Simulation time 1347799053 ps
CPU time 9.38 seconds
Started Jul 06 07:19:48 PM PDT 24
Finished Jul 06 07:19:59 PM PDT 24
Peak memory 216992 kb
Host smart-6a1bbb15-6eac-4c15-915b-5ede85c6a8cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729714823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.1729714823
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.2613992496
Short name T576
Test name
Test status
Simulation time 103018810 ps
CPU time 3.46 seconds
Started Jul 06 07:19:47 PM PDT 24
Finished Jul 06 07:19:52 PM PDT 24
Peak memory 222100 kb
Host smart-642dc79e-98f6-4dfc-9217-78345de91903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613992496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.2613992496
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.1471537050
Short name T497
Test name
Test status
Simulation time 499478277 ps
CPU time 20.83 seconds
Started Jul 06 07:19:48 PM PDT 24
Finished Jul 06 07:20:11 PM PDT 24
Peak memory 217988 kb
Host smart-6c39a8d7-e1bc-4a96-bd0f-87570fc63962
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471537050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.1471537050
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.3974859703
Short name T309
Test name
Test status
Simulation time 818048016 ps
CPU time 11.36 seconds
Started Jul 06 07:19:48 PM PDT 24
Finished Jul 06 07:20:01 PM PDT 24
Peak memory 225500 kb
Host smart-0038ae96-c644-4065-94f2-062ac01b6013
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974859703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.3974859703
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.3072061887
Short name T832
Test name
Test status
Simulation time 228195525 ps
CPU time 6.84 seconds
Started Jul 06 07:19:48 PM PDT 24
Finished Jul 06 07:19:58 PM PDT 24
Peak memory 224828 kb
Host smart-ee5ff9f8-8baf-46cd-a84a-96a3c38483d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072061887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
3072061887
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.2119877558
Short name T348
Test name
Test status
Simulation time 575370008 ps
CPU time 7.59 seconds
Started Jul 06 07:19:48 PM PDT 24
Finished Jul 06 07:19:58 PM PDT 24
Peak memory 225156 kb
Host smart-d7220abf-c102-4b60-adf7-586cc874d0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119877558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.2119877558
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.2035394847
Short name T408
Test name
Test status
Simulation time 35914737 ps
CPU time 1.11 seconds
Started Jul 06 07:19:50 PM PDT 24
Finished Jul 06 07:19:53 PM PDT 24
Peak memory 211084 kb
Host smart-13177f1a-7e2b-4e0a-ae36-155ddf3b16cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035394847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.2035394847
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.333690003
Short name T160
Test name
Test status
Simulation time 307817042 ps
CPU time 30.84 seconds
Started Jul 06 07:19:46 PM PDT 24
Finished Jul 06 07:20:18 PM PDT 24
Peak memory 250532 kb
Host smart-000272c6-9483-4076-9a86-012511c49f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333690003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.333690003
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.3624445445
Short name T791
Test name
Test status
Simulation time 490008576 ps
CPU time 3 seconds
Started Jul 06 07:19:50 PM PDT 24
Finished Jul 06 07:19:56 PM PDT 24
Peak memory 225976 kb
Host smart-d9c73248-db3c-47f8-a7cd-0ec89bbe9828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624445445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.3624445445
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.3605552372
Short name T862
Test name
Test status
Simulation time 7939281156 ps
CPU time 183.02 seconds
Started Jul 06 07:19:47 PM PDT 24
Finished Jul 06 07:22:52 PM PDT 24
Peak memory 249612 kb
Host smart-9e14180f-d4c2-4e2a-8555-1cc693ce1ff1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605552372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.3605552372
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.2136966094
Short name T168
Test name
Test status
Simulation time 8252278860 ps
CPU time 141.36 seconds
Started Jul 06 07:19:48 PM PDT 24
Finished Jul 06 07:22:12 PM PDT 24
Peak memory 263044 kb
Host smart-78ce884e-e5e8-47ce-8ed3-947a9f42d34e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2136966094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all_with_rand_reset.2136966094
Directory /workspace/47.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.23098101
Short name T786
Test name
Test status
Simulation time 48105123 ps
CPU time 0.79 seconds
Started Jul 06 07:19:46 PM PDT 24
Finished Jul 06 07:19:48 PM PDT 24
Peak memory 208328 kb
Host smart-66f99f56-8dd3-4754-9939-57e50ea3c1d8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23098101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctr
l_volatile_unlock_smoke.23098101
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.1078234850
Short name T81
Test name
Test status
Simulation time 13014896 ps
CPU time 0.87 seconds
Started Jul 06 07:19:55 PM PDT 24
Finished Jul 06 07:19:58 PM PDT 24
Peak memory 208392 kb
Host smart-ec0fd15c-333d-436a-b1b0-eff8048093a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078234850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.1078234850
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.2962298030
Short name T843
Test name
Test status
Simulation time 421935187 ps
CPU time 13.47 seconds
Started Jul 06 07:19:55 PM PDT 24
Finished Jul 06 07:20:10 PM PDT 24
Peak memory 217804 kb
Host smart-d33e1308-787e-4eca-8902-b525f65e3576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962298030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.2962298030
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.669108569
Short name T102
Test name
Test status
Simulation time 326529002 ps
CPU time 6.13 seconds
Started Jul 06 07:19:54 PM PDT 24
Finished Jul 06 07:20:02 PM PDT 24
Peak memory 217204 kb
Host smart-b39be075-0d83-41d8-9831-7f1abbb2cca2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669108569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.669108569
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.1592726040
Short name T330
Test name
Test status
Simulation time 73545109 ps
CPU time 3.5 seconds
Started Jul 06 07:19:55 PM PDT 24
Finished Jul 06 07:20:01 PM PDT 24
Peak memory 217800 kb
Host smart-31e47fd4-5fda-4456-842e-30f416217d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592726040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.1592726040
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.1687462186
Short name T303
Test name
Test status
Simulation time 482548881 ps
CPU time 18.19 seconds
Started Jul 06 07:19:56 PM PDT 24
Finished Jul 06 07:20:16 PM PDT 24
Peak memory 225572 kb
Host smart-3d68d123-08fa-4e48-b97e-eed6f1edf968
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687462186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.1687462186
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.1288847541
Short name T270
Test name
Test status
Simulation time 329530227 ps
CPU time 8.2 seconds
Started Jul 06 07:19:53 PM PDT 24
Finished Jul 06 07:20:03 PM PDT 24
Peak memory 225512 kb
Host smart-1fe1d44e-8412-4c45-af14-e1f5b5943b04
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288847541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
1288847541
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.3901679284
Short name T39
Test name
Test status
Simulation time 375783744 ps
CPU time 13.49 seconds
Started Jul 06 07:19:54 PM PDT 24
Finished Jul 06 07:20:10 PM PDT 24
Peak memory 217800 kb
Host smart-6ca80101-e017-4f78-bf4b-4d0328b0d4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901679284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.3901679284
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.288426814
Short name T856
Test name
Test status
Simulation time 26450055 ps
CPU time 1.88 seconds
Started Jul 06 07:19:48 PM PDT 24
Finished Jul 06 07:19:53 PM PDT 24
Peak memory 213364 kb
Host smart-7ca41c3d-4fb1-403d-bd5e-4fe472688923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288426814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.288426814
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.6563593
Short name T391
Test name
Test status
Simulation time 438048939 ps
CPU time 17.71 seconds
Started Jul 06 07:19:49 PM PDT 24
Finished Jul 06 07:20:09 PM PDT 24
Peak memory 250236 kb
Host smart-706a15ff-9ef1-418f-871a-0b3d57a6fdd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6563593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.6563593
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.3219458356
Short name T562
Test name
Test status
Simulation time 86703630 ps
CPU time 7.46 seconds
Started Jul 06 07:19:46 PM PDT 24
Finished Jul 06 07:19:54 PM PDT 24
Peak memory 250296 kb
Host smart-6837d570-373d-41f5-9101-3bb917d3c852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219458356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.3219458356
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.1546667379
Short name T77
Test name
Test status
Simulation time 5176720842 ps
CPU time 104.43 seconds
Started Jul 06 07:19:52 PM PDT 24
Finished Jul 06 07:21:38 PM PDT 24
Peak memory 250700 kb
Host smart-7a63e860-6e3c-439f-a4d2-4f1d6bd403fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546667379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.1546667379
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.1871920782
Short name T105
Test name
Test status
Simulation time 108887821182 ps
CPU time 542.57 seconds
Started Jul 06 07:19:53 PM PDT 24
Finished Jul 06 07:28:57 PM PDT 24
Peak memory 332628 kb
Host smart-ec820ae2-f3f0-4608-94d0-4888d8f75440
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1871920782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.1871920782
Directory /workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.4143125376
Short name T773
Test name
Test status
Simulation time 37214857 ps
CPU time 1.03 seconds
Started Jul 06 07:19:50 PM PDT 24
Finished Jul 06 07:19:53 PM PDT 24
Peak memory 211412 kb
Host smart-67ba85d3-9c65-4ea6-bb45-ddee57eeb273
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143125376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.4143125376
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.2865052442
Short name T535
Test name
Test status
Simulation time 31788727 ps
CPU time 1.13 seconds
Started Jul 06 07:19:55 PM PDT 24
Finished Jul 06 07:19:58 PM PDT 24
Peak memory 208528 kb
Host smart-df906f3f-17a6-4946-8b10-2c51467ed32a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865052442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.2865052442
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.1579551567
Short name T463
Test name
Test status
Simulation time 287752751 ps
CPU time 9.97 seconds
Started Jul 06 07:19:55 PM PDT 24
Finished Jul 06 07:20:07 PM PDT 24
Peak memory 225592 kb
Host smart-62074aee-c80a-47d0-b4a0-c7a210d1ea5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579551567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.1579551567
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.4085792115
Short name T26
Test name
Test status
Simulation time 386667775 ps
CPU time 10.82 seconds
Started Jul 06 07:19:57 PM PDT 24
Finished Jul 06 07:20:09 PM PDT 24
Peak memory 217172 kb
Host smart-a7660dc4-0436-49bc-8a2c-1eae0c0354d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085792115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.4085792115
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.2969778073
Short name T334
Test name
Test status
Simulation time 20566100 ps
CPU time 1.55 seconds
Started Jul 06 07:19:54 PM PDT 24
Finished Jul 06 07:19:58 PM PDT 24
Peak memory 217696 kb
Host smart-de1cf95d-51d3-4c90-a182-298baa6375c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969778073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.2969778073
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.3054387582
Short name T314
Test name
Test status
Simulation time 594184112 ps
CPU time 10.66 seconds
Started Jul 06 07:19:56 PM PDT 24
Finished Jul 06 07:20:08 PM PDT 24
Peak memory 225572 kb
Host smart-3509fee2-189f-4b98-899d-1e34bf7502a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054387582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.3054387582
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.3808445198
Short name T252
Test name
Test status
Simulation time 536204575 ps
CPU time 7.01 seconds
Started Jul 06 07:19:55 PM PDT 24
Finished Jul 06 07:20:04 PM PDT 24
Peak memory 225412 kb
Host smart-e2fba321-998e-4e50-a645-0163e19f53f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808445198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.3808445198
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.2257566946
Short name T735
Test name
Test status
Simulation time 1616468002 ps
CPU time 9.88 seconds
Started Jul 06 07:19:54 PM PDT 24
Finished Jul 06 07:20:05 PM PDT 24
Peak memory 217740 kb
Host smart-2069e49e-c5be-449b-8170-e29513734ae6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257566946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
2257566946
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.4135744570
Short name T355
Test name
Test status
Simulation time 317438625 ps
CPU time 8.73 seconds
Started Jul 06 07:19:54 PM PDT 24
Finished Jul 06 07:20:05 PM PDT 24
Peak memory 224460 kb
Host smart-380ceb53-4bbb-46cd-a60b-99c5afea78c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135744570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.4135744570
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.1087718258
Short name T687
Test name
Test status
Simulation time 59891694 ps
CPU time 3.15 seconds
Started Jul 06 07:19:54 PM PDT 24
Finished Jul 06 07:19:59 PM PDT 24
Peak memory 217188 kb
Host smart-07c24d48-c5f4-4f33-9938-e45837cb9400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087718258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.1087718258
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.3924424995
Short name T316
Test name
Test status
Simulation time 298951654 ps
CPU time 23.95 seconds
Started Jul 06 07:19:55 PM PDT 24
Finished Jul 06 07:20:21 PM PDT 24
Peak memory 245556 kb
Host smart-aa29cfe3-ea2e-4cc0-9660-d149b44a19b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924424995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.3924424995
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.457190599
Short name T671
Test name
Test status
Simulation time 101480486 ps
CPU time 3.61 seconds
Started Jul 06 07:19:55 PM PDT 24
Finished Jul 06 07:20:01 PM PDT 24
Peak memory 217660 kb
Host smart-5654f4ee-cddc-4718-9b69-964a5f1aeb20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457190599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.457190599
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.3131976253
Short name T405
Test name
Test status
Simulation time 766255521 ps
CPU time 29.68 seconds
Started Jul 06 07:19:55 PM PDT 24
Finished Jul 06 07:20:27 PM PDT 24
Peak memory 250416 kb
Host smart-21afb6a7-cd9f-4fd1-a77c-17c701be22ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131976253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.3131976253
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.1822115315
Short name T682
Test name
Test status
Simulation time 138137698 ps
CPU time 0.91 seconds
Started Jul 06 07:19:54 PM PDT 24
Finished Jul 06 07:19:56 PM PDT 24
Peak memory 211412 kb
Host smart-7ece8a3c-3375-4419-8ca8-666cf01f2556
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822115315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.1822115315
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.3219283973
Short name T519
Test name
Test status
Simulation time 36488516 ps
CPU time 1.14 seconds
Started Jul 06 07:16:52 PM PDT 24
Finished Jul 06 07:16:56 PM PDT 24
Peak memory 208524 kb
Host smart-2ce5d526-4439-41c8-8fb7-ce35500a4b2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219283973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.3219283973
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.1150684965
Short name T254
Test name
Test status
Simulation time 12540620 ps
CPU time 1 seconds
Started Jul 06 07:16:47 PM PDT 24
Finished Jul 06 07:16:50 PM PDT 24
Peak memory 208400 kb
Host smart-f471efb2-f272-4e9c-93aa-0a4c15abeb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150684965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.1150684965
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.1698877046
Short name T173
Test name
Test status
Simulation time 1802244197 ps
CPU time 11.67 seconds
Started Jul 06 07:16:41 PM PDT 24
Finished Jul 06 07:16:55 PM PDT 24
Peak memory 217764 kb
Host smart-f8b0bbbb-ce81-4490-b044-15d1e791f330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698877046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.1698877046
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.3202163050
Short name T364
Test name
Test status
Simulation time 155536460 ps
CPU time 4.56 seconds
Started Jul 06 07:16:47 PM PDT 24
Finished Jul 06 07:16:54 PM PDT 24
Peak memory 217220 kb
Host smart-7088ca7c-40c1-45f8-88e0-4209e5514377
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202163050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.3202163050
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.98924789
Short name T594
Test name
Test status
Simulation time 20656910612 ps
CPU time 39.19 seconds
Started Jul 06 07:16:46 PM PDT 24
Finished Jul 06 07:17:26 PM PDT 24
Peak memory 217804 kb
Host smart-e0e5abcd-3620-446e-b1da-da9c5f727d6d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98924789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_l
c_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_erro
rs.98924789
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.524518013
Short name T626
Test name
Test status
Simulation time 122811021 ps
CPU time 2.14 seconds
Started Jul 06 07:17:01 PM PDT 24
Finished Jul 06 07:17:04 PM PDT 24
Peak memory 217136 kb
Host smart-456ea50b-5bea-4f83-9714-abf275050b56
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524518013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.524518013
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.3409351993
Short name T424
Test name
Test status
Simulation time 778392125 ps
CPU time 4.79 seconds
Started Jul 06 07:16:46 PM PDT 24
Finished Jul 06 07:16:52 PM PDT 24
Peak memory 221436 kb
Host smart-25e3e134-e502-48a9-b052-2f609824ab87
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409351993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.3409351993
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.285473793
Short name T668
Test name
Test status
Simulation time 5288875597 ps
CPU time 36.31 seconds
Started Jul 06 07:16:47 PM PDT 24
Finished Jul 06 07:17:24 PM PDT 24
Peak memory 217176 kb
Host smart-6f9e128c-3cb1-4f07-a6af-248e18c0fb97
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285473793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_regwen_during_op.285473793
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.53200903
Short name T498
Test name
Test status
Simulation time 1994162640 ps
CPU time 7.17 seconds
Started Jul 06 07:16:46 PM PDT 24
Finished Jul 06 07:16:54 PM PDT 24
Peak memory 217164 kb
Host smart-27e384e9-a885-4a7a-89c3-60a3fa5d0443
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53200903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.53200903
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.1104458671
Short name T428
Test name
Test status
Simulation time 1730890786 ps
CPU time 29.43 seconds
Started Jul 06 07:16:46 PM PDT 24
Finished Jul 06 07:17:16 PM PDT 24
Peak memory 250480 kb
Host smart-5aba8a95-f2ef-47a1-8d2e-01d388095ff4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104458671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.1104458671
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.4002900593
Short name T693
Test name
Test status
Simulation time 1759305523 ps
CPU time 32.06 seconds
Started Jul 06 07:16:47 PM PDT 24
Finished Jul 06 07:17:20 PM PDT 24
Peak memory 250480 kb
Host smart-3d276577-4081-43dd-8296-713e64bb8ef3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002900593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.4002900593
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.2755455430
Short name T471
Test name
Test status
Simulation time 242303920 ps
CPU time 2.98 seconds
Started Jul 06 07:16:41 PM PDT 24
Finished Jul 06 07:16:46 PM PDT 24
Peak memory 217772 kb
Host smart-02b1dc45-5084-417e-86c2-c641d34a521a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755455430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.2755455430
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.2310287242
Short name T517
Test name
Test status
Simulation time 704690418 ps
CPU time 5.38 seconds
Started Jul 06 07:16:40 PM PDT 24
Finished Jul 06 07:16:48 PM PDT 24
Peak memory 221716 kb
Host smart-deb7e0ce-d55a-46c3-91d1-152dbefa56cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310287242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.2310287242
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.1034426767
Short name T523
Test name
Test status
Simulation time 7650879638 ps
CPU time 16.18 seconds
Started Jul 06 07:16:45 PM PDT 24
Finished Jul 06 07:17:03 PM PDT 24
Peak memory 219496 kb
Host smart-e0513d05-2389-471d-9500-627031b9d16d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034426767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.1034426767
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.3864504748
Short name T490
Test name
Test status
Simulation time 1341322280 ps
CPU time 14 seconds
Started Jul 06 07:17:00 PM PDT 24
Finished Jul 06 07:17:15 PM PDT 24
Peak memory 225464 kb
Host smart-888f76c7-2a78-4977-8fb3-a012e96bf88b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864504748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.3864504748
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.3574918338
Short name T236
Test name
Test status
Simulation time 1316823109 ps
CPU time 8.08 seconds
Started Jul 06 07:16:46 PM PDT 24
Finished Jul 06 07:16:55 PM PDT 24
Peak memory 217780 kb
Host smart-9140c21b-e270-4872-b483-f85cd7478dcc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574918338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.3
574918338
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.1637277093
Short name T537
Test name
Test status
Simulation time 3385818517 ps
CPU time 18.24 seconds
Started Jul 06 07:16:42 PM PDT 24
Finished Jul 06 07:17:02 PM PDT 24
Peak memory 225620 kb
Host smart-d683cf77-2eb9-4240-b2da-5b5288d111d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637277093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.1637277093
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.2271779140
Short name T286
Test name
Test status
Simulation time 26192513 ps
CPU time 1.83 seconds
Started Jul 06 07:16:39 PM PDT 24
Finished Jul 06 07:16:42 PM PDT 24
Peak memory 217212 kb
Host smart-9f2a4db9-7cd9-4c8b-b0d6-f645d20cd385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271779140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.2271779140
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.2648974179
Short name T746
Test name
Test status
Simulation time 777348082 ps
CPU time 28.76 seconds
Started Jul 06 07:16:43 PM PDT 24
Finished Jul 06 07:17:13 PM PDT 24
Peak memory 250544 kb
Host smart-8eadb734-464e-4bac-9026-c2f509b2ce31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648974179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.2648974179
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.3795762774
Short name T226
Test name
Test status
Simulation time 263979594 ps
CPU time 2.95 seconds
Started Jul 06 07:16:41 PM PDT 24
Finished Jul 06 07:16:47 PM PDT 24
Peak memory 221800 kb
Host smart-92771c24-9059-4288-af21-2d735ff3660d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795762774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.3795762774
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.853515824
Short name T859
Test name
Test status
Simulation time 992857270 ps
CPU time 69.3 seconds
Started Jul 06 07:16:46 PM PDT 24
Finished Jul 06 07:17:57 PM PDT 24
Peak memory 275452 kb
Host smart-e3981305-64cd-4d49-9303-a3c51d7c1e29
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853515824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.853515824
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.3297427451
Short name T527
Test name
Test status
Simulation time 22470088 ps
CPU time 1.42 seconds
Started Jul 06 07:16:35 PM PDT 24
Finished Jul 06 07:16:37 PM PDT 24
Peak memory 217264 kb
Host smart-85877c29-1015-4b73-9fbc-359789ddbde2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297427451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.3297427451
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.4221965172
Short name T648
Test name
Test status
Simulation time 19861804 ps
CPU time 0.92 seconds
Started Jul 06 07:16:57 PM PDT 24
Finished Jul 06 07:17:00 PM PDT 24
Peak memory 208620 kb
Host smart-b8847be6-e72d-4298-b44a-382d05c8165a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221965172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.4221965172
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.4158895318
Short name T524
Test name
Test status
Simulation time 703173974 ps
CPU time 10.09 seconds
Started Jul 06 07:17:03 PM PDT 24
Finished Jul 06 07:17:15 PM PDT 24
Peak memory 217676 kb
Host smart-936ece50-b248-417e-b217-690fa12bb846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158895318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.4158895318
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.3729512389
Short name T218
Test name
Test status
Simulation time 78511693 ps
CPU time 1.72 seconds
Started Jul 06 07:16:51 PM PDT 24
Finished Jul 06 07:16:56 PM PDT 24
Peak memory 217212 kb
Host smart-f0edfb2e-8d1c-4f20-9467-4b6ad2d6a467
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729512389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.3729512389
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.3331654051
Short name T749
Test name
Test status
Simulation time 2627833626 ps
CPU time 71.94 seconds
Started Jul 06 07:16:52 PM PDT 24
Finished Jul 06 07:18:07 PM PDT 24
Peak memory 218744 kb
Host smart-3028a2f3-dd47-4404-8e3b-62baef631f50
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331654051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.3331654051
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.1695587768
Short name T21
Test name
Test status
Simulation time 655644745 ps
CPU time 15.07 seconds
Started Jul 06 07:17:02 PM PDT 24
Finished Jul 06 07:17:19 PM PDT 24
Peak memory 217220 kb
Host smart-8fe83846-560f-4531-89d6-b663044bebf0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695587768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.1
695587768
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.2746458992
Short name T485
Test name
Test status
Simulation time 325969934 ps
CPU time 10.32 seconds
Started Jul 06 07:16:53 PM PDT 24
Finished Jul 06 07:17:06 PM PDT 24
Peak memory 217720 kb
Host smart-1a20a37a-861e-4162-be63-d6baac3625fb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746458992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.2746458992
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.3829511471
Short name T101
Test name
Test status
Simulation time 3789187669 ps
CPU time 8.54 seconds
Started Jul 06 07:16:52 PM PDT 24
Finished Jul 06 07:17:04 PM PDT 24
Peak memory 217204 kb
Host smart-b34ff37d-86aa-4c40-957e-a29007cc3ae6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829511471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.3829511471
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.524037654
Short name T18
Test name
Test status
Simulation time 643366012 ps
CPU time 9.03 seconds
Started Jul 06 07:16:50 PM PDT 24
Finished Jul 06 07:17:03 PM PDT 24
Peak memory 217148 kb
Host smart-3f1231f4-b115-4e2f-b541-9d4b895774bf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524037654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.524037654
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.2474935534
Short name T261
Test name
Test status
Simulation time 420747885 ps
CPU time 13.79 seconds
Started Jul 06 07:16:56 PM PDT 24
Finished Jul 06 07:17:12 PM PDT 24
Peak memory 250416 kb
Host smart-956346db-912f-450a-94f6-8269997354f8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474935534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.2474935534
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.482559930
Short name T661
Test name
Test status
Simulation time 28568390 ps
CPU time 1.89 seconds
Started Jul 06 07:16:51 PM PDT 24
Finished Jul 06 07:16:57 PM PDT 24
Peak memory 221664 kb
Host smart-befd0bae-7925-42d2-8ab4-124a0bb56562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482559930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.482559930
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.2458774805
Short name T87
Test name
Test status
Simulation time 1190773973 ps
CPU time 9.82 seconds
Started Jul 06 07:16:52 PM PDT 24
Finished Jul 06 07:17:05 PM PDT 24
Peak memory 214260 kb
Host smart-035ed511-fe98-44cf-9dab-1f6c72cb29e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458774805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.2458774805
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.358492752
Short name T632
Test name
Test status
Simulation time 1059147304 ps
CPU time 11.56 seconds
Started Jul 06 07:16:51 PM PDT 24
Finished Jul 06 07:17:06 PM PDT 24
Peak memory 218420 kb
Host smart-17878ca8-9e58-427a-bfca-9e894af7f2ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358492752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.358492752
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.1840773320
Short name T777
Test name
Test status
Simulation time 713602390 ps
CPU time 15.44 seconds
Started Jul 06 07:16:53 PM PDT 24
Finished Jul 06 07:17:12 PM PDT 24
Peak memory 225504 kb
Host smart-7f09a79d-5414-4d57-9a82-bb522b47bbbc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840773320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.1840773320
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.1432111922
Short name T308
Test name
Test status
Simulation time 353419266 ps
CPU time 11.65 seconds
Started Jul 06 07:16:51 PM PDT 24
Finished Jul 06 07:17:06 PM PDT 24
Peak memory 225520 kb
Host smart-fbac521b-8f97-4625-b43e-f72a1dcede5a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432111922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.1
432111922
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.717709403
Short name T561
Test name
Test status
Simulation time 2653005198 ps
CPU time 10.47 seconds
Started Jul 06 07:16:50 PM PDT 24
Finished Jul 06 07:17:05 PM PDT 24
Peak memory 217900 kb
Host smart-c6f9de3c-ee7c-41d7-a682-73289bd43aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717709403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.717709403
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.1679648334
Short name T86
Test name
Test status
Simulation time 22392647 ps
CPU time 1.67 seconds
Started Jul 06 07:16:50 PM PDT 24
Finished Jul 06 07:16:56 PM PDT 24
Peak memory 217220 kb
Host smart-6bc66e0e-b764-47ee-b06e-92e319bb9462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679648334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.1679648334
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.3501871484
Short name T595
Test name
Test status
Simulation time 573547065 ps
CPU time 24.23 seconds
Started Jul 06 07:17:02 PM PDT 24
Finished Jul 06 07:17:28 PM PDT 24
Peak memory 250488 kb
Host smart-25f0deb9-2d02-419a-8ee6-2fe51de44419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501871484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.3501871484
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.1167668448
Short name T477
Test name
Test status
Simulation time 248569131 ps
CPU time 5.74 seconds
Started Jul 06 07:16:50 PM PDT 24
Finished Jul 06 07:17:00 PM PDT 24
Peak memory 246500 kb
Host smart-c3e0622c-c5ad-444e-896b-3366641635bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167668448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.1167668448
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.53148714
Short name T750
Test name
Test status
Simulation time 10563720185 ps
CPU time 75.99 seconds
Started Jul 06 07:16:52 PM PDT 24
Finished Jul 06 07:18:12 PM PDT 24
Peak memory 275924 kb
Host smart-87dd4c36-c503-4c6d-9d43-2d413eaea01f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53148714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.lc_ctrl_stress_all.53148714
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.4234678606
Short name T754
Test name
Test status
Simulation time 41720670 ps
CPU time 0.91 seconds
Started Jul 06 07:16:53 PM PDT 24
Finished Jul 06 07:16:57 PM PDT 24
Peak memory 211392 kb
Host smart-01833981-8e33-431e-ace5-e6dc26321c8f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234678606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.4234678606
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.2487303801
Short name T161
Test name
Test status
Simulation time 15238498 ps
CPU time 0.91 seconds
Started Jul 06 07:17:02 PM PDT 24
Finished Jul 06 07:17:04 PM PDT 24
Peak memory 208540 kb
Host smart-329ed190-76e6-4742-bcc8-e90cab4f67f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487303801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.2487303801
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.619655490
Short name T50
Test name
Test status
Simulation time 1466860648 ps
CPU time 10.67 seconds
Started Jul 06 07:16:56 PM PDT 24
Finished Jul 06 07:17:10 PM PDT 24
Peak memory 217784 kb
Host smart-80af961c-a387-4767-951b-7e54c296f504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619655490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.619655490
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.1478455560
Short name T422
Test name
Test status
Simulation time 389347895 ps
CPU time 10.11 seconds
Started Jul 06 07:17:03 PM PDT 24
Finished Jul 06 07:17:15 PM PDT 24
Peak memory 216776 kb
Host smart-f8d7df4d-e933-4fc8-bc0f-46883b256f17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478455560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.1478455560
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.3825189692
Short name T97
Test name
Test status
Simulation time 21134645923 ps
CPU time 30.49 seconds
Started Jul 06 07:16:57 PM PDT 24
Finished Jul 06 07:17:30 PM PDT 24
Peak memory 218288 kb
Host smart-01fdcfb5-2439-4d0b-8c0a-6de4f20e4e16
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825189692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.3825189692
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.415864992
Short name T639
Test name
Test status
Simulation time 259038047 ps
CPU time 7.38 seconds
Started Jul 06 07:16:56 PM PDT 24
Finished Jul 06 07:17:06 PM PDT 24
Peak memory 217232 kb
Host smart-14918432-4e20-43e4-8345-b85293ab17ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415864992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.415864992
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.2679584930
Short name T621
Test name
Test status
Simulation time 69415409 ps
CPU time 3.26 seconds
Started Jul 06 07:16:58 PM PDT 24
Finished Jul 06 07:17:03 PM PDT 24
Peak memory 217744 kb
Host smart-2cd2166d-001f-46e5-9648-65d0bfea68c4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679584930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.2679584930
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.2911559884
Short name T601
Test name
Test status
Simulation time 761317588 ps
CPU time 14.05 seconds
Started Jul 06 07:17:02 PM PDT 24
Finished Jul 06 07:17:17 PM PDT 24
Peak memory 217168 kb
Host smart-4a8b08a6-192e-4303-8dbb-a5e524c43f1e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911559884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.2911559884
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.113873619
Short name T73
Test name
Test status
Simulation time 339145213 ps
CPU time 1.81 seconds
Started Jul 06 07:16:58 PM PDT 24
Finished Jul 06 07:17:02 PM PDT 24
Peak memory 217160 kb
Host smart-9dc111bf-260a-4ab5-9be1-a610843dbc75
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113873619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.113873619
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.407719079
Short name T850
Test name
Test status
Simulation time 9399541013 ps
CPU time 51.27 seconds
Started Jul 06 07:16:57 PM PDT 24
Finished Jul 06 07:17:51 PM PDT 24
Peak memory 266988 kb
Host smart-22deee3e-83e3-4131-81fe-131df098c1b1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407719079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_state_failure.407719079
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.1454384104
Short name T403
Test name
Test status
Simulation time 1215644269 ps
CPU time 10.28 seconds
Started Jul 06 07:16:57 PM PDT 24
Finished Jul 06 07:17:10 PM PDT 24
Peak memory 250312 kb
Host smart-3514c581-650b-4d9e-ac41-460ff6202369
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454384104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.1454384104
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.2333469915
Short name T438
Test name
Test status
Simulation time 204220297 ps
CPU time 2.85 seconds
Started Jul 06 07:16:57 PM PDT 24
Finished Jul 06 07:17:02 PM PDT 24
Peak memory 217800 kb
Host smart-4304ce4b-c62b-4069-b4a1-bf6f393e64d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333469915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.2333469915
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.3772640623
Short name T93
Test name
Test status
Simulation time 931631464 ps
CPU time 13.81 seconds
Started Jul 06 07:16:57 PM PDT 24
Finished Jul 06 07:17:13 PM PDT 24
Peak memory 217280 kb
Host smart-92f9ec4d-745e-4799-9c48-647dc1c1ab73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772640623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.3772640623
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.2793232894
Short name T475
Test name
Test status
Simulation time 2009573410 ps
CPU time 22.19 seconds
Started Jul 06 07:17:05 PM PDT 24
Finished Jul 06 07:17:29 PM PDT 24
Peak memory 218008 kb
Host smart-2acf242a-0ab2-44f3-8025-cfe1f31a763a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793232894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.2793232894
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.3211650291
Short name T664
Test name
Test status
Simulation time 1228204870 ps
CPU time 13.35 seconds
Started Jul 06 07:17:01 PM PDT 24
Finished Jul 06 07:17:16 PM PDT 24
Peak memory 225520 kb
Host smart-0fd024c3-1c43-4ecd-a950-aafe308c0ee2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211650291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.3211650291
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.3887224249
Short name T365
Test name
Test status
Simulation time 1071952589 ps
CPU time 13.09 seconds
Started Jul 06 07:17:08 PM PDT 24
Finished Jul 06 07:17:24 PM PDT 24
Peak memory 217716 kb
Host smart-c4d15f23-464e-4c40-96e9-9f27463a3884
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887224249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.3
887224249
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.1764996684
Short name T591
Test name
Test status
Simulation time 1201350413 ps
CPU time 8.23 seconds
Started Jul 06 07:16:57 PM PDT 24
Finished Jul 06 07:17:07 PM PDT 24
Peak memory 225152 kb
Host smart-bf1407fb-2a73-41ea-85dc-a37277431433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764996684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.1764996684
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.3521053512
Short name T715
Test name
Test status
Simulation time 75907095 ps
CPU time 3.98 seconds
Started Jul 06 07:16:57 PM PDT 24
Finished Jul 06 07:17:03 PM PDT 24
Peak memory 217292 kb
Host smart-6b5fd114-ccae-44fb-881b-42b04c9c862b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521053512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.3521053512
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.3290358805
Short name T277
Test name
Test status
Simulation time 176166595 ps
CPU time 18.29 seconds
Started Jul 06 07:17:03 PM PDT 24
Finished Jul 06 07:17:23 PM PDT 24
Peak memory 243920 kb
Host smart-731e7f5e-8323-46ee-81be-0fd1aee4bae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290358805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.3290358805
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.675380651
Short name T276
Test name
Test status
Simulation time 60414503 ps
CPU time 5.95 seconds
Started Jul 06 07:16:56 PM PDT 24
Finished Jul 06 07:17:05 PM PDT 24
Peak memory 245844 kb
Host smart-b146199a-02f1-4b81-89ec-b0881982a780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675380651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.675380651
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.4000170414
Short name T605
Test name
Test status
Simulation time 1867833482 ps
CPU time 53.38 seconds
Started Jul 06 07:17:03 PM PDT 24
Finished Jul 06 07:17:58 PM PDT 24
Peak memory 217252 kb
Host smart-65ba6552-f47b-4e6f-8df2-218b4f3b8af9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000170414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.4000170414
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.2246030228
Short name T604
Test name
Test status
Simulation time 17149478 ps
CPU time 0.82 seconds
Started Jul 06 07:16:57 PM PDT 24
Finished Jul 06 07:17:00 PM PDT 24
Peak memory 208596 kb
Host smart-08be8f00-3d9f-4655-8c9d-587850a1ab19
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246030228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.2246030228
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.1013219100
Short name T259
Test name
Test status
Simulation time 31002058 ps
CPU time 1.04 seconds
Started Jul 06 07:17:09 PM PDT 24
Finished Jul 06 07:17:16 PM PDT 24
Peak memory 208536 kb
Host smart-f912e5b0-c3c0-4c2d-99d5-7a539e9f2e7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013219100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.1013219100
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.4085862109
Short name T439
Test name
Test status
Simulation time 33186655 ps
CPU time 0.81 seconds
Started Jul 06 07:17:04 PM PDT 24
Finished Jul 06 07:17:07 PM PDT 24
Peak memory 208496 kb
Host smart-c12a0b91-1e02-4f91-a21b-50b1deba7fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085862109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.4085862109
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.3936525694
Short name T720
Test name
Test status
Simulation time 298239710 ps
CPU time 11.96 seconds
Started Jul 06 07:17:04 PM PDT 24
Finished Jul 06 07:17:18 PM PDT 24
Peak memory 217776 kb
Host smart-d26daefd-702e-4da2-8e62-9e4f420abe33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936525694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.3936525694
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.3127684806
Short name T530
Test name
Test status
Simulation time 622414509 ps
CPU time 6.82 seconds
Started Jul 06 07:17:03 PM PDT 24
Finished Jul 06 07:17:11 PM PDT 24
Peak memory 216836 kb
Host smart-09dae3c6-b969-4510-9e55-1a08bc916a27
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127684806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.3127684806
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.102664806
Short name T369
Test name
Test status
Simulation time 3555113575 ps
CPU time 57.03 seconds
Started Jul 06 07:17:08 PM PDT 24
Finished Jul 06 07:18:07 PM PDT 24
Peak memory 218424 kb
Host smart-34535bb0-401c-488e-89fd-a10d8c3f7b02
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102664806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_err
ors.102664806
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.4180979270
Short name T644
Test name
Test status
Simulation time 610034664 ps
CPU time 5.79 seconds
Started Jul 06 07:17:02 PM PDT 24
Finished Jul 06 07:17:10 PM PDT 24
Peak memory 217212 kb
Host smart-7a8f1fc1-6168-4230-8272-a6ffe9bd9f4a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180979270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.4
180979270
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.3551520437
Short name T414
Test name
Test status
Simulation time 439003946 ps
CPU time 3.88 seconds
Started Jul 06 07:17:04 PM PDT 24
Finished Jul 06 07:17:10 PM PDT 24
Peak memory 217720 kb
Host smart-6d9fd05a-e7d1-4c60-868a-2e86d85359c4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551520437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.3551520437
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.4211821169
Short name T753
Test name
Test status
Simulation time 2590514927 ps
CPU time 11.15 seconds
Started Jul 06 07:17:05 PM PDT 24
Finished Jul 06 07:17:18 PM PDT 24
Peak memory 217220 kb
Host smart-64ee9d4f-6c18-4a57-a37c-9f2c9347d435
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211821169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.4211821169
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.3544448437
Short name T743
Test name
Test status
Simulation time 3128881353 ps
CPU time 5.05 seconds
Started Jul 06 07:17:04 PM PDT 24
Finished Jul 06 07:17:11 PM PDT 24
Peak memory 217216 kb
Host smart-9469b95f-66cc-456b-aea9-91f49fc77a19
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544448437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
3544448437
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.1660851387
Short name T540
Test name
Test status
Simulation time 2302066212 ps
CPU time 82.34 seconds
Started Jul 06 07:17:03 PM PDT 24
Finished Jul 06 07:18:27 PM PDT 24
Peak memory 267296 kb
Host smart-2c88f2be-b0dd-4ccc-94e9-81a318df8879
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660851387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.1660851387
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.3708193172
Short name T407
Test name
Test status
Simulation time 4646460263 ps
CPU time 16.86 seconds
Started Jul 06 07:17:03 PM PDT 24
Finished Jul 06 07:17:22 PM PDT 24
Peak memory 250256 kb
Host smart-4105a6da-7121-483c-a638-247412203ac6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708193172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.3708193172
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.647206855
Short name T657
Test name
Test status
Simulation time 160420454 ps
CPU time 1.94 seconds
Started Jul 06 07:17:02 PM PDT 24
Finished Jul 06 07:17:06 PM PDT 24
Peak memory 221808 kb
Host smart-24e6ac95-7f01-4f66-b162-bcc296d61b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647206855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.647206855
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.2628920425
Short name T433
Test name
Test status
Simulation time 1412582007 ps
CPU time 13.89 seconds
Started Jul 06 07:17:02 PM PDT 24
Finished Jul 06 07:17:17 PM PDT 24
Peak memory 217208 kb
Host smart-940503f1-b5cd-41db-9213-f17b9b53f56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628920425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.2628920425
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.762204663
Short name T353
Test name
Test status
Simulation time 310175541 ps
CPU time 15.2 seconds
Started Jul 06 07:17:03 PM PDT 24
Finished Jul 06 07:17:21 PM PDT 24
Peak memory 225548 kb
Host smart-c556d995-9dfc-4c1f-bfe1-4eda6acaa578
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762204663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.762204663
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.2665844855
Short name T43
Test name
Test status
Simulation time 2102180528 ps
CPU time 14.09 seconds
Started Jul 06 07:17:03 PM PDT 24
Finished Jul 06 07:17:19 PM PDT 24
Peak memory 225520 kb
Host smart-9e9dbeac-0857-4eda-80cc-3c24bc830c31
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665844855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.2665844855
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.909480110
Short name T441
Test name
Test status
Simulation time 1117525998 ps
CPU time 11.37 seconds
Started Jul 06 07:17:05 PM PDT 24
Finished Jul 06 07:17:18 PM PDT 24
Peak memory 217708 kb
Host smart-48bab502-4000-4f79-a8ae-19d045f4c8bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909480110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.909480110
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.2877589409
Short name T274
Test name
Test status
Simulation time 1322235431 ps
CPU time 8.06 seconds
Started Jul 06 07:17:02 PM PDT 24
Finished Jul 06 07:17:12 PM PDT 24
Peak memory 224264 kb
Host smart-a1d862cb-573d-49d1-9c9e-d30f7c140aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877589409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.2877589409
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.1292515704
Short name T232
Test name
Test status
Simulation time 337778978 ps
CPU time 3.85 seconds
Started Jul 06 07:17:08 PM PDT 24
Finished Jul 06 07:17:14 PM PDT 24
Peak memory 217200 kb
Host smart-cec2e405-4114-4733-bbb4-178325be3225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292515704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.1292515704
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.420756100
Short name T580
Test name
Test status
Simulation time 388540455 ps
CPU time 29.17 seconds
Started Jul 06 07:17:08 PM PDT 24
Finished Jul 06 07:17:40 PM PDT 24
Peak memory 250536 kb
Host smart-cec1ffac-c7c7-4b49-a04a-2697b1039675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420756100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.420756100
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.3728759340
Short name T612
Test name
Test status
Simulation time 154634928 ps
CPU time 9.62 seconds
Started Jul 06 07:17:05 PM PDT 24
Finished Jul 06 07:17:16 PM PDT 24
Peak memory 250592 kb
Host smart-02aa468f-eb31-42ba-ab04-d936d184d44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728759340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.3728759340
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.4525970
Short name T744
Test name
Test status
Simulation time 4437864889 ps
CPU time 61.41 seconds
Started Jul 06 07:17:08 PM PDT 24
Finished Jul 06 07:18:11 PM PDT 24
Peak memory 267676 kb
Host smart-c4a3d0e8-3c5c-4cb2-b39c-273fffea12ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4525970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TE
ST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
lc_ctrl_stress_all.4525970
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.3339380606
Short name T84
Test name
Test status
Simulation time 61714089565 ps
CPU time 1941.75 seconds
Started Jul 06 07:17:12 PM PDT 24
Finished Jul 06 07:49:40 PM PDT 24
Peak memory 774708 kb
Host smart-cc597026-cbf7-4295-a939-fd506d206343
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3339380606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.3339380606
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.1979088058
Short name T183
Test name
Test status
Simulation time 76848088 ps
CPU time 0.97 seconds
Started Jul 06 07:17:04 PM PDT 24
Finished Jul 06 07:17:07 PM PDT 24
Peak memory 212392 kb
Host smart-512cc9d6-fee9-42b4-8da0-efba20405cb5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979088058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.1979088058
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.733258231
Short name T250
Test name
Test status
Simulation time 22563654 ps
CPU time 1.04 seconds
Started Jul 06 07:17:13 PM PDT 24
Finished Jul 06 07:17:19 PM PDT 24
Peak memory 208484 kb
Host smart-f62ac01e-1095-4645-aa9a-c89182a6fefc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733258231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.733258231
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.2204635423
Short name T220
Test name
Test status
Simulation time 21208120 ps
CPU time 0.82 seconds
Started Jul 06 07:17:09 PM PDT 24
Finished Jul 06 07:17:16 PM PDT 24
Peak memory 208552 kb
Host smart-82cd0b19-67c6-44f9-94da-0593e9fe06ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204635423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.2204635423
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.1664094561
Short name T702
Test name
Test status
Simulation time 1639772804 ps
CPU time 17.08 seconds
Started Jul 06 07:17:15 PM PDT 24
Finished Jul 06 07:17:37 PM PDT 24
Peak memory 217744 kb
Host smart-6314df48-d72b-448f-8510-1865f700e8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664094561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.1664094561
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.450073977
Short name T714
Test name
Test status
Simulation time 1016776753 ps
CPU time 6.38 seconds
Started Jul 06 07:17:10 PM PDT 24
Finished Jul 06 07:17:22 PM PDT 24
Peak memory 217224 kb
Host smart-829dc2a2-1cb0-4070-9123-296c1c0c01c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450073977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.450073977
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.1355623391
Short name T372
Test name
Test status
Simulation time 2307521809 ps
CPU time 34.92 seconds
Started Jul 06 07:17:07 PM PDT 24
Finished Jul 06 07:17:43 PM PDT 24
Peak memory 218516 kb
Host smart-bb73fef2-1528-4139-b634-4d422cb9e2db
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355623391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.1355623391
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.1896408288
Short name T69
Test name
Test status
Simulation time 539568071 ps
CPU time 6.53 seconds
Started Jul 06 07:17:11 PM PDT 24
Finished Jul 06 07:17:23 PM PDT 24
Peak memory 217208 kb
Host smart-1cd38f1e-760e-41df-b28e-825758c5c1dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896408288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.1
896408288
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.561511073
Short name T323
Test name
Test status
Simulation time 635080951 ps
CPU time 9.64 seconds
Started Jul 06 07:17:15 PM PDT 24
Finished Jul 06 07:17:30 PM PDT 24
Peak memory 217684 kb
Host smart-761ed99e-4431-4e4c-9a08-cd77c1a8a2a6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561511073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_
prog_failure.561511073
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.2907105171
Short name T381
Test name
Test status
Simulation time 2264799988 ps
CPU time 32.53 seconds
Started Jul 06 07:17:08 PM PDT 24
Finished Jul 06 07:17:41 PM PDT 24
Peak memory 217172 kb
Host smart-8f3eb733-2e4e-4b5c-bb3d-976fe27c561a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907105171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.2907105171
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.2403663657
Short name T445
Test name
Test status
Simulation time 1133667962 ps
CPU time 4.21 seconds
Started Jul 06 07:17:09 PM PDT 24
Finished Jul 06 07:17:18 PM PDT 24
Peak memory 217160 kb
Host smart-6870d5b5-1813-4857-9539-3951c5ac858c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403663657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
2403663657
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.3464214606
Short name T790
Test name
Test status
Simulation time 6845987573 ps
CPU time 45.07 seconds
Started Jul 06 07:17:15 PM PDT 24
Finished Jul 06 07:18:05 PM PDT 24
Peak memory 266884 kb
Host smart-d5fba93c-5bf6-4dda-88bd-8a69120504d9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464214606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.3464214606
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.3448065431
Short name T320
Test name
Test status
Simulation time 2246104802 ps
CPU time 18.3 seconds
Started Jul 06 07:17:10 PM PDT 24
Finished Jul 06 07:17:34 PM PDT 24
Peak memory 249088 kb
Host smart-7b9f0b90-f487-4323-81bd-672b7569f061
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448065431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.3448065431
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.3803291061
Short name T721
Test name
Test status
Simulation time 146260598 ps
CPU time 3.83 seconds
Started Jul 06 07:17:07 PM PDT 24
Finished Jul 06 07:17:12 PM PDT 24
Peak memory 217776 kb
Host smart-e563366a-b56f-4e77-ad13-ad60c95ca474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803291061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.3803291061
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.1035543211
Short name T62
Test name
Test status
Simulation time 1313061825 ps
CPU time 24.32 seconds
Started Jul 06 07:17:07 PM PDT 24
Finished Jul 06 07:17:33 PM PDT 24
Peak memory 214252 kb
Host smart-84208e56-0926-4e0e-aea9-383c16d13572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035543211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.1035543211
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.1127329053
Short name T841
Test name
Test status
Simulation time 1551637335 ps
CPU time 16.72 seconds
Started Jul 06 07:17:15 PM PDT 24
Finished Jul 06 07:17:37 PM PDT 24
Peak memory 218564 kb
Host smart-bafd4d7d-640e-4e1c-a307-ef3aa09f1a16
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127329053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.1127329053
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.2194803404
Short name T636
Test name
Test status
Simulation time 1018815451 ps
CPU time 11.4 seconds
Started Jul 06 07:17:10 PM PDT 24
Finished Jul 06 07:17:27 PM PDT 24
Peak memory 217756 kb
Host smart-3b052cca-fea0-40f3-adad-6b0bcef72de9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194803404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.2194803404
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.3573188335
Short name T30
Test name
Test status
Simulation time 2763024301 ps
CPU time 13.51 seconds
Started Jul 06 07:17:10 PM PDT 24
Finished Jul 06 07:17:29 PM PDT 24
Peak memory 225592 kb
Host smart-fadf21cb-78bc-45d4-899b-1c80f6211335
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573188335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.3
573188335
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.1401698129
Short name T224
Test name
Test status
Simulation time 417409620 ps
CPU time 15.1 seconds
Started Jul 06 07:17:09 PM PDT 24
Finished Jul 06 07:17:29 PM PDT 24
Peak memory 225600 kb
Host smart-416ea253-ae73-4bd6-86a8-2fd97651bf27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401698129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.1401698129
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.3236924071
Short name T705
Test name
Test status
Simulation time 228759117 ps
CPU time 6.76 seconds
Started Jul 06 07:17:10 PM PDT 24
Finished Jul 06 07:17:22 PM PDT 24
Peak memory 217216 kb
Host smart-29839d63-f576-498e-a842-d8806b545034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236924071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.3236924071
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.31839109
Short name T495
Test name
Test status
Simulation time 4468565137 ps
CPU time 31.9 seconds
Started Jul 06 07:17:15 PM PDT 24
Finished Jul 06 07:17:52 PM PDT 24
Peak memory 250628 kb
Host smart-a3ee0897-304d-4988-bc32-db76dabdf23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31839109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.31839109
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.1939245845
Short name T586
Test name
Test status
Simulation time 534077476 ps
CPU time 7.67 seconds
Started Jul 06 07:17:09 PM PDT 24
Finished Jul 06 07:17:22 PM PDT 24
Peak memory 250540 kb
Host smart-02a66c2e-3cd2-4e4a-8e14-7721d2b932cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939245845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.1939245845
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.3114879211
Short name T809
Test name
Test status
Simulation time 70907559308 ps
CPU time 528.93 seconds
Started Jul 06 07:17:14 PM PDT 24
Finished Jul 06 07:26:08 PM PDT 24
Peak memory 288120 kb
Host smart-0ddbf8f4-f457-4a76-824a-fbfdaa3f9a63
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114879211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.3114879211
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.901180
Short name T610
Test name
Test status
Simulation time 30736284 ps
CPU time 0.95 seconds
Started Jul 06 07:17:07 PM PDT 24
Finished Jul 06 07:17:09 PM PDT 24
Peak memory 217180 kb
Host smart-bf6e79f0-cb0a-46d9-90e6-3191ebbf1dd9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volat
ile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_v
olatile_unlock_smoke.901180
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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