Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49051 |
1 |
|
|
T1 |
16 |
|
T2 |
1055 |
|
T3 |
15 |
auto[1] |
1709 |
1 |
|
|
T2 |
27 |
|
T10 |
7 |
|
T39 |
11 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50120 |
1 |
|
|
T1 |
16 |
|
T2 |
1082 |
|
T3 |
15 |
auto[1] |
640 |
1 |
|
|
T14 |
15 |
|
T71 |
15 |
|
T72 |
5 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49076 |
1 |
|
|
T1 |
16 |
|
T2 |
1016 |
|
T3 |
14 |
auto[1] |
1684 |
1 |
|
|
T2 |
66 |
|
T3 |
1 |
|
T13 |
6 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49060 |
1 |
|
|
T1 |
16 |
|
T2 |
995 |
|
T3 |
15 |
auto[1] |
1700 |
1 |
|
|
T2 |
87 |
|
T13 |
8 |
|
T15 |
1 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48992 |
1 |
|
|
T1 |
16 |
|
T2 |
1012 |
|
T3 |
14 |
auto[1] |
1768 |
1 |
|
|
T2 |
70 |
|
T3 |
1 |
|
T13 |
7 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
45839 |
1 |
|
|
T2 |
962 |
|
T3 |
7 |
|
T8 |
55 |
no_err_inj |
4921 |
1 |
|
|
T1 |
16 |
|
T2 |
120 |
|
T3 |
8 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49117 |
1 |
|
|
T1 |
16 |
|
T2 |
1044 |
|
T3 |
15 |
auto[1] |
1643 |
1 |
|
|
T2 |
38 |
|
T10 |
8 |
|
T39 |
13 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50147 |
1 |
|
|
T1 |
16 |
|
T2 |
1082 |
|
T3 |
15 |
auto[1] |
613 |
1 |
|
|
T14 |
5 |
|
T71 |
12 |
|
T72 |
15 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
37233 |
1 |
|
|
T2 |
601 |
|
T7 |
13 |
|
T8 |
55 |
auto[1] |
13527 |
1 |
|
|
T1 |
16 |
|
T2 |
481 |
|
T3 |
15 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49035 |
1 |
|
|
T1 |
16 |
|
T2 |
1014 |
|
T3 |
14 |
auto[1] |
1725 |
1 |
|
|
T2 |
68 |
|
T3 |
1 |
|
T13 |
9 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49036 |
1 |
|
|
T1 |
16 |
|
T2 |
1014 |
|
T3 |
15 |
auto[1] |
1724 |
1 |
|
|
T2 |
68 |
|
T13 |
6 |
|
T17 |
14 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49095 |
1 |
|
|
T1 |
16 |
|
T2 |
1004 |
|
T3 |
14 |
auto[1] |
1665 |
1 |
|
|
T2 |
78 |
|
T3 |
1 |
|
T13 |
10 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49067 |
1 |
|
|
T1 |
16 |
|
T2 |
1048 |
|
T3 |
15 |
auto[1] |
1693 |
1 |
|
|
T2 |
34 |
|
T10 |
7 |
|
T39 |
12 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48608 |
1 |
|
|
T1 |
16 |
|
T2 |
1015 |
|
T3 |
15 |
auto[1] |
2152 |
1 |
|
|
T2 |
67 |
|
T30 |
5 |
|
T68 |
14 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50118 |
1 |
|
|
T1 |
16 |
|
T2 |
1082 |
|
T3 |
15 |
auto[1] |
642 |
1 |
|
|
T14 |
10 |
|
T71 |
13 |
|
T72 |
12 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50140 |
1 |
|
|
T1 |
16 |
|
T2 |
1082 |
|
T3 |
15 |
auto[1] |
620 |
1 |
|
|
T14 |
12 |
|
T71 |
11 |
|
T72 |
8 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50129 |
1 |
|
|
T1 |
16 |
|
T2 |
1082 |
|
T3 |
15 |
auto[1] |
631 |
1 |
|
|
T14 |
19 |
|
T71 |
15 |
|
T72 |
12 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48047 |
1 |
|
|
T1 |
16 |
|
T2 |
1008 |
|
T7 |
13 |
auto[1] |
2713 |
1 |
|
|
T2 |
74 |
|
T3 |
15 |
|
T15 |
11 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47030 |
1 |
|
|
T1 |
16 |
|
T2 |
1082 |
|
T3 |
15 |
auto[1] |
3730 |
1 |
|
|
T8 |
55 |
|
T31 |
66 |
|
T42 |
51 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49024 |
1 |
|
|
T1 |
16 |
|
T2 |
1010 |
|
T3 |
14 |
auto[1] |
1736 |
1 |
|
|
T2 |
72 |
|
T3 |
1 |
|
T13 |
8 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49060 |
1 |
|
|
T1 |
16 |
|
T2 |
1014 |
|
T3 |
14 |
auto[1] |
1700 |
1 |
|
|
T2 |
68 |
|
T3 |
1 |
|
T13 |
12 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49016 |
1 |
|
|
T1 |
16 |
|
T2 |
1019 |
|
T3 |
14 |
auto[1] |
1744 |
1 |
|
|
T2 |
63 |
|
T3 |
1 |
|
T13 |
11 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49091 |
1 |
|
|
T1 |
16 |
|
T2 |
1052 |
|
T3 |
15 |
auto[1] |
1669 |
1 |
|
|
T2 |
30 |
|
T10 |
7 |
|
T39 |
12 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
45340 |
1 |
|
|
T1 |
16 |
|
T2 |
1052 |
|
T3 |
15 |
auto[1] |
5420 |
1 |
|
|
T2 |
30 |
|
T9 |
65 |
|
T10 |
5 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46714 |
1 |
|
|
T1 |
16 |
|
T2 |
1082 |
|
T3 |
15 |
auto[1] |
4046 |
1 |
|
|
T57 |
100 |
|
T69 |
65 |
|
T70 |
60 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50760 |
1 |
|
|
T1 |
16 |
|
T2 |
1082 |
|
T3 |
15 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49090 |
1 |
|
|
T1 |
16 |
|
T2 |
1059 |
|
T3 |
15 |
auto[1] |
1670 |
1 |
|
|
T2 |
23 |
|
T10 |
6 |
|
T39 |
12 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49029 |
1 |
|
|
T1 |
16 |
|
T2 |
1040 |
|
T3 |
15 |
auto[1] |
1731 |
1 |
|
|
T2 |
42 |
|
T10 |
4 |
|
T39 |
11 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48976 |
1 |
|
|
T1 |
16 |
|
T2 |
1051 |
|
T3 |
15 |
auto[1] |
1784 |
1 |
|
|
T2 |
31 |
|
T10 |
8 |
|
T39 |
12 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
44498 |
1 |
|
|
T2 |
928 |
|
T8 |
55 |
|
T9 |
65 |
auto[0] |
no_err_inj |
3549 |
1 |
|
|
T1 |
16 |
|
T2 |
80 |
|
T7 |
13 |
auto[1] |
err_inj |
1341 |
1 |
|
|
T2 |
34 |
|
T3 |
7 |
|
T15 |
6 |
auto[1] |
no_err_inj |
1372 |
1 |
|
|
T2 |
40 |
|
T3 |
8 |
|
T15 |
5 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
46479 |
1 |
|
|
T1 |
16 |
|
T2 |
941 |
|
T7 |
13 |
auto[0] |
auto[1] |
1568 |
1 |
|
|
T2 |
67 |
|
T13 |
12 |
|
T17 |
11 |
auto[1] |
auto[0] |
2581 |
1 |
|
|
T2 |
73 |
|
T3 |
14 |
|
T15 |
11 |
auto[1] |
auto[1] |
132 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T40 |
2 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
46469 |
1 |
|
|
T1 |
16 |
|
T2 |
944 |
|
T7 |
13 |
auto[0] |
auto[1] |
1578 |
1 |
|
|
T2 |
64 |
|
T13 |
6 |
|
T17 |
14 |
auto[1] |
auto[0] |
2567 |
1 |
|
|
T2 |
70 |
|
T3 |
15 |
|
T15 |
11 |
auto[1] |
auto[1] |
146 |
1 |
|
|
T2 |
4 |
|
T35 |
2 |
|
T40 |
2 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
46458 |
1 |
|
|
T1 |
16 |
|
T2 |
951 |
|
T7 |
13 |
auto[0] |
auto[1] |
1589 |
1 |
|
|
T2 |
57 |
|
T13 |
11 |
|
T17 |
6 |
auto[1] |
auto[0] |
2558 |
1 |
|
|
T2 |
68 |
|
T3 |
14 |
|
T15 |
11 |
auto[1] |
auto[1] |
155 |
1 |
|
|
T2 |
6 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
46502 |
1 |
|
|
T1 |
16 |
|
T2 |
926 |
|
T7 |
13 |
auto[0] |
auto[1] |
1545 |
1 |
|
|
T2 |
82 |
|
T13 |
8 |
|
T17 |
8 |
auto[1] |
auto[0] |
2558 |
1 |
|
|
T2 |
69 |
|
T3 |
15 |
|
T15 |
10 |
auto[1] |
auto[1] |
155 |
1 |
|
|
T2 |
5 |
|
T15 |
1 |
|
T41 |
5 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
46448 |
1 |
|
|
T1 |
16 |
|
T2 |
942 |
|
T7 |
13 |
auto[0] |
auto[1] |
1599 |
1 |
|
|
T2 |
66 |
|
T13 |
7 |
|
T17 |
13 |
auto[1] |
auto[0] |
2544 |
1 |
|
|
T2 |
70 |
|
T3 |
14 |
|
T15 |
9 |
auto[1] |
auto[1] |
169 |
1 |
|
|
T2 |
4 |
|
T3 |
1 |
|
T15 |
2 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
46490 |
1 |
|
|
T1 |
16 |
|
T2 |
943 |
|
T7 |
13 |
auto[0] |
auto[1] |
1557 |
1 |
|
|
T2 |
65 |
|
T13 |
6 |
|
T17 |
7 |
auto[1] |
auto[0] |
2586 |
1 |
|
|
T2 |
73 |
|
T3 |
14 |
|
T15 |
11 |
auto[1] |
auto[1] |
127 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36150 |
1 |
|
|
T2 |
581 |
|
T7 |
13 |
|
T8 |
55 |
auto[0] |
auto[1] |
1083 |
1 |
|
|
T2 |
20 |
|
T10 |
7 |
|
T39 |
11 |
auto[1] |
auto[0] |
12901 |
1 |
|
|
T1 |
16 |
|
T2 |
474 |
|
T3 |
15 |
auto[1] |
auto[1] |
626 |
1 |
|
|
T2 |
7 |
|
T19 |
6 |
|
T92 |
8 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36209 |
1 |
|
|
T2 |
580 |
|
T7 |
13 |
|
T8 |
55 |
auto[0] |
auto[1] |
1024 |
1 |
|
|
T2 |
21 |
|
T10 |
8 |
|
T39 |
13 |
auto[1] |
auto[0] |
12908 |
1 |
|
|
T1 |
16 |
|
T2 |
464 |
|
T3 |
15 |
auto[1] |
auto[1] |
619 |
1 |
|
|
T2 |
17 |
|
T19 |
15 |
|
T92 |
12 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36042 |
1 |
|
|
T2 |
585 |
|
T7 |
13 |
|
T8 |
55 |
auto[0] |
auto[1] |
1191 |
1 |
|
|
T2 |
16 |
|
T30 |
5 |
|
T68 |
14 |
auto[1] |
auto[0] |
12566 |
1 |
|
|
T1 |
16 |
|
T2 |
430 |
|
T3 |
15 |
auto[1] |
auto[1] |
961 |
1 |
|
|
T2 |
51 |
|
T19 |
20 |
|
T40 |
36 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36182 |
1 |
|
|
T2 |
574 |
|
T7 |
13 |
|
T8 |
55 |
auto[0] |
auto[1] |
1051 |
1 |
|
|
T2 |
27 |
|
T10 |
7 |
|
T39 |
12 |
auto[1] |
auto[0] |
12885 |
1 |
|
|
T1 |
16 |
|
T2 |
474 |
|
T3 |
15 |
auto[1] |
auto[1] |
642 |
1 |
|
|
T2 |
7 |
|
T19 |
13 |
|
T92 |
10 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
32424 |
1 |
|
|
T2 |
581 |
|
T7 |
13 |
|
T8 |
55 |
auto[0] |
auto[1] |
4809 |
1 |
|
|
T2 |
20 |
|
T9 |
65 |
|
T10 |
5 |
auto[1] |
auto[0] |
12916 |
1 |
|
|
T1 |
16 |
|
T2 |
471 |
|
T3 |
15 |
auto[1] |
auto[1] |
611 |
1 |
|
|
T2 |
10 |
|
T19 |
5 |
|
T92 |
13 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36122 |
1 |
|
|
T2 |
558 |
|
T7 |
13 |
|
T8 |
55 |
auto[0] |
auto[1] |
1111 |
1 |
|
|
T2 |
43 |
|
T13 |
12 |
|
T27 |
6 |
auto[1] |
auto[0] |
12938 |
1 |
|
|
T1 |
16 |
|
T2 |
456 |
|
T3 |
14 |
auto[1] |
auto[1] |
589 |
1 |
|
|
T2 |
25 |
|
T3 |
1 |
|
T17 |
11 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36128 |
1 |
|
|
T2 |
564 |
|
T7 |
13 |
|
T8 |
55 |
auto[0] |
auto[1] |
1105 |
1 |
|
|
T2 |
37 |
|
T13 |
8 |
|
T27 |
5 |
auto[1] |
auto[0] |
12896 |
1 |
|
|
T1 |
16 |
|
T2 |
446 |
|
T3 |
14 |
auto[1] |
auto[1] |
631 |
1 |
|
|
T2 |
35 |
|
T3 |
1 |
|
T16 |
2 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36136 |
1 |
|
|
T2 |
561 |
|
T7 |
13 |
|
T8 |
55 |
auto[0] |
auto[1] |
1097 |
1 |
|
|
T2 |
40 |
|
T13 |
6 |
|
T27 |
10 |
auto[1] |
auto[0] |
12900 |
1 |
|
|
T1 |
16 |
|
T2 |
453 |
|
T3 |
15 |
auto[1] |
auto[1] |
627 |
1 |
|
|
T2 |
28 |
|
T17 |
14 |
|
T19 |
3 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36152 |
1 |
|
|
T2 |
561 |
|
T7 |
13 |
|
T8 |
55 |
auto[0] |
auto[1] |
1081 |
1 |
|
|
T2 |
40 |
|
T13 |
9 |
|
T27 |
4 |
auto[1] |
auto[0] |
12883 |
1 |
|
|
T1 |
16 |
|
T2 |
453 |
|
T3 |
14 |
auto[1] |
auto[1] |
644 |
1 |
|
|
T2 |
28 |
|
T3 |
1 |
|
T15 |
1 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36165 |
1 |
|
|
T2 |
557 |
|
T7 |
13 |
|
T8 |
55 |
auto[0] |
auto[1] |
1068 |
1 |
|
|
T2 |
44 |
|
T13 |
8 |
|
T27 |
7 |
auto[1] |
auto[0] |
12895 |
1 |
|
|
T1 |
16 |
|
T2 |
438 |
|
T3 |
15 |
auto[1] |
auto[1] |
632 |
1 |
|
|
T2 |
43 |
|
T15 |
1 |
|
T17 |
8 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36169 |
1 |
|
|
T2 |
558 |
|
T7 |
13 |
|
T8 |
55 |
auto[0] |
auto[1] |
1064 |
1 |
|
|
T2 |
43 |
|
T13 |
6 |
|
T27 |
9 |
auto[1] |
auto[0] |
12907 |
1 |
|
|
T1 |
16 |
|
T2 |
458 |
|
T3 |
14 |
auto[1] |
auto[1] |
620 |
1 |
|
|
T2 |
23 |
|
T3 |
1 |
|
T16 |
1 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36103 |
1 |
|
|
T2 |
584 |
|
T7 |
13 |
|
T8 |
55 |
auto[0] |
auto[1] |
1130 |
1 |
|
|
T2 |
17 |
|
T10 |
8 |
|
T39 |
12 |
auto[1] |
auto[0] |
12873 |
1 |
|
|
T1 |
16 |
|
T2 |
467 |
|
T3 |
15 |
auto[1] |
auto[1] |
654 |
1 |
|
|
T2 |
14 |
|
T19 |
17 |
|
T92 |
13 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36129 |
1 |
|
|
T2 |
580 |
|
T7 |
13 |
|
T8 |
55 |
auto[0] |
auto[1] |
1104 |
1 |
|
|
T2 |
21 |
|
T10 |
4 |
|
T39 |
11 |
auto[1] |
auto[0] |
12900 |
1 |
|
|
T1 |
16 |
|
T2 |
460 |
|
T3 |
15 |
auto[1] |
auto[1] |
627 |
1 |
|
|
T2 |
21 |
|
T19 |
11 |
|
T92 |
10 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35642 |
1 |
|
|
T2 |
579 |
|
T7 |
13 |
|
T8 |
55 |
auto[0] |
auto[1] |
1591 |
1 |
|
|
T2 |
22 |
|
T35 |
13 |
|
T40 |
14 |
auto[1] |
auto[0] |
12405 |
1 |
|
|
T1 |
16 |
|
T2 |
429 |
|
T17 |
97 |
auto[1] |
auto[1] |
1122 |
1 |
|
|
T2 |
52 |
|
T3 |
15 |
|
T15 |
11 |