Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

101311344

1

T1

39824

T2

258248

T3

49839

auto[1]

1309903

1

T2

31910

T3

98

T8

6501

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

101313275

1

T1

39824

T2

258777

T3

49545

auto[1]

1307972

1

T2

26611

T3

392

T8

7914

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	6646246	1			T1	1512		T2	157022		T3	3233
auto[IdleSt]	22518902	1			T1	30423		T2	268994		T3	10109
auto[ClkMuxSt]	34343	1			T1	16		T2	445		T3	8
auto[CntIncrSt]	33991	1			T1	16		T2	440		T3	8
auto[CntProgSt]	1326640	1			T1	342		T2	10812		T3	116
auto[TransCheckSt]	26765	1			T1	16		T2	304		T3	8
auto[TokenHashSt]	41310937	1			T1	805		T2	151669		T3	192
auto[FlashRmaSt]	34363	1			T1	77		T2	554		T3	31
auto[TokenCheck0St]	12272	1			T1	16		T2	182		T3	8
auto[TokenCheck1St]	9259	1			T1	16		T2	147		T3	8
auto[TransProgSt]	348973	1			T1	430		T2	4231		T3	162
auto[PostTransSt]	13174505	1			T1	6155		T2	181495		T3	17809
auto[ScrapSt]	158004	1			T2	764		T31	3		T42	6
auto[EscalateSt]	6459444	1			T2	170596		T3	7242		T8	10659
auto[InvalidSt]	10524818	1			T2	301640		T3	11003		T13	7961

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1785	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	10524818	1			T2	301640		T3	11003		T13	7961
EscalateSt	6459444	1			T2	170596		T3	7242		T8	10659
ScrapSt	158004	1			T2	764		T31	3		T42	6
PostTransSt	13174505	1			T1	6155		T2	181495		T3	17809
TransProgSt	348973	1			T1	430		T2	4231		T3	162
TokenCheck1St	9259	1			T1	16		T2	147		T3	8
TokenCheck0St	12272	1			T1	16		T2	182		T3	8
FlashRmaSt	34363	1			T1	77		T2	554		T3	31
TokenHashSt	41310937	1			T1	805		T2	151669		T3	192
TransCheckSt	26765	1			T1	16		T2	304		T3	8
CntProgSt	1326640	1			T1	342		T2	10812		T3	116
CntIncrSt	33991	1			T1	16		T2	440		T3	8
ClkMuxSt	34343	1			T1	16		T2	445		T3	8
IdleSt	22518902	1			T1	30423		T2	268994		T3	10109
ResetSt	6646246	1			T1	1512		T2	157022		T3	3233
arcs[ResetSt=>IdleSt]	51097	1			T1	16		T2	1032		T3	15
arcs[IdleSt=>ScrapSt]	289	1			T2	4		T31	1		T42	2
arcs[IdleSt=>ClkMuxSt]	34060	1			T1	16		T2	440		T3	8
arcs[ClkMuxSt=>CntIncrSt]	33991	1			T1	16		T2	440		T3	8
arcs[CntIncrSt=>PostTransSt]	1731	1			T2	42		T10	4		T39	11
arcs[CntIncrSt=>CntProgSt]	32200	1			T1	16		T2	398		T3	8
arcs[CntProgSt=>PostTransSt]	4471	1			T2	94		T10	7		T14	15
arcs[CntProgSt=>TransCheckSt]	26765	1			T1	16		T2	304		T3	8
arcs[TransCheckSt=>PostTransSt]	3806	1			T2	31		T10	8		T57	44
arcs[TransCheckSt=>TokenHashSt]	22822	1			T1	16		T2	273		T3	8
arcs[TokenHashSt=>PostTransSt]	9676	1			T2	91		T9	65		T10	18
arcs[TokenHashSt=>FlashRmaSt]	12365	1			T1	16		T2	182		T3	8
arcs[FlashRmaSt=>TokenCheck0St]	12272	1			T1	16		T2	182		T3	8
arcs[TokenCheck0St=>PostTransSt]	2983	1			T2	35		T10	8		T14	5
arcs[TokenCheck0St=>TokenCheck1St]	9259	1			T1	16		T2	147		T3	8
arcs[TokenCheck1St=>PostTransSt]	722	1			T2	3		T57	19		T65	1
arcs[TransProgSt=>PostTransSt]	7756	1			T1	16		T2	144		T3	8
arcs[IdleSt=>EscalateSt]	195	1			T8	3		T31	3		T42	1
arcs[ClkMuxSt=>EscalateSt]	69	1			T8	3		T31	2		T58	3
arcs[CntIncrSt=>EscalateSt]	60	1			T8	2		T31	1		T58	1
arcs[CntProgSt=>EscalateSt]	964	1			T8	7		T31	5		T42	5
arcs[TransCheckSt=>EscalateSt]	137	1			T8	6		T31	6		T42	6
arcs[TokenHashSt=>EscalateSt]	781	1			T8	14		T31	17		T42	16
arcs[FlashRmaSt=>EscalateSt]	93	1			T8	1		T58	1		T59	4
arcs[TokenCheck0St=>EscalateSt]	30	1			T62	1		T63	3		T64	1
arcs[TokenCheck1St=>EscalateSt]	124	1			T8	2		T31	1		T42	1
arcs[TransProgSt=>EscalateSt]	657	1			T8	6		T31	7		T42	9
arcs[PostTransSt=>EscalateSt]	4787	1			T2	94		T8	8		T10	7
arcs[InvalidSt=>EscalateSt]	12678	1			T2	500		T3	5		T13	56

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6646059	1			T1	1512		T2	157022		T3	3233
auto[0]	auto[IdleSt]	22518775	1			T1	30423		T2	268994		T3	10109
auto[0]	auto[ClkMuxSt]	34293	1			T1	16		T2	445		T3	8
auto[0]	auto[CntIncrSt]	33945	1			T1	16		T2	440		T3	8
auto[0]	auto[CntProgSt]	1326009	1			T1	342		T2	10812		T3	116
auto[0]	auto[TransCheckSt]	26675	1			T1	16		T2	304		T3	8
auto[0]	auto[TokenHashSt]	41310412	1			T1	805		T2	151669		T3	192
auto[0]	auto[FlashRmaSt]	34302	1			T1	77		T2	554		T3	31
auto[0]	auto[TokenCheck0St]	12254	1			T1	16		T2	182		T3	8
auto[0]	auto[TokenCheck1St]	9174	1			T1	16		T2	147		T3	8
auto[0]	auto[TransProgSt]	348540	1			T1	430		T2	4231		T3	162
auto[0]	auto[PostTransSt]	13172063	1			T1	6155		T2	181442		T3	17809
auto[0]	auto[ScrapSt]	157952	1			T2	764		T31	2		T42	4
auto[0]	auto[EscalateSt]	5160593	1			T2	139010		T3	7145		T8	4191
auto[0]	auto[InvalidSt]	10518513	1			T2	301369		T3	11002		T13	7929
auto[1]	auto[ResetSt]	187	1			T8	3		T31	4		T42	3
auto[1]	auto[IdleSt]	127	1			T8	3		T31	1		T59	5
auto[1]	auto[ClkMuxSt]	50	1			T8	3		T31	1		T58	2
auto[1]	auto[CntIncrSt]	46	1			T8	1		T31	1		T59	2
auto[1]	auto[CntProgSt]	631	1			T8	2		T31	3		T42	3
auto[1]	auto[TransCheckSt]	90	1			T8	1		T31	5		T42	5
auto[1]	auto[TokenHashSt]	525	1			T8	7		T31	13		T42	8
auto[1]	auto[FlashRmaSt]	61	1			T59	4		T62	3		T192	1
auto[1]	auto[TokenCheck0St]	18	1			T62	1		T63	2		T64	1
auto[1]	auto[TokenCheck1St]	85	1			T8	2		T31	1		T42	1
auto[1]	auto[TransProgSt]	433	1			T8	5		T31	4		T42	8
auto[1]	auto[PostTransSt]	2442	1			T2	53		T8	6		T10	4
auto[1]	auto[ScrapSt]	52	1			T31	1		T42	2		T58	1
auto[1]	auto[EscalateSt]	1298851	1			T2	31586		T3	97		T8	6468
auto[1]	auto[InvalidSt]	6305	1			T2	271		T3	1		T13	32

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6646085	1			T1	1512		T2	157022		T3	3233
auto[0]	auto[IdleSt]	22518768	1			T1	30423		T2	268994		T3	10109
auto[0]	auto[ClkMuxSt]	34300	1			T1	16		T2	445		T3	8
auto[0]	auto[CntIncrSt]	33950	1			T1	16		T2	440		T3	8
auto[0]	auto[CntProgSt]	1326000	1			T1	342		T2	10812		T3	116
auto[0]	auto[TransCheckSt]	26667	1			T1	16		T2	304		T3	8
auto[0]	auto[TokenHashSt]	41310424	1			T1	805		T2	151669		T3	192
auto[0]	auto[FlashRmaSt]	34296	1			T1	77		T2	554		T3	31
auto[0]	auto[TokenCheck0St]	12254	1			T1	16		T2	182		T3	8
auto[0]	auto[TokenCheck1St]	9183	1			T1	16		T2	147		T3	8
auto[0]	auto[TransProgSt]	348552	1			T1	430		T2	4231		T3	162
auto[0]	auto[PostTransSt]	13172067	1			T1	6155		T2	181454		T3	17809
auto[0]	auto[ScrapSt]	157960	1			T2	764		T31	3		T42	4
auto[0]	auto[EscalateSt]	5162539	1			T2	144255		T3	6854		T8	2786
auto[0]	auto[InvalidSt]	10518445	1			T2	301411		T3	10999		T13	7937
auto[1]	auto[ResetSt]	161	1			T8	1		T31	4		T42	2
auto[1]	auto[IdleSt]	134	1			T8	2		T31	2		T42	1
auto[1]	auto[ClkMuxSt]	43	1			T8	3		T31	2		T58	1
auto[1]	auto[CntIncrSt]	41	1			T8	2		T31	1		T58	1
auto[1]	auto[CntProgSt]	640	1			T8	7		T31	4		T42	4
auto[1]	auto[TransCheckSt]	98	1			T8	5		T31	2		T42	5
auto[1]	auto[TokenHashSt]	513	1			T8	11		T31	13		T42	12
auto[1]	auto[FlashRmaSt]	67	1			T8	1		T58	1		T59	3
auto[1]	auto[TokenCheck0St]	18	1			T63	1		T193	1		T194	1
auto[1]	auto[TokenCheck1St]	76	1			T31	1		T58	1		T62	1
auto[1]	auto[TransProgSt]	421	1			T8	3		T31	5		T42	3
auto[1]	auto[PostTransSt]	2438	1			T2	41		T8	6		T10	3
auto[1]	auto[ScrapSt]	44	1			T42	2		T59	4		T62	3
auto[1]	auto[EscalateSt]	1296905	1			T2	26341		T3	388		T8	7873
auto[1]	auto[InvalidSt]	6373	1			T2	229		T3	4		T13	24