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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.30 97.99 95.77 93.38 100.00 98.55 98.76 96.64


Total test records in report: 990
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T809 /workspace/coverage/default/4.lc_ctrl_stress_all.1357979615 Jul 07 06:59:40 PM PDT 24 Jul 07 07:02:42 PM PDT 24 5692423675 ps
T810 /workspace/coverage/default/25.lc_ctrl_jtag_access.1780117730 Jul 07 07:01:46 PM PDT 24 Jul 07 07:01:56 PM PDT 24 684162154 ps
T811 /workspace/coverage/default/48.lc_ctrl_sec_token_mux.3129464120 Jul 07 07:03:16 PM PDT 24 Jul 07 07:03:28 PM PDT 24 839544126 ps
T812 /workspace/coverage/default/49.lc_ctrl_sec_token_digest.2789354365 Jul 07 07:03:26 PM PDT 24 Jul 07 07:03:34 PM PDT 24 254417167 ps
T813 /workspace/coverage/default/18.lc_ctrl_prog_failure.246796448 Jul 07 07:01:16 PM PDT 24 Jul 07 07:01:19 PM PDT 24 586096099 ps
T814 /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.3200189905 Jul 07 06:59:49 PM PDT 24 Jul 07 06:59:55 PM PDT 24 1197705969 ps
T815 /workspace/coverage/default/47.lc_ctrl_errors.1912339091 Jul 07 07:03:16 PM PDT 24 Jul 07 07:03:30 PM PDT 24 1293095883 ps
T816 /workspace/coverage/default/36.lc_ctrl_sec_token_digest.4236462286 Jul 07 07:02:29 PM PDT 24 Jul 07 07:02:45 PM PDT 24 2715858491 ps
T817 /workspace/coverage/default/34.lc_ctrl_smoke.580317619 Jul 07 07:02:20 PM PDT 24 Jul 07 07:02:22 PM PDT 24 23427213 ps
T818 /workspace/coverage/default/1.lc_ctrl_sec_token_mux.942798189 Jul 07 06:59:18 PM PDT 24 Jul 07 06:59:31 PM PDT 24 368308136 ps
T819 /workspace/coverage/default/41.lc_ctrl_alert_test.4284530070 Jul 07 07:02:54 PM PDT 24 Jul 07 07:02:55 PM PDT 24 17689942 ps
T820 /workspace/coverage/default/17.lc_ctrl_prog_failure.2397667301 Jul 07 07:01:06 PM PDT 24 Jul 07 07:01:09 PM PDT 24 172340148 ps
T821 /workspace/coverage/default/8.lc_ctrl_sec_token_digest.3805714338 Jul 07 07:00:15 PM PDT 24 Jul 07 07:00:27 PM PDT 24 364878138 ps
T822 /workspace/coverage/default/48.lc_ctrl_sec_mubi.4227464561 Jul 07 07:03:16 PM PDT 24 Jul 07 07:03:33 PM PDT 24 1438695550 ps
T823 /workspace/coverage/default/38.lc_ctrl_sec_token_mux.1412059956 Jul 07 07:02:39 PM PDT 24 Jul 07 07:02:48 PM PDT 24 322361897 ps
T824 /workspace/coverage/default/3.lc_ctrl_regwen_during_op.1350296603 Jul 07 06:59:26 PM PDT 24 Jul 07 06:59:40 PM PDT 24 453825849 ps
T825 /workspace/coverage/default/31.lc_ctrl_sec_token_mux.2383807270 Jul 07 07:02:14 PM PDT 24 Jul 07 07:02:29 PM PDT 24 1778870163 ps
T826 /workspace/coverage/default/1.lc_ctrl_jtag_errors.1175656528 Jul 07 06:59:22 PM PDT 24 Jul 07 06:59:44 PM PDT 24 1351625332 ps
T827 /workspace/coverage/default/7.lc_ctrl_sec_mubi.400166165 Jul 07 07:00:12 PM PDT 24 Jul 07 07:00:27 PM PDT 24 1135731046 ps
T828 /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.2383462385 Jul 07 07:01:01 PM PDT 24 Jul 07 07:01:36 PM PDT 24 3108643178 ps
T829 /workspace/coverage/default/39.lc_ctrl_stress_all.2922990288 Jul 07 07:02:46 PM PDT 24 Jul 07 07:04:30 PM PDT 24 4081294254 ps
T830 /workspace/coverage/default/7.lc_ctrl_errors.3392600585 Jul 07 07:00:03 PM PDT 24 Jul 07 07:00:12 PM PDT 24 359759446 ps
T831 /workspace/coverage/default/18.lc_ctrl_smoke.148247481 Jul 07 07:01:09 PM PDT 24 Jul 07 07:01:10 PM PDT 24 24717809 ps
T55 /workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.3370502599 Jul 07 06:59:19 PM PDT 24 Jul 07 07:22:29 PM PDT 24 159973190245 ps
T832 /workspace/coverage/default/9.lc_ctrl_state_post_trans.1900347123 Jul 07 07:00:14 PM PDT 24 Jul 07 07:00:20 PM PDT 24 284904339 ps
T833 /workspace/coverage/default/1.lc_ctrl_smoke.3244848326 Jul 07 06:59:13 PM PDT 24 Jul 07 06:59:17 PM PDT 24 208059495 ps
T834 /workspace/coverage/default/19.lc_ctrl_prog_failure.4010900920 Jul 07 07:01:17 PM PDT 24 Jul 07 07:01:19 PM PDT 24 193073402 ps
T835 /workspace/coverage/default/32.lc_ctrl_smoke.417672606 Jul 07 07:02:15 PM PDT 24 Jul 07 07:02:26 PM PDT 24 161766682 ps
T836 /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.1384325861 Jul 07 06:59:10 PM PDT 24 Jul 07 06:59:11 PM PDT 24 130619387 ps
T837 /workspace/coverage/default/21.lc_ctrl_sec_mubi.1710664665 Jul 07 07:01:32 PM PDT 24 Jul 07 07:01:47 PM PDT 24 1253290660 ps
T838 /workspace/coverage/default/11.lc_ctrl_alert_test.2380989056 Jul 07 07:00:36 PM PDT 24 Jul 07 07:00:38 PM PDT 24 96505270 ps
T839 /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.245571911 Jul 07 07:00:41 PM PDT 24 Jul 07 07:00:57 PM PDT 24 3882417921 ps
T840 /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.2974661902 Jul 07 06:59:30 PM PDT 24 Jul 07 06:59:48 PM PDT 24 504705883 ps
T841 /workspace/coverage/default/11.lc_ctrl_state_failure.3596394726 Jul 07 07:00:31 PM PDT 24 Jul 07 07:00:59 PM PDT 24 981712712 ps
T842 /workspace/coverage/default/13.lc_ctrl_state_post_trans.2881729836 Jul 07 07:00:40 PM PDT 24 Jul 07 07:00:44 PM PDT 24 226439327 ps
T843 /workspace/coverage/default/32.lc_ctrl_sec_token_mux.2562902090 Jul 07 07:02:16 PM PDT 24 Jul 07 07:02:24 PM PDT 24 369509761 ps
T844 /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.2506858685 Jul 07 07:01:43 PM PDT 24 Jul 07 07:01:44 PM PDT 24 14744525 ps
T845 /workspace/coverage/default/3.lc_ctrl_state_failure.3038982769 Jul 07 06:59:28 PM PDT 24 Jul 07 06:59:58 PM PDT 24 428544088 ps
T846 /workspace/coverage/default/25.lc_ctrl_prog_failure.4217219193 Jul 07 07:01:46 PM PDT 24 Jul 07 07:01:50 PM PDT 24 119387646 ps
T847 /workspace/coverage/default/1.lc_ctrl_state_failure.1023556512 Jul 07 06:59:12 PM PDT 24 Jul 07 06:59:39 PM PDT 24 238767260 ps
T848 /workspace/coverage/default/14.lc_ctrl_alert_test.3765892259 Jul 07 07:00:54 PM PDT 24 Jul 07 07:00:55 PM PDT 24 16173962 ps
T849 /workspace/coverage/default/47.lc_ctrl_alert_test.821840337 Jul 07 07:03:19 PM PDT 24 Jul 07 07:03:21 PM PDT 24 17999917 ps
T850 /workspace/coverage/default/22.lc_ctrl_jtag_access.21587103 Jul 07 07:01:36 PM PDT 24 Jul 07 07:01:43 PM PDT 24 1479053926 ps
T851 /workspace/coverage/default/27.lc_ctrl_state_failure.764159192 Jul 07 07:01:56 PM PDT 24 Jul 07 07:02:28 PM PDT 24 241612797 ps
T852 /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.1694321736 Jul 07 07:01:15 PM PDT 24 Jul 07 07:01:47 PM PDT 24 1015840490 ps
T853 /workspace/coverage/default/31.lc_ctrl_jtag_access.786149650 Jul 07 07:02:09 PM PDT 24 Jul 07 07:02:14 PM PDT 24 1379340368 ps
T854 /workspace/coverage/default/13.lc_ctrl_state_failure.717628596 Jul 07 07:00:41 PM PDT 24 Jul 07 07:01:12 PM PDT 24 349059084 ps
T855 /workspace/coverage/default/49.lc_ctrl_smoke.1102532897 Jul 07 07:03:22 PM PDT 24 Jul 07 07:03:25 PM PDT 24 108603912 ps
T856 /workspace/coverage/default/11.lc_ctrl_sec_token_mux.1463029128 Jul 07 07:00:33 PM PDT 24 Jul 07 07:00:42 PM PDT 24 422351893 ps
T857 /workspace/coverage/default/18.lc_ctrl_jtag_access.4171120538 Jul 07 07:01:16 PM PDT 24 Jul 07 07:01:20 PM PDT 24 491856243 ps
T858 /workspace/coverage/default/15.lc_ctrl_jtag_errors.2767679575 Jul 07 07:00:55 PM PDT 24 Jul 07 07:01:27 PM PDT 24 1948728935 ps
T859 /workspace/coverage/default/2.lc_ctrl_sec_token_digest.3416262630 Jul 07 06:59:23 PM PDT 24 Jul 07 06:59:36 PM PDT 24 289549894 ps
T860 /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1957905540 Jul 07 07:03:04 PM PDT 24 Jul 07 07:03:05 PM PDT 24 13450537 ps
T861 /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.2653590669 Jul 07 07:00:12 PM PDT 24 Jul 07 07:01:22 PM PDT 24 13876218185 ps
T862 /workspace/coverage/default/27.lc_ctrl_jtag_access.1875648929 Jul 07 07:01:56 PM PDT 24 Jul 07 07:02:00 PM PDT 24 876680588 ps
T123 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3367303516 Jul 07 06:35:57 PM PDT 24 Jul 07 06:35:58 PM PDT 24 40124474 ps
T124 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1749640533 Jul 07 06:35:44 PM PDT 24 Jul 07 06:35:46 PM PDT 24 160885707 ps
T125 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2037929781 Jul 07 06:35:45 PM PDT 24 Jul 07 06:35:47 PM PDT 24 21953485 ps
T863 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3509175608 Jul 07 06:35:39 PM PDT 24 Jul 07 06:35:40 PM PDT 24 14193606 ps
T118 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3651605334 Jul 07 06:36:19 PM PDT 24 Jul 07 06:36:21 PM PDT 24 71608913 ps
T147 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2354236550 Jul 07 06:36:01 PM PDT 24 Jul 07 06:36:02 PM PDT 24 119161587 ps
T115 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3205922099 Jul 07 06:35:53 PM PDT 24 Jul 07 06:35:55 PM PDT 24 115126956 ps
T864 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.916975994 Jul 07 06:35:34 PM PDT 24 Jul 07 06:35:36 PM PDT 24 44179289 ps
T116 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3253572314 Jul 07 06:36:07 PM PDT 24 Jul 07 06:36:10 PM PDT 24 238358329 ps
T117 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.515594267 Jul 07 06:35:59 PM PDT 24 Jul 07 06:36:02 PM PDT 24 85784415 ps
T172 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2142843217 Jul 07 06:35:34 PM PDT 24 Jul 07 06:35:35 PM PDT 24 39800779 ps
T184 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2931597656 Jul 07 06:36:01 PM PDT 24 Jul 07 06:36:03 PM PDT 24 70683913 ps
T150 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2725428548 Jul 07 06:35:58 PM PDT 24 Jul 07 06:36:02 PM PDT 24 450355460 ps
T185 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2498890227 Jul 07 06:36:06 PM PDT 24 Jul 07 06:36:08 PM PDT 24 78078073 ps
T173 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1679423826 Jul 07 06:36:02 PM PDT 24 Jul 07 06:36:04 PM PDT 24 13545513 ps
T151 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1609250797 Jul 07 06:35:33 PM PDT 24 Jul 07 06:35:41 PM PDT 24 422083969 ps
T174 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3039333344 Jul 07 06:35:43 PM PDT 24 Jul 07 06:35:45 PM PDT 24 13934749 ps
T157 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2441446515 Jul 07 06:36:08 PM PDT 24 Jul 07 06:36:10 PM PDT 24 45590742 ps
T865 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3316435997 Jul 07 06:35:47 PM PDT 24 Jul 07 06:35:49 PM PDT 24 23701800 ps
T148 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.455823033 Jul 07 06:35:55 PM PDT 24 Jul 07 06:35:59 PM PDT 24 344798183 ps
T158 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2645382500 Jul 07 06:35:41 PM PDT 24 Jul 07 06:35:43 PM PDT 24 28111662 ps
T120 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.504623194 Jul 07 06:35:33 PM PDT 24 Jul 07 06:35:34 PM PDT 24 82011404 ps
T149 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3221607053 Jul 07 06:35:37 PM PDT 24 Jul 07 06:35:40 PM PDT 24 225672426 ps
T186 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2697196675 Jul 07 06:36:06 PM PDT 24 Jul 07 06:36:08 PM PDT 24 18630169 ps
T866 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2954774034 Jul 07 06:35:56 PM PDT 24 Jul 07 06:35:59 PM PDT 24 93460925 ps
T867 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2488107091 Jul 07 06:36:14 PM PDT 24 Jul 07 06:36:15 PM PDT 24 12183954 ps
T119 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3532943420 Jul 07 06:36:04 PM PDT 24 Jul 07 06:36:06 PM PDT 24 292198892 ps
T868 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1099902951 Jul 07 06:35:45 PM PDT 24 Jul 07 06:35:46 PM PDT 24 21772920 ps
T159 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3747314845 Jul 07 06:35:55 PM PDT 24 Jul 07 06:35:57 PM PDT 24 149630594 ps
T121 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.858575115 Jul 07 06:36:07 PM PDT 24 Jul 07 06:36:09 PM PDT 24 112460682 ps
T869 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.85663547 Jul 07 06:35:53 PM PDT 24 Jul 07 06:36:04 PM PDT 24 484659784 ps
T175 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3471443389 Jul 07 06:36:07 PM PDT 24 Jul 07 06:36:09 PM PDT 24 14049080 ps
T167 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1927711799 Jul 07 06:35:45 PM PDT 24 Jul 07 06:35:47 PM PDT 24 71760798 ps
T122 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2992217678 Jul 07 06:35:58 PM PDT 24 Jul 07 06:36:00 PM PDT 24 108877238 ps
T129 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.253841033 Jul 07 06:35:43 PM PDT 24 Jul 07 06:35:45 PM PDT 24 44387234 ps
T870 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2740634210 Jul 07 06:35:54 PM PDT 24 Jul 07 06:36:00 PM PDT 24 6910196732 ps
T871 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.343025709 Jul 07 06:35:32 PM PDT 24 Jul 07 06:35:34 PM PDT 24 144334928 ps
T872 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2973739889 Jul 07 06:35:46 PM PDT 24 Jul 07 06:35:47 PM PDT 24 104443282 ps
T135 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2224615396 Jul 07 06:36:09 PM PDT 24 Jul 07 06:36:12 PM PDT 24 150723497 ps
T160 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3127252094 Jul 07 06:36:04 PM PDT 24 Jul 07 06:36:06 PM PDT 24 180867807 ps
T873 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.218602977 Jul 07 06:35:46 PM PDT 24 Jul 07 06:35:49 PM PDT 24 93977158 ps
T127 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3042407504 Jul 07 06:36:01 PM PDT 24 Jul 07 06:36:05 PM PDT 24 124354489 ps
T874 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1479671251 Jul 07 06:36:05 PM PDT 24 Jul 07 06:36:13 PM PDT 24 587341609 ps
T176 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1083377162 Jul 07 06:35:44 PM PDT 24 Jul 07 06:35:45 PM PDT 24 19811487 ps
T875 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.4215379978 Jul 07 06:35:55 PM PDT 24 Jul 07 06:35:56 PM PDT 24 421578767 ps
T140 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1481005566 Jul 07 06:35:54 PM PDT 24 Jul 07 06:35:56 PM PDT 24 43772089 ps
T876 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.691703173 Jul 07 06:35:41 PM PDT 24 Jul 07 06:35:43 PM PDT 24 48558733 ps
T126 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2038456573 Jul 07 06:35:33 PM PDT 24 Jul 07 06:35:38 PM PDT 24 123145390 ps
T877 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.554693287 Jul 07 06:35:56 PM PDT 24 Jul 07 06:36:00 PM PDT 24 448780913 ps
T878 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2630479518 Jul 07 06:36:00 PM PDT 24 Jul 07 06:36:02 PM PDT 24 68414405 ps
T879 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3331537306 Jul 07 06:35:40 PM PDT 24 Jul 07 06:36:01 PM PDT 24 1825767146 ps
T880 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.774091618 Jul 07 06:36:01 PM PDT 24 Jul 07 06:36:03 PM PDT 24 37175325 ps
T881 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2509630357 Jul 07 06:36:09 PM PDT 24 Jul 07 06:36:11 PM PDT 24 22151514 ps
T132 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3331036907 Jul 07 06:36:08 PM PDT 24 Jul 07 06:36:12 PM PDT 24 109826990 ps
T133 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2544966484 Jul 07 06:36:03 PM PDT 24 Jul 07 06:36:05 PM PDT 24 554069731 ps
T882 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2892725939 Jul 07 06:35:47 PM PDT 24 Jul 07 06:35:48 PM PDT 24 13926643 ps
T138 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.574175563 Jul 07 06:36:14 PM PDT 24 Jul 07 06:36:16 PM PDT 24 46757788 ps
T883 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.794086840 Jul 07 06:36:07 PM PDT 24 Jul 07 06:36:09 PM PDT 24 40534506 ps
T884 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3679322978 Jul 07 06:35:39 PM PDT 24 Jul 07 06:35:40 PM PDT 24 15773609 ps
T177 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2928224647 Jul 07 06:35:44 PM PDT 24 Jul 07 06:35:45 PM PDT 24 60043271 ps
T130 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1991260624 Jul 07 06:36:04 PM PDT 24 Jul 07 06:36:07 PM PDT 24 203533016 ps
T885 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3677803507 Jul 07 06:35:58 PM PDT 24 Jul 07 06:35:59 PM PDT 24 36865765 ps
T886 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.781711281 Jul 07 06:36:10 PM PDT 24 Jul 07 06:36:11 PM PDT 24 56709706 ps
T136 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1491280809 Jul 07 06:36:09 PM PDT 24 Jul 07 06:36:12 PM PDT 24 218065447 ps
T178 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.433313136 Jul 07 06:36:03 PM PDT 24 Jul 07 06:36:04 PM PDT 24 15958636 ps
T137 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1234288407 Jul 07 06:35:40 PM PDT 24 Jul 07 06:35:44 PM PDT 24 140572793 ps
T887 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2303529020 Jul 07 06:36:05 PM PDT 24 Jul 07 06:36:06 PM PDT 24 159411448 ps
T888 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2014348644 Jul 07 06:36:00 PM PDT 24 Jul 07 06:36:03 PM PDT 24 1716534918 ps
T134 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3446854899 Jul 07 06:36:10 PM PDT 24 Jul 07 06:36:15 PM PDT 24 667936168 ps
T889 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.455172023 Jul 07 06:36:02 PM PDT 24 Jul 07 06:36:03 PM PDT 24 223789236 ps
T890 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1704019832 Jul 07 06:35:44 PM PDT 24 Jul 07 06:35:46 PM PDT 24 36445254 ps
T891 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1729906802 Jul 07 06:35:36 PM PDT 24 Jul 07 06:35:38 PM PDT 24 198015968 ps
T892 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3198710400 Jul 07 06:35:40 PM PDT 24 Jul 07 06:35:42 PM PDT 24 65728159 ps
T893 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1428404136 Jul 07 06:35:47 PM PDT 24 Jul 07 06:35:49 PM PDT 24 112584280 ps
T894 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2825643727 Jul 07 06:35:59 PM PDT 24 Jul 07 06:36:02 PM PDT 24 275393219 ps
T895 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3688477233 Jul 07 06:36:08 PM PDT 24 Jul 07 06:36:10 PM PDT 24 63759658 ps
T896 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2622523479 Jul 07 06:36:03 PM PDT 24 Jul 07 06:36:05 PM PDT 24 17181679 ps
T897 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1680204752 Jul 07 06:35:43 PM PDT 24 Jul 07 06:35:46 PM PDT 24 571976331 ps
T898 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.736990411 Jul 07 06:35:37 PM PDT 24 Jul 07 06:35:39 PM PDT 24 213540290 ps
T899 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1317548276 Jul 07 06:36:02 PM PDT 24 Jul 07 06:36:05 PM PDT 24 50077974 ps
T900 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1554925725 Jul 07 06:35:48 PM PDT 24 Jul 07 06:35:50 PM PDT 24 66538383 ps
T901 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.4149833406 Jul 07 06:35:40 PM PDT 24 Jul 07 06:35:42 PM PDT 24 13870842 ps
T179 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3369858983 Jul 07 06:35:51 PM PDT 24 Jul 07 06:35:52 PM PDT 24 20614586 ps
T141 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3054108869 Jul 07 06:36:07 PM PDT 24 Jul 07 06:36:10 PM PDT 24 112716018 ps
T902 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2148412289 Jul 07 06:35:51 PM PDT 24 Jul 07 06:36:06 PM PDT 24 630524532 ps
T903 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2161218031 Jul 07 06:36:05 PM PDT 24 Jul 07 06:36:09 PM PDT 24 269234370 ps
T904 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.222984596 Jul 07 06:35:32 PM PDT 24 Jul 07 06:35:34 PM PDT 24 39332160 ps
T905 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2927300452 Jul 07 06:36:14 PM PDT 24 Jul 07 06:36:19 PM PDT 24 505097955 ps
T142 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1210717720 Jul 07 06:36:10 PM PDT 24 Jul 07 06:36:15 PM PDT 24 580809951 ps
T906 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2368327003 Jul 07 06:36:02 PM PDT 24 Jul 07 06:36:04 PM PDT 24 54449110 ps
T907 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2425503120 Jul 07 06:36:00 PM PDT 24 Jul 07 06:36:03 PM PDT 24 170202157 ps
T908 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2620675173 Jul 07 06:35:52 PM PDT 24 Jul 07 06:35:53 PM PDT 24 15688706 ps
T909 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2378501439 Jul 07 06:35:36 PM PDT 24 Jul 07 06:35:38 PM PDT 24 77717293 ps
T910 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.1581191126 Jul 07 06:36:07 PM PDT 24 Jul 07 06:36:08 PM PDT 24 63736828 ps
T911 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.3969957209 Jul 07 06:36:03 PM PDT 24 Jul 07 06:36:05 PM PDT 24 693715860 ps
T912 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3475126568 Jul 07 06:35:46 PM PDT 24 Jul 07 06:35:52 PM PDT 24 1710389011 ps
T913 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.500430141 Jul 07 06:36:19 PM PDT 24 Jul 07 06:36:23 PM PDT 24 474088308 ps
T914 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1030785591 Jul 07 06:36:00 PM PDT 24 Jul 07 06:36:03 PM PDT 24 115910170 ps
T915 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2235941497 Jul 07 06:35:53 PM PDT 24 Jul 07 06:35:55 PM PDT 24 301457627 ps
T916 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3862162873 Jul 07 06:36:02 PM PDT 24 Jul 07 06:36:05 PM PDT 24 120914584 ps
T917 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2139779351 Jul 07 06:36:04 PM PDT 24 Jul 07 06:36:31 PM PDT 24 2357302070 ps
T918 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2643595147 Jul 07 06:35:34 PM PDT 24 Jul 07 06:35:47 PM PDT 24 1397580327 ps
T131 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2518596203 Jul 07 06:35:55 PM PDT 24 Jul 07 06:35:57 PM PDT 24 93765663 ps
T919 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1496562417 Jul 07 06:35:39 PM PDT 24 Jul 07 06:35:40 PM PDT 24 24632070 ps
T920 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2364390456 Jul 07 06:36:07 PM PDT 24 Jul 07 06:36:09 PM PDT 24 23291527 ps
T921 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1802388956 Jul 07 06:35:39 PM PDT 24 Jul 07 06:36:02 PM PDT 24 4528990806 ps
T922 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2765589408 Jul 07 06:35:44 PM PDT 24 Jul 07 06:35:46 PM PDT 24 226092782 ps
T923 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1067744429 Jul 07 06:35:42 PM PDT 24 Jul 07 06:36:22 PM PDT 24 3475283372 ps
T924 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1528002565 Jul 07 06:36:06 PM PDT 24 Jul 07 06:36:07 PM PDT 24 57898379 ps
T925 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1142923812 Jul 07 06:35:35 PM PDT 24 Jul 07 06:35:37 PM PDT 24 16978514 ps
T139 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2112518284 Jul 07 06:35:48 PM PDT 24 Jul 07 06:35:51 PM PDT 24 462296033 ps
T926 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.4089132307 Jul 07 06:35:52 PM PDT 24 Jul 07 06:35:55 PM PDT 24 78045012 ps
T128 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1921296316 Jul 07 06:35:40 PM PDT 24 Jul 07 06:35:46 PM PDT 24 224060123 ps
T927 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.982326475 Jul 07 06:35:32 PM PDT 24 Jul 07 06:35:34 PM PDT 24 19354663 ps
T180 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2600186453 Jul 07 06:36:06 PM PDT 24 Jul 07 06:36:08 PM PDT 24 14721017 ps
T145 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.499985808 Jul 07 06:36:09 PM PDT 24 Jul 07 06:36:12 PM PDT 24 857700198 ps
T928 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2982704599 Jul 07 06:35:34 PM PDT 24 Jul 07 06:35:36 PM PDT 24 122068573 ps
T929 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.585598711 Jul 07 06:35:54 PM PDT 24 Jul 07 06:35:56 PM PDT 24 51496735 ps
T930 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.4201104400 Jul 07 06:35:59 PM PDT 24 Jul 07 06:36:01 PM PDT 24 51408778 ps
T931 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2719741811 Jul 07 06:35:59 PM PDT 24 Jul 07 06:36:01 PM PDT 24 73110124 ps
T932 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.4209387028 Jul 07 06:36:06 PM PDT 24 Jul 07 06:36:08 PM PDT 24 22306143 ps
T933 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.4168445568 Jul 07 06:36:05 PM PDT 24 Jul 07 06:36:06 PM PDT 24 70229430 ps
T934 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.384346966 Jul 07 06:35:47 PM PDT 24 Jul 07 06:36:03 PM PDT 24 1383971477 ps
T935 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2315045885 Jul 07 06:35:39 PM PDT 24 Jul 07 06:35:40 PM PDT 24 26451003 ps
T936 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.506637656 Jul 07 06:36:07 PM PDT 24 Jul 07 06:36:09 PM PDT 24 306107408 ps
T937 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.683377370 Jul 07 06:35:47 PM PDT 24 Jul 07 06:35:49 PM PDT 24 68693906 ps
T938 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2244523514 Jul 07 06:36:11 PM PDT 24 Jul 07 06:36:13 PM PDT 24 38850049 ps
T939 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1166498555 Jul 07 06:36:13 PM PDT 24 Jul 07 06:36:14 PM PDT 24 34150679 ps
T940 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3625036282 Jul 07 06:36:02 PM PDT 24 Jul 07 06:36:04 PM PDT 24 24067725 ps
T941 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2762462184 Jul 07 06:35:33 PM PDT 24 Jul 07 06:35:35 PM PDT 24 120580938 ps
T942 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1888859268 Jul 07 06:35:52 PM PDT 24 Jul 07 06:35:54 PM PDT 24 175190803 ps
T144 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.438877588 Jul 07 06:35:48 PM PDT 24 Jul 07 06:35:51 PM PDT 24 74668760 ps
T181 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3984319055 Jul 07 06:36:05 PM PDT 24 Jul 07 06:36:07 PM PDT 24 12246134 ps
T943 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1859893017 Jul 07 06:35:49 PM PDT 24 Jul 07 06:35:53 PM PDT 24 86646639 ps
T182 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3053668714 Jul 07 06:35:36 PM PDT 24 Jul 07 06:35:38 PM PDT 24 22229545 ps
T944 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2139294765 Jul 07 06:35:43 PM PDT 24 Jul 07 06:35:46 PM PDT 24 82281567 ps
T945 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.4186531402 Jul 07 06:35:59 PM PDT 24 Jul 07 06:36:12 PM PDT 24 982559975 ps
T946 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3577413331 Jul 07 06:35:41 PM PDT 24 Jul 07 06:35:43 PM PDT 24 86347698 ps
T947 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.2924134933 Jul 07 06:35:54 PM PDT 24 Jul 07 06:35:55 PM PDT 24 46030394 ps
T948 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.810038890 Jul 07 06:35:46 PM PDT 24 Jul 07 06:35:48 PM PDT 24 40431620 ps
T949 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1247213221 Jul 07 06:36:19 PM PDT 24 Jul 07 06:36:20 PM PDT 24 37122161 ps
T950 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.884321505 Jul 07 06:35:41 PM PDT 24 Jul 07 06:36:01 PM PDT 24 766689824 ps
T951 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.84370890 Jul 07 06:36:17 PM PDT 24 Jul 07 06:36:20 PM PDT 24 168067205 ps
T952 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1503501184 Jul 07 06:36:06 PM PDT 24 Jul 07 06:36:09 PM PDT 24 97429453 ps
T953 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1468537189 Jul 07 06:36:19 PM PDT 24 Jul 07 06:36:21 PM PDT 24 18665126 ps
T954 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2169031687 Jul 07 06:35:34 PM PDT 24 Jul 07 06:35:37 PM PDT 24 349370075 ps
T955 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1751935875 Jul 07 06:35:53 PM PDT 24 Jul 07 06:35:55 PM PDT 24 25103013 ps
T956 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.497135934 Jul 07 06:36:08 PM PDT 24 Jul 07 06:36:10 PM PDT 24 25932556 ps
T957 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4089376005 Jul 07 06:35:51 PM PDT 24 Jul 07 06:35:54 PM PDT 24 594449602 ps
T958 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1566554357 Jul 07 06:36:00 PM PDT 24 Jul 07 06:36:02 PM PDT 24 153879165 ps
T959 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1456825966 Jul 07 06:35:40 PM PDT 24 Jul 07 06:35:42 PM PDT 24 113409318 ps
T960 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2349418341 Jul 07 06:35:42 PM PDT 24 Jul 07 06:35:43 PM PDT 24 111273805 ps
T961 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1189720035 Jul 07 06:35:37 PM PDT 24 Jul 07 06:35:57 PM PDT 24 6837344722 ps
T962 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1557019693 Jul 07 06:35:59 PM PDT 24 Jul 07 06:36:04 PM PDT 24 320906757 ps
T963 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1262924901 Jul 07 06:35:41 PM PDT 24 Jul 07 06:35:44 PM PDT 24 96916427 ps
T964 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3417884470 Jul 07 06:36:11 PM PDT 24 Jul 07 06:36:13 PM PDT 24 106757192 ps
T965 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2213847283 Jul 07 06:35:42 PM PDT 24 Jul 07 06:35:44 PM PDT 24 72991407 ps
T966 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3757442057 Jul 07 06:36:00 PM PDT 24 Jul 07 06:36:01 PM PDT 24 22265258 ps
T967 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1195216865 Jul 07 06:36:03 PM PDT 24 Jul 07 06:36:05 PM PDT 24 51868013 ps
T968 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2700646237 Jul 07 06:36:06 PM PDT 24 Jul 07 06:36:08 PM PDT 24 27112085 ps
T969 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2313182942 Jul 07 06:35:40 PM PDT 24 Jul 07 06:35:42 PM PDT 24 52221220 ps
T970 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2470931507 Jul 07 06:35:45 PM PDT 24 Jul 07 06:35:47 PM PDT 24 709680535 ps
T971 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.482533238 Jul 07 06:36:01 PM PDT 24 Jul 07 06:36:03 PM PDT 24 2077101887 ps
T972 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.974400634 Jul 07 06:35:59 PM PDT 24 Jul 07 06:36:06 PM PDT 24 665564864 ps
T973 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1034971973 Jul 07 06:36:09 PM PDT 24 Jul 07 06:36:10 PM PDT 24 24293025 ps
T974 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2551450644 Jul 07 06:35:57 PM PDT 24 Jul 07 06:35:59 PM PDT 24 89789693 ps
T975 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3707901959 Jul 07 06:35:52 PM PDT 24 Jul 07 06:35:54 PM PDT 24 37394257 ps
T976 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1499338879 Jul 07 06:35:41 PM PDT 24 Jul 07 06:35:43 PM PDT 24 34959634 ps
T977 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.480471026 Jul 07 06:36:00 PM PDT 24 Jul 07 06:36:02 PM PDT 24 97192753 ps
T978 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1565998801 Jul 07 06:35:33 PM PDT 24 Jul 07 06:35:36 PM PDT 24 59562529 ps
T143 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3324900856 Jul 07 06:36:01 PM PDT 24 Jul 07 06:36:03 PM PDT 24 211732045 ps
T979 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2866675330 Jul 07 06:35:40 PM PDT 24 Jul 07 06:35:46 PM PDT 24 5754731478 ps
T146 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.3198819467 Jul 07 06:36:07 PM PDT 24 Jul 07 06:36:11 PM PDT 24 124441066 ps
T980 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2840497735 Jul 07 06:35:44 PM PDT 24 Jul 07 06:35:50 PM PDT 24 190442980 ps
T981 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3252960524 Jul 07 06:36:00 PM PDT 24 Jul 07 06:36:02 PM PDT 24 227919318 ps
T982 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2110521932 Jul 07 06:36:05 PM PDT 24 Jul 07 06:36:07 PM PDT 24 43881337 ps
T983 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2918293700 Jul 07 06:35:53 PM PDT 24 Jul 07 06:35:56 PM PDT 24 83263172 ps
T984 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3224287304 Jul 07 06:35:52 PM PDT 24 Jul 07 06:35:55 PM PDT 24 544143640 ps
T985 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2216954650 Jul 07 06:36:00 PM PDT 24 Jul 07 06:36:06 PM PDT 24 565592704 ps
T986 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.1725815409 Jul 07 06:35:46 PM PDT 24 Jul 07 06:35:50 PM PDT 24 207721088 ps
T987 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3711064152 Jul 07 06:35:50 PM PDT 24 Jul 07 06:35:52 PM PDT 24 119832425 ps
T183 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.3872825758 Jul 07 06:35:49 PM PDT 24 Jul 07 06:35:51 PM PDT 24 19180284 ps
T988 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1920948983 Jul 07 06:35:40 PM PDT 24 Jul 07 06:35:42 PM PDT 24 117556394 ps
T989 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.806237492 Jul 07 06:36:02 PM PDT 24 Jul 07 06:36:05 PM PDT 24 1669199959 ps
T990 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.522234649 Jul 07 06:35:58 PM PDT 24 Jul 07 06:36:01 PM PDT 24 311595862 ps

Test location /workspace/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.3316436479
Short name T2
Test name
Test status
Simulation time 26951765978 ps
CPU time 707.57 seconds
Started Jul 07 07:00:37 PM PDT 24
Finished Jul 07 07:12:26 PM PDT 24
Peak memory 463820 kb
Host smart-4b0abf89-4093-4f36-b078-b8837b16c489
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3316436479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all_with_rand_reset.3316436479
Directory /workspace/11.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.1811647147
Short name T8
Test name
Test status
Simulation time 1336351958 ps
CPU time 7.09 seconds
Started Jul 07 07:00:01 PM PDT 24
Finished Jul 07 07:00:09 PM PDT 24
Peak memory 224184 kb
Host smart-0f176faf-f748-424f-95b1-5a1fc9a87fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811647147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.1811647147
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.2511463750
Short name T14
Test name
Test status
Simulation time 422898318 ps
CPU time 10.74 seconds
Started Jul 07 07:02:46 PM PDT 24
Finished Jul 07 07:02:57 PM PDT 24
Peak memory 225564 kb
Host smart-6a2550a0-b0a7-4d1f-b449-6e516418d618
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511463750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.2511463750
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.858575115
Short name T121
Test name
Test status
Simulation time 112460682 ps
CPU time 2.15 seconds
Started Jul 07 06:36:07 PM PDT 24
Finished Jul 07 06:36:09 PM PDT 24
Peak memory 217956 kb
Host smart-965affd2-ad5c-4dbe-a221-f091b6edfc97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858575115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.858575115
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.3741057014
Short name T36
Test name
Test status
Simulation time 11716449 ps
CPU time 0.93 seconds
Started Jul 07 07:03:13 PM PDT 24
Finished Jul 07 07:03:14 PM PDT 24
Peak memory 208460 kb
Host smart-71726a85-9f8f-4381-a219-0e8ef2f38ddc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741057014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.3741057014
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.2125893650
Short name T63
Test name
Test status
Simulation time 650658116 ps
CPU time 12.23 seconds
Started Jul 07 07:01:42 PM PDT 24
Finished Jul 07 07:01:55 PM PDT 24
Peak memory 225584 kb
Host smart-a9da7f8d-66bf-4834-be50-c4c5b26f09e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125893650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.2125893650
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.1662293383
Short name T60
Test name
Test status
Simulation time 427696484 ps
CPU time 22.54 seconds
Started Jul 07 06:59:11 PM PDT 24
Finished Jul 07 06:59:34 PM PDT 24
Peak memory 269004 kb
Host smart-5e27449e-4ce4-49e5-8a5f-e068b2162619
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662293383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.1662293383
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.2227518096
Short name T4
Test name
Test status
Simulation time 4451067491 ps
CPU time 11.41 seconds
Started Jul 07 07:02:00 PM PDT 24
Finished Jul 07 07:02:12 PM PDT 24
Peak memory 217260 kb
Host smart-f7d66862-3e56-44c5-b3eb-caf18c0b6c11
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227518096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.2227518096
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.515594267
Short name T117
Test name
Test status
Simulation time 85784415 ps
CPU time 2.23 seconds
Started Jul 07 06:35:59 PM PDT 24
Finished Jul 07 06:36:02 PM PDT 24
Peak memory 222080 kb
Host smart-41afee2a-14e3-4a45-a4e5-69f322f35a43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515594267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_e
rr.515594267
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.3887471160
Short name T592
Test name
Test status
Simulation time 70831493761 ps
CPU time 1182.53 seconds
Started Jul 07 07:01:05 PM PDT 24
Finished Jul 07 07:20:48 PM PDT 24
Peak memory 421116 kb
Host smart-25ae3fec-acb0-4398-92e1-ca26afbbd476
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3887471160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all_with_rand_reset.3887471160
Directory /workspace/16.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.1743744987
Short name T57
Test name
Test status
Simulation time 2065318382 ps
CPU time 11.76 seconds
Started Jul 07 07:01:31 PM PDT 24
Finished Jul 07 07:01:44 PM PDT 24
Peak memory 217748 kb
Host smart-de86a396-9163-4532-abd8-698644b12af5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743744987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
1743744987
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.2664418537
Short name T164
Test name
Test status
Simulation time 1007673655 ps
CPU time 7.67 seconds
Started Jul 07 07:01:07 PM PDT 24
Finished Jul 07 07:01:15 PM PDT 24
Peak memory 225572 kb
Host smart-3e39d31e-2960-4fe7-8587-7d3d66bc66f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664418537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.2664418537
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.3542991955
Short name T11
Test name
Test status
Simulation time 54808927 ps
CPU time 1.15 seconds
Started Jul 07 07:00:40 PM PDT 24
Finished Jul 07 07:00:41 PM PDT 24
Peak memory 208532 kb
Host smart-36ff2ec5-4a75-4194-abea-7d4b9dcbd4ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542991955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.3542991955
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2600186453
Short name T180
Test name
Test status
Simulation time 14721017 ps
CPU time 1.11 seconds
Started Jul 07 06:36:06 PM PDT 24
Finished Jul 07 06:36:08 PM PDT 24
Peak memory 209280 kb
Host smart-df198a39-1c86-45fa-872b-2b9c98830b81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600186453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.2600186453
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3221607053
Short name T149
Test name
Test status
Simulation time 225672426 ps
CPU time 3.28 seconds
Started Jul 07 06:35:37 PM PDT 24
Finished Jul 07 06:35:40 PM PDT 24
Peak memory 217376 kb
Host smart-302d458e-6983-4339-9b36-2d2d7e7bb030
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221607053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.3221607053
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.1593380918
Short name T51
Test name
Test status
Simulation time 967499094 ps
CPU time 11.58 seconds
Started Jul 07 07:01:21 PM PDT 24
Finished Jul 07 07:01:32 PM PDT 24
Peak memory 218432 kb
Host smart-166cc391-7808-43c6-9990-8402cf982bc5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593380918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.1593380918
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3042407504
Short name T127
Test name
Test status
Simulation time 124354489 ps
CPU time 4.44 seconds
Started Jul 07 06:36:01 PM PDT 24
Finished Jul 07 06:36:05 PM PDT 24
Peak memory 217488 kb
Host smart-5e357d63-25b0-43cf-a251-4768d85c5986
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042407504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.3042407504
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3532943420
Short name T119
Test name
Test status
Simulation time 292198892 ps
CPU time 1.85 seconds
Started Jul 07 06:36:04 PM PDT 24
Finished Jul 07 06:36:06 PM PDT 24
Peak memory 222112 kb
Host smart-e33d815a-6c1f-4ebb-b15e-0d515b82421c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532943420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.3532943420
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.2787401266
Short name T17
Test name
Test status
Simulation time 1949937674 ps
CPU time 48.93 seconds
Started Jul 07 06:59:07 PM PDT 24
Finished Jul 07 06:59:56 PM PDT 24
Peak memory 252572 kb
Host smart-8d6875a5-a439-4696-9b02-0c4d5a884063
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787401266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.2787401266
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.3198819467
Short name T146
Test name
Test status
Simulation time 124441066 ps
CPU time 3.09 seconds
Started Jul 07 06:36:07 PM PDT 24
Finished Jul 07 06:36:11 PM PDT 24
Peak memory 222176 kb
Host smart-0bd10d3d-8019-4399-9239-cee130fbe8de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198819467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.3198819467
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.81500483
Short name T56
Test name
Test status
Simulation time 5955952729 ps
CPU time 18 seconds
Started Jul 07 06:59:45 PM PDT 24
Finished Jul 07 07:00:03 PM PDT 24
Peak memory 225648 kb
Host smart-1dde536e-6511-49b5-a978-2e778532aa08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81500483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.81500483
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.218555257
Short name T67
Test name
Test status
Simulation time 7649578396 ps
CPU time 144.47 seconds
Started Jul 07 07:01:46 PM PDT 24
Finished Jul 07 07:04:11 PM PDT 24
Peak memory 250596 kb
Host smart-91c00d0c-e1e8-45ff-8537-2057b5770206
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218555257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.218555257
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3446854899
Short name T134
Test name
Test status
Simulation time 667936168 ps
CPU time 4.19 seconds
Started Jul 07 06:36:10 PM PDT 24
Finished Jul 07 06:36:15 PM PDT 24
Peak memory 217484 kb
Host smart-f143bfc1-e9ae-48ab-85ab-89b651ce2c9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446854899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.3446854899
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1749640533
Short name T124
Test name
Test status
Simulation time 160885707 ps
CPU time 1.85 seconds
Started Jul 07 06:35:44 PM PDT 24
Finished Jul 07 06:35:46 PM PDT 24
Peak memory 217464 kb
Host smart-c1863f40-7c5c-4841-a4c0-ccbcad5e4dfe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749640533 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.1749640533
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.3848420013
Short name T96
Test name
Test status
Simulation time 170097889784 ps
CPU time 1526.62 seconds
Started Jul 07 07:02:30 PM PDT 24
Finished Jul 07 07:27:57 PM PDT 24
Peak memory 447316 kb
Host smart-7a1bbdd1-7f8b-4c58-9106-6ee4b33b8db8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3848420013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.3848420013
Directory /workspace/35.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.635289399
Short name T3
Test name
Test status
Simulation time 7134050857 ps
CPU time 22.02 seconds
Started Jul 07 06:59:08 PM PDT 24
Finished Jul 07 06:59:30 PM PDT 24
Peak memory 250340 kb
Host smart-b4be344c-8b49-4269-b3aa-d50eefd26370
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635289399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_state_post_trans.635289399
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1991260624
Short name T130
Test name
Test status
Simulation time 203533016 ps
CPU time 2.66 seconds
Started Jul 07 06:36:04 PM PDT 24
Finished Jul 07 06:36:07 PM PDT 24
Peak memory 221932 kb
Host smart-a8e1d5bb-b647-422f-a73f-7ce275892fcd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991260624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.1991260624
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3324900856
Short name T143
Test name
Test status
Simulation time 211732045 ps
CPU time 2.44 seconds
Started Jul 07 06:36:01 PM PDT 24
Finished Jul 07 06:36:03 PM PDT 24
Peak memory 217508 kb
Host smart-bdf3fbdd-9615-4447-8341-f643f3162574
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324900856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.3324900856
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.1404830035
Short name T191
Test name
Test status
Simulation time 12500624 ps
CPU time 0.93 seconds
Started Jul 07 06:59:06 PM PDT 24
Finished Jul 07 06:59:07 PM PDT 24
Peak memory 208464 kb
Host smart-550e353f-8f73-4816-b00b-5bd2e342ff95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404830035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.1404830035
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.3957564043
Short name T189
Test name
Test status
Simulation time 31675130 ps
CPU time 0.81 seconds
Started Jul 07 06:59:18 PM PDT 24
Finished Jul 07 06:59:19 PM PDT 24
Peak memory 208512 kb
Host smart-39d525db-f84c-4aa8-acf8-d0caa93ca6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957564043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.3957564043
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.3207844307
Short name T190
Test name
Test status
Simulation time 13421032 ps
CPU time 0.96 seconds
Started Jul 07 06:59:28 PM PDT 24
Finished Jul 07 06:59:29 PM PDT 24
Peak memory 208400 kb
Host smart-1360c3cd-6fb5-4b7f-bc73-0cc77d77a806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207844307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.3207844307
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.3826605689
Short name T111
Test name
Test status
Simulation time 19641619 ps
CPU time 0.9 seconds
Started Jul 07 06:59:39 PM PDT 24
Finished Jul 07 06:59:40 PM PDT 24
Peak memory 208428 kb
Host smart-7acf2b25-8fe1-4194-9161-f5a968ba0fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826605689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.3826605689
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.1671672923
Short name T162
Test name
Test status
Simulation time 36165528 ps
CPU time 0.95 seconds
Started Jul 07 07:00:05 PM PDT 24
Finished Jul 07 07:00:06 PM PDT 24
Peak memory 208428 kb
Host smart-8ad249e1-66c0-4a74-8a3d-604e4e625228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671672923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.1671672923
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.3064289492
Short name T102
Test name
Test status
Simulation time 11902674 ps
CPU time 0.97 seconds
Started Jul 07 07:00:08 PM PDT 24
Finished Jul 07 07:00:10 PM PDT 24
Peak memory 208408 kb
Host smart-f274f58c-2a28-4630-b6d6-cd679b24c7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064289492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.3064289492
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3253572314
Short name T116
Test name
Test status
Simulation time 238358329 ps
CPU time 2.58 seconds
Started Jul 07 06:36:07 PM PDT 24
Finished Jul 07 06:36:10 PM PDT 24
Peak memory 217464 kb
Host smart-258aa294-c639-4779-ae4f-fdc08ec4fc5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253572314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.3253572314
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.499985808
Short name T145
Test name
Test status
Simulation time 857700198 ps
CPU time 3.15 seconds
Started Jul 07 06:36:09 PM PDT 24
Finished Jul 07 06:36:12 PM PDT 24
Peak memory 222620 kb
Host smart-723a43a5-ae6a-46fb-9811-d8e5171f7353
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499985808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg_
err.499985808
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1234288407
Short name T137
Test name
Test status
Simulation time 140572793 ps
CPU time 3.32 seconds
Started Jul 07 06:35:40 PM PDT 24
Finished Jul 07 06:35:44 PM PDT 24
Peak memory 217480 kb
Host smart-b1014db5-d309-4813-a678-9ff3732f2cb9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234288407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.1234288407
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.438877588
Short name T144
Test name
Test status
Simulation time 74668760 ps
CPU time 2.86 seconds
Started Jul 07 06:35:48 PM PDT 24
Finished Jul 07 06:35:51 PM PDT 24
Peak memory 217488 kb
Host smart-3b70fd0f-b82a-41fa-96db-ef904034528e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438877588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_e
rr.438877588
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2112518284
Short name T139
Test name
Test status
Simulation time 462296033 ps
CPU time 2.81 seconds
Started Jul 07 06:35:48 PM PDT 24
Finished Jul 07 06:35:51 PM PDT 24
Peak memory 222168 kb
Host smart-2c07cd51-00b6-4d5a-93fa-131770ceeda6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112518284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.2112518284
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.3370502599
Short name T55
Test name
Test status
Simulation time 159973190245 ps
CPU time 1389.51 seconds
Started Jul 07 06:59:19 PM PDT 24
Finished Jul 07 07:22:29 PM PDT 24
Peak memory 316172 kb
Host smart-6831ae23-a098-4a33-b9e4-a34335a94d70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3370502599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all_with_rand_reset.3370502599
Directory /workspace/1.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.858045201
Short name T28
Test name
Test status
Simulation time 3193080036 ps
CPU time 23.02 seconds
Started Jul 07 07:00:20 PM PDT 24
Finished Jul 07 07:00:43 PM PDT 24
Peak memory 250576 kb
Host smart-e4c7820f-dec6-48f8-ba62-5a70b2c2c8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858045201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.858045201
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.3420603430
Short name T16
Test name
Test status
Simulation time 3060573188 ps
CPU time 17.15 seconds
Started Jul 07 07:00:35 PM PDT 24
Finished Jul 07 07:00:52 PM PDT 24
Peak memory 250472 kb
Host smart-1d8a33fa-06f9-41fd-9352-0d3b0a1c19db
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420603430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.3420603430
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.916975994
Short name T864
Test name
Test status
Simulation time 44179289 ps
CPU time 1.34 seconds
Started Jul 07 06:35:34 PM PDT 24
Finished Jul 07 06:35:36 PM PDT 24
Peak memory 209300 kb
Host smart-1b2f430f-0067-4904-93d1-d9813ccb8fc2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916975994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasing
.916975994
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2762462184
Short name T941
Test name
Test status
Simulation time 120580938 ps
CPU time 1.95 seconds
Started Jul 07 06:35:33 PM PDT 24
Finished Jul 07 06:35:35 PM PDT 24
Peak memory 217224 kb
Host smart-46e113ef-ee3e-4109-bf2e-c613f3be5593
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762462184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.2762462184
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2142843217
Short name T172
Test name
Test status
Simulation time 39800779 ps
CPU time 0.98 seconds
Started Jul 07 06:35:34 PM PDT 24
Finished Jul 07 06:35:35 PM PDT 24
Peak memory 209576 kb
Host smart-5af4ba8d-6149-4a14-b90d-c5f04b86e605
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142843217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.2142843217
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.982326475
Short name T927
Test name
Test status
Simulation time 19354663 ps
CPU time 1.19 seconds
Started Jul 07 06:35:32 PM PDT 24
Finished Jul 07 06:35:34 PM PDT 24
Peak memory 217572 kb
Host smart-938b858b-ba4e-4e33-b0d1-b8c7f80de320
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982326475 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.982326475
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3679322978
Short name T884
Test name
Test status
Simulation time 15773609 ps
CPU time 1.12 seconds
Started Jul 07 06:35:39 PM PDT 24
Finished Jul 07 06:35:40 PM PDT 24
Peak memory 209228 kb
Host smart-4a6af272-317f-48eb-ae01-269e1d2a1007
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679322978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.3679322978
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.343025709
Short name T871
Test name
Test status
Simulation time 144334928 ps
CPU time 1.48 seconds
Started Jul 07 06:35:32 PM PDT 24
Finished Jul 07 06:35:34 PM PDT 24
Peak memory 209260 kb
Host smart-0d69c6c6-95c6-4c1c-b97b-c545af1f2bd1
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343025709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.lc_ctrl_jtag_alert_test.343025709
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2643595147
Short name T918
Test name
Test status
Simulation time 1397580327 ps
CPU time 12.96 seconds
Started Jul 07 06:35:34 PM PDT 24
Finished Jul 07 06:35:47 PM PDT 24
Peak memory 209256 kb
Host smart-cc224412-287c-4e2e-ad71-29cae40adb66
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643595147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.2643595147
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1609250797
Short name T151
Test name
Test status
Simulation time 422083969 ps
CPU time 6.71 seconds
Started Jul 07 06:35:33 PM PDT 24
Finished Jul 07 06:35:41 PM PDT 24
Peak memory 209256 kb
Host smart-e832cf88-62c0-42db-b14f-0a2a0b32e994
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609250797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.1609250797
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2169031687
Short name T954
Test name
Test status
Simulation time 349370075 ps
CPU time 3.02 seconds
Started Jul 07 06:35:34 PM PDT 24
Finished Jul 07 06:35:37 PM PDT 24
Peak memory 210844 kb
Host smart-96e83085-449d-4a6b-a5d1-976de8133b8e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169031687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.2169031687
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2038456573
Short name T126
Test name
Test status
Simulation time 123145390 ps
CPU time 3.59 seconds
Started Jul 07 06:35:33 PM PDT 24
Finished Jul 07 06:35:38 PM PDT 24
Peak memory 217528 kb
Host smart-11025252-2c4d-4875-9225-9d488d93ca34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203845
6573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2038456573
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2982704599
Short name T928
Test name
Test status
Simulation time 122068573 ps
CPU time 2.09 seconds
Started Jul 07 06:35:34 PM PDT 24
Finished Jul 07 06:35:36 PM PDT 24
Peak memory 209208 kb
Host smart-4eb5c286-e64e-4210-9957-edaa90151b3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982704599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.2982704599
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.222984596
Short name T904
Test name
Test status
Simulation time 39332160 ps
CPU time 1.27 seconds
Started Jul 07 06:35:32 PM PDT 24
Finished Jul 07 06:35:34 PM PDT 24
Peak memory 209320 kb
Host smart-a61f341e-a3d7-4c4b-b9e5-e4e6bef74631
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222984596 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.222984596
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1496562417
Short name T919
Test name
Test status
Simulation time 24632070 ps
CPU time 1.14 seconds
Started Jul 07 06:35:39 PM PDT 24
Finished Jul 07 06:35:40 PM PDT 24
Peak memory 209404 kb
Host smart-26ef7802-de21-4e7a-8452-27ba00fb535b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496562417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.1496562417
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.504623194
Short name T120
Test name
Test status
Simulation time 82011404 ps
CPU time 1.35 seconds
Started Jul 07 06:35:33 PM PDT 24
Finished Jul 07 06:35:34 PM PDT 24
Peak memory 217496 kb
Host smart-af9fff8e-c370-496e-bf4c-90ca1feb7aa0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504623194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.504623194
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1565998801
Short name T978
Test name
Test status
Simulation time 59562529 ps
CPU time 2.04 seconds
Started Jul 07 06:35:33 PM PDT 24
Finished Jul 07 06:35:36 PM PDT 24
Peak memory 221908 kb
Host smart-9f2df8d5-1c07-4869-b9d0-0b8a1d3bf57c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565998801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.1565998801
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3509175608
Short name T863
Test name
Test status
Simulation time 14193606 ps
CPU time 0.99 seconds
Started Jul 07 06:35:39 PM PDT 24
Finished Jul 07 06:35:40 PM PDT 24
Peak memory 209428 kb
Host smart-d8e40548-6f8e-4ac0-bba3-e86924eabcd0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509175608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.3509175608
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2313182942
Short name T969
Test name
Test status
Simulation time 52221220 ps
CPU time 1.5 seconds
Started Jul 07 06:35:40 PM PDT 24
Finished Jul 07 06:35:42 PM PDT 24
Peak memory 209300 kb
Host smart-2d260714-ec93-4269-a74d-407898319a90
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313182942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.2313182942
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3053668714
Short name T182
Test name
Test status
Simulation time 22229545 ps
CPU time 1.13 seconds
Started Jul 07 06:35:36 PM PDT 24
Finished Jul 07 06:35:38 PM PDT 24
Peak memory 211232 kb
Host smart-34ac9708-835a-4fe3-8baf-fbf8a5f8fd64
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053668714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.3053668714
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1142923812
Short name T925
Test name
Test status
Simulation time 16978514 ps
CPU time 1.18 seconds
Started Jul 07 06:35:35 PM PDT 24
Finished Jul 07 06:35:37 PM PDT 24
Peak memory 217552 kb
Host smart-64a49866-c1e2-46e5-95f8-2c7867120ae0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142923812 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.1142923812
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.4149833406
Short name T901
Test name
Test status
Simulation time 13870842 ps
CPU time 1.02 seconds
Started Jul 07 06:35:40 PM PDT 24
Finished Jul 07 06:35:42 PM PDT 24
Peak memory 209012 kb
Host smart-f55e81d8-f4fa-4a89-9a9a-930e7ff93af1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149833406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.4149833406
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.736990411
Short name T898
Test name
Test status
Simulation time 213540290 ps
CPU time 1.9 seconds
Started Jul 07 06:35:37 PM PDT 24
Finished Jul 07 06:35:39 PM PDT 24
Peak memory 208680 kb
Host smart-89eb9d38-a5ea-4f10-aaa5-2b5889421e7d
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736990411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.lc_ctrl_jtag_alert_test.736990411
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1189720035
Short name T961
Test name
Test status
Simulation time 6837344722 ps
CPU time 20.1 seconds
Started Jul 07 06:35:37 PM PDT 24
Finished Jul 07 06:35:57 PM PDT 24
Peak memory 217292 kb
Host smart-5181ccfa-383d-443a-acff-909f1716c606
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189720035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.1189720035
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1802388956
Short name T921
Test name
Test status
Simulation time 4528990806 ps
CPU time 22.62 seconds
Started Jul 07 06:35:39 PM PDT 24
Finished Jul 07 06:36:02 PM PDT 24
Peak memory 209124 kb
Host smart-7c2f04f0-4144-443e-8656-79a5498c3f3c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802388956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.1802388956
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1729906802
Short name T891
Test name
Test status
Simulation time 198015968 ps
CPU time 1.67 seconds
Started Jul 07 06:35:36 PM PDT 24
Finished Jul 07 06:35:38 PM PDT 24
Peak memory 210864 kb
Host smart-708b7ca8-4d75-45a4-b05c-cc5c9aa14ea9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729906802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.1729906802
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2840497735
Short name T980
Test name
Test status
Simulation time 190442980 ps
CPU time 5.2 seconds
Started Jul 07 06:35:44 PM PDT 24
Finished Jul 07 06:35:50 PM PDT 24
Peak memory 222204 kb
Host smart-b4dad258-3902-475e-aa2c-4523943d6532
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284049
7735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2840497735
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1499338879
Short name T976
Test name
Test status
Simulation time 34959634 ps
CPU time 1.12 seconds
Started Jul 07 06:35:41 PM PDT 24
Finished Jul 07 06:35:43 PM PDT 24
Peak memory 209284 kb
Host smart-efccddc6-fa2d-4b5f-b9e9-9b748108514a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499338879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.1499338879
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1704019832
Short name T890
Test name
Test status
Simulation time 36445254 ps
CPU time 2.39 seconds
Started Jul 07 06:35:44 PM PDT 24
Finished Jul 07 06:35:46 PM PDT 24
Peak memory 217472 kb
Host smart-35485e6f-2b8c-4293-91ea-9dde5516f22d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704019832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.1704019832
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1921296316
Short name T128
Test name
Test status
Simulation time 224060123 ps
CPU time 6.33 seconds
Started Jul 07 06:35:40 PM PDT 24
Finished Jul 07 06:35:46 PM PDT 24
Peak memory 217488 kb
Host smart-8c785e0a-ff21-4a93-af36-1c9c205376b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921296316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.1921296316
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2622523479
Short name T896
Test name
Test status
Simulation time 17181679 ps
CPU time 1.43 seconds
Started Jul 07 06:36:03 PM PDT 24
Finished Jul 07 06:36:05 PM PDT 24
Peak memory 218596 kb
Host smart-58f0a65a-daec-4057-8965-52789905b70a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622523479 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.2622523479
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.433313136
Short name T178
Test name
Test status
Simulation time 15958636 ps
CPU time 0.88 seconds
Started Jul 07 06:36:03 PM PDT 24
Finished Jul 07 06:36:04 PM PDT 24
Peak memory 209280 kb
Host smart-4cbdc3a7-5e28-4830-9929-e4a9dac38d46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433313136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.433313136
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2368327003
Short name T906
Test name
Test status
Simulation time 54449110 ps
CPU time 1.53 seconds
Started Jul 07 06:36:02 PM PDT 24
Finished Jul 07 06:36:04 PM PDT 24
Peak memory 211312 kb
Host smart-6a653668-5935-462d-b933-20b2c60ed967
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368327003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.2368327003
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2544966484
Short name T133
Test name
Test status
Simulation time 554069731 ps
CPU time 2.24 seconds
Started Jul 07 06:36:03 PM PDT 24
Finished Jul 07 06:36:05 PM PDT 24
Peak memory 217496 kb
Host smart-9a1adb40-b21b-4b6a-8f10-5bdd04cb6c9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544966484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.2544966484
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2700646237
Short name T968
Test name
Test status
Simulation time 27112085 ps
CPU time 1.17 seconds
Started Jul 07 06:36:06 PM PDT 24
Finished Jul 07 06:36:08 PM PDT 24
Peak memory 217588 kb
Host smart-681943f3-7265-43c6-884b-be3290916c21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700646237 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.2700646237
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1034971973
Short name T973
Test name
Test status
Simulation time 24293025 ps
CPU time 1.27 seconds
Started Jul 07 06:36:09 PM PDT 24
Finished Jul 07 06:36:10 PM PDT 24
Peak memory 209340 kb
Host smart-6a3abf57-b4c4-4c93-9f18-d278e4137fc3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034971973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.1034971973
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1317548276
Short name T899
Test name
Test status
Simulation time 50077974 ps
CPU time 1.79 seconds
Started Jul 07 06:36:02 PM PDT 24
Finished Jul 07 06:36:05 PM PDT 24
Peak memory 217556 kb
Host smart-f19112b8-f394-4cbc-b769-b2860c920df7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317548276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.1317548276
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.497135934
Short name T956
Test name
Test status
Simulation time 25932556 ps
CPU time 1.53 seconds
Started Jul 07 06:36:08 PM PDT 24
Finished Jul 07 06:36:10 PM PDT 24
Peak memory 217552 kb
Host smart-4680049e-6761-41ab-8e7c-96f6e6b1eb7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497135934 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.497135934
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3471443389
Short name T175
Test name
Test status
Simulation time 14049080 ps
CPU time 1.05 seconds
Started Jul 07 06:36:07 PM PDT 24
Finished Jul 07 06:36:09 PM PDT 24
Peak memory 209292 kb
Host smart-8b149cfa-f2b0-465c-a396-ac6fd615142c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471443389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.3471443389
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.4168445568
Short name T933
Test name
Test status
Simulation time 70229430 ps
CPU time 1.16 seconds
Started Jul 07 06:36:05 PM PDT 24
Finished Jul 07 06:36:06 PM PDT 24
Peak memory 209284 kb
Host smart-bc367735-3e46-4a16-a36b-650d29cd8e7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168445568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.4168445568
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2161218031
Short name T903
Test name
Test status
Simulation time 269234370 ps
CPU time 3.09 seconds
Started Jul 07 06:36:05 PM PDT 24
Finished Jul 07 06:36:09 PM PDT 24
Peak memory 217512 kb
Host smart-5573b8b3-c0e5-4af6-9f53-b9cbafd3148a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161218031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.2161218031
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1528002565
Short name T924
Test name
Test status
Simulation time 57898379 ps
CPU time 1.24 seconds
Started Jul 07 06:36:06 PM PDT 24
Finished Jul 07 06:36:07 PM PDT 24
Peak memory 218648 kb
Host smart-8ce8fa2d-5e84-4b47-856f-77dbeb66b3ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528002565 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.1528002565
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2110521932
Short name T982
Test name
Test status
Simulation time 43881337 ps
CPU time 0.98 seconds
Started Jul 07 06:36:05 PM PDT 24
Finished Jul 07 06:36:07 PM PDT 24
Peak memory 209292 kb
Host smart-26c65499-9462-4491-b735-498e81bf6197
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110521932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.2110521932
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.506637656
Short name T936
Test name
Test status
Simulation time 306107408 ps
CPU time 1.38 seconds
Started Jul 07 06:36:07 PM PDT 24
Finished Jul 07 06:36:09 PM PDT 24
Peak memory 209340 kb
Host smart-97e95eb5-caff-4d07-8818-7e769824fe72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506637656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_same_csr_outstanding.506637656
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3331036907
Short name T132
Test name
Test status
Simulation time 109826990 ps
CPU time 3.25 seconds
Started Jul 07 06:36:08 PM PDT 24
Finished Jul 07 06:36:12 PM PDT 24
Peak memory 217496 kb
Host smart-f5db9e4b-e58a-43ac-8b28-6dee5ae82800
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331036907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.3331036907
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1503501184
Short name T952
Test name
Test status
Simulation time 97429453 ps
CPU time 2.86 seconds
Started Jul 07 06:36:06 PM PDT 24
Finished Jul 07 06:36:09 PM PDT 24
Peak memory 221932 kb
Host smart-e9cd4049-6d9a-46e8-bd35-39a95dc6848c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503501184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.1503501184
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.4209387028
Short name T932
Test name
Test status
Simulation time 22306143 ps
CPU time 1.1 seconds
Started Jul 07 06:36:06 PM PDT 24
Finished Jul 07 06:36:08 PM PDT 24
Peak memory 217632 kb
Host smart-ad72d270-3e3e-4efc-9faf-d7b4f609ea98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209387028 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.4209387028
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2303529020
Short name T887
Test name
Test status
Simulation time 159411448 ps
CPU time 0.84 seconds
Started Jul 07 06:36:05 PM PDT 24
Finished Jul 07 06:36:06 PM PDT 24
Peak memory 209220 kb
Host smart-600c5cb2-1b24-4390-8396-d9a9a7e0ef75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303529020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.2303529020
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2441446515
Short name T157
Test name
Test status
Simulation time 45590742 ps
CPU time 2.07 seconds
Started Jul 07 06:36:08 PM PDT 24
Finished Jul 07 06:36:10 PM PDT 24
Peak memory 217492 kb
Host smart-00af7f13-7701-4304-93b3-7c7bfbec1cad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441446515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.2441446515
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3054108869
Short name T141
Test name
Test status
Simulation time 112716018 ps
CPU time 2.28 seconds
Started Jul 07 06:36:07 PM PDT 24
Finished Jul 07 06:36:10 PM PDT 24
Peak memory 213016 kb
Host smart-fe40a68a-5c03-4bec-a61d-062f6db1e4ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054108869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.3054108869
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.1581191126
Short name T910
Test name
Test status
Simulation time 63736828 ps
CPU time 1.39 seconds
Started Jul 07 06:36:07 PM PDT 24
Finished Jul 07 06:36:08 PM PDT 24
Peak memory 217576 kb
Host smart-504341a1-a738-4575-bdbc-579aa96d3420
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581191126 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.1581191126
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2364390456
Short name T920
Test name
Test status
Simulation time 23291527 ps
CPU time 0.89 seconds
Started Jul 07 06:36:07 PM PDT 24
Finished Jul 07 06:36:09 PM PDT 24
Peak memory 209188 kb
Host smart-b0ff00ba-209b-4013-b848-0fa828cba825
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364390456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.2364390456
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2498890227
Short name T185
Test name
Test status
Simulation time 78078073 ps
CPU time 1.32 seconds
Started Jul 07 06:36:06 PM PDT 24
Finished Jul 07 06:36:08 PM PDT 24
Peak memory 217528 kb
Host smart-b1a072d6-2866-45b3-84cc-a438d66f2d3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498890227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.2498890227
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1491280809
Short name T136
Test name
Test status
Simulation time 218065447 ps
CPU time 2.42 seconds
Started Jul 07 06:36:09 PM PDT 24
Finished Jul 07 06:36:12 PM PDT 24
Peak memory 217508 kb
Host smart-01b17be0-1825-4ad0-b600-43b176a52325
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491280809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.1491280809
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3651605334
Short name T118
Test name
Test status
Simulation time 71608913 ps
CPU time 1.2 seconds
Started Jul 07 06:36:19 PM PDT 24
Finished Jul 07 06:36:21 PM PDT 24
Peak memory 217504 kb
Host smart-3ba318a0-7dbe-473f-a56c-70991fa7f804
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651605334 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.3651605334
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1468537189
Short name T953
Test name
Test status
Simulation time 18665126 ps
CPU time 1 seconds
Started Jul 07 06:36:19 PM PDT 24
Finished Jul 07 06:36:21 PM PDT 24
Peak memory 209244 kb
Host smart-521ea204-9a60-423f-91e1-a10b839bba69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468537189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.1468537189
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.781711281
Short name T886
Test name
Test status
Simulation time 56709706 ps
CPU time 0.99 seconds
Started Jul 07 06:36:10 PM PDT 24
Finished Jul 07 06:36:11 PM PDT 24
Peak memory 209240 kb
Host smart-ce9e8c74-86f4-4445-bbad-393d23c69c37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781711281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_same_csr_outstanding.781711281
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.794086840
Short name T883
Test name
Test status
Simulation time 40534506 ps
CPU time 2.5 seconds
Started Jul 07 06:36:07 PM PDT 24
Finished Jul 07 06:36:09 PM PDT 24
Peak memory 217712 kb
Host smart-26202219-6e77-43e5-8a9b-708860351932
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794086840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.794086840
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3417884470
Short name T964
Test name
Test status
Simulation time 106757192 ps
CPU time 1.54 seconds
Started Jul 07 06:36:11 PM PDT 24
Finished Jul 07 06:36:13 PM PDT 24
Peak memory 217664 kb
Host smart-f35bdc5b-4e7e-464f-ad76-bdc9a2a2418e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417884470 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.3417884470
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1166498555
Short name T939
Test name
Test status
Simulation time 34150679 ps
CPU time 0.82 seconds
Started Jul 07 06:36:13 PM PDT 24
Finished Jul 07 06:36:14 PM PDT 24
Peak memory 209240 kb
Host smart-ed9af6d5-7c17-4c17-96b1-a7d69a59c21c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166498555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.1166498555
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2509630357
Short name T881
Test name
Test status
Simulation time 22151514 ps
CPU time 1.25 seconds
Started Jul 07 06:36:09 PM PDT 24
Finished Jul 07 06:36:11 PM PDT 24
Peak memory 211328 kb
Host smart-5cd4f9bc-f436-4f25-acd7-8cad11cf98e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509630357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.2509630357
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.500430141
Short name T913
Test name
Test status
Simulation time 474088308 ps
CPU time 4.38 seconds
Started Jul 07 06:36:19 PM PDT 24
Finished Jul 07 06:36:23 PM PDT 24
Peak memory 217452 kb
Host smart-6eee37c1-4926-4652-a758-6d827df10b68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500430141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.500430141
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.574175563
Short name T138
Test name
Test status
Simulation time 46757788 ps
CPU time 1.94 seconds
Started Jul 07 06:36:14 PM PDT 24
Finished Jul 07 06:36:16 PM PDT 24
Peak memory 218704 kb
Host smart-606353d8-8bfe-4c0b-ba16-6004b58e5da1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574175563 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.574175563
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2488107091
Short name T867
Test name
Test status
Simulation time 12183954 ps
CPU time 0.87 seconds
Started Jul 07 06:36:14 PM PDT 24
Finished Jul 07 06:36:15 PM PDT 24
Peak memory 208772 kb
Host smart-4fab90b4-be06-417d-9e15-8e9ffe402a09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488107091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.2488107091
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2244523514
Short name T938
Test name
Test status
Simulation time 38850049 ps
CPU time 1.38 seconds
Started Jul 07 06:36:11 PM PDT 24
Finished Jul 07 06:36:13 PM PDT 24
Peak memory 211340 kb
Host smart-5d3ca473-10da-4332-9ff2-d8ca1516da37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244523514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.2244523514
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.84370890
Short name T951
Test name
Test status
Simulation time 168067205 ps
CPU time 2.47 seconds
Started Jul 07 06:36:17 PM PDT 24
Finished Jul 07 06:36:20 PM PDT 24
Peak memory 217848 kb
Host smart-1c90ae4f-f230-425d-a345-7ffad235d26c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84370890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.84370890
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1210717720
Short name T142
Test name
Test status
Simulation time 580809951 ps
CPU time 4.6 seconds
Started Jul 07 06:36:10 PM PDT 24
Finished Jul 07 06:36:15 PM PDT 24
Peak memory 217484 kb
Host smart-825e1395-906d-43bf-9f89-7ae09ecf4482
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210717720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.1210717720
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3688477233
Short name T895
Test name
Test status
Simulation time 63759658 ps
CPU time 1.28 seconds
Started Jul 07 06:36:08 PM PDT 24
Finished Jul 07 06:36:10 PM PDT 24
Peak memory 218144 kb
Host smart-251ca1ea-7b27-4627-86c5-756eada8657a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688477233 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.3688477233
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1247213221
Short name T949
Test name
Test status
Simulation time 37122161 ps
CPU time 0.8 seconds
Started Jul 07 06:36:19 PM PDT 24
Finished Jul 07 06:36:20 PM PDT 24
Peak memory 208960 kb
Host smart-56103030-99ea-4922-8554-d559e4d26dbd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247213221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.1247213221
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2697196675
Short name T186
Test name
Test status
Simulation time 18630169 ps
CPU time 1.03 seconds
Started Jul 07 06:36:06 PM PDT 24
Finished Jul 07 06:36:08 PM PDT 24
Peak memory 217464 kb
Host smart-17d7e8d7-4b66-40c0-8197-73b3166a31d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697196675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.2697196675
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2927300452
Short name T905
Test name
Test status
Simulation time 505097955 ps
CPU time 3.69 seconds
Started Jul 07 06:36:14 PM PDT 24
Finished Jul 07 06:36:19 PM PDT 24
Peak memory 218616 kb
Host smart-a4d68629-ac16-442e-8773-ed458fe712f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927300452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.2927300452
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2224615396
Short name T135
Test name
Test status
Simulation time 150723497 ps
CPU time 2.29 seconds
Started Jul 07 06:36:09 PM PDT 24
Finished Jul 07 06:36:12 PM PDT 24
Peak memory 222108 kb
Host smart-5a4a3a37-6e4d-4e33-b193-870b7412324f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224615396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.2224615396
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2470931507
Short name T970
Test name
Test status
Simulation time 709680535 ps
CPU time 1.76 seconds
Started Jul 07 06:35:45 PM PDT 24
Finished Jul 07 06:35:47 PM PDT 24
Peak memory 209280 kb
Host smart-5d793bf6-de6d-4f23-aa49-32f819f3dc8e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470931507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.2470931507
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1262924901
Short name T963
Test name
Test status
Simulation time 96916427 ps
CPU time 1.85 seconds
Started Jul 07 06:35:41 PM PDT 24
Finished Jul 07 06:35:44 PM PDT 24
Peak memory 217396 kb
Host smart-f6c9840a-8f24-49f7-9d73-3226da95b9d1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262924901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.1262924901
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1099902951
Short name T868
Test name
Test status
Simulation time 21772920 ps
CPU time 1.03 seconds
Started Jul 07 06:35:45 PM PDT 24
Finished Jul 07 06:35:46 PM PDT 24
Peak memory 209936 kb
Host smart-b08d6ea3-d842-43b3-890b-5997cd5a8d33
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099902951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.1099902951
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2315045885
Short name T935
Test name
Test status
Simulation time 26451003 ps
CPU time 1 seconds
Started Jul 07 06:35:39 PM PDT 24
Finished Jul 07 06:35:40 PM PDT 24
Peak memory 219392 kb
Host smart-df411310-e273-4961-80bb-af1394f893b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315045885 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.2315045885
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2928224647
Short name T177
Test name
Test status
Simulation time 60043271 ps
CPU time 0.99 seconds
Started Jul 07 06:35:44 PM PDT 24
Finished Jul 07 06:35:45 PM PDT 24
Peak memory 209296 kb
Host smart-71632914-6eb4-4d63-a060-b0731341753c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928224647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.2928224647
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2349418341
Short name T960
Test name
Test status
Simulation time 111273805 ps
CPU time 1.36 seconds
Started Jul 07 06:35:42 PM PDT 24
Finished Jul 07 06:35:43 PM PDT 24
Peak memory 209152 kb
Host smart-66a09ece-9f2a-4b24-83c8-1f0592ab58cc
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349418341 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.2349418341
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3331537306
Short name T879
Test name
Test status
Simulation time 1825767146 ps
CPU time 20.46 seconds
Started Jul 07 06:35:40 PM PDT 24
Finished Jul 07 06:36:01 PM PDT 24
Peak memory 209220 kb
Host smart-6368bd49-fd32-4c96-b8c3-75d270a36f44
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331537306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.3331537306
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.884321505
Short name T950
Test name
Test status
Simulation time 766689824 ps
CPU time 18.6 seconds
Started Jul 07 06:35:41 PM PDT 24
Finished Jul 07 06:36:01 PM PDT 24
Peak memory 209188 kb
Host smart-781eb8bb-6639-4708-8931-06f4f43a642b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884321505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.884321505
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2139294765
Short name T944
Test name
Test status
Simulation time 82281567 ps
CPU time 2.62 seconds
Started Jul 07 06:35:43 PM PDT 24
Finished Jul 07 06:35:46 PM PDT 24
Peak memory 210940 kb
Host smart-11ef0110-6542-49bf-840b-4b42722dad5e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139294765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.2139294765
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2765589408
Short name T922
Test name
Test status
Simulation time 226092782 ps
CPU time 2.07 seconds
Started Jul 07 06:35:44 PM PDT 24
Finished Jul 07 06:35:46 PM PDT 24
Peak memory 217588 kb
Host smart-b5fcce36-31f1-424e-8060-bd9223d9f7bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276558
9408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2765589408
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2378501439
Short name T909
Test name
Test status
Simulation time 77717293 ps
CPU time 1.46 seconds
Started Jul 07 06:35:36 PM PDT 24
Finished Jul 07 06:35:38 PM PDT 24
Peak memory 209152 kb
Host smart-df7f12fc-7fcb-4258-a0e5-91ea66687229
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378501439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.2378501439
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3198710400
Short name T892
Test name
Test status
Simulation time 65728159 ps
CPU time 1.24 seconds
Started Jul 07 06:35:40 PM PDT 24
Finished Jul 07 06:35:42 PM PDT 24
Peak memory 211288 kb
Host smart-120771c0-2ebd-4f8a-9936-30ee172d4e3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198710400 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.3198710400
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2645382500
Short name T158
Test name
Test status
Simulation time 28111662 ps
CPU time 1.49 seconds
Started Jul 07 06:35:41 PM PDT 24
Finished Jul 07 06:35:43 PM PDT 24
Peak memory 209268 kb
Host smart-64d7fc5c-74fc-479f-aba6-14b21b40dcde
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645382500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.2645382500
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1920948983
Short name T988
Test name
Test status
Simulation time 117556394 ps
CPU time 2.28 seconds
Started Jul 07 06:35:40 PM PDT 24
Finished Jul 07 06:35:42 PM PDT 24
Peak memory 217676 kb
Host smart-51dff901-b916-451a-aa14-8a7b82484388
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920948983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.1920948983
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1083377162
Short name T176
Test name
Test status
Simulation time 19811487 ps
CPU time 1.22 seconds
Started Jul 07 06:35:44 PM PDT 24
Finished Jul 07 06:35:45 PM PDT 24
Peak memory 209340 kb
Host smart-0bb6d904-0c53-4600-af52-3d95a2afb89b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083377162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.1083377162
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.218602977
Short name T873
Test name
Test status
Simulation time 93977158 ps
CPU time 2.62 seconds
Started Jul 07 06:35:46 PM PDT 24
Finished Jul 07 06:35:49 PM PDT 24
Peak memory 209252 kb
Host smart-5cc52d12-3975-4dec-9117-47a92d7539e1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218602977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bash
.218602977
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3039333344
Short name T174
Test name
Test status
Simulation time 13934749 ps
CPU time 1.05 seconds
Started Jul 07 06:35:43 PM PDT 24
Finished Jul 07 06:35:45 PM PDT 24
Peak memory 210008 kb
Host smart-a2e9f347-f8ac-45c5-956e-1ac45c1cbecb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039333344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.3039333344
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.253841033
Short name T129
Test name
Test status
Simulation time 44387234 ps
CPU time 1.17 seconds
Started Jul 07 06:35:43 PM PDT 24
Finished Jul 07 06:35:45 PM PDT 24
Peak memory 217544 kb
Host smart-671b9d3f-445e-4b9f-acb5-30cdcfb5c07a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253841033 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.253841033
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2892725939
Short name T882
Test name
Test status
Simulation time 13926643 ps
CPU time 1.17 seconds
Started Jul 07 06:35:47 PM PDT 24
Finished Jul 07 06:35:48 PM PDT 24
Peak memory 209148 kb
Host smart-38d9faf7-5832-4f83-a65b-e99fdc579ecd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892725939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.2892725939
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2973739889
Short name T872
Test name
Test status
Simulation time 104443282 ps
CPU time 1.04 seconds
Started Jul 07 06:35:46 PM PDT 24
Finished Jul 07 06:35:47 PM PDT 24
Peak memory 209112 kb
Host smart-24cd674c-bc4c-4fec-b03a-b2f726fa8a81
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973739889 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.2973739889
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2866675330
Short name T979
Test name
Test status
Simulation time 5754731478 ps
CPU time 5.87 seconds
Started Jul 07 06:35:40 PM PDT 24
Finished Jul 07 06:35:46 PM PDT 24
Peak memory 217264 kb
Host smart-868bf149-3746-4f90-8886-367421300d98
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866675330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.2866675330
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1067744429
Short name T923
Test name
Test status
Simulation time 3475283372 ps
CPU time 39.55 seconds
Started Jul 07 06:35:42 PM PDT 24
Finished Jul 07 06:36:22 PM PDT 24
Peak memory 209316 kb
Host smart-6fedcbdf-eabe-4c08-9e5b-b1d314d07c65
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067744429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.1067744429
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3577413331
Short name T946
Test name
Test status
Simulation time 86347698 ps
CPU time 1.2 seconds
Started Jul 07 06:35:41 PM PDT 24
Finished Jul 07 06:35:43 PM PDT 24
Peak memory 210268 kb
Host smart-6a8bec07-8e03-43ce-af4f-af8e164dd3bc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577413331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.3577413331
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1927711799
Short name T167
Test name
Test status
Simulation time 71760798 ps
CPU time 1.68 seconds
Started Jul 07 06:35:45 PM PDT 24
Finished Jul 07 06:35:47 PM PDT 24
Peak memory 220576 kb
Host smart-6759d19f-0dc4-447e-a42c-563a4891febb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192771
1799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1927711799
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1456825966
Short name T959
Test name
Test status
Simulation time 113409318 ps
CPU time 1.33 seconds
Started Jul 07 06:35:40 PM PDT 24
Finished Jul 07 06:35:42 PM PDT 24
Peak memory 209236 kb
Host smart-5a1027c3-95c3-454d-afbb-6e23f07c9fe8
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456825966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.1456825966
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.691703173
Short name T876
Test name
Test status
Simulation time 48558733 ps
CPU time 1.45 seconds
Started Jul 07 06:35:41 PM PDT 24
Finished Jul 07 06:35:43 PM PDT 24
Peak memory 209316 kb
Host smart-80673d37-beeb-4c59-a4fe-d332c2ab420b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691703173 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.691703173
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2037929781
Short name T125
Test name
Test status
Simulation time 21953485 ps
CPU time 1.28 seconds
Started Jul 07 06:35:45 PM PDT 24
Finished Jul 07 06:35:47 PM PDT 24
Peak memory 209284 kb
Host smart-9f8ba981-cb34-4da8-a8a7-e5f9d4c7e604
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037929781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.2037929781
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2213847283
Short name T965
Test name
Test status
Simulation time 72991407 ps
CPU time 1.64 seconds
Started Jul 07 06:35:42 PM PDT 24
Finished Jul 07 06:35:44 PM PDT 24
Peak memory 217476 kb
Host smart-4783fe73-4fa2-4796-ab53-d87795a72537
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213847283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.2213847283
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.3872825758
Short name T183
Test name
Test status
Simulation time 19180284 ps
CPU time 1.35 seconds
Started Jul 07 06:35:49 PM PDT 24
Finished Jul 07 06:35:51 PM PDT 24
Peak memory 217408 kb
Host smart-3536b481-017a-45cb-b8d5-e4bf92151a3f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872825758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.3872825758
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3316435997
Short name T865
Test name
Test status
Simulation time 23701800 ps
CPU time 1.23 seconds
Started Jul 07 06:35:47 PM PDT 24
Finished Jul 07 06:35:49 PM PDT 24
Peak memory 208968 kb
Host smart-eac37e11-911a-43e7-980f-2e799b6724e0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316435997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.3316435997
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3369858983
Short name T179
Test name
Test status
Simulation time 20614586 ps
CPU time 1.05 seconds
Started Jul 07 06:35:51 PM PDT 24
Finished Jul 07 06:35:52 PM PDT 24
Peak memory 209792 kb
Host smart-e6570c74-e66f-4fd9-8087-8633585567fe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369858983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.3369858983
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3711064152
Short name T987
Test name
Test status
Simulation time 119832425 ps
CPU time 1.51 seconds
Started Jul 07 06:35:50 PM PDT 24
Finished Jul 07 06:35:52 PM PDT 24
Peak memory 222692 kb
Host smart-6fd6fb8d-fb60-40ea-bbac-c14f1877a9c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711064152 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.3711064152
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1428404136
Short name T893
Test name
Test status
Simulation time 112584280 ps
CPU time 0.98 seconds
Started Jul 07 06:35:47 PM PDT 24
Finished Jul 07 06:35:49 PM PDT 24
Peak memory 209296 kb
Host smart-040a7588-791f-4fd9-8209-aab71a08b89f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428404136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.1428404136
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.683377370
Short name T937
Test name
Test status
Simulation time 68693906 ps
CPU time 1.12 seconds
Started Jul 07 06:35:47 PM PDT 24
Finished Jul 07 06:35:49 PM PDT 24
Peak memory 209124 kb
Host smart-eed8cf00-de7a-42a5-bdb3-dac006aab535
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683377370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.lc_ctrl_jtag_alert_test.683377370
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3475126568
Short name T912
Test name
Test status
Simulation time 1710389011 ps
CPU time 5.73 seconds
Started Jul 07 06:35:46 PM PDT 24
Finished Jul 07 06:35:52 PM PDT 24
Peak memory 209212 kb
Host smart-0de9b356-de92-4adb-b355-49a5e65b3fd5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475126568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.3475126568
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.384346966
Short name T934
Test name
Test status
Simulation time 1383971477 ps
CPU time 15.53 seconds
Started Jul 07 06:35:47 PM PDT 24
Finished Jul 07 06:36:03 PM PDT 24
Peak memory 217132 kb
Host smart-fb4b1535-eda1-4eee-860e-5a411436d1e7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384346966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.384346966
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.1725815409
Short name T986
Test name
Test status
Simulation time 207721088 ps
CPU time 3.17 seconds
Started Jul 07 06:35:46 PM PDT 24
Finished Jul 07 06:35:50 PM PDT 24
Peak memory 217420 kb
Host smart-0259c480-bca9-4866-9819-c5eb03112720
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725815409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.1725815409
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4089376005
Short name T957
Test name
Test status
Simulation time 594449602 ps
CPU time 3.41 seconds
Started Jul 07 06:35:51 PM PDT 24
Finished Jul 07 06:35:54 PM PDT 24
Peak memory 218504 kb
Host smart-dfb634b0-4b64-408b-aaee-c5f2f53e87f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408937
6005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4089376005
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1680204752
Short name T897
Test name
Test status
Simulation time 571976331 ps
CPU time 2.52 seconds
Started Jul 07 06:35:43 PM PDT 24
Finished Jul 07 06:35:46 PM PDT 24
Peak memory 209224 kb
Host smart-2afeb56c-7c60-4510-b07a-0ccb149345f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680204752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.1680204752
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.810038890
Short name T948
Test name
Test status
Simulation time 40431620 ps
CPU time 1.88 seconds
Started Jul 07 06:35:46 PM PDT 24
Finished Jul 07 06:35:48 PM PDT 24
Peak memory 211224 kb
Host smart-beb60434-f1e7-4ea8-b076-c7aaf25be64d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810038890 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.810038890
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3707901959
Short name T975
Test name
Test status
Simulation time 37394257 ps
CPU time 1.38 seconds
Started Jul 07 06:35:52 PM PDT 24
Finished Jul 07 06:35:54 PM PDT 24
Peak memory 209320 kb
Host smart-e49f42b4-2de2-45ff-885e-ebce37668f54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707901959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.3707901959
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1554925725
Short name T900
Test name
Test status
Simulation time 66538383 ps
CPU time 2.53 seconds
Started Jul 07 06:35:48 PM PDT 24
Finished Jul 07 06:35:50 PM PDT 24
Peak memory 218288 kb
Host smart-b12d468d-bc9b-4acd-93aa-aeb2e16f7744
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554925725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.1554925725
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2551450644
Short name T974
Test name
Test status
Simulation time 89789693 ps
CPU time 1.35 seconds
Started Jul 07 06:35:57 PM PDT 24
Finished Jul 07 06:35:59 PM PDT 24
Peak memory 218564 kb
Host smart-891315f1-211d-497e-be4e-e1865a00993f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551450644 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.2551450644
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2620675173
Short name T908
Test name
Test status
Simulation time 15688706 ps
CPU time 0.96 seconds
Started Jul 07 06:35:52 PM PDT 24
Finished Jul 07 06:35:53 PM PDT 24
Peak memory 209036 kb
Host smart-0f9dd81f-665f-45bd-bd4b-10be6db8180b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620675173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.2620675173
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.4089132307
Short name T926
Test name
Test status
Simulation time 78045012 ps
CPU time 2.7 seconds
Started Jul 07 06:35:52 PM PDT 24
Finished Jul 07 06:35:55 PM PDT 24
Peak memory 209172 kb
Host smart-496e90b8-3e27-4f82-adb7-eef6205bfb5d
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089132307 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.4089132307
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.85663547
Short name T869
Test name
Test status
Simulation time 484659784 ps
CPU time 10.39 seconds
Started Jul 07 06:35:53 PM PDT 24
Finished Jul 07 06:36:04 PM PDT 24
Peak memory 209244 kb
Host smart-1628f223-03f7-4250-aec6-901684e3a430
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85663547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 5.lc_ctrl_jtag_csr_aliasing.85663547
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2148412289
Short name T902
Test name
Test status
Simulation time 630524532 ps
CPU time 14.43 seconds
Started Jul 07 06:35:51 PM PDT 24
Finished Jul 07 06:36:06 PM PDT 24
Peak memory 217104 kb
Host smart-a19f7814-eb2d-47b7-9dcd-d7e87b2f59b7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148412289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.2148412289
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3224287304
Short name T984
Test name
Test status
Simulation time 544143640 ps
CPU time 2.43 seconds
Started Jul 07 06:35:52 PM PDT 24
Finished Jul 07 06:35:55 PM PDT 24
Peak memory 210744 kb
Host smart-ef9682bd-7cd7-402a-a1cc-6cafa3e7e425
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224287304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.3224287304
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1859893017
Short name T943
Test name
Test status
Simulation time 86646639 ps
CPU time 3.46 seconds
Started Jul 07 06:35:49 PM PDT 24
Finished Jul 07 06:35:53 PM PDT 24
Peak memory 221944 kb
Host smart-7a8106bc-91ed-4027-94f1-f4dc8544f348
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185989
3017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1859893017
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2235941497
Short name T915
Test name
Test status
Simulation time 301457627 ps
CPU time 1.94 seconds
Started Jul 07 06:35:53 PM PDT 24
Finished Jul 07 06:35:55 PM PDT 24
Peak memory 209176 kb
Host smart-029e0f74-431f-4451-b6b6-7ebee86241f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235941497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.2235941497
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1888859268
Short name T942
Test name
Test status
Simulation time 175190803 ps
CPU time 1.41 seconds
Started Jul 07 06:35:52 PM PDT 24
Finished Jul 07 06:35:54 PM PDT 24
Peak memory 217444 kb
Host smart-1638d2ac-aa8a-4f21-b098-2382308b67bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888859268 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.1888859268
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1751935875
Short name T955
Test name
Test status
Simulation time 25103013 ps
CPU time 1.01 seconds
Started Jul 07 06:35:53 PM PDT 24
Finished Jul 07 06:35:55 PM PDT 24
Peak memory 217528 kb
Host smart-1f3ef0bc-9255-442a-9da6-ad2fcee732bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751935875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.1751935875
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3205922099
Short name T115
Test name
Test status
Simulation time 115126956 ps
CPU time 1.46 seconds
Started Jul 07 06:35:53 PM PDT 24
Finished Jul 07 06:35:55 PM PDT 24
Peak memory 217516 kb
Host smart-49f7b8d5-130e-4d3e-b789-24e952c64353
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205922099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.3205922099
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1481005566
Short name T140
Test name
Test status
Simulation time 43772089 ps
CPU time 2.29 seconds
Started Jul 07 06:35:54 PM PDT 24
Finished Jul 07 06:35:56 PM PDT 24
Peak memory 212900 kb
Host smart-948397b3-7f72-49ca-a823-9eca12040921
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481005566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.1481005566
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.585598711
Short name T929
Test name
Test status
Simulation time 51496735 ps
CPU time 1.89 seconds
Started Jul 07 06:35:54 PM PDT 24
Finished Jul 07 06:35:56 PM PDT 24
Peak memory 219396 kb
Host smart-78ac758e-cd39-40f9-8cd3-eb766a9079a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585598711 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.585598711
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.2924134933
Short name T947
Test name
Test status
Simulation time 46030394 ps
CPU time 0.87 seconds
Started Jul 07 06:35:54 PM PDT 24
Finished Jul 07 06:35:55 PM PDT 24
Peak memory 209248 kb
Host smart-fb16d98a-ec50-4c2f-a009-76eafe7b910a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924134933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.2924134933
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.4215379978
Short name T875
Test name
Test status
Simulation time 421578767 ps
CPU time 1.02 seconds
Started Jul 07 06:35:55 PM PDT 24
Finished Jul 07 06:35:56 PM PDT 24
Peak memory 208600 kb
Host smart-2bcee704-bb10-4218-a7ef-a7e8785dbe69
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215379978 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.4215379978
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.554693287
Short name T877
Test name
Test status
Simulation time 448780913 ps
CPU time 3.08 seconds
Started Jul 07 06:35:56 PM PDT 24
Finished Jul 07 06:36:00 PM PDT 24
Peak memory 209144 kb
Host smart-f5f4b802-6314-4654-8aa9-18920fdc935d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554693287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.554693287
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2740634210
Short name T870
Test name
Test status
Simulation time 6910196732 ps
CPU time 5.64 seconds
Started Jul 07 06:35:54 PM PDT 24
Finished Jul 07 06:36:00 PM PDT 24
Peak memory 209244 kb
Host smart-fc20b28d-750f-41be-a4ae-4df8b13af983
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740634210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.2740634210
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2918293700
Short name T983
Test name
Test status
Simulation time 83263172 ps
CPU time 1.71 seconds
Started Jul 07 06:35:53 PM PDT 24
Finished Jul 07 06:35:56 PM PDT 24
Peak memory 217448 kb
Host smart-4dfa94b6-0fad-4e9e-974f-e7b452f449bc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918293700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.2918293700
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.522234649
Short name T990
Test name
Test status
Simulation time 311595862 ps
CPU time 2.74 seconds
Started Jul 07 06:35:58 PM PDT 24
Finished Jul 07 06:36:01 PM PDT 24
Peak memory 218428 kb
Host smart-a8bb782c-df92-4a12-bec6-b422419dc2da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522234
649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.522234649
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.455823033
Short name T148
Test name
Test status
Simulation time 344798183 ps
CPU time 4.44 seconds
Started Jul 07 06:35:55 PM PDT 24
Finished Jul 07 06:35:59 PM PDT 24
Peak memory 217364 kb
Host smart-144c43e9-2998-49b4-acf8-2c214afc6890
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455823033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.455823033
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3367303516
Short name T123
Test name
Test status
Simulation time 40124474 ps
CPU time 1.36 seconds
Started Jul 07 06:35:57 PM PDT 24
Finished Jul 07 06:35:58 PM PDT 24
Peak memory 209244 kb
Host smart-de5e12ca-8ac8-4fdc-bbcb-dc5ccc05f9f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367303516 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.3367303516
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3747314845
Short name T159
Test name
Test status
Simulation time 149630594 ps
CPU time 1.8 seconds
Started Jul 07 06:35:55 PM PDT 24
Finished Jul 07 06:35:57 PM PDT 24
Peak memory 217504 kb
Host smart-93699dc3-e0cd-4d51-a816-87d45f43b83e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747314845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.3747314845
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2992217678
Short name T122
Test name
Test status
Simulation time 108877238 ps
CPU time 2.29 seconds
Started Jul 07 06:35:58 PM PDT 24
Finished Jul 07 06:36:00 PM PDT 24
Peak memory 218748 kb
Host smart-e6b05a26-215a-4f9d-9ff6-ca81a4116275
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992217678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.2992217678
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2518596203
Short name T131
Test name
Test status
Simulation time 93765663 ps
CPU time 2.34 seconds
Started Jul 07 06:35:55 PM PDT 24
Finished Jul 07 06:35:57 PM PDT 24
Peak memory 217500 kb
Host smart-795440b8-8427-46cd-8a40-e5acaa7db3f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518596203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.2518596203
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1566554357
Short name T958
Test name
Test status
Simulation time 153879165 ps
CPU time 1.36 seconds
Started Jul 07 06:36:00 PM PDT 24
Finished Jul 07 06:36:02 PM PDT 24
Peak memory 222136 kb
Host smart-65c56dfa-7637-4f06-83dc-e35190a5bd5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566554357 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.1566554357
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1679423826
Short name T173
Test name
Test status
Simulation time 13545513 ps
CPU time 1.04 seconds
Started Jul 07 06:36:02 PM PDT 24
Finished Jul 07 06:36:04 PM PDT 24
Peak memory 208956 kb
Host smart-655142a6-ab56-4669-8bd2-9a55a81247bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679423826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.1679423826
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2425503120
Short name T907
Test name
Test status
Simulation time 170202157 ps
CPU time 2.43 seconds
Started Jul 07 06:36:00 PM PDT 24
Finished Jul 07 06:36:03 PM PDT 24
Peak memory 208712 kb
Host smart-5cae8db4-3ddc-4ad4-90b3-87541aca1f4d
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425503120 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.2425503120
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.974400634
Short name T972
Test name
Test status
Simulation time 665564864 ps
CPU time 6.85 seconds
Started Jul 07 06:35:59 PM PDT 24
Finished Jul 07 06:36:06 PM PDT 24
Peak memory 209216 kb
Host smart-0a0cb62c-8b08-4c0b-8317-8029880ac6a3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974400634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.974400634
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2216954650
Short name T985
Test name
Test status
Simulation time 565592704 ps
CPU time 5.76 seconds
Started Jul 07 06:36:00 PM PDT 24
Finished Jul 07 06:36:06 PM PDT 24
Peak memory 216984 kb
Host smart-a96a0636-d533-46bf-8eec-8b4c1278d8d6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216954650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.2216954650
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2954774034
Short name T866
Test name
Test status
Simulation time 93460925 ps
CPU time 3.07 seconds
Started Jul 07 06:35:56 PM PDT 24
Finished Jul 07 06:35:59 PM PDT 24
Peak memory 210968 kb
Host smart-b2b625c6-5626-417a-955d-5765edc2e09d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954774034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.2954774034
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3252960524
Short name T981
Test name
Test status
Simulation time 227919318 ps
CPU time 2.33 seconds
Started Jul 07 06:36:00 PM PDT 24
Finished Jul 07 06:36:02 PM PDT 24
Peak memory 218892 kb
Host smart-1f49291a-3e26-4b7c-adfb-444c1a68d662
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325296
0524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3252960524
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.482533238
Short name T971
Test name
Test status
Simulation time 2077101887 ps
CPU time 1.98 seconds
Started Jul 07 06:36:01 PM PDT 24
Finished Jul 07 06:36:03 PM PDT 24
Peak memory 209360 kb
Host smart-6d23ea7b-652b-46bc-81a0-0f4ef911e386
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482533238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.482533238
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3677803507
Short name T885
Test name
Test status
Simulation time 36865765 ps
CPU time 1.39 seconds
Started Jul 07 06:35:58 PM PDT 24
Finished Jul 07 06:35:59 PM PDT 24
Peak memory 209272 kb
Host smart-d648476f-b1b2-4624-859e-96352c10f46a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677803507 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.3677803507
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.774091618
Short name T880
Test name
Test status
Simulation time 37175325 ps
CPU time 1.45 seconds
Started Jul 07 06:36:01 PM PDT 24
Finished Jul 07 06:36:03 PM PDT 24
Peak memory 211416 kb
Host smart-30f086e7-694b-4a5c-99a8-d46892149be2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774091618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
same_csr_outstanding.774091618
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1557019693
Short name T962
Test name
Test status
Simulation time 320906757 ps
CPU time 4.36 seconds
Started Jul 07 06:35:59 PM PDT 24
Finished Jul 07 06:36:04 PM PDT 24
Peak memory 217512 kb
Host smart-7bc35ad4-2a99-49e7-817f-2732ee9c36c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557019693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.1557019693
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.480471026
Short name T977
Test name
Test status
Simulation time 97192753 ps
CPU time 1.97 seconds
Started Jul 07 06:36:00 PM PDT 24
Finished Jul 07 06:36:02 PM PDT 24
Peak memory 223352 kb
Host smart-60fa5fdd-6a05-4867-8096-0a199b266feb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480471026 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.480471026
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3757442057
Short name T966
Test name
Test status
Simulation time 22265258 ps
CPU time 0.85 seconds
Started Jul 07 06:36:00 PM PDT 24
Finished Jul 07 06:36:01 PM PDT 24
Peak memory 209232 kb
Host smart-83e3be1e-d11d-457a-84e3-73c53f2fdd6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757442057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.3757442057
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3625036282
Short name T940
Test name
Test status
Simulation time 24067725 ps
CPU time 1.04 seconds
Started Jul 07 06:36:02 PM PDT 24
Finished Jul 07 06:36:04 PM PDT 24
Peak memory 209084 kb
Host smart-638dcf44-316f-4708-a448-65ad75baffed
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625036282 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.3625036282
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2725428548
Short name T150
Test name
Test status
Simulation time 450355460 ps
CPU time 3.04 seconds
Started Jul 07 06:35:58 PM PDT 24
Finished Jul 07 06:36:02 PM PDT 24
Peak memory 209200 kb
Host smart-b92dec93-bf6f-43d3-b3b2-9575ffaf40b8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725428548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.2725428548
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.4186531402
Short name T945
Test name
Test status
Simulation time 982559975 ps
CPU time 12.31 seconds
Started Jul 07 06:35:59 PM PDT 24
Finished Jul 07 06:36:12 PM PDT 24
Peak memory 209188 kb
Host smart-84edf17d-bdc3-49c6-9b43-227874cdd52b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186531402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.4186531402
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2354236550
Short name T147
Test name
Test status
Simulation time 119161587 ps
CPU time 1.45 seconds
Started Jul 07 06:36:01 PM PDT 24
Finished Jul 07 06:36:02 PM PDT 24
Peak memory 217560 kb
Host smart-b31ca521-b2c6-4ca8-b75e-6a6f51b73347
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354236550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.2354236550
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2825643727
Short name T894
Test name
Test status
Simulation time 275393219 ps
CPU time 2.7 seconds
Started Jul 07 06:35:59 PM PDT 24
Finished Jul 07 06:36:02 PM PDT 24
Peak memory 219184 kb
Host smart-8921875e-33be-4488-a494-99968306f4fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282564
3727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2825643727
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2719741811
Short name T931
Test name
Test status
Simulation time 73110124 ps
CPU time 1.48 seconds
Started Jul 07 06:35:59 PM PDT 24
Finished Jul 07 06:36:01 PM PDT 24
Peak memory 209188 kb
Host smart-4aa795d2-b9f1-41d6-94d6-708b40737dec
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719741811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.2719741811
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2630479518
Short name T878
Test name
Test status
Simulation time 68414405 ps
CPU time 1.17 seconds
Started Jul 07 06:36:00 PM PDT 24
Finished Jul 07 06:36:02 PM PDT 24
Peak memory 209604 kb
Host smart-b385002d-1aa2-40bb-9793-f0d22a6a83ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630479518 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.2630479518
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.4201104400
Short name T930
Test name
Test status
Simulation time 51408778 ps
CPU time 1.46 seconds
Started Jul 07 06:35:59 PM PDT 24
Finished Jul 07 06:36:01 PM PDT 24
Peak memory 209308 kb
Host smart-ad329a99-028c-424a-bfda-8d85243dcbed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201104400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.4201104400
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1030785591
Short name T914
Test name
Test status
Simulation time 115910170 ps
CPU time 3.06 seconds
Started Jul 07 06:36:00 PM PDT 24
Finished Jul 07 06:36:03 PM PDT 24
Peak memory 217784 kb
Host smart-2fe61842-f3c3-477d-9205-cddb753cc23b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030785591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.1030785591
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1195216865
Short name T967
Test name
Test status
Simulation time 51868013 ps
CPU time 1.3 seconds
Started Jul 07 06:36:03 PM PDT 24
Finished Jul 07 06:36:05 PM PDT 24
Peak memory 217560 kb
Host smart-f80b6a14-f992-4161-9221-6776a8d72dc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195216865 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.1195216865
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3984319055
Short name T181
Test name
Test status
Simulation time 12246134 ps
CPU time 0.88 seconds
Started Jul 07 06:36:05 PM PDT 24
Finished Jul 07 06:36:07 PM PDT 24
Peak memory 209300 kb
Host smart-c9bd352d-4066-436b-95fd-b443ec2a12b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984319055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.3984319055
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.3969957209
Short name T911
Test name
Test status
Simulation time 693715860 ps
CPU time 1.56 seconds
Started Jul 07 06:36:03 PM PDT 24
Finished Jul 07 06:36:05 PM PDT 24
Peak memory 209372 kb
Host smart-5ca09eed-c33d-425b-96bd-ac22776843a7
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969957209 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.3969957209
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1479671251
Short name T874
Test name
Test status
Simulation time 587341609 ps
CPU time 6.89 seconds
Started Jul 07 06:36:05 PM PDT 24
Finished Jul 07 06:36:13 PM PDT 24
Peak memory 209220 kb
Host smart-43bcbc43-c880-4a77-b102-7ec6cfad2a69
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479671251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.1479671251
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2139779351
Short name T917
Test name
Test status
Simulation time 2357302070 ps
CPU time 27.08 seconds
Started Jul 07 06:36:04 PM PDT 24
Finished Jul 07 06:36:31 PM PDT 24
Peak memory 209236 kb
Host smart-01689c3b-70f1-4513-af31-d7bddd849f93
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139779351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.2139779351
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2014348644
Short name T888
Test name
Test status
Simulation time 1716534918 ps
CPU time 2.72 seconds
Started Jul 07 06:36:00 PM PDT 24
Finished Jul 07 06:36:03 PM PDT 24
Peak memory 217664 kb
Host smart-8500f3df-5b2c-4542-9002-7246c8c1919e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014348644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.2014348644
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.806237492
Short name T989
Test name
Test status
Simulation time 1669199959 ps
CPU time 1.77 seconds
Started Jul 07 06:36:02 PM PDT 24
Finished Jul 07 06:36:05 PM PDT 24
Peak memory 217644 kb
Host smart-1eb90232-db06-4b3e-b151-607f1588cd7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806237
492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.806237492
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.455172023
Short name T889
Test name
Test status
Simulation time 223789236 ps
CPU time 1.57 seconds
Started Jul 07 06:36:02 PM PDT 24
Finished Jul 07 06:36:03 PM PDT 24
Peak memory 209228 kb
Host smart-47c05317-fbc6-47c0-af02-6b078f858cfe
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455172023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.455172023
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2931597656
Short name T184
Test name
Test status
Simulation time 70683913 ps
CPU time 1.79 seconds
Started Jul 07 06:36:01 PM PDT 24
Finished Jul 07 06:36:03 PM PDT 24
Peak memory 217508 kb
Host smart-62d761d8-a98a-48b4-a2c6-4f559e28dbbd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931597656 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.2931597656
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3127252094
Short name T160
Test name
Test status
Simulation time 180867807 ps
CPU time 1.52 seconds
Started Jul 07 06:36:04 PM PDT 24
Finished Jul 07 06:36:06 PM PDT 24
Peak memory 211432 kb
Host smart-c602b516-0cf4-488c-acce-b69ea9a9de61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127252094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.3127252094
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3862162873
Short name T916
Test name
Test status
Simulation time 120914584 ps
CPU time 3.22 seconds
Started Jul 07 06:36:02 PM PDT 24
Finished Jul 07 06:36:05 PM PDT 24
Peak memory 217488 kb
Host smart-358accfa-c397-4cac-bd04-62a4200d2caa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862162873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.3862162873
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.1327744948
Short name T103
Test name
Test status
Simulation time 10827974 ps
CPU time 0.82 seconds
Started Jul 07 06:59:07 PM PDT 24
Finished Jul 07 06:59:08 PM PDT 24
Peak memory 208676 kb
Host smart-565454e7-9170-4964-9373-f483eddc755f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327744948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.1327744948
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.2287887452
Short name T388
Test name
Test status
Simulation time 1301457157 ps
CPU time 13.53 seconds
Started Jul 07 06:59:06 PM PDT 24
Finished Jul 07 06:59:20 PM PDT 24
Peak memory 217804 kb
Host smart-414c3f28-1e90-4a24-9739-993afae8ef76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287887452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.2287887452
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.3639575690
Short name T678
Test name
Test status
Simulation time 1057766554 ps
CPU time 5.92 seconds
Started Jul 07 06:59:08 PM PDT 24
Finished Jul 07 06:59:14 PM PDT 24
Peak memory 216608 kb
Host smart-343c5643-2b2c-412f-9b8a-41cafd60e9f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639575690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.3639575690
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.865142236
Short name T46
Test name
Test status
Simulation time 2010065390 ps
CPU time 61.93 seconds
Started Jul 07 06:59:05 PM PDT 24
Finished Jul 07 07:00:07 PM PDT 24
Peak memory 217780 kb
Host smart-2cc22086-e0f3-4389-a779-bce6548f1c3b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865142236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_err
ors.865142236
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.2847103366
Short name T395
Test name
Test status
Simulation time 10755994067 ps
CPU time 59.28 seconds
Started Jul 07 06:59:08 PM PDT 24
Finished Jul 07 07:00:07 PM PDT 24
Peak memory 217340 kb
Host smart-41b9c682-acf4-4093-82c4-d50a725ab60c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847103366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.2
847103366
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.2079962045
Short name T579
Test name
Test status
Simulation time 99713464 ps
CPU time 2.81 seconds
Started Jul 07 06:59:05 PM PDT 24
Finished Jul 07 06:59:08 PM PDT 24
Peak memory 217700 kb
Host smart-2ba17e7f-6b04-4136-8f1c-acb466e5e244
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079962045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.2079962045
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.1457538675
Short name T561
Test name
Test status
Simulation time 2828352461 ps
CPU time 17.44 seconds
Started Jul 07 06:59:09 PM PDT 24
Finished Jul 07 06:59:27 PM PDT 24
Peak memory 217196 kb
Host smart-7d27c058-5013-4897-a646-6888bee9850f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457538675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.1457538675
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.2814947626
Short name T257
Test name
Test status
Simulation time 3210911002 ps
CPU time 6 seconds
Started Jul 07 06:59:08 PM PDT 24
Finished Jul 07 06:59:14 PM PDT 24
Peak memory 217184 kb
Host smart-df0c1cda-220d-4728-89f2-73a53d34ac2a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814947626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
2814947626
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.2277814129
Short name T732
Test name
Test status
Simulation time 116642382 ps
CPU time 2.71 seconds
Started Jul 07 06:59:08 PM PDT 24
Finished Jul 07 06:59:10 PM PDT 24
Peak memory 217764 kb
Host smart-a2bbd602-deea-4e4b-b9b8-48a5197b0b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277814129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.2277814129
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.134974356
Short name T421
Test name
Test status
Simulation time 3194054456 ps
CPU time 8.92 seconds
Started Jul 07 06:59:06 PM PDT 24
Finished Jul 07 06:59:15 PM PDT 24
Peak memory 214480 kb
Host smart-06c2eab1-d540-4180-88d0-a7afcf32f466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134974356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.134974356
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.1615335807
Short name T288
Test name
Test status
Simulation time 283536678 ps
CPU time 9.8 seconds
Started Jul 07 06:59:08 PM PDT 24
Finished Jul 07 06:59:18 PM PDT 24
Peak memory 218428 kb
Host smart-c8f9b323-926d-495e-b4d9-1b5e86ee4318
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615335807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.1615335807
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.3371559293
Short name T548
Test name
Test status
Simulation time 1721218707 ps
CPU time 12.81 seconds
Started Jul 07 06:59:09 PM PDT 24
Finished Jul 07 06:59:22 PM PDT 24
Peak memory 225508 kb
Host smart-6ed7a8f8-5777-4ae8-80cd-8532908aafdd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371559293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.3371559293
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.1509932211
Short name T637
Test name
Test status
Simulation time 555079510 ps
CPU time 7.74 seconds
Started Jul 07 06:59:09 PM PDT 24
Finished Jul 07 06:59:17 PM PDT 24
Peak memory 217812 kb
Host smart-136c6b8f-487c-4290-8088-1dda23150870
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509932211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.1
509932211
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.648606307
Short name T58
Test name
Test status
Simulation time 176011625 ps
CPU time 7.6 seconds
Started Jul 07 06:59:06 PM PDT 24
Finished Jul 07 06:59:14 PM PDT 24
Peak memory 224608 kb
Host smart-4f4606bb-922f-4943-9199-d6de3d4fbc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648606307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.648606307
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.2396238893
Short name T384
Test name
Test status
Simulation time 182271365 ps
CPU time 3.03 seconds
Started Jul 07 06:59:09 PM PDT 24
Finished Jul 07 06:59:12 PM PDT 24
Peak memory 214436 kb
Host smart-6da722e4-3a4b-4d34-a004-7d28b7648108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396238893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.2396238893
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.441569082
Short name T534
Test name
Test status
Simulation time 510535627 ps
CPU time 28.6 seconds
Started Jul 07 06:59:06 PM PDT 24
Finished Jul 07 06:59:35 PM PDT 24
Peak memory 250524 kb
Host smart-b1445b7c-8024-4d1a-bce9-e400ee3543f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441569082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.441569082
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.1342813172
Short name T684
Test name
Test status
Simulation time 90680328 ps
CPU time 10.06 seconds
Started Jul 07 06:59:09 PM PDT 24
Finished Jul 07 06:59:19 PM PDT 24
Peak memory 244580 kb
Host smart-9ddc448a-d46d-4ca8-8d1e-9f26f44b09d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342813172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.1342813172
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.2949919411
Short name T737
Test name
Test status
Simulation time 6275599738 ps
CPU time 109.54 seconds
Started Jul 07 06:59:10 PM PDT 24
Finished Jul 07 07:00:59 PM PDT 24
Peak memory 250564 kb
Host smart-d446e98a-6aa4-419e-9bb3-18361c9447f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949919411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.2949919411
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.1384325861
Short name T836
Test name
Test status
Simulation time 130619387 ps
CPU time 0.96 seconds
Started Jul 07 06:59:10 PM PDT 24
Finished Jul 07 06:59:11 PM PDT 24
Peak memory 217340 kb
Host smart-96ec1088-1869-4939-a70d-97dc249e5404
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384325861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.1384325861
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.4232341839
Short name T375
Test name
Test status
Simulation time 16921349 ps
CPU time 0.92 seconds
Started Jul 07 06:59:17 PM PDT 24
Finished Jul 07 06:59:19 PM PDT 24
Peak memory 208564 kb
Host smart-f14c23be-1e74-4cde-b6fd-a9b89ac02481
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232341839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.4232341839
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.1972771886
Short name T229
Test name
Test status
Simulation time 1185416376 ps
CPU time 16.53 seconds
Started Jul 07 06:59:14 PM PDT 24
Finished Jul 07 06:59:31 PM PDT 24
Peak memory 225596 kb
Host smart-963bf225-76e8-41b8-bf7b-471e3979776c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972771886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.1972771886
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.4176244634
Short name T708
Test name
Test status
Simulation time 117941890 ps
CPU time 1.35 seconds
Started Jul 07 06:59:18 PM PDT 24
Finished Jul 07 06:59:19 PM PDT 24
Peak memory 216580 kb
Host smart-7730b75a-7b58-48d2-b2e2-ed324b624e7e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176244634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.4176244634
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.1175656528
Short name T826
Test name
Test status
Simulation time 1351625332 ps
CPU time 22.24 seconds
Started Jul 07 06:59:22 PM PDT 24
Finished Jul 07 06:59:44 PM PDT 24
Peak memory 217728 kb
Host smart-39f30579-5042-4889-a3e0-e6268e9e770f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175656528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.1175656528
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.336371744
Short name T18
Test name
Test status
Simulation time 390593406 ps
CPU time 5.52 seconds
Started Jul 07 06:59:19 PM PDT 24
Finished Jul 07 06:59:25 PM PDT 24
Peak memory 217256 kb
Host smart-03ac8a3d-7f3f-485e-bb2b-40711aee89a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336371744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.336371744
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.3292095638
Short name T368
Test name
Test status
Simulation time 1383550095 ps
CPU time 11.1 seconds
Started Jul 07 06:59:14 PM PDT 24
Finished Jul 07 06:59:26 PM PDT 24
Peak memory 217688 kb
Host smart-c9d16061-22da-4f33-8dd3-0265e813ea4f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292095638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.3292095638
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.2675610605
Short name T310
Test name
Test status
Simulation time 3583403329 ps
CPU time 14.97 seconds
Started Jul 07 06:59:19 PM PDT 24
Finished Jul 07 06:59:34 PM PDT 24
Peak memory 217108 kb
Host smart-9dafd2cb-693b-49d6-a8f9-5fa7f83629b4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675610605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.2675610605
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.3331133974
Short name T540
Test name
Test status
Simulation time 1039180815 ps
CPU time 14.17 seconds
Started Jul 07 06:59:14 PM PDT 24
Finished Jul 07 06:59:28 PM PDT 24
Peak memory 217096 kb
Host smart-5de1422b-8a38-4e7d-bfea-b06cc3858dda
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331133974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
3331133974
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.3268632814
Short name T676
Test name
Test status
Simulation time 7372487620 ps
CPU time 67.21 seconds
Started Jul 07 06:59:18 PM PDT 24
Finished Jul 07 07:00:25 PM PDT 24
Peak memory 266908 kb
Host smart-230391ce-06b8-49fd-a905-1b95c5ad1645
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268632814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.3268632814
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.3336710530
Short name T199
Test name
Test status
Simulation time 385783240 ps
CPU time 7.82 seconds
Started Jul 07 06:59:14 PM PDT 24
Finished Jul 07 06:59:22 PM PDT 24
Peak memory 222468 kb
Host smart-cf80393b-aa04-4f27-b8fb-be9ec41c0635
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336710530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.3336710530
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.3470084212
Short name T726
Test name
Test status
Simulation time 620130118 ps
CPU time 6.18 seconds
Started Jul 07 06:59:15 PM PDT 24
Finished Jul 07 06:59:21 PM PDT 24
Peak memory 222436 kb
Host smart-6b8a4f21-6d9c-42e6-897e-1ff754f8cf8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470084212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.3470084212
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.595743719
Short name T634
Test name
Test status
Simulation time 940704604 ps
CPU time 9.53 seconds
Started Jul 07 06:59:10 PM PDT 24
Finished Jul 07 06:59:20 PM PDT 24
Peak memory 217200 kb
Host smart-909c5271-73a3-4028-b045-8d47ade840b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595743719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.595743719
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.3037935615
Short name T94
Test name
Test status
Simulation time 501939700 ps
CPU time 25.06 seconds
Started Jul 07 06:59:16 PM PDT 24
Finished Jul 07 06:59:41 PM PDT 24
Peak memory 268264 kb
Host smart-d3152007-5964-4fb2-9a08-94a35b359166
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037935615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.3037935615
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.2847717836
Short name T768
Test name
Test status
Simulation time 2677952233 ps
CPU time 21.3 seconds
Started Jul 07 06:59:21 PM PDT 24
Finished Jul 07 06:59:43 PM PDT 24
Peak memory 219900 kb
Host smart-8c666f9d-b630-45d4-b54a-8de71f71a98f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847717836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.2847717836
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.3727329507
Short name T556
Test name
Test status
Simulation time 295752873 ps
CPU time 8.88 seconds
Started Jul 07 06:59:21 PM PDT 24
Finished Jul 07 06:59:30 PM PDT 24
Peak memory 225320 kb
Host smart-f9161f3c-5f65-4d1c-a4a7-8c05d399a51c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727329507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.3727329507
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.942798189
Short name T818
Test name
Test status
Simulation time 368308136 ps
CPU time 13.05 seconds
Started Jul 07 06:59:18 PM PDT 24
Finished Jul 07 06:59:31 PM PDT 24
Peak memory 217660 kb
Host smart-329df499-1582-483d-a40a-22caac08cbf0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942798189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.942798189
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.4233504708
Short name T42
Test name
Test status
Simulation time 197447355 ps
CPU time 7.72 seconds
Started Jul 07 06:59:13 PM PDT 24
Finished Jul 07 06:59:21 PM PDT 24
Peak memory 217932 kb
Host smart-7b45f88f-713a-4be9-b4e9-d21b2ef2588c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233504708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.4233504708
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.3244848326
Short name T833
Test name
Test status
Simulation time 208059495 ps
CPU time 3.27 seconds
Started Jul 07 06:59:13 PM PDT 24
Finished Jul 07 06:59:17 PM PDT 24
Peak memory 214408 kb
Host smart-96254259-10b5-43fc-aa32-68444f66507e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244848326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.3244848326
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.1023556512
Short name T847
Test name
Test status
Simulation time 238767260 ps
CPU time 26.63 seconds
Started Jul 07 06:59:12 PM PDT 24
Finished Jul 07 06:59:39 PM PDT 24
Peak memory 250600 kb
Host smart-e27f4246-3b1a-4921-8148-c8a9fd120d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023556512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.1023556512
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.3638617490
Short name T688
Test name
Test status
Simulation time 247812538 ps
CPU time 7.35 seconds
Started Jul 07 06:59:12 PM PDT 24
Finished Jul 07 06:59:19 PM PDT 24
Peak memory 242404 kb
Host smart-ba851261-07bf-4345-aefa-4b91bf5da1d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638617490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.3638617490
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.4042510982
Short name T276
Test name
Test status
Simulation time 36171236991 ps
CPU time 183.01 seconds
Started Jul 07 06:59:21 PM PDT 24
Finished Jul 07 07:02:24 PM PDT 24
Peak memory 283328 kb
Host smart-28dce90a-3d76-4da7-b370-5386a01c77ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042510982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.4042510982
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2367201003
Short name T237
Test name
Test status
Simulation time 22030035 ps
CPU time 1.11 seconds
Started Jul 07 06:59:18 PM PDT 24
Finished Jul 07 06:59:19 PM PDT 24
Peak memory 211432 kb
Host smart-ad179e08-4f9e-407e-a7c9-26a3ea2cbb40
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367201003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.2367201003
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.3629406482
Short name T282
Test name
Test status
Simulation time 35681745 ps
CPU time 0.93 seconds
Started Jul 07 07:00:29 PM PDT 24
Finished Jul 07 07:00:30 PM PDT 24
Peak memory 208544 kb
Host smart-8e1c385d-be40-42f1-8621-b714f7c5c736
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629406482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.3629406482
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.361055982
Short name T666
Test name
Test status
Simulation time 493193645 ps
CPU time 11.57 seconds
Started Jul 07 07:00:24 PM PDT 24
Finished Jul 07 07:00:36 PM PDT 24
Peak memory 217708 kb
Host smart-0c964d7f-992c-4b8b-8e0c-b882a5dbefee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361055982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.361055982
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.3050323940
Short name T20
Test name
Test status
Simulation time 399123883 ps
CPU time 5.96 seconds
Started Jul 07 07:00:27 PM PDT 24
Finished Jul 07 07:00:33 PM PDT 24
Peak memory 217188 kb
Host smart-f70cd509-2eec-4eda-af5f-ea605cb0a7b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050323940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.3050323940
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.3346393651
Short name T376
Test name
Test status
Simulation time 1366762632 ps
CPU time 41.76 seconds
Started Jul 07 07:00:27 PM PDT 24
Finished Jul 07 07:01:08 PM PDT 24
Peak memory 217736 kb
Host smart-e868bc8b-350b-410e-a7cc-c07bb39fef5e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346393651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.3346393651
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.3152315065
Short name T306
Test name
Test status
Simulation time 1634217376 ps
CPU time 5.6 seconds
Started Jul 07 07:00:25 PM PDT 24
Finished Jul 07 07:00:31 PM PDT 24
Peak memory 222720 kb
Host smart-e8b4de50-a7ef-4993-a264-01ec3647d811
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152315065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.3152315065
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.213860389
Short name T733
Test name
Test status
Simulation time 375611137 ps
CPU time 2.45 seconds
Started Jul 07 07:00:26 PM PDT 24
Finished Jul 07 07:00:28 PM PDT 24
Peak memory 217120 kb
Host smart-bb9d14d0-c111-4641-9599-4903ed7efaac
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213860389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke.
213860389
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.1745318188
Short name T398
Test name
Test status
Simulation time 4662585709 ps
CPU time 48.48 seconds
Started Jul 07 07:00:25 PM PDT 24
Finished Jul 07 07:01:13 PM PDT 24
Peak memory 275036 kb
Host smart-1bea1bbb-73da-450d-a4d1-4d89146ad369
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745318188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.1745318188
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.4060728631
Short name T326
Test name
Test status
Simulation time 406183707 ps
CPU time 13.75 seconds
Started Jul 07 07:00:24 PM PDT 24
Finished Jul 07 07:00:38 PM PDT 24
Peak memory 250428 kb
Host smart-80a08ab2-d1e1-4334-b23a-41faa02934cc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060728631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.4060728631
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.971958718
Short name T346
Test name
Test status
Simulation time 724271017 ps
CPU time 3.36 seconds
Started Jul 07 07:00:23 PM PDT 24
Finished Jul 07 07:00:27 PM PDT 24
Peak memory 221936 kb
Host smart-3cab2426-ff8a-4c16-8810-d93c36a3684e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971958718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.971958718
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.3625582778
Short name T673
Test name
Test status
Simulation time 1747774750 ps
CPU time 14.83 seconds
Started Jul 07 07:00:25 PM PDT 24
Finished Jul 07 07:00:40 PM PDT 24
Peak memory 219504 kb
Host smart-2f85fddf-b8d4-4ebc-a12a-0ecb8a6ff188
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625582778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.3625582778
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.1744592066
Short name T696
Test name
Test status
Simulation time 1269368709 ps
CPU time 11.78 seconds
Started Jul 07 07:00:29 PM PDT 24
Finished Jul 07 07:00:41 PM PDT 24
Peak memory 225500 kb
Host smart-37ee298d-dc4b-44b9-9141-89e366b28b67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744592066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.1744592066
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.1688082557
Short name T614
Test name
Test status
Simulation time 2781344802 ps
CPU time 14.04 seconds
Started Jul 07 07:00:26 PM PDT 24
Finished Jul 07 07:00:40 PM PDT 24
Peak memory 225580 kb
Host smart-b52744e0-2091-4902-a025-3e808130c50f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688082557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
1688082557
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.1809567794
Short name T781
Test name
Test status
Simulation time 771160471 ps
CPU time 7.88 seconds
Started Jul 07 07:00:25 PM PDT 24
Finished Jul 07 07:00:33 PM PDT 24
Peak memory 217856 kb
Host smart-6424207a-8a49-43be-96e6-bda2af3759b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809567794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.1809567794
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.3309448640
Short name T606
Test name
Test status
Simulation time 53069577 ps
CPU time 2.93 seconds
Started Jul 07 07:00:22 PM PDT 24
Finished Jul 07 07:00:26 PM PDT 24
Peak memory 213992 kb
Host smart-2355d170-37cd-41c1-8083-b07b742871f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309448640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.3309448640
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.2617366950
Short name T35
Test name
Test status
Simulation time 296814311 ps
CPU time 8.63 seconds
Started Jul 07 07:00:24 PM PDT 24
Finished Jul 07 07:00:33 PM PDT 24
Peak memory 250548 kb
Host smart-35254c1e-c145-4b29-8b1d-988cd2bec66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617366950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.2617366950
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.4214214848
Short name T238
Test name
Test status
Simulation time 28754006744 ps
CPU time 110.64 seconds
Started Jul 07 07:00:28 PM PDT 24
Finished Jul 07 07:02:18 PM PDT 24
Peak memory 272812 kb
Host smart-622fa59a-b323-49c5-b6ef-641fc970ebca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214214848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.4214214848
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.1716179307
Short name T738
Test name
Test status
Simulation time 47254664451 ps
CPU time 190.02 seconds
Started Jul 07 07:00:28 PM PDT 24
Finished Jul 07 07:03:38 PM PDT 24
Peak memory 283532 kb
Host smart-a952485e-0276-4326-9bb8-01d1e9372ba5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1716179307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.1716179307
Directory /workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.4207332943
Short name T216
Test name
Test status
Simulation time 13745027 ps
CPU time 0.93 seconds
Started Jul 07 07:00:22 PM PDT 24
Finished Jul 07 07:00:23 PM PDT 24
Peak memory 211308 kb
Host smart-7f5f19e0-3923-49f4-bc19-bf3105ea4324
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207332943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.4207332943
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.2380989056
Short name T838
Test name
Test status
Simulation time 96505270 ps
CPU time 1.24 seconds
Started Jul 07 07:00:36 PM PDT 24
Finished Jul 07 07:00:38 PM PDT 24
Peak memory 208592 kb
Host smart-21ef0899-f5df-428b-8bf4-17d396de8792
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380989056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.2380989056
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.2231643659
Short name T523
Test name
Test status
Simulation time 318623932 ps
CPU time 10.94 seconds
Started Jul 07 07:00:30 PM PDT 24
Finished Jul 07 07:00:42 PM PDT 24
Peak memory 225500 kb
Host smart-8bcfc64d-ad89-4967-ab54-525a59748dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231643659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.2231643659
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.993798210
Short name T647
Test name
Test status
Simulation time 329407913 ps
CPU time 1.34 seconds
Started Jul 07 07:00:40 PM PDT 24
Finished Jul 07 07:00:42 PM PDT 24
Peak memory 217196 kb
Host smart-b3f0ba1b-f36f-4b1c-ab36-b572d09de965
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993798210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.993798210
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.1312278612
Short name T746
Test name
Test status
Simulation time 1845226627 ps
CPU time 32.55 seconds
Started Jul 07 07:00:32 PM PDT 24
Finished Jul 07 07:01:05 PM PDT 24
Peak memory 217720 kb
Host smart-dbce9826-084f-4f4c-9f0b-536f33b66734
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312278612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.1312278612
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.3141782890
Short name T448
Test name
Test status
Simulation time 729529205 ps
CPU time 4.16 seconds
Started Jul 07 07:00:31 PM PDT 24
Finished Jul 07 07:00:35 PM PDT 24
Peak memory 217728 kb
Host smart-584d05ab-a730-46a1-b72c-47c4c2d19372
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141782890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.3141782890
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.377408752
Short name T483
Test name
Test status
Simulation time 705133024 ps
CPU time 16.82 seconds
Started Jul 07 07:00:30 PM PDT 24
Finished Jul 07 07:00:47 PM PDT 24
Peak memory 217116 kb
Host smart-99770b3d-4a1d-4775-8f29-6d535632b59a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377408752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke.
377408752
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.4086631389
Short name T785
Test name
Test status
Simulation time 1620253350 ps
CPU time 61.93 seconds
Started Jul 07 07:00:29 PM PDT 24
Finished Jul 07 07:01:32 PM PDT 24
Peak memory 275564 kb
Host smart-11f1fa88-4bc3-4d73-b816-1af02d30c611
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086631389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.4086631389
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.3058918998
Short name T598
Test name
Test status
Simulation time 86497444 ps
CPU time 4.43 seconds
Started Jul 07 07:00:29 PM PDT 24
Finished Jul 07 07:00:34 PM PDT 24
Peak memory 217792 kb
Host smart-a5f0da48-e520-44c4-be81-89ba04c0194a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058918998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.3058918998
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.2689200897
Short name T536
Test name
Test status
Simulation time 377599497 ps
CPU time 13.76 seconds
Started Jul 07 07:00:36 PM PDT 24
Finished Jul 07 07:00:50 PM PDT 24
Peak memory 225596 kb
Host smart-35ad40e2-220b-4094-8a73-8ec912cfe0a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689200897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.2689200897
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.492568981
Short name T516
Test name
Test status
Simulation time 2118109857 ps
CPU time 9.44 seconds
Started Jul 07 07:00:35 PM PDT 24
Finished Jul 07 07:00:44 PM PDT 24
Peak memory 225508 kb
Host smart-80a34df3-68f3-4ef2-b6d0-d39b54c5d9ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492568981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_di
gest.492568981
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.1463029128
Short name T856
Test name
Test status
Simulation time 422351893 ps
CPU time 8.83 seconds
Started Jul 07 07:00:33 PM PDT 24
Finished Jul 07 07:00:42 PM PDT 24
Peak memory 217696 kb
Host smart-1ec383b2-afbf-40d0-ad4c-d5bd60820530
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463029128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
1463029128
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.2690723437
Short name T544
Test name
Test status
Simulation time 815014315 ps
CPU time 14.57 seconds
Started Jul 07 07:00:33 PM PDT 24
Finished Jul 07 07:00:48 PM PDT 24
Peak memory 225564 kb
Host smart-8a2cd452-9a2c-4c36-8883-7d2c657992ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690723437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.2690723437
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.1348774346
Short name T465
Test name
Test status
Simulation time 199782939 ps
CPU time 11.42 seconds
Started Jul 07 07:00:28 PM PDT 24
Finished Jul 07 07:00:40 PM PDT 24
Peak memory 217240 kb
Host smart-4168380c-6292-422a-bf22-7328b2a68ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348774346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.1348774346
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.3596394726
Short name T841
Test name
Test status
Simulation time 981712712 ps
CPU time 27.51 seconds
Started Jul 07 07:00:31 PM PDT 24
Finished Jul 07 07:00:59 PM PDT 24
Peak memory 250564 kb
Host smart-0568719f-ffbe-49f6-a178-35dce7c57967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596394726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.3596394726
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.50920194
Short name T546
Test name
Test status
Simulation time 123866552 ps
CPU time 7.22 seconds
Started Jul 07 07:00:34 PM PDT 24
Finished Jul 07 07:00:41 PM PDT 24
Peak memory 250536 kb
Host smart-aed356ed-a7da-4263-8621-bfdb9434d484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50920194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.50920194
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.1344435367
Short name T166
Test name
Test status
Simulation time 52049692508 ps
CPU time 266.97 seconds
Started Jul 07 07:00:34 PM PDT 24
Finished Jul 07 07:05:01 PM PDT 24
Peak memory 267104 kb
Host smart-a49e8195-2cfb-4f0d-94f5-a96d6a189d38
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344435367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.1344435367
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.3901064197
Short name T112
Test name
Test status
Simulation time 92146869 ps
CPU time 0.94 seconds
Started Jul 07 07:00:32 PM PDT 24
Finished Jul 07 07:00:33 PM PDT 24
Peak memory 211372 kb
Host smart-e746a959-3335-4f72-bff9-0a0166b14d5a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901064197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.3901064197
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.1558481058
Short name T424
Test name
Test status
Simulation time 1018455023 ps
CPU time 12.07 seconds
Started Jul 07 07:00:37 PM PDT 24
Finished Jul 07 07:00:50 PM PDT 24
Peak memory 217792 kb
Host smart-358f822c-ac05-472b-9940-8d40323cedb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558481058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.1558481058
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.1336291703
Short name T563
Test name
Test status
Simulation time 3843000184 ps
CPU time 8.58 seconds
Started Jul 07 07:00:36 PM PDT 24
Finished Jul 07 07:00:45 PM PDT 24
Peak memory 217248 kb
Host smart-2622a722-6f99-4070-a9d8-6691380071e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336291703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.1336291703
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.3300174891
Short name T585
Test name
Test status
Simulation time 1580657252 ps
CPU time 28.53 seconds
Started Jul 07 07:00:41 PM PDT 24
Finished Jul 07 07:01:10 PM PDT 24
Peak memory 217972 kb
Host smart-3fd9e2d6-5c0a-4bc9-8d11-7fe4a42e0923
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300174891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.3300174891
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.637522917
Short name T787
Test name
Test status
Simulation time 393987465 ps
CPU time 12.27 seconds
Started Jul 07 07:00:38 PM PDT 24
Finished Jul 07 07:00:51 PM PDT 24
Peak memory 217696 kb
Host smart-ad54a506-e5d6-44a7-91b6-605183e775d7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637522917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag
_prog_failure.637522917
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.1523935339
Short name T645
Test name
Test status
Simulation time 1061748890 ps
CPU time 4.52 seconds
Started Jul 07 07:00:43 PM PDT 24
Finished Jul 07 07:00:48 PM PDT 24
Peak memory 217124 kb
Host smart-49398567-19c5-435d-9e44-2dac0dd295ab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523935339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.1523935339
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.3362107777
Short name T558
Test name
Test status
Simulation time 1441972215 ps
CPU time 41.78 seconds
Started Jul 07 07:00:38 PM PDT 24
Finished Jul 07 07:01:20 PM PDT 24
Peak memory 266860 kb
Host smart-55c1365f-8c09-40c0-851d-bd8ed4d4e2e0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362107777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.3362107777
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.1046159430
Short name T535
Test name
Test status
Simulation time 553086641 ps
CPU time 20.91 seconds
Started Jul 07 07:00:41 PM PDT 24
Finished Jul 07 07:01:03 PM PDT 24
Peak memory 250356 kb
Host smart-f8386aee-8f57-421c-9f8b-69cca1edc63b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046159430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.1046159430
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.302304532
Short name T30
Test name
Test status
Simulation time 27978476 ps
CPU time 1.86 seconds
Started Jul 07 07:00:39 PM PDT 24
Finished Jul 07 07:00:41 PM PDT 24
Peak memory 221576 kb
Host smart-d15789a8-7e03-4ea6-aec9-ee31d32b1ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302304532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.302304532
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.1590653131
Short name T635
Test name
Test status
Simulation time 1023299153 ps
CPU time 9.88 seconds
Started Jul 07 07:00:37 PM PDT 24
Finished Jul 07 07:00:47 PM PDT 24
Peak memory 225648 kb
Host smart-5b12661b-127c-4f13-a6bd-67391ff65682
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590653131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.1590653131
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.3491418098
Short name T32
Test name
Test status
Simulation time 461744435 ps
CPU time 16.46 seconds
Started Jul 07 07:00:43 PM PDT 24
Finished Jul 07 07:00:59 PM PDT 24
Peak memory 225516 kb
Host smart-df50850a-742b-4b81-a783-c891888131de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491418098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.3491418098
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.3457143465
Short name T246
Test name
Test status
Simulation time 635917251 ps
CPU time 10.39 seconds
Started Jul 07 07:00:38 PM PDT 24
Finished Jul 07 07:00:49 PM PDT 24
Peak memory 217652 kb
Host smart-d5552130-e3cf-4e8d-84c1-36d67d574f1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457143465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
3457143465
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.1857930359
Short name T261
Test name
Test status
Simulation time 1492036200 ps
CPU time 14.14 seconds
Started Jul 07 07:00:38 PM PDT 24
Finished Jul 07 07:00:53 PM PDT 24
Peak memory 225572 kb
Host smart-63796a8a-f903-40e7-bf8a-054ef770e39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857930359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.1857930359
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.683322326
Short name T718
Test name
Test status
Simulation time 108982337 ps
CPU time 2.06 seconds
Started Jul 07 07:00:41 PM PDT 24
Finished Jul 07 07:00:43 PM PDT 24
Peak memory 217200 kb
Host smart-c16a8098-243d-44e7-b69b-0ddf89974ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683322326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.683322326
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.3076507896
Short name T532
Test name
Test status
Simulation time 1169710631 ps
CPU time 25.76 seconds
Started Jul 07 07:00:40 PM PDT 24
Finished Jul 07 07:01:06 PM PDT 24
Peak memory 250532 kb
Host smart-05b37b6a-c60c-4b22-97db-b7ef800be4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076507896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.3076507896
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.2943400810
Short name T778
Test name
Test status
Simulation time 136419928 ps
CPU time 3.47 seconds
Started Jul 07 07:00:40 PM PDT 24
Finished Jul 07 07:00:44 PM PDT 24
Peak memory 221924 kb
Host smart-c373b1ed-f7e3-4e34-b238-d7b9ac4d6ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943400810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.2943400810
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.2785108723
Short name T311
Test name
Test status
Simulation time 4876088095 ps
CPU time 68.98 seconds
Started Jul 07 07:00:41 PM PDT 24
Finished Jul 07 07:01:50 PM PDT 24
Peak memory 249872 kb
Host smart-5e7ae93a-2f38-4303-9343-ec5998694e2b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785108723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.2785108723
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.1199570291
Short name T667
Test name
Test status
Simulation time 51925428 ps
CPU time 0.93 seconds
Started Jul 07 07:00:36 PM PDT 24
Finished Jul 07 07:00:37 PM PDT 24
Peak memory 211364 kb
Host smart-a95998aa-c5ad-42dd-a942-ae728bb2fbc1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199570291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.1199570291
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.1070264456
Short name T95
Test name
Test status
Simulation time 46254416 ps
CPU time 0.87 seconds
Started Jul 07 07:00:43 PM PDT 24
Finished Jul 07 07:00:45 PM PDT 24
Peak memory 208432 kb
Host smart-114f5430-9682-465d-98fd-f30aec2b6414
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070264456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.1070264456
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.2240300282
Short name T47
Test name
Test status
Simulation time 323080343 ps
CPU time 10.27 seconds
Started Jul 07 07:00:42 PM PDT 24
Finished Jul 07 07:00:52 PM PDT 24
Peak memory 217784 kb
Host smart-69200dce-2803-4f8b-84d9-5e5707e1d0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240300282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.2240300282
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.4181222549
Short name T616
Test name
Test status
Simulation time 4894995309 ps
CPU time 28.43 seconds
Started Jul 07 07:00:44 PM PDT 24
Finished Jul 07 07:01:13 PM PDT 24
Peak memory 217512 kb
Host smart-25ad43fd-58b6-452b-adbb-2849289f87f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181222549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.4181222549
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.3894310448
Short name T633
Test name
Test status
Simulation time 4574350946 ps
CPU time 35.75 seconds
Started Jul 07 07:00:44 PM PDT 24
Finished Jul 07 07:01:20 PM PDT 24
Peak memory 218536 kb
Host smart-527a89e6-4042-4b08-9c85-2bc28220631c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894310448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.3894310448
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.262777306
Short name T770
Test name
Test status
Simulation time 924982385 ps
CPU time 11.4 seconds
Started Jul 07 07:00:42 PM PDT 24
Finished Jul 07 07:00:53 PM PDT 24
Peak memory 224756 kb
Host smart-b216d677-f961-49b8-858b-7f1d5e541c53
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262777306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag
_prog_failure.262777306
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.767723279
Short name T205
Test name
Test status
Simulation time 236244416 ps
CPU time 4.01 seconds
Started Jul 07 07:00:43 PM PDT 24
Finished Jul 07 07:00:47 PM PDT 24
Peak memory 217160 kb
Host smart-f1199168-08f9-434c-8795-8b66b308f901
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767723279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke.
767723279
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.625328361
Short name T745
Test name
Test status
Simulation time 7231698063 ps
CPU time 47.81 seconds
Started Jul 07 07:00:44 PM PDT 24
Finished Jul 07 07:01:32 PM PDT 24
Peak memory 275232 kb
Host smart-21418d7c-5cda-47fb-bed5-ba30ebd67959
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625328361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_state_failure.625328361
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.245571911
Short name T839
Test name
Test status
Simulation time 3882417921 ps
CPU time 15.44 seconds
Started Jul 07 07:00:41 PM PDT 24
Finished Jul 07 07:00:57 PM PDT 24
Peak memory 247404 kb
Host smart-867dd875-d446-4b77-a119-6f625785dc2f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245571911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_
jtag_state_post_trans.245571911
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.3416146248
Short name T251
Test name
Test status
Simulation time 104612356 ps
CPU time 3.23 seconds
Started Jul 07 07:00:43 PM PDT 24
Finished Jul 07 07:00:46 PM PDT 24
Peak memory 217788 kb
Host smart-6cd5fec9-d425-44e8-a0d7-71ba2eda5f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416146248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.3416146248
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.1344050870
Short name T653
Test name
Test status
Simulation time 1167029257 ps
CPU time 16.66 seconds
Started Jul 07 07:00:42 PM PDT 24
Finished Jul 07 07:00:59 PM PDT 24
Peak memory 218360 kb
Host smart-f3f5d528-de00-432b-b472-341e9e0a908e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344050870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.1344050870
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.1695867418
Short name T655
Test name
Test status
Simulation time 275495149 ps
CPU time 8.99 seconds
Started Jul 07 07:00:45 PM PDT 24
Finished Jul 07 07:00:54 PM PDT 24
Peak memory 225528 kb
Host smart-4cb244ec-4c0c-47bb-a159-54dc4b2d9aba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695867418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.1695867418
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.552633662
Short name T739
Test name
Test status
Simulation time 1274522420 ps
CPU time 12.03 seconds
Started Jul 07 07:00:44 PM PDT 24
Finished Jul 07 07:00:57 PM PDT 24
Peak memory 217708 kb
Host smart-3e807c26-e636-4a64-ad75-cb5e3fd04649
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552633662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.552633662
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.1703301993
Short name T231
Test name
Test status
Simulation time 376533968 ps
CPU time 9.48 seconds
Started Jul 07 07:00:41 PM PDT 24
Finished Jul 07 07:00:51 PM PDT 24
Peak memory 224568 kb
Host smart-1f9fb4c7-c0bc-40b0-ab70-f6baf7dad6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703301993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.1703301993
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.1330612825
Short name T161
Test name
Test status
Simulation time 39227846 ps
CPU time 1.17 seconds
Started Jul 07 07:00:44 PM PDT 24
Finished Jul 07 07:00:45 PM PDT 24
Peak memory 213168 kb
Host smart-9ae1dfbc-c94d-495f-b8c5-3ebc3ab89774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330612825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.1330612825
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.717628596
Short name T854
Test name
Test status
Simulation time 349059084 ps
CPU time 30.79 seconds
Started Jul 07 07:00:41 PM PDT 24
Finished Jul 07 07:01:12 PM PDT 24
Peak memory 250532 kb
Host smart-a7d273ed-e430-4512-aa51-35837a171951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717628596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.717628596
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.2881729836
Short name T842
Test name
Test status
Simulation time 226439327 ps
CPU time 3.45 seconds
Started Jul 07 07:00:40 PM PDT 24
Finished Jul 07 07:00:44 PM PDT 24
Peak memory 217704 kb
Host smart-835a76dc-2fc6-48aa-9f02-3af99971fd5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881729836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.2881729836
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.231239286
Short name T363
Test name
Test status
Simulation time 2429717002 ps
CPU time 66.7 seconds
Started Jul 07 07:00:44 PM PDT 24
Finished Jul 07 07:01:51 PM PDT 24
Peak memory 247808 kb
Host smart-fec42d70-3f0e-4481-b698-e27c895aa995
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231239286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.231239286
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.168225684
Short name T155
Test name
Test status
Simulation time 95726014260 ps
CPU time 1057.41 seconds
Started Jul 07 07:00:44 PM PDT 24
Finished Jul 07 07:18:21 PM PDT 24
Peak memory 512824 kb
Host smart-cae531a8-fc0d-4a3f-9ebb-c0f9f4006a2b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=168225684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.168225684
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.2249300757
Short name T44
Test name
Test status
Simulation time 105462611 ps
CPU time 0.97 seconds
Started Jul 07 07:00:42 PM PDT 24
Finished Jul 07 07:00:43 PM PDT 24
Peak memory 208448 kb
Host smart-b88aa1bf-5ea1-4c9c-827e-ce21d593efb7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249300757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.2249300757
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.3765892259
Short name T848
Test name
Test status
Simulation time 16173962 ps
CPU time 1.14 seconds
Started Jul 07 07:00:54 PM PDT 24
Finished Jul 07 07:00:55 PM PDT 24
Peak memory 208556 kb
Host smart-f6b274ca-f52b-4998-8dfc-18cba76b75d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765892259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.3765892259
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.2755897094
Short name T449
Test name
Test status
Simulation time 272794729 ps
CPU time 8.06 seconds
Started Jul 07 07:00:50 PM PDT 24
Finished Jul 07 07:00:58 PM PDT 24
Peak memory 217836 kb
Host smart-1b76722b-21de-409e-9e92-7ce4d4a521b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755897094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.2755897094
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.2198304569
Short name T672
Test name
Test status
Simulation time 667049729 ps
CPU time 10.08 seconds
Started Jul 07 07:00:53 PM PDT 24
Finished Jul 07 07:01:03 PM PDT 24
Peak memory 216736 kb
Host smart-bbdeadf0-42ad-4ca2-9044-c751faef5ebe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198304569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.2198304569
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.2792215889
Short name T707
Test name
Test status
Simulation time 6533184975 ps
CPU time 31.41 seconds
Started Jul 07 07:00:53 PM PDT 24
Finished Jul 07 07:01:25 PM PDT 24
Peak memory 218072 kb
Host smart-57c2adc5-7fc0-4dc3-ac44-a88a91dad205
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792215889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.2792215889
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.4047763933
Short name T514
Test name
Test status
Simulation time 835787781 ps
CPU time 7.59 seconds
Started Jul 07 07:00:53 PM PDT 24
Finished Jul 07 07:01:00 PM PDT 24
Peak memory 217728 kb
Host smart-c24e270d-c9c2-4d3a-bf16-dd0db846695f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047763933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.4047763933
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.784072591
Short name T578
Test name
Test status
Simulation time 243165564 ps
CPU time 7.75 seconds
Started Jul 07 07:00:50 PM PDT 24
Finished Jul 07 07:00:58 PM PDT 24
Peak memory 217108 kb
Host smart-3bede342-2e1b-4b5b-b80c-0b2761e44f6f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784072591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke.
784072591
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.310631841
Short name T200
Test name
Test status
Simulation time 10323168309 ps
CPU time 59.46 seconds
Started Jul 07 07:00:48 PM PDT 24
Finished Jul 07 07:01:47 PM PDT 24
Peak memory 275500 kb
Host smart-963e60d8-146c-4b6f-815b-8d43222f2b4d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310631841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_state_failure.310631841
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.4111601654
Short name T806
Test name
Test status
Simulation time 1802869005 ps
CPU time 14.64 seconds
Started Jul 07 07:00:50 PM PDT 24
Finished Jul 07 07:01:05 PM PDT 24
Peak memory 222724 kb
Host smart-35e88df1-f8c2-4aad-813f-f8110fe5dcc4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111601654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.4111601654
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.2424341296
Short name T405
Test name
Test status
Simulation time 248713013 ps
CPU time 2.7 seconds
Started Jul 07 07:00:50 PM PDT 24
Finished Jul 07 07:00:53 PM PDT 24
Peak memory 217728 kb
Host smart-0a8570ea-567f-47fe-9dea-817812c85388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424341296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.2424341296
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.2123749026
Short name T456
Test name
Test status
Simulation time 598407167 ps
CPU time 13.21 seconds
Started Jul 07 07:00:53 PM PDT 24
Finished Jul 07 07:01:07 PM PDT 24
Peak memory 225588 kb
Host smart-f12cb9c3-0983-4d3a-8328-2247228b230d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123749026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.2123749026
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.935579529
Short name T315
Test name
Test status
Simulation time 1044356124 ps
CPU time 11.52 seconds
Started Jul 07 07:00:55 PM PDT 24
Finished Jul 07 07:01:06 PM PDT 24
Peak memory 225500 kb
Host smart-33fa458a-e00f-430d-856d-811f065e7061
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935579529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_di
gest.935579529
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.489249109
Short name T512
Test name
Test status
Simulation time 264961269 ps
CPU time 8.1 seconds
Started Jul 07 07:00:52 PM PDT 24
Finished Jul 07 07:01:00 PM PDT 24
Peak memory 217860 kb
Host smart-74fcee2b-39f2-45c4-9c8f-8aaeaa9d7a8f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489249109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.489249109
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.983952490
Short name T451
Test name
Test status
Simulation time 702723888 ps
CPU time 7.9 seconds
Started Jul 07 07:00:49 PM PDT 24
Finished Jul 07 07:00:57 PM PDT 24
Peak memory 225640 kb
Host smart-ac89f469-48e2-446c-bd0c-3fe77540a330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983952490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.983952490
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.2695258166
Short name T324
Test name
Test status
Simulation time 22457733 ps
CPU time 1.66 seconds
Started Jul 07 07:00:49 PM PDT 24
Finished Jul 07 07:00:51 PM PDT 24
Peak memory 213572 kb
Host smart-87466efa-7fca-475f-9df2-fc8d56274af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695258166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.2695258166
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.700261358
Short name T27
Test name
Test status
Simulation time 1680915899 ps
CPU time 22.12 seconds
Started Jul 07 07:00:46 PM PDT 24
Finished Jul 07 07:01:08 PM PDT 24
Peak memory 250616 kb
Host smart-23065cb5-6a44-4a79-b7fa-836a48ccee8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700261358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.700261358
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.1464101857
Short name T504
Test name
Test status
Simulation time 166990692 ps
CPU time 6.37 seconds
Started Jul 07 07:00:46 PM PDT 24
Finished Jul 07 07:00:52 PM PDT 24
Peak memory 250112 kb
Host smart-3aa51cae-ccec-4021-a8a5-8e72746af8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464101857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.1464101857
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.2298427406
Short name T308
Test name
Test status
Simulation time 23011908752 ps
CPU time 330.96 seconds
Started Jul 07 07:00:51 PM PDT 24
Finished Jul 07 07:06:22 PM PDT 24
Peak memory 283348 kb
Host smart-be687c43-5703-46b3-976c-b77fd8544799
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298427406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.2298427406
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.946866704
Short name T114
Test name
Test status
Simulation time 184795850701 ps
CPU time 1145.09 seconds
Started Jul 07 07:00:52 PM PDT 24
Finished Jul 07 07:19:57 PM PDT 24
Peak memory 421704 kb
Host smart-29a75b0a-be38-48f1-a5e6-ab7561632949
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=946866704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all_with_rand_reset.946866704
Directory /workspace/14.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.109352003
Short name T709
Test name
Test status
Simulation time 35704171 ps
CPU time 0.84 seconds
Started Jul 07 07:00:46 PM PDT 24
Finished Jul 07 07:00:47 PM PDT 24
Peak memory 208604 kb
Host smart-fd78fdf1-1c44-4821-8dfb-c2b20acfd106
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109352003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ct
rl_volatile_unlock_smoke.109352003
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.2112655784
Short name T481
Test name
Test status
Simulation time 20221921 ps
CPU time 1.18 seconds
Started Jul 07 07:00:58 PM PDT 24
Finished Jul 07 07:00:59 PM PDT 24
Peak memory 208604 kb
Host smart-0e11f51c-a43c-447f-902f-e2a342678b52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112655784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.2112655784
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.3634428611
Short name T610
Test name
Test status
Simulation time 647300343 ps
CPU time 15.63 seconds
Started Jul 07 07:00:54 PM PDT 24
Finished Jul 07 07:01:10 PM PDT 24
Peak memory 225560 kb
Host smart-8d9b48a4-bc3b-4071-913b-6bc8be27943a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634428611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.3634428611
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.1170160317
Short name T298
Test name
Test status
Simulation time 290975403 ps
CPU time 2.4 seconds
Started Jul 07 07:00:56 PM PDT 24
Finished Jul 07 07:00:59 PM PDT 24
Peak memory 217212 kb
Host smart-ece4d0aa-bbe9-4ff4-85af-a9093a40e4bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170160317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.1170160317
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.2767679575
Short name T858
Test name
Test status
Simulation time 1948728935 ps
CPU time 31.42 seconds
Started Jul 07 07:00:55 PM PDT 24
Finished Jul 07 07:01:27 PM PDT 24
Peak memory 217716 kb
Host smart-1bec75b2-634e-4b5b-aaf2-ef4d9e1022f0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767679575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.2767679575
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.31471729
Short name T223
Test name
Test status
Simulation time 696963639 ps
CPU time 10.04 seconds
Started Jul 07 07:00:55 PM PDT 24
Finished Jul 07 07:01:06 PM PDT 24
Peak memory 217692 kb
Host smart-3402d71c-5ce0-4af8-81ff-1c359505e458
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31471729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p
rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_
prog_failure.31471729
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.3269004283
Short name T381
Test name
Test status
Simulation time 374485143 ps
CPU time 9.46 seconds
Started Jul 07 07:00:51 PM PDT 24
Finished Jul 07 07:01:00 PM PDT 24
Peak memory 217104 kb
Host smart-6fc6de0f-5521-4c3f-8b30-7d3597c399f8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269004283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.3269004283
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.22283774
Short name T320
Test name
Test status
Simulation time 4254032833 ps
CPU time 52.2 seconds
Started Jul 07 07:00:54 PM PDT 24
Finished Jul 07 07:01:47 PM PDT 24
Peak memory 266912 kb
Host smart-88d00765-bb88-49a5-8bb4-874f86f63399
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22283774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag
_state_failure.22283774
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.1629695387
Short name T660
Test name
Test status
Simulation time 1968764976 ps
CPU time 12.25 seconds
Started Jul 07 07:00:58 PM PDT 24
Finished Jul 07 07:01:10 PM PDT 24
Peak memory 249928 kb
Host smart-71a82163-6f25-4c61-a024-a547f267773c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629695387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.1629695387
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.2640121629
Short name T570
Test name
Test status
Simulation time 60072975 ps
CPU time 3.19 seconds
Started Jul 07 07:00:56 PM PDT 24
Finished Jul 07 07:00:59 PM PDT 24
Peak memory 221828 kb
Host smart-9b8af3bc-a9cb-45f2-b2a4-a4a265bfc029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640121629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.2640121629
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.1938281294
Short name T757
Test name
Test status
Simulation time 763233095 ps
CPU time 13.27 seconds
Started Jul 07 07:00:57 PM PDT 24
Finished Jul 07 07:01:10 PM PDT 24
Peak memory 225600 kb
Host smart-df7705a1-88e2-4e7c-b6ee-1764fb5357f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938281294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.1938281294
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.372740854
Short name T420
Test name
Test status
Simulation time 257044524 ps
CPU time 10.66 seconds
Started Jul 07 07:00:55 PM PDT 24
Finished Jul 07 07:01:06 PM PDT 24
Peak memory 225496 kb
Host smart-70e373dc-7b4e-4555-9cb4-c06a0cc1d4f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372740854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_di
gest.372740854
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.2868831408
Short name T110
Test name
Test status
Simulation time 919710896 ps
CPU time 6.86 seconds
Started Jul 07 07:00:57 PM PDT 24
Finished Jul 07 07:01:04 PM PDT 24
Peak memory 225504 kb
Host smart-9df30cc6-81c5-4947-9823-44ea05bda5d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868831408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
2868831408
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.1992390093
Short name T64
Test name
Test status
Simulation time 700768763 ps
CPU time 9.13 seconds
Started Jul 07 07:00:54 PM PDT 24
Finished Jul 07 07:01:03 PM PDT 24
Peak memory 217840 kb
Host smart-cc553f16-dd21-4153-86b8-2cdd400e39d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992390093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.1992390093
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.793542210
Short name T91
Test name
Test status
Simulation time 24467127 ps
CPU time 0.99 seconds
Started Jul 07 07:00:53 PM PDT 24
Finished Jul 07 07:00:54 PM PDT 24
Peak memory 217200 kb
Host smart-bcbb83d9-0b1e-46e5-a01a-1f925e80e3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793542210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.793542210
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.3869134553
Short name T347
Test name
Test status
Simulation time 981635001 ps
CPU time 21.49 seconds
Started Jul 07 07:00:55 PM PDT 24
Finished Jul 07 07:01:17 PM PDT 24
Peak memory 250652 kb
Host smart-7dc0b3fe-e996-4327-aa2a-a2ce57fa9640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869134553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.3869134553
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.53676258
Short name T529
Test name
Test status
Simulation time 371714697 ps
CPU time 3.29 seconds
Started Jul 07 07:00:55 PM PDT 24
Finished Jul 07 07:00:58 PM PDT 24
Peak memory 222276 kb
Host smart-272aa2f7-e5c5-4d58-94a2-7a44a19d7036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53676258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.53676258
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.1684981203
Short name T807
Test name
Test status
Simulation time 2039992726 ps
CPU time 63.05 seconds
Started Jul 07 07:00:55 PM PDT 24
Finished Jul 07 07:01:59 PM PDT 24
Peak memory 278836 kb
Host smart-de25840a-cb6d-4b82-be26-aadce083b755
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684981203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.1684981203
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.1537943381
Short name T597
Test name
Test status
Simulation time 39552150 ps
CPU time 0.86 seconds
Started Jul 07 07:00:54 PM PDT 24
Finished Jul 07 07:00:55 PM PDT 24
Peak memory 208392 kb
Host smart-70d74120-089d-4e34-aaee-6c2573b9847c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537943381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.1537943381
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.3496916418
Short name T78
Test name
Test status
Simulation time 79667145 ps
CPU time 1.23 seconds
Started Jul 07 07:01:02 PM PDT 24
Finished Jul 07 07:01:04 PM PDT 24
Peak memory 208588 kb
Host smart-b85d8e1b-047a-46ea-9cbe-d2409c409dd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496916418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.3496916418
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.3375393489
Short name T65
Test name
Test status
Simulation time 228549865 ps
CPU time 9.34 seconds
Started Jul 07 07:01:02 PM PDT 24
Finished Jul 07 07:01:11 PM PDT 24
Peak memory 217800 kb
Host smart-0daf8e9c-3f15-41fe-b905-f82a70da0142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375393489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.3375393489
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.749755828
Short name T394
Test name
Test status
Simulation time 982123440 ps
CPU time 10.46 seconds
Started Jul 07 07:01:02 PM PDT 24
Finished Jul 07 07:01:13 PM PDT 24
Peak memory 217444 kb
Host smart-fe187125-d650-43ec-bdd9-517b7bb5b470
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749755828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.749755828
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.2700445712
Short name T316
Test name
Test status
Simulation time 1554569151 ps
CPU time 25.95 seconds
Started Jul 07 07:01:04 PM PDT 24
Finished Jul 07 07:01:30 PM PDT 24
Peak memory 217648 kb
Host smart-fd81be42-5ecd-4b67-a0e2-5be8cf337550
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700445712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.2700445712
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.2443208582
Short name T686
Test name
Test status
Simulation time 339107266 ps
CPU time 10.87 seconds
Started Jul 07 07:00:59 PM PDT 24
Finished Jul 07 07:01:10 PM PDT 24
Peak memory 217728 kb
Host smart-1d31649f-7c6d-4080-b6e6-8d4424ad8368
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443208582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.2443208582
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.662287487
Short name T576
Test name
Test status
Simulation time 6870607107 ps
CPU time 14.12 seconds
Started Jul 07 07:01:01 PM PDT 24
Finished Jul 07 07:01:16 PM PDT 24
Peak memory 217188 kb
Host smart-82afcd2f-7eb9-43c8-9c58-56b1b17a48a7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662287487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke.
662287487
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.2383462385
Short name T828
Test name
Test status
Simulation time 3108643178 ps
CPU time 34.57 seconds
Started Jul 07 07:01:01 PM PDT 24
Finished Jul 07 07:01:36 PM PDT 24
Peak memory 268840 kb
Host smart-3e7b6f17-715e-494f-ad28-60d6d5c8e897
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383462385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.2383462385
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.3106372837
Short name T256
Test name
Test status
Simulation time 260844380 ps
CPU time 10.33 seconds
Started Jul 07 07:01:01 PM PDT 24
Finished Jul 07 07:01:12 PM PDT 24
Peak memory 250704 kb
Host smart-51f716cd-0d95-4a12-a3f3-68bb89af4ee8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106372837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.3106372837
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.1199489778
Short name T734
Test name
Test status
Simulation time 286241757 ps
CPU time 3.07 seconds
Started Jul 07 07:01:00 PM PDT 24
Finished Jul 07 07:01:04 PM PDT 24
Peak memory 217836 kb
Host smart-98f4748c-bf14-485b-b996-9ee3a71ca217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199489778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.1199489778
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.19391716
Short name T636
Test name
Test status
Simulation time 165707067 ps
CPU time 9.64 seconds
Started Jul 07 07:01:04 PM PDT 24
Finished Jul 07 07:01:14 PM PDT 24
Peak memory 217756 kb
Host smart-148f67fb-095d-46c0-a7ad-2c04bac4f771
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19391716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.19391716
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.1239704339
Short name T705
Test name
Test status
Simulation time 437275901 ps
CPU time 12.51 seconds
Started Jul 07 07:01:02 PM PDT 24
Finished Jul 07 07:01:15 PM PDT 24
Peak memory 225524 kb
Host smart-15c6dbb4-2f6b-41b1-b9ff-0b56ce1f619a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239704339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.1239704339
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.2978524813
Short name T360
Test name
Test status
Simulation time 1048788127 ps
CPU time 11.93 seconds
Started Jul 07 07:01:03 PM PDT 24
Finished Jul 07 07:01:15 PM PDT 24
Peak memory 225532 kb
Host smart-e5dd036c-7d58-4904-a41d-18da0232a84b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978524813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
2978524813
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.4230632870
Short name T305
Test name
Test status
Simulation time 764394620 ps
CPU time 10.5 seconds
Started Jul 07 07:01:00 PM PDT 24
Finished Jul 07 07:01:10 PM PDT 24
Peak memory 225596 kb
Host smart-2e1bf426-1a01-400b-af5f-3c8fe7c65549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230632870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.4230632870
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.700800369
Short name T396
Test name
Test status
Simulation time 24789778 ps
CPU time 1.79 seconds
Started Jul 07 07:00:59 PM PDT 24
Finished Jul 07 07:01:01 PM PDT 24
Peak memory 213672 kb
Host smart-fc5bd779-d114-4bb2-9bea-61dad33c2677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700800369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.700800369
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.3590631249
Short name T354
Test name
Test status
Simulation time 1908230877 ps
CPU time 22.64 seconds
Started Jul 07 07:01:00 PM PDT 24
Finished Jul 07 07:01:23 PM PDT 24
Peak memory 250452 kb
Host smart-28155528-15d7-47e9-87aa-dd58c3de0342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590631249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.3590631249
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.1648494525
Short name T300
Test name
Test status
Simulation time 323652924 ps
CPU time 3.59 seconds
Started Jul 07 07:00:59 PM PDT 24
Finished Jul 07 07:01:03 PM PDT 24
Peak memory 221920 kb
Host smart-84950e5f-b128-4c1f-b206-0da9aee87aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648494525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.1648494525
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.1395273899
Short name T765
Test name
Test status
Simulation time 14751366121 ps
CPU time 448.66 seconds
Started Jul 07 07:01:05 PM PDT 24
Finished Jul 07 07:08:34 PM PDT 24
Peak memory 252800 kb
Host smart-102432d0-1ce8-40b9-ae69-3e4a42f773c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395273899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.1395273899
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.3431977434
Short name T252
Test name
Test status
Simulation time 13862262 ps
CPU time 1 seconds
Started Jul 07 07:01:02 PM PDT 24
Finished Jul 07 07:01:03 PM PDT 24
Peak memory 208476 kb
Host smart-3c9171f0-0039-4c4c-8a09-2fbfc1a413dc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431977434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.3431977434
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.3337481822
Short name T754
Test name
Test status
Simulation time 30620542 ps
CPU time 0.88 seconds
Started Jul 07 07:01:12 PM PDT 24
Finished Jul 07 07:01:13 PM PDT 24
Peak memory 208444 kb
Host smart-bb1a6eda-e20e-4eb8-a264-991c2dd70f64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337481822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.3337481822
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.1968708442
Short name T759
Test name
Test status
Simulation time 1559986386 ps
CPU time 16.13 seconds
Started Jul 07 07:01:05 PM PDT 24
Finished Jul 07 07:01:21 PM PDT 24
Peak memory 217736 kb
Host smart-5a421ec8-d8b7-4ae6-baba-bc6043d8d0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968708442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.1968708442
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.1420808230
Short name T25
Test name
Test status
Simulation time 3423144425 ps
CPU time 5.8 seconds
Started Jul 07 07:01:08 PM PDT 24
Finished Jul 07 07:01:14 PM PDT 24
Peak memory 217172 kb
Host smart-abb4b4e5-1489-4789-a5fa-583036355f44
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420808230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.1420808230
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.875816365
Short name T404
Test name
Test status
Simulation time 1750610829 ps
CPU time 53.41 seconds
Started Jul 07 07:01:05 PM PDT 24
Finished Jul 07 07:01:59 PM PDT 24
Peak memory 217796 kb
Host smart-6fda997f-6a39-4a47-9035-c370ceab2145
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875816365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_er
rors.875816365
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.3700808252
Short name T348
Test name
Test status
Simulation time 298659078 ps
CPU time 5.75 seconds
Started Jul 07 07:01:06 PM PDT 24
Finished Jul 07 07:01:12 PM PDT 24
Peak memory 217996 kb
Host smart-899e51e5-83bc-430c-af5c-76e9738056af
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700808252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.3700808252
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.957388682
Short name T484
Test name
Test status
Simulation time 620654158 ps
CPU time 6.34 seconds
Started Jul 07 07:01:09 PM PDT 24
Finished Jul 07 07:01:16 PM PDT 24
Peak memory 217140 kb
Host smart-edadba09-fbf0-44fe-a880-47d16f4a457c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957388682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke.
957388682
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.3340761788
Short name T249
Test name
Test status
Simulation time 1596685528 ps
CPU time 61.04 seconds
Started Jul 07 07:01:05 PM PDT 24
Finished Jul 07 07:02:07 PM PDT 24
Peak memory 275476 kb
Host smart-3bd33740-945c-48ad-bbc4-d278b674c352
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340761788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.3340761788
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.2996237779
Short name T568
Test name
Test status
Simulation time 1637102757 ps
CPU time 22.1 seconds
Started Jul 07 07:01:08 PM PDT 24
Finished Jul 07 07:01:30 PM PDT 24
Peak memory 225856 kb
Host smart-9c49d903-87e5-4357-ab0a-cba23685a1dd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996237779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.2996237779
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.2397667301
Short name T820
Test name
Test status
Simulation time 172340148 ps
CPU time 3.17 seconds
Started Jul 07 07:01:06 PM PDT 24
Finished Jul 07 07:01:09 PM PDT 24
Peak memory 217788 kb
Host smart-5f175ece-3753-444d-a53b-2d779eaf7faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397667301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.2397667301
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.4189869015
Short name T531
Test name
Test status
Simulation time 1440725117 ps
CPU time 16.8 seconds
Started Jul 07 07:01:13 PM PDT 24
Finished Jul 07 07:01:30 PM PDT 24
Peak memory 225572 kb
Host smart-98874559-bba2-4c45-9b56-0fc7b31316bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189869015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.4189869015
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.509683749
Short name T478
Test name
Test status
Simulation time 1388601914 ps
CPU time 10.69 seconds
Started Jul 07 07:01:10 PM PDT 24
Finished Jul 07 07:01:21 PM PDT 24
Peak memory 225512 kb
Host smart-5e6d0db1-fdbb-4bdf-bf7f-dfd1d8abbb50
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509683749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_di
gest.509683749
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.3931053260
Short name T723
Test name
Test status
Simulation time 1011311278 ps
CPU time 12.38 seconds
Started Jul 07 07:01:10 PM PDT 24
Finished Jul 07 07:01:22 PM PDT 24
Peak memory 217728 kb
Host smart-d9b0d160-cbac-497f-8216-27c36f625734
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931053260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
3931053260
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.856436226
Short name T321
Test name
Test status
Simulation time 416899190 ps
CPU time 3.35 seconds
Started Jul 07 07:01:03 PM PDT 24
Finished Jul 07 07:01:07 PM PDT 24
Peak memory 217564 kb
Host smart-967c8e2b-4e9b-49d8-977d-038a7cb214de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856436226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.856436226
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.1657727157
Short name T13
Test name
Test status
Simulation time 529309045 ps
CPU time 27.25 seconds
Started Jul 07 07:01:05 PM PDT 24
Finished Jul 07 07:01:32 PM PDT 24
Peak memory 250540 kb
Host smart-5903774f-4036-476c-8ffa-d58803eb14ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657727157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.1657727157
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.2890978916
Short name T262
Test name
Test status
Simulation time 64168514 ps
CPU time 3 seconds
Started Jul 07 07:01:07 PM PDT 24
Finished Jul 07 07:01:10 PM PDT 24
Peak memory 222340 kb
Host smart-4033f9e4-5a67-4d77-b1ad-d05ceca13379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890978916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.2890978916
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.51838453
Short name T674
Test name
Test status
Simulation time 915812358 ps
CPU time 21.12 seconds
Started Jul 07 07:01:11 PM PDT 24
Finished Jul 07 07:01:33 PM PDT 24
Peak memory 217460 kb
Host smart-c61d80eb-7002-4704-a83e-a1edfe621dad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51838453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.lc_ctrl_stress_all.51838453
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.2815818402
Short name T208
Test name
Test status
Simulation time 41802056 ps
CPU time 0.86 seconds
Started Jul 07 07:01:03 PM PDT 24
Finished Jul 07 07:01:04 PM PDT 24
Peak memory 208616 kb
Host smart-a05b037b-a6ea-4bbc-bd79-970c39384847
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815818402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.2815818402
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.3338302657
Short name T428
Test name
Test status
Simulation time 19261353 ps
CPU time 0.89 seconds
Started Jul 07 07:01:18 PM PDT 24
Finished Jul 07 07:01:19 PM PDT 24
Peak memory 208388 kb
Host smart-a2c8d964-ab91-41db-ac64-be22274d0db8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338302657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.3338302657
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.2428494994
Short name T50
Test name
Test status
Simulation time 3427948416 ps
CPU time 20.95 seconds
Started Jul 07 07:01:17 PM PDT 24
Finished Jul 07 07:01:39 PM PDT 24
Peak memory 225576 kb
Host smart-1b5a3d1c-464b-4c69-9f05-a917810b25da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428494994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.2428494994
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.4171120538
Short name T857
Test name
Test status
Simulation time 491856243 ps
CPU time 3.94 seconds
Started Jul 07 07:01:16 PM PDT 24
Finished Jul 07 07:01:20 PM PDT 24
Peak memory 217244 kb
Host smart-d4c61633-27ab-4d3c-b8e9-c9a732a74f40
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171120538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.4171120538
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.2485035314
Short name T92
Test name
Test status
Simulation time 5220218312 ps
CPU time 60.76 seconds
Started Jul 07 07:01:11 PM PDT 24
Finished Jul 07 07:02:12 PM PDT 24
Peak memory 219448 kb
Host smart-e1320a6c-232b-449c-9f36-f55ad934305a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485035314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.2485035314
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.585840668
Short name T517
Test name
Test status
Simulation time 797116386 ps
CPU time 12.43 seconds
Started Jul 07 07:01:13 PM PDT 24
Finished Jul 07 07:01:26 PM PDT 24
Peak memory 217716 kb
Host smart-2f0e47fa-ef54-4bce-b30a-650b4330dbeb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585840668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag
_prog_failure.585840668
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.2466793418
Short name T259
Test name
Test status
Simulation time 758415598 ps
CPU time 9.94 seconds
Started Jul 07 07:01:12 PM PDT 24
Finished Jul 07 07:01:22 PM PDT 24
Peak memory 217124 kb
Host smart-b6d4c72d-b735-4579-80cd-f8b174551857
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466793418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.2466793418
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.1694321736
Short name T852
Test name
Test status
Simulation time 1015840490 ps
CPU time 31.5 seconds
Started Jul 07 07:01:15 PM PDT 24
Finished Jul 07 07:01:47 PM PDT 24
Peak memory 250480 kb
Host smart-c1fb3bc1-bb54-4300-a51b-3b09bdb0690e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694321736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.1694321736
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.1520671918
Short name T225
Test name
Test status
Simulation time 942150503 ps
CPU time 23.41 seconds
Started Jul 07 07:01:12 PM PDT 24
Finished Jul 07 07:01:36 PM PDT 24
Peak memory 250276 kb
Host smart-fb7bc78d-befb-4639-9d1a-c814b9c771fd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520671918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.1520671918
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.246796448
Short name T813
Test name
Test status
Simulation time 586096099 ps
CPU time 2.8 seconds
Started Jul 07 07:01:16 PM PDT 24
Finished Jul 07 07:01:19 PM PDT 24
Peak memory 221848 kb
Host smart-f45045cc-2230-4371-a823-2b3704c1bdd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246796448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.246796448
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.1452881335
Short name T522
Test name
Test status
Simulation time 791667124 ps
CPU time 21.7 seconds
Started Jul 07 07:01:13 PM PDT 24
Finished Jul 07 07:01:35 PM PDT 24
Peak memory 225576 kb
Host smart-6fb5a1d1-4b1d-40a2-b82f-c72f6f8f9b56
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452881335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.1452881335
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.938773700
Short name T805
Test name
Test status
Simulation time 1015330716 ps
CPU time 14.84 seconds
Started Jul 07 07:01:18 PM PDT 24
Finished Jul 07 07:01:33 PM PDT 24
Peak memory 225480 kb
Host smart-07ab231b-7c35-4e32-a5e7-cc3730709ab6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938773700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_di
gest.938773700
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.487627937
Short name T780
Test name
Test status
Simulation time 457604611 ps
CPU time 9.95 seconds
Started Jul 07 07:01:19 PM PDT 24
Finished Jul 07 07:01:29 PM PDT 24
Peak memory 225556 kb
Host smart-518f64a6-ebd0-4859-a745-c0243206d90c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487627937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.487627937
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.4284615004
Short name T530
Test name
Test status
Simulation time 273433452 ps
CPU time 8.04 seconds
Started Jul 07 07:01:16 PM PDT 24
Finished Jul 07 07:01:24 PM PDT 24
Peak memory 224612 kb
Host smart-8dbcaeb3-a580-4886-85b9-fd4788d68cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284615004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.4284615004
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.148247481
Short name T831
Test name
Test status
Simulation time 24717809 ps
CPU time 1.49 seconds
Started Jul 07 07:01:09 PM PDT 24
Finished Jul 07 07:01:10 PM PDT 24
Peak memory 217200 kb
Host smart-1aea8251-05e1-4cd9-9ec4-65f44e7f74b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148247481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.148247481
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.1151589087
Short name T577
Test name
Test status
Simulation time 555337543 ps
CPU time 33.92 seconds
Started Jul 07 07:01:12 PM PDT 24
Finished Jul 07 07:01:46 PM PDT 24
Peak memory 250560 kb
Host smart-8a3e4090-6c0d-48bf-a885-c28ea0114207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151589087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.1151589087
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.1158347377
Short name T329
Test name
Test status
Simulation time 62215880 ps
CPU time 7.61 seconds
Started Jul 07 07:01:14 PM PDT 24
Finished Jul 07 07:01:22 PM PDT 24
Peak memory 250548 kb
Host smart-e0822d4d-b712-42d1-a2c5-2cbf85c2f822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158347377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.1158347377
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.2587853426
Short name T414
Test name
Test status
Simulation time 86255915954 ps
CPU time 769.71 seconds
Started Jul 07 07:01:17 PM PDT 24
Finished Jul 07 07:14:07 PM PDT 24
Peak memory 275624 kb
Host smart-cb91ba1f-6051-40fe-ad3e-98cfa3a09e8b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587853426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.2587853426
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.2325980162
Short name T444
Test name
Test status
Simulation time 290838331 ps
CPU time 0.96 seconds
Started Jul 07 07:01:10 PM PDT 24
Finished Jul 07 07:01:11 PM PDT 24
Peak memory 212404 kb
Host smart-2e5d1da5-9c8d-4f40-b68d-2fa4dbd44791
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325980162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.2325980162
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.443349457
Short name T487
Test name
Test status
Simulation time 77417196 ps
CPU time 0.92 seconds
Started Jul 07 07:01:29 PM PDT 24
Finished Jul 07 07:01:30 PM PDT 24
Peak memory 208520 kb
Host smart-323b06c1-ced9-421b-8302-b3dc65cbd77e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443349457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.443349457
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.1913056242
Short name T697
Test name
Test status
Simulation time 918687537 ps
CPU time 9.52 seconds
Started Jul 07 07:01:17 PM PDT 24
Finished Jul 07 07:01:27 PM PDT 24
Peak memory 225504 kb
Host smart-d70e8cbb-01d5-431d-bd22-238dc205f7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913056242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.1913056242
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.3022447326
Short name T591
Test name
Test status
Simulation time 343910910 ps
CPU time 5.27 seconds
Started Jul 07 07:01:20 PM PDT 24
Finished Jul 07 07:01:25 PM PDT 24
Peak memory 217032 kb
Host smart-adef8c07-6bb0-4163-b0a7-ee501406ba05
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022447326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.3022447326
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.2906432094
Short name T328
Test name
Test status
Simulation time 5910649963 ps
CPU time 35.95 seconds
Started Jul 07 07:01:22 PM PDT 24
Finished Jul 07 07:01:58 PM PDT 24
Peak memory 218320 kb
Host smart-f23e6cdf-d839-4551-a047-df20d93ad83a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906432094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.2906432094
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.2691361379
Short name T234
Test name
Test status
Simulation time 1435994645 ps
CPU time 4.95 seconds
Started Jul 07 07:01:20 PM PDT 24
Finished Jul 07 07:01:25 PM PDT 24
Peak memory 222532 kb
Host smart-e4294f56-b489-4010-aeaf-e72c253163dc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691361379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.2691361379
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.3404874325
Short name T419
Test name
Test status
Simulation time 574060006 ps
CPU time 8.36 seconds
Started Jul 07 07:01:17 PM PDT 24
Finished Jul 07 07:01:26 PM PDT 24
Peak memory 217104 kb
Host smart-15c6d1ca-2e3b-4fda-8767-65b092a77acd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404874325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.3404874325
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.3001917152
Short name T802
Test name
Test status
Simulation time 12387685331 ps
CPU time 51.7 seconds
Started Jul 07 07:01:20 PM PDT 24
Finished Jul 07 07:02:12 PM PDT 24
Peak memory 283228 kb
Host smart-76861a01-09b3-4c8a-abcc-abdf1eea9ba3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001917152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.3001917152
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.4036526787
Short name T648
Test name
Test status
Simulation time 417948854 ps
CPU time 17.22 seconds
Started Jul 07 07:01:21 PM PDT 24
Finished Jul 07 07:01:38 PM PDT 24
Peak memory 247368 kb
Host smart-2705a0db-35df-448d-b485-572bdf89770b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036526787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.4036526787
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.4010900920
Short name T834
Test name
Test status
Simulation time 193073402 ps
CPU time 2.24 seconds
Started Jul 07 07:01:17 PM PDT 24
Finished Jul 07 07:01:19 PM PDT 24
Peak memory 217796 kb
Host smart-1326ecc8-ea10-4a51-aafa-ed0acd6f9d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010900920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.4010900920
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.2161946664
Short name T350
Test name
Test status
Simulation time 501053256 ps
CPU time 8.27 seconds
Started Jul 07 07:01:20 PM PDT 24
Finished Jul 07 07:01:29 PM PDT 24
Peak memory 225508 kb
Host smart-babb47e5-39d1-4035-8c56-eb951198305f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161946664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.2161946664
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.636003674
Short name T542
Test name
Test status
Simulation time 280255985 ps
CPU time 11.05 seconds
Started Jul 07 07:01:20 PM PDT 24
Finished Jul 07 07:01:32 PM PDT 24
Peak memory 217720 kb
Host smart-e99ab9ad-d731-4efa-a8bf-0e91ed3d09cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636003674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.636003674
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.1518748353
Short name T492
Test name
Test status
Simulation time 949859105 ps
CPU time 10.98 seconds
Started Jul 07 07:01:17 PM PDT 24
Finished Jul 07 07:01:28 PM PDT 24
Peak memory 225592 kb
Host smart-6f2a793d-e039-47a0-b80a-4308361a6710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518748353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.1518748353
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.2418173713
Short name T81
Test name
Test status
Simulation time 50311790 ps
CPU time 1.68 seconds
Started Jul 07 07:01:16 PM PDT 24
Finished Jul 07 07:01:18 PM PDT 24
Peak memory 217196 kb
Host smart-b2134fd9-d04a-4831-b6be-2bbee0acf1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418173713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.2418173713
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.376022007
Short name T240
Test name
Test status
Simulation time 198578923 ps
CPU time 18.07 seconds
Started Jul 07 07:01:18 PM PDT 24
Finished Jul 07 07:01:36 PM PDT 24
Peak memory 250608 kb
Host smart-cf3a9871-f951-47b6-a7cb-4e79e9064c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376022007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.376022007
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.2673113752
Short name T289
Test name
Test status
Simulation time 72292840 ps
CPU time 3.97 seconds
Started Jul 07 07:01:16 PM PDT 24
Finished Jul 07 07:01:20 PM PDT 24
Peak memory 222128 kb
Host smart-60545292-f369-4806-8d38-196dc9863a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673113752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.2673113752
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.2499623967
Short name T682
Test name
Test status
Simulation time 4055931753 ps
CPU time 87.46 seconds
Started Jul 07 07:01:20 PM PDT 24
Finished Jul 07 07:02:48 PM PDT 24
Peak memory 250528 kb
Host smart-b3d39567-56a8-4d75-b8e8-7fb4f36e69dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499623967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.2499623967
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.1639735190
Short name T304
Test name
Test status
Simulation time 15983274 ps
CPU time 1.23 seconds
Started Jul 07 07:01:17 PM PDT 24
Finished Jul 07 07:01:18 PM PDT 24
Peak memory 217208 kb
Host smart-83bccd28-9b68-435a-8193-818155055638
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639735190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.1639735190
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.1268167693
Short name T33
Test name
Test status
Simulation time 62050469 ps
CPU time 1.09 seconds
Started Jul 07 06:59:26 PM PDT 24
Finished Jul 07 06:59:28 PM PDT 24
Peak memory 208612 kb
Host smart-37dc0bc1-0a87-4e58-9c7f-f80d0f9cafd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268167693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.1268167693
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.1470843665
Short name T545
Test name
Test status
Simulation time 34833912 ps
CPU time 0.83 seconds
Started Jul 07 06:59:24 PM PDT 24
Finished Jul 07 06:59:25 PM PDT 24
Peak memory 208324 kb
Host smart-a4d2ebb8-94c6-4a3b-9368-5efb578ba318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470843665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.1470843665
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.460590464
Short name T196
Test name
Test status
Simulation time 180785525 ps
CPU time 8.44 seconds
Started Jul 07 06:59:22 PM PDT 24
Finished Jul 07 06:59:31 PM PDT 24
Peak memory 225600 kb
Host smart-20ac68d9-9f39-4626-85a2-04057e69124f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460590464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.460590464
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.2247223825
Short name T445
Test name
Test status
Simulation time 658792574 ps
CPU time 4.78 seconds
Started Jul 07 06:59:22 PM PDT 24
Finished Jul 07 06:59:27 PM PDT 24
Peak memory 216728 kb
Host smart-2d668058-ea34-4f87-9bec-8b18f8dbaf20
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247223825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.2247223825
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.371061840
Short name T337
Test name
Test status
Simulation time 26646204864 ps
CPU time 59.23 seconds
Started Jul 07 06:59:19 PM PDT 24
Finished Jul 07 07:00:18 PM PDT 24
Peak memory 218100 kb
Host smart-e914fa95-912b-4fab-8305-8a19c86923af
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371061840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_err
ors.371061840
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.1003460801
Short name T380
Test name
Test status
Simulation time 1315178748 ps
CPU time 13.96 seconds
Started Jul 07 06:59:21 PM PDT 24
Finished Jul 07 06:59:35 PM PDT 24
Peak memory 217280 kb
Host smart-ad2a0805-e7df-4285-a0b7-5c003f6b51dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003460801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.1
003460801
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.89753776
Short name T418
Test name
Test status
Simulation time 290698840 ps
CPU time 9.4 seconds
Started Jul 07 06:59:21 PM PDT 24
Finished Jul 07 06:59:30 PM PDT 24
Peak memory 222680 kb
Host smart-598fe891-6949-401c-b60c-1390c4523868
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89753776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p
rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_p
rog_failure.89753776
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.3687204814
Short name T365
Test name
Test status
Simulation time 873930342 ps
CPU time 13.09 seconds
Started Jul 07 06:59:24 PM PDT 24
Finished Jul 07 06:59:37 PM PDT 24
Peak memory 217144 kb
Host smart-04d2931b-2f85-4d68-94ea-22e1a6e03d75
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687204814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.3687204814
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.2428657804
Short name T370
Test name
Test status
Simulation time 2655915453 ps
CPU time 5.08 seconds
Started Jul 07 06:59:20 PM PDT 24
Finished Jul 07 06:59:25 PM PDT 24
Peak memory 217112 kb
Host smart-5da0ccec-5887-4423-838b-fee6c9155cda
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428657804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
2428657804
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.2957532214
Short name T748
Test name
Test status
Simulation time 10695145248 ps
CPU time 46.89 seconds
Started Jul 07 06:59:24 PM PDT 24
Finished Jul 07 07:00:11 PM PDT 24
Peak memory 266752 kb
Host smart-7345bbb3-5f83-41fb-bbe1-0426fd4cd15d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957532214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.2957532214
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.2136307485
Short name T799
Test name
Test status
Simulation time 6075306804 ps
CPU time 15.64 seconds
Started Jul 07 06:59:21 PM PDT 24
Finished Jul 07 06:59:37 PM PDT 24
Peak memory 249960 kb
Host smart-1bef4741-e5bb-4293-ac90-f4c22056142f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136307485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.2136307485
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.1413140119
Short name T109
Test name
Test status
Simulation time 53241668 ps
CPU time 2.84 seconds
Started Jul 07 06:59:17 PM PDT 24
Finished Jul 07 06:59:20 PM PDT 24
Peak memory 221800 kb
Host smart-632465ff-0416-458e-a0fe-466d9e62f0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413140119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.1413140119
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.2055239997
Short name T687
Test name
Test status
Simulation time 349915208 ps
CPU time 12.39 seconds
Started Jul 07 06:59:22 PM PDT 24
Finished Jul 07 06:59:34 PM PDT 24
Peak memory 217212 kb
Host smart-1fab1fd5-06f6-469b-b2f6-c67d681253f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055239997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.2055239997
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.1354174974
Short name T105
Test name
Test status
Simulation time 1111372565 ps
CPU time 37.39 seconds
Started Jul 07 06:59:28 PM PDT 24
Finished Jul 07 07:00:05 PM PDT 24
Peak memory 265836 kb
Host smart-74c31749-2f14-4ced-9f5e-680265da2f7e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354174974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.1354174974
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.4197188428
Short name T742
Test name
Test status
Simulation time 406738705 ps
CPU time 14.76 seconds
Started Jul 07 06:59:23 PM PDT 24
Finished Jul 07 06:59:38 PM PDT 24
Peak memory 218412 kb
Host smart-9472d416-168c-497b-88cc-31d02527bab4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197188428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.4197188428
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.3416262630
Short name T859
Test name
Test status
Simulation time 289549894 ps
CPU time 12.96 seconds
Started Jul 07 06:59:23 PM PDT 24
Finished Jul 07 06:59:36 PM PDT 24
Peak memory 225760 kb
Host smart-490e244a-b883-4bcb-ae89-f2eba5de1d5d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416262630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.3416262630
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.911243159
Short name T258
Test name
Test status
Simulation time 411095592 ps
CPU time 5.87 seconds
Started Jul 07 06:59:26 PM PDT 24
Finished Jul 07 06:59:33 PM PDT 24
Peak memory 217724 kb
Host smart-0cfd0489-1e52-47d8-aaea-72d5b94861b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911243159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.911243159
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.4256356773
Short name T728
Test name
Test status
Simulation time 2150427455 ps
CPU time 8.19 seconds
Started Jul 07 06:59:19 PM PDT 24
Finished Jul 07 06:59:28 PM PDT 24
Peak memory 217892 kb
Host smart-acf6da4b-93b6-47f6-a886-5efaa3580eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256356773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.4256356773
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.2109748225
Short name T393
Test name
Test status
Simulation time 305578940 ps
CPU time 2.65 seconds
Started Jul 07 06:59:16 PM PDT 24
Finished Jul 07 06:59:19 PM PDT 24
Peak memory 222876 kb
Host smart-16ac477e-d2ad-4aed-a3b3-749fbcd862cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109748225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.2109748225
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.2285532983
Short name T382
Test name
Test status
Simulation time 793304709 ps
CPU time 17.88 seconds
Started Jul 07 06:59:16 PM PDT 24
Finished Jul 07 06:59:34 PM PDT 24
Peak memory 250496 kb
Host smart-7ba2366b-c17f-40a8-97c1-3e6af3c84702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285532983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.2285532983
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.2888841531
Short name T675
Test name
Test status
Simulation time 73580191 ps
CPU time 7.52 seconds
Started Jul 07 06:59:16 PM PDT 24
Finished Jul 07 06:59:23 PM PDT 24
Peak memory 250776 kb
Host smart-0fe16b90-2b22-4ce2-a117-df47dae69703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888841531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.2888841531
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.1567562571
Short name T379
Test name
Test status
Simulation time 64115039782 ps
CPU time 277.95 seconds
Started Jul 07 06:59:25 PM PDT 24
Finished Jul 07 07:04:03 PM PDT 24
Peak memory 272600 kb
Host smart-d72f69d2-1094-4d18-b6f1-145bc89183d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567562571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.1567562571
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.1933141318
Short name T209
Test name
Test status
Simulation time 18430338 ps
CPU time 0.9 seconds
Started Jul 07 06:59:17 PM PDT 24
Finished Jul 07 06:59:18 PM PDT 24
Peak memory 208424 kb
Host smart-a382fa03-e3ab-45a4-bb28-6f9e78527d98
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933141318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.1933141318
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.2547582315
Short name T650
Test name
Test status
Simulation time 17072418 ps
CPU time 1.08 seconds
Started Jul 07 07:01:24 PM PDT 24
Finished Jul 07 07:01:25 PM PDT 24
Peak memory 208544 kb
Host smart-927a516d-461f-4a8e-9e28-938c31c2343d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547582315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.2547582315
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.3406240465
Short name T488
Test name
Test status
Simulation time 6719793480 ps
CPU time 10.79 seconds
Started Jul 07 07:01:25 PM PDT 24
Finished Jul 07 07:01:37 PM PDT 24
Peak memory 217852 kb
Host smart-a25c642c-0538-433c-a77f-a7453f48c41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406240465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.3406240465
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.2058819851
Short name T581
Test name
Test status
Simulation time 658495196 ps
CPU time 8.65 seconds
Started Jul 07 07:01:25 PM PDT 24
Finished Jul 07 07:01:34 PM PDT 24
Peak memory 216680 kb
Host smart-a45ca5ff-4479-48d4-b76b-ce0e467a1d03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058819851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.2058819851
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.2765887010
Short name T440
Test name
Test status
Simulation time 19710034 ps
CPU time 1.49 seconds
Started Jul 07 07:01:25 PM PDT 24
Finished Jul 07 07:01:27 PM PDT 24
Peak memory 217788 kb
Host smart-76350a30-a000-4f04-a906-1894749d9766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765887010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.2765887010
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.2474772227
Short name T72
Test name
Test status
Simulation time 1018244734 ps
CPU time 11.07 seconds
Started Jul 07 07:01:25 PM PDT 24
Finished Jul 07 07:01:37 PM PDT 24
Peak memory 225576 kb
Host smart-2709b7be-0342-4024-aafb-6ecdc01dcabe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474772227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.2474772227
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.7545010
Short name T107
Test name
Test status
Simulation time 1054903737 ps
CPU time 11.44 seconds
Started Jul 07 07:01:25 PM PDT 24
Finished Jul 07 07:01:37 PM PDT 24
Peak memory 225508 kb
Host smart-7abf710d-1423-4b8d-839d-a2b473d3fe73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7545010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dige
st_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_dige
st.7545010
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.474224568
Short name T108
Test name
Test status
Simulation time 273842651 ps
CPU time 11.01 seconds
Started Jul 07 07:01:23 PM PDT 24
Finished Jul 07 07:01:35 PM PDT 24
Peak memory 217756 kb
Host smart-88f0e07a-e9ea-4f27-81e1-b003ab73f6a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474224568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.474224568
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.3722565873
Short name T493
Test name
Test status
Simulation time 301076073 ps
CPU time 8.91 seconds
Started Jul 07 07:01:24 PM PDT 24
Finished Jul 07 07:01:33 PM PDT 24
Peak memory 225564 kb
Host smart-cbfc6baf-7617-404c-ba06-6d3e964e1c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722565873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.3722565873
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.3620873765
Short name T84
Test name
Test status
Simulation time 196783675 ps
CPU time 4.75 seconds
Started Jul 07 07:01:25 PM PDT 24
Finished Jul 07 07:01:29 PM PDT 24
Peak memory 214476 kb
Host smart-0340de8c-af11-462e-9905-d7823de0964f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620873765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.3620873765
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.3628623232
Short name T482
Test name
Test status
Simulation time 1276876875 ps
CPU time 36.9 seconds
Started Jul 07 07:01:25 PM PDT 24
Finished Jul 07 07:02:02 PM PDT 24
Peak memory 250544 kb
Host smart-5c968205-e72e-40b5-a8ae-d899dc39814e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628623232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.3628623232
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.3875004744
Short name T224
Test name
Test status
Simulation time 86294706 ps
CPU time 7.62 seconds
Started Jul 07 07:01:25 PM PDT 24
Finished Jul 07 07:01:34 PM PDT 24
Peak memory 250072 kb
Host smart-d29def24-0795-44f5-af48-932d408d1b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875004744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.3875004744
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.60673063
Short name T547
Test name
Test status
Simulation time 8563075516 ps
CPU time 48.87 seconds
Started Jul 07 07:01:24 PM PDT 24
Finished Jul 07 07:02:13 PM PDT 24
Peak memory 266984 kb
Host smart-311c4cbc-2e46-4459-b551-8482646fb79a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60673063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.lc_ctrl_stress_all.60673063
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.834757920
Short name T165
Test name
Test status
Simulation time 32594973343 ps
CPU time 558.25 seconds
Started Jul 07 07:01:24 PM PDT 24
Finished Jul 07 07:10:42 PM PDT 24
Peak memory 321812 kb
Host smart-89f18786-07ce-4f3e-9233-05b9b1e038d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=834757920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all_with_rand_reset.834757920
Directory /workspace/20.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.3617071875
Short name T552
Test name
Test status
Simulation time 14843579 ps
CPU time 0.76 seconds
Started Jul 07 07:01:24 PM PDT 24
Finished Jul 07 07:01:25 PM PDT 24
Peak memory 208548 kb
Host smart-96333d0b-4dc0-4e18-af8c-604021a796b8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617071875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.3617071875
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.1120262797
Short name T278
Test name
Test status
Simulation time 68232850 ps
CPU time 1.09 seconds
Started Jul 07 07:01:33 PM PDT 24
Finished Jul 07 07:01:35 PM PDT 24
Peak memory 208564 kb
Host smart-218ebe13-de82-4278-aea6-e69c74f569cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120262797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.1120262797
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.1672579576
Short name T786
Test name
Test status
Simulation time 1608735502 ps
CPU time 18.83 seconds
Started Jul 07 07:01:27 PM PDT 24
Finished Jul 07 07:01:46 PM PDT 24
Peak memory 217780 kb
Host smart-06560bec-0b6a-4242-9af6-50226d2acd37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672579576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.1672579576
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.2088510294
Short name T804
Test name
Test status
Simulation time 2268843625 ps
CPU time 5.83 seconds
Started Jul 07 07:01:28 PM PDT 24
Finished Jul 07 07:01:34 PM PDT 24
Peak memory 217248 kb
Host smart-c3089549-0f51-49c9-87b8-377554e075fd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088510294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.2088510294
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.1463658075
Short name T773
Test name
Test status
Simulation time 267624748 ps
CPU time 2.78 seconds
Started Jul 07 07:01:27 PM PDT 24
Finished Jul 07 07:01:30 PM PDT 24
Peak memory 222004 kb
Host smart-cd038f7c-3473-43a9-a1d9-d0feee66ce37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463658075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.1463658075
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.1710664665
Short name T837
Test name
Test status
Simulation time 1253290660 ps
CPU time 14.42 seconds
Started Jul 07 07:01:32 PM PDT 24
Finished Jul 07 07:01:47 PM PDT 24
Peak memory 225576 kb
Host smart-a50deaab-a2c8-42b3-a013-a5f6c6232d51
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710664665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.1710664665
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.1059393153
Short name T242
Test name
Test status
Simulation time 2140328240 ps
CPU time 19.01 seconds
Started Jul 07 07:01:32 PM PDT 24
Finished Jul 07 07:01:51 PM PDT 24
Peak memory 225520 kb
Host smart-8cdb81c6-d62a-45b0-8a7e-858934997dbc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059393153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.1059393153
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.3601739283
Short name T652
Test name
Test status
Simulation time 760685975 ps
CPU time 10.25 seconds
Started Jul 07 07:01:29 PM PDT 24
Finished Jul 07 07:01:39 PM PDT 24
Peak memory 225592 kb
Host smart-1895e501-e476-4b5a-8436-35481779fb94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601739283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.3601739283
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.452588181
Short name T83
Test name
Test status
Simulation time 125878080 ps
CPU time 3.91 seconds
Started Jul 07 07:01:27 PM PDT 24
Finished Jul 07 07:01:31 PM PDT 24
Peak memory 213536 kb
Host smart-870a0857-61b7-4f86-bc5b-400ae7b9cbea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452588181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.452588181
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.2568962227
Short name T803
Test name
Test status
Simulation time 2872009718 ps
CPU time 27.56 seconds
Started Jul 07 07:01:30 PM PDT 24
Finished Jul 07 07:01:58 PM PDT 24
Peak memory 250616 kb
Host smart-a7257e4e-ca32-439c-ada2-eede5ba79897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568962227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.2568962227
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.2174132169
Short name T491
Test name
Test status
Simulation time 94044000 ps
CPU time 6.72 seconds
Started Jul 07 07:01:28 PM PDT 24
Finished Jul 07 07:01:35 PM PDT 24
Peak memory 246676 kb
Host smart-b6bc4e2f-e105-416f-bbdd-77f67d1220ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174132169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.2174132169
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.4276900690
Short name T503
Test name
Test status
Simulation time 16198284073 ps
CPU time 160.3 seconds
Started Jul 07 07:01:34 PM PDT 24
Finished Jul 07 07:04:15 PM PDT 24
Peak memory 266960 kb
Host smart-fc02a703-8067-44d8-8d68-98ad326504de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276900690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.4276900690
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.2603576625
Short name T693
Test name
Test status
Simulation time 28992904 ps
CPU time 0.87 seconds
Started Jul 07 07:01:28 PM PDT 24
Finished Jul 07 07:01:29 PM PDT 24
Peak memory 207784 kb
Host smart-63d6ad7b-45c2-44ab-a597-4ebe6f216b9d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603576625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.2603576625
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.3863415974
Short name T599
Test name
Test status
Simulation time 75696600 ps
CPU time 1.06 seconds
Started Jul 07 07:01:39 PM PDT 24
Finished Jul 07 07:01:40 PM PDT 24
Peak memory 208528 kb
Host smart-5c4a3926-c7a5-4060-be9d-4368bb330439
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863415974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.3863415974
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.3781486835
Short name T10
Test name
Test status
Simulation time 346631147 ps
CPU time 9.1 seconds
Started Jul 07 07:01:35 PM PDT 24
Finished Jul 07 07:01:44 PM PDT 24
Peak memory 225568 kb
Host smart-de9dc483-41cc-4f1d-a245-4022445d8062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781486835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.3781486835
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.21587103
Short name T850
Test name
Test status
Simulation time 1479053926 ps
CPU time 7.62 seconds
Started Jul 07 07:01:36 PM PDT 24
Finished Jul 07 07:01:43 PM PDT 24
Peak memory 217260 kb
Host smart-143b393b-29b9-4269-94fc-66060101f0c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21587103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.21587103
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.3371536930
Short name T409
Test name
Test status
Simulation time 286331376 ps
CPU time 2.62 seconds
Started Jul 07 07:01:36 PM PDT 24
Finished Jul 07 07:01:39 PM PDT 24
Peak memory 221908 kb
Host smart-dd04fbce-5494-4fae-a6fe-beb232004e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371536930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.3371536930
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.447101351
Short name T422
Test name
Test status
Simulation time 1737500698 ps
CPU time 11.04 seconds
Started Jul 07 07:01:37 PM PDT 24
Finished Jul 07 07:01:48 PM PDT 24
Peak memory 225520 kb
Host smart-c33cf5f6-fbfd-46f7-9063-112d40e6a0c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447101351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_di
gest.447101351
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.2992799470
Short name T747
Test name
Test status
Simulation time 1506547358 ps
CPU time 9.78 seconds
Started Jul 07 07:01:39 PM PDT 24
Finished Jul 07 07:01:49 PM PDT 24
Peak memory 217720 kb
Host smart-224c7cc3-cdda-485d-a55b-9e0b0850e2a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992799470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
2992799470
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.4280544015
Short name T541
Test name
Test status
Simulation time 328978901 ps
CPU time 11.67 seconds
Started Jul 07 07:01:37 PM PDT 24
Finished Jul 07 07:01:49 PM PDT 24
Peak memory 217840 kb
Host smart-dce5496c-084f-49ee-8bff-101211554757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280544015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.4280544015
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.2773690712
Short name T694
Test name
Test status
Simulation time 109805459 ps
CPU time 2.2 seconds
Started Jul 07 07:01:34 PM PDT 24
Finished Jul 07 07:01:36 PM PDT 24
Peak memory 214040 kb
Host smart-fff720b1-3846-4cc9-b2eb-c2aa8c705178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773690712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.2773690712
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.2066307308
Short name T361
Test name
Test status
Simulation time 510227435 ps
CPU time 25.61 seconds
Started Jul 07 07:01:34 PM PDT 24
Finished Jul 07 07:02:00 PM PDT 24
Peak memory 250540 kb
Host smart-8c1a3cbe-f8ec-4022-9def-92c67e5db867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066307308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.2066307308
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.766099563
Short name T318
Test name
Test status
Simulation time 219903477 ps
CPU time 8.94 seconds
Started Jul 07 07:01:31 PM PDT 24
Finished Jul 07 07:01:41 PM PDT 24
Peak memory 250520 kb
Host smart-513b5279-1605-4108-ad6c-f2c514aa6da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766099563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.766099563
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.3595939494
Short name T218
Test name
Test status
Simulation time 9146164514 ps
CPU time 78.21 seconds
Started Jul 07 07:01:37 PM PDT 24
Finished Jul 07 07:02:56 PM PDT 24
Peak memory 268808 kb
Host smart-62ed2d83-472e-4838-9358-54dcd4a7008c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595939494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.3595939494
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.1916731701
Short name T468
Test name
Test status
Simulation time 56911685 ps
CPU time 0.95 seconds
Started Jul 07 07:01:32 PM PDT 24
Finished Jul 07 07:01:33 PM PDT 24
Peak memory 212348 kb
Host smart-38965a93-b0d3-4aa6-a5b6-fc758fa2c655
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916731701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.1916731701
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.2656353081
Short name T113
Test name
Test status
Simulation time 40832506 ps
CPU time 0.83 seconds
Started Jul 07 07:01:40 PM PDT 24
Finished Jul 07 07:01:41 PM PDT 24
Peak memory 208608 kb
Host smart-70c38509-316e-4549-abcd-5e2f7cb9f314
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656353081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.2656353081
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.1385392629
Short name T401
Test name
Test status
Simulation time 697752147 ps
CPU time 14.3 seconds
Started Jul 07 07:01:35 PM PDT 24
Finished Jul 07 07:01:49 PM PDT 24
Peak memory 217784 kb
Host smart-35a918c0-0e0f-45e4-8360-8c2c09ab2b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385392629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.1385392629
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.3055364531
Short name T640
Test name
Test status
Simulation time 9116636224 ps
CPU time 15.95 seconds
Started Jul 07 07:01:40 PM PDT 24
Finished Jul 07 07:01:56 PM PDT 24
Peak memory 217256 kb
Host smart-3d48e809-de01-469a-9898-67fd46083342
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055364531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.3055364531
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.1556224862
Short name T247
Test name
Test status
Simulation time 169648698 ps
CPU time 4.26 seconds
Started Jul 07 07:01:34 PM PDT 24
Finished Jul 07 07:01:39 PM PDT 24
Peak memory 222316 kb
Host smart-15f1740a-6284-4bc4-bfa6-09f6659b6186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556224862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.1556224862
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.575454219
Short name T371
Test name
Test status
Simulation time 627560772 ps
CPU time 14.67 seconds
Started Jul 07 07:01:41 PM PDT 24
Finished Jul 07 07:01:56 PM PDT 24
Peak memory 225512 kb
Host smart-f1baf2d2-b35c-49b2-b62d-ded586c3b250
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575454219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_di
gest.575454219
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.1179768548
Short name T779
Test name
Test status
Simulation time 591520476 ps
CPU time 8.44 seconds
Started Jul 07 07:01:39 PM PDT 24
Finished Jul 07 07:01:48 PM PDT 24
Peak memory 225496 kb
Host smart-ba65117f-4135-4b28-9e6e-d936e75d3bfb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179768548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
1179768548
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.4123832607
Short name T292
Test name
Test status
Simulation time 4754951490 ps
CPU time 11.69 seconds
Started Jul 07 07:01:40 PM PDT 24
Finished Jul 07 07:01:51 PM PDT 24
Peak memory 217916 kb
Host smart-12b42ff6-a288-43bf-b7c5-94f3b1489ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123832607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.4123832607
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.485658617
Short name T99
Test name
Test status
Simulation time 541211910 ps
CPU time 7.84 seconds
Started Jul 07 07:01:36 PM PDT 24
Finished Jul 07 07:01:44 PM PDT 24
Peak memory 217168 kb
Host smart-f4d363c4-170f-4c36-b30b-e33029bf18d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485658617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.485658617
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.2386525803
Short name T461
Test name
Test status
Simulation time 259460791 ps
CPU time 24.8 seconds
Started Jul 07 07:01:36 PM PDT 24
Finished Jul 07 07:02:01 PM PDT 24
Peak memory 250496 kb
Host smart-464bc3ea-9d40-4b28-bb2a-c66c86ec01c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386525803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.2386525803
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.524592308
Short name T769
Test name
Test status
Simulation time 61954581 ps
CPU time 3.3 seconds
Started Jul 07 07:01:35 PM PDT 24
Finished Jul 07 07:01:38 PM PDT 24
Peak memory 217732 kb
Host smart-77e9da36-e76f-4364-bec4-e959f9e726b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524592308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.524592308
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.1088767169
Short name T364
Test name
Test status
Simulation time 10547965807 ps
CPU time 89.03 seconds
Started Jul 07 07:01:38 PM PDT 24
Finished Jul 07 07:03:07 PM PDT 24
Peak memory 225644 kb
Host smart-646f6a80-ae2e-4a8d-a4ea-0db332eb0d6b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088767169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.1088767169
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.3141262382
Short name T40
Test name
Test status
Simulation time 135654766563 ps
CPU time 696.32 seconds
Started Jul 07 07:01:40 PM PDT 24
Finished Jul 07 07:13:17 PM PDT 24
Peak memory 267444 kb
Host smart-52f2a327-0d25-4957-9d8b-c41ee7599207
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3141262382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.3141262382
Directory /workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.1409775456
Short name T37
Test name
Test status
Simulation time 32471123 ps
CPU time 0.82 seconds
Started Jul 07 07:01:34 PM PDT 24
Finished Jul 07 07:01:35 PM PDT 24
Peak memory 208360 kb
Host smart-e886c478-11cc-4c05-8efe-fe38c54d54bb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409775456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.1409775456
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.1014528924
Short name T467
Test name
Test status
Simulation time 37695567 ps
CPU time 1.17 seconds
Started Jul 07 07:01:45 PM PDT 24
Finished Jul 07 07:01:47 PM PDT 24
Peak memory 208488 kb
Host smart-05d2b4d8-0538-48ff-b794-03945846c23e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014528924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.1014528924
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.3457962956
Short name T21
Test name
Test status
Simulation time 659463338 ps
CPU time 7.39 seconds
Started Jul 07 07:01:45 PM PDT 24
Finished Jul 07 07:01:53 PM PDT 24
Peak memory 217180 kb
Host smart-7f1f6578-977d-48b9-8062-164e6110760e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457962956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.3457962956
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.1040677066
Short name T706
Test name
Test status
Simulation time 77537239 ps
CPU time 1.63 seconds
Started Jul 07 07:01:46 PM PDT 24
Finished Jul 07 07:01:48 PM PDT 24
Peak memory 217768 kb
Host smart-7bc9824f-ec4b-4172-804b-450895ae6e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040677066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.1040677066
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.2713703205
Short name T299
Test name
Test status
Simulation time 947575943 ps
CPU time 10.7 seconds
Started Jul 07 07:01:42 PM PDT 24
Finished Jul 07 07:01:53 PM PDT 24
Peak memory 218544 kb
Host smart-781feb85-a6af-4ff0-ba3c-867d4060b1fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713703205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.2713703205
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.777825610
Short name T322
Test name
Test status
Simulation time 1727048346 ps
CPU time 17.04 seconds
Started Jul 07 07:01:43 PM PDT 24
Finished Jul 07 07:02:00 PM PDT 24
Peak memory 225492 kb
Host smart-e1e6cc23-b8cc-40f7-924b-558e261bd055
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777825610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_di
gest.777825610
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.2765255503
Short name T659
Test name
Test status
Simulation time 339259904 ps
CPU time 9.25 seconds
Started Jul 07 07:01:43 PM PDT 24
Finished Jul 07 07:01:53 PM PDT 24
Peak memory 217652 kb
Host smart-efec8527-eb03-4507-815c-69023611d306
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765255503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
2765255503
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.2132157406
Short name T605
Test name
Test status
Simulation time 41907079 ps
CPU time 2.15 seconds
Started Jul 07 07:01:40 PM PDT 24
Finished Jul 07 07:01:43 PM PDT 24
Peak memory 213852 kb
Host smart-333c840d-6ef1-405c-aa9b-6d6189b629d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132157406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.2132157406
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.518059098
Short name T397
Test name
Test status
Simulation time 155764860 ps
CPU time 17.63 seconds
Started Jul 07 07:01:45 PM PDT 24
Finished Jul 07 07:02:03 PM PDT 24
Peak memory 250520 kb
Host smart-1b692e60-c4a9-4aff-8d52-e313b6ee0b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518059098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.518059098
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.1385218328
Short name T431
Test name
Test status
Simulation time 497227729 ps
CPU time 9.12 seconds
Started Jul 07 07:01:44 PM PDT 24
Finished Jul 07 07:01:53 PM PDT 24
Peak memory 246636 kb
Host smart-c6cfaa5e-d070-48a1-bee3-95ef1731e54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385218328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.1385218328
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.3638299520
Short name T156
Test name
Test status
Simulation time 6476707141 ps
CPU time 230.51 seconds
Started Jul 07 07:01:44 PM PDT 24
Finished Jul 07 07:05:35 PM PDT 24
Peak memory 283400 kb
Host smart-3f85d3e4-e73d-4d14-b1d7-6cfd4fe45cce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3638299520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all_with_rand_reset.3638299520
Directory /workspace/24.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.2249665414
Short name T474
Test name
Test status
Simulation time 12452574 ps
CPU time 0.97 seconds
Started Jul 07 07:01:39 PM PDT 24
Finished Jul 07 07:01:41 PM PDT 24
Peak memory 208380 kb
Host smart-e7fb1309-20bb-4dd1-acca-e0cab8e9bf88
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249665414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.2249665414
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.3216687688
Short name T403
Test name
Test status
Simulation time 50942218 ps
CPU time 0.83 seconds
Started Jul 07 07:01:49 PM PDT 24
Finished Jul 07 07:01:50 PM PDT 24
Peak memory 208416 kb
Host smart-b26683c5-f45b-4d89-90f1-be58149cab3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216687688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.3216687688
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.2816434346
Short name T352
Test name
Test status
Simulation time 2018881930 ps
CPU time 12.44 seconds
Started Jul 07 07:01:46 PM PDT 24
Finished Jul 07 07:01:58 PM PDT 24
Peak memory 217804 kb
Host smart-5067886e-a54a-4844-a8d9-7e73a126cf59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816434346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.2816434346
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.1780117730
Short name T810
Test name
Test status
Simulation time 684162154 ps
CPU time 9.37 seconds
Started Jul 07 07:01:46 PM PDT 24
Finished Jul 07 07:01:56 PM PDT 24
Peak memory 216916 kb
Host smart-18b239ab-98ae-44f9-a483-7d80d15d4c53
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780117730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.1780117730
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.4217219193
Short name T846
Test name
Test status
Simulation time 119387646 ps
CPU time 3.2 seconds
Started Jul 07 07:01:46 PM PDT 24
Finished Jul 07 07:01:50 PM PDT 24
Peak memory 217788 kb
Host smart-e4c4a945-2cb2-4f47-89c5-f479239ef52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217219193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.4217219193
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.3995878358
Short name T683
Test name
Test status
Simulation time 270454413 ps
CPU time 9.07 seconds
Started Jul 07 07:01:46 PM PDT 24
Finished Jul 07 07:01:55 PM PDT 24
Peak memory 224904 kb
Host smart-8d0626ff-ddbe-43bb-9421-cff0b88c4e95
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995878358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.3995878358
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.2214858645
Short name T489
Test name
Test status
Simulation time 4390416596 ps
CPU time 20.24 seconds
Started Jul 07 07:01:45 PM PDT 24
Finished Jul 07 07:02:06 PM PDT 24
Peak memory 225568 kb
Host smart-2f718dd1-b790-48e8-9c53-0490d58b3218
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214858645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.2214858645
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.1235640515
Short name T69
Test name
Test status
Simulation time 539491820 ps
CPU time 10.24 seconds
Started Jul 07 07:01:47 PM PDT 24
Finished Jul 07 07:01:57 PM PDT 24
Peak memory 217980 kb
Host smart-4888e324-85e5-471a-9dac-a219c8514aff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235640515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
1235640515
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.26198413
Short name T62
Test name
Test status
Simulation time 420809768 ps
CPU time 9.89 seconds
Started Jul 07 07:01:46 PM PDT 24
Finished Jul 07 07:01:57 PM PDT 24
Peak memory 225560 kb
Host smart-93d1bd43-c1d4-49fb-aeaf-5b0ec036b099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26198413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.26198413
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.3693639072
Short name T286
Test name
Test status
Simulation time 80959866 ps
CPU time 2.95 seconds
Started Jul 07 07:01:45 PM PDT 24
Finished Jul 07 07:01:48 PM PDT 24
Peak memory 214504 kb
Host smart-72918a6f-3421-407b-9867-eb20b77e962e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693639072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.3693639072
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.1695970884
Short name T795
Test name
Test status
Simulation time 521261525 ps
CPU time 29.56 seconds
Started Jul 07 07:01:48 PM PDT 24
Finished Jul 07 07:02:18 PM PDT 24
Peak memory 250596 kb
Host smart-7732958f-0d41-4f21-ac24-1e8e497e531f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695970884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.1695970884
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.1976901118
Short name T619
Test name
Test status
Simulation time 260485986 ps
CPU time 3.1 seconds
Started Jul 07 07:01:47 PM PDT 24
Finished Jul 07 07:01:50 PM PDT 24
Peak memory 220984 kb
Host smart-6acace36-97a2-4d12-97db-b283c7e6ac35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976901118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.1976901118
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.1649356368
Short name T52
Test name
Test status
Simulation time 4777832105 ps
CPU time 161.14 seconds
Started Jul 07 07:01:47 PM PDT 24
Finished Jul 07 07:04:28 PM PDT 24
Peak memory 250612 kb
Host smart-701e2ee3-b0d4-4bac-9c35-343774abe042
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649356368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.1649356368
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.2506858685
Short name T844
Test name
Test status
Simulation time 14744525 ps
CPU time 0.81 seconds
Started Jul 07 07:01:43 PM PDT 24
Finished Jul 07 07:01:44 PM PDT 24
Peak memory 208544 kb
Host smart-be72a5aa-4c7f-401c-b8b5-bd28717a9e70
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506858685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.2506858685
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.2518188775
Short name T340
Test name
Test status
Simulation time 63466788 ps
CPU time 0.98 seconds
Started Jul 07 07:01:53 PM PDT 24
Finished Jul 07 07:01:55 PM PDT 24
Peak memory 208532 kb
Host smart-0c0ce99c-2e08-4ab3-bccb-906b5d0ccc3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518188775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.2518188775
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.1051875525
Short name T275
Test name
Test status
Simulation time 290358348 ps
CPU time 10.7 seconds
Started Jul 07 07:01:51 PM PDT 24
Finished Jul 07 07:02:02 PM PDT 24
Peak memory 217800 kb
Host smart-a5c7dc7b-444a-47c9-b6c1-7b11f4c95c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051875525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.1051875525
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.1382146707
Short name T6
Test name
Test status
Simulation time 292102205 ps
CPU time 4.79 seconds
Started Jul 07 07:01:49 PM PDT 24
Finished Jul 07 07:01:54 PM PDT 24
Peak memory 217188 kb
Host smart-f1752349-3d61-4246-a812-edc8f2bcd6ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382146707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.1382146707
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.2962193647
Short name T219
Test name
Test status
Simulation time 217422484 ps
CPU time 2.64 seconds
Started Jul 07 07:01:47 PM PDT 24
Finished Jul 07 07:01:50 PM PDT 24
Peak memory 217808 kb
Host smart-cd548090-106f-4869-ad0e-bfdf80d368bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962193647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.2962193647
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.3364382079
Short name T630
Test name
Test status
Simulation time 4137973965 ps
CPU time 19.82 seconds
Started Jul 07 07:01:55 PM PDT 24
Finished Jul 07 07:02:15 PM PDT 24
Peak memory 225816 kb
Host smart-a76aece6-7b42-45d4-9537-045e53b5a616
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364382079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.3364382079
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.1773827913
Short name T344
Test name
Test status
Simulation time 412225279 ps
CPU time 10.42 seconds
Started Jul 07 07:01:54 PM PDT 24
Finished Jul 07 07:02:05 PM PDT 24
Peak memory 217692 kb
Host smart-bb292787-79c2-4de2-8ebc-adfb4a47f57d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773827913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
1773827913
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.2575227229
Short name T572
Test name
Test status
Simulation time 1589627553 ps
CPU time 10.3 seconds
Started Jul 07 07:01:50 PM PDT 24
Finished Jul 07 07:02:00 PM PDT 24
Peak memory 224256 kb
Host smart-246f4199-8ada-4a9c-8334-0e56bceaa84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575227229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.2575227229
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.2584472282
Short name T664
Test name
Test status
Simulation time 72069851 ps
CPU time 1.65 seconds
Started Jul 07 07:01:46 PM PDT 24
Finished Jul 07 07:01:48 PM PDT 24
Peak memory 213492 kb
Host smart-47eed426-e269-4285-b0d1-26621fc810fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584472282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.2584472282
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.957031293
Short name T387
Test name
Test status
Simulation time 229834124 ps
CPU time 27.43 seconds
Started Jul 07 07:01:49 PM PDT 24
Finished Jul 07 07:02:17 PM PDT 24
Peak memory 250496 kb
Host smart-21e17c90-fd4d-48af-8399-8e2dc44a6ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957031293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.957031293
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.61306017
Short name T437
Test name
Test status
Simulation time 499089429 ps
CPU time 6.94 seconds
Started Jul 07 07:01:49 PM PDT 24
Finished Jul 07 07:01:56 PM PDT 24
Peak memory 246504 kb
Host smart-be662336-b9bd-489b-afc5-de50df632aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61306017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.61306017
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.1483164603
Short name T472
Test name
Test status
Simulation time 35419138956 ps
CPU time 138.52 seconds
Started Jul 07 07:01:55 PM PDT 24
Finished Jul 07 07:04:14 PM PDT 24
Peak memory 250940 kb
Host smart-ad7c2a8e-afd8-42f5-8c59-5ccc1634742a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483164603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.1483164603
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.2146476208
Short name T569
Test name
Test status
Simulation time 36199217 ps
CPU time 0.91 seconds
Started Jul 07 07:01:50 PM PDT 24
Finished Jul 07 07:01:51 PM PDT 24
Peak memory 208440 kb
Host smart-39ba707f-4b0e-4b57-99d9-6586e4424a0b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146476208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.2146476208
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.330632733
Short name T701
Test name
Test status
Simulation time 32831862 ps
CPU time 0.92 seconds
Started Jul 07 07:01:57 PM PDT 24
Finished Jul 07 07:01:58 PM PDT 24
Peak memory 208544 kb
Host smart-de5c08ed-ffb7-45aa-afc6-cb54873a3b92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330632733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.330632733
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.783292235
Short name T438
Test name
Test status
Simulation time 873855915 ps
CPU time 9.7 seconds
Started Jul 07 07:01:54 PM PDT 24
Finished Jul 07 07:02:04 PM PDT 24
Peak memory 217772 kb
Host smart-575abf53-d5fd-4560-98f2-ec6a7178b036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783292235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.783292235
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.1875648929
Short name T862
Test name
Test status
Simulation time 876680588 ps
CPU time 3.09 seconds
Started Jul 07 07:01:56 PM PDT 24
Finished Jul 07 07:02:00 PM PDT 24
Peak memory 217196 kb
Host smart-e445da0c-dd65-4076-867d-582e3ef2ede5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875648929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.1875648929
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.3565357104
Short name T612
Test name
Test status
Simulation time 193909452 ps
CPU time 4.38 seconds
Started Jul 07 07:01:53 PM PDT 24
Finished Jul 07 07:01:58 PM PDT 24
Peak memory 217800 kb
Host smart-170ed0d2-d2cf-4169-ba85-963bd61fcb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565357104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.3565357104
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.1935551235
Short name T730
Test name
Test status
Simulation time 256035705 ps
CPU time 11.28 seconds
Started Jul 07 07:02:00 PM PDT 24
Finished Jul 07 07:02:12 PM PDT 24
Peak memory 218432 kb
Host smart-b6046314-7224-4ee1-9f4e-f0ec1c603b8b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935551235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.1935551235
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.3195383647
Short name T797
Test name
Test status
Simulation time 6389501439 ps
CPU time 14.01 seconds
Started Jul 07 07:02:01 PM PDT 24
Finished Jul 07 07:02:16 PM PDT 24
Peak memory 225560 kb
Host smart-48bb2d41-cd97-48b9-9752-11c4077b6996
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195383647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.3195383647
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.22427355
Short name T284
Test name
Test status
Simulation time 713865614 ps
CPU time 12.58 seconds
Started Jul 07 07:01:57 PM PDT 24
Finished Jul 07 07:02:10 PM PDT 24
Peak memory 217724 kb
Host smart-854383f2-5ac4-4885-b07b-fff1f0dc817c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22427355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.22427355
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.287876666
Short name T496
Test name
Test status
Simulation time 279310096 ps
CPU time 10.74 seconds
Started Jul 07 07:01:53 PM PDT 24
Finished Jul 07 07:02:05 PM PDT 24
Peak memory 217872 kb
Host smart-c6d1fb12-0458-48f6-87d2-d4bfcb65f953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287876666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.287876666
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.3140701004
Short name T400
Test name
Test status
Simulation time 68405614 ps
CPU time 3.47 seconds
Started Jul 07 07:01:53 PM PDT 24
Finished Jul 07 07:01:57 PM PDT 24
Peak memory 217204 kb
Host smart-db73e6ed-f88c-4d82-b759-97e107d3760d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140701004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.3140701004
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.764159192
Short name T851
Test name
Test status
Simulation time 241612797 ps
CPU time 31.01 seconds
Started Jul 07 07:01:56 PM PDT 24
Finished Jul 07 07:02:28 PM PDT 24
Peak memory 250548 kb
Host smart-ebd5e66d-2f75-4dca-956f-c49ffec5f902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764159192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.764159192
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.185994216
Short name T566
Test name
Test status
Simulation time 185996699 ps
CPU time 6.23 seconds
Started Jul 07 07:01:56 PM PDT 24
Finished Jul 07 07:02:03 PM PDT 24
Peak memory 246836 kb
Host smart-e7f9553c-0efb-4b93-a414-7d76cb56a031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185994216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.185994216
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.349415672
Short name T169
Test name
Test status
Simulation time 2035736666 ps
CPU time 40.25 seconds
Started Jul 07 07:01:59 PM PDT 24
Finished Jul 07 07:02:40 PM PDT 24
Peak memory 246100 kb
Host smart-bb057cca-1741-47fa-96be-95d33d48e004
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349415672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.349415672
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.1816091281
Short name T89
Test name
Test status
Simulation time 23478078 ps
CPU time 0.96 seconds
Started Jul 07 07:01:55 PM PDT 24
Finished Jul 07 07:01:56 PM PDT 24
Peak memory 217372 kb
Host smart-1ad474f4-06ea-4442-936d-75ae22818009
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816091281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.1816091281
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.4000241104
Short name T792
Test name
Test status
Simulation time 18299711 ps
CPU time 0.97 seconds
Started Jul 07 07:02:02 PM PDT 24
Finished Jul 07 07:02:03 PM PDT 24
Peak memory 208540 kb
Host smart-a34f8c86-3419-423f-95c4-1ae705b820f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000241104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.4000241104
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.3117119543
Short name T426
Test name
Test status
Simulation time 1194632206 ps
CPU time 12.36 seconds
Started Jul 07 07:01:58 PM PDT 24
Finished Jul 07 07:02:11 PM PDT 24
Peak memory 217680 kb
Host smart-04ceb1e6-fb9e-486f-8c07-b0f02f6dd8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117119543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.3117119543
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.1980351740
Short name T307
Test name
Test status
Simulation time 100475546 ps
CPU time 3.31 seconds
Started Jul 07 07:02:01 PM PDT 24
Finished Jul 07 07:02:05 PM PDT 24
Peak memory 221780 kb
Host smart-78c88a0c-1798-4b14-bb76-517f2cf9a313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980351740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.1980351740
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.9509930
Short name T248
Test name
Test status
Simulation time 964202393 ps
CPU time 15.59 seconds
Started Jul 07 07:02:01 PM PDT 24
Finished Jul 07 07:02:17 PM PDT 24
Peak memory 217820 kb
Host smart-71009d83-c5f3-4e92-a198-2fa1d9c96edd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9509930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.9509930
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.3030474367
Short name T554
Test name
Test status
Simulation time 431842229 ps
CPU time 10.76 seconds
Started Jul 07 07:02:00 PM PDT 24
Finished Jul 07 07:02:11 PM PDT 24
Peak memory 225508 kb
Host smart-4d11715c-fff1-4eb2-a38c-8ac179baad3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030474367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.3030474367
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.1705258700
Short name T521
Test name
Test status
Simulation time 1592073207 ps
CPU time 11.47 seconds
Started Jul 07 07:02:01 PM PDT 24
Finished Jul 07 07:02:13 PM PDT 24
Peak memory 217720 kb
Host smart-b16cdebd-f720-442c-94d6-7f2d25436da9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705258700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
1705258700
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.2640054295
Short name T657
Test name
Test status
Simulation time 965756406 ps
CPU time 8.37 seconds
Started Jul 07 07:01:57 PM PDT 24
Finished Jul 07 07:02:06 PM PDT 24
Peak memory 225576 kb
Host smart-33ec2b9c-40ef-4bb1-93fb-af9478d93f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640054295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.2640054295
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.1777824729
Short name T253
Test name
Test status
Simulation time 363266257 ps
CPU time 5.74 seconds
Started Jul 07 07:01:57 PM PDT 24
Finished Jul 07 07:02:03 PM PDT 24
Peak memory 217196 kb
Host smart-f77dad3d-c27e-4aa6-a6e7-a33b649479fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777824729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.1777824729
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.676766112
Short name T227
Test name
Test status
Simulation time 789092127 ps
CPU time 30.63 seconds
Started Jul 07 07:01:57 PM PDT 24
Finished Jul 07 07:02:28 PM PDT 24
Peak memory 250500 kb
Host smart-78af7b92-2dce-47a0-820c-202d33608ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676766112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.676766112
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.1989259101
Short name T323
Test name
Test status
Simulation time 635909176 ps
CPU time 7.46 seconds
Started Jul 07 07:02:00 PM PDT 24
Finished Jul 07 07:02:08 PM PDT 24
Peak memory 250532 kb
Host smart-671d126d-6de6-4e7c-9d4c-a1d04e198049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989259101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.1989259101
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.1494230758
Short name T559
Test name
Test status
Simulation time 16941767430 ps
CPU time 151.08 seconds
Started Jul 07 07:02:02 PM PDT 24
Finished Jul 07 07:04:33 PM PDT 24
Peak memory 222084 kb
Host smart-1f3c4149-168e-4870-8f73-c5730e844525
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494230758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.1494230758
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.3139518341
Short name T727
Test name
Test status
Simulation time 42821914 ps
CPU time 0.84 seconds
Started Jul 07 07:02:01 PM PDT 24
Finished Jul 07 07:02:02 PM PDT 24
Peak memory 208568 kb
Host smart-574247ba-510c-4dac-a650-9b3118593edd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139518341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.3139518341
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.1800999877
Short name T582
Test name
Test status
Simulation time 102927858 ps
CPU time 0.91 seconds
Started Jul 07 07:02:03 PM PDT 24
Finished Jul 07 07:02:04 PM PDT 24
Peak memory 208552 kb
Host smart-e183545f-62b9-4e68-a619-3cfee2908c45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800999877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.1800999877
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.4207778242
Short name T39
Test name
Test status
Simulation time 1617879088 ps
CPU time 28.76 seconds
Started Jul 07 07:02:06 PM PDT 24
Finished Jul 07 07:02:35 PM PDT 24
Peak memory 225508 kb
Host smart-c0ab8ef0-5d76-4028-8873-6a097b033226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207778242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.4207778242
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.1760260081
Short name T355
Test name
Test status
Simulation time 345044629 ps
CPU time 8.1 seconds
Started Jul 07 07:02:05 PM PDT 24
Finished Jul 07 07:02:14 PM PDT 24
Peak memory 216692 kb
Host smart-2f489042-6c70-49c0-ab42-a28d0057f781
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760260081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.1760260081
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.182388499
Short name T264
Test name
Test status
Simulation time 254507816 ps
CPU time 2.8 seconds
Started Jul 07 07:02:05 PM PDT 24
Finished Jul 07 07:02:08 PM PDT 24
Peak memory 217752 kb
Host smart-26681c1b-d7be-49bc-b029-39034f1baff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182388499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.182388499
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.2858744255
Short name T71
Test name
Test status
Simulation time 225444638 ps
CPU time 11.96 seconds
Started Jul 07 07:02:09 PM PDT 24
Finished Jul 07 07:02:21 PM PDT 24
Peak memory 217784 kb
Host smart-28386b2e-120e-45a2-b3a6-a1881b6adc58
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858744255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.2858744255
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.2740879951
Short name T211
Test name
Test status
Simulation time 2433880577 ps
CPU time 21.58 seconds
Started Jul 07 07:02:08 PM PDT 24
Finished Jul 07 07:02:30 PM PDT 24
Peak memory 225568 kb
Host smart-ec1b6619-c6cd-452d-8067-92b731876168
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740879951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.2740879951
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.951656949
Short name T507
Test name
Test status
Simulation time 1387386003 ps
CPU time 13.29 seconds
Started Jul 07 07:02:06 PM PDT 24
Finished Jul 07 07:02:19 PM PDT 24
Peak memory 217716 kb
Host smart-51df23a2-8ccc-4fc8-a20e-6cea347aa6d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951656949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.951656949
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.1754771345
Short name T595
Test name
Test status
Simulation time 1090754776 ps
CPU time 10.93 seconds
Started Jul 07 07:02:08 PM PDT 24
Finished Jul 07 07:02:20 PM PDT 24
Peak memory 225564 kb
Host smart-5a5958fe-49e4-4b2f-b832-9d55d1cb1207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754771345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.1754771345
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.1839477742
Short name T452
Test name
Test status
Simulation time 462760717 ps
CPU time 6.33 seconds
Started Jul 07 07:02:01 PM PDT 24
Finished Jul 07 07:02:08 PM PDT 24
Peak memory 217128 kb
Host smart-2fcef0ac-f0b1-4f62-8069-320a55a94621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839477742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.1839477742
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.3393882452
Short name T607
Test name
Test status
Simulation time 267069816 ps
CPU time 24.9 seconds
Started Jul 07 07:02:06 PM PDT 24
Finished Jul 07 07:02:31 PM PDT 24
Peak memory 250540 kb
Host smart-f5d3d54e-45ca-4d2a-b599-a7f4c4b83d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393882452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.3393882452
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.3403190906
Short name T215
Test name
Test status
Simulation time 97044620 ps
CPU time 8.17 seconds
Started Jul 07 07:02:05 PM PDT 24
Finished Jul 07 07:02:14 PM PDT 24
Peak memory 250376 kb
Host smart-1e7458a6-01bc-4fce-b7ba-645db13ad748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403190906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.3403190906
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.3512303285
Short name T434
Test name
Test status
Simulation time 5707236844 ps
CPU time 46.84 seconds
Started Jul 07 07:02:05 PM PDT 24
Finished Jul 07 07:02:52 PM PDT 24
Peak memory 225632 kb
Host smart-6b4359c3-2a78-4eee-9c2a-8bfe99d93b8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512303285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.3512303285
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.449758227
Short name T575
Test name
Test status
Simulation time 48621489601 ps
CPU time 468.14 seconds
Started Jul 07 07:02:07 PM PDT 24
Finished Jul 07 07:09:55 PM PDT 24
Peak memory 282412 kb
Host smart-659d04bd-3f1b-4f95-9032-f6ebd991291b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=449758227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all_with_rand_reset.449758227
Directory /workspace/29.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.498571232
Short name T670
Test name
Test status
Simulation time 67314678 ps
CPU time 0.9 seconds
Started Jul 07 07:02:07 PM PDT 24
Finished Jul 07 07:02:09 PM PDT 24
Peak memory 208380 kb
Host smart-3a6dbdc4-bc67-4d6d-adfd-b458b4a79d1f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498571232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ct
rl_volatile_unlock_smoke.498571232
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.1979877003
Short name T470
Test name
Test status
Simulation time 44466294 ps
CPU time 0.99 seconds
Started Jul 07 06:59:33 PM PDT 24
Finished Jul 07 06:59:35 PM PDT 24
Peak memory 208532 kb
Host smart-a6ee9c1d-49a9-4e71-b9b3-4e6df88b8f01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979877003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.1979877003
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.1701639890
Short name T391
Test name
Test status
Simulation time 1331417014 ps
CPU time 10.32 seconds
Started Jul 07 06:59:29 PM PDT 24
Finished Jul 07 06:59:40 PM PDT 24
Peak memory 225548 kb
Host smart-47ebc5a9-e671-48c0-9abd-1b258c02604d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701639890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.1701639890
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.3134060478
Short name T480
Test name
Test status
Simulation time 1675335767 ps
CPU time 10.23 seconds
Started Jul 07 06:59:39 PM PDT 24
Finished Jul 07 06:59:49 PM PDT 24
Peak memory 217140 kb
Host smart-cc1f6af2-6b58-4f85-8a89-43c69dc11baa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134060478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.3134060478
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.33866524
Short name T668
Test name
Test status
Simulation time 2699676386 ps
CPU time 41.13 seconds
Started Jul 07 06:59:31 PM PDT 24
Finished Jul 07 07:00:12 PM PDT 24
Peak memory 218576 kb
Host smart-bb480056-5f3d-43e1-ab93-8106beeafaaf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33866524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_l
c_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_erro
rs.33866524
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.31502913
Short name T373
Test name
Test status
Simulation time 375841046 ps
CPU time 3.01 seconds
Started Jul 07 06:59:30 PM PDT 24
Finished Jul 07 06:59:33 PM PDT 24
Peak memory 217392 kb
Host smart-dcc86be9-57d1-4211-a5b5-48e34d7458db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31502913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.31502913
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.1278220271
Short name T100
Test name
Test status
Simulation time 3896195974 ps
CPU time 26.86 seconds
Started Jul 07 06:59:32 PM PDT 24
Finished Jul 07 06:59:59 PM PDT 24
Peak memory 225556 kb
Host smart-8dcc39ca-555a-4bdc-8279-6908b4b0a700
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278220271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.1278220271
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1995816030
Short name T270
Test name
Test status
Simulation time 923469237 ps
CPU time 15.02 seconds
Started Jul 07 06:59:30 PM PDT 24
Finished Jul 07 06:59:46 PM PDT 24
Peak memory 217108 kb
Host smart-feb8b215-a0b4-4935-8ed5-e24b33e35160
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995816030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.1995816030
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.3967711482
Short name T163
Test name
Test status
Simulation time 275383821 ps
CPU time 2.81 seconds
Started Jul 07 06:59:30 PM PDT 24
Finished Jul 07 06:59:33 PM PDT 24
Peak memory 217120 kb
Host smart-cb5851ff-9e3f-4e30-85b4-2685b083008e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967711482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
3967711482
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.4223619855
Short name T313
Test name
Test status
Simulation time 1829384659 ps
CPU time 53.97 seconds
Started Jul 07 06:59:32 PM PDT 24
Finished Jul 07 07:00:27 PM PDT 24
Peak memory 266840 kb
Host smart-7fb0bfc9-89bd-4e75-9f04-415a300e6b0e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223619855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.4223619855
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.2974661902
Short name T840
Test name
Test status
Simulation time 504705883 ps
CPU time 17.47 seconds
Started Jul 07 06:59:30 PM PDT 24
Finished Jul 07 06:59:48 PM PDT 24
Peak memory 250456 kb
Host smart-750120e4-9d73-4763-862a-0eb2e5e904bd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974661902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.2974661902
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.487290206
Short name T533
Test name
Test status
Simulation time 85367368 ps
CPU time 3.08 seconds
Started Jul 07 06:59:30 PM PDT 24
Finished Jul 07 06:59:33 PM PDT 24
Peak memory 221876 kb
Host smart-d98e68e0-3205-4976-ac83-6472201205e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487290206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.487290206
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.1350296603
Short name T824
Test name
Test status
Simulation time 453825849 ps
CPU time 13.34 seconds
Started Jul 07 06:59:26 PM PDT 24
Finished Jul 07 06:59:40 PM PDT 24
Peak memory 213572 kb
Host smart-6327fb0b-9c12-4ad7-b4dd-f26280bf8fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350296603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.1350296603
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.3694828114
Short name T93
Test name
Test status
Simulation time 246723421 ps
CPU time 25.82 seconds
Started Jul 07 06:59:33 PM PDT 24
Finished Jul 07 06:59:59 PM PDT 24
Peak memory 269368 kb
Host smart-b4450239-afb4-43fb-a774-90687dd9ca86
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694828114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.3694828114
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.704900749
Short name T699
Test name
Test status
Simulation time 321866464 ps
CPU time 14.05 seconds
Started Jul 07 06:59:32 PM PDT 24
Finished Jul 07 06:59:47 PM PDT 24
Peak memory 218500 kb
Host smart-0a800391-0791-411a-8d35-5d36ffd80543
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704900749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.704900749
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.667614915
Short name T383
Test name
Test status
Simulation time 1388629342 ps
CPU time 14.27 seconds
Started Jul 07 06:59:31 PM PDT 24
Finished Jul 07 06:59:45 PM PDT 24
Peak memory 225492 kb
Host smart-b1277db3-cebd-4ad1-a24e-96eb7c9ef089
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667614915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_dig
est.667614915
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.1275575800
Short name T334
Test name
Test status
Simulation time 2124682412 ps
CPU time 12.88 seconds
Started Jul 07 06:59:34 PM PDT 24
Finished Jul 07 06:59:47 PM PDT 24
Peak memory 217660 kb
Host smart-dcc3e92a-72f7-48e0-adbd-0457b77f825a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275575800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.1
275575800
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.1752505393
Short name T663
Test name
Test status
Simulation time 1271391952 ps
CPU time 10.73 seconds
Started Jul 07 06:59:26 PM PDT 24
Finished Jul 07 06:59:37 PM PDT 24
Peak memory 224584 kb
Host smart-b7e7b537-a104-41f3-a0cc-4dbe5288be0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752505393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.1752505393
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.2002369637
Short name T260
Test name
Test status
Simulation time 249357116 ps
CPU time 4.05 seconds
Started Jul 07 06:59:28 PM PDT 24
Finished Jul 07 06:59:33 PM PDT 24
Peak memory 217264 kb
Host smart-b1953901-b1ae-4916-9aa6-fbc990907eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002369637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.2002369637
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.3038982769
Short name T845
Test name
Test status
Simulation time 428544088 ps
CPU time 29.62 seconds
Started Jul 07 06:59:28 PM PDT 24
Finished Jul 07 06:59:58 PM PDT 24
Peak memory 250492 kb
Host smart-86e0231f-9c58-42d4-bca1-8a9fcc7e750e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038982769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.3038982769
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.2142528345
Short name T362
Test name
Test status
Simulation time 254868685 ps
CPU time 8.05 seconds
Started Jul 07 06:59:27 PM PDT 24
Finished Jul 07 06:59:35 PM PDT 24
Peak memory 250540 kb
Host smart-e226b77d-bf4f-4d1f-9542-f669a3ee3dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142528345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.2142528345
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.3982010693
Short name T79
Test name
Test status
Simulation time 36392295771 ps
CPU time 138.01 seconds
Started Jul 07 06:59:33 PM PDT 24
Finished Jul 07 07:01:51 PM PDT 24
Peak memory 283100 kb
Host smart-b713a8bb-e8eb-46d8-92f8-53cb734fa935
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982010693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.3982010693
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.2777492004
Short name T729
Test name
Test status
Simulation time 23243088 ps
CPU time 0.9 seconds
Started Jul 07 06:59:30 PM PDT 24
Finished Jul 07 06:59:31 PM PDT 24
Peak memory 208148 kb
Host smart-2770bbe0-8209-4eb9-be65-192b5af2d866
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777492004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.2777492004
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.3102579598
Short name T494
Test name
Test status
Simulation time 28626342 ps
CPU time 1.11 seconds
Started Jul 07 07:02:12 PM PDT 24
Finished Jul 07 07:02:14 PM PDT 24
Peak memory 208572 kb
Host smart-e0bd2005-6a4d-4a7e-ba4b-c2473cc1e0d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102579598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.3102579598
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.3615482865
Short name T584
Test name
Test status
Simulation time 391427671 ps
CPU time 12.47 seconds
Started Jul 07 07:02:03 PM PDT 24
Finished Jul 07 07:02:16 PM PDT 24
Peak memory 217712 kb
Host smart-197b50d4-291a-46cd-8991-ed080b37634a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615482865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.3615482865
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.4002155212
Short name T171
Test name
Test status
Simulation time 172417697 ps
CPU time 4.59 seconds
Started Jul 07 07:02:12 PM PDT 24
Finished Jul 07 07:02:17 PM PDT 24
Peak memory 217196 kb
Host smart-20fb192f-0b55-4f45-8edb-da56fa1ce088
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002155212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.4002155212
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.3582425250
Short name T68
Test name
Test status
Simulation time 286725953 ps
CPU time 3.72 seconds
Started Jul 07 07:02:05 PM PDT 24
Finished Jul 07 07:02:08 PM PDT 24
Peak memory 217752 kb
Host smart-2b727fa2-ac59-4cfe-83dc-d182f88448b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582425250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.3582425250
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.1659103476
Short name T571
Test name
Test status
Simulation time 1241711444 ps
CPU time 13.24 seconds
Started Jul 07 07:02:08 PM PDT 24
Finished Jul 07 07:02:21 PM PDT 24
Peak memory 225524 kb
Host smart-1a772098-e03a-4016-a2a2-faf68ec6ceb1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659103476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.1659103476
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.2810220021
Short name T416
Test name
Test status
Simulation time 2129012968 ps
CPU time 12.42 seconds
Started Jul 07 07:02:13 PM PDT 24
Finished Jul 07 07:02:26 PM PDT 24
Peak memory 225032 kb
Host smart-5b8a974f-b8ab-4eec-9d17-63689c561a39
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810220021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
2810220021
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.33857542
Short name T31
Test name
Test status
Simulation time 2204521076 ps
CPU time 7.6 seconds
Started Jul 07 07:02:09 PM PDT 24
Finished Jul 07 07:02:17 PM PDT 24
Peak memory 224760 kb
Host smart-fa633684-15b6-4efd-ac3e-9eb8523fd22b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33857542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.33857542
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.2741162720
Short name T339
Test name
Test status
Simulation time 122805442 ps
CPU time 2.64 seconds
Started Jul 07 07:02:07 PM PDT 24
Finished Jul 07 07:02:10 PM PDT 24
Peak memory 217208 kb
Host smart-da31b55c-14a8-41e0-8fff-1775f9510fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741162720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.2741162720
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.269502834
Short name T471
Test name
Test status
Simulation time 1422894406 ps
CPU time 27.17 seconds
Started Jul 07 07:02:05 PM PDT 24
Finished Jul 07 07:02:33 PM PDT 24
Peak memory 250492 kb
Host smart-5fc4198f-db85-4d9d-b8d1-f9dd306e549b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269502834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.269502834
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.2857971467
Short name T793
Test name
Test status
Simulation time 121643733 ps
CPU time 3.69 seconds
Started Jul 07 07:02:05 PM PDT 24
Finished Jul 07 07:02:09 PM PDT 24
Peak memory 225940 kb
Host smart-ea38e65b-2d1f-4857-8af3-87aeddc6d0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857971467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.2857971467
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.2706123425
Short name T170
Test name
Test status
Simulation time 8200540319 ps
CPU time 46.94 seconds
Started Jul 07 07:02:13 PM PDT 24
Finished Jul 07 07:03:00 PM PDT 24
Peak memory 250592 kb
Host smart-dc7f4936-8350-43bd-999d-a86d7e7701ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706123425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.2706123425
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.2147052825
Short name T731
Test name
Test status
Simulation time 38784921 ps
CPU time 0.91 seconds
Started Jul 07 07:02:05 PM PDT 24
Finished Jul 07 07:02:07 PM PDT 24
Peak memory 211392 kb
Host smart-6124a575-0b95-4a0f-ba89-c0f3caab6083
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147052825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.2147052825
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.3010035754
Short name T441
Test name
Test status
Simulation time 15994911 ps
CPU time 1.08 seconds
Started Jul 07 07:02:14 PM PDT 24
Finished Jul 07 07:02:16 PM PDT 24
Peak memory 208556 kb
Host smart-4e0f27a5-025b-4f48-8886-22f0b2f60986
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010035754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.3010035754
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.786149650
Short name T853
Test name
Test status
Simulation time 1379340368 ps
CPU time 5.39 seconds
Started Jul 07 07:02:09 PM PDT 24
Finished Jul 07 07:02:14 PM PDT 24
Peak memory 217204 kb
Host smart-66f473ee-5858-462b-88ed-27cc05d61365
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786149650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.786149650
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.3981656071
Short name T290
Test name
Test status
Simulation time 625249399 ps
CPU time 2.82 seconds
Started Jul 07 07:02:13 PM PDT 24
Finished Jul 07 07:02:16 PM PDT 24
Peak memory 221752 kb
Host smart-d45f9fd5-4955-4d93-a518-ee329181de67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981656071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.3981656071
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.3084070898
Short name T626
Test name
Test status
Simulation time 739411290 ps
CPU time 16.65 seconds
Started Jul 07 07:02:12 PM PDT 24
Finished Jul 07 07:02:29 PM PDT 24
Peak memory 218424 kb
Host smart-847292ee-e7e3-4287-9272-f98f51b668be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084070898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.3084070898
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.3386801632
Short name T618
Test name
Test status
Simulation time 338464618 ps
CPU time 10.99 seconds
Started Jul 07 07:02:17 PM PDT 24
Finished Jul 07 07:02:28 PM PDT 24
Peak memory 225760 kb
Host smart-10845bc4-5adb-4d17-8c61-a3946764f262
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386801632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.3386801632
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.2383807270
Short name T825
Test name
Test status
Simulation time 1778870163 ps
CPU time 14.02 seconds
Started Jul 07 07:02:14 PM PDT 24
Finished Jul 07 07:02:29 PM PDT 24
Peak memory 217716 kb
Host smart-539001f6-d0fe-44c2-8bd2-f81559f418b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383807270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
2383807270
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.7089295
Short name T499
Test name
Test status
Simulation time 282798023 ps
CPU time 12.01 seconds
Started Jul 07 07:02:15 PM PDT 24
Finished Jul 07 07:02:27 PM PDT 24
Peak memory 225664 kb
Host smart-d51ce1f3-69ef-482d-86ae-3aed6c23d523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7089295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.7089295
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.4077103983
Short name T510
Test name
Test status
Simulation time 51817116 ps
CPU time 1.15 seconds
Started Jul 07 07:02:09 PM PDT 24
Finished Jul 07 07:02:10 PM PDT 24
Peak memory 217180 kb
Host smart-8a7ae036-3372-439e-ac0a-eebfc2d8f8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077103983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.4077103983
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.4118270858
Short name T621
Test name
Test status
Simulation time 372981241 ps
CPU time 42.94 seconds
Started Jul 07 07:02:14 PM PDT 24
Finished Jul 07 07:02:58 PM PDT 24
Peak memory 250608 kb
Host smart-0e909446-7c0a-4a57-a511-802047397ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118270858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.4118270858
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.2294797997
Short name T505
Test name
Test status
Simulation time 99037863 ps
CPU time 7.66 seconds
Started Jul 07 07:02:08 PM PDT 24
Finished Jul 07 07:02:16 PM PDT 24
Peak memory 250524 kb
Host smart-da63900d-3ce4-44b7-86e2-a733867e0d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294797997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.2294797997
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.3248065475
Short name T583
Test name
Test status
Simulation time 842614536 ps
CPU time 20.18 seconds
Started Jul 07 07:02:15 PM PDT 24
Finished Jul 07 07:02:36 PM PDT 24
Peak memory 219968 kb
Host smart-f4be3ae3-963d-4924-bc90-ae43bdf3f8fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248065475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.3248065475
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.3791159079
Short name T295
Test name
Test status
Simulation time 14230413 ps
CPU time 1.08 seconds
Started Jul 07 07:02:13 PM PDT 24
Finished Jul 07 07:02:14 PM PDT 24
Peak memory 211416 kb
Host smart-0e9aa274-6350-4c0d-9339-689062ee155a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791159079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.3791159079
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.1407016407
Short name T80
Test name
Test status
Simulation time 64945053 ps
CPU time 1.06 seconds
Started Jul 07 07:02:17 PM PDT 24
Finished Jul 07 07:02:19 PM PDT 24
Peak memory 208528 kb
Host smart-89184934-5406-493d-8719-b03be3419b71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407016407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.1407016407
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.2607656612
Short name T475
Test name
Test status
Simulation time 873511194 ps
CPU time 11.29 seconds
Started Jul 07 07:02:14 PM PDT 24
Finished Jul 07 07:02:27 PM PDT 24
Peak memory 225592 kb
Host smart-999bc2dd-b4e0-4d40-acd7-6737fd462827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607656612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.2607656612
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.1853151315
Short name T735
Test name
Test status
Simulation time 1628815262 ps
CPU time 2.92 seconds
Started Jul 07 07:02:16 PM PDT 24
Finished Jul 07 07:02:19 PM PDT 24
Peak memory 217192 kb
Host smart-d0c360f0-33d0-41cc-a823-b4f567ee8adf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853151315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.1853151315
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.1455240355
Short name T255
Test name
Test status
Simulation time 350986318 ps
CPU time 3.18 seconds
Started Jul 07 07:02:14 PM PDT 24
Finished Jul 07 07:02:18 PM PDT 24
Peak memory 217784 kb
Host smart-b53f73cc-6c8f-4a51-8d3e-5f1a1136e4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455240355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.1455240355
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.3272993976
Short name T620
Test name
Test status
Simulation time 506600366 ps
CPU time 15.94 seconds
Started Jul 07 07:02:19 PM PDT 24
Finished Jul 07 07:02:35 PM PDT 24
Peak memory 219504 kb
Host smart-89e0f4f8-839e-4c8f-8555-722c3c60a47f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272993976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.3272993976
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.2888057555
Short name T764
Test name
Test status
Simulation time 6331201875 ps
CPU time 17.26 seconds
Started Jul 07 07:02:15 PM PDT 24
Finished Jul 07 07:02:33 PM PDT 24
Peak memory 225556 kb
Host smart-a00c7148-9c44-478e-9c8c-5976b6d5cb10
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888057555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.2888057555
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.2562902090
Short name T843
Test name
Test status
Simulation time 369509761 ps
CPU time 7.93 seconds
Started Jul 07 07:02:16 PM PDT 24
Finished Jul 07 07:02:24 PM PDT 24
Peak memory 217744 kb
Host smart-312ff6ce-77b5-49f8-843a-b514026eba08
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562902090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
2562902090
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.48748015
Short name T283
Test name
Test status
Simulation time 1471016698 ps
CPU time 11.01 seconds
Started Jul 07 07:02:16 PM PDT 24
Finished Jul 07 07:02:27 PM PDT 24
Peak memory 217864 kb
Host smart-182f2bd7-8714-4626-b269-85b459e24556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48748015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.48748015
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.417672606
Short name T835
Test name
Test status
Simulation time 161766682 ps
CPU time 10.56 seconds
Started Jul 07 07:02:15 PM PDT 24
Finished Jul 07 07:02:26 PM PDT 24
Peak memory 217216 kb
Host smart-2ccea0ce-3c19-429c-9c32-5f19f493b6aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417672606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.417672606
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.4097855433
Short name T427
Test name
Test status
Simulation time 4629099899 ps
CPU time 22.59 seconds
Started Jul 07 07:02:14 PM PDT 24
Finished Jul 07 07:02:38 PM PDT 24
Peak memory 250640 kb
Host smart-cd2fabe5-71b4-4050-b1a7-fbb35bb21183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097855433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.4097855433
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.1321132834
Short name T677
Test name
Test status
Simulation time 564694318 ps
CPU time 3.95 seconds
Started Jul 07 07:02:13 PM PDT 24
Finished Jul 07 07:02:17 PM PDT 24
Peak memory 222204 kb
Host smart-a2e74f97-08ec-4037-b21b-fb0c2b9559b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321132834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.1321132834
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.3085338606
Short name T789
Test name
Test status
Simulation time 5420694585 ps
CPU time 98.33 seconds
Started Jul 07 07:02:18 PM PDT 24
Finished Jul 07 07:03:56 PM PDT 24
Peak memory 250608 kb
Host smart-57319de2-3c39-45e7-8a59-5232c63e49e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085338606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.3085338606
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.2590733083
Short name T152
Test name
Test status
Simulation time 23971033594 ps
CPU time 476.07 seconds
Started Jul 07 07:02:18 PM PDT 24
Finished Jul 07 07:10:14 PM PDT 24
Peak memory 364376 kb
Host smart-c098189f-650c-4c52-bf0d-bc90ebcc050d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2590733083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.2590733083
Directory /workspace/32.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.2239696144
Short name T206
Test name
Test status
Simulation time 58980936 ps
CPU time 0.86 seconds
Started Jul 07 07:02:15 PM PDT 24
Finished Jul 07 07:02:16 PM PDT 24
Peak memory 207804 kb
Host smart-33b1fa5b-ecb7-4aa8-8e6b-77f28d93bbf6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239696144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.2239696144
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.3057078572
Short name T639
Test name
Test status
Simulation time 16795062 ps
CPU time 0.92 seconds
Started Jul 07 07:02:20 PM PDT 24
Finished Jul 07 07:02:21 PM PDT 24
Peak memory 208796 kb
Host smart-c77238e7-f896-4570-a14b-f527e97f9b2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057078572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.3057078572
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.12827876
Short name T641
Test name
Test status
Simulation time 715824268 ps
CPU time 20.02 seconds
Started Jul 07 07:02:23 PM PDT 24
Finished Jul 07 07:02:43 PM PDT 24
Peak memory 225520 kb
Host smart-d7ca82c8-beb5-49e0-ad8b-cbe48ef313e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12827876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.12827876
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.1072510810
Short name T766
Test name
Test status
Simulation time 224212426 ps
CPU time 6.08 seconds
Started Jul 07 07:02:23 PM PDT 24
Finished Jul 07 07:02:29 PM PDT 24
Peak memory 216800 kb
Host smart-f5eda644-c8da-43e8-930c-6139465c4e93
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072510810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.1072510810
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.2952478446
Short name T588
Test name
Test status
Simulation time 152064033 ps
CPU time 2.84 seconds
Started Jul 07 07:02:23 PM PDT 24
Finished Jul 07 07:02:26 PM PDT 24
Peak memory 217776 kb
Host smart-cdbc1787-0e2d-409a-a5e1-a31fdcda59a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952478446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.2952478446
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.447125452
Short name T798
Test name
Test status
Simulation time 356556202 ps
CPU time 12.52 seconds
Started Jul 07 07:02:23 PM PDT 24
Finished Jul 07 07:02:36 PM PDT 24
Peak memory 225532 kb
Host smart-fa2f2212-3252-4dcc-8dd9-e93eb752b362
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447125452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.447125452
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.3847028499
Short name T790
Test name
Test status
Simulation time 349994242 ps
CPU time 14.62 seconds
Started Jul 07 07:02:21 PM PDT 24
Finished Jul 07 07:02:36 PM PDT 24
Peak memory 225500 kb
Host smart-65649871-e9d0-4686-b51e-d2d5258bac9f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847028499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.3847028499
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.1909315169
Short name T658
Test name
Test status
Simulation time 1428693402 ps
CPU time 12.85 seconds
Started Jul 07 07:02:21 PM PDT 24
Finished Jul 07 07:02:34 PM PDT 24
Peak memory 217732 kb
Host smart-e4f1ee16-e0c6-4f98-b62d-e6ccb6f0912e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909315169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
1909315169
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.3384887476
Short name T425
Test name
Test status
Simulation time 230966817 ps
CPU time 6.53 seconds
Started Jul 07 07:02:21 PM PDT 24
Finished Jul 07 07:02:28 PM PDT 24
Peak memory 224124 kb
Host smart-6095d2d3-ddbf-48a7-ac07-c61c7835966d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384887476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.3384887476
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.2097432669
Short name T235
Test name
Test status
Simulation time 23991971 ps
CPU time 1.59 seconds
Started Jul 07 07:02:23 PM PDT 24
Finished Jul 07 07:02:25 PM PDT 24
Peak memory 213584 kb
Host smart-90675a47-53a1-4d93-91ff-4ac72db7be09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097432669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.2097432669
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.1629996761
Short name T776
Test name
Test status
Simulation time 484625034 ps
CPU time 23.08 seconds
Started Jul 07 07:02:19 PM PDT 24
Finished Jul 07 07:02:42 PM PDT 24
Peak memory 250532 kb
Host smart-3406d93f-f63f-4a83-88f8-63e835a7dea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629996761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.1629996761
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.578884699
Short name T600
Test name
Test status
Simulation time 187097614 ps
CPU time 9.71 seconds
Started Jul 07 07:02:21 PM PDT 24
Finished Jul 07 07:02:31 PM PDT 24
Peak memory 250532 kb
Host smart-9d327b2c-cd9b-4225-bb07-4c7e55f1566a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578884699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.578884699
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.786755064
Short name T704
Test name
Test status
Simulation time 30148921946 ps
CPU time 170.2 seconds
Started Jul 07 07:02:20 PM PDT 24
Finished Jul 07 07:05:10 PM PDT 24
Peak memory 283344 kb
Host smart-743e4888-1b52-4408-ac5e-953615800b23
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786755064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.786755064
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.13486970
Short name T153
Test name
Test status
Simulation time 63782335232 ps
CPU time 580.77 seconds
Started Jul 07 07:02:22 PM PDT 24
Finished Jul 07 07:12:03 PM PDT 24
Peak memory 288472 kb
Host smart-cfbe73ee-bbfb-4f1c-ba80-7a9140cf9124
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=13486970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.13486970
Directory /workspace/33.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.827068086
Short name T45
Test name
Test status
Simulation time 18274753 ps
CPU time 1 seconds
Started Jul 07 07:02:20 PM PDT 24
Finished Jul 07 07:02:21 PM PDT 24
Peak memory 217216 kb
Host smart-b06646dc-b5fe-4996-939b-d3996d48b11b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827068086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ct
rl_volatile_unlock_smoke.827068086
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.227371567
Short name T198
Test name
Test status
Simulation time 41784484 ps
CPU time 0.99 seconds
Started Jul 07 07:02:28 PM PDT 24
Finished Jul 07 07:02:29 PM PDT 24
Peak memory 208604 kb
Host smart-66fa2fa5-9098-4ff2-8d64-39dd04d001c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227371567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.227371567
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.903928489
Short name T800
Test name
Test status
Simulation time 231831548 ps
CPU time 9.11 seconds
Started Jul 07 07:02:24 PM PDT 24
Finished Jul 07 07:02:33 PM PDT 24
Peak memory 217800 kb
Host smart-e30f9003-f7f1-43a9-911e-13d0d0b1d28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903928489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.903928489
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.1399746048
Short name T97
Test name
Test status
Simulation time 2496624577 ps
CPU time 15.93 seconds
Started Jul 07 07:02:25 PM PDT 24
Finished Jul 07 07:02:41 PM PDT 24
Peak memory 217248 kb
Host smart-d64aced3-ebbe-4820-8bc1-99075be9583f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399746048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.1399746048
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.591075010
Short name T98
Test name
Test status
Simulation time 103334828 ps
CPU time 3.39 seconds
Started Jul 07 07:02:28 PM PDT 24
Finished Jul 07 07:02:32 PM PDT 24
Peak memory 222000 kb
Host smart-eb401763-ba65-4ce2-a171-7f198b187b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591075010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.591075010
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.2110630796
Short name T49
Test name
Test status
Simulation time 885067909 ps
CPU time 15.95 seconds
Started Jul 07 07:02:22 PM PDT 24
Finished Jul 07 07:02:38 PM PDT 24
Peak memory 218436 kb
Host smart-734e9e75-68f7-40f4-9879-19948d0e6b20
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110630796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.2110630796
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.802102774
Short name T12
Test name
Test status
Simulation time 1858547527 ps
CPU time 12.86 seconds
Started Jul 07 07:02:28 PM PDT 24
Finished Jul 07 07:02:41 PM PDT 24
Peak memory 225512 kb
Host smart-2e9495ab-5501-445b-b005-c7095e88c023
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802102774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_di
gest.802102774
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.365359362
Short name T608
Test name
Test status
Simulation time 425062644 ps
CPU time 10.36 seconds
Started Jul 07 07:02:26 PM PDT 24
Finished Jul 07 07:02:37 PM PDT 24
Peak memory 217636 kb
Host smart-58fd2425-6a88-4549-a10f-2e1acb63a134
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365359362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.365359362
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.2943525758
Short name T345
Test name
Test status
Simulation time 375797767 ps
CPU time 9.06 seconds
Started Jul 07 07:02:22 PM PDT 24
Finished Jul 07 07:02:31 PM PDT 24
Peak memory 225540 kb
Host smart-428a6fae-00db-4df1-9216-6842044efcac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943525758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.2943525758
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.580317619
Short name T817
Test name
Test status
Simulation time 23427213 ps
CPU time 1.84 seconds
Started Jul 07 07:02:20 PM PDT 24
Finished Jul 07 07:02:22 PM PDT 24
Peak memory 222580 kb
Host smart-71e6b931-8c5a-4078-af9d-bed998025447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580317619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.580317619
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.760946399
Short name T587
Test name
Test status
Simulation time 354241145 ps
CPU time 29.13 seconds
Started Jul 07 07:02:25 PM PDT 24
Finished Jul 07 07:02:54 PM PDT 24
Peak memory 250536 kb
Host smart-cb13cc56-d94c-40d5-97b0-8007218ca1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760946399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.760946399
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.745344143
Short name T230
Test name
Test status
Simulation time 410310616 ps
CPU time 6.89 seconds
Started Jul 07 07:02:24 PM PDT 24
Finished Jul 07 07:02:31 PM PDT 24
Peak memory 244080 kb
Host smart-69c12c1e-0532-49c5-a36e-f552f7b2375e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745344143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.745344143
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.2673743155
Short name T643
Test name
Test status
Simulation time 7188485186 ps
CPU time 246.56 seconds
Started Jul 07 07:02:24 PM PDT 24
Finished Jul 07 07:06:31 PM PDT 24
Peak memory 267920 kb
Host smart-11528be0-9357-47ec-950a-cde9e552dd60
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673743155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.2673743155
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.2242735539
Short name T560
Test name
Test status
Simulation time 27364868 ps
CPU time 1.16 seconds
Started Jul 07 07:02:24 PM PDT 24
Finished Jul 07 07:02:25 PM PDT 24
Peak memory 217360 kb
Host smart-3ce33488-7ecf-417a-acb7-7c7544333a1b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242735539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.2242735539
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.308148021
Short name T486
Test name
Test status
Simulation time 49553144 ps
CPU time 1.03 seconds
Started Jul 07 07:02:29 PM PDT 24
Finished Jul 07 07:02:31 PM PDT 24
Peak memory 208576 kb
Host smart-d1a63e20-350b-4885-8410-285546f103d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308148021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.308148021
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.2584391169
Short name T222
Test name
Test status
Simulation time 240720035 ps
CPU time 11.69 seconds
Started Jul 07 07:02:26 PM PDT 24
Finished Jul 07 07:02:38 PM PDT 24
Peak memory 217728 kb
Host smart-2256630d-2ac4-4a04-9dbe-1fccd8aec549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584391169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.2584391169
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.694371907
Short name T271
Test name
Test status
Simulation time 608509690 ps
CPU time 4.18 seconds
Started Jul 07 07:02:26 PM PDT 24
Finished Jul 07 07:02:30 PM PDT 24
Peak memory 217100 kb
Host smart-6c523abf-88ea-4b0c-91b6-85ba259bfa2f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694371907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.694371907
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.4105332734
Short name T695
Test name
Test status
Simulation time 187851702 ps
CPU time 2.2 seconds
Started Jul 07 07:02:27 PM PDT 24
Finished Jul 07 07:02:29 PM PDT 24
Peak memory 217768 kb
Host smart-9a96bf8d-c531-448c-bf84-a3f0196db78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105332734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.4105332734
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.50525840
Short name T651
Test name
Test status
Simulation time 2147225673 ps
CPU time 14.34 seconds
Started Jul 07 07:02:26 PM PDT 24
Finished Jul 07 07:02:41 PM PDT 24
Peak memory 225576 kb
Host smart-65a26799-91b2-4938-9134-79090695c9f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50525840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.50525840
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.3920180457
Short name T692
Test name
Test status
Simulation time 380599276 ps
CPU time 11.1 seconds
Started Jul 07 07:02:30 PM PDT 24
Finished Jul 07 07:02:41 PM PDT 24
Peak memory 225520 kb
Host smart-863c9577-1089-49a0-b8aa-6c01f45f8c6b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920180457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.3920180457
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.237129316
Short name T615
Test name
Test status
Simulation time 316734237 ps
CPU time 7.7 seconds
Started Jul 07 07:02:28 PM PDT 24
Finished Jul 07 07:02:36 PM PDT 24
Peak memory 225632 kb
Host smart-774d4d3a-9aa1-418d-93a1-673da3db5d1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237129316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.237129316
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.1615058100
Short name T564
Test name
Test status
Simulation time 6416135872 ps
CPU time 10.39 seconds
Started Jul 07 07:02:26 PM PDT 24
Finished Jul 07 07:02:37 PM PDT 24
Peak memory 225440 kb
Host smart-d969b4ce-f898-4513-a049-7924d685f2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615058100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.1615058100
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.3632267654
Short name T73
Test name
Test status
Simulation time 36419359 ps
CPU time 2.02 seconds
Started Jul 07 07:02:23 PM PDT 24
Finished Jul 07 07:02:25 PM PDT 24
Peak memory 213760 kb
Host smart-1e66d6a0-15a8-458e-90de-7fb6e20d8a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632267654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.3632267654
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.1318871152
Short name T309
Test name
Test status
Simulation time 278921527 ps
CPU time 23.69 seconds
Started Jul 07 07:02:28 PM PDT 24
Finished Jul 07 07:02:52 PM PDT 24
Peak memory 250524 kb
Host smart-e2006f23-f471-4fff-a5e4-81d04c91d1f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318871152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.1318871152
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.957667645
Short name T736
Test name
Test status
Simulation time 66080043 ps
CPU time 7.04 seconds
Started Jul 07 07:02:26 PM PDT 24
Finished Jul 07 07:02:34 PM PDT 24
Peak memory 246820 kb
Host smart-a8045dea-02ee-4875-ac4d-676b0901019b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957667645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.957667645
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.2576029932
Short name T82
Test name
Test status
Simulation time 2721630619 ps
CPU time 64.71 seconds
Started Jul 07 07:02:28 PM PDT 24
Finished Jul 07 07:03:32 PM PDT 24
Peak memory 275756 kb
Host smart-d28804eb-540b-4984-879e-27d8b38480ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576029932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.2576029932
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.3369975966
Short name T85
Test name
Test status
Simulation time 41609734 ps
CPU time 1.06 seconds
Started Jul 07 07:02:25 PM PDT 24
Finished Jul 07 07:02:26 PM PDT 24
Peak memory 211452 kb
Host smart-31e89e3d-d686-498a-a6fd-6f79c3c421f1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369975966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.3369975966
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.2630160130
Short name T518
Test name
Test status
Simulation time 21144796 ps
CPU time 1.16 seconds
Started Jul 07 07:02:34 PM PDT 24
Finished Jul 07 07:02:35 PM PDT 24
Peak memory 208628 kb
Host smart-be7b1551-3080-47ac-a936-d8e4b8a8fe4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630160130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.2630160130
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.274744561
Short name T622
Test name
Test status
Simulation time 558927417 ps
CPU time 15.44 seconds
Started Jul 07 07:02:32 PM PDT 24
Finished Jul 07 07:02:47 PM PDT 24
Peak memory 217796 kb
Host smart-79ca234f-5da5-4f08-8279-511deb4a51ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274744561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.274744561
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.145880712
Short name T5
Test name
Test status
Simulation time 245091924 ps
CPU time 6.99 seconds
Started Jul 07 07:02:34 PM PDT 24
Finished Jul 07 07:02:41 PM PDT 24
Peak memory 216984 kb
Host smart-0fe8a2fb-455c-419e-95d6-d34729fdbf0d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145880712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.145880712
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.1946645635
Short name T565
Test name
Test status
Simulation time 215886059 ps
CPU time 3.31 seconds
Started Jul 07 07:02:30 PM PDT 24
Finished Jul 07 07:02:34 PM PDT 24
Peak memory 221940 kb
Host smart-6d772e0a-6743-427a-b0af-9ee3a0a397d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946645635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.1946645635
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.3798255163
Short name T702
Test name
Test status
Simulation time 377490889 ps
CPU time 18.31 seconds
Started Jul 07 07:02:30 PM PDT 24
Finished Jul 07 07:02:49 PM PDT 24
Peak memory 217864 kb
Host smart-ac8828e6-00e6-4b24-afbd-15c3da42b26b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798255163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.3798255163
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.4236462286
Short name T816
Test name
Test status
Simulation time 2715858491 ps
CPU time 15.13 seconds
Started Jul 07 07:02:29 PM PDT 24
Finished Jul 07 07:02:45 PM PDT 24
Peak memory 225584 kb
Host smart-7387d53b-7ebd-46da-a946-f4e80c137280
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236462286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.4236462286
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.1846902864
Short name T712
Test name
Test status
Simulation time 3616950763 ps
CPU time 8.8 seconds
Started Jul 07 07:02:34 PM PDT 24
Finished Jul 07 07:02:43 PM PDT 24
Peak memory 218044 kb
Host smart-3b3c68b5-723e-4755-878c-3baba494e661
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846902864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
1846902864
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.3569261745
Short name T744
Test name
Test status
Simulation time 191546089 ps
CPU time 6.25 seconds
Started Jul 07 07:02:30 PM PDT 24
Finished Jul 07 07:02:37 PM PDT 24
Peak memory 224592 kb
Host smart-440a2660-22fe-4cd5-a5f7-f240a5091542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569261745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.3569261745
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.1785751231
Short name T369
Test name
Test status
Simulation time 143171319 ps
CPU time 4.72 seconds
Started Jul 07 07:02:30 PM PDT 24
Finished Jul 07 07:02:35 PM PDT 24
Peak memory 217284 kb
Host smart-39bbcd88-76ca-4cf4-b520-7ff74181fdaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785751231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.1785751231
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.1408619821
Short name T551
Test name
Test status
Simulation time 647860372 ps
CPU time 25.36 seconds
Started Jul 07 07:02:32 PM PDT 24
Finished Jul 07 07:02:57 PM PDT 24
Peak memory 250524 kb
Host smart-bb0e1304-e846-42c7-9269-a32f9f68e543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408619821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.1408619821
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.2157363425
Short name T314
Test name
Test status
Simulation time 78659908 ps
CPU time 9.55 seconds
Started Jul 07 07:02:31 PM PDT 24
Finished Jul 07 07:02:41 PM PDT 24
Peak memory 250536 kb
Host smart-b944f3d0-ff4d-4846-8ed2-7eb2df15bfff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157363425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.2157363425
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.2916584616
Short name T791
Test name
Test status
Simulation time 6678134082 ps
CPU time 57.06 seconds
Started Jul 07 07:02:34 PM PDT 24
Finished Jul 07 07:03:31 PM PDT 24
Peak memory 252860 kb
Host smart-3927f66a-42ba-4e52-bf3b-ab7967d2c801
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916584616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.2916584616
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.3762821155
Short name T469
Test name
Test status
Simulation time 79596224387 ps
CPU time 539.38 seconds
Started Jul 07 07:02:33 PM PDT 24
Finished Jul 07 07:11:33 PM PDT 24
Peak memory 421672 kb
Host smart-1289aa14-1dbe-4d40-9942-d02dbe463c5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3762821155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.3762821155
Directory /workspace/36.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.2535367764
Short name T473
Test name
Test status
Simulation time 15456409 ps
CPU time 1.19 seconds
Started Jul 07 07:02:30 PM PDT 24
Finished Jul 07 07:02:31 PM PDT 24
Peak memory 211412 kb
Host smart-422dc4bb-0c97-4e1a-b5ca-fb7df0d1227c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535367764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.2535367764
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.2922998790
Short name T412
Test name
Test status
Simulation time 103493730 ps
CPU time 1.03 seconds
Started Jul 07 07:02:41 PM PDT 24
Finished Jul 07 07:02:43 PM PDT 24
Peak memory 208548 kb
Host smart-64bf974e-2a60-4edc-8090-269c03824d4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922998790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.2922998790
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.4163894133
Short name T586
Test name
Test status
Simulation time 334638801 ps
CPU time 15.78 seconds
Started Jul 07 07:02:35 PM PDT 24
Finished Jul 07 07:02:51 PM PDT 24
Peak memory 217728 kb
Host smart-e45d5180-53a2-4fb7-8a7b-3cca7e4b6310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163894133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.4163894133
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.1717795486
Short name T690
Test name
Test status
Simulation time 314295450 ps
CPU time 8.27 seconds
Started Jul 07 07:02:37 PM PDT 24
Finished Jul 07 07:02:45 PM PDT 24
Peak memory 216676 kb
Host smart-a3c4abe5-13b2-4e6e-9b0c-7e309d0cb777
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717795486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.1717795486
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.3074962905
Short name T720
Test name
Test status
Simulation time 29539409 ps
CPU time 1.83 seconds
Started Jul 07 07:02:33 PM PDT 24
Finished Jul 07 07:02:35 PM PDT 24
Peak memory 221672 kb
Host smart-d49b4fdf-6bdb-4957-83a9-4dfb89b46923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074962905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.3074962905
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.2377525568
Short name T537
Test name
Test status
Simulation time 242318051 ps
CPU time 12.96 seconds
Started Jul 07 07:02:33 PM PDT 24
Finished Jul 07 07:02:47 PM PDT 24
Peak memory 218616 kb
Host smart-12b194e9-e0ca-4f77-b88c-2d44c4611405
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377525568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.2377525568
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.1096947727
Short name T625
Test name
Test status
Simulation time 1563701639 ps
CPU time 10.86 seconds
Started Jul 07 07:02:36 PM PDT 24
Finished Jul 07 07:02:47 PM PDT 24
Peak memory 225520 kb
Host smart-1d67484a-f7c2-4bfa-906d-5ec845e0abfb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096947727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.1096947727
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.3506145164
Short name T527
Test name
Test status
Simulation time 683427671 ps
CPU time 12.42 seconds
Started Jul 07 07:02:34 PM PDT 24
Finished Jul 07 07:02:47 PM PDT 24
Peak memory 225512 kb
Host smart-424e4445-8e48-4705-bce6-807b3a2d567f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506145164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
3506145164
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.4223259065
Short name T417
Test name
Test status
Simulation time 232969739 ps
CPU time 10.18 seconds
Started Jul 07 07:02:35 PM PDT 24
Finished Jul 07 07:02:46 PM PDT 24
Peak memory 225560 kb
Host smart-810448c1-d939-449d-9eb6-f3d298aae2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223259065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.4223259065
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.422986240
Short name T602
Test name
Test status
Simulation time 55424484 ps
CPU time 2.22 seconds
Started Jul 07 07:02:29 PM PDT 24
Finished Jul 07 07:02:32 PM PDT 24
Peak memory 217192 kb
Host smart-6ee5617c-db48-4233-9b85-61b0ce5c584c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422986240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.422986240
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.1190103429
Short name T254
Test name
Test status
Simulation time 1396492788 ps
CPU time 26.6 seconds
Started Jul 07 07:02:34 PM PDT 24
Finished Jul 07 07:03:01 PM PDT 24
Peak memory 250532 kb
Host smart-3b54babc-91bd-47cd-97f1-b9a5c2af54c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190103429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.1190103429
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.1613227005
Short name T555
Test name
Test status
Simulation time 191576202 ps
CPU time 3.55 seconds
Started Jul 07 07:02:36 PM PDT 24
Finished Jul 07 07:02:40 PM PDT 24
Peak memory 225940 kb
Host smart-1154e308-fbbf-4069-b2b1-2ad0eb631681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613227005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.1613227005
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.2591443851
Short name T654
Test name
Test status
Simulation time 7466872002 ps
CPU time 88.22 seconds
Started Jul 07 07:02:37 PM PDT 24
Finished Jul 07 07:04:05 PM PDT 24
Peak memory 275256 kb
Host smart-88ff4e98-81ee-453b-8397-5921bbdd6e9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591443851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.2591443851
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.3970283973
Short name T629
Test name
Test status
Simulation time 15473649 ps
CPU time 1 seconds
Started Jul 07 07:02:33 PM PDT 24
Finished Jul 07 07:02:34 PM PDT 24
Peak memory 211416 kb
Host smart-f29f42a4-d6cb-482c-a084-4c6ab833f6b3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970283973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.3970283973
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.1522722200
Short name T280
Test name
Test status
Simulation time 14972192 ps
CPU time 0.9 seconds
Started Jul 07 07:02:44 PM PDT 24
Finished Jul 07 07:02:45 PM PDT 24
Peak memory 208392 kb
Host smart-0902b240-7e51-4b45-9f8f-9d5e40331406
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522722200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.1522722200
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.2061546763
Short name T378
Test name
Test status
Simulation time 1115672695 ps
CPU time 11.72 seconds
Started Jul 07 07:02:38 PM PDT 24
Finished Jul 07 07:02:50 PM PDT 24
Peak memory 217876 kb
Host smart-ff2b1297-54ca-4bcc-ab2a-5fd2de87d483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061546763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.2061546763
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.2154689785
Short name T567
Test name
Test status
Simulation time 458745494 ps
CPU time 1.21 seconds
Started Jul 07 07:02:39 PM PDT 24
Finished Jul 07 07:02:41 PM PDT 24
Peak memory 217444 kb
Host smart-c3d7600a-e2c5-4041-be74-fa9258a2e338
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154689785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.2154689785
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.2508509030
Short name T628
Test name
Test status
Simulation time 57380617 ps
CPU time 2.62 seconds
Started Jul 07 07:02:38 PM PDT 24
Finished Jul 07 07:02:40 PM PDT 24
Peak memory 217780 kb
Host smart-5d917c0f-34eb-4ccd-9bef-b8635c7ad007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508509030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.2508509030
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.734105613
Short name T353
Test name
Test status
Simulation time 252424433 ps
CPU time 12.98 seconds
Started Jul 07 07:02:37 PM PDT 24
Finished Jul 07 07:02:50 PM PDT 24
Peak memory 217776 kb
Host smart-850c12e2-a647-4a2e-a725-5929ec86c6c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734105613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.734105613
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.4246757395
Short name T525
Test name
Test status
Simulation time 251800516 ps
CPU time 12.16 seconds
Started Jul 07 07:02:42 PM PDT 24
Finished Jul 07 07:02:55 PM PDT 24
Peak memory 225516 kb
Host smart-268fe159-8ca1-4c39-ad45-4ec5aaf2dd78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246757395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.4246757395
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.1412059956
Short name T823
Test name
Test status
Simulation time 322361897 ps
CPU time 9.24 seconds
Started Jul 07 07:02:39 PM PDT 24
Finished Jul 07 07:02:48 PM PDT 24
Peak memory 217724 kb
Host smart-f4f00cb6-0d6a-4998-8469-d0565b4030ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412059956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
1412059956
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.1405916323
Short name T402
Test name
Test status
Simulation time 451158192 ps
CPU time 16.06 seconds
Started Jul 07 07:02:40 PM PDT 24
Finished Jul 07 07:02:56 PM PDT 24
Peak memory 217860 kb
Host smart-d9cc3eb0-22bc-4e64-907c-61177998f6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405916323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.1405916323
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.567577527
Short name T450
Test name
Test status
Simulation time 102644743 ps
CPU time 4.86 seconds
Started Jul 07 07:02:39 PM PDT 24
Finished Jul 07 07:02:44 PM PDT 24
Peak memory 217196 kb
Host smart-134075e2-3697-496a-939a-109cfae608db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567577527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.567577527
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.1628431813
Short name T265
Test name
Test status
Simulation time 1076022535 ps
CPU time 20.36 seconds
Started Jul 07 07:02:38 PM PDT 24
Finished Jul 07 07:02:58 PM PDT 24
Peak memory 250544 kb
Host smart-0579f967-fe89-4975-883e-e9d58d5ae66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628431813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.1628431813
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.2211522165
Short name T485
Test name
Test status
Simulation time 152526634 ps
CPU time 4.27 seconds
Started Jul 07 07:02:36 PM PDT 24
Finished Jul 07 07:02:40 PM PDT 24
Peak memory 222052 kb
Host smart-8e837441-a047-4d04-9987-ac2e2a0bcee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211522165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.2211522165
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.1612820685
Short name T458
Test name
Test status
Simulation time 19855094160 ps
CPU time 176.84 seconds
Started Jul 07 07:02:42 PM PDT 24
Finished Jul 07 07:05:39 PM PDT 24
Peak memory 283372 kb
Host smart-caabd0cf-9c7c-49e6-acdc-2fabc277ff35
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612820685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.1612820685
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.4199140474
Short name T154
Test name
Test status
Simulation time 45890620316 ps
CPU time 370.33 seconds
Started Jul 07 07:02:41 PM PDT 24
Finished Jul 07 07:08:52 PM PDT 24
Peak memory 314968 kb
Host smart-45b04004-9378-477f-93be-350997e24389
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4199140474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.4199140474
Directory /workspace/38.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.214117453
Short name T236
Test name
Test status
Simulation time 39677727 ps
CPU time 0.79 seconds
Started Jul 07 07:02:39 PM PDT 24
Finished Jul 07 07:02:40 PM PDT 24
Peak memory 208232 kb
Host smart-c2efd513-26a0-4c94-a698-6e18a7096db7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214117453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ct
rl_volatile_unlock_smoke.214117453
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.1984030731
Short name T761
Test name
Test status
Simulation time 15003921 ps
CPU time 0.93 seconds
Started Jul 07 07:02:45 PM PDT 24
Finished Jul 07 07:02:46 PM PDT 24
Peak memory 208456 kb
Host smart-0b6f5dee-9ecf-44d2-bdb1-5d9498e7c8c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984030731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.1984030731
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.2339569897
Short name T228
Test name
Test status
Simulation time 2204878662 ps
CPU time 8.17 seconds
Started Jul 07 07:02:44 PM PDT 24
Finished Jul 07 07:02:52 PM PDT 24
Peak memory 225892 kb
Host smart-2b26c76d-b504-4143-b9bd-0654d939ee5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339569897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.2339569897
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.4003878879
Short name T23
Test name
Test status
Simulation time 879835375 ps
CPU time 20.38 seconds
Started Jul 07 07:02:47 PM PDT 24
Finished Jul 07 07:03:08 PM PDT 24
Peak memory 216952 kb
Host smart-9a35894a-8406-441c-a1ec-98cc8031b137
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003878879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.4003878879
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.83689843
Short name T749
Test name
Test status
Simulation time 31107541 ps
CPU time 2.2 seconds
Started Jul 07 07:02:42 PM PDT 24
Finished Jul 07 07:02:45 PM PDT 24
Peak memory 221684 kb
Host smart-2c506afc-e9d2-4b82-80c7-d59688ced44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83689843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.83689843
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.3200933617
Short name T513
Test name
Test status
Simulation time 673158304 ps
CPU time 15.38 seconds
Started Jul 07 07:02:45 PM PDT 24
Finished Jul 07 07:03:01 PM PDT 24
Peak memory 225552 kb
Host smart-40196730-c60e-4e97-a2ba-a8ed4ad2d6b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200933617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.3200933617
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.148856927
Short name T498
Test name
Test status
Simulation time 1844712097 ps
CPU time 16.55 seconds
Started Jul 07 07:02:49 PM PDT 24
Finished Jul 07 07:03:05 PM PDT 24
Peak memory 225452 kb
Host smart-5210c28a-688b-4caa-a19a-eb83ccc14ad2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148856927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_di
gest.148856927
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.68219064
Short name T519
Test name
Test status
Simulation time 1775237453 ps
CPU time 9.49 seconds
Started Jul 07 07:02:49 PM PDT 24
Finished Jul 07 07:02:59 PM PDT 24
Peak memory 217708 kb
Host smart-71c9f9bb-8aed-4841-bf5a-fe3e5451e2bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68219064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.68219064
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.4017069688
Short name T771
Test name
Test status
Simulation time 1455665956 ps
CPU time 9.68 seconds
Started Jul 07 07:02:48 PM PDT 24
Finished Jul 07 07:02:58 PM PDT 24
Peak memory 225564 kb
Host smart-0c6d69b1-e3a2-4665-8669-20428dff7cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017069688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.4017069688
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.3496116885
Short name T297
Test name
Test status
Simulation time 40729267 ps
CPU time 2.99 seconds
Started Jul 07 07:02:45 PM PDT 24
Finished Jul 07 07:02:48 PM PDT 24
Peak memory 214080 kb
Host smart-49f69ca3-b99a-4670-9482-714d9fc9f7b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496116885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.3496116885
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.3008426356
Short name T476
Test name
Test status
Simulation time 255572983 ps
CPU time 30.05 seconds
Started Jul 07 07:02:43 PM PDT 24
Finished Jul 07 07:03:13 PM PDT 24
Peak memory 247196 kb
Host smart-3c3fd1e9-b94f-440d-bcf2-68f1743257dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008426356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.3008426356
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.1402758550
Short name T617
Test name
Test status
Simulation time 121241961 ps
CPU time 9.4 seconds
Started Jul 07 07:02:42 PM PDT 24
Finished Jul 07 07:02:51 PM PDT 24
Peak memory 250548 kb
Host smart-abaa330a-eb9a-45d8-bc6f-57c4231be318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402758550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.1402758550
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.2922990288
Short name T829
Test name
Test status
Simulation time 4081294254 ps
CPU time 104.34 seconds
Started Jul 07 07:02:46 PM PDT 24
Finished Jul 07 07:04:30 PM PDT 24
Peak memory 279068 kb
Host smart-749dfe15-b9cf-436f-9efc-490ccc67f022
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922990288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.2922990288
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.1643418582
Short name T511
Test name
Test status
Simulation time 37196935 ps
CPU time 0.92 seconds
Started Jul 07 07:02:44 PM PDT 24
Finished Jul 07 07:02:45 PM PDT 24
Peak memory 211336 kb
Host smart-9568b4ef-ba31-4fae-b012-32dd91826474
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643418582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.1643418582
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.3061780320
Short name T665
Test name
Test status
Simulation time 31983390 ps
CPU time 0.95 seconds
Started Jul 07 06:59:40 PM PDT 24
Finished Jul 07 06:59:41 PM PDT 24
Peak memory 208512 kb
Host smart-d1bc5342-c013-439a-ade0-25cceafd2fab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061780320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.3061780320
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.3214745248
Short name T777
Test name
Test status
Simulation time 386840886 ps
CPU time 11.25 seconds
Started Jul 07 06:59:35 PM PDT 24
Finished Jul 07 06:59:46 PM PDT 24
Peak memory 217764 kb
Host smart-f398f6fa-0cff-4ecb-a037-d48fcb11e44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214745248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.3214745248
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.231918569
Short name T685
Test name
Test status
Simulation time 1244364049 ps
CPU time 9.17 seconds
Started Jul 07 06:59:43 PM PDT 24
Finished Jul 07 06:59:52 PM PDT 24
Peak memory 217004 kb
Host smart-d5b7d5c5-aa44-4933-81f6-2bcc57168a7b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231918569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.231918569
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.659402132
Short name T508
Test name
Test status
Simulation time 4173558227 ps
CPU time 34.08 seconds
Started Jul 07 06:59:38 PM PDT 24
Finished Jul 07 07:00:13 PM PDT 24
Peak memory 218412 kb
Host smart-8336d699-5866-4a64-94e7-7d86ec46f4c5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659402132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_err
ors.659402132
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.3080512743
Short name T661
Test name
Test status
Simulation time 379446439 ps
CPU time 5.83 seconds
Started Jul 07 06:59:41 PM PDT 24
Finished Jul 07 06:59:47 PM PDT 24
Peak memory 217312 kb
Host smart-a81dcfda-91be-4520-b0af-83277ba2929d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080512743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.3
080512743
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.4080304222
Short name T642
Test name
Test status
Simulation time 597098059 ps
CPU time 3.61 seconds
Started Jul 07 06:59:38 PM PDT 24
Finished Jul 07 06:59:42 PM PDT 24
Peak memory 221252 kb
Host smart-12dd6c0a-eec0-4461-a14b-e4eaeb0ba15d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080304222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.4080304222
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.4280118332
Short name T722
Test name
Test status
Simulation time 1186606682 ps
CPU time 16.49 seconds
Started Jul 07 06:59:41 PM PDT 24
Finished Jul 07 06:59:58 PM PDT 24
Peak memory 217136 kb
Host smart-4f7dfa9d-009e-4f2d-abdd-be2b1d57f0a3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280118332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.4280118332
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.3747676833
Short name T557
Test name
Test status
Simulation time 176117363 ps
CPU time 5.87 seconds
Started Jul 07 06:59:38 PM PDT 24
Finished Jul 07 06:59:44 PM PDT 24
Peak memory 217152 kb
Host smart-73086eb6-2fb2-419f-9a85-946d51191170
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747676833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
3747676833
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.1723586616
Short name T250
Test name
Test status
Simulation time 12980053260 ps
CPU time 65.27 seconds
Started Jul 07 06:59:38 PM PDT 24
Finished Jul 07 07:00:43 PM PDT 24
Peak memory 268112 kb
Host smart-1e8f7679-95d7-47df-bf08-0de4bb3ce5f2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723586616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.1723586616
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.2171508897
Short name T713
Test name
Test status
Simulation time 664870996 ps
CPU time 10.67 seconds
Started Jul 07 06:59:37 PM PDT 24
Finished Jul 07 06:59:48 PM PDT 24
Peak memory 223544 kb
Host smart-c41bcfa5-cfa7-476b-bff3-3a3481eae937
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171508897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.2171508897
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.4261508567
Short name T767
Test name
Test status
Simulation time 61540147 ps
CPU time 2.58 seconds
Started Jul 07 06:59:39 PM PDT 24
Finished Jul 07 06:59:42 PM PDT 24
Peak memory 217796 kb
Host smart-9c465b0c-71d2-40c3-a97f-3546642aeee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261508567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.4261508567
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.2641883448
Short name T649
Test name
Test status
Simulation time 1855418154 ps
CPU time 10.66 seconds
Started Jul 07 06:59:33 PM PDT 24
Finished Jul 07 06:59:44 PM PDT 24
Peak memory 214252 kb
Host smart-71622f58-a14b-4e2d-8084-3ace55828b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641883448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.2641883448
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.915986192
Short name T61
Test name
Test status
Simulation time 928647266 ps
CPU time 24.3 seconds
Started Jul 07 06:59:40 PM PDT 24
Finished Jul 07 07:00:05 PM PDT 24
Peak memory 281496 kb
Host smart-13a762e8-d562-461f-a096-f7025015e389
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915986192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.915986192
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.1965336694
Short name T446
Test name
Test status
Simulation time 4912669219 ps
CPU time 10.73 seconds
Started Jul 07 06:59:45 PM PDT 24
Finished Jul 07 06:59:56 PM PDT 24
Peak memory 218880 kb
Host smart-7fa99a34-2022-44db-b781-931f5eb4a07f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965336694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.1965336694
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.3341760132
Short name T407
Test name
Test status
Simulation time 1938855493 ps
CPU time 16.99 seconds
Started Jul 07 06:59:44 PM PDT 24
Finished Jul 07 07:00:01 PM PDT 24
Peak memory 225516 kb
Host smart-3b837db3-2758-4afb-bf3c-afe649537a24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341760132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.3341760132
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.1383893317
Short name T439
Test name
Test status
Simulation time 1458364472 ps
CPU time 10.54 seconds
Started Jul 07 06:59:40 PM PDT 24
Finished Jul 07 06:59:51 PM PDT 24
Peak memory 217724 kb
Host smart-7debfc7d-0a59-43c1-8c9c-180ed10113f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383893317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.1
383893317
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.3964937678
Short name T272
Test name
Test status
Simulation time 414781754 ps
CPU time 14.96 seconds
Started Jul 07 06:59:36 PM PDT 24
Finished Jul 07 06:59:51 PM PDT 24
Peak memory 217872 kb
Host smart-f739b042-3943-4c6f-b433-5c97d0b63880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964937678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.3964937678
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.1342843625
Short name T501
Test name
Test status
Simulation time 28723631 ps
CPU time 1.59 seconds
Started Jul 07 06:59:34 PM PDT 24
Finished Jul 07 06:59:36 PM PDT 24
Peak memory 213460 kb
Host smart-7ab71803-5f74-47ee-8699-35a1bc04a62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342843625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.1342843625
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.53963938
Short name T319
Test name
Test status
Simulation time 299677013 ps
CPU time 28.97 seconds
Started Jul 07 06:59:36 PM PDT 24
Finished Jul 07 07:00:05 PM PDT 24
Peak memory 250784 kb
Host smart-982cefbd-2599-462c-b446-47371f172ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53963938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.53963938
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.200689064
Short name T656
Test name
Test status
Simulation time 53451519 ps
CPU time 6.79 seconds
Started Jul 07 06:59:36 PM PDT 24
Finished Jul 07 06:59:43 PM PDT 24
Peak memory 242592 kb
Host smart-ef20f06d-79e2-4747-8105-014ec926f02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200689064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.200689064
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.1357979615
Short name T809
Test name
Test status
Simulation time 5692423675 ps
CPU time 181.66 seconds
Started Jul 07 06:59:40 PM PDT 24
Finished Jul 07 07:02:42 PM PDT 24
Peak memory 250568 kb
Host smart-d7d448bc-8f7c-4bf6-8b51-12cd74eff753
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357979615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.1357979615
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.800779285
Short name T336
Test name
Test status
Simulation time 69015911 ps
CPU time 1.05 seconds
Started Jul 07 06:59:36 PM PDT 24
Finished Jul 07 06:59:38 PM PDT 24
Peak memory 212380 kb
Host smart-88e8a739-2c80-4df0-a987-297f9b80d7eb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800779285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctr
l_volatile_unlock_smoke.800779285
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.1408910791
Short name T724
Test name
Test status
Simulation time 62339727 ps
CPU time 1.09 seconds
Started Jul 07 07:02:49 PM PDT 24
Finished Jul 07 07:02:51 PM PDT 24
Peak memory 208524 kb
Host smart-ba10f3c4-f0e8-4bb2-8241-e7e8159dd1a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408910791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.1408910791
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.3684453725
Short name T168
Test name
Test status
Simulation time 1549514817 ps
CPU time 22.41 seconds
Started Jul 07 07:02:47 PM PDT 24
Finished Jul 07 07:03:09 PM PDT 24
Peak memory 217772 kb
Host smart-b5067524-59d4-4043-92c6-890c6dd6260c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684453725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.3684453725
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.2709303494
Short name T782
Test name
Test status
Simulation time 137076107 ps
CPU time 2.58 seconds
Started Jul 07 07:02:47 PM PDT 24
Finished Jul 07 07:02:50 PM PDT 24
Peak memory 217304 kb
Host smart-c58acfa7-f291-4509-afae-25de2a941494
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709303494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.2709303494
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.3521048196
Short name T377
Test name
Test status
Simulation time 119798868 ps
CPU time 2.34 seconds
Started Jul 07 07:02:44 PM PDT 24
Finished Jul 07 07:02:47 PM PDT 24
Peak memory 217776 kb
Host smart-d0dab03b-a0fb-4a83-b1f3-40802447b5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521048196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.3521048196
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.931223995
Short name T372
Test name
Test status
Simulation time 670420971 ps
CPU time 13.78 seconds
Started Jul 07 07:02:50 PM PDT 24
Finished Jul 07 07:03:04 PM PDT 24
Peak memory 225508 kb
Host smart-68788943-64a1-41c9-a97c-46e1e622f82e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931223995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_di
gest.931223995
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.164461559
Short name T796
Test name
Test status
Simulation time 743540129 ps
CPU time 13.15 seconds
Started Jul 07 07:02:49 PM PDT 24
Finished Jul 07 07:03:02 PM PDT 24
Peak memory 225440 kb
Host smart-cf220dd5-7f48-4f50-8494-49103f790be0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164461559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.164461559
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.2224471938
Short name T644
Test name
Test status
Simulation time 283705776 ps
CPU time 12.12 seconds
Started Jul 07 07:02:48 PM PDT 24
Finished Jul 07 07:03:00 PM PDT 24
Peak memory 225632 kb
Host smart-5418695e-5ae6-4608-a945-96d91a23e537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224471938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.2224471938
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.482776478
Short name T343
Test name
Test status
Simulation time 147638811 ps
CPU time 8.44 seconds
Started Jul 07 07:02:45 PM PDT 24
Finished Jul 07 07:02:54 PM PDT 24
Peak memory 217228 kb
Host smart-ed41df0f-6527-483e-93b8-143158689e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482776478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.482776478
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.2450325615
Short name T763
Test name
Test status
Simulation time 185265267 ps
CPU time 18.87 seconds
Started Jul 07 07:02:45 PM PDT 24
Finished Jul 07 07:03:05 PM PDT 24
Peak memory 250624 kb
Host smart-76e9e5de-819b-43e0-ab22-120219f06589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450325615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.2450325615
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.4265448849
Short name T243
Test name
Test status
Simulation time 319318663 ps
CPU time 4.16 seconds
Started Jul 07 07:02:49 PM PDT 24
Finished Jul 07 07:02:54 PM PDT 24
Peak memory 217756 kb
Host smart-cb23bf45-7876-4c32-864c-2e82ab8b5771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265448849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.4265448849
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.455418045
Short name T538
Test name
Test status
Simulation time 13724947361 ps
CPU time 111.11 seconds
Started Jul 07 07:02:51 PM PDT 24
Finished Jul 07 07:04:43 PM PDT 24
Peak memory 267240 kb
Host smart-8851e6e3-52e0-45dd-91d8-3aa74673a45a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455418045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.455418045
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.6444408
Short name T760
Test name
Test status
Simulation time 41335395453 ps
CPU time 744.28 seconds
Started Jul 07 07:02:50 PM PDT 24
Finished Jul 07 07:15:14 PM PDT 24
Peak memory 446856 kb
Host smart-69b7ac92-dd3b-4792-9820-12c54fca74b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=6444408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all_with_rand_reset.6444408
Directory /workspace/40.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.1809257960
Short name T38
Test name
Test status
Simulation time 20096288 ps
CPU time 0.74 seconds
Started Jul 07 07:02:46 PM PDT 24
Finished Jul 07 07:02:47 PM PDT 24
Peak memory 208232 kb
Host smart-f8ed4ce9-1fea-4216-9ca7-b2c2d30f2696
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809257960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.1809257960
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.4284530070
Short name T819
Test name
Test status
Simulation time 17689942 ps
CPU time 0.91 seconds
Started Jul 07 07:02:54 PM PDT 24
Finished Jul 07 07:02:55 PM PDT 24
Peak memory 208564 kb
Host smart-fa8b6d38-d29c-4229-8245-706e52a1d5a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284530070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.4284530070
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.2384542070
Short name T741
Test name
Test status
Simulation time 4374704691 ps
CPU time 15.4 seconds
Started Jul 07 07:02:50 PM PDT 24
Finished Jul 07 07:03:05 PM PDT 24
Peak memory 218476 kb
Host smart-0c6f4dd2-4467-40b7-9370-8f9b1f57dbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384542070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.2384542070
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.546408797
Short name T783
Test name
Test status
Simulation time 1042041601 ps
CPU time 3 seconds
Started Jul 07 07:02:48 PM PDT 24
Finished Jul 07 07:02:51 PM PDT 24
Peak memory 217316 kb
Host smart-9701fe3d-88a7-4378-8f44-0e82037eac53
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546408797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.546408797
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.75867300
Short name T277
Test name
Test status
Simulation time 215122042 ps
CPU time 3.44 seconds
Started Jul 07 07:02:52 PM PDT 24
Finished Jul 07 07:02:55 PM PDT 24
Peak memory 217712 kb
Host smart-44868712-102b-426b-96a0-49ba5bbc468c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75867300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.75867300
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.3671598153
Short name T627
Test name
Test status
Simulation time 376008353 ps
CPU time 14.23 seconds
Started Jul 07 07:02:51 PM PDT 24
Finished Jul 07 07:03:05 PM PDT 24
Peak memory 225580 kb
Host smart-ecc8fc80-56ad-462b-a341-39bcf540617d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671598153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.3671598153
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.945194337
Short name T101
Test name
Test status
Simulation time 249262918 ps
CPU time 10.98 seconds
Started Jul 07 07:02:49 PM PDT 24
Finished Jul 07 07:03:01 PM PDT 24
Peak memory 225508 kb
Host smart-9b48a8be-ad77-4db4-8206-0cc958b279e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945194337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_di
gest.945194337
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.523983242
Short name T293
Test name
Test status
Simulation time 289809340 ps
CPU time 9.98 seconds
Started Jul 07 07:02:51 PM PDT 24
Finished Jul 07 07:03:01 PM PDT 24
Peak memory 217728 kb
Host smart-ca6d7e8a-631c-43ea-9d28-34f7221f5fd5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523983242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.523983242
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.119203024
Short name T333
Test name
Test status
Simulation time 1435701055 ps
CPU time 8.11 seconds
Started Jul 07 07:02:50 PM PDT 24
Finished Jul 07 07:02:59 PM PDT 24
Peak memory 224312 kb
Host smart-ccf7fb92-0951-45fd-8efd-85d909384d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119203024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.119203024
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.3073949784
Short name T76
Test name
Test status
Simulation time 19708433 ps
CPU time 1.39 seconds
Started Jul 07 07:02:52 PM PDT 24
Finished Jul 07 07:02:53 PM PDT 24
Peak memory 213100 kb
Host smart-39982deb-6d14-46f4-9098-6e07e4c6116e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073949784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.3073949784
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.1119878707
Short name T415
Test name
Test status
Simulation time 854157684 ps
CPU time 28.45 seconds
Started Jul 07 07:02:50 PM PDT 24
Finished Jul 07 07:03:19 PM PDT 24
Peak memory 245676 kb
Host smart-217ae073-5fec-4b39-af7f-ecd89f6bcf59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119878707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.1119878707
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.62092440
Short name T539
Test name
Test status
Simulation time 194221064 ps
CPU time 7.29 seconds
Started Jul 07 07:02:53 PM PDT 24
Finished Jul 07 07:03:00 PM PDT 24
Peak memory 217784 kb
Host smart-d4f632ed-8e54-483c-900a-e050e3db7a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62092440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.62092440
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.576914453
Short name T794
Test name
Test status
Simulation time 42490766370 ps
CPU time 253.32 seconds
Started Jul 07 07:02:47 PM PDT 24
Finished Jul 07 07:07:01 PM PDT 24
Peak memory 273748 kb
Host smart-68c3303b-535d-482f-8965-f23e2c1451b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576914453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.576914453
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.221415275
Short name T406
Test name
Test status
Simulation time 31881695 ps
CPU time 0.94 seconds
Started Jul 07 07:02:51 PM PDT 24
Finished Jul 07 07:02:52 PM PDT 24
Peak memory 211396 kb
Host smart-7ae23e56-f817-4cba-bbc1-48d5c74d3054
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221415275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ct
rl_volatile_unlock_smoke.221415275
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.2973422866
Short name T594
Test name
Test status
Simulation time 38972709 ps
CPU time 0.94 seconds
Started Jul 07 07:02:57 PM PDT 24
Finished Jul 07 07:02:58 PM PDT 24
Peak memory 208508 kb
Host smart-91143207-b2dd-45f5-820a-ef8d10a4b31f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973422866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.2973422866
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.4124053286
Short name T455
Test name
Test status
Simulation time 599316878 ps
CPU time 14.33 seconds
Started Jul 07 07:02:53 PM PDT 24
Finished Jul 07 07:03:08 PM PDT 24
Peak memory 217796 kb
Host smart-b928c67a-7fb5-4bab-8044-c2f627e04bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124053286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.4124053286
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.3253753365
Short name T26
Test name
Test status
Simulation time 335642760 ps
CPU time 2.59 seconds
Started Jul 07 07:02:54 PM PDT 24
Finished Jul 07 07:02:57 PM PDT 24
Peak memory 217444 kb
Host smart-4441155c-6fa5-476f-bbac-81da19012081
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253753365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.3253753365
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.373911107
Short name T520
Test name
Test status
Simulation time 151014264 ps
CPU time 3.97 seconds
Started Jul 07 07:02:57 PM PDT 24
Finished Jul 07 07:03:01 PM PDT 24
Peak memory 217760 kb
Host smart-be0ec269-fd52-4baa-8460-ed1fd575d188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373911107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.373911107
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.2014137151
Short name T515
Test name
Test status
Simulation time 240613070 ps
CPU time 9.38 seconds
Started Jul 07 07:02:53 PM PDT 24
Finished Jul 07 07:03:03 PM PDT 24
Peak memory 217700 kb
Host smart-815bc5c0-3d76-4c7f-9049-d569d30879ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014137151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.2014137151
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.1491537406
Short name T573
Test name
Test status
Simulation time 2591722603 ps
CPU time 11.22 seconds
Started Jul 07 07:02:52 PM PDT 24
Finished Jul 07 07:03:03 PM PDT 24
Peak memory 217784 kb
Host smart-1458b6f9-bb8d-4300-9e0d-417338637f4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491537406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
1491537406
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.752620771
Short name T433
Test name
Test status
Simulation time 851776799 ps
CPU time 15.6 seconds
Started Jul 07 07:02:55 PM PDT 24
Finished Jul 07 07:03:11 PM PDT 24
Peak memory 225572 kb
Host smart-f014effe-638e-483e-99c9-a60f3a7f5b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752620771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.752620771
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.3812366210
Short name T495
Test name
Test status
Simulation time 76214672 ps
CPU time 1.23 seconds
Started Jul 07 07:02:55 PM PDT 24
Finished Jul 07 07:02:56 PM PDT 24
Peak memory 217196 kb
Host smart-80eb5de7-c465-40e8-8071-b9574c6c96d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812366210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.3812366210
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.3146263094
Short name T385
Test name
Test status
Simulation time 881561140 ps
CPU time 27 seconds
Started Jul 07 07:02:55 PM PDT 24
Finished Jul 07 07:03:22 PM PDT 24
Peak memory 250472 kb
Host smart-840dfe40-9bd8-4f5e-9db2-0e00f15878ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146263094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.3146263094
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.1305491104
Short name T269
Test name
Test status
Simulation time 715120945 ps
CPU time 3.5 seconds
Started Jul 07 07:02:53 PM PDT 24
Finished Jul 07 07:02:57 PM PDT 24
Peak memory 225940 kb
Host smart-d201d6b4-9d62-49c6-8743-196f640b7c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305491104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.1305491104
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.482649392
Short name T646
Test name
Test status
Simulation time 1971908269 ps
CPU time 25.92 seconds
Started Jul 07 07:02:55 PM PDT 24
Finished Jul 07 07:03:21 PM PDT 24
Peak memory 226240 kb
Host smart-a0b6f7d3-7b23-4685-81d9-6c943c20dc29
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482649392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.482649392
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.2253126445
Short name T351
Test name
Test status
Simulation time 20460635 ps
CPU time 0.83 seconds
Started Jul 07 07:02:53 PM PDT 24
Finished Jul 07 07:02:54 PM PDT 24
Peak memory 208384 kb
Host smart-69bd877a-a4d6-43e0-87ad-ca071713dd65
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253126445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.2253126445
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.1577867029
Short name T700
Test name
Test status
Simulation time 81534539 ps
CPU time 1.28 seconds
Started Jul 07 07:02:59 PM PDT 24
Finished Jul 07 07:03:00 PM PDT 24
Peak memory 208544 kb
Host smart-9d9eaf5c-fd99-4745-89ae-dea64e898502
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577867029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.1577867029
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.2890861137
Short name T479
Test name
Test status
Simulation time 1083705710 ps
CPU time 16.18 seconds
Started Jul 07 07:03:02 PM PDT 24
Finished Jul 07 07:03:19 PM PDT 24
Peak memory 217780 kb
Host smart-7c6646cf-1a63-4e08-8818-43f9dbcbc3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890861137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.2890861137
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.2002042194
Short name T751
Test name
Test status
Simulation time 1460091150 ps
CPU time 4.03 seconds
Started Jul 07 07:03:02 PM PDT 24
Finished Jul 07 07:03:06 PM PDT 24
Peak memory 217216 kb
Host smart-5f44f415-df6e-4f08-b61e-a466665baa56
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002042194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.2002042194
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.2365112967
Short name T714
Test name
Test status
Simulation time 43477798 ps
CPU time 1.86 seconds
Started Jul 07 07:03:01 PM PDT 24
Finished Jul 07 07:03:03 PM PDT 24
Peak memory 217768 kb
Host smart-2ab8b0d4-db50-46c7-9eae-74e28ffefc1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365112967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.2365112967
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.3606633100
Short name T436
Test name
Test status
Simulation time 885639320 ps
CPU time 10.93 seconds
Started Jul 07 07:03:01 PM PDT 24
Finished Jul 07 07:03:12 PM PDT 24
Peak memory 225504 kb
Host smart-44359c99-cb5d-4fb0-9b1e-3833119fb298
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606633100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.3606633100
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.3349377585
Short name T453
Test name
Test status
Simulation time 2212705074 ps
CPU time 12.61 seconds
Started Jul 07 07:02:59 PM PDT 24
Finished Jul 07 07:03:12 PM PDT 24
Peak memory 217788 kb
Host smart-bd05198d-01dd-419d-a4eb-0e4380b210ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349377585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
3349377585
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.2772201341
Short name T460
Test name
Test status
Simulation time 212099754 ps
CPU time 9.52 seconds
Started Jul 07 07:02:59 PM PDT 24
Finished Jul 07 07:03:08 PM PDT 24
Peak memory 224436 kb
Host smart-3bdd4646-82a2-4637-996b-17fc8056d3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772201341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.2772201341
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.207434688
Short name T75
Test name
Test status
Simulation time 63266523 ps
CPU time 1.48 seconds
Started Jul 07 07:02:58 PM PDT 24
Finished Jul 07 07:03:00 PM PDT 24
Peak memory 217192 kb
Host smart-96286ca5-c345-49ce-8cfc-203def09ca08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207434688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.207434688
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.1848730216
Short name T509
Test name
Test status
Simulation time 975528162 ps
CPU time 28.3 seconds
Started Jul 07 07:03:01 PM PDT 24
Finished Jul 07 07:03:30 PM PDT 24
Peak memory 250552 kb
Host smart-fe41a50d-74b7-42c4-8c06-d3c51fea13cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848730216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.1848730216
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.4211614272
Short name T331
Test name
Test status
Simulation time 74813425 ps
CPU time 6.69 seconds
Started Jul 07 07:03:00 PM PDT 24
Finished Jul 07 07:03:07 PM PDT 24
Peak memory 246516 kb
Host smart-75bd6353-3d7b-4485-9047-47eff7f83301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211614272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.4211614272
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.1391229890
Short name T374
Test name
Test status
Simulation time 2589134404 ps
CPU time 45.09 seconds
Started Jul 07 07:03:01 PM PDT 24
Finished Jul 07 07:03:46 PM PDT 24
Peak memory 250588 kb
Host smart-87e81f2d-fe77-4dcb-963e-0e9dd986eaa3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391229890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.1391229890
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.1701424849
Short name T332
Test name
Test status
Simulation time 106293016 ps
CPU time 0.99 seconds
Started Jul 07 07:02:55 PM PDT 24
Finished Jul 07 07:02:56 PM PDT 24
Peak memory 212600 kb
Host smart-cdd50dff-2fe1-4317-807b-831d93e2aaf8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701424849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.1701424849
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.205816901
Short name T285
Test name
Test status
Simulation time 68790683 ps
CPU time 0.94 seconds
Started Jul 07 07:03:04 PM PDT 24
Finished Jul 07 07:03:05 PM PDT 24
Peak memory 208496 kb
Host smart-34401377-b6da-469b-92af-809807665b94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205816901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.205816901
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.650602058
Short name T244
Test name
Test status
Simulation time 478338452 ps
CPU time 16.05 seconds
Started Jul 07 07:03:06 PM PDT 24
Finished Jul 07 07:03:22 PM PDT 24
Peak memory 217776 kb
Host smart-55ff3b9c-f2ae-403c-8756-12df61c1ce51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650602058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.650602058
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.3267990335
Short name T601
Test name
Test status
Simulation time 4602757917 ps
CPU time 11.05 seconds
Started Jul 07 07:03:05 PM PDT 24
Finished Jul 07 07:03:16 PM PDT 24
Peak memory 217284 kb
Host smart-6e9e98be-a021-4f23-b5eb-395029610a26
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267990335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.3267990335
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.1794801989
Short name T775
Test name
Test status
Simulation time 362900708 ps
CPU time 4.09 seconds
Started Jul 07 07:03:03 PM PDT 24
Finished Jul 07 07:03:07 PM PDT 24
Peak memory 217792 kb
Host smart-fbee6554-6929-47f6-a32b-da03206b0552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794801989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.1794801989
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.3875194797
Short name T553
Test name
Test status
Simulation time 412688206 ps
CPU time 9.82 seconds
Started Jul 07 07:03:04 PM PDT 24
Finished Jul 07 07:03:15 PM PDT 24
Peak memory 225528 kb
Host smart-3de1fdad-49af-40ab-af1b-7298c0984a05
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875194797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.3875194797
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.532951978
Short name T217
Test name
Test status
Simulation time 276233724 ps
CPU time 7.82 seconds
Started Jul 07 07:03:03 PM PDT 24
Finished Jul 07 07:03:11 PM PDT 24
Peak memory 217712 kb
Host smart-ec0db459-4995-424e-a0b6-c62951ea196e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532951978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.532951978
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.377014412
Short name T574
Test name
Test status
Simulation time 3459317274 ps
CPU time 10.92 seconds
Started Jul 07 07:03:04 PM PDT 24
Finished Jul 07 07:03:16 PM PDT 24
Peak memory 225656 kb
Host smart-7922b678-6946-4d34-9deb-4a6231692615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377014412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.377014412
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.3242502937
Short name T66
Test name
Test status
Simulation time 44814818 ps
CPU time 3.16 seconds
Started Jul 07 07:03:03 PM PDT 24
Finished Jul 07 07:03:06 PM PDT 24
Peak memory 214732 kb
Host smart-7ebb820e-270f-4313-84a7-a27b69c4da33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242502937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.3242502937
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.3655796867
Short name T604
Test name
Test status
Simulation time 278898477 ps
CPU time 32.02 seconds
Started Jul 07 07:02:59 PM PDT 24
Finished Jul 07 07:03:32 PM PDT 24
Peak memory 250544 kb
Host smart-1916686f-dbbe-4931-9d9b-ec103811adae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655796867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.3655796867
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.3791101419
Short name T203
Test name
Test status
Simulation time 107387432 ps
CPU time 6.38 seconds
Started Jul 07 07:03:02 PM PDT 24
Finished Jul 07 07:03:09 PM PDT 24
Peak memory 246416 kb
Host smart-90ab3544-668a-44f1-a2c9-0e3802af7ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791101419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.3791101419
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.3205597396
Short name T593
Test name
Test status
Simulation time 7288429707 ps
CPU time 126.02 seconds
Started Jul 07 07:03:07 PM PDT 24
Finished Jul 07 07:05:13 PM PDT 24
Peak memory 275136 kb
Host smart-70c9e36b-a8be-4d60-9b8a-5312ce8acfff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205597396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.3205597396
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.3535269317
Short name T74
Test name
Test status
Simulation time 26828155 ps
CPU time 1.18 seconds
Started Jul 07 07:03:00 PM PDT 24
Finished Jul 07 07:03:02 PM PDT 24
Peak memory 211392 kb
Host smart-1102c6e1-03c6-4956-bbbf-7edc3c0fb9e7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535269317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.3535269317
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.2915325749
Short name T413
Test name
Test status
Simulation time 183761516 ps
CPU time 1.05 seconds
Started Jul 07 07:03:12 PM PDT 24
Finished Jul 07 07:03:14 PM PDT 24
Peak memory 208496 kb
Host smart-393babce-b8e5-4db3-be71-52f5344d9bad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915325749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.2915325749
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.3684663705
Short name T263
Test name
Test status
Simulation time 3205698852 ps
CPU time 12.77 seconds
Started Jul 07 07:03:18 PM PDT 24
Finished Jul 07 07:03:31 PM PDT 24
Peak memory 218028 kb
Host smart-ca122a8e-92ee-4f7c-9fa3-b34ff276e650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684663705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.3684663705
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.1618070171
Short name T808
Test name
Test status
Simulation time 4437291634 ps
CPU time 12.21 seconds
Started Jul 07 07:03:11 PM PDT 24
Finished Jul 07 07:03:23 PM PDT 24
Peak memory 217340 kb
Host smart-d33de275-ded6-47fa-b0a8-66726e7de8a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618070171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.1618070171
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.3126817506
Short name T281
Test name
Test status
Simulation time 44903267 ps
CPU time 2.06 seconds
Started Jul 07 07:03:14 PM PDT 24
Finished Jul 07 07:03:16 PM PDT 24
Peak memory 217768 kb
Host smart-a15d6998-0890-4a4b-b830-bfb0974a01af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126817506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.3126817506
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.2033535689
Short name T490
Test name
Test status
Simulation time 1317991691 ps
CPU time 13.9 seconds
Started Jul 07 07:03:16 PM PDT 24
Finished Jul 07 07:03:30 PM PDT 24
Peak memory 219524 kb
Host smart-31f742eb-9816-457e-9778-f1c0d5f8e6ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033535689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.2033535689
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.1431074878
Short name T9
Test name
Test status
Simulation time 1173450772 ps
CPU time 8.97 seconds
Started Jul 07 07:03:12 PM PDT 24
Finished Jul 07 07:03:21 PM PDT 24
Peak memory 225504 kb
Host smart-1a7c1d29-ff1f-4c4b-97ec-8c5af0420736
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431074878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.1431074878
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.3216928301
Short name T204
Test name
Test status
Simulation time 603250988 ps
CPU time 7.23 seconds
Started Jul 07 07:03:06 PM PDT 24
Finished Jul 07 07:03:13 PM PDT 24
Peak memory 217716 kb
Host smart-88b2b180-fda8-4f0a-ae01-d24d634dde86
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216928301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
3216928301
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.1154551121
Short name T562
Test name
Test status
Simulation time 220663534 ps
CPU time 6.73 seconds
Started Jul 07 07:03:15 PM PDT 24
Finished Jul 07 07:03:21 PM PDT 24
Peak memory 224656 kb
Host smart-6661fb40-b75b-4025-b95d-c41fea2c3ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154551121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.1154551121
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.1969435414
Short name T435
Test name
Test status
Simulation time 42357911 ps
CPU time 1.79 seconds
Started Jul 07 07:03:05 PM PDT 24
Finished Jul 07 07:03:07 PM PDT 24
Peak memory 217332 kb
Host smart-9d955a81-9be7-4824-813e-6ffe738d336e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969435414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.1969435414
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.2662904204
Short name T29
Test name
Test status
Simulation time 821894079 ps
CPU time 16.17 seconds
Started Jul 07 07:03:04 PM PDT 24
Finished Jul 07 07:03:21 PM PDT 24
Peak memory 250648 kb
Host smart-9c94beb8-4cc5-440b-a85b-5e53e6a3bc15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662904204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.2662904204
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.2250488846
Short name T273
Test name
Test status
Simulation time 57395814 ps
CPU time 7.03 seconds
Started Jul 07 07:03:05 PM PDT 24
Finished Jul 07 07:03:12 PM PDT 24
Peak memory 250552 kb
Host smart-92b3a560-aa8e-4d0f-92bc-cd0171c1fa31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250488846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.2250488846
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.3629810498
Short name T609
Test name
Test status
Simulation time 17112776757 ps
CPU time 153.27 seconds
Started Jul 07 07:03:11 PM PDT 24
Finished Jul 07 07:05:45 PM PDT 24
Peak memory 266976 kb
Host smart-549c40ac-7fd5-4ac6-953c-9e476f57ab5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629810498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.3629810498
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1957905540
Short name T860
Test name
Test status
Simulation time 13450537 ps
CPU time 0.83 seconds
Started Jul 07 07:03:04 PM PDT 24
Finished Jul 07 07:03:05 PM PDT 24
Peak memory 208584 kb
Host smart-a613f99e-1e30-4ec5-b549-e336a624ec8d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957905540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.1957905540
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.3991812689
Short name T411
Test name
Test status
Simulation time 34198871 ps
CPU time 0.94 seconds
Started Jul 07 07:03:13 PM PDT 24
Finished Jul 07 07:03:14 PM PDT 24
Peak memory 208456 kb
Host smart-ae3e94c7-1c41-483d-a850-790bf7810dea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991812689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.3991812689
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.1655761950
Short name T710
Test name
Test status
Simulation time 1666078523 ps
CPU time 12.83 seconds
Started Jul 07 07:03:11 PM PDT 24
Finished Jul 07 07:03:24 PM PDT 24
Peak memory 217796 kb
Host smart-c0f80169-8756-49ae-a0ef-f8dcf7bde9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655761950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.1655761950
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.3179344455
Short name T669
Test name
Test status
Simulation time 3993719432 ps
CPU time 4.07 seconds
Started Jul 07 07:03:16 PM PDT 24
Finished Jul 07 07:03:20 PM PDT 24
Peak memory 217152 kb
Host smart-1a961492-7250-48cb-89d9-7bef71df5536
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179344455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.3179344455
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.127554445
Short name T550
Test name
Test status
Simulation time 215680063 ps
CPU time 2.49 seconds
Started Jul 07 07:03:13 PM PDT 24
Finished Jul 07 07:03:16 PM PDT 24
Peak memory 217788 kb
Host smart-e6d35f8e-b7e1-41d7-b461-49b3361b1eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127554445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.127554445
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.2864179802
Short name T671
Test name
Test status
Simulation time 1795616706 ps
CPU time 14.42 seconds
Started Jul 07 07:03:12 PM PDT 24
Finished Jul 07 07:03:27 PM PDT 24
Peak memory 225588 kb
Host smart-7b8e0084-2bf6-4c4f-8924-aea29674d46a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864179802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.2864179802
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.4037760900
Short name T750
Test name
Test status
Simulation time 1452990101 ps
CPU time 11.72 seconds
Started Jul 07 07:03:13 PM PDT 24
Finished Jul 07 07:03:25 PM PDT 24
Peak memory 225488 kb
Host smart-3eac0d9c-a7c8-4610-8000-7a1c015da3cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037760900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.4037760900
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.3524845058
Short name T212
Test name
Test status
Simulation time 203193839 ps
CPU time 6.92 seconds
Started Jul 07 07:03:13 PM PDT 24
Finished Jul 07 07:03:20 PM PDT 24
Peak memory 217704 kb
Host smart-18e5a0e5-a52a-4040-b4fb-905913d74331
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524845058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
3524845058
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.4149932906
Short name T267
Test name
Test status
Simulation time 472588183 ps
CPU time 10.4 seconds
Started Jul 07 07:03:12 PM PDT 24
Finished Jul 07 07:03:23 PM PDT 24
Peak memory 225560 kb
Host smart-025ca8ab-498d-469d-a580-6ab5a828aace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149932906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.4149932906
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.1015566821
Short name T90
Test name
Test status
Simulation time 112949117 ps
CPU time 2.45 seconds
Started Jul 07 07:03:15 PM PDT 24
Finished Jul 07 07:03:17 PM PDT 24
Peak memory 213876 kb
Host smart-469fb538-63f9-498c-8fb4-31c7251d0137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015566821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.1015566821
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.3328372534
Short name T302
Test name
Test status
Simulation time 469087725 ps
CPU time 24.83 seconds
Started Jul 07 07:03:11 PM PDT 24
Finished Jul 07 07:03:36 PM PDT 24
Peak memory 250536 kb
Host smart-434c0bb7-34da-4aa5-909b-abaa0cb885db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328372534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.3328372534
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.1345309628
Short name T356
Test name
Test status
Simulation time 317796677 ps
CPU time 3.16 seconds
Started Jul 07 07:03:13 PM PDT 24
Finished Jul 07 07:03:17 PM PDT 24
Peak memory 225924 kb
Host smart-84d13289-afee-4aaa-b8f0-890103378cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345309628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.1345309628
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.884453293
Short name T680
Test name
Test status
Simulation time 11199935248 ps
CPU time 184.81 seconds
Started Jul 07 07:03:12 PM PDT 24
Finished Jul 07 07:06:17 PM PDT 24
Peak memory 275532 kb
Host smart-c0e11150-3d29-40bf-a534-9a7e5254f0ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884453293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.884453293
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.180228987
Short name T187
Test name
Test status
Simulation time 95148963714 ps
CPU time 341.83 seconds
Started Jul 07 07:03:12 PM PDT 24
Finished Jul 07 07:08:54 PM PDT 24
Peak memory 283464 kb
Host smart-90523a42-41a8-47bc-a274-8654f6d05d2f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=180228987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all_with_rand_reset.180228987
Directory /workspace/46.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.2714736133
Short name T755
Test name
Test status
Simulation time 29611238 ps
CPU time 0.88 seconds
Started Jul 07 07:03:07 PM PDT 24
Finished Jul 07 07:03:08 PM PDT 24
Peak memory 208420 kb
Host smart-8614181f-e881-4c4c-b429-9e32522318f1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714736133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.2714736133
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.821840337
Short name T849
Test name
Test status
Simulation time 17999917 ps
CPU time 1.01 seconds
Started Jul 07 07:03:19 PM PDT 24
Finished Jul 07 07:03:21 PM PDT 24
Peak memory 208560 kb
Host smart-1770c79d-f804-4a38-b7aa-b7a332c6927e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821840337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.821840337
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.1912339091
Short name T815
Test name
Test status
Simulation time 1293095883 ps
CPU time 14.46 seconds
Started Jul 07 07:03:16 PM PDT 24
Finished Jul 07 07:03:30 PM PDT 24
Peak memory 217780 kb
Host smart-b4cc55fc-abd1-4196-9b5b-762f237fa030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912339091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.1912339091
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.314571065
Short name T104
Test name
Test status
Simulation time 713590666 ps
CPU time 10.11 seconds
Started Jul 07 07:03:15 PM PDT 24
Finished Jul 07 07:03:25 PM PDT 24
Peak memory 217172 kb
Host smart-c4dad314-6867-4fe8-9937-8369493a8a30
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314571065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.314571065
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.3280102383
Short name T459
Test name
Test status
Simulation time 63400772 ps
CPU time 1.98 seconds
Started Jul 07 07:03:19 PM PDT 24
Finished Jul 07 07:03:21 PM PDT 24
Peak memory 217808 kb
Host smart-761d61f8-2284-4df5-83ae-5e9a9c3fdddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280102383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.3280102383
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.894165575
Short name T410
Test name
Test status
Simulation time 4277613226 ps
CPU time 11.26 seconds
Started Jul 07 07:03:19 PM PDT 24
Finished Jul 07 07:03:31 PM PDT 24
Peak memory 225664 kb
Host smart-bfb6fa06-b3c1-426a-84fe-a2188accef3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894165575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.894165575
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.115509508
Short name T390
Test name
Test status
Simulation time 1010340462 ps
CPU time 13.87 seconds
Started Jul 07 07:03:13 PM PDT 24
Finished Jul 07 07:03:28 PM PDT 24
Peak memory 225492 kb
Host smart-03c4fb46-0c0f-40ee-9459-98b604283a9a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115509508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_di
gest.115509508
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.486183403
Short name T226
Test name
Test status
Simulation time 535497876 ps
CPU time 8.31 seconds
Started Jul 07 07:03:13 PM PDT 24
Finished Jul 07 07:03:22 PM PDT 24
Peak memory 217660 kb
Host smart-e5420d03-d95f-4e43-8f7a-342fadaab0d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486183403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.486183403
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.1152602800
Short name T192
Test name
Test status
Simulation time 260343506 ps
CPU time 10.8 seconds
Started Jul 07 07:03:15 PM PDT 24
Finished Jul 07 07:03:26 PM PDT 24
Peak memory 217856 kb
Host smart-e03a16a4-121c-46a7-bb87-b107937b4dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152602800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.1152602800
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.2697006173
Short name T86
Test name
Test status
Simulation time 536021012 ps
CPU time 5.33 seconds
Started Jul 07 07:03:13 PM PDT 24
Finished Jul 07 07:03:19 PM PDT 24
Peak memory 217124 kb
Host smart-7067e60f-2a38-4110-95d6-1be53e0c5cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697006173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.2697006173
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.2177268443
Short name T681
Test name
Test status
Simulation time 267288835 ps
CPU time 26.37 seconds
Started Jul 07 07:03:17 PM PDT 24
Finished Jul 07 07:03:43 PM PDT 24
Peak memory 250508 kb
Host smart-d4a8c88e-92f2-466e-938c-deb6a521df21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177268443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.2177268443
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.2477145045
Short name T358
Test name
Test status
Simulation time 233667692 ps
CPU time 6.42 seconds
Started Jul 07 07:03:15 PM PDT 24
Finished Jul 07 07:03:21 PM PDT 24
Peak memory 242352 kb
Host smart-f02e511d-8549-4860-a0ca-a58f60de2b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477145045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.2477145045
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.1994609670
Short name T19
Test name
Test status
Simulation time 7413314815 ps
CPU time 254.89 seconds
Started Jul 07 07:03:17 PM PDT 24
Finished Jul 07 07:07:32 PM PDT 24
Peak memory 269648 kb
Host smart-eee8a6bc-ed6c-4164-89e4-cdde305920e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994609670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.1994609670
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.1094217403
Short name T106
Test name
Test status
Simulation time 12913670684 ps
CPU time 56.52 seconds
Started Jul 07 07:03:19 PM PDT 24
Finished Jul 07 07:04:16 PM PDT 24
Peak memory 226008 kb
Host smart-d62fabc9-6a0e-422d-9c5e-58523252126c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1094217403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all_with_rand_reset.1094217403
Directory /workspace/47.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.1290131227
Short name T711
Test name
Test status
Simulation time 46344876 ps
CPU time 0.91 seconds
Started Jul 07 07:03:20 PM PDT 24
Finished Jul 07 07:03:21 PM PDT 24
Peak memory 208688 kb
Host smart-1718efbc-9286-4f06-ba1a-901eb5657b4b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290131227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.1290131227
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.2667169646
Short name T330
Test name
Test status
Simulation time 44186233 ps
CPU time 1.24 seconds
Started Jul 07 07:03:21 PM PDT 24
Finished Jul 07 07:03:23 PM PDT 24
Peak memory 208548 kb
Host smart-5f82bab9-4c6c-4937-9d3d-8082d393d53b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667169646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.2667169646
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.1165970858
Short name T788
Test name
Test status
Simulation time 1304903302 ps
CPU time 13.83 seconds
Started Jul 07 07:03:21 PM PDT 24
Finished Jul 07 07:03:35 PM PDT 24
Peak memory 217720 kb
Host smart-2383f80f-3528-4c58-9fbc-e709dc99b208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165970858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.1165970858
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.3489987813
Short name T327
Test name
Test status
Simulation time 4303123528 ps
CPU time 7.15 seconds
Started Jul 07 07:03:17 PM PDT 24
Finished Jul 07 07:03:24 PM PDT 24
Peak memory 217256 kb
Host smart-4e40a1f4-e75a-4d37-bd79-70a36fcd661d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489987813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.3489987813
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.3171009431
Short name T214
Test name
Test status
Simulation time 17649588 ps
CPU time 1.67 seconds
Started Jul 07 07:03:22 PM PDT 24
Finished Jul 07 07:03:24 PM PDT 24
Peak memory 218024 kb
Host smart-47e300d5-f25d-4946-b0de-2ffe8a663678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171009431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.3171009431
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.4227464561
Short name T822
Test name
Test status
Simulation time 1438695550 ps
CPU time 17.26 seconds
Started Jul 07 07:03:16 PM PDT 24
Finished Jul 07 07:03:33 PM PDT 24
Peak memory 225580 kb
Host smart-2d03c960-13a0-4cad-a256-f5e26ad519df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227464561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.4227464561
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.974253437
Short name T549
Test name
Test status
Simulation time 1038425093 ps
CPU time 9.61 seconds
Started Jul 07 07:03:19 PM PDT 24
Finished Jul 07 07:03:29 PM PDT 24
Peak memory 225476 kb
Host smart-7945f22a-74f4-4d26-b776-12fa887b0a70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974253437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_di
gest.974253437
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.3129464120
Short name T811
Test name
Test status
Simulation time 839544126 ps
CPU time 11.28 seconds
Started Jul 07 07:03:16 PM PDT 24
Finished Jul 07 07:03:28 PM PDT 24
Peak memory 225516 kb
Host smart-cd39c01f-f44d-4246-a72b-6123041eb7d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129464120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
3129464120
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.3473487304
Short name T719
Test name
Test status
Simulation time 1501445949 ps
CPU time 15.36 seconds
Started Jul 07 07:03:17 PM PDT 24
Finished Jul 07 07:03:33 PM PDT 24
Peak memory 225592 kb
Host smart-f1d04af5-3ed4-427c-9f2f-ac0a78b9eb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473487304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.3473487304
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.2316044991
Short name T301
Test name
Test status
Simulation time 106182038 ps
CPU time 1.58 seconds
Started Jul 07 07:03:13 PM PDT 24
Finished Jul 07 07:03:15 PM PDT 24
Peak memory 213476 kb
Host smart-0026f55a-0907-4155-b4f5-fefcc7dc1f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316044991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.2316044991
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.295627234
Short name T195
Test name
Test status
Simulation time 258787258 ps
CPU time 32.09 seconds
Started Jul 07 07:03:19 PM PDT 24
Finished Jul 07 07:03:51 PM PDT 24
Peak memory 244680 kb
Host smart-d57b6d70-005c-4c60-89c0-9c8de5082541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295627234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.295627234
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.378316077
Short name T632
Test name
Test status
Simulation time 214415858 ps
CPU time 5.99 seconds
Started Jul 07 07:03:21 PM PDT 24
Finished Jul 07 07:03:28 PM PDT 24
Peak memory 246796 kb
Host smart-d4afc61c-173c-442e-abc0-95c455467c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378316077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.378316077
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.504708489
Short name T48
Test name
Test status
Simulation time 3033901729 ps
CPU time 64.54 seconds
Started Jul 07 07:03:23 PM PDT 24
Finished Jul 07 07:04:28 PM PDT 24
Peak memory 251548 kb
Host smart-ec6909dc-0a1b-4e94-b231-9184080a23cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504708489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.504708489
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.3364366748
Short name T54
Test name
Test status
Simulation time 38437110626 ps
CPU time 360.62 seconds
Started Jul 07 07:03:24 PM PDT 24
Finished Jul 07 07:09:25 PM PDT 24
Peak memory 273292 kb
Host smart-1cd823e2-d5e3-447d-ad7c-695ddece5a76
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3364366748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.3364366748
Directory /workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.227241100
Short name T624
Test name
Test status
Simulation time 22549744 ps
CPU time 1.24 seconds
Started Jul 07 07:03:29 PM PDT 24
Finished Jul 07 07:03:30 PM PDT 24
Peak memory 208896 kb
Host smart-19a047c5-e707-470e-81d8-55609d8fe2ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227241100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.227241100
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.3448189710
Short name T623
Test name
Test status
Simulation time 1075021034 ps
CPU time 11.86 seconds
Started Jul 07 07:03:23 PM PDT 24
Finished Jul 07 07:03:35 PM PDT 24
Peak memory 217784 kb
Host smart-bb95ca0b-d606-4239-bf49-d2ff0809f19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448189710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.3448189710
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.3220467027
Short name T24
Test name
Test status
Simulation time 730301019 ps
CPU time 7.27 seconds
Started Jul 07 07:03:20 PM PDT 24
Finished Jul 07 07:03:28 PM PDT 24
Peak memory 216816 kb
Host smart-65a79141-c072-4812-b51d-778c82e622d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220467027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.3220467027
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.534149558
Short name T526
Test name
Test status
Simulation time 56509781 ps
CPU time 2.5 seconds
Started Jul 07 07:03:23 PM PDT 24
Finished Jul 07 07:03:26 PM PDT 24
Peak memory 221896 kb
Host smart-4aa3d684-96d6-4442-86aa-60cc41dd4b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534149558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.534149558
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.2789354365
Short name T812
Test name
Test status
Simulation time 254417167 ps
CPU time 8.44 seconds
Started Jul 07 07:03:26 PM PDT 24
Finished Jul 07 07:03:34 PM PDT 24
Peak memory 225512 kb
Host smart-8f164fc8-a03d-4c7a-bb40-472ed4f9f415
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789354365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.2789354365
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.2470058539
Short name T335
Test name
Test status
Simulation time 578369579 ps
CPU time 7.44 seconds
Started Jul 07 07:03:20 PM PDT 24
Finished Jul 07 07:03:28 PM PDT 24
Peak memory 217716 kb
Host smart-d87ec1c2-d600-443f-a1b5-26882fbc8112
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470058539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
2470058539
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.3481299798
Short name T194
Test name
Test status
Simulation time 1299299895 ps
CPU time 7.17 seconds
Started Jul 07 07:03:24 PM PDT 24
Finished Jul 07 07:03:32 PM PDT 24
Peak memory 217772 kb
Host smart-2cadd338-5505-428e-88b5-5483d53fd58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481299798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.3481299798
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.1102532897
Short name T855
Test name
Test status
Simulation time 108603912 ps
CPU time 2.61 seconds
Started Jul 07 07:03:22 PM PDT 24
Finished Jul 07 07:03:25 PM PDT 24
Peak memory 217200 kb
Host smart-b67e56fc-de89-40ec-959d-c8780f0ea468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102532897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.1102532897
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.1485429776
Short name T603
Test name
Test status
Simulation time 379246865 ps
CPU time 33.33 seconds
Started Jul 07 07:03:24 PM PDT 24
Finished Jul 07 07:03:58 PM PDT 24
Peak memory 250780 kb
Host smart-341919fe-7221-4055-85c4-14e5d1283c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485429776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.1485429776
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.1682605782
Short name T524
Test name
Test status
Simulation time 90462769 ps
CPU time 10.24 seconds
Started Jul 07 07:03:23 PM PDT 24
Finished Jul 07 07:03:34 PM PDT 24
Peak memory 250540 kb
Host smart-7ec504d6-6594-470a-b4e1-22bfc1a10453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682605782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.1682605782
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.1833629411
Short name T53
Test name
Test status
Simulation time 46484335407 ps
CPU time 691.46 seconds
Started Jul 07 07:03:25 PM PDT 24
Finished Jul 07 07:14:57 PM PDT 24
Peak memory 268812 kb
Host smart-9366ba61-e245-43fc-84b0-d16dbe26fd29
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833629411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.1833629411
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.437164122
Short name T762
Test name
Test status
Simulation time 160732066 ps
CPU time 0.89 seconds
Started Jul 07 07:03:21 PM PDT 24
Finished Jul 07 07:03:23 PM PDT 24
Peak memory 208424 kb
Host smart-bfc1f4c7-8331-4404-b15f-b043ec8df38a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437164122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ct
rl_volatile_unlock_smoke.437164122
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.3132520751
Short name T772
Test name
Test status
Simulation time 59176406 ps
CPU time 1.13 seconds
Started Jul 07 06:59:51 PM PDT 24
Finished Jul 07 06:59:52 PM PDT 24
Peak memory 208520 kb
Host smart-7e3429d9-ec48-40ed-aa8b-679e7d71b393
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132520751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.3132520751
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.2119631359
Short name T188
Test name
Test status
Simulation time 38097406 ps
CPU time 0.85 seconds
Started Jul 07 06:59:47 PM PDT 24
Finished Jul 07 06:59:48 PM PDT 24
Peak memory 208432 kb
Host smart-6079cd64-6703-4ebe-83a8-4e6535ffe474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119631359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.2119631359
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.3485452496
Short name T721
Test name
Test status
Simulation time 1207515013 ps
CPU time 11.07 seconds
Started Jul 07 06:59:49 PM PDT 24
Finished Jul 07 07:00:00 PM PDT 24
Peak memory 216976 kb
Host smart-35856358-ce38-403f-8d84-e2097f25e9eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485452496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.3485452496
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.339941763
Short name T497
Test name
Test status
Simulation time 3351439184 ps
CPU time 83.84 seconds
Started Jul 07 06:59:52 PM PDT 24
Finished Jul 07 07:01:16 PM PDT 24
Peak memory 218424 kb
Host smart-4f432e99-05c4-48d1-85ca-20f55f60b4a5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339941763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_err
ors.339941763
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.2359300479
Short name T266
Test name
Test status
Simulation time 280043412 ps
CPU time 3.94 seconds
Started Jul 07 06:59:49 PM PDT 24
Finished Jul 07 06:59:53 PM PDT 24
Peak memory 216932 kb
Host smart-feb5baf0-2c92-4c84-b39c-6763acd6e175
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359300479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.2
359300479
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.3200189905
Short name T814
Test name
Test status
Simulation time 1197705969 ps
CPU time 5.12 seconds
Started Jul 07 06:59:49 PM PDT 24
Finished Jul 07 06:59:55 PM PDT 24
Peak memory 217700 kb
Host smart-06c0f5c4-c49e-4f78-804d-d4da582f2fcc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200189905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.3200189905
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.2287807011
Short name T296
Test name
Test status
Simulation time 803295384 ps
CPU time 16.99 seconds
Started Jul 07 06:59:49 PM PDT 24
Finished Jul 07 07:00:06 PM PDT 24
Peak memory 216816 kb
Host smart-901c0266-cdf7-4e1e-b54b-a4a8d5f13054
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287807011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.2287807011
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.3202446314
Short name T477
Test name
Test status
Simulation time 48425057 ps
CPU time 1.43 seconds
Started Jul 07 06:59:47 PM PDT 24
Finished Jul 07 06:59:49 PM PDT 24
Peak memory 217080 kb
Host smart-ca963529-202f-49ac-b68b-9872dcf4b75d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202446314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
3202446314
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.91324512
Short name T689
Test name
Test status
Simulation time 7577696410 ps
CPU time 131.61 seconds
Started Jul 07 06:59:49 PM PDT 24
Finished Jul 07 07:02:01 PM PDT 24
Peak memory 283420 kb
Host smart-242bbaeb-fff3-40f8-9ba2-4d6e4a6d67b9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91324512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_
state_failure.91324512
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.1472298496
Short name T528
Test name
Test status
Simulation time 1586310969 ps
CPU time 11.74 seconds
Started Jul 07 06:59:52 PM PDT 24
Finished Jul 07 07:00:04 PM PDT 24
Peak memory 250456 kb
Host smart-f4b5360f-f2ec-4eab-a404-deb1595bf207
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472298496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.1472298496
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.1489547563
Short name T432
Test name
Test status
Simulation time 281850875 ps
CPU time 2.26 seconds
Started Jul 07 06:59:44 PM PDT 24
Finished Jul 07 06:59:47 PM PDT 24
Peak memory 217784 kb
Host smart-8b9b7b58-d507-44f7-9587-61fac4a202d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489547563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.1489547563
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.2667892501
Short name T752
Test name
Test status
Simulation time 683392056 ps
CPU time 24.27 seconds
Started Jul 07 06:59:44 PM PDT 24
Finished Jul 07 07:00:09 PM PDT 24
Peak memory 214264 kb
Host smart-818d7765-fcaf-4af1-bfad-a3d8b9181ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667892501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.2667892501
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.4168028133
Short name T596
Test name
Test status
Simulation time 1924031563 ps
CPU time 16.78 seconds
Started Jul 07 06:59:52 PM PDT 24
Finished Jul 07 07:00:09 PM PDT 24
Peak memory 218616 kb
Host smart-859614d4-8d8d-490c-b5eb-6bf75fb46776
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168028133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.4168028133
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.310671052
Short name T743
Test name
Test status
Simulation time 1531907700 ps
CPU time 11.35 seconds
Started Jul 07 06:59:49 PM PDT 24
Finished Jul 07 07:00:00 PM PDT 24
Peak memory 225504 kb
Host smart-642e808b-de1a-48d9-98f5-78feff47b33c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310671052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_dig
est.310671052
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.3117469273
Short name T70
Test name
Test status
Simulation time 1100767174 ps
CPU time 6.01 seconds
Started Jul 07 06:59:51 PM PDT 24
Finished Jul 07 06:59:57 PM PDT 24
Peak memory 217724 kb
Host smart-700fc91c-5258-4bc6-891b-ac8e4744e1a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117469273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.3
117469273
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.101620588
Short name T287
Test name
Test status
Simulation time 2587798431 ps
CPU time 8.62 seconds
Started Jul 07 06:59:43 PM PDT 24
Finished Jul 07 06:59:52 PM PDT 24
Peak memory 217908 kb
Host smart-40dde445-3842-49bf-b3e5-1c703b4bf4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101620588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.101620588
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.2849533341
Short name T423
Test name
Test status
Simulation time 31528141 ps
CPU time 1.64 seconds
Started Jul 07 06:59:44 PM PDT 24
Finished Jul 07 06:59:46 PM PDT 24
Peak memory 213520 kb
Host smart-d15f71de-1d9a-46a9-b9d8-ab72a5d26929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849533341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.2849533341
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.107299227
Short name T466
Test name
Test status
Simulation time 177159621 ps
CPU time 22.26 seconds
Started Jul 07 06:59:44 PM PDT 24
Finished Jul 07 07:00:07 PM PDT 24
Peak memory 250516 kb
Host smart-d757f78e-4842-44a4-82f8-94a02466e2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107299227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.107299227
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.3139918373
Short name T359
Test name
Test status
Simulation time 114842005 ps
CPU time 3.43 seconds
Started Jul 07 06:59:50 PM PDT 24
Finished Jul 07 06:59:54 PM PDT 24
Peak memory 226200 kb
Host smart-28dc3ff9-2cf9-4b58-8fce-533bd05bac5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139918373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.3139918373
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.489828687
Short name T87
Test name
Test status
Simulation time 90459377242 ps
CPU time 406.06 seconds
Started Jul 07 06:59:52 PM PDT 24
Finished Jul 07 07:06:39 PM PDT 24
Peak memory 308056 kb
Host smart-39d419ee-29e3-4235-b083-edb7e091ac2d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489828687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.489828687
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.1207636874
Short name T457
Test name
Test status
Simulation time 42627530 ps
CPU time 0.94 seconds
Started Jul 07 06:59:50 PM PDT 24
Finished Jul 07 06:59:51 PM PDT 24
Peak memory 208688 kb
Host smart-751bba74-edff-4752-98fc-cd4a7df11f45
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207636874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.1207636874
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.1234123142
Short name T717
Test name
Test status
Simulation time 18583302 ps
CPU time 0.95 seconds
Started Jul 07 07:00:05 PM PDT 24
Finished Jul 07 07:00:06 PM PDT 24
Peak memory 208528 kb
Host smart-daf986ee-a323-47fa-a70c-a9744cf7c167
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234123142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.1234123142
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.3697657477
Short name T715
Test name
Test status
Simulation time 13598352 ps
CPU time 0.83 seconds
Started Jul 07 06:59:52 PM PDT 24
Finished Jul 07 06:59:53 PM PDT 24
Peak memory 208304 kb
Host smart-58624c29-32f8-470a-a45b-16156096316c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697657477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.3697657477
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.1801358157
Short name T611
Test name
Test status
Simulation time 258147177 ps
CPU time 10.72 seconds
Started Jul 07 06:59:53 PM PDT 24
Finished Jul 07 07:00:04 PM PDT 24
Peak memory 217784 kb
Host smart-962a2141-2a20-49bb-8daa-63bf1071eb35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801358157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.1801358157
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.622965976
Short name T430
Test name
Test status
Simulation time 317924330 ps
CPU time 2.71 seconds
Started Jul 07 06:59:55 PM PDT 24
Finished Jul 07 06:59:58 PM PDT 24
Peak memory 217208 kb
Host smart-7080ce04-5ee6-42e1-a934-b4c1beee2f22
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622965976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.622965976
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.4246708558
Short name T303
Test name
Test status
Simulation time 3263938349 ps
CPU time 42.71 seconds
Started Jul 07 06:59:54 PM PDT 24
Finished Jul 07 07:00:37 PM PDT 24
Peak memory 218480 kb
Host smart-17552e94-c124-49bf-bbb9-b588831b6530
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246708558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.4246708558
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.1737530946
Short name T239
Test name
Test status
Simulation time 398230161 ps
CPU time 3.47 seconds
Started Jul 07 06:59:55 PM PDT 24
Finished Jul 07 06:59:59 PM PDT 24
Peak memory 217232 kb
Host smart-2d5130dd-2bf7-420d-ada5-659d1f02dce3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737530946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.1
737530946
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.2483191907
Short name T399
Test name
Test status
Simulation time 693142053 ps
CPU time 19.82 seconds
Started Jul 07 06:59:56 PM PDT 24
Finished Jul 07 07:00:16 PM PDT 24
Peak memory 217700 kb
Host smart-5a95493f-4d34-4ed5-8cc7-38b99053caa2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483191907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.2483191907
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.620550661
Short name T662
Test name
Test status
Simulation time 3858317295 ps
CPU time 27.26 seconds
Started Jul 07 06:59:55 PM PDT 24
Finished Jul 07 07:00:22 PM PDT 24
Peak memory 217212 kb
Host smart-5f25da49-4724-4dab-ac85-12c15ef3caa5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620550661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_j
tag_regwen_during_op.620550661
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.3445305219
Short name T1
Test name
Test status
Simulation time 410565838 ps
CPU time 6.27 seconds
Started Jul 07 06:59:51 PM PDT 24
Finished Jul 07 06:59:57 PM PDT 24
Peak memory 217120 kb
Host smart-a96bae0b-5b7b-442b-bdf4-a1a82e20e237
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445305219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
3445305219
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.1676518552
Short name T784
Test name
Test status
Simulation time 5986368710 ps
CPU time 35.19 seconds
Started Jul 07 06:59:54 PM PDT 24
Finished Jul 07 07:00:30 PM PDT 24
Peak memory 269136 kb
Host smart-ae65a373-567a-49a0-80d4-fddad3e809dd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676518552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.1676518552
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.740905773
Short name T357
Test name
Test status
Simulation time 1198548352 ps
CPU time 28.39 seconds
Started Jul 07 06:59:53 PM PDT 24
Finished Jul 07 07:00:21 PM PDT 24
Peak memory 250352 kb
Host smart-c830d104-612b-4a0d-bedc-d996dcd0d203
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740905773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_j
tag_state_post_trans.740905773
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.1859743260
Short name T342
Test name
Test status
Simulation time 511251251 ps
CPU time 5.25 seconds
Started Jul 07 06:59:53 PM PDT 24
Finished Jul 07 06:59:59 PM PDT 24
Peak memory 222168 kb
Host smart-c856fd90-10b1-432c-894d-1fd4b700d95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859743260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.1859743260
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.1433575510
Short name T454
Test name
Test status
Simulation time 293287396 ps
CPU time 10.73 seconds
Started Jul 07 06:59:52 PM PDT 24
Finished Jul 07 07:00:03 PM PDT 24
Peak memory 217200 kb
Host smart-b7c0b610-e563-440a-ae0f-a00d2433bdca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433575510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.1433575510
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.3256606585
Short name T317
Test name
Test status
Simulation time 482279344 ps
CPU time 16.47 seconds
Started Jul 07 06:59:55 PM PDT 24
Finished Jul 07 07:00:12 PM PDT 24
Peak memory 225560 kb
Host smart-42bbebc4-a3d3-4895-b945-db22dd09d787
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256606585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.3256606585
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.1257902309
Short name T443
Test name
Test status
Simulation time 1492297000 ps
CPU time 16.49 seconds
Started Jul 07 06:59:59 PM PDT 24
Finished Jul 07 07:00:16 PM PDT 24
Peak memory 225484 kb
Host smart-a14d5a72-3072-4729-a961-499e21046c03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257902309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.1257902309
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.615937306
Short name T502
Test name
Test status
Simulation time 2191966505 ps
CPU time 11.42 seconds
Started Jul 07 07:00:04 PM PDT 24
Finished Jul 07 07:00:15 PM PDT 24
Peak memory 217796 kb
Host smart-f7969359-9c31-408d-a4cd-19da607ccf74
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615937306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.615937306
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.1547111994
Short name T193
Test name
Test status
Simulation time 1036290977 ps
CPU time 11.8 seconds
Started Jul 07 06:59:53 PM PDT 24
Finished Jul 07 07:00:05 PM PDT 24
Peak memory 225588 kb
Host smart-c62fbd32-80d7-48c7-aaa3-c00babcc51c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547111994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.1547111994
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.1106608541
Short name T233
Test name
Test status
Simulation time 79970434 ps
CPU time 3.57 seconds
Started Jul 07 06:59:50 PM PDT 24
Finished Jul 07 06:59:53 PM PDT 24
Peak memory 217196 kb
Host smart-15ebbda3-0787-4e81-acce-9341372419f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106608541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.1106608541
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.3306727138
Short name T245
Test name
Test status
Simulation time 245279970 ps
CPU time 26.2 seconds
Started Jul 07 06:59:51 PM PDT 24
Finished Jul 07 07:00:18 PM PDT 24
Peak memory 250528 kb
Host smart-b8b6afc1-1503-40ce-89ad-d9f82805a0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306727138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.3306727138
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.163075390
Short name T220
Test name
Test status
Simulation time 697537396 ps
CPU time 9 seconds
Started Jul 07 06:59:52 PM PDT 24
Finished Jul 07 07:00:01 PM PDT 24
Peak memory 250540 kb
Host smart-3254c842-561c-4483-9905-fdf6468dc380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163075390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.163075390
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.2451114000
Short name T392
Test name
Test status
Simulation time 115056589095 ps
CPU time 261.99 seconds
Started Jul 07 07:00:02 PM PDT 24
Finished Jul 07 07:04:24 PM PDT 24
Peak memory 221704 kb
Host smart-c59bb37b-7e55-42e3-9889-357f89b56653
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451114000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.2451114000
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.3868512009
Short name T43
Test name
Test status
Simulation time 26518530 ps
CPU time 0.97 seconds
Started Jul 07 06:59:55 PM PDT 24
Finished Jul 07 06:59:57 PM PDT 24
Peak memory 208512 kb
Host smart-c316718b-40aa-403e-a3c0-7082013220df
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868512009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.3868512009
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.3540068691
Short name T202
Test name
Test status
Simulation time 35149248 ps
CPU time 0.91 seconds
Started Jul 07 07:00:07 PM PDT 24
Finished Jul 07 07:00:08 PM PDT 24
Peak memory 208812 kb
Host smart-454d4e96-e869-4ef4-8fc0-9594f19fe73d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540068691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.3540068691
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.3392600585
Short name T830
Test name
Test status
Simulation time 359759446 ps
CPU time 7.97 seconds
Started Jul 07 07:00:03 PM PDT 24
Finished Jul 07 07:00:12 PM PDT 24
Peak memory 217788 kb
Host smart-28a706ad-8e61-4d84-9e2a-f3ac88115d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392600585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.3392600585
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.173626584
Short name T386
Test name
Test status
Simulation time 102145774 ps
CPU time 2.03 seconds
Started Jul 07 07:00:03 PM PDT 24
Finished Jul 07 07:00:05 PM PDT 24
Peak memory 217120 kb
Host smart-4eea30e2-204b-4764-baf1-4293117bcead
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173626584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.173626584
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.3993662868
Short name T801
Test name
Test status
Simulation time 4823333494 ps
CPU time 43.24 seconds
Started Jul 07 07:00:01 PM PDT 24
Finished Jul 07 07:00:45 PM PDT 24
Peak memory 217756 kb
Host smart-acf440b9-5567-46e7-9079-f695f385a4be
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993662868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.3993662868
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.825915057
Short name T462
Test name
Test status
Simulation time 1428625913 ps
CPU time 4.04 seconds
Started Jul 07 07:00:04 PM PDT 24
Finished Jul 07 07:00:08 PM PDT 24
Peak memory 217280 kb
Host smart-48f4e4e0-6f62-4636-accd-870721e56578
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825915057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.825915057
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.2689568278
Short name T500
Test name
Test status
Simulation time 966332871 ps
CPU time 3.43 seconds
Started Jul 07 07:00:05 PM PDT 24
Finished Jul 07 07:00:09 PM PDT 24
Peak memory 217868 kb
Host smart-5baf3980-6bc5-4caf-809c-6085bc51c79e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689568278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.2689568278
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.2965257143
Short name T88
Test name
Test status
Simulation time 4517587979 ps
CPU time 32.38 seconds
Started Jul 07 07:00:08 PM PDT 24
Finished Jul 07 07:00:40 PM PDT 24
Peak memory 217112 kb
Host smart-6f959465-2806-4c7b-a92a-128a53b6da7c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965257143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.2965257143
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.1371066081
Short name T589
Test name
Test status
Simulation time 737195024 ps
CPU time 4.61 seconds
Started Jul 07 07:00:03 PM PDT 24
Finished Jul 07 07:00:08 PM PDT 24
Peak memory 217372 kb
Host smart-fb98ab71-9332-4d6e-93f5-c565ef5df1f2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371066081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
1371066081
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.795081734
Short name T349
Test name
Test status
Simulation time 2310690001 ps
CPU time 77.38 seconds
Started Jul 07 07:00:05 PM PDT 24
Finished Jul 07 07:01:23 PM PDT 24
Peak memory 266940 kb
Host smart-303b0b33-09ae-47eb-9a61-e53915032d04
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795081734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_state_failure.795081734
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.2115969328
Short name T15
Test name
Test status
Simulation time 852265176 ps
CPU time 13.22 seconds
Started Jul 07 07:00:06 PM PDT 24
Finished Jul 07 07:00:20 PM PDT 24
Peak memory 222544 kb
Host smart-596d80e4-1573-45ac-817f-0c2475b429a1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115969328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.2115969328
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.1084734101
Short name T463
Test name
Test status
Simulation time 54842670 ps
CPU time 2.56 seconds
Started Jul 07 07:00:04 PM PDT 24
Finished Jul 07 07:00:06 PM PDT 24
Peak memory 217776 kb
Host smart-5b3a20d4-6cf3-4a50-b8ab-eeba7ee1450e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084734101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.1084734101
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.2018990491
Short name T34
Test name
Test status
Simulation time 1673551307 ps
CPU time 25.29 seconds
Started Jul 07 07:00:05 PM PDT 24
Finished Jul 07 07:00:30 PM PDT 24
Peak memory 217192 kb
Host smart-53ffa2e5-e64f-44ee-8888-96e3073076a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018990491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.2018990491
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.400166165
Short name T827
Test name
Test status
Simulation time 1135731046 ps
CPU time 15.11 seconds
Started Jul 07 07:00:12 PM PDT 24
Finished Jul 07 07:00:27 PM PDT 24
Peak memory 218512 kb
Host smart-4ffe753a-b26c-4dff-8db2-f594b1521505
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400166165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.400166165
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.3836476891
Short name T210
Test name
Test status
Simulation time 514218615 ps
CPU time 11.14 seconds
Started Jul 07 07:00:12 PM PDT 24
Finished Jul 07 07:00:23 PM PDT 24
Peak memory 225516 kb
Host smart-cbef558c-fb5c-4dfd-affd-a3692cf2e6cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836476891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.3836476891
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.2236856343
Short name T274
Test name
Test status
Simulation time 341239642 ps
CPU time 8.2 seconds
Started Jul 07 07:00:12 PM PDT 24
Finished Jul 07 07:00:20 PM PDT 24
Peak memory 217736 kb
Host smart-550468d2-3700-4c43-a63a-7093cc9641ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236856343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.2
236856343
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.2018869813
Short name T7
Test name
Test status
Simulation time 33884231 ps
CPU time 2.67 seconds
Started Jul 07 06:59:58 PM PDT 24
Finished Jul 07 07:00:01 PM PDT 24
Peak memory 214184 kb
Host smart-92a69dc8-aba7-475d-b8ad-215254a99637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018869813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.2018869813
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.3711816161
Short name T698
Test name
Test status
Simulation time 267985189 ps
CPU time 27.14 seconds
Started Jul 07 07:00:02 PM PDT 24
Finished Jul 07 07:00:29 PM PDT 24
Peak memory 250516 kb
Host smart-12d760c7-4cef-4e1b-8d4d-261bd8a730e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711816161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.3711816161
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.3918823688
Short name T341
Test name
Test status
Simulation time 1070108901 ps
CPU time 13.42 seconds
Started Jul 07 07:00:01 PM PDT 24
Finished Jul 07 07:00:14 PM PDT 24
Peak memory 250528 kb
Host smart-31239630-05ef-4653-929a-7639dc434677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918823688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.3918823688
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.2133370749
Short name T464
Test name
Test status
Simulation time 11449975944 ps
CPU time 55.09 seconds
Started Jul 07 07:00:12 PM PDT 24
Finished Jul 07 07:01:08 PM PDT 24
Peak memory 252036 kb
Host smart-79e8328d-5d85-4749-a1c1-6d79ea91a065
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133370749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.2133370749
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.4180690029
Short name T367
Test name
Test status
Simulation time 43331948110 ps
CPU time 440.62 seconds
Started Jul 07 07:00:08 PM PDT 24
Finished Jul 07 07:07:29 PM PDT 24
Peak memory 316060 kb
Host smart-38befd11-5351-488f-a79a-1a867f749cd0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4180690029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all_with_rand_reset.4180690029
Directory /workspace/7.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.2200134820
Short name T679
Test name
Test status
Simulation time 15822581 ps
CPU time 1 seconds
Started Jul 07 07:00:00 PM PDT 24
Finished Jul 07 07:00:01 PM PDT 24
Peak memory 211300 kb
Host smart-6a45cca5-286a-4d45-8f44-e50c029bdf18
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200134820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.2200134820
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.1038587468
Short name T279
Test name
Test status
Simulation time 11134577 ps
CPU time 0.88 seconds
Started Jul 07 07:00:14 PM PDT 24
Finished Jul 07 07:00:15 PM PDT 24
Peak memory 208352 kb
Host smart-806f287a-6ea8-472a-8391-53212dc1bfe2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038587468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.1038587468
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.4107277846
Short name T408
Test name
Test status
Simulation time 230801819 ps
CPU time 10.77 seconds
Started Jul 07 07:00:09 PM PDT 24
Finished Jul 07 07:00:20 PM PDT 24
Peak memory 217704 kb
Host smart-6db5151d-dd86-446d-8d33-50220c3d48bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107277846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.4107277846
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.3892928891
Short name T325
Test name
Test status
Simulation time 1341261074 ps
CPU time 16.02 seconds
Started Jul 07 07:00:12 PM PDT 24
Finished Jul 07 07:00:28 PM PDT 24
Peak memory 217204 kb
Host smart-f6fc0eb9-e472-4257-95b5-86caea4489da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892928891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.3892928891
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.913606275
Short name T725
Test name
Test status
Simulation time 1960405161 ps
CPU time 35.4 seconds
Started Jul 07 07:00:09 PM PDT 24
Finished Jul 07 07:00:45 PM PDT 24
Peak memory 217660 kb
Host smart-717905f0-a7aa-435b-a86b-7f4419ef1feb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913606275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_err
ors.913606275
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.2531914392
Short name T366
Test name
Test status
Simulation time 4939390283 ps
CPU time 7.14 seconds
Started Jul 07 07:00:10 PM PDT 24
Finished Jul 07 07:00:18 PM PDT 24
Peak memory 217320 kb
Host smart-de155e7e-5b81-480e-8ab9-2a2104bb6c73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531914392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.2
531914392
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.3159210138
Short name T201
Test name
Test status
Simulation time 611641009 ps
CPU time 7.61 seconds
Started Jul 07 07:00:13 PM PDT 24
Finished Jul 07 07:00:20 PM PDT 24
Peak memory 217708 kb
Host smart-8684a590-3383-4a7c-80b0-e17a69ab832b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159210138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.3159210138
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.3604933587
Short name T241
Test name
Test status
Simulation time 5745017869 ps
CPU time 18.66 seconds
Started Jul 07 07:00:09 PM PDT 24
Finished Jul 07 07:00:28 PM PDT 24
Peak memory 217180 kb
Host smart-a89d2913-3ae9-4d23-b935-133a6ba0f57d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604933587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.3604933587
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.429175926
Short name T716
Test name
Test status
Simulation time 466609213 ps
CPU time 6.23 seconds
Started Jul 07 07:00:11 PM PDT 24
Finished Jul 07 07:00:17 PM PDT 24
Peak memory 217204 kb
Host smart-96f235c0-3154-4fb4-b032-c6a0acba3378
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429175926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.429175926
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.2653590669
Short name T861
Test name
Test status
Simulation time 13876218185 ps
CPU time 69.58 seconds
Started Jul 07 07:00:12 PM PDT 24
Finished Jul 07 07:01:22 PM PDT 24
Peak memory 278252 kb
Host smart-fe660992-ef3b-4563-8d53-4293f84a2573
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653590669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.2653590669
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.2060145930
Short name T543
Test name
Test status
Simulation time 965154226 ps
CPU time 12.83 seconds
Started Jul 07 07:00:13 PM PDT 24
Finished Jul 07 07:00:26 PM PDT 24
Peak memory 250280 kb
Host smart-ae62fe86-5890-4f58-a913-b5326ee129f3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060145930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.2060145930
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.1096245504
Short name T197
Test name
Test status
Simulation time 102135651 ps
CPU time 2.61 seconds
Started Jul 07 07:00:07 PM PDT 24
Finished Jul 07 07:00:10 PM PDT 24
Peak memory 221916 kb
Host smart-45b0940d-73f3-45ca-8ea6-cde580e8bb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096245504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.1096245504
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.1391272875
Short name T613
Test name
Test status
Simulation time 669438461 ps
CPU time 8.07 seconds
Started Jul 07 07:00:09 PM PDT 24
Finished Jul 07 07:00:18 PM PDT 24
Peak memory 217108 kb
Host smart-85027f6b-3ba5-4710-8d8f-0d2278bf8fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391272875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.1391272875
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.3805714338
Short name T821
Test name
Test status
Simulation time 364878138 ps
CPU time 11.16 seconds
Started Jul 07 07:00:15 PM PDT 24
Finished Jul 07 07:00:27 PM PDT 24
Peak memory 225520 kb
Host smart-68ce0e72-ab35-4a6d-90b2-fee957001732
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805714338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.3805714338
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.3631355900
Short name T207
Test name
Test status
Simulation time 667431649 ps
CPU time 9.96 seconds
Started Jul 07 07:00:15 PM PDT 24
Finished Jul 07 07:00:25 PM PDT 24
Peak memory 225528 kb
Host smart-92668c52-320e-4f06-bbd9-5d129e4c1ca7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631355900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.3
631355900
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.2849187411
Short name T703
Test name
Test status
Simulation time 1397544356 ps
CPU time 12.31 seconds
Started Jul 07 07:00:05 PM PDT 24
Finished Jul 07 07:00:18 PM PDT 24
Peak memory 225556 kb
Host smart-577a2b7b-f573-4c4c-b9df-3d8b9b8b3ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849187411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.2849187411
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.920094687
Short name T312
Test name
Test status
Simulation time 552003599 ps
CPU time 10.83 seconds
Started Jul 07 07:00:05 PM PDT 24
Finished Jul 07 07:00:16 PM PDT 24
Peak memory 217204 kb
Host smart-630fbf38-018d-456a-96e9-2f5f20eb8c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920094687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.920094687
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.1839929721
Short name T268
Test name
Test status
Simulation time 678353971 ps
CPU time 18.17 seconds
Started Jul 07 07:00:06 PM PDT 24
Finished Jul 07 07:00:25 PM PDT 24
Peak memory 250504 kb
Host smart-20c1025b-015f-411d-9dc6-66814e3c9bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839929721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.1839929721
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.2465955024
Short name T580
Test name
Test status
Simulation time 59936786 ps
CPU time 6.69 seconds
Started Jul 07 07:00:05 PM PDT 24
Finished Jul 07 07:00:12 PM PDT 24
Peak memory 250096 kb
Host smart-45b0ac7d-e25a-42c0-9824-ea2c090ac4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465955024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.2465955024
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.3028922696
Short name T77
Test name
Test status
Simulation time 10745194618 ps
CPU time 76.64 seconds
Started Jul 07 07:00:15 PM PDT 24
Finished Jul 07 07:01:32 PM PDT 24
Peak memory 270100 kb
Host smart-c9fa8e6f-1ab2-4b68-bb20-2ace06c0f917
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028922696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.3028922696
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.3002944707
Short name T41
Test name
Test status
Simulation time 116344364077 ps
CPU time 745.63 seconds
Started Jul 07 07:00:13 PM PDT 24
Finished Jul 07 07:12:39 PM PDT 24
Peak memory 496464 kb
Host smart-2a626293-b493-4abe-8677-93be5ab642d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3002944707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.3002944707
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.1734402278
Short name T429
Test name
Test status
Simulation time 45381260 ps
CPU time 0.93 seconds
Started Jul 07 07:00:06 PM PDT 24
Finished Jul 07 07:00:07 PM PDT 24
Peak memory 211304 kb
Host smart-dd329ad8-dff0-43c6-9433-f70744bb15d2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734402278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.1734402278
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.1035904024
Short name T221
Test name
Test status
Simulation time 17148884 ps
CPU time 0.96 seconds
Started Jul 07 07:00:22 PM PDT 24
Finished Jul 07 07:00:23 PM PDT 24
Peak memory 208752 kb
Host smart-ba0f0ddd-b6f4-4f1c-a5cf-acbd85578138
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035904024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.1035904024
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.2109129442
Short name T638
Test name
Test status
Simulation time 16257698 ps
CPU time 0.92 seconds
Started Jul 07 07:00:16 PM PDT 24
Finished Jul 07 07:00:18 PM PDT 24
Peak memory 208432 kb
Host smart-caaf0e78-e2d3-42be-b96a-402c026b0c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109129442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.2109129442
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.2161093888
Short name T774
Test name
Test status
Simulation time 1021002224 ps
CPU time 13.73 seconds
Started Jul 07 07:00:16 PM PDT 24
Finished Jul 07 07:00:30 PM PDT 24
Peak memory 217788 kb
Host smart-b7466df0-ebf9-464c-9809-be930a764201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161093888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.2161093888
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.1548863547
Short name T22
Test name
Test status
Simulation time 419271448 ps
CPU time 2 seconds
Started Jul 07 07:00:23 PM PDT 24
Finished Jul 07 07:00:26 PM PDT 24
Peak memory 217492 kb
Host smart-1c501cce-b4f8-4708-b563-488e79bc5607
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548863547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.1548863547
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.433799386
Short name T389
Test name
Test status
Simulation time 3733052754 ps
CPU time 31.7 seconds
Started Jul 07 07:00:23 PM PDT 24
Finished Jul 07 07:00:55 PM PDT 24
Peak memory 218512 kb
Host smart-a62beec4-d7e2-4999-8492-7d474077259a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433799386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_err
ors.433799386
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.297605153
Short name T631
Test name
Test status
Simulation time 1928382310 ps
CPU time 20.53 seconds
Started Jul 07 07:00:21 PM PDT 24
Finished Jul 07 07:00:42 PM PDT 24
Peak memory 217204 kb
Host smart-8eefee2d-d7fa-4cf2-a386-a8c64ff8f775
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297605153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.297605153
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.4146726804
Short name T753
Test name
Test status
Simulation time 1227933533 ps
CPU time 8.64 seconds
Started Jul 07 07:00:18 PM PDT 24
Finished Jul 07 07:00:27 PM PDT 24
Peak memory 217696 kb
Host smart-dc89a15e-ca71-44bd-ba68-119e40f9653b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146726804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.4146726804
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.3156471353
Short name T232
Test name
Test status
Simulation time 768592648 ps
CPU time 11.38 seconds
Started Jul 07 07:00:21 PM PDT 24
Finished Jul 07 07:00:33 PM PDT 24
Peak memory 217128 kb
Host smart-a23a60d7-4ccc-400e-b322-4824fe7af407
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156471353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.3156471353
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.2749371356
Short name T291
Test name
Test status
Simulation time 648788611 ps
CPU time 4.64 seconds
Started Jul 07 07:00:15 PM PDT 24
Finished Jul 07 07:00:20 PM PDT 24
Peak memory 217244 kb
Host smart-8b94d786-d529-4bbf-bce7-07842bb48e53
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749371356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
2749371356
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.665338346
Short name T691
Test name
Test status
Simulation time 5046793072 ps
CPU time 55.48 seconds
Started Jul 07 07:00:17 PM PDT 24
Finished Jul 07 07:01:12 PM PDT 24
Peak memory 266896 kb
Host smart-a285e7f7-19b9-461a-a69f-c833a40b325c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665338346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_state_failure.665338346
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.3423458198
Short name T756
Test name
Test status
Simulation time 1813992901 ps
CPU time 17.35 seconds
Started Jul 07 07:00:19 PM PDT 24
Finished Jul 07 07:00:37 PM PDT 24
Peak memory 250456 kb
Host smart-b2aa6124-95cc-401d-a80f-41d3eade716a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423458198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.3423458198
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.3581923687
Short name T213
Test name
Test status
Simulation time 35319865 ps
CPU time 2.42 seconds
Started Jul 07 07:00:14 PM PDT 24
Finished Jul 07 07:00:17 PM PDT 24
Peak memory 217700 kb
Host smart-805647f4-b590-4391-bafb-359fe0306fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581923687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.3581923687
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.4192647010
Short name T447
Test name
Test status
Simulation time 275719919 ps
CPU time 11.44 seconds
Started Jul 07 07:00:19 PM PDT 24
Finished Jul 07 07:00:30 PM PDT 24
Peak memory 213636 kb
Host smart-81e75356-cd87-4032-abd7-56afae024a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192647010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.4192647010
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.529981335
Short name T740
Test name
Test status
Simulation time 1083140065 ps
CPU time 15.31 seconds
Started Jul 07 07:00:22 PM PDT 24
Finished Jul 07 07:00:38 PM PDT 24
Peak memory 225580 kb
Host smart-8e02ad45-f5d0-48bf-b970-c5e3559c00aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529981335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.529981335
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.4034091690
Short name T294
Test name
Test status
Simulation time 270187685 ps
CPU time 8.15 seconds
Started Jul 07 07:00:22 PM PDT 24
Finished Jul 07 07:00:30 PM PDT 24
Peak memory 225500 kb
Host smart-b3a5197a-0d1a-4a90-99b1-a1b106209b55
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034091690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.4034091690
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.2379357161
Short name T338
Test name
Test status
Simulation time 469589209 ps
CPU time 9.73 seconds
Started Jul 07 07:00:21 PM PDT 24
Finished Jul 07 07:00:31 PM PDT 24
Peak memory 217968 kb
Host smart-2043fe0c-01f4-47a3-8999-670353cb8d31
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379357161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.2
379357161
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.681432924
Short name T59
Test name
Test status
Simulation time 310565496 ps
CPU time 10.87 seconds
Started Jul 07 07:00:16 PM PDT 24
Finished Jul 07 07:00:27 PM PDT 24
Peak memory 217868 kb
Host smart-95b8e4e8-1b08-40ac-9d03-0c62119d2dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681432924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.681432924
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.440322785
Short name T590
Test name
Test status
Simulation time 86169128 ps
CPU time 2.23 seconds
Started Jul 07 07:00:15 PM PDT 24
Finished Jul 07 07:00:17 PM PDT 24
Peak memory 217188 kb
Host smart-8f1cfa40-0149-43e6-8420-b530a4aca81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440322785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.440322785
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.713637596
Short name T442
Test name
Test status
Simulation time 204606576 ps
CPU time 21.71 seconds
Started Jul 07 07:00:15 PM PDT 24
Finished Jul 07 07:00:37 PM PDT 24
Peak memory 250548 kb
Host smart-420f4c9d-50bc-45b4-a020-52064c9dd966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713637596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.713637596
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.1900347123
Short name T832
Test name
Test status
Simulation time 284904339 ps
CPU time 5.97 seconds
Started Jul 07 07:00:14 PM PDT 24
Finished Jul 07 07:00:20 PM PDT 24
Peak memory 246504 kb
Host smart-95d48c1e-dfa3-4c48-be8b-16aa626e5259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900347123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.1900347123
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.2273079513
Short name T758
Test name
Test status
Simulation time 7024626841 ps
CPU time 273.21 seconds
Started Jul 07 07:00:20 PM PDT 24
Finished Jul 07 07:04:54 PM PDT 24
Peak memory 250592 kb
Host smart-2c081e03-d478-4f53-a167-702bc00fc286
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273079513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.2273079513
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.3575148011
Short name T506
Test name
Test status
Simulation time 95057423 ps
CPU time 1.01 seconds
Started Jul 07 07:00:16 PM PDT 24
Finished Jul 07 07:00:17 PM PDT 24
Peak memory 211372 kb
Host smart-27a9dc5c-2046-42a6-9dd8-baa79fe612d7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575148011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.3575148011
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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