Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53828 |
1 |
|
|
T1 |
15 |
|
T4 |
7 |
|
T10 |
14 |
auto[1] |
1868 |
1 |
|
|
T5 |
13 |
|
T8 |
5 |
|
T15 |
15 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55119 |
1 |
|
|
T1 |
15 |
|
T4 |
7 |
|
T10 |
14 |
auto[1] |
577 |
1 |
|
|
T41 |
14 |
|
T42 |
12 |
|
T58 |
11 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53595 |
1 |
|
|
T1 |
15 |
|
T4 |
7 |
|
T10 |
13 |
auto[1] |
2101 |
1 |
|
|
T10 |
1 |
|
T13 |
3 |
|
T62 |
5 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53505 |
1 |
|
|
T1 |
15 |
|
T4 |
7 |
|
T10 |
14 |
auto[1] |
2191 |
1 |
|
|
T5 |
1 |
|
T13 |
4 |
|
T62 |
7 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53609 |
1 |
|
|
T1 |
15 |
|
T4 |
7 |
|
T10 |
14 |
auto[1] |
2087 |
1 |
|
|
T5 |
2 |
|
T13 |
7 |
|
T8 |
1 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
50461 |
1 |
|
|
T1 |
4 |
|
T10 |
8 |
|
T5 |
146 |
no_err_inj |
5235 |
1 |
|
|
T1 |
11 |
|
T4 |
7 |
|
T10 |
6 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53895 |
1 |
|
|
T1 |
15 |
|
T4 |
7 |
|
T10 |
14 |
auto[1] |
1801 |
1 |
|
|
T5 |
22 |
|
T8 |
2 |
|
T15 |
6 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55112 |
1 |
|
|
T1 |
15 |
|
T4 |
7 |
|
T10 |
14 |
auto[1] |
584 |
1 |
|
|
T41 |
16 |
|
T42 |
12 |
|
T58 |
10 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40403 |
1 |
|
|
T1 |
15 |
|
T10 |
14 |
|
T11 |
16 |
auto[1] |
15293 |
1 |
|
|
T4 |
7 |
|
T5 |
72 |
|
T8 |
39 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53620 |
1 |
|
|
T1 |
15 |
|
T4 |
7 |
|
T10 |
13 |
auto[1] |
2076 |
1 |
|
|
T10 |
1 |
|
T5 |
1 |
|
T13 |
10 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53620 |
1 |
|
|
T1 |
14 |
|
T4 |
7 |
|
T10 |
12 |
auto[1] |
2076 |
1 |
|
|
T1 |
1 |
|
T10 |
2 |
|
T5 |
1 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53556 |
1 |
|
|
T1 |
14 |
|
T4 |
7 |
|
T10 |
14 |
auto[1] |
2140 |
1 |
|
|
T1 |
1 |
|
T5 |
1 |
|
T13 |
9 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53774 |
1 |
|
|
T1 |
15 |
|
T4 |
7 |
|
T10 |
14 |
auto[1] |
1922 |
1 |
|
|
T5 |
15 |
|
T8 |
9 |
|
T15 |
12 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53206 |
1 |
|
|
T1 |
15 |
|
T4 |
7 |
|
T10 |
14 |
auto[1] |
2490 |
1 |
|
|
T5 |
3 |
|
T8 |
3 |
|
T15 |
71 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55059 |
1 |
|
|
T1 |
15 |
|
T4 |
7 |
|
T10 |
14 |
auto[1] |
637 |
1 |
|
|
T41 |
27 |
|
T42 |
12 |
|
T58 |
14 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55072 |
1 |
|
|
T1 |
15 |
|
T4 |
7 |
|
T10 |
14 |
auto[1] |
624 |
1 |
|
|
T41 |
17 |
|
T42 |
11 |
|
T58 |
19 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55137 |
1 |
|
|
T1 |
15 |
|
T4 |
7 |
|
T10 |
14 |
auto[1] |
559 |
1 |
|
|
T41 |
14 |
|
T42 |
17 |
|
T58 |
15 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52740 |
1 |
|
|
T4 |
7 |
|
T11 |
16 |
|
T5 |
173 |
auto[1] |
2956 |
1 |
|
|
T1 |
15 |
|
T10 |
14 |
|
T5 |
10 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51962 |
1 |
|
|
T1 |
15 |
|
T4 |
7 |
|
T10 |
14 |
auto[1] |
3734 |
1 |
|
|
T34 |
58 |
|
T46 |
66 |
|
T47 |
89 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53627 |
1 |
|
|
T1 |
14 |
|
T4 |
7 |
|
T10 |
14 |
auto[1] |
2069 |
1 |
|
|
T1 |
1 |
|
T13 |
5 |
|
T62 |
6 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53657 |
1 |
|
|
T1 |
14 |
|
T4 |
7 |
|
T10 |
11 |
auto[1] |
2039 |
1 |
|
|
T1 |
1 |
|
T10 |
3 |
|
T13 |
3 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53595 |
1 |
|
|
T1 |
15 |
|
T4 |
7 |
|
T10 |
13 |
auto[1] |
2101 |
1 |
|
|
T10 |
1 |
|
T13 |
1 |
|
T62 |
8 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53827 |
1 |
|
|
T1 |
15 |
|
T4 |
7 |
|
T10 |
14 |
auto[1] |
1869 |
1 |
|
|
T5 |
16 |
|
T8 |
5 |
|
T15 |
13 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49991 |
1 |
|
|
T1 |
15 |
|
T4 |
7 |
|
T10 |
14 |
auto[1] |
5705 |
1 |
|
|
T5 |
18 |
|
T8 |
5 |
|
T15 |
14 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51992 |
1 |
|
|
T1 |
15 |
|
T4 |
7 |
|
T10 |
14 |
auto[1] |
3704 |
1 |
|
|
T33 |
50 |
|
T56 |
89 |
|
T57 |
61 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55696 |
1 |
|
|
T1 |
15 |
|
T4 |
7 |
|
T10 |
14 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53862 |
1 |
|
|
T1 |
15 |
|
T4 |
7 |
|
T10 |
14 |
auto[1] |
1834 |
1 |
|
|
T5 |
18 |
|
T8 |
7 |
|
T15 |
12 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53816 |
1 |
|
|
T1 |
15 |
|
T4 |
7 |
|
T10 |
14 |
auto[1] |
1880 |
1 |
|
|
T5 |
16 |
|
T8 |
10 |
|
T15 |
5 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53903 |
1 |
|
|
T1 |
15 |
|
T4 |
7 |
|
T10 |
14 |
auto[1] |
1793 |
1 |
|
|
T5 |
19 |
|
T8 |
7 |
|
T15 |
7 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
49005 |
1 |
|
|
T5 |
140 |
|
T13 |
55 |
|
T8 |
53 |
auto[0] |
no_err_inj |
3735 |
1 |
|
|
T4 |
7 |
|
T11 |
16 |
|
T5 |
33 |
auto[1] |
err_inj |
1456 |
1 |
|
|
T1 |
4 |
|
T10 |
8 |
|
T5 |
6 |
auto[1] |
no_err_inj |
1500 |
1 |
|
|
T1 |
11 |
|
T10 |
6 |
|
T5 |
4 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50865 |
1 |
|
|
T4 |
7 |
|
T11 |
16 |
|
T5 |
173 |
auto[0] |
auto[1] |
1875 |
1 |
|
|
T13 |
3 |
|
T62 |
5 |
|
T15 |
69 |
auto[1] |
auto[0] |
2792 |
1 |
|
|
T1 |
14 |
|
T10 |
11 |
|
T5 |
10 |
auto[1] |
auto[1] |
164 |
1 |
|
|
T1 |
1 |
|
T10 |
3 |
|
T15 |
3 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50829 |
1 |
|
|
T4 |
7 |
|
T11 |
16 |
|
T5 |
173 |
auto[0] |
auto[1] |
1911 |
1 |
|
|
T13 |
13 |
|
T62 |
5 |
|
T15 |
63 |
auto[1] |
auto[0] |
2791 |
1 |
|
|
T1 |
14 |
|
T10 |
12 |
|
T5 |
9 |
auto[1] |
auto[1] |
165 |
1 |
|
|
T1 |
1 |
|
T10 |
2 |
|
T5 |
1 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50796 |
1 |
|
|
T4 |
7 |
|
T11 |
16 |
|
T5 |
173 |
auto[0] |
auto[1] |
1944 |
1 |
|
|
T13 |
1 |
|
T62 |
8 |
|
T15 |
60 |
auto[1] |
auto[0] |
2799 |
1 |
|
|
T1 |
15 |
|
T10 |
13 |
|
T5 |
10 |
auto[1] |
auto[1] |
157 |
1 |
|
|
T10 |
1 |
|
T15 |
10 |
|
T31 |
5 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50716 |
1 |
|
|
T4 |
7 |
|
T11 |
16 |
|
T5 |
173 |
auto[0] |
auto[1] |
2024 |
1 |
|
|
T13 |
4 |
|
T62 |
7 |
|
T15 |
58 |
auto[1] |
auto[0] |
2789 |
1 |
|
|
T1 |
15 |
|
T10 |
14 |
|
T5 |
9 |
auto[1] |
auto[1] |
167 |
1 |
|
|
T5 |
1 |
|
T15 |
8 |
|
T31 |
4 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50819 |
1 |
|
|
T4 |
7 |
|
T11 |
16 |
|
T5 |
173 |
auto[0] |
auto[1] |
1921 |
1 |
|
|
T13 |
7 |
|
T62 |
5 |
|
T15 |
60 |
auto[1] |
auto[0] |
2790 |
1 |
|
|
T1 |
15 |
|
T10 |
14 |
|
T5 |
8 |
auto[1] |
auto[1] |
166 |
1 |
|
|
T5 |
2 |
|
T8 |
1 |
|
T15 |
7 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50795 |
1 |
|
|
T4 |
7 |
|
T11 |
16 |
|
T5 |
173 |
auto[0] |
auto[1] |
1945 |
1 |
|
|
T13 |
3 |
|
T62 |
5 |
|
T15 |
69 |
auto[1] |
auto[0] |
2800 |
1 |
|
|
T1 |
15 |
|
T10 |
13 |
|
T5 |
10 |
auto[1] |
auto[1] |
156 |
1 |
|
|
T10 |
1 |
|
T15 |
3 |
|
T31 |
4 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39179 |
1 |
|
|
T1 |
15 |
|
T10 |
14 |
|
T11 |
16 |
auto[0] |
auto[1] |
1224 |
1 |
|
|
T5 |
8 |
|
T8 |
5 |
|
T15 |
15 |
auto[1] |
auto[0] |
14649 |
1 |
|
|
T4 |
7 |
|
T5 |
67 |
|
T8 |
39 |
auto[1] |
auto[1] |
644 |
1 |
|
|
T5 |
5 |
|
T31 |
13 |
|
T38 |
16 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39277 |
1 |
|
|
T1 |
15 |
|
T10 |
14 |
|
T11 |
16 |
auto[0] |
auto[1] |
1126 |
1 |
|
|
T5 |
13 |
|
T8 |
2 |
|
T15 |
6 |
auto[1] |
auto[0] |
14618 |
1 |
|
|
T4 |
7 |
|
T5 |
63 |
|
T8 |
39 |
auto[1] |
auto[1] |
675 |
1 |
|
|
T5 |
9 |
|
T31 |
19 |
|
T38 |
16 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38832 |
1 |
|
|
T1 |
15 |
|
T10 |
14 |
|
T11 |
16 |
auto[0] |
auto[1] |
1571 |
1 |
|
|
T5 |
3 |
|
T8 |
3 |
|
T15 |
49 |
auto[1] |
auto[0] |
14374 |
1 |
|
|
T4 |
7 |
|
T5 |
72 |
|
T8 |
39 |
auto[1] |
auto[1] |
919 |
1 |
|
|
T15 |
22 |
|
T16 |
19 |
|
T19 |
20 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39168 |
1 |
|
|
T1 |
15 |
|
T10 |
14 |
|
T11 |
16 |
auto[0] |
auto[1] |
1235 |
1 |
|
|
T5 |
6 |
|
T8 |
9 |
|
T15 |
12 |
auto[1] |
auto[0] |
14606 |
1 |
|
|
T4 |
7 |
|
T5 |
63 |
|
T8 |
39 |
auto[1] |
auto[1] |
687 |
1 |
|
|
T5 |
9 |
|
T31 |
18 |
|
T38 |
10 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35385 |
1 |
|
|
T1 |
15 |
|
T10 |
14 |
|
T11 |
16 |
auto[0] |
auto[1] |
5018 |
1 |
|
|
T5 |
11 |
|
T8 |
5 |
|
T15 |
14 |
auto[1] |
auto[0] |
14606 |
1 |
|
|
T4 |
7 |
|
T5 |
65 |
|
T8 |
39 |
auto[1] |
auto[1] |
687 |
1 |
|
|
T5 |
7 |
|
T31 |
15 |
|
T38 |
18 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39080 |
1 |
|
|
T1 |
14 |
|
T10 |
11 |
|
T11 |
16 |
auto[0] |
auto[1] |
1323 |
1 |
|
|
T1 |
1 |
|
T10 |
3 |
|
T13 |
3 |
auto[1] |
auto[0] |
14577 |
1 |
|
|
T4 |
7 |
|
T5 |
72 |
|
T8 |
39 |
auto[1] |
auto[1] |
716 |
1 |
|
|
T15 |
47 |
|
T17 |
12 |
|
T18 |
9 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39038 |
1 |
|
|
T1 |
14 |
|
T10 |
14 |
|
T11 |
16 |
auto[0] |
auto[1] |
1365 |
1 |
|
|
T1 |
1 |
|
T13 |
5 |
|
T62 |
6 |
auto[1] |
auto[0] |
14589 |
1 |
|
|
T4 |
7 |
|
T5 |
72 |
|
T8 |
39 |
auto[1] |
auto[1] |
704 |
1 |
|
|
T15 |
61 |
|
T17 |
8 |
|
T18 |
12 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39056 |
1 |
|
|
T1 |
14 |
|
T10 |
12 |
|
T11 |
16 |
auto[0] |
auto[1] |
1347 |
1 |
|
|
T1 |
1 |
|
T10 |
2 |
|
T5 |
1 |
auto[1] |
auto[0] |
14564 |
1 |
|
|
T4 |
7 |
|
T5 |
72 |
|
T8 |
37 |
auto[1] |
auto[1] |
729 |
1 |
|
|
T8 |
2 |
|
T15 |
42 |
|
T17 |
8 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39073 |
1 |
|
|
T1 |
15 |
|
T10 |
13 |
|
T11 |
16 |
auto[0] |
auto[1] |
1330 |
1 |
|
|
T10 |
1 |
|
T5 |
1 |
|
T13 |
10 |
auto[1] |
auto[0] |
14547 |
1 |
|
|
T4 |
7 |
|
T5 |
72 |
|
T8 |
38 |
auto[1] |
auto[1] |
746 |
1 |
|
|
T8 |
1 |
|
T15 |
43 |
|
T17 |
12 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38958 |
1 |
|
|
T1 |
15 |
|
T10 |
14 |
|
T11 |
16 |
auto[0] |
auto[1] |
1445 |
1 |
|
|
T5 |
1 |
|
T13 |
4 |
|
T62 |
7 |
auto[1] |
auto[0] |
14547 |
1 |
|
|
T4 |
7 |
|
T5 |
72 |
|
T8 |
39 |
auto[1] |
auto[1] |
746 |
1 |
|
|
T15 |
42 |
|
T17 |
13 |
|
T18 |
9 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39036 |
1 |
|
|
T1 |
15 |
|
T10 |
13 |
|
T11 |
16 |
auto[0] |
auto[1] |
1367 |
1 |
|
|
T10 |
1 |
|
T13 |
3 |
|
T62 |
5 |
auto[1] |
auto[0] |
14559 |
1 |
|
|
T4 |
7 |
|
T5 |
72 |
|
T8 |
39 |
auto[1] |
auto[1] |
734 |
1 |
|
|
T15 |
51 |
|
T17 |
9 |
|
T18 |
6 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39251 |
1 |
|
|
T1 |
15 |
|
T10 |
14 |
|
T11 |
16 |
auto[0] |
auto[1] |
1152 |
1 |
|
|
T5 |
11 |
|
T8 |
7 |
|
T15 |
7 |
auto[1] |
auto[0] |
14652 |
1 |
|
|
T4 |
7 |
|
T5 |
64 |
|
T8 |
39 |
auto[1] |
auto[1] |
641 |
1 |
|
|
T5 |
8 |
|
T31 |
14 |
|
T38 |
15 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39189 |
1 |
|
|
T1 |
15 |
|
T10 |
14 |
|
T11 |
16 |
auto[0] |
auto[1] |
1214 |
1 |
|
|
T5 |
11 |
|
T8 |
10 |
|
T15 |
5 |
auto[1] |
auto[0] |
14627 |
1 |
|
|
T4 |
7 |
|
T5 |
67 |
|
T8 |
39 |
auto[1] |
auto[1] |
666 |
1 |
|
|
T5 |
5 |
|
T31 |
16 |
|
T38 |
20 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38740 |
1 |
|
|
T11 |
16 |
|
T5 |
101 |
|
T12 |
2 |
auto[0] |
auto[1] |
1663 |
1 |
|
|
T1 |
15 |
|
T10 |
14 |
|
T5 |
10 |
auto[1] |
auto[0] |
14000 |
1 |
|
|
T4 |
7 |
|
T5 |
72 |
|
T8 |
26 |
auto[1] |
auto[1] |
1293 |
1 |
|
|
T8 |
13 |
|
T15 |
10 |
|
T191 |
10 |