Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

106983464

1

T1

8281

T2

21924

T3

28415

auto[1]

1470339

1

T1

99

T10

396

T5

990

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

106977277

1

T1

8182

T2

21924

T3

28415

auto[1]

1476526

1

T1

198

T10

297

T5

1089

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7186226	1			T1	1598		T2	12189		T3	118
auto[IdleSt]	20879958	1			T1	1796		T2	3711		T3	28297
auto[ClkMuxSt]	35872	1			T1	11		T4	7		T10	6
auto[CntIncrSt]	35478	1			T1	11		T4	7		T10	6
auto[CntProgSt]	1710996	1			T1	500		T4	14		T10	12
auto[TransCheckSt]	27440	1			T1	11		T4	7		T10	6
auto[TokenHashSt]	49404500	1			T1	120		T4	80878		T10	241
auto[FlashRmaSt]	35912	1			T1	46		T4	7		T10	47
auto[TokenCheck0St]	12796	1			T1	11		T4	7		T10	6
auto[TokenCheck1St]	9720	1			T1	11		T4	7		T10	6
auto[TransProgSt]	440241	1			T1	410		T4	14		T10	12
auto[PostTransSt]	12371454	1			T1	2802		T4	1736		T9	970
auto[ScrapSt]	386034	1			T2	317		T5	494		T8	499
auto[EscalateSt]	6370707	1			T1	632		T10	1210		T5	5625
auto[InvalidSt]	9544299	1			T1	420		T2	5687		T10	503

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2170	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	9544299	1			T1	420		T2	5687		T10	503
EscalateSt	6370707	1			T1	632		T10	1210		T5	5625
ScrapSt	386034	1			T2	317		T5	494		T8	499
PostTransSt	12371454	1			T1	2802		T4	1736		T9	970
TransProgSt	440241	1			T1	410		T4	14		T10	12
TokenCheck1St	9720	1			T1	11		T4	7		T10	6
TokenCheck0St	12796	1			T1	11		T4	7		T10	6
FlashRmaSt	35912	1			T1	46		T4	7		T10	47
TokenHashSt	49404500	1			T1	120		T4	80878		T10	241
TransCheckSt	27440	1			T1	11		T4	7		T10	6
CntProgSt	1710996	1			T1	500		T4	14		T10	12
CntIncrSt	35478	1			T1	11		T4	7		T10	6
ClkMuxSt	35872	1			T1	11		T4	7		T10	6
IdleSt	20879958	1			T1	1796		T2	3711		T3	28297
ResetSt	7186226	1			T1	1598		T2	12189		T3	118
arcs[ResetSt=>IdleSt]	55919	1			T1	15		T2	121		T3	1
arcs[IdleSt=>ScrapSt]	305	1			T2	3		T5	1		T8	1
arcs[IdleSt=>ClkMuxSt]	35550	1			T1	11		T4	7		T10	6
arcs[ClkMuxSt=>CntIncrSt]	35478	1			T1	11		T4	7		T10	6
arcs[CntIncrSt=>PostTransSt]	1883	1			T5	16		T8	10		T15	5
arcs[CntIncrSt=>CntProgSt]	33530	1			T1	11		T4	7		T10	6
arcs[CntProgSt=>PostTransSt]	4898	1			T5	16		T8	8		T15	85
arcs[CntProgSt=>TransCheckSt]	27440	1			T1	11		T4	7		T10	6
arcs[TransCheckSt=>PostTransSt]	3677	1			T5	19		T8	7		T15	7
arcs[TransCheckSt=>TokenHashSt]	23669	1			T1	11		T4	7		T10	6
arcs[TokenHashSt=>PostTransSt]	10198	1			T5	52		T8	17		T15	39
arcs[TokenHashSt=>FlashRmaSt]	12885	1			T1	11		T4	7		T10	6
arcs[FlashRmaSt=>TokenCheck0St]	12796	1			T1	11		T4	7		T10	6
arcs[TokenCheck0St=>PostTransSt]	3053	1			T5	21		T8	2		T15	6
arcs[TokenCheck0St=>TokenCheck1St]	9720	1			T1	11		T4	7		T10	6
arcs[TokenCheck1St=>PostTransSt]	634	1			T5	1		T33	9		T30	2
arcs[TransProgSt=>PostTransSt]	8192	1			T1	11		T4	7		T10	6
arcs[IdleSt=>EscalateSt]	225	1			T47	7		T50	4		T51	9
arcs[ClkMuxSt=>EscalateSt]	72	1			T34	1		T46	4		T47	2
arcs[CntIncrSt=>EscalateSt]	65	1			T47	3		T48	1		T49	1
arcs[CntProgSt=>EscalateSt]	1192	1			T34	21		T46	9		T47	13
arcs[TransCheckSt=>EscalateSt]	94	1			T34	1		T46	8		T47	11
arcs[TokenHashSt=>EscalateSt]	585	1			T34	8		T15	1		T46	15
arcs[FlashRmaSt=>EscalateSt]	89	1			T34	3		T47	2		T48	2
arcs[TokenCheck0St=>EscalateSt]	23	1			T49	2		T55	1		T51	2
arcs[TokenCheck1St=>EscalateSt]	144	1			T34	3		T46	6		T47	4
arcs[TransProgSt=>EscalateSt]	750	1			T34	16		T46	8		T47	12
arcs[PostTransSt=>EscalateSt]	5110	1			T5	16		T8	8		T15	85
arcs[InvalidSt=>EscalateSt]	15282	1			T1	3		T10	7		T5	5

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7186071	1			T1	1598		T2	12189		T3	118
auto[0]	auto[IdleSt]	20879809	1			T1	1796		T2	3711		T3	28297
auto[0]	auto[ClkMuxSt]	35823	1			T1	11		T4	7		T10	6
auto[0]	auto[CntIncrSt]	35433	1			T1	11		T4	7		T10	6
auto[0]	auto[CntProgSt]	1710240	1			T1	500		T4	14		T10	12
auto[0]	auto[TransCheckSt]	27376	1			T1	11		T4	7		T10	6
auto[0]	auto[TokenHashSt]	49404116	1			T1	120		T4	80878		T10	241
auto[0]	auto[FlashRmaSt]	35847	1			T1	46		T4	7		T10	47
auto[0]	auto[TokenCheck0St]	12781	1			T1	11		T4	7		T10	6
auto[0]	auto[TokenCheck1St]	9617	1			T1	11		T4	7		T10	6
auto[0]	auto[TransProgSt]	439740	1			T1	410		T4	14		T10	12
auto[0]	auto[PostTransSt]	12368860	1			T1	2802		T4	1736		T9	970
auto[0]	auto[ScrapSt]	385982	1			T2	317		T5	494		T8	499
auto[0]	auto[EscalateSt]	4912993	1			T1	534		T10	818		T5	4645
auto[0]	auto[InvalidSt]	9536606	1			T1	419		T2	5687		T10	499
auto[1]	auto[ResetSt]	155	1			T34	3		T46	4		T47	2
auto[1]	auto[IdleSt]	149	1			T47	3		T50	3		T51	5
auto[1]	auto[ClkMuxSt]	49	1			T34	1		T46	4		T47	2
auto[1]	auto[CntIncrSt]	45	1			T47	2		T49	1		T55	2
auto[1]	auto[CntProgSt]	756	1			T34	16		T46	6		T47	5
auto[1]	auto[TransCheckSt]	64	1			T34	1		T46	6		T47	9
auto[1]	auto[TokenHashSt]	384	1			T34	6		T15	1		T46	7
auto[1]	auto[FlashRmaSt]	65	1			T34	3		T47	2		T48	2
auto[1]	auto[TokenCheck0St]	15	1			T49	2		T55	1		T51	1
auto[1]	auto[TokenCheck1St]	103	1			T34	2		T46	5		T47	4
auto[1]	auto[TransProgSt]	501	1			T34	15		T46	7		T47	6
auto[1]	auto[PostTransSt]	2594	1			T5	8		T8	4		T15	38
auto[1]	auto[ScrapSt]	52	1			T34	1		T47	2		T190	2
auto[1]	auto[EscalateSt]	1457714	1			T1	98		T10	392		T5	980
auto[1]	auto[InvalidSt]	7693	1			T1	1		T10	4		T5	2

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7186054	1			T1	1598		T2	12189		T3	118
auto[0]	auto[IdleSt]	20879817	1			T1	1796		T2	3711		T3	28297
auto[0]	auto[ClkMuxSt]	35824	1			T1	11		T4	7		T10	6
auto[0]	auto[CntIncrSt]	35438	1			T1	11		T4	7		T10	6
auto[0]	auto[CntProgSt]	1710176	1			T1	500		T4	14		T10	12
auto[0]	auto[TransCheckSt]	27375	1			T1	11		T4	7		T10	6
auto[0]	auto[TokenHashSt]	49404108	1			T1	120		T4	80878		T10	241
auto[0]	auto[FlashRmaSt]	35857	1			T1	46		T4	7		T10	47
auto[0]	auto[TokenCheck0St]	12776	1			T1	11		T4	7		T10	6
auto[0]	auto[TokenCheck1St]	9628	1			T1	11		T4	7		T10	6
auto[0]	auto[TransProgSt]	439722	1			T1	410		T4	14		T10	12
auto[0]	auto[PostTransSt]	12368873	1			T1	2802		T4	1736		T9	970
auto[0]	auto[ScrapSt]	385977	1			T2	317		T5	494		T8	499
auto[0]	auto[EscalateSt]	4906772	1			T1	436		T10	916		T5	4547
auto[0]	auto[InvalidSt]	9536710	1			T1	418		T2	5687		T10	500
auto[1]	auto[ResetSt]	172	1			T34	2		T46	3		T47	4
auto[1]	auto[IdleSt]	141	1			T47	7		T50	3		T51	8
auto[1]	auto[ClkMuxSt]	48	1			T46	2		T47	1		T190	1
auto[1]	auto[CntIncrSt]	40	1			T47	2		T48	1		T55	2
auto[1]	auto[CntProgSt]	820	1			T34	12		T46	5		T47	12
auto[1]	auto[TransCheckSt]	65	1			T46	8		T47	6		T55	2
auto[1]	auto[TokenHashSt]	392	1			T34	5		T46	11		T31	1
auto[1]	auto[FlashRmaSt]	55	1			T34	2		T48	2		T190	1
auto[1]	auto[TokenCheck0St]	20	1			T49	1		T55	1		T51	1
auto[1]	auto[TokenCheck1St]	92	1			T34	3		T46	2		T47	3
auto[1]	auto[TransProgSt]	519	1			T34	10		T46	5		T47	9
auto[1]	auto[PostTransSt]	2581	1			T5	8		T8	4		T15	47
auto[1]	auto[ScrapSt]	57	1			T34	1		T47	2		T48	2
auto[1]	auto[EscalateSt]	1463935	1			T1	196		T10	294		T5	1078
auto[1]	auto[InvalidSt]	7589	1			T1	2		T10	3		T5	3