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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.93 97.99 95.59 93.38 97.67 98.55 99.00 96.29


Total test records in report: 993
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T811 /workspace/coverage/default/23.lc_ctrl_alert_test.2587059471 Jul 09 05:09:07 PM PDT 24 Jul 09 05:09:09 PM PDT 24 68612187 ps
T812 /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.1093139612 Jul 09 05:07:25 PM PDT 24 Jul 09 05:08:08 PM PDT 24 1121923538 ps
T813 /workspace/coverage/default/5.lc_ctrl_alert_test.3969870336 Jul 09 05:07:48 PM PDT 24 Jul 09 05:07:50 PM PDT 24 17541348 ps
T814 /workspace/coverage/default/11.lc_ctrl_jtag_errors.3152271571 Jul 09 05:08:19 PM PDT 24 Jul 09 05:09:29 PM PDT 24 3342479998 ps
T815 /workspace/coverage/default/46.lc_ctrl_prog_failure.1506767926 Jul 09 05:10:15 PM PDT 24 Jul 09 05:10:20 PM PDT 24 401477058 ps
T816 /workspace/coverage/default/41.lc_ctrl_alert_test.1291153273 Jul 09 05:10:01 PM PDT 24 Jul 09 05:10:03 PM PDT 24 63416047 ps
T817 /workspace/coverage/default/22.lc_ctrl_errors.3443359609 Jul 09 05:09:02 PM PDT 24 Jul 09 05:09:12 PM PDT 24 505058568 ps
T818 /workspace/coverage/default/9.lc_ctrl_regwen_during_op.416995856 Jul 09 05:08:09 PM PDT 24 Jul 09 05:08:16 PM PDT 24 1077876617 ps
T819 /workspace/coverage/default/25.lc_ctrl_security_escalation.1347173190 Jul 09 05:09:11 PM PDT 24 Jul 09 05:09:24 PM PDT 24 326852451 ps
T820 /workspace/coverage/default/5.lc_ctrl_sec_token_mux.3217344024 Jul 09 05:07:51 PM PDT 24 Jul 09 05:08:00 PM PDT 24 518136223 ps
T821 /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.2059702422 Jul 09 05:09:08 PM PDT 24 Jul 09 05:09:10 PM PDT 24 25209253 ps
T822 /workspace/coverage/default/3.lc_ctrl_errors.3174336013 Jul 09 05:07:33 PM PDT 24 Jul 09 05:07:45 PM PDT 24 5686005944 ps
T823 /workspace/coverage/default/7.lc_ctrl_sec_token_digest.3203718443 Jul 09 05:08:02 PM PDT 24 Jul 09 05:08:26 PM PDT 24 7277630856 ps
T824 /workspace/coverage/default/10.lc_ctrl_sec_token_mux.2008612707 Jul 09 05:08:19 PM PDT 24 Jul 09 05:08:30 PM PDT 24 2033129801 ps
T825 /workspace/coverage/default/3.lc_ctrl_prog_failure.572295839 Jul 09 05:07:31 PM PDT 24 Jul 09 05:07:35 PM PDT 24 235175736 ps
T826 /workspace/coverage/default/44.lc_ctrl_sec_mubi.1831045866 Jul 09 05:10:06 PM PDT 24 Jul 09 05:10:21 PM PDT 24 430797794 ps
T827 /workspace/coverage/default/31.lc_ctrl_sec_token_mux.1216986707 Jul 09 05:09:27 PM PDT 24 Jul 09 05:09:42 PM PDT 24 1210975692 ps
T828 /workspace/coverage/default/8.lc_ctrl_smoke.2786630189 Jul 09 05:08:04 PM PDT 24 Jul 09 05:08:07 PM PDT 24 67496478 ps
T829 /workspace/coverage/default/13.lc_ctrl_security_escalation.3701767188 Jul 09 05:08:27 PM PDT 24 Jul 09 05:08:41 PM PDT 24 1456991271 ps
T830 /workspace/coverage/default/41.lc_ctrl_state_failure.1609697604 Jul 09 05:09:55 PM PDT 24 Jul 09 05:10:24 PM PDT 24 1209115191 ps
T831 /workspace/coverage/default/40.lc_ctrl_sec_token_digest.3027068068 Jul 09 05:09:56 PM PDT 24 Jul 09 05:10:05 PM PDT 24 1324862518 ps
T832 /workspace/coverage/default/45.lc_ctrl_security_escalation.20697386 Jul 09 05:10:12 PM PDT 24 Jul 09 05:10:28 PM PDT 24 404216989 ps
T833 /workspace/coverage/default/46.lc_ctrl_state_post_trans.1354745209 Jul 09 05:10:14 PM PDT 24 Jul 09 05:10:18 PM PDT 24 79410773 ps
T834 /workspace/coverage/default/12.lc_ctrl_state_post_trans.432276278 Jul 09 05:08:22 PM PDT 24 Jul 09 05:08:26 PM PDT 24 70397976 ps
T835 /workspace/coverage/default/18.lc_ctrl_jtag_errors.768251826 Jul 09 05:08:44 PM PDT 24 Jul 09 05:09:43 PM PDT 24 2081486637 ps
T79 /workspace/coverage/default/34.lc_ctrl_smoke.4247410072 Jul 09 05:09:42 PM PDT 24 Jul 09 05:09:46 PM PDT 24 140091857 ps
T836 /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.2779234076 Jul 09 05:07:42 PM PDT 24 Jul 09 05:08:02 PM PDT 24 1815765464 ps
T837 /workspace/coverage/default/25.lc_ctrl_prog_failure.2408966312 Jul 09 05:09:12 PM PDT 24 Jul 09 05:09:14 PM PDT 24 24274032 ps
T838 /workspace/coverage/default/13.lc_ctrl_sec_token_mux.1762281589 Jul 09 05:08:27 PM PDT 24 Jul 09 05:08:38 PM PDT 24 874177108 ps
T839 /workspace/coverage/default/29.lc_ctrl_security_escalation.625831230 Jul 09 05:09:20 PM PDT 24 Jul 09 05:09:36 PM PDT 24 2922029345 ps
T840 /workspace/coverage/default/16.lc_ctrl_jtag_smoke.1985103606 Jul 09 05:08:40 PM PDT 24 Jul 09 05:08:45 PM PDT 24 457285193 ps
T841 /workspace/coverage/default/5.lc_ctrl_sec_token_digest.1372575155 Jul 09 05:07:52 PM PDT 24 Jul 09 05:08:23 PM PDT 24 1255010229 ps
T842 /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.4228488218 Jul 09 05:08:05 PM PDT 24 Jul 09 05:08:20 PM PDT 24 969826088 ps
T843 /workspace/coverage/default/3.lc_ctrl_jtag_priority.3457829906 Jul 09 05:07:35 PM PDT 24 Jul 09 05:07:42 PM PDT 24 548434719 ps
T844 /workspace/coverage/default/10.lc_ctrl_jtag_smoke.1073191901 Jul 09 05:08:17 PM PDT 24 Jul 09 05:08:27 PM PDT 24 11839626135 ps
T845 /workspace/coverage/default/35.lc_ctrl_security_escalation.3242496841 Jul 09 05:09:42 PM PDT 24 Jul 09 05:09:51 PM PDT 24 693284176 ps
T187 /workspace/coverage/default/6.lc_ctrl_claim_transition_if.3900388690 Jul 09 05:07:52 PM PDT 24 Jul 09 05:07:54 PM PDT 24 37171741 ps
T152 /workspace/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.1489693261 Jul 09 05:10:15 PM PDT 24 Jul 09 05:22:05 PM PDT 24 71332639601 ps
T846 /workspace/coverage/default/44.lc_ctrl_prog_failure.2737066696 Jul 09 05:10:07 PM PDT 24 Jul 09 05:10:09 PM PDT 24 21056520 ps
T847 /workspace/coverage/default/26.lc_ctrl_jtag_access.2185156383 Jul 09 05:09:14 PM PDT 24 Jul 09 05:09:25 PM PDT 24 346704216 ps
T848 /workspace/coverage/default/14.lc_ctrl_security_escalation.1529103128 Jul 09 05:08:33 PM PDT 24 Jul 09 05:08:44 PM PDT 24 903845504 ps
T849 /workspace/coverage/default/38.lc_ctrl_sec_token_mux.3556904035 Jul 09 05:09:46 PM PDT 24 Jul 09 05:09:57 PM PDT 24 301622910 ps
T850 /workspace/coverage/default/5.lc_ctrl_claim_transition_if.1655111768 Jul 09 05:07:48 PM PDT 24 Jul 09 05:07:49 PM PDT 24 69918937 ps
T851 /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3104526663 Jul 09 05:09:02 PM PDT 24 Jul 09 05:09:05 PM PDT 24 13833164 ps
T852 /workspace/coverage/default/25.lc_ctrl_sec_mubi.4143460225 Jul 09 05:09:10 PM PDT 24 Jul 09 05:09:22 PM PDT 24 204406821 ps
T853 /workspace/coverage/default/33.lc_ctrl_security_escalation.1617131486 Jul 09 05:09:34 PM PDT 24 Jul 09 05:09:43 PM PDT 24 581615624 ps
T854 /workspace/coverage/default/15.lc_ctrl_jtag_errors.819192670 Jul 09 05:08:35 PM PDT 24 Jul 09 05:09:18 PM PDT 24 1294473107 ps
T153 /workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.2034182463 Jul 09 05:09:40 PM PDT 24 Jul 09 05:21:54 PM PDT 24 26229693131 ps
T855 /workspace/coverage/default/32.lc_ctrl_state_post_trans.285857800 Jul 09 05:09:38 PM PDT 24 Jul 09 05:09:45 PM PDT 24 41691093 ps
T856 /workspace/coverage/default/9.lc_ctrl_jtag_access.106320020 Jul 09 05:08:10 PM PDT 24 Jul 09 05:08:18 PM PDT 24 1950916367 ps
T857 /workspace/coverage/default/2.lc_ctrl_sec_token_mux.2919982494 Jul 09 05:07:23 PM PDT 24 Jul 09 05:07:30 PM PDT 24 195355715 ps
T858 /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.3142546295 Jul 09 05:08:33 PM PDT 24 Jul 09 05:08:34 PM PDT 24 11914933 ps
T859 /workspace/coverage/default/26.lc_ctrl_errors.2648476002 Jul 09 05:09:16 PM PDT 24 Jul 09 05:09:28 PM PDT 24 838984555 ps
T860 /workspace/coverage/default/43.lc_ctrl_jtag_access.592478705 Jul 09 05:10:05 PM PDT 24 Jul 09 05:10:11 PM PDT 24 412489468 ps
T861 /workspace/coverage/default/21.lc_ctrl_alert_test.252402051 Jul 09 05:08:58 PM PDT 24 Jul 09 05:09:00 PM PDT 24 14864114 ps
T862 /workspace/coverage/default/14.lc_ctrl_sec_token_mux.1078896630 Jul 09 05:08:36 PM PDT 24 Jul 09 05:08:55 PM PDT 24 2311435968 ps
T863 /workspace/coverage/default/13.lc_ctrl_sec_token_digest.330981555 Jul 09 05:08:26 PM PDT 24 Jul 09 05:08:37 PM PDT 24 3639666722 ps
T864 /workspace/coverage/default/37.lc_ctrl_prog_failure.3691085410 Jul 09 05:09:44 PM PDT 24 Jul 09 05:09:47 PM PDT 24 44404113 ps
T131 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.281928936 Jul 09 05:05:00 PM PDT 24 Jul 09 05:05:06 PM PDT 24 127316797 ps
T111 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.249483563 Jul 09 05:05:00 PM PDT 24 Jul 09 05:05:07 PM PDT 24 21740887 ps
T99 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3556610856 Jul 09 05:05:14 PM PDT 24 Jul 09 05:05:21 PM PDT 24 163434570 ps
T112 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1692406627 Jul 09 05:04:59 PM PDT 24 Jul 09 05:05:10 PM PDT 24 1009555083 ps
T100 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.223610580 Jul 09 05:04:52 PM PDT 24 Jul 09 05:04:59 PM PDT 24 338318455 ps
T101 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2077329934 Jul 09 05:05:03 PM PDT 24 Jul 09 05:05:10 PM PDT 24 87483383 ps
T178 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.1792352574 Jul 09 05:05:07 PM PDT 24 Jul 09 05:05:12 PM PDT 24 19683291 ps
T132 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.4218342597 Jul 09 05:04:49 PM PDT 24 Jul 09 05:04:57 PM PDT 24 3461122951 ps
T106 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3979675059 Jul 09 05:05:08 PM PDT 24 Jul 09 05:05:13 PM PDT 24 12609317 ps
T103 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.645203127 Jul 09 05:05:01 PM PDT 24 Jul 09 05:05:10 PM PDT 24 51136089 ps
T107 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2884342376 Jul 09 05:05:11 PM PDT 24 Jul 09 05:05:16 PM PDT 24 27862009 ps
T139 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1420793273 Jul 09 05:04:51 PM PDT 24 Jul 09 05:04:56 PM PDT 24 42963952 ps
T140 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.2745191271 Jul 09 05:05:17 PM PDT 24 Jul 09 05:05:20 PM PDT 24 19414881 ps
T128 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.635248368 Jul 09 05:05:06 PM PDT 24 Jul 09 05:05:19 PM PDT 24 16225753004 ps
T164 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3039441691 Jul 09 05:05:14 PM PDT 24 Jul 09 05:05:18 PM PDT 24 21169209 ps
T108 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.1770376211 Jul 09 05:05:13 PM PDT 24 Jul 09 05:05:19 PM PDT 24 72131654 ps
T109 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.33507286 Jul 09 05:04:53 PM PDT 24 Jul 09 05:05:00 PM PDT 24 44182103 ps
T179 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3103937163 Jul 09 05:05:05 PM PDT 24 Jul 09 05:05:11 PM PDT 24 25759285 ps
T118 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1265566920 Jul 09 05:05:04 PM PDT 24 Jul 09 05:05:13 PM PDT 24 92915673 ps
T165 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3273773185 Jul 09 05:04:46 PM PDT 24 Jul 09 05:04:52 PM PDT 24 43711563 ps
T166 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3953645742 Jul 09 05:05:11 PM PDT 24 Jul 09 05:05:16 PM PDT 24 15445292 ps
T129 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1290351209 Jul 09 05:04:46 PM PDT 24 Jul 09 05:04:55 PM PDT 24 372248666 ps
T865 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.757690798 Jul 09 05:05:09 PM PDT 24 Jul 09 05:05:15 PM PDT 24 64960797 ps
T866 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1658554117 Jul 09 05:05:03 PM PDT 24 Jul 09 05:05:13 PM PDT 24 1338079187 ps
T867 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.508500052 Jul 09 05:04:52 PM PDT 24 Jul 09 05:04:59 PM PDT 24 322435091 ps
T167 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3329029324 Jul 09 05:04:59 PM PDT 24 Jul 09 05:05:05 PM PDT 24 49610059 ps
T141 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3140730354 Jul 09 05:04:53 PM PDT 24 Jul 09 05:04:59 PM PDT 24 25398036 ps
T868 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3795440899 Jul 09 05:05:04 PM PDT 24 Jul 09 05:05:10 PM PDT 24 31045623 ps
T869 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2571203964 Jul 09 05:04:57 PM PDT 24 Jul 09 05:05:05 PM PDT 24 921135027 ps
T870 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2444228550 Jul 09 05:04:51 PM PDT 24 Jul 09 05:04:55 PM PDT 24 29777497 ps
T180 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1009523382 Jul 09 05:05:12 PM PDT 24 Jul 09 05:05:18 PM PDT 24 212785472 ps
T871 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3499516604 Jul 09 05:04:58 PM PDT 24 Jul 09 05:05:21 PM PDT 24 698976963 ps
T181 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.4171845763 Jul 09 05:05:10 PM PDT 24 Jul 09 05:05:15 PM PDT 24 241896968 ps
T872 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3693432514 Jul 09 05:04:57 PM PDT 24 Jul 09 05:05:05 PM PDT 24 31868927 ps
T873 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.4148613263 Jul 09 05:05:03 PM PDT 24 Jul 09 05:05:10 PM PDT 24 45536358 ps
T182 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2935514460 Jul 09 05:04:51 PM PDT 24 Jul 09 05:04:56 PM PDT 24 95553855 ps
T183 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.615678602 Jul 09 05:05:16 PM PDT 24 Jul 09 05:05:20 PM PDT 24 180674037 ps
T874 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3595855224 Jul 09 05:05:08 PM PDT 24 Jul 09 05:05:13 PM PDT 24 56155251 ps
T104 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3824014741 Jul 09 05:05:16 PM PDT 24 Jul 09 05:05:20 PM PDT 24 180703145 ps
T875 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2027891793 Jul 09 05:05:09 PM PDT 24 Jul 09 05:05:13 PM PDT 24 35274060 ps
T876 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.4279032938 Jul 09 05:04:49 PM PDT 24 Jul 09 05:04:55 PM PDT 24 124165042 ps
T877 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2742507073 Jul 09 05:05:17 PM PDT 24 Jul 09 05:05:20 PM PDT 24 108355742 ps
T878 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3143399981 Jul 09 05:05:08 PM PDT 24 Jul 09 05:05:14 PM PDT 24 304324741 ps
T105 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1150483610 Jul 09 05:04:57 PM PDT 24 Jul 09 05:05:04 PM PDT 24 44887905 ps
T879 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3586709439 Jul 09 05:04:42 PM PDT 24 Jul 09 05:04:46 PM PDT 24 423354720 ps
T880 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.166545245 Jul 09 05:05:06 PM PDT 24 Jul 09 05:05:20 PM PDT 24 2657560351 ps
T881 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.137483876 Jul 09 05:04:53 PM PDT 24 Jul 09 05:05:16 PM PDT 24 694931385 ps
T882 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.355397490 Jul 09 05:04:52 PM PDT 24 Jul 09 05:04:57 PM PDT 24 18596450 ps
T883 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.28305961 Jul 09 05:04:51 PM PDT 24 Jul 09 05:04:57 PM PDT 24 26272461 ps
T884 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.4263496343 Jul 09 05:05:14 PM PDT 24 Jul 09 05:05:21 PM PDT 24 117958822 ps
T130 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3243369701 Jul 09 05:05:06 PM PDT 24 Jul 09 05:05:14 PM PDT 24 468193568 ps
T885 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.415886097 Jul 09 05:05:10 PM PDT 24 Jul 09 05:05:34 PM PDT 24 3457340724 ps
T886 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3612216555 Jul 09 05:05:03 PM PDT 24 Jul 09 05:05:09 PM PDT 24 88621882 ps
T887 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.48764233 Jul 09 05:05:08 PM PDT 24 Jul 09 05:05:14 PM PDT 24 105793158 ps
T888 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2748996381 Jul 09 05:05:18 PM PDT 24 Jul 09 05:05:22 PM PDT 24 138322718 ps
T125 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3324847951 Jul 09 05:05:13 PM PDT 24 Jul 09 05:05:21 PM PDT 24 108323092 ps
T889 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.4030836844 Jul 09 05:05:12 PM PDT 24 Jul 09 05:05:17 PM PDT 24 21088714 ps
T890 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1377435732 Jul 09 05:05:00 PM PDT 24 Jul 09 05:05:06 PM PDT 24 13835364 ps
T127 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2507425385 Jul 09 05:04:48 PM PDT 24 Jul 09 05:04:54 PM PDT 24 40671782 ps
T121 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.4243949318 Jul 09 05:05:02 PM PDT 24 Jul 09 05:05:11 PM PDT 24 450642132 ps
T891 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1490570653 Jul 09 05:05:00 PM PDT 24 Jul 09 05:05:07 PM PDT 24 61216527 ps
T892 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1457710268 Jul 09 05:05:10 PM PDT 24 Jul 09 05:05:14 PM PDT 24 73227761 ps
T893 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3862929683 Jul 09 05:05:07 PM PDT 24 Jul 09 05:05:12 PM PDT 24 680363773 ps
T894 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2611144990 Jul 09 05:04:51 PM PDT 24 Jul 09 05:04:57 PM PDT 24 186088691 ps
T895 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3355197924 Jul 09 05:05:16 PM PDT 24 Jul 09 05:05:22 PM PDT 24 1173726579 ps
T896 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3943925563 Jul 09 05:05:12 PM PDT 24 Jul 09 05:05:18 PM PDT 24 88141361 ps
T897 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1810940052 Jul 09 05:05:04 PM PDT 24 Jul 09 05:05:11 PM PDT 24 82361535 ps
T898 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3922932086 Jul 09 05:05:09 PM PDT 24 Jul 09 05:05:14 PM PDT 24 97471514 ps
T899 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2916323378 Jul 09 05:05:03 PM PDT 24 Jul 09 05:05:09 PM PDT 24 307780336 ps
T900 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2306285034 Jul 09 05:04:52 PM PDT 24 Jul 09 05:04:59 PM PDT 24 300481257 ps
T901 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.2296790380 Jul 09 05:05:07 PM PDT 24 Jul 09 05:05:13 PM PDT 24 35129911 ps
T902 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.3817187254 Jul 09 05:04:50 PM PDT 24 Jul 09 05:04:55 PM PDT 24 13906828 ps
T903 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.580736677 Jul 09 05:05:08 PM PDT 24 Jul 09 05:05:13 PM PDT 24 26388649 ps
T904 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2667990341 Jul 09 05:04:50 PM PDT 24 Jul 09 05:04:55 PM PDT 24 26651363 ps
T114 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.381371920 Jul 09 05:05:12 PM PDT 24 Jul 09 05:05:20 PM PDT 24 121810246 ps
T905 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1556809833 Jul 09 05:05:01 PM PDT 24 Jul 09 05:05:07 PM PDT 24 23852010 ps
T171 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1263285192 Jul 09 05:04:52 PM PDT 24 Jul 09 05:04:58 PM PDT 24 53797606 ps
T119 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.977408361 Jul 09 05:05:10 PM PDT 24 Jul 09 05:05:16 PM PDT 24 702120529 ps
T906 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2121747844 Jul 09 05:04:58 PM PDT 24 Jul 09 05:05:06 PM PDT 24 300247318 ps
T168 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.4234949882 Jul 09 05:05:09 PM PDT 24 Jul 09 05:05:13 PM PDT 24 19684943 ps
T907 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2890596871 Jul 09 05:05:10 PM PDT 24 Jul 09 05:05:15 PM PDT 24 121240784 ps
T908 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2030197737 Jul 09 05:05:12 PM PDT 24 Jul 09 05:05:18 PM PDT 24 57063233 ps
T909 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2128885463 Jul 09 05:05:13 PM PDT 24 Jul 09 05:05:18 PM PDT 24 15927021 ps
T117 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.746678754 Jul 09 05:05:08 PM PDT 24 Jul 09 05:05:16 PM PDT 24 115988632 ps
T910 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2856998458 Jul 09 05:04:52 PM PDT 24 Jul 09 05:04:57 PM PDT 24 59270846 ps
T911 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1778891597 Jul 09 05:04:52 PM PDT 24 Jul 09 05:04:58 PM PDT 24 39431397 ps
T169 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3470525340 Jul 09 05:05:08 PM PDT 24 Jul 09 05:05:12 PM PDT 24 44920470 ps
T912 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1290061441 Jul 09 05:05:17 PM PDT 24 Jul 09 05:05:20 PM PDT 24 21008134 ps
T913 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.527366745 Jul 09 05:04:52 PM PDT 24 Jul 09 05:05:00 PM PDT 24 199516751 ps
T170 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.397169192 Jul 09 05:05:06 PM PDT 24 Jul 09 05:05:11 PM PDT 24 20252056 ps
T914 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1865811471 Jul 09 05:05:01 PM PDT 24 Jul 09 05:05:08 PM PDT 24 83948828 ps
T915 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3434152873 Jul 09 05:04:53 PM PDT 24 Jul 09 05:05:00 PM PDT 24 310069688 ps
T916 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.4259181162 Jul 09 05:05:03 PM PDT 24 Jul 09 05:05:09 PM PDT 24 181226770 ps
T917 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1153839284 Jul 09 05:05:15 PM PDT 24 Jul 09 05:05:21 PM PDT 24 225287622 ps
T918 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1738642591 Jul 09 05:04:53 PM PDT 24 Jul 09 05:04:59 PM PDT 24 57808269 ps
T919 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3381831832 Jul 09 05:05:14 PM PDT 24 Jul 09 05:05:19 PM PDT 24 53724533 ps
T920 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1539229296 Jul 09 05:04:51 PM PDT 24 Jul 09 05:04:56 PM PDT 24 51342808 ps
T120 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.3866032044 Jul 09 05:05:15 PM PDT 24 Jul 09 05:05:21 PM PDT 24 144779395 ps
T921 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2443964728 Jul 09 05:04:56 PM PDT 24 Jul 09 05:05:07 PM PDT 24 1099129006 ps
T922 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2777470268 Jul 09 05:04:56 PM PDT 24 Jul 09 05:05:03 PM PDT 24 27018755 ps
T923 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3768140690 Jul 09 05:04:56 PM PDT 24 Jul 09 05:05:09 PM PDT 24 444424073 ps
T924 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2384366115 Jul 09 05:04:58 PM PDT 24 Jul 09 05:05:05 PM PDT 24 19368671 ps
T925 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.908045418 Jul 09 05:05:00 PM PDT 24 Jul 09 05:05:06 PM PDT 24 665703385 ps
T926 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.4034078978 Jul 09 05:05:00 PM PDT 24 Jul 09 05:05:15 PM PDT 24 698795831 ps
T927 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1697791488 Jul 09 05:04:56 PM PDT 24 Jul 09 05:05:13 PM PDT 24 1242670299 ps
T174 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.524621931 Jul 09 05:04:53 PM PDT 24 Jul 09 05:04:59 PM PDT 24 49152335 ps
T928 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1972899723 Jul 09 05:04:57 PM PDT 24 Jul 09 05:05:03 PM PDT 24 22927746 ps
T929 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3930573537 Jul 09 05:04:57 PM PDT 24 Jul 09 05:05:04 PM PDT 24 36380269 ps
T930 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.472096931 Jul 09 05:05:06 PM PDT 24 Jul 09 05:05:11 PM PDT 24 100098679 ps
T931 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.820055744 Jul 09 05:05:01 PM PDT 24 Jul 09 05:05:22 PM PDT 24 1095415783 ps
T932 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3236927415 Jul 09 05:04:48 PM PDT 24 Jul 09 05:04:54 PM PDT 24 347860163 ps
T933 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2418502109 Jul 09 05:05:04 PM PDT 24 Jul 09 05:05:13 PM PDT 24 4651315808 ps
T934 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1949036153 Jul 09 05:05:03 PM PDT 24 Jul 09 05:05:09 PM PDT 24 20032919 ps
T935 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.985486372 Jul 09 05:05:10 PM PDT 24 Jul 09 05:05:16 PM PDT 24 64957758 ps
T936 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2799490175 Jul 09 05:05:05 PM PDT 24 Jul 09 05:05:10 PM PDT 24 28077377 ps
T937 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1528757294 Jul 09 05:05:02 PM PDT 24 Jul 09 05:05:08 PM PDT 24 165945647 ps
T938 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.537048505 Jul 09 05:05:09 PM PDT 24 Jul 09 05:05:17 PM PDT 24 99771495 ps
T172 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3879298837 Jul 09 05:04:57 PM PDT 24 Jul 09 05:05:03 PM PDT 24 12618893 ps
T939 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1932933564 Jul 09 05:05:02 PM PDT 24 Jul 09 05:05:09 PM PDT 24 391433538 ps
T940 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2727779367 Jul 09 05:04:59 PM PDT 24 Jul 09 05:05:06 PM PDT 24 48596676 ps
T941 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1333299799 Jul 09 05:05:11 PM PDT 24 Jul 09 05:05:19 PM PDT 24 154491264 ps
T942 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1294405965 Jul 09 05:04:56 PM PDT 24 Jul 09 05:05:02 PM PDT 24 148916359 ps
T175 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3371882998 Jul 09 05:05:00 PM PDT 24 Jul 09 05:05:06 PM PDT 24 26762448 ps
T943 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1357264535 Jul 09 05:04:47 PM PDT 24 Jul 09 05:04:53 PM PDT 24 333975390 ps
T944 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3782516729 Jul 09 05:05:11 PM PDT 24 Jul 09 05:05:16 PM PDT 24 63000049 ps
T945 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1558122873 Jul 09 05:04:52 PM PDT 24 Jul 09 05:05:12 PM PDT 24 1241036369 ps
T946 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3102418814 Jul 09 05:04:45 PM PDT 24 Jul 09 05:04:50 PM PDT 24 69118261 ps
T947 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.842615725 Jul 09 05:04:56 PM PDT 24 Jul 09 05:05:03 PM PDT 24 15177339 ps
T948 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2340726465 Jul 09 05:05:10 PM PDT 24 Jul 09 05:05:15 PM PDT 24 70034774 ps
T173 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2879260172 Jul 09 05:04:52 PM PDT 24 Jul 09 05:04:57 PM PDT 24 23794002 ps
T949 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.4059253432 Jul 09 05:04:51 PM PDT 24 Jul 09 05:04:58 PM PDT 24 368510772 ps
T950 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.72531869 Jul 09 05:05:09 PM PDT 24 Jul 09 05:05:14 PM PDT 24 19297218 ps
T951 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.941253841 Jul 09 05:04:49 PM PDT 24 Jul 09 05:04:55 PM PDT 24 110169425 ps
T177 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.297095754 Jul 09 05:04:51 PM PDT 24 Jul 09 05:04:56 PM PDT 24 32488211 ps
T113 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3856895908 Jul 09 05:05:14 PM PDT 24 Jul 09 05:05:21 PM PDT 24 317203101 ps
T952 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3445800466 Jul 09 05:05:09 PM PDT 24 Jul 09 05:05:13 PM PDT 24 56830258 ps
T953 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.4182522482 Jul 09 05:05:02 PM PDT 24 Jul 09 05:05:11 PM PDT 24 148469832 ps
T954 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.767146437 Jul 09 05:04:55 PM PDT 24 Jul 09 05:05:03 PM PDT 24 96306719 ps
T955 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2041027895 Jul 09 05:05:03 PM PDT 24 Jul 09 05:05:10 PM PDT 24 192969539 ps
T956 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1256287436 Jul 09 05:04:51 PM PDT 24 Jul 09 05:04:56 PM PDT 24 43755071 ps
T957 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1198736702 Jul 09 05:05:08 PM PDT 24 Jul 09 05:05:12 PM PDT 24 18919165 ps
T958 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1674629426 Jul 09 05:04:53 PM PDT 24 Jul 09 05:05:00 PM PDT 24 105542521 ps
T959 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.553317872 Jul 09 05:05:15 PM PDT 24 Jul 09 05:05:19 PM PDT 24 22408131 ps
T110 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2847950265 Jul 09 05:05:10 PM PDT 24 Jul 09 05:05:17 PM PDT 24 100963396 ps
T960 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2156854922 Jul 09 05:05:11 PM PDT 24 Jul 09 05:05:16 PM PDT 24 41093897 ps
T176 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1435289450 Jul 09 05:04:58 PM PDT 24 Jul 09 05:05:04 PM PDT 24 52418013 ps
T961 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.938134184 Jul 09 05:04:57 PM PDT 24 Jul 09 05:05:03 PM PDT 24 55311981 ps
T962 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.681059128 Jul 09 05:04:57 PM PDT 24 Jul 09 05:05:04 PM PDT 24 100626477 ps
T963 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2024218272 Jul 09 05:04:46 PM PDT 24 Jul 09 05:05:12 PM PDT 24 3567793734 ps
T964 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3024207457 Jul 09 05:05:09 PM PDT 24 Jul 09 05:05:15 PM PDT 24 31775291 ps
T965 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1902424551 Jul 09 05:04:53 PM PDT 24 Jul 09 05:05:00 PM PDT 24 100313330 ps
T966 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.437637862 Jul 09 05:05:07 PM PDT 24 Jul 09 05:05:18 PM PDT 24 286140754 ps
T967 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1981448650 Jul 09 05:05:07 PM PDT 24 Jul 09 05:05:13 PM PDT 24 541266725 ps
T968 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1530979626 Jul 09 05:05:00 PM PDT 24 Jul 09 05:05:07 PM PDT 24 53467456 ps
T969 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2169580930 Jul 09 05:04:53 PM PDT 24 Jul 09 05:04:59 PM PDT 24 75503268 ps
T970 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3976280945 Jul 09 05:05:10 PM PDT 24 Jul 09 05:05:22 PM PDT 24 3811212659 ps
T971 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1152967982 Jul 09 05:04:53 PM PDT 24 Jul 09 05:04:59 PM PDT 24 299138831 ps
T972 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1526708048 Jul 09 05:05:06 PM PDT 24 Jul 09 05:05:12 PM PDT 24 30780580 ps
T124 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1272915489 Jul 09 05:05:14 PM PDT 24 Jul 09 05:05:20 PM PDT 24 239866540 ps
T973 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.3393539782 Jul 09 05:05:02 PM PDT 24 Jul 09 05:05:09 PM PDT 24 105687212 ps
T974 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1537287336 Jul 09 05:05:13 PM PDT 24 Jul 09 05:05:18 PM PDT 24 62228818 ps
T975 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.4138724116 Jul 09 05:04:58 PM PDT 24 Jul 09 05:05:05 PM PDT 24 121538246 ps
T976 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2928916979 Jul 09 05:04:49 PM PDT 24 Jul 09 05:04:55 PM PDT 24 604780701 ps
T977 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.4219268699 Jul 09 05:05:14 PM PDT 24 Jul 09 05:05:20 PM PDT 24 127137187 ps
T126 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2277759433 Jul 09 05:04:52 PM PDT 24 Jul 09 05:04:58 PM PDT 24 208110824 ps
T978 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3293825067 Jul 09 05:04:49 PM PDT 24 Jul 09 05:04:57 PM PDT 24 881641279 ps
T979 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.17732509 Jul 09 05:05:08 PM PDT 24 Jul 09 05:05:13 PM PDT 24 39826760 ps
T980 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2115542796 Jul 09 05:05:09 PM PDT 24 Jul 09 05:05:15 PM PDT 24 24271301 ps
T122 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.97841318 Jul 09 05:04:54 PM PDT 24 Jul 09 05:05:02 PM PDT 24 1280982647 ps
T981 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.4037528945 Jul 09 05:05:03 PM PDT 24 Jul 09 05:05:09 PM PDT 24 59757185 ps
T982 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3156064295 Jul 09 05:04:54 PM PDT 24 Jul 09 05:05:03 PM PDT 24 122122206 ps
T983 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.646862912 Jul 09 05:04:50 PM PDT 24 Jul 09 05:04:55 PM PDT 24 95492530 ps
T115 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1659912026 Jul 09 05:05:08 PM PDT 24 Jul 09 05:05:15 PM PDT 24 285041586 ps
T984 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1100616559 Jul 09 05:05:08 PM PDT 24 Jul 09 05:05:34 PM PDT 24 3714697971 ps
T985 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1945203334 Jul 09 05:05:01 PM PDT 24 Jul 09 05:05:08 PM PDT 24 166511476 ps
T116 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3876548243 Jul 09 05:05:05 PM PDT 24 Jul 09 05:05:13 PM PDT 24 869864192 ps
T986 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1867957285 Jul 09 05:04:55 PM PDT 24 Jul 09 05:05:04 PM PDT 24 1081036313 ps
T987 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2788844517 Jul 09 05:05:12 PM PDT 24 Jul 09 05:05:17 PM PDT 24 27126844 ps
T123 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.459595711 Jul 09 05:05:12 PM PDT 24 Jul 09 05:05:18 PM PDT 24 408722133 ps
T988 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3208132205 Jul 09 05:04:59 PM PDT 24 Jul 09 05:05:06 PM PDT 24 402147024 ps
T989 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.4163613069 Jul 09 05:05:04 PM PDT 24 Jul 09 05:05:10 PM PDT 24 190999309 ps
T990 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.297654510 Jul 09 05:04:48 PM PDT 24 Jul 09 05:04:56 PM PDT 24 329576730 ps
T991 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.475829847 Jul 09 05:05:01 PM PDT 24 Jul 09 05:05:08 PM PDT 24 64903703 ps
T992 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.494445985 Jul 09 05:05:17 PM PDT 24 Jul 09 05:05:19 PM PDT 24 12977422 ps
T993 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.328276735 Jul 09 05:05:09 PM PDT 24 Jul 09 05:05:13 PM PDT 24 81144043 ps

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.3744347004
Short name T5
Test name
Test status
Simulation time 16520553143 ps
CPU time 269.17 seconds
Started Jul 09 05:09:59 PM PDT 24
Finished Jul 09 05:14:29 PM PDT 24
Peak memory 229024 kb
Host smart-68fb1f26-c641-4116-aa33-5ea018b96dd8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744347004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.3744347004
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.3088213096
Short name T31
Test name
Test status
Simulation time 19939519171 ps
CPU time 592.46 seconds
Started Jul 09 05:08:46 PM PDT 24
Finished Jul 09 05:18:39 PM PDT 24
Peak memory 283384 kb
Host smart-7c055e65-bc4f-4e5e-990c-961c02fa4b82
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3088213096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.3088213096
Directory /workspace/17.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.1714631485
Short name T47
Test name
Test status
Simulation time 768180483 ps
CPU time 10.04 seconds
Started Jul 09 05:10:01 PM PDT 24
Finished Jul 09 05:10:12 PM PDT 24
Peak memory 217844 kb
Host smart-1cd6c127-3ecd-4bfd-9772-6cfbe709f7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714631485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.1714631485
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.3181771894
Short name T41
Test name
Test status
Simulation time 383875879 ps
CPU time 12.66 seconds
Started Jul 09 05:08:46 PM PDT 24
Finished Jul 09 05:08:59 PM PDT 24
Peak memory 217896 kb
Host smart-8a00fc31-e57c-4620-a17a-449667ec6bcf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181771894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.3181771894
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.909799539
Short name T9
Test name
Test status
Simulation time 19410407 ps
CPU time 0.79 seconds
Started Jul 09 05:08:52 PM PDT 24
Finished Jul 09 05:08:54 PM PDT 24
Peak memory 208416 kb
Host smart-87a3e685-8870-46cf-9455-8166248ce985
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909799539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ct
rl_volatile_unlock_smoke.909799539
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.1374975348
Short name T2
Test name
Test status
Simulation time 609041203 ps
CPU time 37.71 seconds
Started Jul 09 05:07:20 PM PDT 24
Finished Jul 09 05:07:58 PM PDT 24
Peak memory 283996 kb
Host smart-185cf39c-02f9-451b-9fa1-0b621a560506
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374975348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.1374975348
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.3549772789
Short name T33
Test name
Test status
Simulation time 176784614 ps
CPU time 6.93 seconds
Started Jul 09 05:08:54 PM PDT 24
Finished Jul 09 05:09:02 PM PDT 24
Peak memory 217588 kb
Host smart-6837b2dc-26e0-40f8-9cce-0adafbbd867e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549772789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
3549772789
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2077329934
Short name T101
Test name
Test status
Simulation time 87483383 ps
CPU time 1.82 seconds
Started Jul 09 05:05:03 PM PDT 24
Finished Jul 09 05:05:10 PM PDT 24
Peak memory 221436 kb
Host smart-b6f988b9-3663-45cc-82ad-a24c0949048b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077329934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.2077329934
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.4231278833
Short name T55
Test name
Test status
Simulation time 1032243036 ps
CPU time 7.63 seconds
Started Jul 09 05:09:52 PM PDT 24
Finished Jul 09 05:10:00 PM PDT 24
Peak memory 217660 kb
Host smart-5b302d6d-7333-46c2-90fa-7efd50db5212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231278833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.4231278833
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.645203127
Short name T103
Test name
Test status
Simulation time 51136089 ps
CPU time 3.24 seconds
Started Jul 09 05:05:01 PM PDT 24
Finished Jul 09 05:05:10 PM PDT 24
Peak memory 217400 kb
Host smart-c1c482e9-0a2a-4495-acd0-f1f97f46b51f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645203127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.645203127
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.281954460
Short name T52
Test name
Test status
Simulation time 363974489 ps
CPU time 41.17 seconds
Started Jul 09 05:07:27 PM PDT 24
Finished Jul 09 05:08:09 PM PDT 24
Peak memory 269464 kb
Host smart-39bbc99e-0fc3-4e2f-afe6-f92954846404
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281954460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.281954460
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.2467059138
Short name T6
Test name
Test status
Simulation time 3265664681 ps
CPU time 6.49 seconds
Started Jul 09 05:09:22 PM PDT 24
Finished Jul 09 05:09:29 PM PDT 24
Peak memory 217156 kb
Host smart-d89e8c7e-8919-4797-8397-93137f980006
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467059138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.2467059138
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3273773185
Short name T165
Test name
Test status
Simulation time 43711563 ps
CPU time 1.29 seconds
Started Jul 09 05:04:46 PM PDT 24
Finished Jul 09 05:04:52 PM PDT 24
Peak memory 209140 kb
Host smart-345b7d89-7eda-4f40-ab76-bd8f652a42be
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273773185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.3273773185
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1290351209
Short name T129
Test name
Test status
Simulation time 372248666 ps
CPU time 5.06 seconds
Started Jul 09 05:04:46 PM PDT 24
Finished Jul 09 05:04:55 PM PDT 24
Peak memory 216920 kb
Host smart-3e7eee7a-7a9d-4821-a1f3-d4a51ab50908
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290351209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.1290351209
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.4091136815
Short name T15
Test name
Test status
Simulation time 118248736331 ps
CPU time 8509.47 seconds
Started Jul 09 05:09:05 PM PDT 24
Finished Jul 09 07:30:57 PM PDT 24
Peak memory 676452 kb
Host smart-0a037445-8bb0-468e-8172-00d1fabbe166
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4091136815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.4091136815
Directory /workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.19210450
Short name T80
Test name
Test status
Simulation time 47802568 ps
CPU time 1 seconds
Started Jul 09 05:08:45 PM PDT 24
Finished Jul 09 05:08:46 PM PDT 24
Peak memory 208408 kb
Host smart-91c342b1-a9e3-428a-8c76-5560ead165e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19210450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.19210450
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.977408361
Short name T119
Test name
Test status
Simulation time 702120529 ps
CPU time 2.53 seconds
Started Jul 09 05:05:10 PM PDT 24
Finished Jul 09 05:05:16 PM PDT 24
Peak memory 221740 kb
Host smart-432da322-9aa9-4676-aa0e-b311c41c2d7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977408361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg_
err.977408361
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.761094989
Short name T45
Test name
Test status
Simulation time 41079623901 ps
CPU time 395.7 seconds
Started Jul 09 05:07:25 PM PDT 24
Finished Jul 09 05:14:02 PM PDT 24
Peak memory 356984 kb
Host smart-98af0592-f5b3-4efd-9a62-fdbf2c6e0cdd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=761094989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all_with_rand_reset.761094989
Directory /workspace/1.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.459595711
Short name T123
Test name
Test status
Simulation time 408722133 ps
CPU time 2.66 seconds
Started Jul 09 05:05:12 PM PDT 24
Finished Jul 09 05:05:18 PM PDT 24
Peak memory 221816 kb
Host smart-1b2d0562-866d-479b-82ca-e81e6d90cc98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459595711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_e
rr.459595711
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.381371920
Short name T114
Test name
Test status
Simulation time 121810246 ps
CPU time 4.53 seconds
Started Jul 09 05:05:12 PM PDT 24
Finished Jul 09 05:05:20 PM PDT 24
Peak memory 217356 kb
Host smart-196a531b-899e-4b07-8430-b2aeb84b6dcd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381371920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg_
err.381371920
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.3310943130
Short name T14
Test name
Test status
Simulation time 255761079 ps
CPU time 3.8 seconds
Started Jul 09 05:08:25 PM PDT 24
Finished Jul 09 05:08:29 PM PDT 24
Peak memory 214660 kb
Host smart-b7ac14a8-af14-44b9-82b3-5c10e3f1a6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310943130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.3310943130
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.3962959996
Short name T587
Test name
Test status
Simulation time 1654023434 ps
CPU time 69.73 seconds
Started Jul 09 05:08:15 PM PDT 24
Finished Jul 09 05:09:25 PM PDT 24
Peak memory 275796 kb
Host smart-e3b15de0-3017-4ec5-9476-d7ad02d869d2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962959996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.3962959996
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2847950265
Short name T110
Test name
Test status
Simulation time 100963396 ps
CPU time 4.05 seconds
Started Jul 09 05:05:10 PM PDT 24
Finished Jul 09 05:05:17 PM PDT 24
Peak memory 217344 kb
Host smart-03364498-63a1-4b82-933c-d00d4cc8f9df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847950265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.2847950265
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3856895908
Short name T113
Test name
Test status
Simulation time 317203101 ps
CPU time 3.81 seconds
Started Jul 09 05:05:14 PM PDT 24
Finished Jul 09 05:05:21 PM PDT 24
Peak memory 222012 kb
Host smart-ceab0512-f4b0-46ed-917e-fdab203b5d75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856895908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.3856895908
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1420793273
Short name T139
Test name
Test status
Simulation time 42963952 ps
CPU time 0.92 seconds
Started Jul 09 05:04:51 PM PDT 24
Finished Jul 09 05:04:56 PM PDT 24
Peak memory 209024 kb
Host smart-da81c23c-0b0b-41fd-a374-b8ad9bf018ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420793273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.1420793273
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.4079936184
Short name T85
Test name
Test status
Simulation time 80885125216 ps
CPU time 1179.58 seconds
Started Jul 09 05:07:16 PM PDT 24
Finished Jul 09 05:26:56 PM PDT 24
Peak memory 332440 kb
Host smart-c4f90ce8-e90e-4517-b63a-5a2f17009a5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4079936184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all_with_rand_reset.4079936184
Directory /workspace/0.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.4243949318
Short name T121
Test name
Test status
Simulation time 450642132 ps
CPU time 4.17 seconds
Started Jul 09 05:05:02 PM PDT 24
Finished Jul 09 05:05:11 PM PDT 24
Peak memory 217400 kb
Host smart-f51ccf3c-3c36-420a-81a0-b2289509edb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243949318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.4243949318
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.1101934342
Short name T186
Test name
Test status
Simulation time 36751040 ps
CPU time 0.85 seconds
Started Jul 09 05:07:19 PM PDT 24
Finished Jul 09 05:07:20 PM PDT 24
Peak memory 208412 kb
Host smart-52832dbb-141e-43cd-b200-6258b9844d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101934342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.1101934342
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.1148744848
Short name T189
Test name
Test status
Simulation time 36028624 ps
CPU time 0.82 seconds
Started Jul 09 05:07:25 PM PDT 24
Finished Jul 09 05:07:27 PM PDT 24
Peak memory 208436 kb
Host smart-c43859df-c776-48e9-af59-10794dfa4858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148744848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.1148744848
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.3375313224
Short name T188
Test name
Test status
Simulation time 34571376 ps
CPU time 1.01 seconds
Started Jul 09 05:07:41 PM PDT 24
Finished Jul 09 05:07:43 PM PDT 24
Peak memory 208312 kb
Host smart-e5c156fe-ef23-480f-99e7-b7d1bd968ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375313224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.3375313224
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.2998106272
Short name T144
Test name
Test status
Simulation time 78036232 ps
CPU time 0.79 seconds
Started Jul 09 05:08:09 PM PDT 24
Finished Jul 09 05:08:11 PM PDT 24
Peak memory 208464 kb
Host smart-30ac81b9-2a8e-445e-9e4b-ff4353f9c6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998106272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.2998106272
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.4264417898
Short name T17
Test name
Test status
Simulation time 4770886907 ps
CPU time 83.36 seconds
Started Jul 09 05:07:52 PM PDT 24
Finished Jul 09 05:09:15 PM PDT 24
Peak memory 283112 kb
Host smart-0d3a6bf3-b74e-45cb-9ff7-0d5c2787d4c0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264417898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.4264417898
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.97841318
Short name T122
Test name
Test status
Simulation time 1280982647 ps
CPU time 2.71 seconds
Started Jul 09 05:04:54 PM PDT 24
Finished Jul 09 05:05:02 PM PDT 24
Peak memory 221904 kb
Host smart-a5ea4eee-badb-41f7-876b-04e1f8c9a0dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97841318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_er
r.97841318
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2277759433
Short name T126
Test name
Test status
Simulation time 208110824 ps
CPU time 1.94 seconds
Started Jul 09 05:04:52 PM PDT 24
Finished Jul 09 05:04:58 PM PDT 24
Peak memory 217412 kb
Host smart-afe0f68b-41d0-456c-9133-366c44df78da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277759433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.2277759433
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.746678754
Short name T117
Test name
Test status
Simulation time 115988632 ps
CPU time 4.17 seconds
Started Jul 09 05:05:08 PM PDT 24
Finished Jul 09 05:05:16 PM PDT 24
Peak memory 217452 kb
Host smart-40d396a1-0389-4e9f-8e32-9bd69d636ea5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746678754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_e
rr.746678754
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.2402751317
Short name T191
Test name
Test status
Simulation time 2479945110 ps
CPU time 6.48 seconds
Started Jul 09 05:07:33 PM PDT 24
Finished Jul 09 05:07:40 PM PDT 24
Peak memory 217708 kb
Host smart-258a0694-3982-452c-8bf3-b012007acebc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402751317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.2402751317
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.4059253432
Short name T949
Test name
Test status
Simulation time 368510772 ps
CPU time 3.07 seconds
Started Jul 09 05:04:51 PM PDT 24
Finished Jul 09 05:04:58 PM PDT 24
Peak memory 208804 kb
Host smart-fbb9a501-16a6-4a7e-85b2-c4d45ed6acec
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059253432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.4059253432
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.3817187254
Short name T902
Test name
Test status
Simulation time 13906828 ps
CPU time 1.05 seconds
Started Jul 09 05:04:50 PM PDT 24
Finished Jul 09 05:04:55 PM PDT 24
Peak memory 209632 kb
Host smart-e6408b5d-1aad-4597-ae3b-918d5c3d230f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817187254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.3817187254
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3102418814
Short name T946
Test name
Test status
Simulation time 69118261 ps
CPU time 1.28 seconds
Started Jul 09 05:04:45 PM PDT 24
Finished Jul 09 05:04:50 PM PDT 24
Peak memory 217988 kb
Host smart-8438a886-7212-41b9-b146-9354cc0809b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102418814 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.3102418814
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2444228550
Short name T870
Test name
Test status
Simulation time 29777497 ps
CPU time 0.93 seconds
Started Jul 09 05:04:51 PM PDT 24
Finished Jul 09 05:04:55 PM PDT 24
Peak memory 208932 kb
Host smart-1edcdb37-e06d-4381-82ce-1594f21a49f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444228550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.2444228550
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2306285034
Short name T900
Test name
Test status
Simulation time 300481257 ps
CPU time 2.44 seconds
Started Jul 09 05:04:52 PM PDT 24
Finished Jul 09 05:04:59 PM PDT 24
Peak memory 208960 kb
Host smart-0a215477-54ad-4327-87fd-d3e55528258f
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306285034 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.2306285034
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2024218272
Short name T963
Test name
Test status
Simulation time 3567793734 ps
CPU time 22.21 seconds
Started Jul 09 05:04:46 PM PDT 24
Finished Jul 09 05:05:12 PM PDT 24
Peak memory 209124 kb
Host smart-fc10344d-200d-4584-9824-fb61a7ce0460
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024218272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.2024218272
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.297654510
Short name T990
Test name
Test status
Simulation time 329576730 ps
CPU time 4.37 seconds
Started Jul 09 05:04:48 PM PDT 24
Finished Jul 09 05:04:56 PM PDT 24
Peak memory 210236 kb
Host smart-afd9af32-495b-4665-a091-89ed5baeba89
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297654510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.297654510
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2928916979
Short name T976
Test name
Test status
Simulation time 604780701 ps
CPU time 2.19 seconds
Started Jul 09 05:04:49 PM PDT 24
Finished Jul 09 05:04:55 PM PDT 24
Peak memory 218456 kb
Host smart-944fda66-b8e8-42f1-8fdd-d38efb320910
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292891
6979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2928916979
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3586709439
Short name T879
Test name
Test status
Simulation time 423354720 ps
CPU time 1.12 seconds
Started Jul 09 05:04:42 PM PDT 24
Finished Jul 09 05:04:46 PM PDT 24
Peak memory 217232 kb
Host smart-7d39b3cb-6304-4eb2-b3b9-9e44847ba620
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586709439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.3586709439
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.941253841
Short name T951
Test name
Test status
Simulation time 110169425 ps
CPU time 1.25 seconds
Started Jul 09 05:04:49 PM PDT 24
Finished Jul 09 05:04:55 PM PDT 24
Peak memory 211120 kb
Host smart-2d049857-f968-4bc9-9634-05aa09301348
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941253841 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.941253841
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2667990341
Short name T904
Test name
Test status
Simulation time 26651363 ps
CPU time 1.14 seconds
Started Jul 09 05:04:50 PM PDT 24
Finished Jul 09 05:04:55 PM PDT 24
Peak memory 217480 kb
Host smart-2ddb2c48-3367-4e13-bb7e-4ab97516e9cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667990341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.2667990341
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.33507286
Short name T109
Test name
Test status
Simulation time 44182103 ps
CPU time 2.72 seconds
Started Jul 09 05:04:53 PM PDT 24
Finished Jul 09 05:05:00 PM PDT 24
Peak memory 217336 kb
Host smart-5747f71a-a9ad-427b-b25e-338094119f1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33507286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.33507286
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1902424551
Short name T965
Test name
Test status
Simulation time 100313330 ps
CPU time 2.4 seconds
Started Jul 09 05:04:53 PM PDT 24
Finished Jul 09 05:05:00 PM PDT 24
Peak memory 212796 kb
Host smart-02464f7b-f8bb-4f60-85a9-70a43ec93014
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902424551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.1902424551
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.4279032938
Short name T876
Test name
Test status
Simulation time 124165042 ps
CPU time 1.66 seconds
Started Jul 09 05:04:49 PM PDT 24
Finished Jul 09 05:04:55 PM PDT 24
Peak memory 217412 kb
Host smart-fa805b5c-3f86-453a-bc77-066b92611d21
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279032938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.4279032938
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1263285192
Short name T171
Test name
Test status
Simulation time 53797606 ps
CPU time 1.5 seconds
Started Jul 09 05:04:52 PM PDT 24
Finished Jul 09 05:04:58 PM PDT 24
Peak memory 209156 kb
Host smart-abff0488-f24b-4350-adcd-511f8fe1dbae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263285192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.1263285192
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.646862912
Short name T983
Test name
Test status
Simulation time 95492530 ps
CPU time 1.24 seconds
Started Jul 09 05:04:50 PM PDT 24
Finished Jul 09 05:04:55 PM PDT 24
Peak memory 210768 kb
Host smart-c22701ee-edf1-497d-83ab-12e6405756ea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646862912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_reset
.646862912
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1539229296
Short name T920
Test name
Test status
Simulation time 51342808 ps
CPU time 1.25 seconds
Started Jul 09 05:04:51 PM PDT 24
Finished Jul 09 05:04:56 PM PDT 24
Peak memory 217348 kb
Host smart-2c31c1eb-1ab6-403e-90b7-1ff251d6ef53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539229296 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.1539229296
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1674629426
Short name T958
Test name
Test status
Simulation time 105542521 ps
CPU time 2.59 seconds
Started Jul 09 05:04:53 PM PDT 24
Finished Jul 09 05:05:00 PM PDT 24
Peak memory 209008 kb
Host smart-176da0ad-40b2-473a-ac7d-0708e7322186
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674629426 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.1674629426
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3293825067
Short name T978
Test name
Test status
Simulation time 881641279 ps
CPU time 4.17 seconds
Started Jul 09 05:04:49 PM PDT 24
Finished Jul 09 05:04:57 PM PDT 24
Peak memory 209168 kb
Host smart-cc669c82-d044-4a5b-89a6-3a100c77b063
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293825067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.3293825067
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1558122873
Short name T945
Test name
Test status
Simulation time 1241036369 ps
CPU time 15.89 seconds
Started Jul 09 05:04:52 PM PDT 24
Finished Jul 09 05:05:12 PM PDT 24
Peak memory 208608 kb
Host smart-af17e351-10dc-491a-89de-c688176c8e85
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558122873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.1558122873
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1357264535
Short name T943
Test name
Test status
Simulation time 333975390 ps
CPU time 1.79 seconds
Started Jul 09 05:04:47 PM PDT 24
Finished Jul 09 05:04:53 PM PDT 24
Peak memory 210656 kb
Host smart-1916abd2-7142-4590-9e92-3dab4f94a097
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357264535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.1357264535
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2169580930
Short name T969
Test name
Test status
Simulation time 75503268 ps
CPU time 1.56 seconds
Started Jul 09 05:04:53 PM PDT 24
Finished Jul 09 05:04:59 PM PDT 24
Peak memory 217432 kb
Host smart-979f9b3f-f884-4db4-b379-f9d415405242
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216958
0930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2169580930
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3236927415
Short name T932
Test name
Test status
Simulation time 347860163 ps
CPU time 1.63 seconds
Started Jul 09 05:04:48 PM PDT 24
Finished Jul 09 05:04:54 PM PDT 24
Peak memory 217128 kb
Host smart-9fcf22e8-ae46-4ed7-9a46-7ef0c554b7d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236927415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.3236927415
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2935514460
Short name T182
Test name
Test status
Simulation time 95553855 ps
CPU time 1.11 seconds
Started Jul 09 05:04:51 PM PDT 24
Finished Jul 09 05:04:56 PM PDT 24
Peak memory 217300 kb
Host smart-d70ee4a8-db3b-4aa0-8a4d-cd0e30ab9fb0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935514460 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.2935514460
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1256287436
Short name T956
Test name
Test status
Simulation time 43755071 ps
CPU time 1.09 seconds
Started Jul 09 05:04:51 PM PDT 24
Finished Jul 09 05:04:56 PM PDT 24
Peak memory 217364 kb
Host smart-d6553173-5a5d-45d4-85e7-727b343b5c6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256287436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.1256287436
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.28305961
Short name T883
Test name
Test status
Simulation time 26272461 ps
CPU time 2.07 seconds
Started Jul 09 05:04:51 PM PDT 24
Finished Jul 09 05:04:57 PM PDT 24
Peak memory 217488 kb
Host smart-7a91bec2-4c5b-4821-956c-ead8f841cfde
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28305961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.28305961
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2507425385
Short name T127
Test name
Test status
Simulation time 40671782 ps
CPU time 1.94 seconds
Started Jul 09 05:04:48 PM PDT 24
Finished Jul 09 05:04:54 PM PDT 24
Peak memory 221840 kb
Host smart-a9e04375-6234-456b-813f-483999ba23d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507425385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.2507425385
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2890596871
Short name T907
Test name
Test status
Simulation time 121240784 ps
CPU time 1.44 seconds
Started Jul 09 05:05:10 PM PDT 24
Finished Jul 09 05:05:15 PM PDT 24
Peak memory 223272 kb
Host smart-5b97add2-d01f-4be1-9af9-1362d643bf80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890596871 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.2890596871
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1198736702
Short name T957
Test name
Test status
Simulation time 18919165 ps
CPU time 1.16 seconds
Started Jul 09 05:05:08 PM PDT 24
Finished Jul 09 05:05:12 PM PDT 24
Peak memory 209032 kb
Host smart-7afac1e2-b084-4c0a-b61c-62d7968b386f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198736702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.1198736702
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.1792352574
Short name T178
Test name
Test status
Simulation time 19683291 ps
CPU time 0.93 seconds
Started Jul 09 05:05:07 PM PDT 24
Finished Jul 09 05:05:12 PM PDT 24
Peak memory 209228 kb
Host smart-13d60280-f218-4a58-a721-d11119c6b792
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792352574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.1792352574
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.537048505
Short name T938
Test name
Test status
Simulation time 99771495 ps
CPU time 4.45 seconds
Started Jul 09 05:05:09 PM PDT 24
Finished Jul 09 05:05:17 PM PDT 24
Peak memory 217376 kb
Host smart-a0f78595-ae66-4ea7-bbdc-8f2490e722e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537048505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.537048505
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.72531869
Short name T950
Test name
Test status
Simulation time 19297218 ps
CPU time 1.33 seconds
Started Jul 09 05:05:09 PM PDT 24
Finished Jul 09 05:05:14 PM PDT 24
Peak memory 218104 kb
Host smart-534bdfbd-ea43-4aa4-b35e-5c1201fd4589
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72531869 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.72531869
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.4234949882
Short name T168
Test name
Test status
Simulation time 19684943 ps
CPU time 0.96 seconds
Started Jul 09 05:05:09 PM PDT 24
Finished Jul 09 05:05:13 PM PDT 24
Peak memory 209136 kb
Host smart-7baacebc-17ca-4460-bb41-10a41830d826
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234949882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.4234949882
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.48764233
Short name T887
Test name
Test status
Simulation time 105793158 ps
CPU time 1.93 seconds
Started Jul 09 05:05:08 PM PDT 24
Finished Jul 09 05:05:14 PM PDT 24
Peak memory 209128 kb
Host smart-5f19095c-b062-4728-8307-969024223abd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48764233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_
same_csr_outstanding.48764233
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3024207457
Short name T964
Test name
Test status
Simulation time 31775291 ps
CPU time 2.43 seconds
Started Jul 09 05:05:09 PM PDT 24
Finished Jul 09 05:05:15 PM PDT 24
Peak memory 218440 kb
Host smart-e3e989e2-322d-4fe2-8632-af3996279df1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024207457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.3024207457
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1659912026
Short name T115
Test name
Test status
Simulation time 285041586 ps
CPU time 3.47 seconds
Started Jul 09 05:05:08 PM PDT 24
Finished Jul 09 05:05:15 PM PDT 24
Peak memory 222076 kb
Host smart-bca9731d-acbb-4faa-9a72-5567da8c017e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659912026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.1659912026
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.4030836844
Short name T889
Test name
Test status
Simulation time 21088714 ps
CPU time 1.15 seconds
Started Jul 09 05:05:12 PM PDT 24
Finished Jul 09 05:05:17 PM PDT 24
Peak memory 217396 kb
Host smart-f3dcd657-e17b-4a47-9a07-f5bbe0a2334a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030836844 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.4030836844
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3953645742
Short name T166
Test name
Test status
Simulation time 15445292 ps
CPU time 0.96 seconds
Started Jul 09 05:05:11 PM PDT 24
Finished Jul 09 05:05:16 PM PDT 24
Peak memory 209236 kb
Host smart-f855e161-3746-4e64-949a-c181ec85794b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953645742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.3953645742
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1537287336
Short name T974
Test name
Test status
Simulation time 62228818 ps
CPU time 1.26 seconds
Started Jul 09 05:05:13 PM PDT 24
Finished Jul 09 05:05:18 PM PDT 24
Peak memory 217388 kb
Host smart-349e670c-25c2-4cb1-b21c-822c5a008b17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537287336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.1537287336
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1333299799
Short name T941
Test name
Test status
Simulation time 154491264 ps
CPU time 3.66 seconds
Started Jul 09 05:05:11 PM PDT 24
Finished Jul 09 05:05:19 PM PDT 24
Peak memory 217320 kb
Host smart-c0b7fbb3-9615-4ddb-8f9f-0e6fc05fd326
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333299799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.1333299799
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3324847951
Short name T125
Test name
Test status
Simulation time 108323092 ps
CPU time 4.1 seconds
Started Jul 09 05:05:13 PM PDT 24
Finished Jul 09 05:05:21 PM PDT 24
Peak memory 217424 kb
Host smart-31a5a041-6738-43bd-8bb5-21d3de90591f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324847951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.3324847951
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2030197737
Short name T908
Test name
Test status
Simulation time 57063233 ps
CPU time 1.41 seconds
Started Jul 09 05:05:12 PM PDT 24
Finished Jul 09 05:05:18 PM PDT 24
Peak memory 218388 kb
Host smart-9cc0752a-99e4-4849-b5f5-db8b9c822fc7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030197737 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.2030197737
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3470525340
Short name T169
Test name
Test status
Simulation time 44920470 ps
CPU time 0.86 seconds
Started Jul 09 05:05:08 PM PDT 24
Finished Jul 09 05:05:12 PM PDT 24
Peak memory 208500 kb
Host smart-1094f34d-a04a-4478-a08e-597e181d2bf0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470525340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.3470525340
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.4171845763
Short name T181
Test name
Test status
Simulation time 241896968 ps
CPU time 1.34 seconds
Started Jul 09 05:05:10 PM PDT 24
Finished Jul 09 05:05:15 PM PDT 24
Peak memory 209168 kb
Host smart-9b0f3d0b-a7ea-4c79-b131-029eccb26592
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171845763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.4171845763
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.1770376211
Short name T108
Test name
Test status
Simulation time 72131654 ps
CPU time 2.25 seconds
Started Jul 09 05:05:13 PM PDT 24
Finished Jul 09 05:05:19 PM PDT 24
Peak memory 217564 kb
Host smart-65bb084c-7b12-4dc0-abff-1787cd30435b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770376211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.1770376211
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.985486372
Short name T935
Test name
Test status
Simulation time 64957758 ps
CPU time 2.95 seconds
Started Jul 09 05:05:10 PM PDT 24
Finished Jul 09 05:05:16 PM PDT 24
Peak memory 217488 kb
Host smart-d083c7f7-e4a8-4e8c-9282-c396d4f16a30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985486372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg_
err.985486372
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2340726465
Short name T948
Test name
Test status
Simulation time 70034774 ps
CPU time 1.37 seconds
Started Jul 09 05:05:10 PM PDT 24
Finished Jul 09 05:05:15 PM PDT 24
Peak memory 221664 kb
Host smart-8a82fb41-ced6-46b3-b001-a25cb29cbd2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340726465 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.2340726465
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3979675059
Short name T106
Test name
Test status
Simulation time 12609317 ps
CPU time 1.02 seconds
Started Jul 09 05:05:08 PM PDT 24
Finished Jul 09 05:05:13 PM PDT 24
Peak memory 209036 kb
Host smart-1a336d77-75ba-40b5-8759-32aa227d2172
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979675059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.3979675059
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3782516729
Short name T944
Test name
Test status
Simulation time 63000049 ps
CPU time 1.45 seconds
Started Jul 09 05:05:11 PM PDT 24
Finished Jul 09 05:05:16 PM PDT 24
Peak memory 211108 kb
Host smart-5238732f-7efa-4dfc-8e2d-3e81391b1295
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782516729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.3782516729
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1153839284
Short name T917
Test name
Test status
Simulation time 225287622 ps
CPU time 3.66 seconds
Started Jul 09 05:05:15 PM PDT 24
Finished Jul 09 05:05:21 PM PDT 24
Peak memory 217296 kb
Host smart-2b4f2aef-9573-4be9-9e1e-dd2734d0f8a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153839284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.1153839284
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2156854922
Short name T960
Test name
Test status
Simulation time 41093897 ps
CPU time 1.5 seconds
Started Jul 09 05:05:11 PM PDT 24
Finished Jul 09 05:05:16 PM PDT 24
Peak memory 219044 kb
Host smart-e3221bec-4ce7-4e7f-9a22-3c7e56aa892b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156854922 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.2156854922
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2884342376
Short name T107
Test name
Test status
Simulation time 27862009 ps
CPU time 0.86 seconds
Started Jul 09 05:05:11 PM PDT 24
Finished Jul 09 05:05:16 PM PDT 24
Peak memory 209220 kb
Host smart-d2119fb0-0e48-462e-92be-b8bde88ebf64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884342376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.2884342376
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2788844517
Short name T987
Test name
Test status
Simulation time 27126844 ps
CPU time 1.04 seconds
Started Jul 09 05:05:12 PM PDT 24
Finished Jul 09 05:05:17 PM PDT 24
Peak memory 209160 kb
Host smart-308997a1-1d0f-4dcb-8efb-dcf39d758142
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788844517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.2788844517
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.757690798
Short name T865
Test name
Test status
Simulation time 64960797 ps
CPU time 2.28 seconds
Started Jul 09 05:05:09 PM PDT 24
Finished Jul 09 05:05:15 PM PDT 24
Peak memory 217708 kb
Host smart-c875b22b-1557-47fb-9399-a6d11f36f912
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757690798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.757690798
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1290061441
Short name T912
Test name
Test status
Simulation time 21008134 ps
CPU time 1.67 seconds
Started Jul 09 05:05:17 PM PDT 24
Finished Jul 09 05:05:20 PM PDT 24
Peak memory 222800 kb
Host smart-8c657aa7-b350-462d-be6e-2eaab7afaa2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290061441 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.1290061441
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.2745191271
Short name T140
Test name
Test status
Simulation time 19414881 ps
CPU time 1.2 seconds
Started Jul 09 05:05:17 PM PDT 24
Finished Jul 09 05:05:20 PM PDT 24
Peak memory 209216 kb
Host smart-e1dcb889-6486-44d8-8982-6a88abfe63eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745191271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.2745191271
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1009523382
Short name T180
Test name
Test status
Simulation time 212785472 ps
CPU time 1.49 seconds
Started Jul 09 05:05:12 PM PDT 24
Finished Jul 09 05:05:18 PM PDT 24
Peak memory 211324 kb
Host smart-42b844f8-5738-45a2-a3c0-9b274cb441b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009523382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.1009523382
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3355197924
Short name T895
Test name
Test status
Simulation time 1173726579 ps
CPU time 3.68 seconds
Started Jul 09 05:05:16 PM PDT 24
Finished Jul 09 05:05:22 PM PDT 24
Peak memory 217348 kb
Host smart-041b1584-9e05-4eab-a4ea-9229790a8c4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355197924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.3355197924
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.3866032044
Short name T120
Test name
Test status
Simulation time 144779395 ps
CPU time 3.27 seconds
Started Jul 09 05:05:15 PM PDT 24
Finished Jul 09 05:05:21 PM PDT 24
Peak memory 217304 kb
Host smart-50c6299a-376f-4b91-8e04-21d065a497d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866032044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.3866032044
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3943925563
Short name T896
Test name
Test status
Simulation time 88141361 ps
CPU time 1.49 seconds
Started Jul 09 05:05:12 PM PDT 24
Finished Jul 09 05:05:18 PM PDT 24
Peak memory 217400 kb
Host smart-fe38aeff-89c5-4406-852a-82606957bde3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943925563 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.3943925563
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.494445985
Short name T992
Test name
Test status
Simulation time 12977422 ps
CPU time 0.87 seconds
Started Jul 09 05:05:17 PM PDT 24
Finished Jul 09 05:05:19 PM PDT 24
Peak memory 208796 kb
Host smart-2783f47f-1a27-4689-80e1-2802e9a398e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494445985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.494445985
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.615678602
Short name T183
Test name
Test status
Simulation time 180674037 ps
CPU time 1.45 seconds
Started Jul 09 05:05:16 PM PDT 24
Finished Jul 09 05:05:20 PM PDT 24
Peak memory 209248 kb
Host smart-636dc7f4-0ad1-4713-978a-eb162e9b00dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615678602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_same_csr_outstanding.615678602
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.4263496343
Short name T884
Test name
Test status
Simulation time 117958822 ps
CPU time 3.36 seconds
Started Jul 09 05:05:14 PM PDT 24
Finished Jul 09 05:05:21 PM PDT 24
Peak memory 217472 kb
Host smart-22275ef1-58c0-4bbe-9d4c-dd310f21c287
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263496343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.4263496343
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3824014741
Short name T104
Test name
Test status
Simulation time 180703145 ps
CPU time 2.05 seconds
Started Jul 09 05:05:16 PM PDT 24
Finished Jul 09 05:05:20 PM PDT 24
Peak memory 221992 kb
Host smart-68e1af86-d455-47c3-955b-3b6380390b92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824014741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.3824014741
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2748996381
Short name T888
Test name
Test status
Simulation time 138322718 ps
CPU time 2.26 seconds
Started Jul 09 05:05:18 PM PDT 24
Finished Jul 09 05:05:22 PM PDT 24
Peak memory 217560 kb
Host smart-5cacc788-6b84-43ba-9f72-e612ead2f471
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748996381 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.2748996381
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2128885463
Short name T909
Test name
Test status
Simulation time 15927021 ps
CPU time 0.93 seconds
Started Jul 09 05:05:13 PM PDT 24
Finished Jul 09 05:05:18 PM PDT 24
Peak memory 209228 kb
Host smart-12f01f1c-73b0-4102-acc5-6da5b4891952
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128885463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.2128885463
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.553317872
Short name T959
Test name
Test status
Simulation time 22408131 ps
CPU time 1.27 seconds
Started Jul 09 05:05:15 PM PDT 24
Finished Jul 09 05:05:19 PM PDT 24
Peak memory 209108 kb
Host smart-b73187f1-6389-4179-b599-74afbea40db4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553317872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_same_csr_outstanding.553317872
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.4219268699
Short name T977
Test name
Test status
Simulation time 127137187 ps
CPU time 2.7 seconds
Started Jul 09 05:05:14 PM PDT 24
Finished Jul 09 05:05:20 PM PDT 24
Peak memory 217472 kb
Host smart-b5abc8e4-da14-482b-9bd0-e07cc4f95da9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219268699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.4219268699
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1272915489
Short name T124
Test name
Test status
Simulation time 239866540 ps
CPU time 2.94 seconds
Started Jul 09 05:05:14 PM PDT 24
Finished Jul 09 05:05:20 PM PDT 24
Peak memory 222000 kb
Host smart-e7f2afc1-2b04-4167-b9bf-97c284edac1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272915489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.1272915489
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3381831832
Short name T919
Test name
Test status
Simulation time 53724533 ps
CPU time 1.6 seconds
Started Jul 09 05:05:14 PM PDT 24
Finished Jul 09 05:05:19 PM PDT 24
Peak memory 217424 kb
Host smart-72b2240a-aa5a-414b-86fe-844c93cf5260
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381831832 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.3381831832
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3039441691
Short name T164
Test name
Test status
Simulation time 21169209 ps
CPU time 0.94 seconds
Started Jul 09 05:05:14 PM PDT 24
Finished Jul 09 05:05:18 PM PDT 24
Peak memory 209120 kb
Host smart-de9c2311-42eb-4f0b-8915-1beab8c59efc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039441691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.3039441691
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2742507073
Short name T877
Test name
Test status
Simulation time 108355742 ps
CPU time 1.29 seconds
Started Jul 09 05:05:17 PM PDT 24
Finished Jul 09 05:05:20 PM PDT 24
Peak memory 217384 kb
Host smart-d78c02e1-e4ab-4266-b225-542228163e97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742507073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.2742507073
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3556610856
Short name T99
Test name
Test status
Simulation time 163434570 ps
CPU time 3.29 seconds
Started Jul 09 05:05:14 PM PDT 24
Finished Jul 09 05:05:21 PM PDT 24
Peak memory 217376 kb
Host smart-e5baf06b-cee3-49bd-83ee-62fb7bfbac1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556610856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.3556610856
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2879260172
Short name T173
Test name
Test status
Simulation time 23794002 ps
CPU time 1.1 seconds
Started Jul 09 05:04:52 PM PDT 24
Finished Jul 09 05:04:57 PM PDT 24
Peak memory 209184 kb
Host smart-3f0ddcaf-8b55-4f2a-a668-fce035cb6df3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879260172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.2879260172
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.767146437
Short name T954
Test name
Test status
Simulation time 96306719 ps
CPU time 1.88 seconds
Started Jul 09 05:04:55 PM PDT 24
Finished Jul 09 05:05:03 PM PDT 24
Peak memory 209248 kb
Host smart-16c05238-a8f8-4f1f-b64a-e4deeb600882
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767146437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bash
.767146437
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.355397490
Short name T882
Test name
Test status
Simulation time 18596450 ps
CPU time 1.03 seconds
Started Jul 09 05:04:52 PM PDT 24
Finished Jul 09 05:04:57 PM PDT 24
Peak memory 209792 kb
Host smart-649719b6-6650-4db3-b398-25870427cfbe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355397490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_reset
.355397490
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1972899723
Short name T928
Test name
Test status
Simulation time 22927746 ps
CPU time 1.12 seconds
Started Jul 09 05:04:57 PM PDT 24
Finished Jul 09 05:05:03 PM PDT 24
Peak memory 218864 kb
Host smart-792a2333-6247-40d1-8184-54a485f837a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972899723 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.1972899723
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.524621931
Short name T174
Test name
Test status
Simulation time 49152335 ps
CPU time 1.03 seconds
Started Jul 09 05:04:53 PM PDT 24
Finished Jul 09 05:04:59 PM PDT 24
Peak memory 208752 kb
Host smart-d1a3900d-4f0e-41d8-8560-73d3e39863f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524621931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.524621931
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2856998458
Short name T910
Test name
Test status
Simulation time 59270846 ps
CPU time 1.27 seconds
Started Jul 09 05:04:52 PM PDT 24
Finished Jul 09 05:04:57 PM PDT 24
Peak memory 208412 kb
Host smart-449694fd-7bf9-42d1-8a94-55bf55d01b95
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856998458 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.2856998458
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2443964728
Short name T921
Test name
Test status
Simulation time 1099129006 ps
CPU time 5.71 seconds
Started Jul 09 05:04:56 PM PDT 24
Finished Jul 09 05:05:07 PM PDT 24
Peak memory 216916 kb
Host smart-30a30950-dedc-4829-a29c-26e33c195169
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443964728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.2443964728
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.4218342597
Short name T132
Test name
Test status
Simulation time 3461122951 ps
CPU time 5.15 seconds
Started Jul 09 05:04:49 PM PDT 24
Finished Jul 09 05:04:57 PM PDT 24
Peak memory 209144 kb
Host smart-b934ced0-c68e-4db2-95f5-eb665d29b0e1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218342597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.4218342597
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2611144990
Short name T894
Test name
Test status
Simulation time 186088691 ps
CPU time 1.87 seconds
Started Jul 09 05:04:51 PM PDT 24
Finished Jul 09 05:04:57 PM PDT 24
Peak memory 217396 kb
Host smart-eae52d6e-7b40-4420-a124-04c8ca6ca650
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611144990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.2611144990
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.527366745
Short name T913
Test name
Test status
Simulation time 199516751 ps
CPU time 3.58 seconds
Started Jul 09 05:04:52 PM PDT 24
Finished Jul 09 05:05:00 PM PDT 24
Peak memory 218516 kb
Host smart-f31358ea-c335-4a86-abec-d07d88962d08
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527366
745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.527366745
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3434152873
Short name T915
Test name
Test status
Simulation time 310069688 ps
CPU time 2.46 seconds
Started Jul 09 05:04:53 PM PDT 24
Finished Jul 09 05:05:00 PM PDT 24
Peak memory 217292 kb
Host smart-78ce3b51-1515-4d60-99ab-4a6e24cb46d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434152873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.3434152873
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1778891597
Short name T911
Test name
Test status
Simulation time 39431397 ps
CPU time 1.47 seconds
Started Jul 09 05:04:52 PM PDT 24
Finished Jul 09 05:04:58 PM PDT 24
Peak memory 209144 kb
Host smart-8debd49f-c44d-4ba6-b142-cdb25720ee06
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778891597 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.1778891597
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.842615725
Short name T947
Test name
Test status
Simulation time 15177339 ps
CPU time 1.03 seconds
Started Jul 09 05:04:56 PM PDT 24
Finished Jul 09 05:05:03 PM PDT 24
Peak memory 209056 kb
Host smart-79cac89c-80ef-4645-800f-4c9474c5c8d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842615725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
same_csr_outstanding.842615725
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.223610580
Short name T100
Test name
Test status
Simulation time 338318455 ps
CPU time 2.77 seconds
Started Jul 09 05:04:52 PM PDT 24
Finished Jul 09 05:04:59 PM PDT 24
Peak memory 217316 kb
Host smart-de85e0a5-9ed2-41b7-82ee-a9cbebb7154b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223610580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.223610580
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3612216555
Short name T886
Test name
Test status
Simulation time 88621882 ps
CPU time 1.12 seconds
Started Jul 09 05:05:03 PM PDT 24
Finished Jul 09 05:05:09 PM PDT 24
Peak memory 209092 kb
Host smart-0ea61257-3fa2-4b61-85bf-ea0c81d4053a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612216555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.3612216555
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2777470268
Short name T922
Test name
Test status
Simulation time 27018755 ps
CPU time 1.64 seconds
Started Jul 09 05:04:56 PM PDT 24
Finished Jul 09 05:05:03 PM PDT 24
Peak memory 209068 kb
Host smart-a0ec6db5-437a-454f-9cf9-1c524fb427e3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777470268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.2777470268
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3329029324
Short name T167
Test name
Test status
Simulation time 49610059 ps
CPU time 0.9 seconds
Started Jul 09 05:04:59 PM PDT 24
Finished Jul 09 05:05:05 PM PDT 24
Peak memory 209612 kb
Host smart-5cd921de-b97e-480a-8ac6-a2f13d456bff
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329029324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.3329029324
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3693432514
Short name T872
Test name
Test status
Simulation time 31868927 ps
CPU time 1.86 seconds
Started Jul 09 05:04:57 PM PDT 24
Finished Jul 09 05:05:05 PM PDT 24
Peak memory 217864 kb
Host smart-e5a37e9c-012f-4bff-a397-439a3a371d8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693432514 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.3693432514
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.297095754
Short name T177
Test name
Test status
Simulation time 32488211 ps
CPU time 0.86 seconds
Started Jul 09 05:04:51 PM PDT 24
Finished Jul 09 05:04:56 PM PDT 24
Peak memory 208712 kb
Host smart-497767e1-5d4f-4efb-8eba-786abdf1d379
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297095754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.297095754
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.508500052
Short name T867
Test name
Test status
Simulation time 322435091 ps
CPU time 2.53 seconds
Started Jul 09 05:04:52 PM PDT 24
Finished Jul 09 05:04:59 PM PDT 24
Peak memory 209100 kb
Host smart-d4175d3c-2f3d-451a-b670-810a4c00900e
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508500052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.lc_ctrl_jtag_alert_test.508500052
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3768140690
Short name T923
Test name
Test status
Simulation time 444424073 ps
CPU time 7.43 seconds
Started Jul 09 05:04:56 PM PDT 24
Finished Jul 09 05:05:09 PM PDT 24
Peak memory 216824 kb
Host smart-ece1a635-9cac-4d29-b479-37c57b39178a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768140690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.3768140690
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.137483876
Short name T881
Test name
Test status
Simulation time 694931385 ps
CPU time 18.08 seconds
Started Jul 09 05:04:53 PM PDT 24
Finished Jul 09 05:05:16 PM PDT 24
Peak memory 208840 kb
Host smart-5111d440-f948-4192-a102-fd6f2b8df110
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137483876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.137483876
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1152967982
Short name T971
Test name
Test status
Simulation time 299138831 ps
CPU time 1.97 seconds
Started Jul 09 05:04:53 PM PDT 24
Finished Jul 09 05:04:59 PM PDT 24
Peak memory 217276 kb
Host smart-f0597175-deaa-4635-b8a1-fec00ef66a19
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152967982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.1152967982
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3156064295
Short name T982
Test name
Test status
Simulation time 122122206 ps
CPU time 3.75 seconds
Started Jul 09 05:04:54 PM PDT 24
Finished Jul 09 05:05:03 PM PDT 24
Peak memory 218464 kb
Host smart-1366c887-6e6b-4600-8638-38a4517de20f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315606
4295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3156064295
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1738642591
Short name T918
Test name
Test status
Simulation time 57808269 ps
CPU time 1.32 seconds
Started Jul 09 05:04:53 PM PDT 24
Finished Jul 09 05:04:59 PM PDT 24
Peak memory 209172 kb
Host smart-e715bea6-b92e-4a6b-a839-91fd422f5ece
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738642591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.1738642591
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3140730354
Short name T141
Test name
Test status
Simulation time 25398036 ps
CPU time 1.11 seconds
Started Jul 09 05:04:53 PM PDT 24
Finished Jul 09 05:04:59 PM PDT 24
Peak memory 209348 kb
Host smart-8fccbce9-a7ff-449a-87bc-a4a572daccf3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140730354 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.3140730354
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.249483563
Short name T111
Test name
Test status
Simulation time 21740887 ps
CPU time 1.5 seconds
Started Jul 09 05:05:00 PM PDT 24
Finished Jul 09 05:05:07 PM PDT 24
Peak memory 209220 kb
Host smart-b9ced7ad-628b-4cd2-a2fa-8b6fb27712f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249483563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
same_csr_outstanding.249483563
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1867957285
Short name T986
Test name
Test status
Simulation time 1081036313 ps
CPU time 4.03 seconds
Started Jul 09 05:04:55 PM PDT 24
Finished Jul 09 05:05:04 PM PDT 24
Peak memory 217496 kb
Host smart-cd3a3452-f46a-4ffe-9707-0c8b4d327a76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867957285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.1867957285
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1556809833
Short name T905
Test name
Test status
Simulation time 23852010 ps
CPU time 1.36 seconds
Started Jul 09 05:05:01 PM PDT 24
Finished Jul 09 05:05:07 PM PDT 24
Peak memory 209136 kb
Host smart-8088fc71-a5a2-4e18-8682-de519c570e21
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556809833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.1556809833
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2571203964
Short name T869
Test name
Test status
Simulation time 921135027 ps
CPU time 2.71 seconds
Started Jul 09 05:04:57 PM PDT 24
Finished Jul 09 05:05:05 PM PDT 24
Peak memory 216892 kb
Host smart-926ee2de-5934-4a75-a41e-d89c04eb103f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571203964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.2571203964
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3879298837
Short name T172
Test name
Test status
Simulation time 12618893 ps
CPU time 1.09 seconds
Started Jul 09 05:04:57 PM PDT 24
Finished Jul 09 05:05:03 PM PDT 24
Peak memory 209824 kb
Host smart-20a9f786-ecdc-420b-bab9-c641f3dd36a7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879298837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.3879298837
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3930573537
Short name T929
Test name
Test status
Simulation time 36380269 ps
CPU time 1.39 seconds
Started Jul 09 05:04:57 PM PDT 24
Finished Jul 09 05:05:04 PM PDT 24
Peak memory 217424 kb
Host smart-64f41837-c8a2-408c-9776-2eadd2c493da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930573537 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.3930573537
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1435289450
Short name T176
Test name
Test status
Simulation time 52418013 ps
CPU time 1.06 seconds
Started Jul 09 05:04:58 PM PDT 24
Finished Jul 09 05:05:04 PM PDT 24
Peak memory 209220 kb
Host smart-d6767b6c-b851-47f5-9181-517ed2a42c1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435289450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.1435289450
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1528757294
Short name T937
Test name
Test status
Simulation time 165945647 ps
CPU time 1.07 seconds
Started Jul 09 05:05:02 PM PDT 24
Finished Jul 09 05:05:08 PM PDT 24
Peak memory 208572 kb
Host smart-9df405a5-1fac-42a2-a232-2f83a7e91845
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528757294 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.1528757294
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1692406627
Short name T112
Test name
Test status
Simulation time 1009555083 ps
CPU time 6.63 seconds
Started Jul 09 05:04:59 PM PDT 24
Finished Jul 09 05:05:10 PM PDT 24
Peak memory 208948 kb
Host smart-ca924ddb-449a-42b4-aa77-02e842edefe3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692406627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.1692406627
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1697791488
Short name T927
Test name
Test status
Simulation time 1242670299 ps
CPU time 11.64 seconds
Started Jul 09 05:04:56 PM PDT 24
Finished Jul 09 05:05:13 PM PDT 24
Peak memory 208548 kb
Host smart-62cfe1cc-cf6b-413e-b542-ee3a2509e8ac
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697791488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.1697791488
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.681059128
Short name T962
Test name
Test status
Simulation time 100626477 ps
CPU time 2.05 seconds
Started Jul 09 05:04:57 PM PDT 24
Finished Jul 09 05:05:04 PM PDT 24
Peak memory 210528 kb
Host smart-63da5c75-4928-4fd4-8cfa-dcde6bcd0190
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681059128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.681059128
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1932933564
Short name T939
Test name
Test status
Simulation time 391433538 ps
CPU time 1.86 seconds
Started Jul 09 05:05:02 PM PDT 24
Finished Jul 09 05:05:09 PM PDT 24
Peak memory 217448 kb
Host smart-e0b34b1c-ce48-4bc5-a54d-e5be961d19d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193293
3564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1932933564
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.3393539782
Short name T973
Test name
Test status
Simulation time 105687212 ps
CPU time 1.77 seconds
Started Jul 09 05:05:02 PM PDT 24
Finished Jul 09 05:05:09 PM PDT 24
Peak memory 209100 kb
Host smart-e57a9e81-8291-4d53-b6dd-4a5d2751d564
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393539782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.3393539782
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2727779367
Short name T940
Test name
Test status
Simulation time 48596676 ps
CPU time 2.19 seconds
Started Jul 09 05:04:59 PM PDT 24
Finished Jul 09 05:05:06 PM PDT 24
Peak memory 211412 kb
Host smart-ea5211cd-e6bf-4870-b901-cd846044a9a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727779367 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.2727779367
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2384366115
Short name T924
Test name
Test status
Simulation time 19368671 ps
CPU time 1.19 seconds
Started Jul 09 05:04:58 PM PDT 24
Finished Jul 09 05:05:05 PM PDT 24
Peak memory 211372 kb
Host smart-dd6b41fb-4b97-48c5-856a-b7aca9af9b1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384366115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.2384366115
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1150483610
Short name T105
Test name
Test status
Simulation time 44887905 ps
CPU time 2.35 seconds
Started Jul 09 05:04:57 PM PDT 24
Finished Jul 09 05:05:04 PM PDT 24
Peak memory 217312 kb
Host smart-49e9c8bb-254f-4c93-ab8a-059680d46b52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150483610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.1150483610
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.4037528945
Short name T981
Test name
Test status
Simulation time 59757185 ps
CPU time 1.02 seconds
Started Jul 09 05:05:03 PM PDT 24
Finished Jul 09 05:05:09 PM PDT 24
Peak memory 217516 kb
Host smart-a8c92ecf-91f3-4c38-9dae-8925c056ca6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037528945 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.4037528945
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1377435732
Short name T890
Test name
Test status
Simulation time 13835364 ps
CPU time 0.88 seconds
Started Jul 09 05:05:00 PM PDT 24
Finished Jul 09 05:05:06 PM PDT 24
Peak memory 209160 kb
Host smart-9f02db7f-c5ae-4ac3-adb5-0997cb8ac41e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377435732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.1377435732
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.4259181162
Short name T916
Test name
Test status
Simulation time 181226770 ps
CPU time 1.27 seconds
Started Jul 09 05:05:03 PM PDT 24
Finished Jul 09 05:05:09 PM PDT 24
Peak memory 208488 kb
Host smart-65f62f89-c27b-4090-825e-b530c31c7c2c
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259181162 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.4259181162
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2121747844
Short name T906
Test name
Test status
Simulation time 300247318 ps
CPU time 3.31 seconds
Started Jul 09 05:04:58 PM PDT 24
Finished Jul 09 05:05:06 PM PDT 24
Peak memory 216900 kb
Host smart-edabab47-2961-4083-aa25-19bd209316a9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121747844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.2121747844
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3499516604
Short name T871
Test name
Test status
Simulation time 698976963 ps
CPU time 17.49 seconds
Started Jul 09 05:04:58 PM PDT 24
Finished Jul 09 05:05:21 PM PDT 24
Peak memory 209024 kb
Host smart-a9b0c0fe-dfbc-4a05-81db-186ce66f0c64
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499516604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.3499516604
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.4138724116
Short name T975
Test name
Test status
Simulation time 121538246 ps
CPU time 1.94 seconds
Started Jul 09 05:04:58 PM PDT 24
Finished Jul 09 05:05:05 PM PDT 24
Peak memory 210812 kb
Host smart-27f716b6-85ff-4f82-b727-87acd3f1771e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138724116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.4138724116
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3208132205
Short name T988
Test name
Test status
Simulation time 402147024 ps
CPU time 1.87 seconds
Started Jul 09 05:04:59 PM PDT 24
Finished Jul 09 05:05:06 PM PDT 24
Peak memory 220292 kb
Host smart-39a29210-0fa2-4bb9-971c-6c9c7cf68cd7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320813
2205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3208132205
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.938134184
Short name T961
Test name
Test status
Simulation time 55311981 ps
CPU time 1.39 seconds
Started Jul 09 05:04:57 PM PDT 24
Finished Jul 09 05:05:03 PM PDT 24
Peak memory 217228 kb
Host smart-5be18903-62c3-4b89-9ee4-f83b64d7ed29
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938134184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.938134184
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1294405965
Short name T942
Test name
Test status
Simulation time 148916359 ps
CPU time 1.42 seconds
Started Jul 09 05:04:56 PM PDT 24
Finished Jul 09 05:05:02 PM PDT 24
Peak memory 209292 kb
Host smart-aabbe7f6-fe94-4c8b-a240-c381d3536d32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294405965 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.1294405965
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1526708048
Short name T972
Test name
Test status
Simulation time 30780580 ps
CPU time 1.45 seconds
Started Jul 09 05:05:06 PM PDT 24
Finished Jul 09 05:05:12 PM PDT 24
Peak memory 209088 kb
Host smart-b44b3411-e014-4f82-a7c5-763251b9cf18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526708048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.1526708048
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.475829847
Short name T991
Test name
Test status
Simulation time 64903703 ps
CPU time 1.82 seconds
Started Jul 09 05:05:01 PM PDT 24
Finished Jul 09 05:05:08 PM PDT 24
Peak memory 217412 kb
Host smart-dc3aa4a1-66ac-40b5-8a0d-47caa3b578ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475829847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.475829847
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3795440899
Short name T868
Test name
Test status
Simulation time 31045623 ps
CPU time 1.18 seconds
Started Jul 09 05:05:04 PM PDT 24
Finished Jul 09 05:05:10 PM PDT 24
Peak memory 217376 kb
Host smart-8b7d9a01-1da8-4b1e-8b62-efa748bc0f78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795440899 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.3795440899
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3371882998
Short name T175
Test name
Test status
Simulation time 26762448 ps
CPU time 1.1 seconds
Started Jul 09 05:05:00 PM PDT 24
Finished Jul 09 05:05:06 PM PDT 24
Peak memory 209028 kb
Host smart-ace50e62-02bc-470d-83c5-086991966c82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371882998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.3371882998
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.281928936
Short name T131
Test name
Test status
Simulation time 127316797 ps
CPU time 1.31 seconds
Started Jul 09 05:05:00 PM PDT 24
Finished Jul 09 05:05:06 PM PDT 24
Peak memory 208368 kb
Host smart-6a15fa91-7b92-47a5-93ee-fc681c271467
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281928936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.lc_ctrl_jtag_alert_test.281928936
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.820055744
Short name T931
Test name
Test status
Simulation time 1095415783 ps
CPU time 15.82 seconds
Started Jul 09 05:05:01 PM PDT 24
Finished Jul 09 05:05:22 PM PDT 24
Peak memory 209168 kb
Host smart-a7ee18ce-b70a-49fe-94d5-f929cf8b5477
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820055744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.820055744
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.166545245
Short name T880
Test name
Test status
Simulation time 2657560351 ps
CPU time 9.31 seconds
Started Jul 09 05:05:06 PM PDT 24
Finished Jul 09 05:05:20 PM PDT 24
Peak memory 209044 kb
Host smart-1f13811e-a572-4b72-b3d5-e4f5ae51e34b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166545245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.166545245
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.4182522482
Short name T953
Test name
Test status
Simulation time 148469832 ps
CPU time 3.85 seconds
Started Jul 09 05:05:02 PM PDT 24
Finished Jul 09 05:05:11 PM PDT 24
Peak memory 210576 kb
Host smart-c678ad6d-71be-4fe0-aa31-3f23c777580e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182522482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.4182522482
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2041027895
Short name T955
Test name
Test status
Simulation time 192969539 ps
CPU time 2.05 seconds
Started Jul 09 05:05:03 PM PDT 24
Finished Jul 09 05:05:10 PM PDT 24
Peak memory 217588 kb
Host smart-1086f353-8d14-426c-8f21-15923718d8eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204102
7895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2041027895
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.908045418
Short name T925
Test name
Test status
Simulation time 665703385 ps
CPU time 1.21 seconds
Started Jul 09 05:05:00 PM PDT 24
Finished Jul 09 05:05:06 PM PDT 24
Peak memory 208956 kb
Host smart-261f2cbc-2f14-4f2c-898b-52113af3a104
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908045418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.908045418
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1945203334
Short name T985
Test name
Test status
Simulation time 166511476 ps
CPU time 1.99 seconds
Started Jul 09 05:05:01 PM PDT 24
Finished Jul 09 05:05:08 PM PDT 24
Peak memory 211000 kb
Host smart-b626f13c-3f78-4a6c-8681-6af33ec20b3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945203334 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.1945203334
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1949036153
Short name T934
Test name
Test status
Simulation time 20032919 ps
CPU time 1.36 seconds
Started Jul 09 05:05:03 PM PDT 24
Finished Jul 09 05:05:09 PM PDT 24
Peak memory 209360 kb
Host smart-9df6c4b7-650f-47e9-b16a-10c36d288373
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949036153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.1949036153
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1658554117
Short name T866
Test name
Test status
Simulation time 1338079187 ps
CPU time 4.91 seconds
Started Jul 09 05:05:03 PM PDT 24
Finished Jul 09 05:05:13 PM PDT 24
Peak memory 217328 kb
Host smart-e91e31e4-dcdd-45ef-b404-e4410dee8acc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658554117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.1658554117
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.580736677
Short name T903
Test name
Test status
Simulation time 26388649 ps
CPU time 1.23 seconds
Started Jul 09 05:05:08 PM PDT 24
Finished Jul 09 05:05:13 PM PDT 24
Peak memory 218480 kb
Host smart-32d2fb5c-e1c7-4bc7-a08e-90e14e353f35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580736677 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.580736677
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2799490175
Short name T936
Test name
Test status
Simulation time 28077377 ps
CPU time 0.9 seconds
Started Jul 09 05:05:05 PM PDT 24
Finished Jul 09 05:05:10 PM PDT 24
Peak memory 208748 kb
Host smart-875ac32f-6987-49f2-bf7f-21deb65a5ae9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799490175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.2799490175
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2916323378
Short name T899
Test name
Test status
Simulation time 307780336 ps
CPU time 0.99 seconds
Started Jul 09 05:05:03 PM PDT 24
Finished Jul 09 05:05:09 PM PDT 24
Peak memory 208952 kb
Host smart-e0c47585-f9b8-42f6-9aed-5095e5a347da
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916323378 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.2916323378
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2418502109
Short name T933
Test name
Test status
Simulation time 4651315808 ps
CPU time 4.73 seconds
Started Jul 09 05:05:04 PM PDT 24
Finished Jul 09 05:05:13 PM PDT 24
Peak memory 209120 kb
Host smart-30d8b507-d1f9-48fe-8f26-4a79dd9649cc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418502109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.2418502109
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.4034078978
Short name T926
Test name
Test status
Simulation time 698795831 ps
CPU time 9.55 seconds
Started Jul 09 05:05:00 PM PDT 24
Finished Jul 09 05:05:15 PM PDT 24
Peak memory 208752 kb
Host smart-402f4fc9-5633-4be8-87fa-d53e14bf7b5c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034078978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.4034078978
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1865811471
Short name T914
Test name
Test status
Simulation time 83948828 ps
CPU time 1.66 seconds
Started Jul 09 05:05:01 PM PDT 24
Finished Jul 09 05:05:08 PM PDT 24
Peak memory 210832 kb
Host smart-598b2418-daf2-4578-a03b-1529579df0f8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865811471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.1865811471
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1810940052
Short name T897
Test name
Test status
Simulation time 82361535 ps
CPU time 2.22 seconds
Started Jul 09 05:05:04 PM PDT 24
Finished Jul 09 05:05:11 PM PDT 24
Peak memory 218548 kb
Host smart-3fa7a299-3c39-4e7a-91db-4fc3c332df4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181094
0052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1810940052
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1530979626
Short name T968
Test name
Test status
Simulation time 53467456 ps
CPU time 2.01 seconds
Started Jul 09 05:05:00 PM PDT 24
Finished Jul 09 05:05:07 PM PDT 24
Peak memory 209100 kb
Host smart-50297d20-6f8d-4ac9-8674-5fbb4e8af9f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530979626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.1530979626
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1490570653
Short name T891
Test name
Test status
Simulation time 61216527 ps
CPU time 2.03 seconds
Started Jul 09 05:05:00 PM PDT 24
Finished Jul 09 05:05:07 PM PDT 24
Peak memory 209152 kb
Host smart-38e60eab-1097-413b-8a50-9414e1689814
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490570653 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.1490570653
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.4163613069
Short name T989
Test name
Test status
Simulation time 190999309 ps
CPU time 1.07 seconds
Started Jul 09 05:05:04 PM PDT 24
Finished Jul 09 05:05:10 PM PDT 24
Peak memory 209064 kb
Host smart-6ee25038-46e6-48fb-b42a-57dbb6cfed36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163613069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.4163613069
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.4148613263
Short name T873
Test name
Test status
Simulation time 45536358 ps
CPU time 1.62 seconds
Started Jul 09 05:05:03 PM PDT 24
Finished Jul 09 05:05:10 PM PDT 24
Peak memory 217464 kb
Host smart-f79b575f-c9e6-4c66-9cd9-50278ad41f8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148613263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.4148613263
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.2296790380
Short name T901
Test name
Test status
Simulation time 35129911 ps
CPU time 2 seconds
Started Jul 09 05:05:07 PM PDT 24
Finished Jul 09 05:05:13 PM PDT 24
Peak memory 223232 kb
Host smart-bcea5e09-eb89-4adb-b15b-cd027da8b175
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296790380 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.2296790380
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2027891793
Short name T875
Test name
Test status
Simulation time 35274060 ps
CPU time 0.95 seconds
Started Jul 09 05:05:09 PM PDT 24
Finished Jul 09 05:05:13 PM PDT 24
Peak memory 209132 kb
Host smart-adbce61d-45f6-4b8e-9b02-1ad879ed96e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027891793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.2027891793
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.472096931
Short name T930
Test name
Test status
Simulation time 100098679 ps
CPU time 1.2 seconds
Started Jul 09 05:05:06 PM PDT 24
Finished Jul 09 05:05:11 PM PDT 24
Peak memory 209104 kb
Host smart-8a7b4ce4-d49b-48cc-ab37-ef3fd47412f0
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472096931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.lc_ctrl_jtag_alert_test.472096931
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.635248368
Short name T128
Test name
Test status
Simulation time 16225753004 ps
CPU time 9.27 seconds
Started Jul 09 05:05:06 PM PDT 24
Finished Jul 09 05:05:19 PM PDT 24
Peak memory 209008 kb
Host smart-9f47ce5b-abe3-481e-acb9-599797fc925b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635248368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.635248368
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1100616559
Short name T984
Test name
Test status
Simulation time 3714697971 ps
CPU time 22.53 seconds
Started Jul 09 05:05:08 PM PDT 24
Finished Jul 09 05:05:34 PM PDT 24
Peak memory 209220 kb
Host smart-bab49206-7381-4de8-a360-60f00c359b45
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100616559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.1100616559
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3143399981
Short name T878
Test name
Test status
Simulation time 304324741 ps
CPU time 2.31 seconds
Started Jul 09 05:05:08 PM PDT 24
Finished Jul 09 05:05:14 PM PDT 24
Peak memory 217284 kb
Host smart-bc74e498-91bb-4006-854f-7280ca95d0b0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143399981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.3143399981
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1981448650
Short name T967
Test name
Test status
Simulation time 541266725 ps
CPU time 2.49 seconds
Started Jul 09 05:05:07 PM PDT 24
Finished Jul 09 05:05:13 PM PDT 24
Peak memory 223488 kb
Host smart-2137d6f9-7129-4664-9dd1-405e08c9f2ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198144
8650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1981448650
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.17732509
Short name T979
Test name
Test status
Simulation time 39826760 ps
CPU time 1.11 seconds
Started Jul 09 05:05:08 PM PDT 24
Finished Jul 09 05:05:13 PM PDT 24
Peak memory 209112 kb
Host smart-dde9a471-38b0-4d8d-be91-9d2dc079ee53
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17732509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test
+UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 8.lc_ctrl_jtag_csr_rw.17732509
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3445800466
Short name T952
Test name
Test status
Simulation time 56830258 ps
CPU time 1.21 seconds
Started Jul 09 05:05:09 PM PDT 24
Finished Jul 09 05:05:13 PM PDT 24
Peak memory 209180 kb
Host smart-c428090e-f42c-4cdf-b281-ceb35457ae5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445800466 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.3445800466
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.328276735
Short name T993
Test name
Test status
Simulation time 81144043 ps
CPU time 1.3 seconds
Started Jul 09 05:05:09 PM PDT 24
Finished Jul 09 05:05:13 PM PDT 24
Peak memory 211164 kb
Host smart-4a2dad24-4948-47f4-8e23-58784d365e04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328276735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
same_csr_outstanding.328276735
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3922932086
Short name T898
Test name
Test status
Simulation time 97471514 ps
CPU time 1.85 seconds
Started Jul 09 05:05:09 PM PDT 24
Finished Jul 09 05:05:14 PM PDT 24
Peak memory 217416 kb
Host smart-675b9c9a-f2f1-4f06-8c91-3a48c4a0733c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922932086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.3922932086
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3876548243
Short name T116
Test name
Test status
Simulation time 869864192 ps
CPU time 2.85 seconds
Started Jul 09 05:05:05 PM PDT 24
Finished Jul 09 05:05:13 PM PDT 24
Peak memory 217324 kb
Host smart-a6cd7c21-739a-4d15-8338-3df65d5efd56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876548243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.3876548243
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2115542796
Short name T980
Test name
Test status
Simulation time 24271301 ps
CPU time 1.57 seconds
Started Jul 09 05:05:09 PM PDT 24
Finished Jul 09 05:05:15 PM PDT 24
Peak memory 219248 kb
Host smart-c122f8f7-fea4-4365-9e39-8a3d2192bcca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115542796 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.2115542796
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.397169192
Short name T170
Test name
Test status
Simulation time 20252056 ps
CPU time 1.2 seconds
Started Jul 09 05:05:06 PM PDT 24
Finished Jul 09 05:05:11 PM PDT 24
Peak memory 209148 kb
Host smart-835bd765-5257-4a31-8590-3527e2df7688
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397169192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.397169192
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1457710268
Short name T892
Test name
Test status
Simulation time 73227761 ps
CPU time 0.95 seconds
Started Jul 09 05:05:10 PM PDT 24
Finished Jul 09 05:05:14 PM PDT 24
Peak memory 209384 kb
Host smart-2fca2217-db77-44f1-8e91-d02ce82dc1e8
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457710268 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.1457710268
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.415886097
Short name T885
Test name
Test status
Simulation time 3457340724 ps
CPU time 21.05 seconds
Started Jul 09 05:05:10 PM PDT 24
Finished Jul 09 05:05:34 PM PDT 24
Peak memory 217568 kb
Host smart-74e7ab0a-abc6-4dd8-8c15-f795ed94b3fb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415886097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.415886097
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3976280945
Short name T970
Test name
Test status
Simulation time 3811212659 ps
CPU time 9.1 seconds
Started Jul 09 05:05:10 PM PDT 24
Finished Jul 09 05:05:22 PM PDT 24
Peak memory 209528 kb
Host smart-578a5999-1750-4838-b92d-c296b0ae78c7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976280945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.3976280945
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3243369701
Short name T130
Test name
Test status
Simulation time 468193568 ps
CPU time 3.57 seconds
Started Jul 09 05:05:06 PM PDT 24
Finished Jul 09 05:05:14 PM PDT 24
Peak memory 217340 kb
Host smart-7d323dc8-eec2-4049-93b2-0715c8f999cc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243369701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.3243369701
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.437637862
Short name T966
Test name
Test status
Simulation time 286140754 ps
CPU time 6.9 seconds
Started Jul 09 05:05:07 PM PDT 24
Finished Jul 09 05:05:18 PM PDT 24
Peak memory 217792 kb
Host smart-c5a9e57f-b0e5-4439-9066-e60e2ff3d714
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437637
862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.437637862
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3862929683
Short name T893
Test name
Test status
Simulation time 680363773 ps
CPU time 1.3 seconds
Started Jul 09 05:05:07 PM PDT 24
Finished Jul 09 05:05:12 PM PDT 24
Peak memory 209016 kb
Host smart-52fe1cbf-3e94-4d93-939f-3b82a9f332cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862929683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.3862929683
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3103937163
Short name T179
Test name
Test status
Simulation time 25759285 ps
CPU time 1.19 seconds
Started Jul 09 05:05:05 PM PDT 24
Finished Jul 09 05:05:11 PM PDT 24
Peak memory 209236 kb
Host smart-d7b96f27-272e-4a13-b9b5-6f7b8d9d1980
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103937163 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.3103937163
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3595855224
Short name T874
Test name
Test status
Simulation time 56155251 ps
CPU time 1.32 seconds
Started Jul 09 05:05:08 PM PDT 24
Finished Jul 09 05:05:13 PM PDT 24
Peak memory 211296 kb
Host smart-c352dc22-444a-42fd-bf0f-f7c898fb92d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595855224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.3595855224
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1265566920
Short name T118
Test name
Test status
Simulation time 92915673 ps
CPU time 3.86 seconds
Started Jul 09 05:05:04 PM PDT 24
Finished Jul 09 05:05:13 PM PDT 24
Peak memory 217328 kb
Host smart-1f9289e3-5dbd-4635-b140-be201db30f7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265566920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.1265566920
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.891886812
Short name T329
Test name
Test status
Simulation time 66165885 ps
CPU time 1.06 seconds
Started Jul 09 05:07:18 PM PDT 24
Finished Jul 09 05:07:20 PM PDT 24
Peak memory 208360 kb
Host smart-d68a83ab-2cd3-4ad3-9335-80f39b6272a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891886812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.891886812
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.1363718449
Short name T208
Test name
Test status
Simulation time 13481205 ps
CPU time 0.84 seconds
Started Jul 09 05:07:11 PM PDT 24
Finished Jul 09 05:07:12 PM PDT 24
Peak memory 208148 kb
Host smart-44fbb5e9-7d55-4119-9c22-c92b966272ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363718449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.1363718449
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.3797246460
Short name T314
Test name
Test status
Simulation time 969221572 ps
CPU time 9.29 seconds
Started Jul 09 05:07:08 PM PDT 24
Finished Jul 09 05:07:18 PM PDT 24
Peak memory 225536 kb
Host smart-30c0ad18-14ac-4577-a127-10b8279d5395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797246460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.3797246460
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.3073815311
Short name T745
Test name
Test status
Simulation time 931390016 ps
CPU time 2.86 seconds
Started Jul 09 05:07:14 PM PDT 24
Finished Jul 09 05:07:18 PM PDT 24
Peak memory 216528 kb
Host smart-1c1d6025-2a5b-42af-9d4e-cb7953245b8f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073815311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.3073815311
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.4107627582
Short name T658
Test name
Test status
Simulation time 23412933505 ps
CPU time 54.89 seconds
Started Jul 09 05:07:13 PM PDT 24
Finished Jul 09 05:08:09 PM PDT 24
Peak memory 218296 kb
Host smart-22a70376-195f-4d2e-acc7-2de2412fb94d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107627582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.4107627582
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.1903690061
Short name T420
Test name
Test status
Simulation time 3294569050 ps
CPU time 13.25 seconds
Started Jul 09 05:07:13 PM PDT 24
Finished Jul 09 05:07:27 PM PDT 24
Peak memory 217200 kb
Host smart-969731d7-4ca0-4275-a93b-e6f0a8902025
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903690061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.1
903690061
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.3516361701
Short name T249
Test name
Test status
Simulation time 993635205 ps
CPU time 7.27 seconds
Started Jul 09 05:07:14 PM PDT 24
Finished Jul 09 05:07:22 PM PDT 24
Peak memory 217660 kb
Host smart-57fde2d2-9fed-4958-95d6-1ac85c7e247d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516361701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.3516361701
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.661423263
Short name T61
Test name
Test status
Simulation time 6955710244 ps
CPU time 16.65 seconds
Started Jul 09 05:07:13 PM PDT 24
Finished Jul 09 05:07:31 PM PDT 24
Peak memory 217052 kb
Host smart-2190b18f-1caf-4b86-b902-bc5239dbd5ac
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661423263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_regwen_during_op.661423263
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.835354259
Short name T65
Test name
Test status
Simulation time 583181072 ps
CPU time 3.02 seconds
Started Jul 09 05:07:11 PM PDT 24
Finished Jul 09 05:07:15 PM PDT 24
Peak memory 216996 kb
Host smart-8f0d4d05-1416-4cb9-9339-f69e1a155666
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835354259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.835354259
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.3047538357
Short name T312
Test name
Test status
Simulation time 6130164986 ps
CPU time 53.99 seconds
Started Jul 09 05:07:09 PM PDT 24
Finished Jul 09 05:08:03 PM PDT 24
Peak memory 277644 kb
Host smart-51ffe041-7786-4c54-86d1-0945a3e5027b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047538357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.3047538357
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.866509662
Short name T197
Test name
Test status
Simulation time 6229874933 ps
CPU time 16.52 seconds
Started Jul 09 05:07:09 PM PDT 24
Finished Jul 09 05:07:26 PM PDT 24
Peak memory 250304 kb
Host smart-fa08e130-5523-4e7d-bb45-10c2da223260
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866509662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_state_post_trans.866509662
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.1655643482
Short name T549
Test name
Test status
Simulation time 395627956 ps
CPU time 4.19 seconds
Started Jul 09 05:07:08 PM PDT 24
Finished Jul 09 05:07:13 PM PDT 24
Peak memory 217624 kb
Host smart-ecba0371-2129-411f-ba2e-b133a082fb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655643482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.1655643482
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.2936791294
Short name T751
Test name
Test status
Simulation time 638764675 ps
CPU time 17.86 seconds
Started Jul 09 05:07:07 PM PDT 24
Finished Jul 09 05:07:25 PM PDT 24
Peak memory 217152 kb
Host smart-0c3ce3ee-69b2-4b4c-91a2-183d6302988b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936791294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.2936791294
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.436813319
Short name T54
Test name
Test status
Simulation time 412419020 ps
CPU time 41.11 seconds
Started Jul 09 05:07:17 PM PDT 24
Finished Jul 09 05:07:59 PM PDT 24
Peak memory 283900 kb
Host smart-a04241a2-22e2-4fa6-9f23-c7ae3ada518f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436813319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.436813319
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.990603975
Short name T286
Test name
Test status
Simulation time 251285078 ps
CPU time 11.94 seconds
Started Jul 09 05:07:17 PM PDT 24
Finished Jul 09 05:07:29 PM PDT 24
Peak memory 225404 kb
Host smart-2611b8c0-09e0-4eb1-b6f6-8f64f35eba87
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990603975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.990603975
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.3657420411
Short name T517
Test name
Test status
Simulation time 518793275 ps
CPU time 18.82 seconds
Started Jul 09 05:07:16 PM PDT 24
Finished Jul 09 05:07:35 PM PDT 24
Peak memory 225380 kb
Host smart-d8a2619d-2ff3-4a34-a626-f1894dbb76df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657420411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.3657420411
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.1681706348
Short name T539
Test name
Test status
Simulation time 207583078 ps
CPU time 8.32 seconds
Started Jul 09 05:07:19 PM PDT 24
Finished Jul 09 05:07:28 PM PDT 24
Peak memory 217676 kb
Host smart-abe9fce4-1cee-4b7d-ac29-aed2fb9dc3f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681706348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.1
681706348
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.2717469191
Short name T393
Test name
Test status
Simulation time 923239045 ps
CPU time 10.9 seconds
Started Jul 09 05:07:06 PM PDT 24
Finished Jul 09 05:07:18 PM PDT 24
Peak memory 225512 kb
Host smart-b0fb80b7-3637-4978-a04b-5af2053c4890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717469191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.2717469191
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.785980871
Short name T64
Test name
Test status
Simulation time 217131545 ps
CPU time 3.69 seconds
Started Jul 09 05:07:08 PM PDT 24
Finished Jul 09 05:07:13 PM PDT 24
Peak memory 217144 kb
Host smart-4b040c42-2ec8-4584-99d2-0456f784ad5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785980871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.785980871
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.3111728833
Short name T471
Test name
Test status
Simulation time 141219228 ps
CPU time 20.46 seconds
Started Jul 09 05:07:09 PM PDT 24
Finished Jul 09 05:07:30 PM PDT 24
Peak memory 250384 kb
Host smart-60cbe3cd-d704-499b-b382-a72e138d40bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111728833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.3111728833
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.926269631
Short name T627
Test name
Test status
Simulation time 360974057 ps
CPU time 8.75 seconds
Started Jul 09 05:07:08 PM PDT 24
Finished Jul 09 05:07:17 PM PDT 24
Peak memory 250340 kb
Host smart-76f1a274-4c15-4096-a63c-79f0677383c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926269631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.926269631
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.1872443423
Short name T620
Test name
Test status
Simulation time 3559670393 ps
CPU time 60.68 seconds
Started Jul 09 05:07:18 PM PDT 24
Finished Jul 09 05:08:19 PM PDT 24
Peak memory 258640 kb
Host smart-26931fee-4d14-4058-87ff-d4b9ae02d26b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872443423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.1872443423
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.3413119490
Short name T690
Test name
Test status
Simulation time 19152624 ps
CPU time 0.97 seconds
Started Jul 09 05:07:08 PM PDT 24
Finished Jul 09 05:07:10 PM PDT 24
Peak memory 211304 kb
Host smart-39ada883-1c52-4caf-95f3-3557538e8fcf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413119490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.3413119490
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.3137426813
Short name T594
Test name
Test status
Simulation time 44610829 ps
CPU time 0.92 seconds
Started Jul 09 05:07:24 PM PDT 24
Finished Jul 09 05:07:26 PM PDT 24
Peak memory 208368 kb
Host smart-8fea2f7a-4f5c-4ab7-a856-96fd4c1577d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137426813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.3137426813
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.1404718809
Short name T573
Test name
Test status
Simulation time 295043893 ps
CPU time 15.04 seconds
Started Jul 09 05:07:17 PM PDT 24
Finished Jul 09 05:07:33 PM PDT 24
Peak memory 217588 kb
Host smart-eb9fed06-6555-41e6-a437-f292aa1b8b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404718809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.1404718809
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.1105122841
Short name T771
Test name
Test status
Simulation time 147643765 ps
CPU time 1.46 seconds
Started Jul 09 05:07:20 PM PDT 24
Finished Jul 09 05:07:22 PM PDT 24
Peak memory 217012 kb
Host smart-d8d7f29f-ec2c-4a7e-83a2-911361bfc540
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105122841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.1105122841
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.710695773
Short name T809
Test name
Test status
Simulation time 3146232924 ps
CPU time 24.82 seconds
Started Jul 09 05:07:22 PM PDT 24
Finished Jul 09 05:07:48 PM PDT 24
Peak memory 218224 kb
Host smart-135b62c3-9934-456f-9e32-3dbc8fd346b0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710695773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_err
ors.710695773
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.2362217580
Short name T543
Test name
Test status
Simulation time 1420543934 ps
CPU time 7.66 seconds
Started Jul 09 05:07:21 PM PDT 24
Finished Jul 09 05:07:30 PM PDT 24
Peak memory 217108 kb
Host smart-e12682d6-2226-4e30-a80b-d91b4712d65a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362217580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.2
362217580
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.2975023376
Short name T472
Test name
Test status
Simulation time 1622726964 ps
CPU time 4.49 seconds
Started Jul 09 05:07:21 PM PDT 24
Finished Jul 09 05:07:27 PM PDT 24
Peak memory 222320 kb
Host smart-e6e1707f-5e36-4cf7-957b-77d8c3c68dce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975023376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.2975023376
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.4032229418
Short name T773
Test name
Test status
Simulation time 5360698854 ps
CPU time 17.04 seconds
Started Jul 09 05:07:23 PM PDT 24
Finished Jul 09 05:07:40 PM PDT 24
Peak memory 217136 kb
Host smart-aa3a1b45-1cfb-44b3-a751-a0e3ef6261f2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032229418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.4032229418
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.952634497
Short name T73
Test name
Test status
Simulation time 972012003 ps
CPU time 3.39 seconds
Started Jul 09 05:07:22 PM PDT 24
Finished Jul 09 05:07:26 PM PDT 24
Peak memory 216988 kb
Host smart-c5054fb7-dd5c-47bf-a411-9771a5141b5e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952634497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.952634497
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.134773387
Short name T506
Test name
Test status
Simulation time 4891864826 ps
CPU time 31.41 seconds
Started Jul 09 05:07:21 PM PDT 24
Finished Jul 09 05:07:54 PM PDT 24
Peak memory 250400 kb
Host smart-3bea94c8-4c34-4d54-b0c4-f4740ddf87de
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134773387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_state_failure.134773387
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.542976237
Short name T434
Test name
Test status
Simulation time 854221334 ps
CPU time 14.64 seconds
Started Jul 09 05:07:20 PM PDT 24
Finished Jul 09 05:07:35 PM PDT 24
Peak memory 225856 kb
Host smart-5651c980-18a4-4aab-8946-b7d07d6a1948
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542976237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_j
tag_state_post_trans.542976237
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.870498590
Short name T686
Test name
Test status
Simulation time 69106061 ps
CPU time 3.72 seconds
Started Jul 09 05:07:15 PM PDT 24
Finished Jul 09 05:07:20 PM PDT 24
Peak memory 221708 kb
Host smart-4dc3d30e-8bfd-4d4b-8f12-5a3c0bc3f492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870498590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.870498590
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.3595032917
Short name T359
Test name
Test status
Simulation time 1774507947 ps
CPU time 8.88 seconds
Started Jul 09 05:07:18 PM PDT 24
Finished Jul 09 05:07:27 PM PDT 24
Peak memory 214000 kb
Host smart-c69d9e60-02a6-41b4-aa8f-9fe6480f0fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595032917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.3595032917
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.652585401
Short name T785
Test name
Test status
Simulation time 456490045 ps
CPU time 17.6 seconds
Started Jul 09 05:07:22 PM PDT 24
Finished Jul 09 05:07:40 PM PDT 24
Peak memory 217948 kb
Host smart-2ba7c5b4-2f7d-4630-872e-dc72ed8787f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652585401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.652585401
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.364687014
Short name T296
Test name
Test status
Simulation time 16580770830 ps
CPU time 22.06 seconds
Started Jul 09 05:07:20 PM PDT 24
Finished Jul 09 05:07:43 PM PDT 24
Peak memory 225428 kb
Host smart-2789c937-4b6b-4e39-824a-ad172e69506a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364687014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_dig
est.364687014
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.3037312787
Short name T56
Test name
Test status
Simulation time 3614956043 ps
CPU time 14.28 seconds
Started Jul 09 05:07:21 PM PDT 24
Finished Jul 09 05:07:37 PM PDT 24
Peak memory 217724 kb
Host smart-afafe37c-7d0f-4d14-a8ab-e3ba791f0faf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037312787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.3
037312787
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.1634473800
Short name T521
Test name
Test status
Simulation time 1832848967 ps
CPU time 10.18 seconds
Started Jul 09 05:07:16 PM PDT 24
Finished Jul 09 05:07:28 PM PDT 24
Peak memory 225520 kb
Host smart-4c3d07f4-a560-428b-ac9f-747fa76bb225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634473800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.1634473800
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.125365313
Short name T264
Test name
Test status
Simulation time 31425753 ps
CPU time 1.96 seconds
Started Jul 09 05:07:16 PM PDT 24
Finished Jul 09 05:07:19 PM PDT 24
Peak memory 217080 kb
Host smart-fc7430b3-b781-432f-8969-c91fd2c0b3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125365313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.125365313
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.372738638
Short name T248
Test name
Test status
Simulation time 391087321 ps
CPU time 32.41 seconds
Started Jul 09 05:07:17 PM PDT 24
Finished Jul 09 05:07:50 PM PDT 24
Peak memory 250388 kb
Host smart-d98fab3a-b667-4697-875c-4909e1eaf4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372738638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.372738638
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.564767000
Short name T432
Test name
Test status
Simulation time 694015491 ps
CPU time 6.05 seconds
Started Jul 09 05:07:14 PM PDT 24
Finished Jul 09 05:07:21 PM PDT 24
Peak memory 250020 kb
Host smart-d40bdd23-7b00-4208-b582-e898a66831ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564767000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.564767000
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.916322642
Short name T500
Test name
Test status
Simulation time 9399776855 ps
CPU time 366.31 seconds
Started Jul 09 05:07:21 PM PDT 24
Finished Jul 09 05:13:29 PM PDT 24
Peak memory 280312 kb
Host smart-4cae03d6-7c8b-45fc-aecf-6ff567944356
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916322642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.916322642
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1106829764
Short name T628
Test name
Test status
Simulation time 37950040 ps
CPU time 1 seconds
Started Jul 09 05:07:19 PM PDT 24
Finished Jul 09 05:07:21 PM PDT 24
Peak memory 211352 kb
Host smart-3f6c89a6-911f-4093-991d-88f6bb3f2d4e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106829764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.1106829764
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.3706233555
Short name T277
Test name
Test status
Simulation time 86273490 ps
CPU time 1.07 seconds
Started Jul 09 05:08:20 PM PDT 24
Finished Jul 09 05:08:22 PM PDT 24
Peak memory 208468 kb
Host smart-8d87dab5-b27f-414b-9332-a99ba5cce038
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706233555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.3706233555
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.3024331949
Short name T499
Test name
Test status
Simulation time 240781879 ps
CPU time 8.25 seconds
Started Jul 09 05:08:20 PM PDT 24
Finished Jul 09 05:08:29 PM PDT 24
Peak memory 217628 kb
Host smart-46686dcb-5006-4717-bc5c-350c2bcd457a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024331949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.3024331949
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.3709424744
Short name T796
Test name
Test status
Simulation time 487664641 ps
CPU time 2.76 seconds
Started Jul 09 05:08:20 PM PDT 24
Finished Jul 09 05:08:24 PM PDT 24
Peak memory 217056 kb
Host smart-19e20665-d4e1-41cb-8d96-fc4065958738
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709424744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.3709424744
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.2220412094
Short name T469
Test name
Test status
Simulation time 1152596998 ps
CPU time 36.4 seconds
Started Jul 09 05:08:16 PM PDT 24
Finished Jul 09 05:08:52 PM PDT 24
Peak memory 217564 kb
Host smart-9e5fdcc0-8089-4a57-afe8-2332df8c8410
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220412094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.2220412094
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.3861760381
Short name T206
Test name
Test status
Simulation time 579508106 ps
CPU time 8.85 seconds
Started Jul 09 05:08:22 PM PDT 24
Finished Jul 09 05:08:31 PM PDT 24
Peak memory 217648 kb
Host smart-c8b9a5e0-4630-4e6b-8e0b-bfc1d354c770
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861760381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.3861760381
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.1073191901
Short name T844
Test name
Test status
Simulation time 11839626135 ps
CPU time 9.71 seconds
Started Jul 09 05:08:17 PM PDT 24
Finished Jul 09 05:08:27 PM PDT 24
Peak memory 217064 kb
Host smart-e057f79b-f20c-44cd-9db0-41f46c53d284
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073191901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.1073191901
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.1535880373
Short name T315
Test name
Test status
Simulation time 1932040185 ps
CPU time 20.22 seconds
Started Jul 09 05:08:16 PM PDT 24
Finished Jul 09 05:08:37 PM PDT 24
Peak memory 250324 kb
Host smart-b6f5b118-a7eb-404d-9ee1-ccc453c5c71f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535880373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.1535880373
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.1368190051
Short name T651
Test name
Test status
Simulation time 709038883 ps
CPU time 2.6 seconds
Started Jul 09 05:08:16 PM PDT 24
Finished Jul 09 05:08:19 PM PDT 24
Peak memory 221952 kb
Host smart-3d34a198-2ffd-40f7-84b8-d396eea7641a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368190051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.1368190051
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.2782054768
Short name T366
Test name
Test status
Simulation time 373244373 ps
CPU time 17.55 seconds
Started Jul 09 05:08:19 PM PDT 24
Finished Jul 09 05:08:37 PM PDT 24
Peak memory 218324 kb
Host smart-a86b3782-054b-413b-ab0d-c8d459dcd927
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782054768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.2782054768
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.3764538258
Short name T158
Test name
Test status
Simulation time 722914987 ps
CPU time 10.39 seconds
Started Jul 09 05:08:15 PM PDT 24
Finished Jul 09 05:08:25 PM PDT 24
Peak memory 225344 kb
Host smart-ffdbc6cd-0712-4a1c-a200-a74bd2a9b449
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764538258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.3764538258
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.2008612707
Short name T824
Test name
Test status
Simulation time 2033129801 ps
CPU time 9.9 seconds
Started Jul 09 05:08:19 PM PDT 24
Finished Jul 09 05:08:30 PM PDT 24
Peak memory 217592 kb
Host smart-0c68ac2c-189e-4737-87c7-2cbe01deb481
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008612707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
2008612707
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.3953223119
Short name T665
Test name
Test status
Simulation time 1155398438 ps
CPU time 10.91 seconds
Started Jul 09 05:08:23 PM PDT 24
Finished Jul 09 05:08:34 PM PDT 24
Peak memory 224620 kb
Host smart-894fd288-c12c-4acf-9e35-11f06bda4dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953223119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.3953223119
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.1309015707
Short name T593
Test name
Test status
Simulation time 30697122 ps
CPU time 2.01 seconds
Started Jul 09 05:08:10 PM PDT 24
Finished Jul 09 05:08:13 PM PDT 24
Peak memory 217152 kb
Host smart-f491df50-97f5-4583-be7a-72ededb69129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309015707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.1309015707
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.394518518
Short name T496
Test name
Test status
Simulation time 840051854 ps
CPU time 23.55 seconds
Started Jul 09 05:08:19 PM PDT 24
Finished Jul 09 05:08:43 PM PDT 24
Peak memory 250480 kb
Host smart-47387acc-eb9d-4ef1-9e79-26f4e0ba621e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394518518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.394518518
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.2336775422
Short name T421
Test name
Test status
Simulation time 308451633 ps
CPU time 6.34 seconds
Started Jul 09 05:08:14 PM PDT 24
Finished Jul 09 05:08:21 PM PDT 24
Peak memory 246140 kb
Host smart-bfadc8ba-67d9-4722-b476-eed349f83f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336775422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.2336775422
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.781637187
Short name T588
Test name
Test status
Simulation time 1674026546 ps
CPU time 50.11 seconds
Started Jul 09 05:08:24 PM PDT 24
Finished Jul 09 05:09:14 PM PDT 24
Peak memory 250372 kb
Host smart-78bd95d5-0858-4e78-beed-3cd14a334431
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781637187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.781637187
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.82360733
Short name T44
Test name
Test status
Simulation time 18167220578 ps
CPU time 365.53 seconds
Started Jul 09 05:08:14 PM PDT 24
Finished Jul 09 05:14:20 PM PDT 24
Peak memory 282660 kb
Host smart-79e3f874-5670-4137-8369-40459df1a03a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=82360733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.82360733
Directory /workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.735040119
Short name T537
Test name
Test status
Simulation time 28057831 ps
CPU time 0.94 seconds
Started Jul 09 05:08:13 PM PDT 24
Finished Jul 09 05:08:15 PM PDT 24
Peak memory 212264 kb
Host smart-859484c9-4fbb-407f-91fc-6405171ac56c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735040119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ct
rl_volatile_unlock_smoke.735040119
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.3659630503
Short name T494
Test name
Test status
Simulation time 14340204 ps
CPU time 1.04 seconds
Started Jul 09 05:08:23 PM PDT 24
Finished Jul 09 05:08:24 PM PDT 24
Peak memory 208400 kb
Host smart-76b6dc24-5275-4e85-915c-ce1f2f30d4b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659630503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.3659630503
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.2087271449
Short name T614
Test name
Test status
Simulation time 310082899 ps
CPU time 11.91 seconds
Started Jul 09 05:08:20 PM PDT 24
Finished Jul 09 05:08:33 PM PDT 24
Peak memory 225532 kb
Host smart-0dce0102-e2ae-47a8-8563-300a6ee62665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087271449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.2087271449
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.187297169
Short name T788
Test name
Test status
Simulation time 60790485 ps
CPU time 1.45 seconds
Started Jul 09 05:08:18 PM PDT 24
Finished Jul 09 05:08:20 PM PDT 24
Peak memory 216592 kb
Host smart-a71e12bb-5768-4b6c-abf3-ae16da62d4dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187297169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.187297169
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.3152271571
Short name T814
Test name
Test status
Simulation time 3342479998 ps
CPU time 68.8 seconds
Started Jul 09 05:08:19 PM PDT 24
Finished Jul 09 05:09:29 PM PDT 24
Peak memory 217748 kb
Host smart-d4830f4b-cf4b-400b-8817-c083a1db0157
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152271571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.3152271571
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.4070035651
Short name T477
Test name
Test status
Simulation time 686766180 ps
CPU time 6.01 seconds
Started Jul 09 05:08:22 PM PDT 24
Finished Jul 09 05:08:28 PM PDT 24
Peak memory 217648 kb
Host smart-b27a4a32-8720-4021-b2c9-26efd7f32ec4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070035651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.4070035651
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.1235432291
Short name T89
Test name
Test status
Simulation time 641707107 ps
CPU time 16.98 seconds
Started Jul 09 05:08:20 PM PDT 24
Finished Jul 09 05:08:38 PM PDT 24
Peak memory 216944 kb
Host smart-bbd6149e-5c21-44b0-9ac9-3cd6019a1e1f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235432291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.1235432291
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.1479508500
Short name T291
Test name
Test status
Simulation time 1627752548 ps
CPU time 55.83 seconds
Started Jul 09 05:08:19 PM PDT 24
Finished Jul 09 05:09:15 PM PDT 24
Peak memory 268668 kb
Host smart-40669d32-f599-4c67-9026-34f82b7355d8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479508500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.1479508500
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.400243765
Short name T196
Test name
Test status
Simulation time 2816951015 ps
CPU time 8.58 seconds
Started Jul 09 05:08:20 PM PDT 24
Finished Jul 09 05:08:29 PM PDT 24
Peak memory 217728 kb
Host smart-c595458c-b2af-4ce0-bf3b-cf7c852e97be
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400243765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_
jtag_state_post_trans.400243765
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.2394488620
Short name T654
Test name
Test status
Simulation time 29893855 ps
CPU time 1.73 seconds
Started Jul 09 05:08:23 PM PDT 24
Finished Jul 09 05:08:26 PM PDT 24
Peak memory 217616 kb
Host smart-1d6193e8-4a82-423b-bb4e-a6bbea7d6692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394488620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.2394488620
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.3846367925
Short name T230
Test name
Test status
Simulation time 351484430 ps
CPU time 11.02 seconds
Started Jul 09 05:08:24 PM PDT 24
Finished Jul 09 05:08:35 PM PDT 24
Peak memory 218316 kb
Host smart-acdf81f9-91b0-4414-86fd-d2f87330af40
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846367925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.3846367925
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.3476880346
Short name T333
Test name
Test status
Simulation time 1116499120 ps
CPU time 8.91 seconds
Started Jul 09 05:08:21 PM PDT 24
Finished Jul 09 05:08:30 PM PDT 24
Peak memory 225392 kb
Host smart-7ffe98d3-0a0d-4fac-97e0-2533e78407ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476880346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.3476880346
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.2817292344
Short name T340
Test name
Test status
Simulation time 760571202 ps
CPU time 13.45 seconds
Started Jul 09 05:08:19 PM PDT 24
Finished Jul 09 05:08:33 PM PDT 24
Peak memory 217688 kb
Host smart-32946223-b781-4ee3-9c5d-5e3e7cc78401
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817292344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
2817292344
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.195637131
Short name T390
Test name
Test status
Simulation time 1248534884 ps
CPU time 8.09 seconds
Started Jul 09 05:08:20 PM PDT 24
Finished Jul 09 05:08:28 PM PDT 24
Peak memory 225536 kb
Host smart-f7266fc3-3601-4786-b646-d3318fd41241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195637131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.195637131
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.988353094
Short name T459
Test name
Test status
Simulation time 32444487 ps
CPU time 2.74 seconds
Started Jul 09 05:08:22 PM PDT 24
Finished Jul 09 05:08:25 PM PDT 24
Peak memory 214140 kb
Host smart-83cc0c34-31ae-401f-9378-5218b712f64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988353094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.988353094
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.3841516876
Short name T446
Test name
Test status
Simulation time 932826534 ps
CPU time 22.91 seconds
Started Jul 09 05:08:22 PM PDT 24
Finished Jul 09 05:08:46 PM PDT 24
Peak memory 250408 kb
Host smart-1116995e-d9ab-4dac-996f-c174ba0643cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841516876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.3841516876
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.4026147452
Short name T576
Test name
Test status
Simulation time 78166079 ps
CPU time 3.35 seconds
Started Jul 09 05:08:20 PM PDT 24
Finished Jul 09 05:08:24 PM PDT 24
Peak memory 221800 kb
Host smart-0144998d-2885-4cd8-b647-bd07581308e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026147452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.4026147452
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.3883158805
Short name T676
Test name
Test status
Simulation time 34730448735 ps
CPU time 182.62 seconds
Started Jul 09 05:08:20 PM PDT 24
Finished Jul 09 05:11:23 PM PDT 24
Peak memory 280772 kb
Host smart-fb802c2c-23d0-4fd0-a021-c13b1c7fa60f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883158805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.3883158805
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.1724351509
Short name T656
Test name
Test status
Simulation time 14445614 ps
CPU time 0.85 seconds
Started Jul 09 05:08:20 PM PDT 24
Finished Jul 09 05:08:21 PM PDT 24
Peak memory 208236 kb
Host smart-765a67ef-bfa2-42a2-aa78-17029a723d41
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724351509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.1724351509
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.408369044
Short name T292
Test name
Test status
Simulation time 71577904 ps
CPU time 1.15 seconds
Started Jul 09 05:08:28 PM PDT 24
Finished Jul 09 05:08:30 PM PDT 24
Peak memory 208396 kb
Host smart-79620498-339d-41f3-86ad-abc72eebdfe1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408369044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.408369044
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.732063214
Short name T645
Test name
Test status
Simulation time 511473318 ps
CPU time 12.3 seconds
Started Jul 09 05:08:23 PM PDT 24
Finished Jul 09 05:08:36 PM PDT 24
Peak memory 225504 kb
Host smart-fb814e9d-b494-4554-805e-712f902f4d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732063214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.732063214
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.888702706
Short name T290
Test name
Test status
Simulation time 940626685 ps
CPU time 6.62 seconds
Started Jul 09 05:08:24 PM PDT 24
Finished Jul 09 05:08:31 PM PDT 24
Peak memory 217128 kb
Host smart-6288c5a3-13fa-46cd-be35-fe81b854a7d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888702706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.888702706
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.1763728541
Short name T577
Test name
Test status
Simulation time 5468115222 ps
CPU time 23.54 seconds
Started Jul 09 05:08:25 PM PDT 24
Finished Jul 09 05:08:49 PM PDT 24
Peak memory 218252 kb
Host smart-42cb758b-721a-47c6-8ca7-18fcdfbf5f65
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763728541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.1763728541
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.3001659078
Short name T339
Test name
Test status
Simulation time 50730807 ps
CPU time 2.43 seconds
Started Jul 09 05:08:23 PM PDT 24
Finished Jul 09 05:08:26 PM PDT 24
Peak memory 220808 kb
Host smart-077fb408-1e85-4e87-accf-231adfedc9b9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001659078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.3001659078
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.1194309473
Short name T310
Test name
Test status
Simulation time 2223748841 ps
CPU time 13.8 seconds
Started Jul 09 05:08:23 PM PDT 24
Finished Jul 09 05:08:37 PM PDT 24
Peak memory 217032 kb
Host smart-a9f84307-8ef3-4686-9be4-90ad50745b4f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194309473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.1194309473
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.2743238729
Short name T375
Test name
Test status
Simulation time 5129117502 ps
CPU time 41.59 seconds
Started Jul 09 05:08:22 PM PDT 24
Finished Jul 09 05:09:05 PM PDT 24
Peak memory 251984 kb
Host smart-14b62779-30e3-4e4e-85b2-3ebedc5e3563
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743238729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.2743238729
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.3881434007
Short name T307
Test name
Test status
Simulation time 404019516 ps
CPU time 19.18 seconds
Started Jul 09 05:08:24 PM PDT 24
Finished Jul 09 05:08:43 PM PDT 24
Peak memory 250388 kb
Host smart-2b2fb304-4fd7-4c84-ba11-f36813a70ebb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881434007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.3881434007
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.3312126478
Short name T696
Test name
Test status
Simulation time 54805951 ps
CPU time 2.04 seconds
Started Jul 09 05:08:23 PM PDT 24
Finished Jul 09 05:08:26 PM PDT 24
Peak memory 217744 kb
Host smart-2dbc5746-a304-4dfc-959d-1c6cb40be69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312126478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.3312126478
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.1770695799
Short name T730
Test name
Test status
Simulation time 819965770 ps
CPU time 16.18 seconds
Started Jul 09 05:08:26 PM PDT 24
Finished Jul 09 05:08:42 PM PDT 24
Peak memory 225360 kb
Host smart-b6cb664f-b0d4-4b7d-9829-4215fd12cb8f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770695799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.1770695799
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.2872198884
Short name T563
Test name
Test status
Simulation time 222634605 ps
CPU time 9.72 seconds
Started Jul 09 05:08:27 PM PDT 24
Finished Jul 09 05:08:37 PM PDT 24
Peak memory 217608 kb
Host smart-04e878e0-1ac3-43fc-b1ae-ca0598958083
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872198884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
2872198884
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.24517114
Short name T612
Test name
Test status
Simulation time 172131423 ps
CPU time 8.06 seconds
Started Jul 09 05:08:22 PM PDT 24
Finished Jul 09 05:08:30 PM PDT 24
Peak memory 224760 kb
Host smart-e19c4f1b-bf08-4aab-b6f5-cc2236a33af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24517114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.24517114
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.3100305245
Short name T611
Test name
Test status
Simulation time 589241778 ps
CPU time 3.29 seconds
Started Jul 09 05:08:25 PM PDT 24
Finished Jul 09 05:08:29 PM PDT 24
Peak memory 217032 kb
Host smart-d9b41e24-7f0f-44e1-bf93-8d20da188700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100305245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.3100305245
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.1714414230
Short name T300
Test name
Test status
Simulation time 444788589 ps
CPU time 25.76 seconds
Started Jul 09 05:08:22 PM PDT 24
Finished Jul 09 05:08:48 PM PDT 24
Peak memory 250416 kb
Host smart-8916099d-2376-4121-8ea7-265be11a6b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714414230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.1714414230
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.432276278
Short name T834
Test name
Test status
Simulation time 70397976 ps
CPU time 3.3 seconds
Started Jul 09 05:08:22 PM PDT 24
Finished Jul 09 05:08:26 PM PDT 24
Peak memory 222136 kb
Host smart-9fba7e91-acd6-4b19-81f3-f8fa096b9925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432276278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.432276278
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.2026250302
Short name T246
Test name
Test status
Simulation time 11777758577 ps
CPU time 30.52 seconds
Started Jul 09 05:08:27 PM PDT 24
Finished Jul 09 05:08:58 PM PDT 24
Peak memory 250444 kb
Host smart-b3386313-19f2-4f50-a963-4eef8ddff6c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026250302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.2026250302
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.2207191600
Short name T739
Test name
Test status
Simulation time 7048758672 ps
CPU time 126.76 seconds
Started Jul 09 05:08:29 PM PDT 24
Finished Jul 09 05:10:36 PM PDT 24
Peak memory 266976 kb
Host smart-ca90a3b4-b242-44d2-af1b-31b1d6e8639d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2207191600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all_with_rand_reset.2207191600
Directory /workspace/12.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.875542489
Short name T426
Test name
Test status
Simulation time 73201516 ps
CPU time 0.73 seconds
Started Jul 09 05:08:21 PM PDT 24
Finished Jul 09 05:08:22 PM PDT 24
Peak memory 206884 kb
Host smart-8e40002c-8eea-4ce3-89a0-1b3f67d17884
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875542489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ct
rl_volatile_unlock_smoke.875542489
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.2056411425
Short name T493
Test name
Test status
Simulation time 57283955 ps
CPU time 1 seconds
Started Jul 09 05:08:31 PM PDT 24
Finished Jul 09 05:08:33 PM PDT 24
Peak memory 208436 kb
Host smart-03aeeaa0-f163-4804-b791-920b6e104f1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056411425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.2056411425
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.561281389
Short name T660
Test name
Test status
Simulation time 1559785144 ps
CPU time 12.23 seconds
Started Jul 09 05:08:29 PM PDT 24
Finished Jul 09 05:08:41 PM PDT 24
Peak memory 217744 kb
Host smart-91100f72-ca86-49cc-bd9b-60eb80366702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561281389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.561281389
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.2279425833
Short name T655
Test name
Test status
Simulation time 123860132 ps
CPU time 2.01 seconds
Started Jul 09 05:08:30 PM PDT 24
Finished Jul 09 05:08:32 PM PDT 24
Peak memory 217076 kb
Host smart-fce102de-d224-4f8e-b449-ca80918841f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279425833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.2279425833
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.3379948237
Short name T639
Test name
Test status
Simulation time 8115488756 ps
CPU time 34.54 seconds
Started Jul 09 05:08:26 PM PDT 24
Finished Jul 09 05:09:01 PM PDT 24
Peak memory 218336 kb
Host smart-f69c5fdd-5096-4ca7-b206-eeb2fdcde96c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379948237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.3379948237
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.4128368416
Short name T585
Test name
Test status
Simulation time 7684829300 ps
CPU time 9.36 seconds
Started Jul 09 05:08:28 PM PDT 24
Finished Jul 09 05:08:38 PM PDT 24
Peak memory 217656 kb
Host smart-9d99563d-1257-4123-a8ed-99300672e53c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128368416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.4128368416
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.2631642247
Short name T194
Test name
Test status
Simulation time 244764273 ps
CPU time 8.12 seconds
Started Jul 09 05:08:27 PM PDT 24
Finished Jul 09 05:08:35 PM PDT 24
Peak memory 216932 kb
Host smart-44826185-d5e4-448d-8e02-0952b70837c9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631642247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.2631642247
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.767612665
Short name T649
Test name
Test status
Simulation time 6007824777 ps
CPU time 63.91 seconds
Started Jul 09 05:08:29 PM PDT 24
Finished Jul 09 05:09:33 PM PDT 24
Peak memory 266744 kb
Host smart-137dd043-27d3-408f-9abf-36d97003eaac
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767612665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_state_failure.767612665
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.2326059856
Short name T448
Test name
Test status
Simulation time 610795600 ps
CPU time 10.33 seconds
Started Jul 09 05:08:30 PM PDT 24
Finished Jul 09 05:08:41 PM PDT 24
Peak memory 250728 kb
Host smart-f6465325-cbbf-408a-897e-1e1095991849
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326059856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.2326059856
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.2429573403
Short name T269
Test name
Test status
Simulation time 72354772 ps
CPU time 3.69 seconds
Started Jul 09 05:08:28 PM PDT 24
Finished Jul 09 05:08:32 PM PDT 24
Peak memory 222132 kb
Host smart-eacd9cd3-5d72-4d23-b22d-4ae629831821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429573403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.2429573403
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.3184202431
Short name T304
Test name
Test status
Simulation time 2119463212 ps
CPU time 17.21 seconds
Started Jul 09 05:08:26 PM PDT 24
Finished Jul 09 05:08:44 PM PDT 24
Peak memory 225524 kb
Host smart-6992724b-9dda-41be-9181-ab77a0c6d8d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184202431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.3184202431
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.330981555
Short name T863
Test name
Test status
Simulation time 3639666722 ps
CPU time 10.42 seconds
Started Jul 09 05:08:26 PM PDT 24
Finished Jul 09 05:08:37 PM PDT 24
Peak memory 225468 kb
Host smart-67b085ad-91ac-4d5f-a952-c944e90cd002
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330981555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_di
gest.330981555
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.1762281589
Short name T838
Test name
Test status
Simulation time 874177108 ps
CPU time 10.49 seconds
Started Jul 09 05:08:27 PM PDT 24
Finished Jul 09 05:08:38 PM PDT 24
Peak memory 217712 kb
Host smart-169be8ed-af40-44bd-ad63-08940a337fdb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762281589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
1762281589
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.3701767188
Short name T829
Test name
Test status
Simulation time 1456991271 ps
CPU time 13.64 seconds
Started Jul 09 05:08:27 PM PDT 24
Finished Jul 09 05:08:41 PM PDT 24
Peak memory 217796 kb
Host smart-e525d41f-d0cb-4497-949c-9e0f4e603a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701767188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.3701767188
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.2395050281
Short name T243
Test name
Test status
Simulation time 2442027097 ps
CPU time 28.51 seconds
Started Jul 09 05:08:31 PM PDT 24
Finished Jul 09 05:09:00 PM PDT 24
Peak memory 250856 kb
Host smart-0a7af22b-fdf5-4671-9b51-6db04519c294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395050281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.2395050281
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.1253814637
Short name T337
Test name
Test status
Simulation time 72555591 ps
CPU time 7.83 seconds
Started Jul 09 05:08:27 PM PDT 24
Finished Jul 09 05:08:35 PM PDT 24
Peak memory 250476 kb
Host smart-1a63fc42-a7ff-4d71-bf5e-fec6a6501d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253814637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.1253814637
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.1834566336
Short name T568
Test name
Test status
Simulation time 11741159229 ps
CPU time 156.29 seconds
Started Jul 09 05:08:28 PM PDT 24
Finished Jul 09 05:11:05 PM PDT 24
Peak memory 275256 kb
Host smart-c568084f-7fb2-426f-814c-0b892b965644
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834566336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.1834566336
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.895647847
Short name T137
Test name
Test status
Simulation time 63264171269 ps
CPU time 436.78 seconds
Started Jul 09 05:08:31 PM PDT 24
Finished Jul 09 05:15:48 PM PDT 24
Peak memory 278480 kb
Host smart-af3a2feb-9924-4960-b177-2a7efee0cf91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=895647847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.895647847
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.995883336
Short name T803
Test name
Test status
Simulation time 45014220 ps
CPU time 0.8 seconds
Started Jul 09 05:08:31 PM PDT 24
Finished Jul 09 05:08:32 PM PDT 24
Peak memory 208636 kb
Host smart-0696f921-2dd8-49c7-8931-d33bfc122258
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995883336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ct
rl_volatile_unlock_smoke.995883336
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.3438519836
Short name T297
Test name
Test status
Simulation time 61056032 ps
CPU time 1.03 seconds
Started Jul 09 05:08:38 PM PDT 24
Finished Jul 09 05:08:39 PM PDT 24
Peak memory 208476 kb
Host smart-de70046b-d649-46a2-8373-492c4e8edc51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438519836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.3438519836
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.2831142848
Short name T659
Test name
Test status
Simulation time 662926527 ps
CPU time 12.9 seconds
Started Jul 09 05:08:29 PM PDT 24
Finished Jul 09 05:08:42 PM PDT 24
Peak memory 217684 kb
Host smart-e194798f-0bd8-4319-96b6-5637025ef396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831142848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.2831142848
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.3208347439
Short name T368
Test name
Test status
Simulation time 1016739548 ps
CPU time 6.57 seconds
Started Jul 09 05:08:30 PM PDT 24
Finished Jul 09 05:08:37 PM PDT 24
Peak memory 216688 kb
Host smart-78de1d6a-c00e-4213-b27a-aac3c26a5d8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208347439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.3208347439
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.347224048
Short name T245
Test name
Test status
Simulation time 12260386121 ps
CPU time 75.92 seconds
Started Jul 09 05:08:31 PM PDT 24
Finished Jul 09 05:09:47 PM PDT 24
Peak memory 218356 kb
Host smart-e219f97f-ae93-496d-a394-befaacaaa91c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347224048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_er
rors.347224048
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.908016380
Short name T733
Test name
Test status
Simulation time 482103204 ps
CPU time 4.54 seconds
Started Jul 09 05:08:30 PM PDT 24
Finished Jul 09 05:08:35 PM PDT 24
Peak memory 217532 kb
Host smart-a58547d3-d053-48a7-b07a-09249a91c52b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908016380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag
_prog_failure.908016380
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.3267698984
Short name T510
Test name
Test status
Simulation time 623644938 ps
CPU time 2.58 seconds
Started Jul 09 05:08:30 PM PDT 24
Finished Jul 09 05:08:33 PM PDT 24
Peak memory 216932 kb
Host smart-824f4848-6b84-4739-9c4f-bf2aea225710
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267698984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.3267698984
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.2593952597
Short name T441
Test name
Test status
Simulation time 5225717866 ps
CPU time 36.94 seconds
Started Jul 09 05:08:31 PM PDT 24
Finished Jul 09 05:09:09 PM PDT 24
Peak memory 267044 kb
Host smart-bf98dbfb-9174-43d9-af6c-2d881b947092
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593952597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.2593952597
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.1874117188
Short name T532
Test name
Test status
Simulation time 775186693 ps
CPU time 11.41 seconds
Started Jul 09 05:08:32 PM PDT 24
Finished Jul 09 05:08:44 PM PDT 24
Peak memory 250364 kb
Host smart-34a4c245-9781-4665-976d-860bb15ad5eb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874117188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.1874117188
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.2661577806
Short name T600
Test name
Test status
Simulation time 149540042 ps
CPU time 2.03 seconds
Started Jul 09 05:08:33 PM PDT 24
Finished Jul 09 05:08:36 PM PDT 24
Peak memory 217660 kb
Host smart-91dd01a1-b862-4eb1-b3a8-6c88f26a149b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661577806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.2661577806
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.483799401
Short name T484
Test name
Test status
Simulation time 3003501058 ps
CPU time 22.32 seconds
Started Jul 09 05:08:34 PM PDT 24
Finished Jul 09 05:08:57 PM PDT 24
Peak memory 218524 kb
Host smart-50dbfb74-3fd8-47b7-9f54-82de81fa9c03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483799401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_di
gest.483799401
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.1078896630
Short name T862
Test name
Test status
Simulation time 2311435968 ps
CPU time 18.08 seconds
Started Jul 09 05:08:36 PM PDT 24
Finished Jul 09 05:08:55 PM PDT 24
Peak memory 217680 kb
Host smart-748b9dc7-c8ef-469b-97ae-3f588964342e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078896630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
1078896630
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.1529103128
Short name T848
Test name
Test status
Simulation time 903845504 ps
CPU time 10.85 seconds
Started Jul 09 05:08:33 PM PDT 24
Finished Jul 09 05:08:44 PM PDT 24
Peak memory 217680 kb
Host smart-a1eafb1d-a27c-4df1-ae88-77ea98694b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529103128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.1529103128
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.3462314806
Short name T618
Test name
Test status
Simulation time 2152448929 ps
CPU time 6.93 seconds
Started Jul 09 05:08:28 PM PDT 24
Finished Jul 09 05:08:36 PM PDT 24
Peak memory 217168 kb
Host smart-6114216e-b4ae-49e7-99b7-15524b0d8d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462314806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.3462314806
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.3520441343
Short name T530
Test name
Test status
Simulation time 3467716508 ps
CPU time 20.17 seconds
Started Jul 09 05:08:32 PM PDT 24
Finished Jul 09 05:08:52 PM PDT 24
Peak memory 250476 kb
Host smart-5e647530-b634-4adb-b678-94dda0eadaf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520441343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.3520441343
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.1158689873
Short name T254
Test name
Test status
Simulation time 275638010 ps
CPU time 8.72 seconds
Started Jul 09 05:08:31 PM PDT 24
Finished Jul 09 05:08:41 PM PDT 24
Peak memory 250792 kb
Host smart-2cf01c4c-6da9-4294-a148-0bc4da094aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158689873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.1158689873
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.3579194607
Short name T550
Test name
Test status
Simulation time 2208498115 ps
CPU time 68.45 seconds
Started Jul 09 05:08:38 PM PDT 24
Finished Jul 09 05:09:47 PM PDT 24
Peak memory 269024 kb
Host smart-d38e634e-e601-44e9-a302-c334cda5bf5f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579194607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.3579194607
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.2698371983
Short name T214
Test name
Test status
Simulation time 20495496 ps
CPU time 1.04 seconds
Started Jul 09 05:08:31 PM PDT 24
Finished Jul 09 05:08:33 PM PDT 24
Peak memory 217240 kb
Host smart-2106fc05-939e-44d3-a4e7-74c5291b849b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698371983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.2698371983
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.3926327700
Short name T683
Test name
Test status
Simulation time 31203673 ps
CPU time 1.11 seconds
Started Jul 09 05:08:34 PM PDT 24
Finished Jul 09 05:08:36 PM PDT 24
Peak memory 208800 kb
Host smart-348a66fe-953a-4c79-8be7-847712665f0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926327700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.3926327700
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.3827434825
Short name T414
Test name
Test status
Simulation time 818461362 ps
CPU time 10.02 seconds
Started Jul 09 05:08:35 PM PDT 24
Finished Jul 09 05:08:45 PM PDT 24
Peak memory 225512 kb
Host smart-63c9869b-eb26-4823-9620-71e3d83a3d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827434825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.3827434825
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.1190483360
Short name T675
Test name
Test status
Simulation time 1404213738 ps
CPU time 8.5 seconds
Started Jul 09 05:08:35 PM PDT 24
Finished Jul 09 05:08:44 PM PDT 24
Peak memory 216672 kb
Host smart-149c8e7e-2ae4-42e6-90b7-9c55d1e99549
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190483360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.1190483360
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.819192670
Short name T854
Test name
Test status
Simulation time 1294473107 ps
CPU time 42.54 seconds
Started Jul 09 05:08:35 PM PDT 24
Finished Jul 09 05:09:18 PM PDT 24
Peak memory 218244 kb
Host smart-abc228fd-a2fe-4a07-a44e-d8068f513cd2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819192670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_er
rors.819192670
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.2201262598
Short name T454
Test name
Test status
Simulation time 302871195 ps
CPU time 9.25 seconds
Started Jul 09 05:08:34 PM PDT 24
Finished Jul 09 05:08:43 PM PDT 24
Peak memory 217612 kb
Host smart-e19324b6-2854-4c75-b41b-dd432a865f07
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201262598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.2201262598
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.1544932773
Short name T726
Test name
Test status
Simulation time 79928574 ps
CPU time 2.85 seconds
Started Jul 09 05:08:34 PM PDT 24
Finished Jul 09 05:08:37 PM PDT 24
Peak memory 217004 kb
Host smart-f2b4b3dd-a7ec-43ee-ba12-d9018fade95a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544932773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.1544932773
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.4151856812
Short name T216
Test name
Test status
Simulation time 1440364616 ps
CPU time 49.76 seconds
Started Jul 09 05:08:34 PM PDT 24
Finished Jul 09 05:09:25 PM PDT 24
Peak memory 266740 kb
Host smart-cceeb748-4e6b-4fc6-8031-2e45e5d032b8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151856812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.4151856812
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.1137085027
Short name T392
Test name
Test status
Simulation time 868280752 ps
CPU time 14.35 seconds
Started Jul 09 05:08:37 PM PDT 24
Finished Jul 09 05:08:52 PM PDT 24
Peak memory 250328 kb
Host smart-d0808da7-4455-4453-9e54-ecceef258972
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137085027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.1137085027
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.3384593859
Short name T460
Test name
Test status
Simulation time 308725150 ps
CPU time 3.46 seconds
Started Jul 09 05:08:36 PM PDT 24
Finished Jul 09 05:08:40 PM PDT 24
Peak memory 222356 kb
Host smart-4b0890ac-99f0-4bd5-9d28-4711b981aa0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384593859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.3384593859
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.2383374163
Short name T372
Test name
Test status
Simulation time 3097360100 ps
CPU time 16.21 seconds
Started Jul 09 05:08:37 PM PDT 24
Finished Jul 09 05:08:53 PM PDT 24
Peak memory 225488 kb
Host smart-a3ca2257-519c-4ddc-abad-907c1eef0e07
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383374163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.2383374163
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.3042339448
Short name T234
Test name
Test status
Simulation time 1448378349 ps
CPU time 9.35 seconds
Started Jul 09 05:08:36 PM PDT 24
Finished Jul 09 05:08:46 PM PDT 24
Peak memory 217596 kb
Host smart-817a4e9a-54bb-4826-a6d3-73b661c9aaa6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042339448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
3042339448
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.1061531750
Short name T570
Test name
Test status
Simulation time 793451606 ps
CPU time 9.17 seconds
Started Jul 09 05:08:35 PM PDT 24
Finished Jul 09 05:08:45 PM PDT 24
Peak memory 224704 kb
Host smart-b7db113f-cfe6-4929-ad76-2f99cd190220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061531750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.1061531750
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.1665080659
Short name T731
Test name
Test status
Simulation time 290443301 ps
CPU time 3.83 seconds
Started Jul 09 05:08:36 PM PDT 24
Finished Jul 09 05:08:41 PM PDT 24
Peak memory 217016 kb
Host smart-aabcbd2e-8b1c-461c-9e5d-593628f469cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665080659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.1665080659
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.4021284700
Short name T671
Test name
Test status
Simulation time 1263491553 ps
CPU time 17.81 seconds
Started Jul 09 05:08:36 PM PDT 24
Finished Jul 09 05:08:54 PM PDT 24
Peak memory 250368 kb
Host smart-0535cacb-9158-4135-ae91-5460350e0d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021284700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.4021284700
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.652811441
Short name T777
Test name
Test status
Simulation time 375779042 ps
CPU time 7.61 seconds
Started Jul 09 05:08:33 PM PDT 24
Finished Jul 09 05:08:41 PM PDT 24
Peak memory 250448 kb
Host smart-5f8f7b01-2be9-4a7e-9c6a-83527581e999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652811441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.652811441
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.2532009830
Short name T762
Test name
Test status
Simulation time 5925508483 ps
CPU time 89.2 seconds
Started Jul 09 05:08:34 PM PDT 24
Finished Jul 09 05:10:04 PM PDT 24
Peak memory 266860 kb
Host smart-f4ec3201-c53d-4cb5-aeb6-677b6dc1d4de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532009830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.2532009830
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.3142546295
Short name T858
Test name
Test status
Simulation time 11914933 ps
CPU time 0.82 seconds
Started Jul 09 05:08:33 PM PDT 24
Finished Jul 09 05:08:34 PM PDT 24
Peak memory 208540 kb
Host smart-ba7d4e0f-2545-49cd-a7e7-68f8130a0118
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142546295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.3142546295
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.89676746
Short name T93
Test name
Test status
Simulation time 11999190 ps
CPU time 0.95 seconds
Started Jul 09 05:08:42 PM PDT 24
Finished Jul 09 05:08:43 PM PDT 24
Peak memory 208372 kb
Host smart-7e615a54-8be2-4c8a-966b-5396f3a4c81a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89676746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.89676746
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.1540779268
Short name T282
Test name
Test status
Simulation time 457687422 ps
CPU time 12.21 seconds
Started Jul 09 05:08:41 PM PDT 24
Finished Jul 09 05:08:54 PM PDT 24
Peak memory 217660 kb
Host smart-c40ff286-356b-449b-8968-0225d9a37aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540779268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.1540779268
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.2097076726
Short name T7
Test name
Test status
Simulation time 740594594 ps
CPU time 7.31 seconds
Started Jul 09 05:08:38 PM PDT 24
Finished Jul 09 05:08:46 PM PDT 24
Peak memory 216684 kb
Host smart-23e10181-a51c-4bb4-802b-02bf5edf6b37
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097076726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.2097076726
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.2867475017
Short name T560
Test name
Test status
Simulation time 10405701272 ps
CPU time 73.78 seconds
Started Jul 09 05:08:40 PM PDT 24
Finished Jul 09 05:09:54 PM PDT 24
Peak memory 218336 kb
Host smart-f9c1a82a-09e0-41e6-9047-7e3d0d5f56d6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867475017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.2867475017
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.4230443318
Short name T643
Test name
Test status
Simulation time 1623059952 ps
CPU time 7.48 seconds
Started Jul 09 05:08:39 PM PDT 24
Finished Jul 09 05:08:47 PM PDT 24
Peak memory 217660 kb
Host smart-ff42db4d-3d6d-467f-83af-8dce6c9c4e47
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230443318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.4230443318
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.1985103606
Short name T840
Test name
Test status
Simulation time 457285193 ps
CPU time 4.11 seconds
Started Jul 09 05:08:40 PM PDT 24
Finished Jul 09 05:08:45 PM PDT 24
Peak memory 216980 kb
Host smart-b4ce17d6-6d2c-4e94-bc4c-c9e1055c92f1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985103606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.1985103606
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.1942167471
Short name T357
Test name
Test status
Simulation time 19709993560 ps
CPU time 44.4 seconds
Started Jul 09 05:08:40 PM PDT 24
Finished Jul 09 05:09:25 PM PDT 24
Peak memory 267900 kb
Host smart-c9542dea-bde7-4081-89e0-a3213752afed
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942167471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.1942167471
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.3744298753
Short name T240
Test name
Test status
Simulation time 4391967017 ps
CPU time 21.08 seconds
Started Jul 09 05:08:45 PM PDT 24
Finished Jul 09 05:09:07 PM PDT 24
Peak memory 250352 kb
Host smart-213de38b-bb78-4243-a8af-ed10a53aec43
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744298753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.3744298753
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.1938927008
Short name T523
Test name
Test status
Simulation time 228905040 ps
CPU time 2.88 seconds
Started Jul 09 05:08:39 PM PDT 24
Finished Jul 09 05:08:42 PM PDT 24
Peak memory 217656 kb
Host smart-426b251e-db63-408b-bca1-4fc7d2f99ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938927008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.1938927008
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.1316377188
Short name T754
Test name
Test status
Simulation time 2297938005 ps
CPU time 16.98 seconds
Started Jul 09 05:08:41 PM PDT 24
Finished Jul 09 05:08:59 PM PDT 24
Peak memory 219464 kb
Host smart-6cdc3b5f-a2a1-4309-8625-0c543e1d601a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316377188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.1316377188
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.1103029105
Short name T680
Test name
Test status
Simulation time 1192675971 ps
CPU time 13.25 seconds
Started Jul 09 05:08:44 PM PDT 24
Finished Jul 09 05:08:58 PM PDT 24
Peak memory 225432 kb
Host smart-a5203700-8b22-469e-9cb0-1a2f06685b7b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103029105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.1103029105
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.2873836946
Short name T700
Test name
Test status
Simulation time 1243317147 ps
CPU time 9.44 seconds
Started Jul 09 05:08:39 PM PDT 24
Finished Jul 09 05:08:49 PM PDT 24
Peak memory 225392 kb
Host smart-57cd33b6-5f28-4e90-9133-3465cfcec9f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873836946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
2873836946
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.492903645
Short name T34
Test name
Test status
Simulation time 181957599 ps
CPU time 8.96 seconds
Started Jul 09 05:08:39 PM PDT 24
Finished Jul 09 05:08:48 PM PDT 24
Peak memory 224844 kb
Host smart-fd40ba0f-7c29-4df6-a3de-a04ad1988c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492903645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.492903645
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.3108292862
Short name T386
Test name
Test status
Simulation time 42642530 ps
CPU time 2.05 seconds
Started Jul 09 05:08:41 PM PDT 24
Finished Jul 09 05:08:44 PM PDT 24
Peak memory 213396 kb
Host smart-1151043f-1659-4a8b-82f4-9b56968beecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108292862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.3108292862
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.2672867861
Short name T263
Test name
Test status
Simulation time 633119381 ps
CPU time 19.62 seconds
Started Jul 09 05:08:40 PM PDT 24
Finished Jul 09 05:09:01 PM PDT 24
Peak memory 250384 kb
Host smart-9a815c44-2425-46c2-9efb-24d7b3a494d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672867861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.2672867861
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.2708578282
Short name T480
Test name
Test status
Simulation time 72475771 ps
CPU time 7.3 seconds
Started Jul 09 05:08:43 PM PDT 24
Finished Jul 09 05:08:51 PM PDT 24
Peak memory 249972 kb
Host smart-fc90379c-5740-4d19-9bcb-a27c4679121c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708578282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.2708578282
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.3352848736
Short name T302
Test name
Test status
Simulation time 3839365183 ps
CPU time 66.59 seconds
Started Jul 09 05:08:44 PM PDT 24
Finished Jul 09 05:09:51 PM PDT 24
Peak memory 272036 kb
Host smart-ae977634-3f57-41b8-95c9-81cabe145fd3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352848736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.3352848736
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.1756206676
Short name T275
Test name
Test status
Simulation time 34597055 ps
CPU time 0.91 seconds
Started Jul 09 05:08:39 PM PDT 24
Finished Jul 09 05:08:41 PM PDT 24
Peak memory 211304 kb
Host smart-78b9d380-b947-486d-8750-b6559ff6ecab
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756206676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.1756206676
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.1509070432
Short name T474
Test name
Test status
Simulation time 376682310 ps
CPU time 16.87 seconds
Started Jul 09 05:08:42 PM PDT 24
Finished Jul 09 05:09:00 PM PDT 24
Peak memory 225508 kb
Host smart-75f38f01-c050-4313-97e1-c0f3ca82e4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509070432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.1509070432
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.1224383026
Short name T226
Test name
Test status
Simulation time 143544765 ps
CPU time 1.67 seconds
Started Jul 09 05:08:46 PM PDT 24
Finished Jul 09 05:08:49 PM PDT 24
Peak memory 217144 kb
Host smart-c80f8f3b-1d3f-4191-a484-ed39af6381c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224383026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.1224383026
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.2824923569
Short name T682
Test name
Test status
Simulation time 4492011073 ps
CPU time 78.42 seconds
Started Jul 09 05:08:42 PM PDT 24
Finished Jul 09 05:10:01 PM PDT 24
Peak memory 218284 kb
Host smart-5d6663b7-f848-4d90-a363-e2d84124e313
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824923569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.2824923569
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.2046049185
Short name T364
Test name
Test status
Simulation time 3846526572 ps
CPU time 3.88 seconds
Started Jul 09 05:08:43 PM PDT 24
Finished Jul 09 05:08:48 PM PDT 24
Peak memory 222864 kb
Host smart-ba874548-f3c8-47ac-8cdc-bd0cd18fff55
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046049185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.2046049185
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.571732196
Short name T547
Test name
Test status
Simulation time 290965497 ps
CPU time 2.84 seconds
Started Jul 09 05:08:41 PM PDT 24
Finished Jul 09 05:08:44 PM PDT 24
Peak memory 216980 kb
Host smart-66aadbdd-ef3b-497f-a4ac-7347c3a7d9c0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571732196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke.
571732196
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.3362018999
Short name T712
Test name
Test status
Simulation time 1588721680 ps
CPU time 39.92 seconds
Started Jul 09 05:08:44 PM PDT 24
Finished Jul 09 05:09:25 PM PDT 24
Peak memory 250340 kb
Host smart-7ebe305a-e49b-4d51-801e-29fe6e2515fe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362018999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.3362018999
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.198041949
Short name T805
Test name
Test status
Simulation time 3480469464 ps
CPU time 17.42 seconds
Started Jul 09 05:08:43 PM PDT 24
Finished Jul 09 05:09:01 PM PDT 24
Peak memory 250396 kb
Host smart-1f3069f7-4771-41b7-ad0e-19e94a28f3a4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198041949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_
jtag_state_post_trans.198041949
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.1121009184
Short name T609
Test name
Test status
Simulation time 159462577 ps
CPU time 2.63 seconds
Started Jul 09 05:08:42 PM PDT 24
Finished Jul 09 05:08:45 PM PDT 24
Peak memory 217728 kb
Host smart-bebc0375-9347-4244-b1ee-84007a4cb9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121009184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.1121009184
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.1681165814
Short name T804
Test name
Test status
Simulation time 158452311 ps
CPU time 7.15 seconds
Started Jul 09 05:08:46 PM PDT 24
Finished Jul 09 05:08:54 PM PDT 24
Peak memory 225444 kb
Host smart-807f1d2e-1c8a-47e6-9cfa-6a584ec83913
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681165814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.1681165814
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.3995590664
Short name T295
Test name
Test status
Simulation time 3428738644 ps
CPU time 6.56 seconds
Started Jul 09 05:08:46 PM PDT 24
Finished Jul 09 05:08:53 PM PDT 24
Peak memory 217716 kb
Host smart-9714542d-1926-4758-9b07-289d11e98df1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995590664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
3995590664
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.2075723939
Short name T381
Test name
Test status
Simulation time 331898275 ps
CPU time 8.53 seconds
Started Jul 09 05:08:42 PM PDT 24
Finished Jul 09 05:08:51 PM PDT 24
Peak memory 224904 kb
Host smart-0e86b949-9e52-4930-a942-54473c59ecad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075723939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.2075723939
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.804477393
Short name T772
Test name
Test status
Simulation time 97730063 ps
CPU time 3.58 seconds
Started Jul 09 05:08:43 PM PDT 24
Finished Jul 09 05:08:47 PM PDT 24
Peak memory 222184 kb
Host smart-e761c09a-5d2e-45c1-b935-376b88c1fcc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804477393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.804477393
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.2028596749
Short name T701
Test name
Test status
Simulation time 1044434726 ps
CPU time 22.8 seconds
Started Jul 09 05:08:45 PM PDT 24
Finished Jul 09 05:09:08 PM PDT 24
Peak memory 250792 kb
Host smart-e47c3a4e-ba61-468e-a2fc-5aef3a77074b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028596749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.2028596749
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.3121829623
Short name T476
Test name
Test status
Simulation time 62818500 ps
CPU time 9.2 seconds
Started Jul 09 05:08:45 PM PDT 24
Finished Jul 09 05:08:55 PM PDT 24
Peak memory 250432 kb
Host smart-ea3cbf82-cf9a-4648-87b0-91dfcd7554b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121829623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.3121829623
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.3323538296
Short name T184
Test name
Test status
Simulation time 4161314474 ps
CPU time 121.12 seconds
Started Jul 09 05:08:46 PM PDT 24
Finished Jul 09 05:10:48 PM PDT 24
Peak memory 250580 kb
Host smart-714db118-4beb-4ba5-8da1-69c815ea3f40
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323538296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.3323538296
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.3954999932
Short name T35
Test name
Test status
Simulation time 15318811 ps
CPU time 0.8 seconds
Started Jul 09 05:08:43 PM PDT 24
Finished Jul 09 05:08:44 PM PDT 24
Peak memory 208312 kb
Host smart-2713b07b-c515-4dd3-87be-258d927ccc55
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954999932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.3954999932
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.183004772
Short name T82
Test name
Test status
Simulation time 59137821 ps
CPU time 0.98 seconds
Started Jul 09 05:08:45 PM PDT 24
Finished Jul 09 05:08:47 PM PDT 24
Peak memory 208376 kb
Host smart-0038f1a8-f150-4ebf-aab2-e4193921ae3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183004772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.183004772
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.4226275809
Short name T575
Test name
Test status
Simulation time 778917033 ps
CPU time 16.53 seconds
Started Jul 09 05:08:46 PM PDT 24
Finished Jul 09 05:09:04 PM PDT 24
Peak memory 217596 kb
Host smart-c374faa2-3685-4528-a310-e17c4a1a0bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226275809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.4226275809
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.1125500170
Short name T345
Test name
Test status
Simulation time 204159256 ps
CPU time 5.01 seconds
Started Jul 09 05:08:46 PM PDT 24
Finished Jul 09 05:08:52 PM PDT 24
Peak memory 217076 kb
Host smart-8eeecacc-531a-454c-9b6c-a0de40c52626
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125500170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.1125500170
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.768251826
Short name T835
Test name
Test status
Simulation time 2081486637 ps
CPU time 58.72 seconds
Started Jul 09 05:08:44 PM PDT 24
Finished Jul 09 05:09:43 PM PDT 24
Peak memory 217572 kb
Host smart-4d591604-c6fa-4ce8-8cab-f942f9902a1d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768251826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_er
rors.768251826
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.569593065
Short name T770
Test name
Test status
Simulation time 935179137 ps
CPU time 24.44 seconds
Started Jul 09 05:08:46 PM PDT 24
Finished Jul 09 05:09:12 PM PDT 24
Peak memory 217624 kb
Host smart-cf894495-3aea-41b7-91e8-3be2d8ad1395
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569593065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag
_prog_failure.569593065
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.3424158998
Short name T574
Test name
Test status
Simulation time 266153731 ps
CPU time 4.74 seconds
Started Jul 09 05:08:47 PM PDT 24
Finished Jul 09 05:08:53 PM PDT 24
Peak memory 217004 kb
Host smart-b01cc179-fd8d-4577-9325-d49b68a11f01
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424158998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.3424158998
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.904155559
Short name T624
Test name
Test status
Simulation time 5710954384 ps
CPU time 60.17 seconds
Started Jul 09 05:08:46 PM PDT 24
Finished Jul 09 05:09:48 PM PDT 24
Peak memory 278636 kb
Host smart-9691279f-0b75-4506-a0a2-caaf4221a915
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904155559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_state_failure.904155559
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.3686528302
Short name T729
Test name
Test status
Simulation time 366952045 ps
CPU time 16.85 seconds
Started Jul 09 05:08:47 PM PDT 24
Finished Jul 09 05:09:04 PM PDT 24
Peak memory 250480 kb
Host smart-3534cf6d-c670-4024-9c57-407813cf96fe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686528302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.3686528302
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.125845325
Short name T316
Test name
Test status
Simulation time 920154212 ps
CPU time 2.93 seconds
Started Jul 09 05:08:47 PM PDT 24
Finished Jul 09 05:08:51 PM PDT 24
Peak memory 217688 kb
Host smart-2caa6c10-3be8-4dc6-8ec2-17feda303f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125845325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.125845325
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.2513311696
Short name T222
Test name
Test status
Simulation time 7394037080 ps
CPU time 16.71 seconds
Started Jul 09 05:08:46 PM PDT 24
Finished Jul 09 05:09:04 PM PDT 24
Peak memory 225672 kb
Host smart-e0ed9aac-b038-43fc-94d8-11d2a2c99e26
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513311696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.2513311696
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.3777988784
Short name T752
Test name
Test status
Simulation time 2655399157 ps
CPU time 17.31 seconds
Started Jul 09 05:08:51 PM PDT 24
Finished Jul 09 05:09:08 PM PDT 24
Peak memory 225392 kb
Host smart-83135568-97a1-42d5-9cbb-600e595d940c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777988784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.3777988784
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.2788804971
Short name T485
Test name
Test status
Simulation time 1129846706 ps
CPU time 7.63 seconds
Started Jul 09 05:08:47 PM PDT 24
Finished Jul 09 05:08:55 PM PDT 24
Peak memory 217668 kb
Host smart-7b8ab421-db0e-45cd-a131-3a974a0af679
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788804971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
2788804971
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.837415917
Short name T794
Test name
Test status
Simulation time 412702895 ps
CPU time 14.34 seconds
Started Jul 09 05:08:45 PM PDT 24
Finished Jul 09 05:09:01 PM PDT 24
Peak memory 224336 kb
Host smart-564303e7-2f52-4c36-8712-ce94ccb54d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837415917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.837415917
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.2038940429
Short name T74
Test name
Test status
Simulation time 489041766 ps
CPU time 2.8 seconds
Started Jul 09 05:08:45 PM PDT 24
Finished Jul 09 05:08:49 PM PDT 24
Peak memory 217112 kb
Host smart-b2fb80f6-fb14-4998-bde8-c13df105be90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038940429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.2038940429
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.1000648916
Short name T652
Test name
Test status
Simulation time 561186178 ps
CPU time 14.53 seconds
Started Jul 09 05:08:54 PM PDT 24
Finished Jul 09 05:09:09 PM PDT 24
Peak memory 250444 kb
Host smart-2d3bcd3c-652d-475e-8b55-0eb511315e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000648916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.1000648916
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.2280008709
Short name T205
Test name
Test status
Simulation time 216868829 ps
CPU time 3.95 seconds
Started Jul 09 05:08:51 PM PDT 24
Finished Jul 09 05:08:56 PM PDT 24
Peak memory 217600 kb
Host smart-348af68c-b021-4c6f-9469-40f1ee133b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280008709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.2280008709
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.3322635135
Short name T638
Test name
Test status
Simulation time 38526420499 ps
CPU time 634.85 seconds
Started Jul 09 05:08:51 PM PDT 24
Finished Jul 09 05:19:26 PM PDT 24
Peak memory 250408 kb
Host smart-976f6f5f-e917-4a5c-9682-53c9f9e6a074
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322635135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.3322635135
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.49032567
Short name T83
Test name
Test status
Simulation time 14395854936 ps
CPU time 382.31 seconds
Started Jul 09 05:08:46 PM PDT 24
Finished Jul 09 05:15:09 PM PDT 24
Peak memory 267084 kb
Host smart-a1378ce8-e43b-45c6-a970-3ef86912c9a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=49032567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.49032567
Directory /workspace/18.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.3880481713
Short name T355
Test name
Test status
Simulation time 43867000 ps
CPU time 0.79 seconds
Started Jul 09 05:08:46 PM PDT 24
Finished Jul 09 05:08:48 PM PDT 24
Peak memory 208192 kb
Host smart-1f6b111f-2801-4ae4-b6bb-6c8f5082f8fe
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880481713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.3880481713
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.2663901229
Short name T356
Test name
Test status
Simulation time 16317391 ps
CPU time 1.07 seconds
Started Jul 09 05:08:55 PM PDT 24
Finished Jul 09 05:08:56 PM PDT 24
Peak memory 208484 kb
Host smart-0dd12a17-f7a7-45d5-aa8b-8030a0c5d3ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663901229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.2663901229
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.825219638
Short name T468
Test name
Test status
Simulation time 729235405 ps
CPU time 15.66 seconds
Started Jul 09 05:08:53 PM PDT 24
Finished Jul 09 05:09:09 PM PDT 24
Peak memory 217628 kb
Host smart-05f3f230-8db1-4528-af71-1e5c9f4f30ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825219638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.825219638
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.2476770300
Short name T562
Test name
Test status
Simulation time 2024593876 ps
CPU time 6.37 seconds
Started Jul 09 05:08:51 PM PDT 24
Finished Jul 09 05:08:58 PM PDT 24
Peak memory 217032 kb
Host smart-fea0eea5-bf9f-4ff4-8551-399f13289f47
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476770300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.2476770300
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.2187334386
Short name T406
Test name
Test status
Simulation time 3058478991 ps
CPU time 84.61 seconds
Started Jul 09 05:08:51 PM PDT 24
Finished Jul 09 05:10:16 PM PDT 24
Peak memory 218372 kb
Host smart-6a0f8ec3-c8d4-4742-9b30-e1a6d01a4b40
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187334386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.2187334386
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.4159478994
Short name T86
Test name
Test status
Simulation time 275049347 ps
CPU time 4.66 seconds
Started Jul 09 05:08:52 PM PDT 24
Finished Jul 09 05:08:57 PM PDT 24
Peak memory 217656 kb
Host smart-9b5043f0-8bd6-476c-a575-18bc63189f2c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159478994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.4159478994
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.1627003886
Short name T736
Test name
Test status
Simulation time 565070104 ps
CPU time 8.64 seconds
Started Jul 09 05:08:52 PM PDT 24
Finished Jul 09 05:09:01 PM PDT 24
Peak memory 217000 kb
Host smart-a2808bce-cdd9-46ab-ae1c-55a4b41208cb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627003886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.1627003886
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.4174509957
Short name T18
Test name
Test status
Simulation time 1785685271 ps
CPU time 69.91 seconds
Started Jul 09 05:08:50 PM PDT 24
Finished Jul 09 05:10:01 PM PDT 24
Peak memory 274932 kb
Host smart-19b51f42-5100-4c3b-ae5a-a83b94bf2322
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174509957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.4174509957
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.315050618
Short name T698
Test name
Test status
Simulation time 1387874168 ps
CPU time 15.97 seconds
Started Jul 09 05:08:49 PM PDT 24
Finished Jul 09 05:09:06 PM PDT 24
Peak memory 250308 kb
Host smart-f7b6a198-b4f7-4322-92c8-d4690521d4a9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315050618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_
jtag_state_post_trans.315050618
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.938898926
Short name T425
Test name
Test status
Simulation time 25337227 ps
CPU time 2.08 seconds
Started Jul 09 05:08:50 PM PDT 24
Finished Jul 09 05:08:53 PM PDT 24
Peak memory 217704 kb
Host smart-5e03067a-1707-4df6-8cb1-3bc12610b265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938898926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.938898926
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.1366684252
Short name T640
Test name
Test status
Simulation time 696467620 ps
CPU time 20.5 seconds
Started Jul 09 05:08:51 PM PDT 24
Finished Jul 09 05:09:12 PM PDT 24
Peak memory 225544 kb
Host smart-590cb438-17a2-479a-a1d3-7c6aaf71210d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366684252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.1366684252
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.3897035190
Short name T706
Test name
Test status
Simulation time 2868338124 ps
CPU time 15.99 seconds
Started Jul 09 05:08:50 PM PDT 24
Finished Jul 09 05:09:06 PM PDT 24
Peak memory 225508 kb
Host smart-ba1f0198-122f-4a9b-9a86-87aaa683edd9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897035190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.3897035190
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.526655949
Short name T431
Test name
Test status
Simulation time 878177270 ps
CPU time 7.3 seconds
Started Jul 09 05:08:51 PM PDT 24
Finished Jul 09 05:08:59 PM PDT 24
Peak memory 217676 kb
Host smart-daffaf64-a645-464f-b4c8-e4d0a5e29740
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526655949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.526655949
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.1591979020
Short name T405
Test name
Test status
Simulation time 1266991898 ps
CPU time 8.16 seconds
Started Jul 09 05:08:51 PM PDT 24
Finished Jul 09 05:09:00 PM PDT 24
Peak memory 225524 kb
Host smart-323a81ff-2645-4c92-bcb1-fad76b096146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591979020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.1591979020
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.3727440911
Short name T253
Test name
Test status
Simulation time 330271563 ps
CPU time 2.35 seconds
Started Jul 09 05:08:52 PM PDT 24
Finished Jul 09 05:08:55 PM PDT 24
Peak memory 217228 kb
Host smart-4d302461-a4ca-4a55-86ca-170bad996b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727440911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.3727440911
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.1781516084
Short name T715
Test name
Test status
Simulation time 1011630500 ps
CPU time 29.43 seconds
Started Jul 09 05:08:50 PM PDT 24
Finished Jul 09 05:09:20 PM PDT 24
Peak memory 250360 kb
Host smart-6c3f84bc-8dd3-48d0-9062-2d4f254ed7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781516084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.1781516084
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.3662356227
Short name T741
Test name
Test status
Simulation time 104504745 ps
CPU time 8.17 seconds
Started Jul 09 05:08:49 PM PDT 24
Finished Jul 09 05:08:58 PM PDT 24
Peak memory 246612 kb
Host smart-064299ff-6044-4c3d-842d-12caa27200ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662356227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.3662356227
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.1333347121
Short name T96
Test name
Test status
Simulation time 5544228762 ps
CPU time 139.33 seconds
Started Jul 09 05:08:53 PM PDT 24
Finished Jul 09 05:11:13 PM PDT 24
Peak memory 275092 kb
Host smart-9cde09de-952a-496e-b3a2-8979f3064a8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333347121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.1333347121
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.1465198728
Short name T559
Test name
Test status
Simulation time 65688588750 ps
CPU time 1141.57 seconds
Started Jul 09 05:08:56 PM PDT 24
Finished Jul 09 05:27:58 PM PDT 24
Peak memory 421604 kb
Host smart-72b6c3fe-f387-41a8-bd79-ee5813da53f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1465198728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.1465198728
Directory /workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.2235158488
Short name T36
Test name
Test status
Simulation time 23513034 ps
CPU time 0.92 seconds
Started Jul 09 05:08:51 PM PDT 24
Finished Jul 09 05:08:53 PM PDT 24
Peak memory 211220 kb
Host smart-f1d0d3c7-4d6c-4fd0-845a-7ce31fbe98a6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235158488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.2235158488
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.4278378297
Short name T791
Test name
Test status
Simulation time 87437985 ps
CPU time 0.86 seconds
Started Jul 09 05:07:28 PM PDT 24
Finished Jul 09 05:07:29 PM PDT 24
Peak memory 208280 kb
Host smart-0aa95f4f-10a7-4a3e-b71d-59e8d892a25a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278378297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.4278378297
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.1228278678
Short name T489
Test name
Test status
Simulation time 1980212658 ps
CPU time 16.78 seconds
Started Jul 09 05:07:25 PM PDT 24
Finished Jul 09 05:07:43 PM PDT 24
Peak memory 217580 kb
Host smart-42a006ab-2eb7-4a54-99a8-9d761db91c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228278678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.1228278678
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.337845105
Short name T346
Test name
Test status
Simulation time 299230658 ps
CPU time 1.64 seconds
Started Jul 09 05:07:27 PM PDT 24
Finished Jul 09 05:07:30 PM PDT 24
Peak memory 217120 kb
Host smart-250df509-5f80-45bb-abf8-e77d5a173e98
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337845105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.337845105
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.1169911721
Short name T783
Test name
Test status
Simulation time 16581193277 ps
CPU time 83.32 seconds
Started Jul 09 05:07:26 PM PDT 24
Finished Jul 09 05:08:50 PM PDT 24
Peak memory 218276 kb
Host smart-455ad786-ba43-4905-9d77-fd7416bcd980
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169911721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.1169911721
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.1527240117
Short name T689
Test name
Test status
Simulation time 2356745029 ps
CPU time 6.71 seconds
Started Jul 09 05:07:25 PM PDT 24
Finished Jul 09 05:07:33 PM PDT 24
Peak memory 217192 kb
Host smart-3c0ba1af-d262-4d71-87f3-55baa3e4a6c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527240117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.1
527240117
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.3602519489
Short name T705
Test name
Test status
Simulation time 298065739 ps
CPU time 6 seconds
Started Jul 09 05:07:30 PM PDT 24
Finished Jul 09 05:07:37 PM PDT 24
Peak memory 222520 kb
Host smart-474868d7-8ab4-4eeb-8b42-f60480c6b277
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602519489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.3602519489
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.4054150503
Short name T604
Test name
Test status
Simulation time 5342963454 ps
CPU time 24.41 seconds
Started Jul 09 05:07:25 PM PDT 24
Finished Jul 09 05:07:51 PM PDT 24
Peak memory 217100 kb
Host smart-8d7715b7-0e4d-4124-af37-43ef8d68d002
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054150503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.4054150503
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.1507728604
Short name T299
Test name
Test status
Simulation time 1132595984 ps
CPU time 4.95 seconds
Started Jul 09 05:07:25 PM PDT 24
Finished Jul 09 05:07:31 PM PDT 24
Peak memory 217040 kb
Host smart-4ce2d109-2714-480e-a130-4f19d2412ac4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507728604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
1507728604
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.1093139612
Short name T812
Test name
Test status
Simulation time 1121923538 ps
CPU time 42.87 seconds
Started Jul 09 05:07:25 PM PDT 24
Finished Jul 09 05:08:08 PM PDT 24
Peak memory 266796 kb
Host smart-876e1888-6816-416f-a1f7-6d0e01e46426
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093139612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.1093139612
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.3086257199
Short name T504
Test name
Test status
Simulation time 564188320 ps
CPU time 12.94 seconds
Started Jul 09 05:07:24 PM PDT 24
Finished Jul 09 05:07:38 PM PDT 24
Peak memory 246144 kb
Host smart-d80b458e-722b-41b9-a9ef-afa96d094758
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086257199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.3086257199
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.3498578551
Short name T466
Test name
Test status
Simulation time 112230534 ps
CPU time 1.85 seconds
Started Jul 09 05:07:24 PM PDT 24
Finished Jul 09 05:07:27 PM PDT 24
Peak memory 217628 kb
Host smart-ed5ce3ed-e00b-4279-b145-52b7b42bc618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498578551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.3498578551
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.3094608
Short name T453
Test name
Test status
Simulation time 199945789 ps
CPU time 12.32 seconds
Started Jul 09 05:07:24 PM PDT 24
Finished Jul 09 05:07:37 PM PDT 24
Peak memory 214080 kb
Host smart-83ff837c-cc2b-4c38-b14c-fadbe11ae53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.3094608
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.2759321629
Short name T215
Test name
Test status
Simulation time 235178726 ps
CPU time 13.51 seconds
Started Jul 09 05:07:24 PM PDT 24
Finished Jul 09 05:07:38 PM PDT 24
Peak memory 225848 kb
Host smart-189422e3-a3c6-4d48-904d-7d77c3df7593
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759321629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.2759321629
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.4239445525
Short name T327
Test name
Test status
Simulation time 265316920 ps
CPU time 11.89 seconds
Started Jul 09 05:07:28 PM PDT 24
Finished Jul 09 05:07:41 PM PDT 24
Peak memory 225460 kb
Host smart-d31f688b-f749-42c6-8b88-f566e7f026af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239445525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.4239445525
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.2919982494
Short name T857
Test name
Test status
Simulation time 195355715 ps
CPU time 5.9 seconds
Started Jul 09 05:07:23 PM PDT 24
Finished Jul 09 05:07:30 PM PDT 24
Peak memory 217652 kb
Host smart-f1fede20-261e-4df9-b8f6-02991088bb31
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919982494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.2
919982494
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.4110047391
Short name T362
Test name
Test status
Simulation time 396346134 ps
CPU time 10.98 seconds
Started Jul 09 05:07:25 PM PDT 24
Finished Jul 09 05:07:37 PM PDT 24
Peak memory 225212 kb
Host smart-fda5f3a7-cfc7-4e80-916d-80addcc52b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110047391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.4110047391
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.3925404738
Short name T635
Test name
Test status
Simulation time 296735189 ps
CPU time 3.68 seconds
Started Jul 09 05:07:25 PM PDT 24
Finished Jul 09 05:07:30 PM PDT 24
Peak memory 214192 kb
Host smart-7b83d861-3519-4d0d-a3f7-af79ca97d15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925404738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.3925404738
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.3144366603
Short name T714
Test name
Test status
Simulation time 295185418 ps
CPU time 37.62 seconds
Started Jul 09 05:07:28 PM PDT 24
Finished Jul 09 05:08:06 PM PDT 24
Peak memory 250340 kb
Host smart-4fb9cc9c-3658-4661-924c-b55471141b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144366603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.3144366603
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.1955836080
Short name T303
Test name
Test status
Simulation time 118946204 ps
CPU time 7.46 seconds
Started Jul 09 05:07:25 PM PDT 24
Finished Jul 09 05:07:33 PM PDT 24
Peak memory 250364 kb
Host smart-6a6c15a4-e579-4dbb-9ac6-412e9b82129d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955836080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.1955836080
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.2868605107
Short name T487
Test name
Test status
Simulation time 12175173001 ps
CPU time 127.41 seconds
Started Jul 09 05:07:31 PM PDT 24
Finished Jul 09 05:09:39 PM PDT 24
Peak memory 268580 kb
Host smart-d3587182-b5da-4bcc-942a-7742a1b408d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868605107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.2868605107
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.1348324068
Short name T274
Test name
Test status
Simulation time 96287163 ps
CPU time 1.44 seconds
Started Jul 09 05:07:25 PM PDT 24
Finished Jul 09 05:07:28 PM PDT 24
Peak memory 217136 kb
Host smart-5f6e354e-a609-4a90-9721-1fcdb685e299
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348324068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.1348324068
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.2746229041
Short name T70
Test name
Test status
Simulation time 92462737 ps
CPU time 0.9 seconds
Started Jul 09 05:08:59 PM PDT 24
Finished Jul 09 05:09:01 PM PDT 24
Peak memory 208460 kb
Host smart-f40be947-07a9-434b-abe6-f0c31cb0988d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746229041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.2746229041
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.2945662037
Short name T43
Test name
Test status
Simulation time 2158892388 ps
CPU time 12.89 seconds
Started Jul 09 05:08:55 PM PDT 24
Finished Jul 09 05:09:08 PM PDT 24
Peak memory 217732 kb
Host smart-2bac63b9-aa29-4a7a-8df7-c70535e051bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945662037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.2945662037
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.822323439
Short name T23
Test name
Test status
Simulation time 1577308081 ps
CPU time 19.99 seconds
Started Jul 09 05:08:56 PM PDT 24
Finished Jul 09 05:09:17 PM PDT 24
Peak memory 216996 kb
Host smart-a94b62dc-1b97-49d1-ae68-53203eb2a6a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822323439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.822323439
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.3381968694
Short name T630
Test name
Test status
Simulation time 43010775 ps
CPU time 2.22 seconds
Started Jul 09 05:08:58 PM PDT 24
Finished Jul 09 05:09:01 PM PDT 24
Peak memory 217720 kb
Host smart-1b40f182-801f-4994-800d-d648859dd106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381968694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.3381968694
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.1617033740
Short name T279
Test name
Test status
Simulation time 338653522 ps
CPU time 14.95 seconds
Started Jul 09 05:08:53 PM PDT 24
Finished Jul 09 05:09:08 PM PDT 24
Peak memory 218348 kb
Host smart-d5546144-55cb-4537-af4f-7fe1739cb261
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617033740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.1617033740
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.2291521376
Short name T341
Test name
Test status
Simulation time 1325577845 ps
CPU time 19.69 seconds
Started Jul 09 05:08:54 PM PDT 24
Finished Jul 09 05:09:14 PM PDT 24
Peak memory 225396 kb
Host smart-486ef359-2a07-453d-bcd6-d3e5e4db4858
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291521376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.2291521376
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.2391385511
Short name T442
Test name
Test status
Simulation time 1840259764 ps
CPU time 9.8 seconds
Started Jul 09 05:08:54 PM PDT 24
Finished Jul 09 05:09:04 PM PDT 24
Peak memory 217728 kb
Host smart-2ab62925-7692-4ced-aea7-1800fe12e7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391385511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.2391385511
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.968864625
Short name T72
Test name
Test status
Simulation time 139852122 ps
CPU time 3.16 seconds
Started Jul 09 05:08:55 PM PDT 24
Finished Jul 09 05:08:59 PM PDT 24
Peak memory 214296 kb
Host smart-dab375f6-f392-4090-b7c9-fcb7f14e3dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968864625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.968864625
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.1561047769
Short name T669
Test name
Test status
Simulation time 935231122 ps
CPU time 23.28 seconds
Started Jul 09 05:08:56 PM PDT 24
Finished Jul 09 05:09:20 PM PDT 24
Peak memory 250460 kb
Host smart-1f5b2567-6d7a-4eb9-9bb3-b61a93d92e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561047769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.1561047769
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.1992660772
Short name T244
Test name
Test status
Simulation time 341359732 ps
CPU time 3.42 seconds
Started Jul 09 05:08:52 PM PDT 24
Finished Jul 09 05:08:56 PM PDT 24
Peak memory 221724 kb
Host smart-ee39fd1f-769a-4d51-9c15-2fac05443b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992660772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.1992660772
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.1194533759
Short name T40
Test name
Test status
Simulation time 4986589169 ps
CPU time 119.3 seconds
Started Jul 09 05:08:58 PM PDT 24
Finished Jul 09 05:10:58 PM PDT 24
Peak memory 283160 kb
Host smart-1ccce7d6-0ad6-4b95-96d4-fc2f37051fad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194533759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.1194533759
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.1490745961
Short name T695
Test name
Test status
Simulation time 92696750934 ps
CPU time 870.88 seconds
Started Jul 09 05:08:57 PM PDT 24
Finished Jul 09 05:23:29 PM PDT 24
Peak memory 421548 kb
Host smart-e64a1f54-6a3e-4d7f-8c23-e0aa6244d543
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1490745961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all_with_rand_reset.1490745961
Directory /workspace/20.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.252402051
Short name T861
Test name
Test status
Simulation time 14864114 ps
CPU time 0.87 seconds
Started Jul 09 05:08:58 PM PDT 24
Finished Jul 09 05:09:00 PM PDT 24
Peak memory 208244 kb
Host smart-a161d185-dde4-4187-a5b2-66ccf05f2600
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252402051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.252402051
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.3298480746
Short name T156
Test name
Test status
Simulation time 220259550 ps
CPU time 8.96 seconds
Started Jul 09 05:08:59 PM PDT 24
Finished Jul 09 05:09:09 PM PDT 24
Peak memory 217664 kb
Host smart-0722ec6f-1a47-4c04-9176-daa6d58e5e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298480746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.3298480746
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.3824906404
Short name T646
Test name
Test status
Simulation time 1340777614 ps
CPU time 2.53 seconds
Started Jul 09 05:09:01 PM PDT 24
Finished Jul 09 05:09:06 PM PDT 24
Peak memory 217144 kb
Host smart-55e99050-f262-4e9a-a180-27caab7cbfee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824906404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.3824906404
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.365704737
Short name T90
Test name
Test status
Simulation time 53209390 ps
CPU time 2.8 seconds
Started Jul 09 05:08:57 PM PDT 24
Finished Jul 09 05:09:00 PM PDT 24
Peak memory 217704 kb
Host smart-c4227e56-04c2-4428-a61f-104cbda27b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365704737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.365704737
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.2427031021
Short name T670
Test name
Test status
Simulation time 1697836157 ps
CPU time 12.31 seconds
Started Jul 09 05:08:58 PM PDT 24
Finished Jul 09 05:09:11 PM PDT 24
Peak memory 225412 kb
Host smart-5bba0d3b-3fd9-4d9f-b815-cdda5ff699ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427031021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.2427031021
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.2748695204
Short name T280
Test name
Test status
Simulation time 429760506 ps
CPU time 9.53 seconds
Started Jul 09 05:09:01 PM PDT 24
Finished Jul 09 05:09:12 PM PDT 24
Peak memory 217624 kb
Host smart-7c9ae251-d929-4122-8abd-30ef2f8fe68a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748695204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
2748695204
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.754129496
Short name T763
Test name
Test status
Simulation time 870891660 ps
CPU time 9.52 seconds
Started Jul 09 05:08:59 PM PDT 24
Finished Jul 09 05:09:09 PM PDT 24
Peak memory 225484 kb
Host smart-4ec5023c-aa45-4501-8acf-be1f85484f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754129496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.754129496
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.2043314680
Short name T672
Test name
Test status
Simulation time 82408403 ps
CPU time 2 seconds
Started Jul 09 05:08:57 PM PDT 24
Finished Jul 09 05:09:00 PM PDT 24
Peak memory 213544 kb
Host smart-56a84364-ec6e-4256-b475-3523b150bf18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043314680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.2043314680
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.3811789589
Short name T319
Test name
Test status
Simulation time 774291807 ps
CPU time 22.38 seconds
Started Jul 09 05:08:59 PM PDT 24
Finished Jul 09 05:09:23 PM PDT 24
Peak memory 250480 kb
Host smart-2bc96e19-40cd-4da7-9332-6703cf4d60d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811789589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.3811789589
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.3152317652
Short name T223
Test name
Test status
Simulation time 159013813 ps
CPU time 3.54 seconds
Started Jul 09 05:09:00 PM PDT 24
Finished Jul 09 05:09:05 PM PDT 24
Peak memory 221276 kb
Host smart-324fd46c-30f2-4b9f-9bd9-24ff67fd72d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152317652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.3152317652
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.2372287871
Short name T19
Test name
Test status
Simulation time 14606635794 ps
CPU time 115.69 seconds
Started Jul 09 05:08:58 PM PDT 24
Finished Jul 09 05:10:54 PM PDT 24
Peak memory 280180 kb
Host smart-0a7f0dfc-6cf2-46d5-8085-14c65274e7c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372287871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.2372287871
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.4122883240
Short name T78
Test name
Test status
Simulation time 13327197 ps
CPU time 1.18 seconds
Started Jul 09 05:08:58 PM PDT 24
Finished Jul 09 05:09:00 PM PDT 24
Peak memory 211276 kb
Host smart-2722f68e-1f58-4a40-b0be-73ed4c21e4c8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122883240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.4122883240
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.3857776724
Short name T374
Test name
Test status
Simulation time 91359083 ps
CPU time 1.35 seconds
Started Jul 09 05:09:02 PM PDT 24
Finished Jul 09 05:09:05 PM PDT 24
Peak memory 208440 kb
Host smart-bea74a76-5ad9-4ad3-802a-406c75000c10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857776724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.3857776724
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.3443359609
Short name T817
Test name
Test status
Simulation time 505058568 ps
CPU time 8.46 seconds
Started Jul 09 05:09:02 PM PDT 24
Finished Jul 09 05:09:12 PM PDT 24
Peak memory 225396 kb
Host smart-43e29125-e160-4102-af9f-d0a5a4c4891a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443359609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.3443359609
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.1313581948
Short name T22
Test name
Test status
Simulation time 1083988605 ps
CPU time 6.68 seconds
Started Jul 09 05:09:01 PM PDT 24
Finished Jul 09 05:09:09 PM PDT 24
Peak memory 216556 kb
Host smart-35b22625-edf0-4cb8-af09-a4b1251b7c95
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313581948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.1313581948
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.3305550206
Short name T685
Test name
Test status
Simulation time 289013677 ps
CPU time 2.9 seconds
Started Jul 09 05:09:01 PM PDT 24
Finished Jul 09 05:09:05 PM PDT 24
Peak memory 217708 kb
Host smart-f01e1b53-794f-41e1-94ab-8cac683dda42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305550206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.3305550206
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.2770179382
Short name T636
Test name
Test status
Simulation time 1001483670 ps
CPU time 9.41 seconds
Started Jul 09 05:09:04 PM PDT 24
Finished Jul 09 05:09:15 PM PDT 24
Peak memory 218316 kb
Host smart-99311922-c104-48d7-a8c8-f5d20eb3ff42
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770179382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.2770179382
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.705470408
Short name T193
Test name
Test status
Simulation time 1885208277 ps
CPU time 12.23 seconds
Started Jul 09 05:09:01 PM PDT 24
Finished Jul 09 05:09:15 PM PDT 24
Peak memory 225416 kb
Host smart-73e2f256-9cff-4da1-b2e5-44c9366386b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705470408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_di
gest.705470408
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.4077920636
Short name T509
Test name
Test status
Simulation time 198272770 ps
CPU time 7.9 seconds
Started Jul 09 05:09:03 PM PDT 24
Finished Jul 09 05:09:12 PM PDT 24
Peak memory 217608 kb
Host smart-6bccafd0-6b75-4746-9c93-ecd26d959e5e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077920636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
4077920636
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.1209088796
Short name T409
Test name
Test status
Simulation time 4409696096 ps
CPU time 9.32 seconds
Started Jul 09 05:09:03 PM PDT 24
Finished Jul 09 05:09:14 PM PDT 24
Peak memory 217860 kb
Host smart-b2dda88c-96e2-4234-a418-10aafe1c592c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209088796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.1209088796
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.1589498132
Short name T11
Test name
Test status
Simulation time 201485696 ps
CPU time 2.9 seconds
Started Jul 09 05:08:58 PM PDT 24
Finished Jul 09 05:09:02 PM PDT 24
Peak memory 214004 kb
Host smart-c4a98d0c-1e0d-4cc2-96f4-39a0958787c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589498132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.1589498132
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.1851049982
Short name T278
Test name
Test status
Simulation time 237842803 ps
CPU time 27 seconds
Started Jul 09 05:09:00 PM PDT 24
Finished Jul 09 05:09:29 PM PDT 24
Peak memory 245072 kb
Host smart-aef47883-a55a-4f8e-b40a-b519e245c4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851049982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.1851049982
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.222541682
Short name T317
Test name
Test status
Simulation time 229428411 ps
CPU time 6.23 seconds
Started Jul 09 05:08:58 PM PDT 24
Finished Jul 09 05:09:05 PM PDT 24
Peak memory 249896 kb
Host smart-e7cd944d-abb2-48d3-8db9-2084ee2e2bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222541682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.222541682
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.1573302521
Short name T451
Test name
Test status
Simulation time 22908972184 ps
CPU time 118.08 seconds
Started Jul 09 05:09:01 PM PDT 24
Finished Jul 09 05:11:01 PM PDT 24
Peak memory 282864 kb
Host smart-373447ad-baee-49fe-87c2-36c548204d4b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573302521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.1573302521
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2832651489
Short name T371
Test name
Test status
Simulation time 54507463 ps
CPU time 1.08 seconds
Started Jul 09 05:08:58 PM PDT 24
Finished Jul 09 05:09:00 PM PDT 24
Peak memory 211404 kb
Host smart-26c6a0db-749a-4cc0-9417-b67d18282325
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832651489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.2832651489
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.2587059471
Short name T811
Test name
Test status
Simulation time 68612187 ps
CPU time 1.05 seconds
Started Jul 09 05:09:07 PM PDT 24
Finished Jul 09 05:09:09 PM PDT 24
Peak memory 208388 kb
Host smart-8a320f69-219d-4d43-900b-847593e2874f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587059471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.2587059471
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.3292301665
Short name T664
Test name
Test status
Simulation time 1338209997 ps
CPU time 11.28 seconds
Started Jul 09 05:09:01 PM PDT 24
Finished Jul 09 05:09:14 PM PDT 24
Peak memory 217704 kb
Host smart-92969503-3d95-47f9-a7c4-0453ef663a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292301665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.3292301665
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.339066546
Short name T26
Test name
Test status
Simulation time 479010781 ps
CPU time 5.97 seconds
Started Jul 09 05:09:07 PM PDT 24
Finished Jul 09 05:09:14 PM PDT 24
Peak memory 216748 kb
Host smart-38a9a773-f5e9-4c2a-a2d7-5ee313280c7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339066546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.339066546
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.3560753440
Short name T63
Test name
Test status
Simulation time 68960631 ps
CPU time 2.49 seconds
Started Jul 09 05:09:03 PM PDT 24
Finished Jul 09 05:09:07 PM PDT 24
Peak memory 217804 kb
Host smart-6ce18b5b-74f7-405f-9daa-ee0bfc90f741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560753440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.3560753440
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.721900890
Short name T693
Test name
Test status
Simulation time 868335740 ps
CPU time 13.32 seconds
Started Jul 09 05:09:07 PM PDT 24
Finished Jul 09 05:09:21 PM PDT 24
Peak memory 225376 kb
Host smart-d3737d63-2ddd-4216-8219-a9b95cbf72ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721900890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_di
gest.721900890
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.2549371896
Short name T778
Test name
Test status
Simulation time 382168506 ps
CPU time 7.2 seconds
Started Jul 09 05:09:05 PM PDT 24
Finished Jul 09 05:09:13 PM PDT 24
Peak memory 217536 kb
Host smart-d4dbf3a6-8079-4f9e-8bb0-cb8ad099fb29
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549371896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
2549371896
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.3496169226
Short name T403
Test name
Test status
Simulation time 620118300 ps
CPU time 7.63 seconds
Started Jul 09 05:09:03 PM PDT 24
Finished Jul 09 05:09:12 PM PDT 24
Peak memory 217704 kb
Host smart-487cd334-c11b-4a12-bf4e-22dc236138b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496169226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.3496169226
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.2923576906
Short name T385
Test name
Test status
Simulation time 71875599 ps
CPU time 2.57 seconds
Started Jul 09 05:09:05 PM PDT 24
Finished Jul 09 05:09:08 PM PDT 24
Peak memory 217080 kb
Host smart-4a437b14-62d7-4e5c-b1bc-e410d829bbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923576906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.2923576906
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.3772946058
Short name T224
Test name
Test status
Simulation time 223042631 ps
CPU time 27.15 seconds
Started Jul 09 05:09:03 PM PDT 24
Finished Jul 09 05:09:32 PM PDT 24
Peak memory 250384 kb
Host smart-5d3b6115-5fc7-461d-854a-14cb850e84d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772946058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.3772946058
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.2057825349
Short name T740
Test name
Test status
Simulation time 71969895 ps
CPU time 8.4 seconds
Started Jul 09 05:09:04 PM PDT 24
Finished Jul 09 05:09:14 PM PDT 24
Peak memory 250404 kb
Host smart-afd911a7-7247-44ec-b885-a69ad72b7aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057825349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.2057825349
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.1242014537
Short name T270
Test name
Test status
Simulation time 12651847548 ps
CPU time 287.82 seconds
Started Jul 09 05:09:06 PM PDT 24
Finished Jul 09 05:13:55 PM PDT 24
Peak memory 274364 kb
Host smart-ae58b090-352b-4995-925b-c63fe481cc38
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242014537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.1242014537
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3104526663
Short name T851
Test name
Test status
Simulation time 13833164 ps
CPU time 0.81 seconds
Started Jul 09 05:09:02 PM PDT 24
Finished Jul 09 05:09:05 PM PDT 24
Peak memory 208240 kb
Host smart-55ce40e0-d454-4fc3-b05b-b7779da78c45
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104526663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.3104526663
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.261402495
Short name T605
Test name
Test status
Simulation time 20392773 ps
CPU time 1.17 seconds
Started Jul 09 05:09:10 PM PDT 24
Finished Jul 09 05:09:12 PM PDT 24
Peak memory 208520 kb
Host smart-7c61488a-12a4-4ffa-b26d-12b9bd157ff4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261402495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.261402495
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.1426673919
Short name T430
Test name
Test status
Simulation time 2086621762 ps
CPU time 21.89 seconds
Started Jul 09 05:09:07 PM PDT 24
Finished Jul 09 05:09:30 PM PDT 24
Peak memory 225508 kb
Host smart-3fa20a8a-544c-45cd-8198-0cdb5716a9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426673919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.1426673919
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.1927968040
Short name T256
Test name
Test status
Simulation time 437986933 ps
CPU time 11.73 seconds
Started Jul 09 05:09:05 PM PDT 24
Finished Jul 09 05:09:18 PM PDT 24
Peak memory 217092 kb
Host smart-6751824b-a03c-4226-8eea-8912677b219b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927968040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.1927968040
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.1181642870
Short name T235
Test name
Test status
Simulation time 122611083 ps
CPU time 3.22 seconds
Started Jul 09 05:09:06 PM PDT 24
Finished Jul 09 05:09:10 PM PDT 24
Peak memory 217656 kb
Host smart-2f535ae6-b4ea-4656-9f2e-9071b66f2818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181642870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.1181642870
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.4286477189
Short name T149
Test name
Test status
Simulation time 512940123 ps
CPU time 8.34 seconds
Started Jul 09 05:09:08 PM PDT 24
Finished Jul 09 05:09:18 PM PDT 24
Peak memory 225428 kb
Host smart-1ba3cb5e-09be-47d8-81a9-28fa7b2ea5ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286477189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.4286477189
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.2521189985
Short name T535
Test name
Test status
Simulation time 406144662 ps
CPU time 6.4 seconds
Started Jul 09 05:09:08 PM PDT 24
Finished Jul 09 05:09:15 PM PDT 24
Peak memory 217604 kb
Host smart-5adad2e4-e074-4cd9-8092-86b728a80a90
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521189985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
2521189985
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.2433745591
Short name T538
Test name
Test status
Simulation time 323490122 ps
CPU time 10.62 seconds
Started Jul 09 05:09:07 PM PDT 24
Finished Jul 09 05:09:18 PM PDT 24
Peak memory 225504 kb
Host smart-33dad2f0-c346-4fe5-bda6-7fcb1ad46056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433745591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.2433745591
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.1448969379
Short name T155
Test name
Test status
Simulation time 49420187 ps
CPU time 2.84 seconds
Started Jul 09 05:09:06 PM PDT 24
Finished Jul 09 05:09:10 PM PDT 24
Peak memory 217048 kb
Host smart-5f691af7-ab29-4a94-b197-7df368530807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448969379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.1448969379
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.3367075829
Short name T266
Test name
Test status
Simulation time 942080333 ps
CPU time 26.83 seconds
Started Jul 09 05:09:07 PM PDT 24
Finished Jul 09 05:09:35 PM PDT 24
Peak memory 250492 kb
Host smart-1d095706-d0c7-4128-99bc-70395617dc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367075829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.3367075829
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.3959551920
Short name T520
Test name
Test status
Simulation time 67215648 ps
CPU time 6.93 seconds
Started Jul 09 05:09:08 PM PDT 24
Finished Jul 09 05:09:16 PM PDT 24
Peak memory 246432 kb
Host smart-4ede5740-2c5d-4596-a79d-e5ef4b5cd3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959551920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.3959551920
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.957995671
Short name T631
Test name
Test status
Simulation time 52091404190 ps
CPU time 253.98 seconds
Started Jul 09 05:09:08 PM PDT 24
Finished Jul 09 05:13:23 PM PDT 24
Peak memory 250428 kb
Host smart-54abdb0a-d6ee-4e8a-b386-79a863e3edb5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957995671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.957995671
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.806728785
Short name T642
Test name
Test status
Simulation time 13197208 ps
CPU time 1.13 seconds
Started Jul 09 05:09:06 PM PDT 24
Finished Jul 09 05:09:08 PM PDT 24
Peak memory 211312 kb
Host smart-9a6d5fa6-8c13-405e-9d39-ec8717e0ccab
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806728785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ct
rl_volatile_unlock_smoke.806728785
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.1880602751
Short name T365
Test name
Test status
Simulation time 122635760 ps
CPU time 0.98 seconds
Started Jul 09 05:09:15 PM PDT 24
Finished Jul 09 05:09:16 PM PDT 24
Peak memory 208204 kb
Host smart-d85f7c77-bb8d-4a10-8fbf-085cf419ef24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880602751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.1880602751
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.346338252
Short name T753
Test name
Test status
Simulation time 481406703 ps
CPU time 14.24 seconds
Started Jul 09 05:09:09 PM PDT 24
Finished Jul 09 05:09:24 PM PDT 24
Peak memory 225512 kb
Host smart-00073051-54c4-4fc6-87f1-9746f6e0456f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346338252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.346338252
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.900646541
Short name T413
Test name
Test status
Simulation time 42917489 ps
CPU time 1.21 seconds
Started Jul 09 05:09:12 PM PDT 24
Finished Jul 09 05:09:14 PM PDT 24
Peak memory 216324 kb
Host smart-680bc379-3627-467c-a3c5-02172e04d21c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900646541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.900646541
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.2408966312
Short name T837
Test name
Test status
Simulation time 24274032 ps
CPU time 1.66 seconds
Started Jul 09 05:09:12 PM PDT 24
Finished Jul 09 05:09:14 PM PDT 24
Peak memory 221464 kb
Host smart-04000d72-30a1-4ee9-a831-cda6bff47c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408966312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.2408966312
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.4143460225
Short name T852
Test name
Test status
Simulation time 204406821 ps
CPU time 11.12 seconds
Started Jul 09 05:09:10 PM PDT 24
Finished Jul 09 05:09:22 PM PDT 24
Peak memory 217924 kb
Host smart-c97603f3-b5c7-4f9b-907e-08be277dfd12
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143460225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.4143460225
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.368482395
Short name T483
Test name
Test status
Simulation time 204372038 ps
CPU time 9.87 seconds
Started Jul 09 05:09:12 PM PDT 24
Finished Jul 09 05:09:22 PM PDT 24
Peak memory 225392 kb
Host smart-bc53e1a2-d8fa-4b97-bbf4-771e9ffc74a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368482395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_di
gest.368482395
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.655839737
Short name T455
Test name
Test status
Simulation time 715267973 ps
CPU time 9.25 seconds
Started Jul 09 05:09:11 PM PDT 24
Finished Jul 09 05:09:20 PM PDT 24
Peak memory 217640 kb
Host smart-fc0331c3-47f1-4eb0-a479-05d047a4dd6a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655839737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.655839737
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.1347173190
Short name T819
Test name
Test status
Simulation time 326852451 ps
CPU time 11.78 seconds
Started Jul 09 05:09:11 PM PDT 24
Finished Jul 09 05:09:24 PM PDT 24
Peak memory 225528 kb
Host smart-0f7a8cac-3778-47a2-bada-ae747b80f274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347173190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.1347173190
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.3576212572
Short name T554
Test name
Test status
Simulation time 184170945 ps
CPU time 3.04 seconds
Started Jul 09 05:09:10 PM PDT 24
Finished Jul 09 05:09:14 PM PDT 24
Peak memory 214204 kb
Host smart-f50737a2-4a36-469d-a638-2262e317a948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576212572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.3576212572
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.2312875946
Short name T427
Test name
Test status
Simulation time 1352541170 ps
CPU time 21.88 seconds
Started Jul 09 05:09:15 PM PDT 24
Finished Jul 09 05:09:37 PM PDT 24
Peak memory 250244 kb
Host smart-9a1c33ba-c1b3-49bb-a26f-315bfc086956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312875946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.2312875946
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.353389900
Short name T565
Test name
Test status
Simulation time 896496318 ps
CPU time 6.35 seconds
Started Jul 09 05:09:12 PM PDT 24
Finished Jul 09 05:09:19 PM PDT 24
Peak memory 249984 kb
Host smart-9804f053-3bb7-4c13-b46f-1eaf4c04a607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353389900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.353389900
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.2254454405
Short name T384
Test name
Test status
Simulation time 18208391351 ps
CPU time 293.05 seconds
Started Jul 09 05:09:12 PM PDT 24
Finished Jul 09 05:14:06 PM PDT 24
Peak memory 287532 kb
Host smart-1e0c512d-f122-42d7-861e-e4c64fc249b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254454405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.2254454405
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.2059702422
Short name T821
Test name
Test status
Simulation time 25209253 ps
CPU time 0.85 seconds
Started Jul 09 05:09:08 PM PDT 24
Finished Jul 09 05:09:10 PM PDT 24
Peak memory 208228 kb
Host smart-7c4b97a0-3feb-402f-84c6-4e5fe7005436
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059702422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.2059702422
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.1553917579
Short name T91
Test name
Test status
Simulation time 17916502 ps
CPU time 1.01 seconds
Started Jul 09 05:09:16 PM PDT 24
Finished Jul 09 05:09:17 PM PDT 24
Peak memory 208328 kb
Host smart-21d10b9c-156a-438f-b792-f192b6e9c8dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553917579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.1553917579
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.2648476002
Short name T859
Test name
Test status
Simulation time 838984555 ps
CPU time 11.21 seconds
Started Jul 09 05:09:16 PM PDT 24
Finished Jul 09 05:09:28 PM PDT 24
Peak memory 217668 kb
Host smart-2449af1c-b90c-420c-aa7b-b489aa96b9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648476002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.2648476002
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.2185156383
Short name T847
Test name
Test status
Simulation time 346704216 ps
CPU time 9.92 seconds
Started Jul 09 05:09:14 PM PDT 24
Finished Jul 09 05:09:25 PM PDT 24
Peak memory 217124 kb
Host smart-f7de4962-18ed-4fa8-820a-ff09332f47a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185156383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.2185156383
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.1175436251
Short name T369
Test name
Test status
Simulation time 65906946 ps
CPU time 3.34 seconds
Started Jul 09 05:09:10 PM PDT 24
Finished Jul 09 05:09:14 PM PDT 24
Peak memory 217648 kb
Host smart-0d65ab19-0f04-41ec-be68-42b11eaca72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175436251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.1175436251
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.3389344858
Short name T580
Test name
Test status
Simulation time 1447583007 ps
CPU time 8.61 seconds
Started Jul 09 05:09:15 PM PDT 24
Finished Jul 09 05:09:25 PM PDT 24
Peak memory 225380 kb
Host smart-5a402d31-50dd-4d12-b1d6-56be926eb44d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389344858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.3389344858
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.835078257
Short name T57
Test name
Test status
Simulation time 355860550 ps
CPU time 12.28 seconds
Started Jul 09 05:09:15 PM PDT 24
Finished Jul 09 05:09:28 PM PDT 24
Peak memory 217652 kb
Host smart-95ae4297-4e60-4b89-99af-61c787af9d72
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835078257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.835078257
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.609691675
Short name T662
Test name
Test status
Simulation time 1165750631 ps
CPU time 9.89 seconds
Started Jul 09 05:09:25 PM PDT 24
Finished Jul 09 05:09:36 PM PDT 24
Peak memory 225440 kb
Host smart-efd479d2-dd12-4f8b-ba0d-5c49dd71426d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609691675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.609691675
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.213919161
Short name T69
Test name
Test status
Simulation time 196405682 ps
CPU time 3.03 seconds
Started Jul 09 05:09:11 PM PDT 24
Finished Jul 09 05:09:15 PM PDT 24
Peak memory 214476 kb
Host smart-e92efea7-b72b-44ec-b879-e2fd6f27d5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213919161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.213919161
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.608882800
Short name T210
Test name
Test status
Simulation time 1318965389 ps
CPU time 27.67 seconds
Started Jul 09 05:09:12 PM PDT 24
Finished Jul 09 05:09:40 PM PDT 24
Peak memory 250372 kb
Host smart-2400a5ed-991e-4d11-91cf-edca595868ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608882800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.608882800
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.2207259162
Short name T462
Test name
Test status
Simulation time 558606767 ps
CPU time 8.15 seconds
Started Jul 09 05:09:15 PM PDT 24
Finished Jul 09 05:09:23 PM PDT 24
Peak memory 250360 kb
Host smart-6696d617-ffea-42d9-88ce-a09b77cb0d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207259162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.2207259162
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.4093784243
Short name T774
Test name
Test status
Simulation time 16478612562 ps
CPU time 36.85 seconds
Started Jul 09 05:09:25 PM PDT 24
Finished Jul 09 05:10:03 PM PDT 24
Peak memory 266824 kb
Host smart-5a8935dd-207b-473f-bc87-0ec6cfd5f8c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093784243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.4093784243
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.325940851
Short name T613
Test name
Test status
Simulation time 32594284 ps
CPU time 0.98 seconds
Started Jul 09 05:09:11 PM PDT 24
Finished Jul 09 05:09:12 PM PDT 24
Peak memory 211244 kb
Host smart-fb58b8ea-847c-42ec-a318-afdf256a80f2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325940851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ct
rl_volatile_unlock_smoke.325940851
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.88589231
Short name T709
Test name
Test status
Simulation time 158364926 ps
CPU time 0.93 seconds
Started Jul 09 05:09:19 PM PDT 24
Finished Jul 09 05:09:20 PM PDT 24
Peak memory 208420 kb
Host smart-f11e0eb0-b910-408a-a55c-2879b596cb29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88589231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.88589231
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.2530917266
Short name T644
Test name
Test status
Simulation time 1000478316 ps
CPU time 11.83 seconds
Started Jul 09 05:09:15 PM PDT 24
Finished Jul 09 05:09:28 PM PDT 24
Peak memory 217672 kb
Host smart-d3c1d1ce-bc8c-463a-967b-839f890bac7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530917266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.2530917266
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.1537718001
Short name T389
Test name
Test status
Simulation time 944718185 ps
CPU time 5.81 seconds
Started Jul 09 05:09:15 PM PDT 24
Finished Jul 09 05:09:22 PM PDT 24
Peak memory 217132 kb
Host smart-f48e79f9-8efe-45d9-8787-135ff7336056
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537718001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.1537718001
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.3121273651
Short name T236
Test name
Test status
Simulation time 286338450 ps
CPU time 3.79 seconds
Started Jul 09 05:09:25 PM PDT 24
Finished Jul 09 05:09:29 PM PDT 24
Peak memory 217660 kb
Host smart-b7b39723-a576-4aa9-87a6-4ad6f0622a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121273651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.3121273651
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.2923794041
Short name T415
Test name
Test status
Simulation time 1434782979 ps
CPU time 14.72 seconds
Started Jul 09 05:09:18 PM PDT 24
Finished Jul 09 05:09:33 PM PDT 24
Peak memory 218308 kb
Host smart-7ef32526-7b81-448f-8e6c-aafef2071b58
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923794041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.2923794041
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.2378973854
Short name T143
Test name
Test status
Simulation time 1731586212 ps
CPU time 9.13 seconds
Started Jul 09 05:09:15 PM PDT 24
Finished Jul 09 05:09:25 PM PDT 24
Peak memory 225392 kb
Host smart-a178ed36-0cc5-4037-a15b-7de74aaf76f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378973854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.2378973854
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.326029645
Short name T674
Test name
Test status
Simulation time 327229242 ps
CPU time 8.52 seconds
Started Jul 09 05:09:25 PM PDT 24
Finished Jul 09 05:09:34 PM PDT 24
Peak memory 225396 kb
Host smart-0b0bfcda-dbe0-46a8-901f-d81ba898cb72
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326029645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.326029645
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.3781644733
Short name T623
Test name
Test status
Simulation time 1067984111 ps
CPU time 8.05 seconds
Started Jul 09 05:09:16 PM PDT 24
Finished Jul 09 05:09:25 PM PDT 24
Peak memory 224676 kb
Host smart-6e5e7e54-623f-4ce1-963a-9e15d56afac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781644733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.3781644733
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.2800497677
Short name T719
Test name
Test status
Simulation time 936742430 ps
CPU time 3.16 seconds
Started Jul 09 05:09:14 PM PDT 24
Finished Jul 09 05:09:18 PM PDT 24
Peak memory 217124 kb
Host smart-fd37c202-290a-4109-b6d6-2a897f925a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800497677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.2800497677
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.4145137114
Short name T443
Test name
Test status
Simulation time 1098086593 ps
CPU time 34.47 seconds
Started Jul 09 05:09:15 PM PDT 24
Finished Jul 09 05:09:50 PM PDT 24
Peak memory 250440 kb
Host smart-fd2eb8c2-24e1-4f85-9ff3-07d6357b7691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145137114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.4145137114
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.4191525423
Short name T743
Test name
Test status
Simulation time 41159516 ps
CPU time 6.01 seconds
Started Jul 09 05:09:14 PM PDT 24
Finished Jul 09 05:09:20 PM PDT 24
Peak memory 250380 kb
Host smart-6dfb7ee0-d3d3-4d14-9b23-4150e9dd753a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191525423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.4191525423
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.740340281
Short name T30
Test name
Test status
Simulation time 18844588758 ps
CPU time 136.67 seconds
Started Jul 09 05:09:33 PM PDT 24
Finished Jul 09 05:11:50 PM PDT 24
Peak memory 225512 kb
Host smart-dd61163f-a40d-4cae-a903-b5a6e0a44631
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740340281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.740340281
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.4077362023
Short name T84
Test name
Test status
Simulation time 29954276087 ps
CPU time 945.27 seconds
Started Jul 09 05:09:33 PM PDT 24
Finished Jul 09 05:25:20 PM PDT 24
Peak memory 692964 kb
Host smart-b0669715-b7b8-41b2-9dc4-d939e76b8a39
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4077362023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all_with_rand_reset.4077362023
Directory /workspace/27.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.1843705622
Short name T239
Test name
Test status
Simulation time 13836776 ps
CPU time 0.95 seconds
Started Jul 09 05:09:16 PM PDT 24
Finished Jul 09 05:09:17 PM PDT 24
Peak memory 208536 kb
Host smart-900ae9a6-51c5-403e-8f61-7bec2397e460
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843705622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.1843705622
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.612007804
Short name T625
Test name
Test status
Simulation time 38502600 ps
CPU time 1.18 seconds
Started Jul 09 05:09:18 PM PDT 24
Finished Jul 09 05:09:19 PM PDT 24
Peak memory 208416 kb
Host smart-dc2e8a4e-661e-4218-a971-4d4a371a99f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612007804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.612007804
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.3168339037
Short name T444
Test name
Test status
Simulation time 229124417 ps
CPU time 11.81 seconds
Started Jul 09 05:09:33 PM PDT 24
Finished Jul 09 05:09:46 PM PDT 24
Peak memory 217656 kb
Host smart-8426b17b-3c78-414b-84b2-677a5104da2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168339037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.3168339037
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.1058357653
Short name T440
Test name
Test status
Simulation time 1664745857 ps
CPU time 10.53 seconds
Started Jul 09 05:09:21 PM PDT 24
Finished Jul 09 05:09:32 PM PDT 24
Peak memory 217088 kb
Host smart-e55477d8-6073-4b74-bd6b-6aecd3e3e0e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058357653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.1058357653
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.554838317
Short name T490
Test name
Test status
Simulation time 26483363 ps
CPU time 1.73 seconds
Started Jul 09 05:09:32 PM PDT 24
Finished Jul 09 05:09:34 PM PDT 24
Peak memory 221476 kb
Host smart-e4f0ba15-21bd-4fc9-bf59-9dd2b68f5242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554838317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.554838317
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.2582982084
Short name T810
Test name
Test status
Simulation time 1897286184 ps
CPU time 15.59 seconds
Started Jul 09 05:09:32 PM PDT 24
Finished Jul 09 05:09:48 PM PDT 24
Peak memory 225264 kb
Host smart-66f2d4d2-67be-4fea-9530-b61ae88b0a9b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582982084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.2582982084
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.2785580619
Short name T579
Test name
Test status
Simulation time 209867899 ps
CPU time 10.19 seconds
Started Jul 09 05:09:18 PM PDT 24
Finished Jul 09 05:09:29 PM PDT 24
Peak memory 217656 kb
Host smart-746e1365-e62f-4270-afd5-c627e5f4989c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785580619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.2785580619
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.569477564
Short name T311
Test name
Test status
Simulation time 567978009 ps
CPU time 11.43 seconds
Started Jul 09 05:09:22 PM PDT 24
Finished Jul 09 05:09:34 PM PDT 24
Peak memory 217704 kb
Host smart-9728e04a-c701-4590-a9bc-b9c22a629ffa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569477564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.569477564
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.1122980558
Short name T697
Test name
Test status
Simulation time 326066473 ps
CPU time 7.29 seconds
Started Jul 09 05:09:22 PM PDT 24
Finished Jul 09 05:09:30 PM PDT 24
Peak memory 224120 kb
Host smart-a7e5bda5-fed4-4db4-a499-8950a9ab3111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122980558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.1122980558
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.2237833580
Short name T159
Test name
Test status
Simulation time 213345672 ps
CPU time 2.75 seconds
Started Jul 09 05:09:19 PM PDT 24
Finished Jul 09 05:09:22 PM PDT 24
Peak memory 214212 kb
Host smart-93e3d372-89aa-40d6-b08f-9f597069071c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237833580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.2237833580
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.493988942
Short name T581
Test name
Test status
Simulation time 1043919108 ps
CPU time 22.29 seconds
Started Jul 09 05:09:19 PM PDT 24
Finished Jul 09 05:09:42 PM PDT 24
Peak memory 246596 kb
Host smart-83db4ffc-f08c-45b7-85a8-47acd25b99cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493988942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.493988942
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.2021892342
Short name T548
Test name
Test status
Simulation time 236624345 ps
CPU time 7.36 seconds
Started Jul 09 05:09:20 PM PDT 24
Finished Jul 09 05:09:27 PM PDT 24
Peak memory 249980 kb
Host smart-54ff5ec0-bc6f-4481-9898-9cf8f7f44249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021892342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.2021892342
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.3540308188
Short name T161
Test name
Test status
Simulation time 14848342563 ps
CPU time 112.5 seconds
Started Jul 09 05:09:22 PM PDT 24
Finished Jul 09 05:11:15 PM PDT 24
Peak memory 249428 kb
Host smart-88f99b0d-f63a-4bf5-bcfe-79f6cab39323
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540308188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.3540308188
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.2281458118
Short name T135
Test name
Test status
Simulation time 37439637972 ps
CPU time 919.37 seconds
Started Jul 09 05:09:19 PM PDT 24
Finished Jul 09 05:24:39 PM PDT 24
Peak memory 487176 kb
Host smart-a1c5c603-2d96-471d-87ca-21a37543f120
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2281458118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all_with_rand_reset.2281458118
Directory /workspace/28.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.2389658012
Short name T598
Test name
Test status
Simulation time 14876024 ps
CPU time 0.88 seconds
Started Jul 09 05:09:33 PM PDT 24
Finished Jul 09 05:09:35 PM PDT 24
Peak memory 208124 kb
Host smart-43209377-1129-492d-b642-7c3def378789
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389658012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.2389658012
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.4095183329
Short name T542
Test name
Test status
Simulation time 87931321 ps
CPU time 1.29 seconds
Started Jul 09 05:09:25 PM PDT 24
Finished Jul 09 05:09:27 PM PDT 24
Peak memory 208616 kb
Host smart-f4bc5b7e-8d87-42ff-a05b-a37374a1b060
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095183329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.4095183329
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.3242882471
Short name T259
Test name
Test status
Simulation time 256136012 ps
CPU time 10.26 seconds
Started Jul 09 05:09:18 PM PDT 24
Finished Jul 09 05:09:29 PM PDT 24
Peak memory 217752 kb
Host smart-5f0d5d28-02c8-4083-ab4b-96c35f93e969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242882471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.3242882471
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.1331870442
Short name T707
Test name
Test status
Simulation time 141806362 ps
CPU time 3.08 seconds
Started Jul 09 05:09:25 PM PDT 24
Finished Jul 09 05:09:30 PM PDT 24
Peak memory 217660 kb
Host smart-9295daa3-c6f0-4460-89a1-042ad69cbac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331870442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.1331870442
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.191896548
Short name T634
Test name
Test status
Simulation time 1059909124 ps
CPU time 16.77 seconds
Started Jul 09 05:09:27 PM PDT 24
Finished Jul 09 05:09:45 PM PDT 24
Peak memory 225440 kb
Host smart-aac97626-cb25-46bd-8d0f-0e8b961a7e70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191896548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.191896548
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.3032656305
Short name T787
Test name
Test status
Simulation time 382952902 ps
CPU time 14.2 seconds
Started Jul 09 05:09:23 PM PDT 24
Finished Jul 09 05:09:38 PM PDT 24
Peak memory 225372 kb
Host smart-7a5d80b1-3085-4385-8032-e7dfcbe3123d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032656305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.3032656305
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.2243573712
Short name T332
Test name
Test status
Simulation time 549991785 ps
CPU time 11.13 seconds
Started Jul 09 05:09:22 PM PDT 24
Finished Jul 09 05:09:34 PM PDT 24
Peak memory 217628 kb
Host smart-aa9c7ce0-0f16-4251-bd00-bacd3398828f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243573712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
2243573712
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.625831230
Short name T839
Test name
Test status
Simulation time 2922029345 ps
CPU time 15.72 seconds
Started Jul 09 05:09:20 PM PDT 24
Finished Jul 09 05:09:36 PM PDT 24
Peak memory 225536 kb
Host smart-17ecf311-1da6-4bc1-a9f6-3735a053c3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625831230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.625831230
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.3636295880
Short name T284
Test name
Test status
Simulation time 66109225 ps
CPU time 3.23 seconds
Started Jul 09 05:09:21 PM PDT 24
Finished Jul 09 05:09:25 PM PDT 24
Peak memory 217036 kb
Host smart-01defcc1-f53f-46fd-9b40-64bd4b5a38b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636295880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.3636295880
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.793520700
Short name T536
Test name
Test status
Simulation time 1079377216 ps
CPU time 28.73 seconds
Started Jul 09 05:09:32 PM PDT 24
Finished Jul 09 05:10:01 PM PDT 24
Peak memory 250320 kb
Host smart-72b88a81-f264-4f39-945d-2b372a61e91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793520700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.793520700
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.786176952
Short name T323
Test name
Test status
Simulation time 91362864 ps
CPU time 6.38 seconds
Started Jul 09 05:09:33 PM PDT 24
Finished Jul 09 05:09:41 PM PDT 24
Peak memory 246536 kb
Host smart-cbc0f05a-7499-4257-94fb-e09e42a4b2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786176952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.786176952
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.2229803134
Short name T380
Test name
Test status
Simulation time 1598069833 ps
CPU time 37.01 seconds
Started Jul 09 05:09:23 PM PDT 24
Finished Jul 09 05:10:00 PM PDT 24
Peak memory 217196 kb
Host smart-c1a11ba3-a061-4488-9cd2-bb43feb35665
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229803134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.2229803134
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.1990368451
Short name T28
Test name
Test status
Simulation time 51153572 ps
CPU time 0.98 seconds
Started Jul 09 05:09:19 PM PDT 24
Finished Jul 09 05:09:20 PM PDT 24
Peak memory 208328 kb
Host smart-ecbf76e8-9036-44b7-8a92-1002773463d4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990368451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.1990368451
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.1413735043
Short name T242
Test name
Test status
Simulation time 118138239 ps
CPU time 0.9 seconds
Started Jul 09 05:07:38 PM PDT 24
Finished Jul 09 05:07:39 PM PDT 24
Peak memory 208272 kb
Host smart-42235f20-31dd-423c-b0c2-667519c48f71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413735043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.1413735043
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.3820949744
Short name T458
Test name
Test status
Simulation time 72228865 ps
CPU time 0.92 seconds
Started Jul 09 05:07:32 PM PDT 24
Finished Jul 09 05:07:34 PM PDT 24
Peak memory 208312 kb
Host smart-e4b18a74-41f7-4c27-b715-9bf5b6ec4712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820949744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.3820949744
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.3174336013
Short name T822
Test name
Test status
Simulation time 5686005944 ps
CPU time 12.29 seconds
Started Jul 09 05:07:33 PM PDT 24
Finished Jul 09 05:07:45 PM PDT 24
Peak memory 225528 kb
Host smart-2172f092-8c3f-4488-8f17-aaf9f3524639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174336013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.3174336013
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.1384234139
Short name T661
Test name
Test status
Simulation time 1166674874 ps
CPU time 7.61 seconds
Started Jul 09 05:07:32 PM PDT 24
Finished Jul 09 05:07:40 PM PDT 24
Peak memory 217044 kb
Host smart-74f23ef7-137e-4d51-af2b-b1e8c03dd597
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384234139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.1384234139
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.1595359011
Short name T481
Test name
Test status
Simulation time 4950254555 ps
CPU time 38.06 seconds
Started Jul 09 05:07:34 PM PDT 24
Finished Jul 09 05:08:12 PM PDT 24
Peak memory 217976 kb
Host smart-30ca57e7-c66b-4e61-857a-5f2c40e4e0a9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595359011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.1595359011
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.3457829906
Short name T843
Test name
Test status
Simulation time 548434719 ps
CPU time 6.42 seconds
Started Jul 09 05:07:35 PM PDT 24
Finished Jul 09 05:07:42 PM PDT 24
Peak memory 217096 kb
Host smart-d5986e06-44a2-43b2-8476-95d28dcc023d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457829906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.3
457829906
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.3329556898
Short name T379
Test name
Test status
Simulation time 1755244712 ps
CPU time 9.87 seconds
Started Jul 09 05:07:37 PM PDT 24
Finished Jul 09 05:07:48 PM PDT 24
Peak memory 217664 kb
Host smart-1068c18e-c901-444e-97a1-b3d9cb6c40b7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329556898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.3329556898
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.34537512
Short name T479
Test name
Test status
Simulation time 9298241349 ps
CPU time 12.43 seconds
Started Jul 09 05:07:37 PM PDT 24
Finished Jul 09 05:07:51 PM PDT 24
Peak memory 216996 kb
Host smart-30ef563a-7d32-4147-b15d-1a0ea5a284bf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34537512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_r
egwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jt
ag_regwen_during_op.34537512
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.1065623865
Short name T394
Test name
Test status
Simulation time 210335114 ps
CPU time 6.91 seconds
Started Jul 09 05:07:33 PM PDT 24
Finished Jul 09 05:07:40 PM PDT 24
Peak memory 217056 kb
Host smart-7b6de30c-d65a-4519-97f5-bb603a1bb11c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065623865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
1065623865
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.4230457764
Short name T667
Test name
Test status
Simulation time 6242571093 ps
CPU time 63.63 seconds
Started Jul 09 05:07:37 PM PDT 24
Finished Jul 09 05:08:42 PM PDT 24
Peak memory 283128 kb
Host smart-3fce6968-dc55-4011-8ad2-e1128df383f3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230457764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.4230457764
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.572295839
Short name T825
Test name
Test status
Simulation time 235175736 ps
CPU time 3.39 seconds
Started Jul 09 05:07:31 PM PDT 24
Finished Jul 09 05:07:35 PM PDT 24
Peak memory 217580 kb
Host smart-38e3594a-9588-4083-9540-be566894acd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572295839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.572295839
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.3305211696
Short name T77
Test name
Test status
Simulation time 352712572 ps
CPU time 20.69 seconds
Started Jul 09 05:07:33 PM PDT 24
Finished Jul 09 05:07:54 PM PDT 24
Peak memory 214280 kb
Host smart-1d7dedd0-8f1f-47da-a960-b4eebd9ed273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305211696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.3305211696
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.1708482125
Short name T53
Test name
Test status
Simulation time 110934225 ps
CPU time 27.25 seconds
Started Jul 09 05:07:36 PM PDT 24
Finished Jul 09 05:08:04 PM PDT 24
Peak memory 267140 kb
Host smart-ad7a672b-9952-4c6b-9714-23b37dd111c5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708482125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.1708482125
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.2517780298
Short name T765
Test name
Test status
Simulation time 1526234560 ps
CPU time 15.7 seconds
Started Jul 09 05:07:37 PM PDT 24
Finished Jul 09 05:07:53 PM PDT 24
Peak memory 218300 kb
Host smart-4fc08995-e7f6-4a2f-95cc-21871e478113
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517780298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.2517780298
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.737986237
Short name T688
Test name
Test status
Simulation time 3728465492 ps
CPU time 9.26 seconds
Started Jul 09 05:07:38 PM PDT 24
Finished Jul 09 05:07:48 PM PDT 24
Peak memory 225464 kb
Host smart-beeddb2d-96ca-49d1-8fec-80345fa54ea2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737986237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_dig
est.737986237
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.2398175148
Short name T331
Test name
Test status
Simulation time 825157942 ps
CPU time 9.09 seconds
Started Jul 09 05:07:46 PM PDT 24
Finished Jul 09 05:07:56 PM PDT 24
Peak memory 225348 kb
Host smart-5fe75046-193a-4d0d-a994-60d747dd4eb6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398175148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.2
398175148
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.546162863
Short name T722
Test name
Test status
Simulation time 421465754 ps
CPU time 7.18 seconds
Started Jul 09 05:07:34 PM PDT 24
Finished Jul 09 05:07:41 PM PDT 24
Peak memory 224148 kb
Host smart-fb485f9c-d7e5-4380-9a0b-d6ce62b736da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546162863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.546162863
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.2777199514
Short name T75
Test name
Test status
Simulation time 209426695 ps
CPU time 3.17 seconds
Started Jul 09 05:07:29 PM PDT 24
Finished Jul 09 05:07:32 PM PDT 24
Peak memory 217128 kb
Host smart-5ab94193-9950-4475-bdf4-ce993442c26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777199514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.2777199514
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.2348380298
Short name T251
Test name
Test status
Simulation time 949808611 ps
CPU time 27.52 seconds
Started Jul 09 05:07:29 PM PDT 24
Finished Jul 09 05:07:57 PM PDT 24
Peak memory 250328 kb
Host smart-afe0147a-db17-46c7-930c-7abe0741f523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348380298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.2348380298
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.1987229324
Short name T388
Test name
Test status
Simulation time 102217296 ps
CPU time 6.8 seconds
Started Jul 09 05:07:29 PM PDT 24
Finished Jul 09 05:07:36 PM PDT 24
Peak memory 249832 kb
Host smart-d9e86802-ee2a-4e01-9f21-3dd1ecb99625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987229324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.1987229324
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.1042092820
Short name T501
Test name
Test status
Simulation time 1143484136 ps
CPU time 22.32 seconds
Started Jul 09 05:07:46 PM PDT 24
Finished Jul 09 05:08:09 PM PDT 24
Peak memory 237364 kb
Host smart-10c25d0f-b0ce-412f-805e-efa8b88be4b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042092820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.1042092820
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.4177466170
Short name T134
Test name
Test status
Simulation time 350298668714 ps
CPU time 370.19 seconds
Started Jul 09 05:07:39 PM PDT 24
Finished Jul 09 05:13:49 PM PDT 24
Peak memory 404904 kb
Host smart-59daf9a5-f837-409b-adaf-6743f0c89ad8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4177466170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all_with_rand_reset.4177466170
Directory /workspace/3.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1484477038
Short name T486
Test name
Test status
Simulation time 14295119 ps
CPU time 1.03 seconds
Started Jul 09 05:07:32 PM PDT 24
Finished Jul 09 05:07:33 PM PDT 24
Peak memory 208416 kb
Host smart-40ea19d0-e910-4be7-ade4-92116d7c066f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484477038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.1484477038
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.4149553969
Short name T603
Test name
Test status
Simulation time 198118371 ps
CPU time 0.9 seconds
Started Jul 09 05:09:26 PM PDT 24
Finished Jul 09 05:09:28 PM PDT 24
Peak memory 208404 kb
Host smart-015e6457-2d49-4920-aab7-c29d3a00d7bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149553969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.4149553969
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.884247026
Short name T321
Test name
Test status
Simulation time 347336048 ps
CPU time 16.17 seconds
Started Jul 09 05:09:22 PM PDT 24
Finished Jul 09 05:09:39 PM PDT 24
Peak memory 225524 kb
Host smart-2be52151-38dc-4b57-8f9b-6f4f95a4557a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884247026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.884247026
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.238844816
Short name T163
Test name
Test status
Simulation time 979931644 ps
CPU time 13.23 seconds
Started Jul 09 05:09:34 PM PDT 24
Finished Jul 09 05:09:48 PM PDT 24
Peak memory 217096 kb
Host smart-4516d97e-1003-4283-827f-d077b7a104c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238844816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.238844816
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.3706003175
Short name T571
Test name
Test status
Simulation time 297701420 ps
CPU time 2.59 seconds
Started Jul 09 05:09:24 PM PDT 24
Finished Jul 09 05:09:27 PM PDT 24
Peak memory 221752 kb
Host smart-627e023e-41c8-4348-9577-a785984416b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706003175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.3706003175
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.3344155434
Short name T748
Test name
Test status
Simulation time 2861316522 ps
CPU time 18.11 seconds
Started Jul 09 05:09:25 PM PDT 24
Finished Jul 09 05:09:44 PM PDT 24
Peak memory 225520 kb
Host smart-94f78f18-1964-46b5-81f1-a8626fdd8b5f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344155434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.3344155434
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.3510745962
Short name T287
Test name
Test status
Simulation time 240651254 ps
CPU time 10.27 seconds
Started Jul 09 05:09:27 PM PDT 24
Finished Jul 09 05:09:39 PM PDT 24
Peak memory 225368 kb
Host smart-8b943c5f-6a10-4d46-807f-46c72062e680
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510745962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.3510745962
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.1874844251
Short name T348
Test name
Test status
Simulation time 569532027 ps
CPU time 12.12 seconds
Started Jul 09 05:09:24 PM PDT 24
Finished Jul 09 05:09:37 PM PDT 24
Peak memory 225468 kb
Host smart-bd9105db-99e1-4d8c-b85a-5bcbd8598941
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874844251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
1874844251
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.2347441431
Short name T498
Test name
Test status
Simulation time 358330175 ps
CPU time 13.94 seconds
Started Jul 09 05:09:25 PM PDT 24
Finished Jul 09 05:09:41 PM PDT 24
Peak memory 217596 kb
Host smart-a5838a17-4c65-410b-be1a-26b3c83e6f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347441431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.2347441431
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.27735141
Short name T648
Test name
Test status
Simulation time 643773519 ps
CPU time 3.9 seconds
Started Jul 09 05:09:23 PM PDT 24
Finished Jul 09 05:09:28 PM PDT 24
Peak memory 217088 kb
Host smart-9c24d001-05cb-4592-a63d-4319ff31322c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27735141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.27735141
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.1236298411
Short name T759
Test name
Test status
Simulation time 364033200 ps
CPU time 30.81 seconds
Started Jul 09 05:09:26 PM PDT 24
Finished Jul 09 05:09:59 PM PDT 24
Peak memory 250388 kb
Host smart-383e51c2-298b-4637-a209-d716c581d19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236298411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.1236298411
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.1284111109
Short name T569
Test name
Test status
Simulation time 124306981 ps
CPU time 7.51 seconds
Started Jul 09 05:09:26 PM PDT 24
Finished Jul 09 05:09:35 PM PDT 24
Peak memory 250388 kb
Host smart-c0e8debb-7a40-41d6-861b-23645a52563f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284111109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.1284111109
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.1435851195
Short name T353
Test name
Test status
Simulation time 937110042 ps
CPU time 54.71 seconds
Started Jul 09 05:09:27 PM PDT 24
Finished Jul 09 05:10:23 PM PDT 24
Peak memory 250404 kb
Host smart-47fd0386-1c6b-471b-a756-5146d57708b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435851195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.1435851195
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.1729640559
Short name T298
Test name
Test status
Simulation time 41522459 ps
CPU time 0.95 seconds
Started Jul 09 05:09:23 PM PDT 24
Finished Jul 09 05:09:25 PM PDT 24
Peak memory 211264 kb
Host smart-ba6ce7f2-b6c9-4771-9775-8baea886e6b4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729640559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.1729640559
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.291176673
Short name T322
Test name
Test status
Simulation time 15548135 ps
CPU time 1.04 seconds
Started Jul 09 05:09:29 PM PDT 24
Finished Jul 09 05:09:31 PM PDT 24
Peak memory 208476 kb
Host smart-522041f5-0322-496d-913c-e10088d1c47b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291176673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.291176673
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.1219110795
Short name T800
Test name
Test status
Simulation time 4612770025 ps
CPU time 13.93 seconds
Started Jul 09 05:09:27 PM PDT 24
Finished Jul 09 05:09:43 PM PDT 24
Peak memory 225460 kb
Host smart-535a8b1e-b4d4-446c-8198-8a8036164541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219110795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.1219110795
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.725554175
Short name T162
Test name
Test status
Simulation time 803632838 ps
CPU time 17.91 seconds
Started Jul 09 05:09:26 PM PDT 24
Finished Jul 09 05:09:46 PM PDT 24
Peak memory 217108 kb
Host smart-523d1f8d-cfff-48ed-a7ed-50e235dbac08
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725554175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.725554175
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.3642757145
Short name T218
Test name
Test status
Simulation time 77759657 ps
CPU time 4.12 seconds
Started Jul 09 05:09:27 PM PDT 24
Finished Jul 09 05:09:33 PM PDT 24
Peak memory 221808 kb
Host smart-94bdbe65-b2f0-4ba0-bebc-6d67b652a6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642757145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.3642757145
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.2200286518
Short name T727
Test name
Test status
Simulation time 370002251 ps
CPU time 8.62 seconds
Started Jul 09 05:09:26 PM PDT 24
Finished Jul 09 05:09:37 PM PDT 24
Peak memory 217880 kb
Host smart-079b5162-12d7-47d9-9904-c633b639c1eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200286518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.2200286518
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.1219639624
Short name T511
Test name
Test status
Simulation time 769322784 ps
CPU time 27.18 seconds
Started Jul 09 05:09:28 PM PDT 24
Finished Jul 09 05:09:56 PM PDT 24
Peak memory 225344 kb
Host smart-4307cc5e-0c13-4409-8508-42203189dcb4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219639624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.1219639624
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.1216986707
Short name T827
Test name
Test status
Simulation time 1210975692 ps
CPU time 13.72 seconds
Started Jul 09 05:09:27 PM PDT 24
Finished Jul 09 05:09:42 PM PDT 24
Peak memory 217600 kb
Host smart-55f74664-db54-4643-bac5-47a027c9e6ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216986707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
1216986707
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.3957903434
Short name T48
Test name
Test status
Simulation time 1482058073 ps
CPU time 9.67 seconds
Started Jul 09 05:09:27 PM PDT 24
Finished Jul 09 05:09:39 PM PDT 24
Peak memory 225452 kb
Host smart-c35511d0-5167-4eae-9930-a28e9c61f3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957903434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.3957903434
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.3619789337
Short name T376
Test name
Test status
Simulation time 27093778 ps
CPU time 1.05 seconds
Started Jul 09 05:09:28 PM PDT 24
Finished Jul 09 05:09:30 PM PDT 24
Peak memory 217036 kb
Host smart-57ffb2fe-dfaa-40f2-a5f4-30313cb79466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619789337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.3619789337
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.1369873960
Short name T419
Test name
Test status
Simulation time 1491688241 ps
CPU time 22.28 seconds
Started Jul 09 05:09:27 PM PDT 24
Finished Jul 09 05:09:51 PM PDT 24
Peak memory 250444 kb
Host smart-3b06551b-2a87-4a36-94b6-2de5d39047a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369873960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.1369873960
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.2718664396
Short name T336
Test name
Test status
Simulation time 302007725 ps
CPU time 7.31 seconds
Started Jul 09 05:09:30 PM PDT 24
Finished Jul 09 05:09:38 PM PDT 24
Peak memory 249940 kb
Host smart-c6e04d7e-fc46-494c-8f03-91217c3a6e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718664396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.2718664396
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.455600869
Short name T767
Test name
Test status
Simulation time 2684934017 ps
CPU time 65.48 seconds
Started Jul 09 05:09:27 PM PDT 24
Finished Jul 09 05:10:35 PM PDT 24
Peak memory 251264 kb
Host smart-492e944b-41ec-440b-a7f3-084e522b9771
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455600869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.455600869
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.1780457880
Short name T534
Test name
Test status
Simulation time 14378912 ps
CPU time 1.19 seconds
Started Jul 09 05:09:26 PM PDT 24
Finished Jul 09 05:09:29 PM PDT 24
Peak memory 211236 kb
Host smart-f7a172db-7e50-4af8-84c2-7b4942143a69
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780457880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.1780457880
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.2541907718
Short name T578
Test name
Test status
Simulation time 33744262 ps
CPU time 1.12 seconds
Started Jul 09 05:09:33 PM PDT 24
Finished Jul 09 05:09:34 PM PDT 24
Peak memory 208412 kb
Host smart-c78a1ab5-8ab8-4ddc-8a4d-7d6ac025f024
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541907718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.2541907718
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.1895038784
Short name T276
Test name
Test status
Simulation time 2934442824 ps
CPU time 13.33 seconds
Started Jul 09 05:09:33 PM PDT 24
Finished Jul 09 05:09:47 PM PDT 24
Peak memory 217676 kb
Host smart-cf893329-ac6e-437c-ae63-0f2a8c8e6326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895038784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.1895038784
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.1675860750
Short name T25
Test name
Test status
Simulation time 358238842 ps
CPU time 3.14 seconds
Started Jul 09 05:09:37 PM PDT 24
Finished Jul 09 05:09:41 PM PDT 24
Peak memory 217112 kb
Host smart-fe38c3ff-af0b-4125-a553-2a9db9f38fa1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675860750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.1675860750
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.2301066745
Short name T633
Test name
Test status
Simulation time 340346399 ps
CPU time 3.16 seconds
Started Jul 09 05:09:33 PM PDT 24
Finished Jul 09 05:09:36 PM PDT 24
Peak memory 221808 kb
Host smart-efc9307a-3d0c-4306-b142-4f5b046f7ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301066745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.2301066745
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.637914377
Short name T677
Test name
Test status
Simulation time 1037365458 ps
CPU time 11.02 seconds
Started Jul 09 05:09:34 PM PDT 24
Finished Jul 09 05:09:46 PM PDT 24
Peak memory 218376 kb
Host smart-11b4ca29-a630-4511-b715-8eb091349c0e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637914377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.637914377
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.2728199361
Short name T746
Test name
Test status
Simulation time 795296699 ps
CPU time 8.67 seconds
Started Jul 09 05:09:34 PM PDT 24
Finished Jul 09 05:09:43 PM PDT 24
Peak memory 217600 kb
Host smart-4aec6c6c-ff0e-4f5a-aee3-fce7305dd6f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728199361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.2728199361
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.4037435994
Short name T725
Test name
Test status
Simulation time 257363913 ps
CPU time 9.34 seconds
Started Jul 09 05:09:47 PM PDT 24
Finished Jul 09 05:09:57 PM PDT 24
Peak memory 225392 kb
Host smart-141a1ea1-64db-4c30-955b-7a27e7ce3bfa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037435994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
4037435994
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.935354107
Short name T435
Test name
Test status
Simulation time 875470175 ps
CPU time 9.3 seconds
Started Jul 09 05:09:33 PM PDT 24
Finished Jul 09 05:09:43 PM PDT 24
Peak memory 224528 kb
Host smart-632269da-2866-424d-8da0-8f23f826e6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935354107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.935354107
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.501676384
Short name T59
Test name
Test status
Simulation time 47539466 ps
CPU time 2.42 seconds
Started Jul 09 05:09:27 PM PDT 24
Finished Jul 09 05:09:31 PM PDT 24
Peak memory 217068 kb
Host smart-4f4a1d28-438e-4a26-9f70-fcb4257a2b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501676384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.501676384
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.1591444879
Short name T586
Test name
Test status
Simulation time 283852232 ps
CPU time 25.94 seconds
Started Jul 09 05:09:34 PM PDT 24
Finished Jul 09 05:10:01 PM PDT 24
Peak memory 250496 kb
Host smart-b1ee601c-2c64-4ba5-ba37-17324ac84769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591444879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.1591444879
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.285857800
Short name T855
Test name
Test status
Simulation time 41691093 ps
CPU time 6.54 seconds
Started Jul 09 05:09:38 PM PDT 24
Finished Jul 09 05:09:45 PM PDT 24
Peak memory 249968 kb
Host smart-680bc6c5-c77d-491a-ac84-bbcb343bdace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285857800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.285857800
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.4224966371
Short name T38
Test name
Test status
Simulation time 9241214320 ps
CPU time 116.38 seconds
Started Jul 09 05:09:36 PM PDT 24
Finished Jul 09 05:11:33 PM PDT 24
Peak memory 255252 kb
Host smart-bef8e152-0719-4ec0-9cdb-54d89fdd4150
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224966371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.4224966371
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.4153653098
Short name T750
Test name
Test status
Simulation time 26517362693 ps
CPU time 495.09 seconds
Started Jul 09 05:09:35 PM PDT 24
Finished Jul 09 05:17:51 PM PDT 24
Peak memory 263912 kb
Host smart-9a36cf90-fecb-40db-b407-efc49905308b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4153653098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.4153653098
Directory /workspace/32.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.4292096983
Short name T306
Test name
Test status
Simulation time 11015588 ps
CPU time 0.92 seconds
Started Jul 09 05:09:33 PM PDT 24
Finished Jul 09 05:09:36 PM PDT 24
Peak memory 208340 kb
Host smart-1f3559b7-5ef6-42c3-8194-505a7af64ba8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292096983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.4292096983
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.1682339630
Short name T370
Test name
Test status
Simulation time 50411996 ps
CPU time 0.93 seconds
Started Jul 09 05:09:42 PM PDT 24
Finished Jul 09 05:09:44 PM PDT 24
Peak memory 208456 kb
Host smart-40d7b617-e5e6-4d67-9c79-8901365e4650
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682339630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.1682339630
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.3633007112
Short name T780
Test name
Test status
Simulation time 1261554300 ps
CPU time 11.85 seconds
Started Jul 09 05:09:35 PM PDT 24
Finished Jul 09 05:09:48 PM PDT 24
Peak memory 225552 kb
Host smart-db02af37-0abe-43b7-b9f4-9668e15007a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633007112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.3633007112
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.1962647347
Short name T400
Test name
Test status
Simulation time 2208967400 ps
CPU time 5.96 seconds
Started Jul 09 05:09:36 PM PDT 24
Finished Jul 09 05:09:43 PM PDT 24
Peak memory 216864 kb
Host smart-6e2123ba-1191-46b5-acb4-d26dee16bff4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962647347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.1962647347
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.221035594
Short name T148
Test name
Test status
Simulation time 49487500 ps
CPU time 2.11 seconds
Started Jul 09 05:09:41 PM PDT 24
Finished Jul 09 05:09:45 PM PDT 24
Peak memory 217704 kb
Host smart-54080566-998d-4af8-a611-08281b9b0d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221035594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.221035594
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.3431681422
Short name T424
Test name
Test status
Simulation time 748850635 ps
CPU time 27.54 seconds
Started Jul 09 05:09:36 PM PDT 24
Finished Jul 09 05:10:05 PM PDT 24
Peak memory 219392 kb
Host smart-899eff82-96ff-4818-81dd-72621fa0cf8a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431681422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.3431681422
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.2880695100
Short name T227
Test name
Test status
Simulation time 1415025468 ps
CPU time 13.73 seconds
Started Jul 09 05:09:37 PM PDT 24
Finished Jul 09 05:09:52 PM PDT 24
Peak memory 225460 kb
Host smart-a3d4ab29-e484-4c90-a342-ab5b5fc99e33
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880695100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.2880695100
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.3711491904
Short name T492
Test name
Test status
Simulation time 296145606 ps
CPU time 7.11 seconds
Started Jul 09 05:09:35 PM PDT 24
Finished Jul 09 05:09:43 PM PDT 24
Peak memory 217640 kb
Host smart-4d9e35f1-1dc7-4388-b78e-de0375862a2b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711491904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
3711491904
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.1617131486
Short name T853
Test name
Test status
Simulation time 581615624 ps
CPU time 7.96 seconds
Started Jul 09 05:09:34 PM PDT 24
Finished Jul 09 05:09:43 PM PDT 24
Peak memory 224360 kb
Host smart-6da4fa36-36cb-48c2-a576-4302780eae53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617131486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.1617131486
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.2586259931
Short name T67
Test name
Test status
Simulation time 54472791 ps
CPU time 1.03 seconds
Started Jul 09 05:09:33 PM PDT 24
Finished Jul 09 05:09:35 PM PDT 24
Peak memory 211684 kb
Host smart-5c85a606-28e2-4f72-9b22-04ad642a8ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586259931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.2586259931
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.2225969974
Short name T203
Test name
Test status
Simulation time 690843779 ps
CPU time 31.95 seconds
Started Jul 09 05:09:37 PM PDT 24
Finished Jul 09 05:10:10 PM PDT 24
Peak memory 250480 kb
Host smart-459a9067-266b-4bde-9994-72751564f42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225969974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.2225969974
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.898939031
Short name T147
Test name
Test status
Simulation time 185855044 ps
CPU time 7.97 seconds
Started Jul 09 05:09:36 PM PDT 24
Finished Jul 09 05:09:45 PM PDT 24
Peak memory 250408 kb
Host smart-8e45bacb-1684-4617-a44a-0e779385033d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898939031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.898939031
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.1643580987
Short name T237
Test name
Test status
Simulation time 24545269058 ps
CPU time 131.94 seconds
Started Jul 09 05:09:37 PM PDT 24
Finished Jul 09 05:11:50 PM PDT 24
Peak memory 283320 kb
Host smart-ed985e3f-c0ea-4fa3-a3fb-3a65da0ff8e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643580987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.1643580987
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.3167424155
Short name T138
Test name
Test status
Simulation time 23414748928 ps
CPU time 844.18 seconds
Started Jul 09 05:09:38 PM PDT 24
Finished Jul 09 05:23:43 PM PDT 24
Peak memory 314020 kb
Host smart-920c775d-c7a5-4f86-8acb-ca69f1bbadc9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3167424155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.3167424155
Directory /workspace/33.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.109505945
Short name T20
Test name
Test status
Simulation time 44936060 ps
CPU time 1.02 seconds
Started Jul 09 05:09:38 PM PDT 24
Finished Jul 09 05:09:40 PM PDT 24
Peak memory 211340 kb
Host smart-5d7a140b-1ef1-4c63-94ec-af8580a6778a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109505945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ct
rl_volatile_unlock_smoke.109505945
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.1997750749
Short name T637
Test name
Test status
Simulation time 17773277 ps
CPU time 0.92 seconds
Started Jul 09 05:09:39 PM PDT 24
Finished Jul 09 05:09:41 PM PDT 24
Peak memory 208408 kb
Host smart-458ade9d-07f8-4f34-94c3-b843f3493e5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997750749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.1997750749
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.3837278194
Short name T606
Test name
Test status
Simulation time 631140583 ps
CPU time 16.32 seconds
Started Jul 09 05:09:41 PM PDT 24
Finished Jul 09 05:09:59 PM PDT 24
Peak memory 217672 kb
Host smart-ef192ab8-7a7f-4823-b61e-df22102886ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837278194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.3837278194
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.4187199514
Short name T626
Test name
Test status
Simulation time 323526691 ps
CPU time 4.7 seconds
Started Jul 09 05:09:38 PM PDT 24
Finished Jul 09 05:09:44 PM PDT 24
Peak memory 216600 kb
Host smart-94c34af3-97de-4473-af66-1b3b1f7d9f45
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187199514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.4187199514
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.723380090
Short name T708
Test name
Test status
Simulation time 29203410 ps
CPU time 1.7 seconds
Started Jul 09 05:09:42 PM PDT 24
Finished Jul 09 05:09:44 PM PDT 24
Peak memory 217676 kb
Host smart-b113776b-2190-4a01-a203-ea4a20ad204f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723380090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.723380090
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.2798625743
Short name T757
Test name
Test status
Simulation time 368579418 ps
CPU time 16.67 seconds
Started Jul 09 05:09:37 PM PDT 24
Finished Jul 09 05:09:54 PM PDT 24
Peak memory 225504 kb
Host smart-987f5eab-061a-4996-8d8d-1139f6a74528
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798625743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.2798625743
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.643004177
Short name T470
Test name
Test status
Simulation time 1180124211 ps
CPU time 23.67 seconds
Started Jul 09 05:09:38 PM PDT 24
Finished Jul 09 05:10:03 PM PDT 24
Peak memory 225464 kb
Host smart-3a0c9031-2153-42d2-af86-898134773cc6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643004177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_di
gest.643004177
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.3508764499
Short name T436
Test name
Test status
Simulation time 332491567 ps
CPU time 9.94 seconds
Started Jul 09 05:09:40 PM PDT 24
Finished Jul 09 05:09:51 PM PDT 24
Peak memory 225380 kb
Host smart-b939709b-cc8e-4d3f-875f-5010a1c61a7e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508764499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
3508764499
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.4132126694
Short name T437
Test name
Test status
Simulation time 1940024580 ps
CPU time 9.04 seconds
Started Jul 09 05:09:40 PM PDT 24
Finished Jul 09 05:09:51 PM PDT 24
Peak memory 224188 kb
Host smart-ca9f42f5-1ce2-47b1-839f-24a9f5741c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132126694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.4132126694
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.4247410072
Short name T79
Test name
Test status
Simulation time 140091857 ps
CPU time 3.03 seconds
Started Jul 09 05:09:42 PM PDT 24
Finished Jul 09 05:09:46 PM PDT 24
Peak memory 217080 kb
Host smart-658227c0-a1fe-4652-9a7d-4b7ad803e704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247410072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.4247410072
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.725105655
Short name T247
Test name
Test status
Simulation time 729124828 ps
CPU time 33.53 seconds
Started Jul 09 05:09:36 PM PDT 24
Finished Jul 09 05:10:10 PM PDT 24
Peak memory 250396 kb
Host smart-664baaa2-e6ff-4995-bdfe-16d3d2336e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725105655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.725105655
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.4256199481
Short name T261
Test name
Test status
Simulation time 78009868 ps
CPU time 2.76 seconds
Started Jul 09 05:09:38 PM PDT 24
Finished Jul 09 05:09:42 PM PDT 24
Peak memory 221948 kb
Host smart-6a108bbe-f405-40b9-acd1-b4283a79b65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256199481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.4256199481
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.4004489846
Short name T531
Test name
Test status
Simulation time 48656296217 ps
CPU time 278.06 seconds
Started Jul 09 05:09:40 PM PDT 24
Finished Jul 09 05:14:19 PM PDT 24
Peak memory 275280 kb
Host smart-43dda12b-14a9-4bf5-b953-b53bf26ebb84
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004489846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.4004489846
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.2034182463
Short name T153
Test name
Test status
Simulation time 26229693131 ps
CPU time 733.83 seconds
Started Jul 09 05:09:40 PM PDT 24
Finished Jul 09 05:21:54 PM PDT 24
Peak memory 496432 kb
Host smart-ee506f82-33f4-4e0d-b0d9-c93cbb090260
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2034182463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.2034182463
Directory /workspace/34.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1064748863
Short name T779
Test name
Test status
Simulation time 12666432 ps
CPU time 0.96 seconds
Started Jul 09 05:09:40 PM PDT 24
Finished Jul 09 05:09:42 PM PDT 24
Peak memory 211252 kb
Host smart-5eda2135-0056-4b37-b4ff-bed272c298fe
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064748863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.1064748863
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.2684106633
Short name T330
Test name
Test status
Simulation time 81195848 ps
CPU time 1.2 seconds
Started Jul 09 05:09:44 PM PDT 24
Finished Jul 09 05:09:46 PM PDT 24
Peak memory 208412 kb
Host smart-66dfacd3-5feb-43aa-9008-f52ad0eb24bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684106633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.2684106633
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.4208810690
Short name T289
Test name
Test status
Simulation time 393400777 ps
CPU time 12.38 seconds
Started Jul 09 05:09:43 PM PDT 24
Finished Jul 09 05:09:56 PM PDT 24
Peak memory 217664 kb
Host smart-e0ff079e-85d3-48a9-ad28-b4ae6a26e0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208810690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.4208810690
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.471195208
Short name T464
Test name
Test status
Simulation time 5326387283 ps
CPU time 7.6 seconds
Started Jul 09 05:09:41 PM PDT 24
Finished Jul 09 05:09:50 PM PDT 24
Peak memory 217208 kb
Host smart-b2995c10-8364-4e5f-be52-92c4306a0d1a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471195208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.471195208
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.2456732127
Short name T738
Test name
Test status
Simulation time 998515906 ps
CPU time 6.46 seconds
Started Jul 09 05:09:40 PM PDT 24
Finished Jul 09 05:09:47 PM PDT 24
Peak memory 217696 kb
Host smart-a0b8847d-8e50-4c01-8b91-d979c518035e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456732127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.2456732127
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.2015277680
Short name T438
Test name
Test status
Simulation time 2467424380 ps
CPU time 13.61 seconds
Started Jul 09 05:09:40 PM PDT 24
Finished Jul 09 05:09:54 PM PDT 24
Peak memory 218432 kb
Host smart-c19bcd13-3302-44cc-af7c-5fa5f91bd6e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015277680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.2015277680
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.3952769045
Short name T583
Test name
Test status
Simulation time 577457696 ps
CPU time 12.43 seconds
Started Jul 09 05:09:39 PM PDT 24
Finished Jul 09 05:09:52 PM PDT 24
Peak memory 225348 kb
Host smart-948508dc-f14c-41c1-9f27-649cba09f874
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952769045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.3952769045
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.165362127
Short name T358
Test name
Test status
Simulation time 300795922 ps
CPU time 7.88 seconds
Started Jul 09 05:09:41 PM PDT 24
Finished Jul 09 05:09:50 PM PDT 24
Peak memory 217660 kb
Host smart-2b3cc8f5-38b3-4f99-b24e-a707e468dafa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165362127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.165362127
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.3242496841
Short name T845
Test name
Test status
Simulation time 693284176 ps
CPU time 8.52 seconds
Started Jul 09 05:09:42 PM PDT 24
Finished Jul 09 05:09:51 PM PDT 24
Peak memory 217796 kb
Host smart-1d0b0ee8-aeee-46c1-8e6c-cafa3ba56a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242496841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.3242496841
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.1177657906
Short name T590
Test name
Test status
Simulation time 93340376 ps
CPU time 1.63 seconds
Started Jul 09 05:09:40 PM PDT 24
Finished Jul 09 05:09:42 PM PDT 24
Peak memory 217172 kb
Host smart-aab5005a-f487-44a9-bbee-2f9b733593f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177657906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.1177657906
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.1183500664
Short name T704
Test name
Test status
Simulation time 326533792 ps
CPU time 22.23 seconds
Started Jul 09 05:09:40 PM PDT 24
Finished Jul 09 05:10:03 PM PDT 24
Peak memory 250556 kb
Host smart-4cba13f3-456e-424c-86d2-53122a304c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183500664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.1183500664
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.3006778255
Short name T597
Test name
Test status
Simulation time 63491093 ps
CPU time 3.59 seconds
Started Jul 09 05:09:39 PM PDT 24
Finished Jul 09 05:09:44 PM PDT 24
Peak memory 225828 kb
Host smart-27bd40fa-5bd1-4e16-a62f-e5a292bd5632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006778255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.3006778255
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.503731254
Short name T241
Test name
Test status
Simulation time 6017736646 ps
CPU time 109.33 seconds
Started Jul 09 05:09:40 PM PDT 24
Finished Jul 09 05:11:30 PM PDT 24
Peak memory 283160 kb
Host smart-4bf722ed-5209-404f-993b-84e382c4d433
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503731254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.503731254
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.3874292962
Short name T351
Test name
Test status
Simulation time 24117284 ps
CPU time 0.94 seconds
Started Jul 09 05:09:40 PM PDT 24
Finished Jul 09 05:09:42 PM PDT 24
Peak memory 208304 kb
Host smart-28163edd-e4ee-4895-94d2-a0991cfd58e2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874292962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.3874292962
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.1184834414
Short name T344
Test name
Test status
Simulation time 14982603 ps
CPU time 0.91 seconds
Started Jul 09 05:09:42 PM PDT 24
Finished Jul 09 05:09:44 PM PDT 24
Peak memory 208460 kb
Host smart-baf7cd4a-f3e0-4032-8a51-097ea2a7ced6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184834414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.1184834414
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.69397709
Short name T157
Test name
Test status
Simulation time 1030647508 ps
CPU time 8.49 seconds
Started Jul 09 05:09:44 PM PDT 24
Finished Jul 09 05:09:53 PM PDT 24
Peak memory 217736 kb
Host smart-639632fc-4e97-41f9-97c1-99fb7ab639c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69397709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.69397709
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.278722493
Short name T775
Test name
Test status
Simulation time 3261935366 ps
CPU time 18.01 seconds
Started Jul 09 05:09:45 PM PDT 24
Finished Jul 09 05:10:04 PM PDT 24
Peak memory 217100 kb
Host smart-b1bb531e-5d3c-4d60-bd45-0862ea963270
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278722493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.278722493
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.3376695610
Short name T352
Test name
Test status
Simulation time 165153635 ps
CPU time 2.56 seconds
Started Jul 09 05:09:42 PM PDT 24
Finished Jul 09 05:09:46 PM PDT 24
Peak memory 221640 kb
Host smart-cd94859c-14ef-4482-847e-520d4e4283b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376695610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.3376695610
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.4009815209
Short name T213
Test name
Test status
Simulation time 1466852946 ps
CPU time 11.36 seconds
Started Jul 09 05:09:45 PM PDT 24
Finished Jul 09 05:09:57 PM PDT 24
Peak memory 218252 kb
Host smart-d98e46c0-22e6-485b-8b16-e8b2f1d09c38
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009815209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.4009815209
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.3735755856
Short name T212
Test name
Test status
Simulation time 2650683073 ps
CPU time 13.62 seconds
Started Jul 09 05:09:49 PM PDT 24
Finished Jul 09 05:10:04 PM PDT 24
Peak memory 225372 kb
Host smart-945babd0-f0e2-4d89-a236-4f1327f6246b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735755856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.3735755856
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.3650391527
Short name T433
Test name
Test status
Simulation time 913281357 ps
CPU time 10.4 seconds
Started Jul 09 05:09:43 PM PDT 24
Finished Jul 09 05:09:55 PM PDT 24
Peak memory 217612 kb
Host smart-43fa2d66-def7-4cd7-bbbd-c7f9432edefb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650391527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
3650391527
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.1450402756
Short name T447
Test name
Test status
Simulation time 1722858047 ps
CPU time 10.13 seconds
Started Jul 09 05:09:48 PM PDT 24
Finished Jul 09 05:09:59 PM PDT 24
Peak memory 225552 kb
Host smart-4fd66710-a752-41a9-bcea-a7bd356a2a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450402756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.1450402756
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.3130417558
Short name T781
Test name
Test status
Simulation time 28558596 ps
CPU time 2.54 seconds
Started Jul 09 05:09:45 PM PDT 24
Finished Jul 09 05:09:48 PM PDT 24
Peak memory 223012 kb
Host smart-d4c6561e-bf29-4122-8eef-3ec5ed6765c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130417558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.3130417558
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.1924783662
Short name T62
Test name
Test status
Simulation time 140999077 ps
CPU time 17.89 seconds
Started Jul 09 05:09:49 PM PDT 24
Finished Jul 09 05:10:08 PM PDT 24
Peak memory 245932 kb
Host smart-99a3bb13-f051-437e-bc4c-707ba9874706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924783662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.1924783662
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.2313496436
Short name T199
Test name
Test status
Simulation time 111063246 ps
CPU time 6.68 seconds
Started Jul 09 05:09:43 PM PDT 24
Finished Jul 09 05:09:51 PM PDT 24
Peak memory 245956 kb
Host smart-c315f2ce-334a-4454-ae80-6ddc59051065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313496436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.2313496436
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.1486625423
Short name T71
Test name
Test status
Simulation time 7034248838 ps
CPU time 260.32 seconds
Started Jul 09 05:09:45 PM PDT 24
Finished Jul 09 05:14:06 PM PDT 24
Peak memory 251208 kb
Host smart-5f2210c7-2c47-48d6-9bea-a3ed120b2268
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486625423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.1486625423
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.3620762509
Short name T396
Test name
Test status
Simulation time 36770378 ps
CPU time 0.93 seconds
Started Jul 09 05:09:43 PM PDT 24
Finished Jul 09 05:09:45 PM PDT 24
Peak memory 208492 kb
Host smart-0559515c-7af8-4d18-8ed2-1ef42a4707cf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620762509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.3620762509
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.184687062
Short name T395
Test name
Test status
Simulation time 38598387 ps
CPU time 0.86 seconds
Started Jul 09 05:09:46 PM PDT 24
Finished Jul 09 05:09:48 PM PDT 24
Peak memory 208332 kb
Host smart-146c8a46-d49f-42e9-99de-5bc7539d5664
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184687062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.184687062
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.303944706
Short name T32
Test name
Test status
Simulation time 685000457 ps
CPU time 16.25 seconds
Started Jul 09 05:09:43 PM PDT 24
Finished Jul 09 05:10:00 PM PDT 24
Peak memory 217664 kb
Host smart-cbe06a49-67d4-4980-8c7c-c9d615e234c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303944706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.303944706
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.1845390160
Short name T694
Test name
Test status
Simulation time 1691201591 ps
CPU time 4.93 seconds
Started Jul 09 05:09:46 PM PDT 24
Finished Jul 09 05:09:52 PM PDT 24
Peak memory 216800 kb
Host smart-a772ed7c-2898-48a8-b0ce-578f5190fc88
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845390160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.1845390160
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.3691085410
Short name T864
Test name
Test status
Simulation time 44404113 ps
CPU time 2.56 seconds
Started Jul 09 05:09:44 PM PDT 24
Finished Jul 09 05:09:47 PM PDT 24
Peak memory 217596 kb
Host smart-81417b7c-e048-4f61-b6bf-bb79db4bb7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691085410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.3691085410
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.2580864333
Short name T58
Test name
Test status
Simulation time 484510465 ps
CPU time 11.93 seconds
Started Jul 09 05:09:48 PM PDT 24
Finished Jul 09 05:10:01 PM PDT 24
Peak memory 225460 kb
Host smart-8832d012-ab09-4abd-9807-51e1b2b6abe4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580864333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.2580864333
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.2681770875
Short name T401
Test name
Test status
Simulation time 2097732465 ps
CPU time 9.05 seconds
Started Jul 09 05:09:49 PM PDT 24
Finished Jul 09 05:09:59 PM PDT 24
Peak memory 225464 kb
Host smart-4dfc831a-bdb7-44a8-a08e-64bc8571fe93
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681770875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.2681770875
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.2540926916
Short name T808
Test name
Test status
Simulation time 481015100 ps
CPU time 8.55 seconds
Started Jul 09 05:09:46 PM PDT 24
Finished Jul 09 05:09:55 PM PDT 24
Peak memory 217568 kb
Host smart-8502eb81-3390-4bb9-938f-815a77521154
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540926916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
2540926916
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.3311598360
Short name T92
Test name
Test status
Simulation time 917193322 ps
CPU time 7.77 seconds
Started Jul 09 05:09:47 PM PDT 24
Finished Jul 09 05:09:56 PM PDT 24
Peak memory 217864 kb
Host smart-a7a5036b-7f6f-4810-b57e-d2188074a2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311598360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.3311598360
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.3238863474
Short name T601
Test name
Test status
Simulation time 42641756 ps
CPU time 1.7 seconds
Started Jul 09 05:09:45 PM PDT 24
Finished Jul 09 05:09:47 PM PDT 24
Peak memory 217128 kb
Host smart-06175583-5f79-4ac9-9eaf-dc57bc4fa276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238863474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.3238863474
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.3387424054
Short name T363
Test name
Test status
Simulation time 2860273382 ps
CPU time 29.57 seconds
Started Jul 09 05:09:44 PM PDT 24
Finished Jul 09 05:10:15 PM PDT 24
Peak memory 250524 kb
Host smart-5f04584e-eb64-492a-8246-165ad6236aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387424054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.3387424054
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.1186788694
Short name T737
Test name
Test status
Simulation time 66375783 ps
CPU time 6.39 seconds
Started Jul 09 05:09:41 PM PDT 24
Finished Jul 09 05:09:49 PM PDT 24
Peak memory 246456 kb
Host smart-757461d3-5e67-4e42-90e8-4ff7c176ea30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186788694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.1186788694
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.415861253
Short name T95
Test name
Test status
Simulation time 43923245226 ps
CPU time 444.74 seconds
Started Jul 09 05:09:46 PM PDT 24
Finished Jul 09 05:17:12 PM PDT 24
Peak memory 275348 kb
Host smart-e15165df-0b6b-45fd-8b5f-1e89d71f3ebb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415861253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.415861253
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.710788856
Short name T657
Test name
Test status
Simulation time 17131369471 ps
CPU time 360.87 seconds
Started Jul 09 05:09:46 PM PDT 24
Finished Jul 09 05:15:48 PM PDT 24
Peak memory 277408 kb
Host smart-fed31830-acb5-45c9-b342-133afc44f6d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=710788856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.710788856
Directory /workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.1908775705
Short name T445
Test name
Test status
Simulation time 43614158 ps
CPU time 1.13 seconds
Started Jul 09 05:09:42 PM PDT 24
Finished Jul 09 05:09:44 PM PDT 24
Peak memory 217252 kb
Host smart-054d28a1-ae70-41bb-bc20-7ea0b244f7bf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908775705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.1908775705
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.1214625684
Short name T367
Test name
Test status
Simulation time 51980393 ps
CPU time 1.18 seconds
Started Jul 09 05:09:52 PM PDT 24
Finished Jul 09 05:09:54 PM PDT 24
Peak memory 208464 kb
Host smart-36c8ea2f-fc26-4da8-939a-9b2b2b35dc64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214625684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.1214625684
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.3551077214
Short name T373
Test name
Test status
Simulation time 498393451 ps
CPU time 18.11 seconds
Started Jul 09 05:09:46 PM PDT 24
Finished Jul 09 05:10:06 PM PDT 24
Peak memory 217704 kb
Host smart-cfcdf5bb-0512-48c1-9251-1d2363840391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551077214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.3551077214
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.3425634095
Short name T378
Test name
Test status
Simulation time 33406940 ps
CPU time 1.17 seconds
Started Jul 09 05:09:46 PM PDT 24
Finished Jul 09 05:09:48 PM PDT 24
Peak memory 216428 kb
Host smart-abbf9313-1a8e-413d-ba7f-89c902c069ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425634095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.3425634095
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.2698831706
Short name T529
Test name
Test status
Simulation time 956276845 ps
CPU time 2.8 seconds
Started Jul 09 05:09:49 PM PDT 24
Finished Jul 09 05:09:53 PM PDT 24
Peak memory 217628 kb
Host smart-888d6b51-6396-4225-8c87-aad662e20033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698831706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.2698831706
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.145193617
Short name T495
Test name
Test status
Simulation time 2075479779 ps
CPU time 13.16 seconds
Started Jul 09 05:09:49 PM PDT 24
Finished Jul 09 05:10:02 PM PDT 24
Peak memory 225428 kb
Host smart-04640a79-1919-4873-bf39-df0911a37642
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145193617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.145193617
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.3823698196
Short name T769
Test name
Test status
Simulation time 658051062 ps
CPU time 11.39 seconds
Started Jul 09 05:09:46 PM PDT 24
Finished Jul 09 05:09:59 PM PDT 24
Peak memory 225332 kb
Host smart-9fc423a8-bb22-49fa-b356-a23f30145134
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823698196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.3823698196
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.3556904035
Short name T849
Test name
Test status
Simulation time 301622910 ps
CPU time 10.21 seconds
Started Jul 09 05:09:46 PM PDT 24
Finished Jul 09 05:09:57 PM PDT 24
Peak memory 217644 kb
Host smart-73c067bc-085c-4511-a9c5-dc5df8e9aedb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556904035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
3556904035
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.2633052343
Short name T49
Test name
Test status
Simulation time 287177210 ps
CPU time 8.37 seconds
Started Jul 09 05:09:45 PM PDT 24
Finished Jul 09 05:09:55 PM PDT 24
Peak memory 217732 kb
Host smart-114b84fe-dbd5-4151-ab3e-dc0bbebbca7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633052343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.2633052343
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.222382261
Short name T305
Test name
Test status
Simulation time 37067824 ps
CPU time 2.37 seconds
Started Jul 09 05:09:51 PM PDT 24
Finished Jul 09 05:09:54 PM PDT 24
Peak memory 217148 kb
Host smart-5a60b70b-1c83-4ddb-bd6c-88140875537e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222382261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.222382261
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.1752218513
Short name T267
Test name
Test status
Simulation time 145267711 ps
CPU time 16.44 seconds
Started Jul 09 05:09:46 PM PDT 24
Finished Jul 09 05:10:04 PM PDT 24
Peak memory 250440 kb
Host smart-8f1259d0-d02f-4698-bb3a-940d29ac0416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752218513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.1752218513
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.2758850800
Short name T361
Test name
Test status
Simulation time 298721156 ps
CPU time 8.21 seconds
Started Jul 09 05:09:49 PM PDT 24
Finished Jul 09 05:09:58 PM PDT 24
Peak memory 250496 kb
Host smart-f0cc4a8e-102f-4b08-93b0-45f71534ac75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758850800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.2758850800
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.1718376741
Short name T428
Test name
Test status
Simulation time 4207066373 ps
CPU time 16.51 seconds
Started Jul 09 05:09:53 PM PDT 24
Finished Jul 09 05:10:11 PM PDT 24
Peak memory 250332 kb
Host smart-945de97a-05f9-4585-abb1-9984a8efe347
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718376741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.1718376741
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.1788387674
Short name T102
Test name
Test status
Simulation time 43025349343 ps
CPU time 1896.62 seconds
Started Jul 09 05:09:50 PM PDT 24
Finished Jul 09 05:41:28 PM PDT 24
Peak memory 496416 kb
Host smart-0cb95228-6f73-44b4-8163-7368bb021ff9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1788387674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.1788387674
Directory /workspace/38.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.939469668
Short name T546
Test name
Test status
Simulation time 15690203 ps
CPU time 1.13 seconds
Started Jul 09 05:09:47 PM PDT 24
Finished Jul 09 05:09:49 PM PDT 24
Peak memory 211288 kb
Host smart-89590350-0e05-437b-a35d-f11c9cff6e06
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939469668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ct
rl_volatile_unlock_smoke.939469668
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.3952481526
Short name T318
Test name
Test status
Simulation time 30263234 ps
CPU time 0.99 seconds
Started Jul 09 05:09:51 PM PDT 24
Finished Jul 09 05:09:53 PM PDT 24
Peak memory 208460 kb
Host smart-3a265311-468d-4786-9a8b-77bb6e7c27c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952481526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.3952481526
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.1370618571
Short name T238
Test name
Test status
Simulation time 2641555261 ps
CPU time 12.33 seconds
Started Jul 09 05:09:53 PM PDT 24
Finished Jul 09 05:10:06 PM PDT 24
Peak memory 225520 kb
Host smart-b9285623-e3dd-4adc-bbc9-15c2c718b6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370618571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.1370618571
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.2165238641
Short name T228
Test name
Test status
Simulation time 277070019 ps
CPU time 1.57 seconds
Started Jul 09 05:09:50 PM PDT 24
Finished Jul 09 05:09:53 PM PDT 24
Peak memory 217080 kb
Host smart-07cf3dbf-b7a5-433d-bb62-2a50ce8a31be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165238641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.2165238641
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.1762681884
Short name T265
Test name
Test status
Simulation time 44331172 ps
CPU time 2.7 seconds
Started Jul 09 05:09:53 PM PDT 24
Finished Jul 09 05:09:57 PM PDT 24
Peak memory 217664 kb
Host smart-d0d89061-6708-4542-a106-57effc9703ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762681884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.1762681884
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.3295669484
Short name T720
Test name
Test status
Simulation time 1359934254 ps
CPU time 14.59 seconds
Started Jul 09 05:09:58 PM PDT 24
Finished Jul 09 05:10:13 PM PDT 24
Peak memory 225524 kb
Host smart-b5a8a2e5-9b13-43d1-87b1-c70f1371c592
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295669484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.3295669484
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.2272435762
Short name T324
Test name
Test status
Simulation time 226153219 ps
CPU time 9.43 seconds
Started Jul 09 05:09:52 PM PDT 24
Finished Jul 09 05:10:03 PM PDT 24
Peak memory 225440 kb
Host smart-b27d870f-0805-4f04-b96a-7be413f0fe42
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272435762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.2272435762
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.4145373525
Short name T301
Test name
Test status
Simulation time 5350701574 ps
CPU time 9.45 seconds
Started Jul 09 05:09:51 PM PDT 24
Finished Jul 09 05:10:02 PM PDT 24
Peak memory 225480 kb
Host smart-c7cc025e-e023-42df-9b45-32c5bef64921
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145373525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
4145373525
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.1072685721
Short name T201
Test name
Test status
Simulation time 23594001 ps
CPU time 2.19 seconds
Started Jul 09 05:09:53 PM PDT 24
Finished Jul 09 05:09:56 PM PDT 24
Peak memory 213688 kb
Host smart-efcda197-0784-4d44-86e5-3ebfc9baf050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072685721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.1072685721
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.2560137671
Short name T209
Test name
Test status
Simulation time 798465622 ps
CPU time 22.85 seconds
Started Jul 09 05:09:53 PM PDT 24
Finished Jul 09 05:10:16 PM PDT 24
Peak memory 250452 kb
Host smart-75cbf24c-5888-4021-973b-715a074986ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560137671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.2560137671
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.2830496461
Short name T619
Test name
Test status
Simulation time 59375298 ps
CPU time 9.28 seconds
Started Jul 09 05:09:50 PM PDT 24
Finished Jul 09 05:10:01 PM PDT 24
Peak memory 250428 kb
Host smart-43bacaa6-5590-490a-b9f6-5699110c9315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830496461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.2830496461
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.3407063999
Short name T615
Test name
Test status
Simulation time 10977742914 ps
CPU time 374.14 seconds
Started Jul 09 05:09:51 PM PDT 24
Finished Jul 09 05:16:06 PM PDT 24
Peak memory 249884 kb
Host smart-8d66bb7f-aaa1-488e-897a-dc63a0fe4b67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407063999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.3407063999
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.3403236015
Short name T508
Test name
Test status
Simulation time 22254168 ps
CPU time 1.53 seconds
Started Jul 09 05:09:57 PM PDT 24
Finished Jul 09 05:09:59 PM PDT 24
Peak memory 217396 kb
Host smart-c232072f-e764-42b7-806d-a03de3242122
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403236015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.3403236015
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.34300083
Short name T742
Test name
Test status
Simulation time 17097593 ps
CPU time 1.12 seconds
Started Jul 09 05:07:45 PM PDT 24
Finished Jul 09 05:07:47 PM PDT 24
Peak memory 208412 kb
Host smart-4103944a-5eb9-4858-8163-951a1483ad6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34300083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.34300083
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.2624239744
Short name T699
Test name
Test status
Simulation time 264709312 ps
CPU time 13.59 seconds
Started Jul 09 05:07:36 PM PDT 24
Finished Jul 09 05:07:50 PM PDT 24
Peak memory 217620 kb
Host smart-d4199b3b-1728-4a60-9d07-662b0c2e6183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624239744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.2624239744
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.1604980292
Short name T735
Test name
Test status
Simulation time 477157183 ps
CPU time 6.04 seconds
Started Jul 09 05:07:44 PM PDT 24
Finished Jul 09 05:07:51 PM PDT 24
Peak memory 216608 kb
Host smart-298aa534-3257-4eab-9a1e-7720f1f90189
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604980292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.1604980292
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.2870400799
Short name T402
Test name
Test status
Simulation time 2089556984 ps
CPU time 41.74 seconds
Started Jul 09 05:07:43 PM PDT 24
Finished Jul 09 05:08:26 PM PDT 24
Peak memory 218000 kb
Host smart-119cac65-01a5-440d-9069-d91e985c191b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870400799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.2870400799
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.3043924909
Short name T145
Test name
Test status
Simulation time 2021780182 ps
CPU time 13.05 seconds
Started Jul 09 05:07:43 PM PDT 24
Finished Jul 09 05:07:57 PM PDT 24
Peak memory 217092 kb
Host smart-1162cb30-c672-498d-a061-b6d33dfebd4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043924909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.3
043924909
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.2211883816
Short name T326
Test name
Test status
Simulation time 1518918149 ps
CPU time 13.42 seconds
Started Jul 09 05:07:42 PM PDT 24
Finished Jul 09 05:07:56 PM PDT 24
Peak memory 223712 kb
Host smart-d3ba24bd-723e-4108-bc6f-183eddebf113
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211883816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.2211883816
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.1651237940
Short name T198
Test name
Test status
Simulation time 2353547015 ps
CPU time 17.9 seconds
Started Jul 09 05:07:41 PM PDT 24
Finished Jul 09 05:07:59 PM PDT 24
Peak memory 217004 kb
Host smart-790e6d95-4c2a-458b-b7e7-a2cad1760f2c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651237940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.1651237940
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.1033552433
Short name T502
Test name
Test status
Simulation time 347780119 ps
CPU time 2.32 seconds
Started Jul 09 05:07:41 PM PDT 24
Finished Jul 09 05:07:44 PM PDT 24
Peak memory 217008 kb
Host smart-b9ba2e5f-1d7a-4820-a515-3709fd8ed228
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033552433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
1033552433
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.1980069852
Short name T684
Test name
Test status
Simulation time 4157598770 ps
CPU time 30.92 seconds
Started Jul 09 05:07:41 PM PDT 24
Finished Jul 09 05:08:13 PM PDT 24
Peak memory 267228 kb
Host smart-a502c0f5-9d37-4012-b17f-3d108bb77a70
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980069852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.1980069852
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.2779234076
Short name T836
Test name
Test status
Simulation time 1815765464 ps
CPU time 18.4 seconds
Started Jul 09 05:07:42 PM PDT 24
Finished Jul 09 05:08:02 PM PDT 24
Peak memory 250176 kb
Host smart-7be67d99-124c-45de-9f90-ceaabc6b85bb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779234076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.2779234076
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.4067928271
Short name T497
Test name
Test status
Simulation time 407614692 ps
CPU time 3.47 seconds
Started Jul 09 05:07:38 PM PDT 24
Finished Jul 09 05:07:42 PM PDT 24
Peak memory 217696 kb
Host smart-0427f8fa-4db2-4b8a-a2cd-9d4e5db75480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067928271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.4067928271
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.2154205597
Short name T88
Test name
Test status
Simulation time 1206120118 ps
CPU time 9.5 seconds
Started Jul 09 05:07:41 PM PDT 24
Finished Jul 09 05:07:51 PM PDT 24
Peak memory 217084 kb
Host smart-30c59dd2-92d2-429e-8049-d75dae893a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154205597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.2154205597
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.3843004518
Short name T94
Test name
Test status
Simulation time 1098770988 ps
CPU time 37.51 seconds
Started Jul 09 05:07:45 PM PDT 24
Finished Jul 09 05:08:23 PM PDT 24
Peak memory 268524 kb
Host smart-8e53c832-e025-45fe-9cc0-7822172248fd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843004518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.3843004518
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.116292114
Short name T42
Test name
Test status
Simulation time 524936922 ps
CPU time 12.07 seconds
Started Jul 09 05:07:43 PM PDT 24
Finished Jul 09 05:07:56 PM PDT 24
Peak memory 218328 kb
Host smart-3feb058c-64c8-4375-96ba-adb8b9630e3f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116292114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.116292114
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.4049952253
Short name T522
Test name
Test status
Simulation time 2990334263 ps
CPU time 15.11 seconds
Started Jul 09 05:07:43 PM PDT 24
Finished Jul 09 05:07:59 PM PDT 24
Peak memory 225488 kb
Host smart-97d35ace-0a38-4f4a-b582-d1580c781f7c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049952253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.4049952253
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.4224893996
Short name T678
Test name
Test status
Simulation time 314770589 ps
CPU time 10.64 seconds
Started Jul 09 05:07:40 PM PDT 24
Finished Jul 09 05:07:51 PM PDT 24
Peak memory 217600 kb
Host smart-64f23033-cbb2-42c4-a5d3-aa7a77c991ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224893996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.4
224893996
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.2568874784
Short name T285
Test name
Test status
Simulation time 247911926 ps
CPU time 9.55 seconds
Started Jul 09 05:07:37 PM PDT 24
Finished Jul 09 05:07:47 PM PDT 24
Peak memory 225532 kb
Host smart-8d93e693-a309-4544-a6ee-ab97349d69dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568874784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.2568874784
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.66966429
Short name T262
Test name
Test status
Simulation time 35421411 ps
CPU time 1.33 seconds
Started Jul 09 05:07:36 PM PDT 24
Finished Jul 09 05:07:38 PM PDT 24
Peak memory 217208 kb
Host smart-c94feec2-9100-45d4-bcb8-4a9dffea36c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66966429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.66966429
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.1738051909
Short name T519
Test name
Test status
Simulation time 1515415671 ps
CPU time 22.7 seconds
Started Jul 09 05:07:37 PM PDT 24
Finished Jul 09 05:08:00 PM PDT 24
Peak memory 250440 kb
Host smart-6078d54a-544b-41ef-ac1f-b27e06c0a14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738051909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.1738051909
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.526263850
Short name T526
Test name
Test status
Simulation time 61996315 ps
CPU time 8.84 seconds
Started Jul 09 05:07:41 PM PDT 24
Finished Jul 09 05:07:51 PM PDT 24
Peak memory 250356 kb
Host smart-2f2892a4-39cf-41f7-afc4-be08357acff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526263850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.526263850
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.2807920181
Short name T273
Test name
Test status
Simulation time 2418097995 ps
CPU time 74.17 seconds
Started Jul 09 05:07:43 PM PDT 24
Finished Jul 09 05:08:58 PM PDT 24
Peak memory 226248 kb
Host smart-4d0c716b-c9d3-41da-9559-b8033e3fc1b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807920181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.2807920181
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.2015020087
Short name T450
Test name
Test status
Simulation time 19358029 ps
CPU time 1.34 seconds
Started Jul 09 05:07:41 PM PDT 24
Finished Jul 09 05:07:43 PM PDT 24
Peak memory 217128 kb
Host smart-6741b7bc-c837-45da-b7e9-6704da1b131f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015020087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.2015020087
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.586423970
Short name T768
Test name
Test status
Simulation time 41020119 ps
CPU time 0.81 seconds
Started Jul 09 05:09:58 PM PDT 24
Finished Jul 09 05:10:00 PM PDT 24
Peak memory 208296 kb
Host smart-a2c27a93-94d4-4b97-8a94-6f2d41c2e427
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586423970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.586423970
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.795754000
Short name T39
Test name
Test status
Simulation time 672402677 ps
CPU time 14.53 seconds
Started Jul 09 05:09:58 PM PDT 24
Finished Jul 09 05:10:13 PM PDT 24
Peak memory 217680 kb
Host smart-5c597b41-cf34-429b-88ac-049ed6cdefa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795754000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.795754000
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.4171911908
Short name T27
Test name
Test status
Simulation time 509340527 ps
CPU time 3.66 seconds
Started Jul 09 05:09:57 PM PDT 24
Finished Jul 09 05:10:02 PM PDT 24
Peak memory 217140 kb
Host smart-4fef8e9a-63a4-4e78-b5ff-a29c24c3f197
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171911908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.4171911908
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.2312265233
Short name T418
Test name
Test status
Simulation time 135785541 ps
CPU time 1.94 seconds
Started Jul 09 05:10:00 PM PDT 24
Finished Jul 09 05:10:03 PM PDT 24
Peak memory 217600 kb
Host smart-5b4b601f-e74f-4377-bb5e-ec14f4fb5f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312265233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.2312265233
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.3027068068
Short name T831
Test name
Test status
Simulation time 1324862518 ps
CPU time 8.26 seconds
Started Jul 09 05:09:56 PM PDT 24
Finished Jul 09 05:10:05 PM PDT 24
Peak memory 225388 kb
Host smart-6fac88d8-7dbb-47cb-81db-98557d74999d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027068068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.3027068068
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.2617322413
Short name T713
Test name
Test status
Simulation time 448023517 ps
CPU time 9.94 seconds
Started Jul 09 05:09:58 PM PDT 24
Finished Jul 09 05:10:09 PM PDT 24
Peak memory 225392 kb
Host smart-81da66e7-623f-48af-b3fd-4818be2cb72a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617322413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
2617322413
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.1011208319
Short name T552
Test name
Test status
Simulation time 954352071 ps
CPU time 10.98 seconds
Started Jul 09 05:09:54 PM PDT 24
Finished Jul 09 05:10:06 PM PDT 24
Peak memory 225436 kb
Host smart-0e101c99-fbd7-49b9-88d1-45afd9f4cdcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011208319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.1011208319
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.2408084661
Short name T225
Test name
Test status
Simulation time 225088349 ps
CPU time 2.05 seconds
Started Jul 09 05:09:53 PM PDT 24
Finished Jul 09 05:09:56 PM PDT 24
Peak memory 217116 kb
Host smart-c2b675b7-2bba-44e4-a5fe-034ae935a5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408084661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.2408084661
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.4123506732
Short name T382
Test name
Test status
Simulation time 587689614 ps
CPU time 21.68 seconds
Started Jul 09 05:09:53 PM PDT 24
Finished Jul 09 05:10:15 PM PDT 24
Peak memory 250448 kb
Host smart-0a369e23-b132-4fe2-b372-8cd9d518b39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123506732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.4123506732
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.2715628875
Short name T195
Test name
Test status
Simulation time 446484344 ps
CPU time 3.92 seconds
Started Jul 09 05:09:52 PM PDT 24
Finished Jul 09 05:09:57 PM PDT 24
Peak memory 222040 kb
Host smart-0ca2afd0-adb2-458d-8619-bf0d8235cddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715628875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.2715628875
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.3494130778
Short name T233
Test name
Test status
Simulation time 5760745794 ps
CPU time 105.6 seconds
Started Jul 09 05:09:55 PM PDT 24
Finished Jul 09 05:11:42 PM PDT 24
Peak memory 275272 kb
Host smart-ba0e1a0d-f1d8-48fd-83f6-8c226ab32462
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494130778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.3494130778
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.2033607734
Short name T596
Test name
Test status
Simulation time 12116862 ps
CPU time 0.95 seconds
Started Jul 09 05:09:51 PM PDT 24
Finished Jul 09 05:09:53 PM PDT 24
Peak memory 208520 kb
Host smart-6732e6ef-3ce0-4a9b-b9bd-556ec7de678c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033607734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.2033607734
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.1291153273
Short name T816
Test name
Test status
Simulation time 63416047 ps
CPU time 1.07 seconds
Started Jul 09 05:10:01 PM PDT 24
Finished Jul 09 05:10:03 PM PDT 24
Peak memory 208464 kb
Host smart-d6f7322b-e3a8-47a9-999c-b3fb86a759ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291153273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.1291153273
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.3948819529
Short name T422
Test name
Test status
Simulation time 827049769 ps
CPU time 14.11 seconds
Started Jul 09 05:09:59 PM PDT 24
Finished Jul 09 05:10:14 PM PDT 24
Peak memory 217680 kb
Host smart-7de7286b-879c-4f3f-a406-0461db84beb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948819529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.3948819529
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.110026048
Short name T703
Test name
Test status
Simulation time 2281561103 ps
CPU time 15.24 seconds
Started Jul 09 05:09:58 PM PDT 24
Finished Jul 09 05:10:14 PM PDT 24
Peak memory 217136 kb
Host smart-711f7444-570a-47ee-bf8c-8e977f0299dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110026048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.110026048
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.1092131938
Short name T423
Test name
Test status
Simulation time 36063615 ps
CPU time 2.05 seconds
Started Jul 09 05:10:00 PM PDT 24
Finished Jul 09 05:10:03 PM PDT 24
Peak memory 217616 kb
Host smart-5627122b-1bc2-464e-bc3a-56af582140c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092131938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.1092131938
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.326985311
Short name T192
Test name
Test status
Simulation time 1319341375 ps
CPU time 17.09 seconds
Started Jul 09 05:10:00 PM PDT 24
Finished Jul 09 05:10:18 PM PDT 24
Peak memory 218312 kb
Host smart-e328ed25-899a-40bc-bb51-3b3c3f485da9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326985311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.326985311
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.2072172400
Short name T429
Test name
Test status
Simulation time 536699318 ps
CPU time 7.51 seconds
Started Jul 09 05:10:01 PM PDT 24
Finished Jul 09 05:10:10 PM PDT 24
Peak memory 225444 kb
Host smart-8fc02ca7-2536-4481-b746-a0e8aba37d8b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072172400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.2072172400
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.2953075542
Short name T582
Test name
Test status
Simulation time 251003589 ps
CPU time 9.96 seconds
Started Jul 09 05:09:59 PM PDT 24
Finished Jul 09 05:10:10 PM PDT 24
Peak memory 217612 kb
Host smart-6c4cb109-b148-4b14-bfea-08274f32e4ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953075542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
2953075542
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.3085503138
Short name T46
Test name
Test status
Simulation time 775984308 ps
CPU time 7.66 seconds
Started Jul 09 05:10:02 PM PDT 24
Finished Jul 09 05:10:11 PM PDT 24
Peak memory 225416 kb
Host smart-9930a242-2784-4049-a321-c385cb49b487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085503138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.3085503138
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.3155237397
Short name T377
Test name
Test status
Simulation time 292767530 ps
CPU time 3.08 seconds
Started Jul 09 05:09:55 PM PDT 24
Finished Jul 09 05:09:59 PM PDT 24
Peak memory 217104 kb
Host smart-8810fe87-bbba-44c8-8048-752c54140289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155237397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.3155237397
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.1609697604
Short name T830
Test name
Test status
Simulation time 1209115191 ps
CPU time 28.12 seconds
Started Jul 09 05:09:55 PM PDT 24
Finished Jul 09 05:10:24 PM PDT 24
Peak memory 250412 kb
Host smart-108a3ba9-80b7-474f-96af-6995dc4d934c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609697604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.1609697604
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.1057794394
Short name T491
Test name
Test status
Simulation time 162205834 ps
CPU time 10.23 seconds
Started Jul 09 05:09:55 PM PDT 24
Finished Jul 09 05:10:06 PM PDT 24
Peak memory 250536 kb
Host smart-96788281-d01b-4f2a-82dc-bd48bc78799f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057794394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.1057794394
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.937758398
Short name T160
Test name
Test status
Simulation time 5973720319 ps
CPU time 124.34 seconds
Started Jul 09 05:09:58 PM PDT 24
Finished Jul 09 05:12:03 PM PDT 24
Peak memory 225688 kb
Host smart-ced9110c-b5f5-43e1-85ec-3c1fb1add9aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937758398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.937758398
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.1766180066
Short name T744
Test name
Test status
Simulation time 13779667 ps
CPU time 1.13 seconds
Started Jul 09 05:10:00 PM PDT 24
Finished Jul 09 05:10:03 PM PDT 24
Peak memory 211264 kb
Host smart-97d1538e-5fe5-46df-9fad-04bf8e937d0e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766180066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.1766180066
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.1125627214
Short name T527
Test name
Test status
Simulation time 21753141 ps
CPU time 0.86 seconds
Started Jul 09 05:10:01 PM PDT 24
Finished Jul 09 05:10:03 PM PDT 24
Peak memory 208316 kb
Host smart-adeae79f-0f9f-4245-9c02-95e9fa3a5e50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125627214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.1125627214
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.790417410
Short name T608
Test name
Test status
Simulation time 980635858 ps
CPU time 20.97 seconds
Started Jul 09 05:10:00 PM PDT 24
Finished Jul 09 05:10:22 PM PDT 24
Peak memory 225504 kb
Host smart-88c73415-d3fc-4dba-b7d5-5234299347e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790417410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.790417410
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.2258088308
Short name T347
Test name
Test status
Simulation time 281094020 ps
CPU time 2.38 seconds
Started Jul 09 05:10:02 PM PDT 24
Finished Jul 09 05:10:06 PM PDT 24
Peak memory 217004 kb
Host smart-71fdb3f6-55af-4404-abc9-a9885b0dd961
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258088308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.2258088308
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.2102180656
Short name T439
Test name
Test status
Simulation time 24021150 ps
CPU time 1.56 seconds
Started Jul 09 05:09:59 PM PDT 24
Finished Jul 09 05:10:01 PM PDT 24
Peak memory 217696 kb
Host smart-e52599fc-1e56-46d8-84c0-634e537b0dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102180656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.2102180656
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.1532487495
Short name T204
Test name
Test status
Simulation time 1602001204 ps
CPU time 15.56 seconds
Started Jul 09 05:10:00 PM PDT 24
Finished Jul 09 05:10:16 PM PDT 24
Peak memory 225324 kb
Host smart-4a4375de-53a0-48da-9457-9c7ef34a6f8a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532487495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.1532487495
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.2660218233
Short name T354
Test name
Test status
Simulation time 1246495647 ps
CPU time 7.53 seconds
Started Jul 09 05:09:58 PM PDT 24
Finished Jul 09 05:10:06 PM PDT 24
Peak memory 225428 kb
Host smart-70c7a842-ecb4-4d28-b53a-081c8b0184bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660218233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
2660218233
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.1993238768
Short name T335
Test name
Test status
Simulation time 55338723 ps
CPU time 1.18 seconds
Started Jul 09 05:09:59 PM PDT 24
Finished Jul 09 05:10:01 PM PDT 24
Peak memory 211716 kb
Host smart-78c1fb2b-7b17-4484-ba02-3aed51b380b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993238768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.1993238768
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.1280606766
Short name T632
Test name
Test status
Simulation time 1453640580 ps
CPU time 20.9 seconds
Started Jul 09 05:10:02 PM PDT 24
Finished Jul 09 05:10:23 PM PDT 24
Peak memory 244992 kb
Host smart-7c028ab7-8ab6-4072-8716-a2fb0fe9c298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280606766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.1280606766
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.1291949269
Short name T410
Test name
Test status
Simulation time 44955226 ps
CPU time 6.48 seconds
Started Jul 09 05:10:03 PM PDT 24
Finished Jul 09 05:10:11 PM PDT 24
Peak memory 246304 kb
Host smart-2fb50867-c94a-4e0f-9c9c-3c469b37deb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291949269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.1291949269
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.2594209316
Short name T66
Test name
Test status
Simulation time 115328870159 ps
CPU time 593.16 seconds
Started Jul 09 05:10:02 PM PDT 24
Finished Jul 09 05:19:57 PM PDT 24
Peak memory 310044 kb
Host smart-678c5547-b26a-4659-96f3-4b0af37ee19b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2594209316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.2594209316
Directory /workspace/42.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.910748577
Short name T557
Test name
Test status
Simulation time 52929053 ps
CPU time 0.93 seconds
Started Jul 09 05:09:59 PM PDT 24
Finished Jul 09 05:10:01 PM PDT 24
Peak memory 211300 kb
Host smart-07951ef3-883d-4b55-bb98-918087a972ac
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910748577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ct
rl_volatile_unlock_smoke.910748577
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.2399474235
Short name T749
Test name
Test status
Simulation time 55200938 ps
CPU time 0.94 seconds
Started Jul 09 05:10:08 PM PDT 24
Finished Jul 09 05:10:10 PM PDT 24
Peak memory 208376 kb
Host smart-263b4dad-26e3-44ab-b6ed-7cef765fed45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399474235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.2399474235
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.4157338755
Short name T516
Test name
Test status
Simulation time 230551525 ps
CPU time 12.46 seconds
Started Jul 09 05:10:03 PM PDT 24
Finished Jul 09 05:10:17 PM PDT 24
Peak memory 225468 kb
Host smart-d9285957-6eea-401b-bf8a-73bb8cbf4c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157338755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.4157338755
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.592478705
Short name T860
Test name
Test status
Simulation time 412489468 ps
CPU time 5.07 seconds
Started Jul 09 05:10:05 PM PDT 24
Finished Jul 09 05:10:11 PM PDT 24
Peak memory 216628 kb
Host smart-3a65e110-7e19-4972-bb0b-6ef13359e0b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592478705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.592478705
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.2392212551
Short name T281
Test name
Test status
Simulation time 42740412 ps
CPU time 1.55 seconds
Started Jul 09 05:10:09 PM PDT 24
Finished Jul 09 05:10:11 PM PDT 24
Peak memory 217680 kb
Host smart-62c8dc62-bb68-4cc1-8e7c-e32e57c3d6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392212551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.2392212551
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.1985854619
Short name T717
Test name
Test status
Simulation time 750491438 ps
CPU time 17.63 seconds
Started Jul 09 05:10:03 PM PDT 24
Finished Jul 09 05:10:22 PM PDT 24
Peak memory 218380 kb
Host smart-8e24d8b0-556b-421a-b9bd-548d596362f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985854619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.1985854619
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.1033496419
Short name T798
Test name
Test status
Simulation time 166961929 ps
CPU time 7.99 seconds
Started Jul 09 05:10:02 PM PDT 24
Finished Jul 09 05:10:12 PM PDT 24
Peak memory 225436 kb
Host smart-4e493e02-d893-4708-8248-c644093ca5d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033496419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.1033496419
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.2000092412
Short name T792
Test name
Test status
Simulation time 1375930341 ps
CPU time 11.38 seconds
Started Jul 09 05:10:02 PM PDT 24
Finished Jul 09 05:10:15 PM PDT 24
Peak memory 225408 kb
Host smart-54668ac2-069c-492f-ba33-6d385d8cf814
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000092412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
2000092412
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.2673449029
Short name T465
Test name
Test status
Simulation time 558719049 ps
CPU time 11.56 seconds
Started Jul 09 05:10:05 PM PDT 24
Finished Jul 09 05:10:17 PM PDT 24
Peak memory 225412 kb
Host smart-1132b2ed-ae64-4582-af8f-d964c863061d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673449029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.2673449029
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.2724672918
Short name T728
Test name
Test status
Simulation time 140804073 ps
CPU time 2.98 seconds
Started Jul 09 05:10:05 PM PDT 24
Finished Jul 09 05:10:09 PM PDT 24
Peak memory 214484 kb
Host smart-6a89f5cd-b1ec-4cdb-a653-34f6280b9847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724672918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.2724672918
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.2216047792
Short name T449
Test name
Test status
Simulation time 349137475 ps
CPU time 36.75 seconds
Started Jul 09 05:10:01 PM PDT 24
Finished Jul 09 05:10:39 PM PDT 24
Peak memory 250472 kb
Host smart-1942f1b2-176b-4add-9eb6-010e81faffe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216047792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.2216047792
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.3385120898
Short name T776
Test name
Test status
Simulation time 303414274 ps
CPU time 9.4 seconds
Started Jul 09 05:10:05 PM PDT 24
Finished Jul 09 05:10:15 PM PDT 24
Peak memory 250332 kb
Host smart-f9e5388f-d483-4e78-a8d6-61390eb67efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385120898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.3385120898
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.1927433681
Short name T641
Test name
Test status
Simulation time 25305244764 ps
CPU time 451.34 seconds
Started Jul 09 05:10:03 PM PDT 24
Finished Jul 09 05:17:36 PM PDT 24
Peak memory 258872 kb
Host smart-5d70469c-2c35-4f99-97d2-c27d186ad6f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927433681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.1927433681
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.3909586979
Short name T133
Test name
Test status
Simulation time 15084674434 ps
CPU time 300.68 seconds
Started Jul 09 05:10:07 PM PDT 24
Finished Jul 09 05:15:09 PM PDT 24
Peak memory 274708 kb
Host smart-73970b06-4d73-488e-9968-4d7e8e7432c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3909586979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.3909586979
Directory /workspace/43.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.3512145808
Short name T258
Test name
Test status
Simulation time 24829021 ps
CPU time 1.01 seconds
Started Jul 09 05:10:03 PM PDT 24
Finished Jul 09 05:10:05 PM PDT 24
Peak memory 208592 kb
Host smart-2b23f3ea-bdd3-4e61-a09f-f6e87847b289
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512145808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.3512145808
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.113085370
Short name T338
Test name
Test status
Simulation time 80124680 ps
CPU time 1.13 seconds
Started Jul 09 05:10:12 PM PDT 24
Finished Jul 09 05:10:14 PM PDT 24
Peak memory 208440 kb
Host smart-da001cea-b2fd-4041-b723-eb74e94e9867
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113085370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.113085370
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.2843450740
Short name T512
Test name
Test status
Simulation time 1000926158 ps
CPU time 14.72 seconds
Started Jul 09 05:10:07 PM PDT 24
Finished Jul 09 05:10:23 PM PDT 24
Peak memory 217732 kb
Host smart-13df6c0b-d7bb-4b8c-bf87-204d74b7dcb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843450740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.2843450740
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.1463382980
Short name T666
Test name
Test status
Simulation time 70090346 ps
CPU time 1.2 seconds
Started Jul 09 05:10:09 PM PDT 24
Finished Jul 09 05:10:11 PM PDT 24
Peak memory 217088 kb
Host smart-000ff1f2-b478-4022-91ff-7b70d568aff2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463382980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.1463382980
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.2737066696
Short name T846
Test name
Test status
Simulation time 21056520 ps
CPU time 1.73 seconds
Started Jul 09 05:10:07 PM PDT 24
Finished Jul 09 05:10:09 PM PDT 24
Peak memory 217660 kb
Host smart-8534c928-a303-49a8-9eba-1dc0aae8ae90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737066696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.2737066696
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.1831045866
Short name T826
Test name
Test status
Simulation time 430797794 ps
CPU time 13.77 seconds
Started Jul 09 05:10:06 PM PDT 24
Finished Jul 09 05:10:21 PM PDT 24
Peak memory 225524 kb
Host smart-e774d4dc-4de9-48d1-b078-29cba72f8113
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831045866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.1831045866
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.169982417
Short name T202
Test name
Test status
Simulation time 2554348837 ps
CPU time 13.31 seconds
Started Jul 09 05:10:10 PM PDT 24
Finished Jul 09 05:10:24 PM PDT 24
Peak memory 225396 kb
Host smart-64904959-240b-424b-9017-3b027d64b61b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169982417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_di
gest.169982417
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.3494137935
Short name T515
Test name
Test status
Simulation time 1315505921 ps
CPU time 11.5 seconds
Started Jul 09 05:10:07 PM PDT 24
Finished Jul 09 05:10:19 PM PDT 24
Peak memory 217524 kb
Host smart-ae45b060-c258-47aa-a210-dbb9fb680206
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494137935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
3494137935
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.1965131586
Short name T673
Test name
Test status
Simulation time 2740340509 ps
CPU time 11.86 seconds
Started Jul 09 05:10:08 PM PDT 24
Finished Jul 09 05:10:20 PM PDT 24
Peak memory 224876 kb
Host smart-f1a0ca7d-9f9d-4207-88cd-30aadc2d5107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965131586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.1965131586
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.2322084354
Short name T668
Test name
Test status
Simulation time 74506280 ps
CPU time 2.08 seconds
Started Jul 09 05:10:07 PM PDT 24
Finished Jul 09 05:10:10 PM PDT 24
Peak memory 217224 kb
Host smart-dd25de4e-ac9a-4012-9078-5ba454d55e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322084354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.2322084354
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.4162424757
Short name T687
Test name
Test status
Simulation time 201254083 ps
CPU time 20.32 seconds
Started Jul 09 05:10:08 PM PDT 24
Finished Jul 09 05:10:29 PM PDT 24
Peak memory 250416 kb
Host smart-8a11697e-e372-4800-a4e3-4e4f9737b670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162424757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.4162424757
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.1790336414
Short name T795
Test name
Test status
Simulation time 129767553 ps
CPU time 7.36 seconds
Started Jul 09 05:10:07 PM PDT 24
Finished Jul 09 05:10:15 PM PDT 24
Peak memory 250388 kb
Host smart-fc350f4a-a863-411b-b989-f09de43cf05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790336414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.1790336414
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.865039505
Short name T68
Test name
Test status
Simulation time 4001951378 ps
CPU time 130.44 seconds
Started Jul 09 05:10:17 PM PDT 24
Finished Jul 09 05:12:28 PM PDT 24
Peak memory 267792 kb
Host smart-abb6d921-1861-478e-b12e-3aca880f7a6e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865039505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.865039505
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.1489693261
Short name T152
Test name
Test status
Simulation time 71332639601 ps
CPU time 709.12 seconds
Started Jul 09 05:10:15 PM PDT 24
Finished Jul 09 05:22:05 PM PDT 24
Peak memory 275604 kb
Host smart-75e801d5-8f6f-44a3-9976-179313085b01
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1489693261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all_with_rand_reset.1489693261
Directory /workspace/44.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.2692501389
Short name T398
Test name
Test status
Simulation time 43309401 ps
CPU time 1.59 seconds
Started Jul 09 05:10:06 PM PDT 24
Finished Jul 09 05:10:08 PM PDT 24
Peak memory 217056 kb
Host smart-b450ef06-8522-4855-b344-66fa67d8ccfd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692501389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.2692501389
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.3004810363
Short name T607
Test name
Test status
Simulation time 13041288 ps
CPU time 0.85 seconds
Started Jul 09 05:10:16 PM PDT 24
Finished Jul 09 05:10:18 PM PDT 24
Peak memory 208284 kb
Host smart-8f20769d-b9a5-4fa2-a63e-823f77078eb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004810363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.3004810363
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.539005846
Short name T555
Test name
Test status
Simulation time 250049055 ps
CPU time 10.39 seconds
Started Jul 09 05:10:16 PM PDT 24
Finished Jul 09 05:10:27 PM PDT 24
Peak memory 217668 kb
Host smart-89931683-5744-4bdd-b6f6-6d7be233264c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539005846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.539005846
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.2299434549
Short name T461
Test name
Test status
Simulation time 3530159282 ps
CPU time 7.81 seconds
Started Jul 09 05:10:16 PM PDT 24
Finished Jul 09 05:10:25 PM PDT 24
Peak memory 217148 kb
Host smart-09c5b07a-dc11-4858-9424-58dc1b8dfebb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299434549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.2299434549
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.2135127121
Short name T793
Test name
Test status
Simulation time 56153534 ps
CPU time 1.98 seconds
Started Jul 09 05:10:13 PM PDT 24
Finished Jul 09 05:10:16 PM PDT 24
Peak memory 217620 kb
Host smart-419a8d44-ed23-4a1f-81f3-254b03eff5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135127121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.2135127121
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.3454841774
Short name T544
Test name
Test status
Simulation time 875599428 ps
CPU time 19.95 seconds
Started Jul 09 05:10:17 PM PDT 24
Finished Jul 09 05:10:37 PM PDT 24
Peak memory 218388 kb
Host smart-6a9eec98-9901-4cc2-b423-59a2c080d8bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454841774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.3454841774
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.1864869109
Short name T328
Test name
Test status
Simulation time 4047424526 ps
CPU time 15.66 seconds
Started Jul 09 05:10:10 PM PDT 24
Finished Jul 09 05:10:27 PM PDT 24
Peak memory 225528 kb
Host smart-0cc6e05e-106f-4d6c-88da-5e946eecab99
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864869109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.1864869109
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.3449273380
Short name T412
Test name
Test status
Simulation time 5364920883 ps
CPU time 8.22 seconds
Started Jul 09 05:10:13 PM PDT 24
Finished Jul 09 05:10:21 PM PDT 24
Peak memory 225492 kb
Host smart-e436bc0e-a37f-4e3d-af4d-f21549ac3f22
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449273380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
3449273380
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.20697386
Short name T832
Test name
Test status
Simulation time 404216989 ps
CPU time 14.9 seconds
Started Jul 09 05:10:12 PM PDT 24
Finished Jul 09 05:10:28 PM PDT 24
Peak memory 217720 kb
Host smart-81612ef4-7613-46d4-bfee-8525241ba680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20697386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.20697386
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.564568124
Short name T229
Test name
Test status
Simulation time 79993869 ps
CPU time 3.33 seconds
Started Jul 09 05:10:12 PM PDT 24
Finished Jul 09 05:10:15 PM PDT 24
Peak memory 214220 kb
Host smart-9bca4e3b-046b-4c4d-b9b8-dfb3d692dfcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564568124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.564568124
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.687694923
Short name T755
Test name
Test status
Simulation time 336625550 ps
CPU time 24.15 seconds
Started Jul 09 05:10:09 PM PDT 24
Finished Jul 09 05:10:34 PM PDT 24
Peak memory 244920 kb
Host smart-d5189c58-d3c4-4718-96b3-b409631f09da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687694923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.687694923
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.2611670902
Short name T250
Test name
Test status
Simulation time 158661861 ps
CPU time 3.06 seconds
Started Jul 09 05:10:13 PM PDT 24
Finished Jul 09 05:10:17 PM PDT 24
Peak memory 217572 kb
Host smart-06a7ac93-fb90-4903-9c46-1698b20115e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611670902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.2611670902
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.1759858485
Short name T343
Test name
Test status
Simulation time 22559713536 ps
CPU time 186.08 seconds
Started Jul 09 05:10:16 PM PDT 24
Finished Jul 09 05:13:23 PM PDT 24
Peak memory 420648 kb
Host smart-fa419b8a-dce6-41e6-9c05-972ffc3a68b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759858485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.1759858485
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.3242571850
Short name T541
Test name
Test status
Simulation time 25752632942 ps
CPU time 338.86 seconds
Started Jul 09 05:10:15 PM PDT 24
Finished Jul 09 05:15:54 PM PDT 24
Peak memory 421592 kb
Host smart-f318161a-6041-48a3-b778-1e0f34de3476
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3242571850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all_with_rand_reset.3242571850
Directory /workspace/45.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1919403212
Short name T293
Test name
Test status
Simulation time 30682468 ps
CPU time 0.82 seconds
Started Jul 09 05:10:14 PM PDT 24
Finished Jul 09 05:10:16 PM PDT 24
Peak memory 208236 kb
Host smart-888d9c11-676e-46da-9486-fe1516d7a0b0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919403212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.1919403212
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.870998417
Short name T271
Test name
Test status
Simulation time 13477445 ps
CPU time 1.01 seconds
Started Jul 09 05:10:16 PM PDT 24
Finished Jul 09 05:10:18 PM PDT 24
Peak memory 208408 kb
Host smart-3ec336e6-a761-42e2-b151-af47ff721f80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870998417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.870998417
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.1021520199
Short name T387
Test name
Test status
Simulation time 1642407539 ps
CPU time 18.55 seconds
Started Jul 09 05:10:18 PM PDT 24
Finished Jul 09 05:10:37 PM PDT 24
Peak memory 217660 kb
Host smart-3e6ae0ec-eeab-44b8-b9ed-b2b654e0900a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021520199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.1021520199
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.94482242
Short name T21
Test name
Test status
Simulation time 11257364615 ps
CPU time 31.59 seconds
Started Jul 09 05:10:17 PM PDT 24
Finished Jul 09 05:10:50 PM PDT 24
Peak memory 217096 kb
Host smart-7bde0826-2e89-407b-a8aa-804c47067fa2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94482242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.94482242
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.1506767926
Short name T815
Test name
Test status
Simulation time 401477058 ps
CPU time 3.43 seconds
Started Jul 09 05:10:15 PM PDT 24
Finished Jul 09 05:10:20 PM PDT 24
Peak memory 217656 kb
Host smart-241f487b-ffb2-4d56-85a3-8666c10c4bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506767926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.1506767926
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.2600680771
Short name T524
Test name
Test status
Simulation time 760205372 ps
CPU time 12.71 seconds
Started Jul 09 05:10:16 PM PDT 24
Finished Jul 09 05:10:30 PM PDT 24
Peak memory 217832 kb
Host smart-18f1dbf7-f596-4f5b-9740-40ed05f79d91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600680771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.2600680771
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.659587655
Short name T313
Test name
Test status
Simulation time 1449824487 ps
CPU time 11.99 seconds
Started Jul 09 05:10:16 PM PDT 24
Finished Jul 09 05:10:29 PM PDT 24
Peak memory 225468 kb
Host smart-a510916d-408d-42f4-af71-210986be008c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659587655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_di
gest.659587655
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.3732689339
Short name T724
Test name
Test status
Simulation time 265661838 ps
CPU time 6.32 seconds
Started Jul 09 05:10:17 PM PDT 24
Finished Jul 09 05:10:24 PM PDT 24
Peak memory 217588 kb
Host smart-5bdac39b-2565-43d7-a7ba-ffa456f6bf2e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732689339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
3732689339
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.3570217952
Short name T629
Test name
Test status
Simulation time 658445491 ps
CPU time 10.41 seconds
Started Jul 09 05:10:17 PM PDT 24
Finished Jul 09 05:10:28 PM PDT 24
Peak memory 225524 kb
Host smart-968aafd9-5230-44af-8608-fb251d3ea5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570217952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.3570217952
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.3283932163
Short name T553
Test name
Test status
Simulation time 1923836358 ps
CPU time 5.63 seconds
Started Jul 09 05:10:12 PM PDT 24
Finished Jul 09 05:10:18 PM PDT 24
Peak memory 217180 kb
Host smart-76be4e22-c61c-4a07-91c9-530060e8eafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283932163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.3283932163
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.1780798715
Short name T591
Test name
Test status
Simulation time 180376241 ps
CPU time 25.01 seconds
Started Jul 09 05:10:14 PM PDT 24
Finished Jul 09 05:10:40 PM PDT 24
Peak memory 250480 kb
Host smart-a6105abc-63b0-4c2b-89e9-a40d531bf5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780798715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.1780798715
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.1354745209
Short name T833
Test name
Test status
Simulation time 79410773 ps
CPU time 3 seconds
Started Jul 09 05:10:14 PM PDT 24
Finished Jul 09 05:10:18 PM PDT 24
Peak memory 225488 kb
Host smart-15e6efca-d69e-416f-85c2-7457c302d8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354745209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.1354745209
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.1390738374
Short name T98
Test name
Test status
Simulation time 12633302189 ps
CPU time 314.52 seconds
Started Jul 09 05:10:18 PM PDT 24
Finished Jul 09 05:15:33 PM PDT 24
Peak memory 421428 kb
Host smart-49cdb16a-eefd-45f3-bb4f-77856b0432b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390738374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.1390738374
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.1496195801
Short name T617
Test name
Test status
Simulation time 16787599 ps
CPU time 1.12 seconds
Started Jul 09 05:10:14 PM PDT 24
Finished Jul 09 05:10:15 PM PDT 24
Peak memory 211324 kb
Host smart-0ca13c13-aa70-4107-b28c-97929e2e2063
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496195801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.1496195801
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.2693700419
Short name T142
Test name
Test status
Simulation time 25421266 ps
CPU time 1.28 seconds
Started Jul 09 05:10:22 PM PDT 24
Finished Jul 09 05:10:25 PM PDT 24
Peak memory 208492 kb
Host smart-d20c0071-6f18-4683-b00f-abf6f14a620f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693700419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.2693700419
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.1870235786
Short name T558
Test name
Test status
Simulation time 989368047 ps
CPU time 13.32 seconds
Started Jul 09 05:10:20 PM PDT 24
Finished Jul 09 05:10:34 PM PDT 24
Peak memory 217732 kb
Host smart-225a55e6-3b2c-4064-b3f4-5edc149c550f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870235786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.1870235786
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.1469592814
Short name T572
Test name
Test status
Simulation time 716110538 ps
CPU time 7.81 seconds
Started Jul 09 05:10:22 PM PDT 24
Finished Jul 09 05:10:32 PM PDT 24
Peak memory 217076 kb
Host smart-a5b9fd6c-082b-40e9-96ed-71da417f4b37
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469592814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.1469592814
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.2474567213
Short name T786
Test name
Test status
Simulation time 89930370 ps
CPU time 2.18 seconds
Started Jul 09 05:10:24 PM PDT 24
Finished Jul 09 05:10:28 PM PDT 24
Peak memory 217672 kb
Host smart-874529c2-ed31-456a-be9b-45be828d38a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474567213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.2474567213
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.785019790
Short name T691
Test name
Test status
Simulation time 757368724 ps
CPU time 13.32 seconds
Started Jul 09 05:10:18 PM PDT 24
Finished Jul 09 05:10:32 PM PDT 24
Peak memory 225532 kb
Host smart-48d5eb98-7f65-42ff-aa3d-1da0d7448f1a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785019790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.785019790
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.4042019318
Short name T663
Test name
Test status
Simulation time 442601396 ps
CPU time 9.12 seconds
Started Jul 09 05:10:24 PM PDT 24
Finished Jul 09 05:10:34 PM PDT 24
Peak memory 225444 kb
Host smart-dadc52fa-a9d3-45ce-b5f4-c222c54e4352
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042019318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.4042019318
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.4008363510
Short name T584
Test name
Test status
Simulation time 277554844 ps
CPU time 7.56 seconds
Started Jul 09 05:10:23 PM PDT 24
Finished Jul 09 05:10:32 PM PDT 24
Peak memory 217616 kb
Host smart-85d0c5c1-e234-471a-a561-58b114f316b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008363510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
4008363510
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.573272478
Short name T190
Test name
Test status
Simulation time 333780721 ps
CPU time 9.18 seconds
Started Jul 09 05:10:20 PM PDT 24
Finished Jul 09 05:10:30 PM PDT 24
Peak memory 223852 kb
Host smart-2a5190fc-9cab-412f-a5eb-d905dadb55db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573272478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.573272478
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.3178868442
Short name T513
Test name
Test status
Simulation time 239960331 ps
CPU time 1.45 seconds
Started Jul 09 05:10:16 PM PDT 24
Finished Jul 09 05:10:18 PM PDT 24
Peak memory 217216 kb
Host smart-7eb4c2f2-e8a2-4eef-8f0f-64a125b8f3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178868442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.3178868442
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.929882396
Short name T478
Test name
Test status
Simulation time 661343392 ps
CPU time 31.44 seconds
Started Jul 09 05:10:17 PM PDT 24
Finished Jul 09 05:10:50 PM PDT 24
Peak memory 250372 kb
Host smart-05a0f9f8-1f5a-4db9-8225-2dd37fae2ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929882396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.929882396
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.67412863
Short name T518
Test name
Test status
Simulation time 52227758 ps
CPU time 5.95 seconds
Started Jul 09 05:10:16 PM PDT 24
Finished Jul 09 05:10:23 PM PDT 24
Peak memory 245740 kb
Host smart-a71f018e-277d-4a96-8ce5-511825e0ce8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67412863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.67412863
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.4272240780
Short name T87
Test name
Test status
Simulation time 3727334269 ps
CPU time 96.41 seconds
Started Jul 09 05:10:24 PM PDT 24
Finished Jul 09 05:12:02 PM PDT 24
Peak memory 250248 kb
Host smart-0a0f9b65-ccbb-4bd0-b2b9-5f9ea12807f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272240780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.4272240780
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.551412137
Short name T764
Test name
Test status
Simulation time 14597648 ps
CPU time 1.02 seconds
Started Jul 09 05:10:15 PM PDT 24
Finished Jul 09 05:10:17 PM PDT 24
Peak memory 208364 kb
Host smart-ef82870b-22bf-4fb1-95bb-203e9cddaa40
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551412137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ct
rl_volatile_unlock_smoke.551412137
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.3829116444
Short name T350
Test name
Test status
Simulation time 39503290 ps
CPU time 1.05 seconds
Started Jul 09 05:10:22 PM PDT 24
Finished Jul 09 05:10:24 PM PDT 24
Peak memory 208352 kb
Host smart-241df9b1-be56-4937-9e6f-e78ee020c0c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829116444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.3829116444
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.3591789253
Short name T716
Test name
Test status
Simulation time 1363563005 ps
CPU time 10.35 seconds
Started Jul 09 05:10:22 PM PDT 24
Finished Jul 09 05:10:33 PM PDT 24
Peak memory 225460 kb
Host smart-ca622524-8f8a-4d96-9851-a8f5f135a085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591789253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.3591789253
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.1322555277
Short name T24
Test name
Test status
Simulation time 1011562192 ps
CPU time 13.47 seconds
Started Jul 09 05:10:19 PM PDT 24
Finished Jul 09 05:10:33 PM PDT 24
Peak memory 216832 kb
Host smart-7856b4f4-e706-46f0-aa77-173a23169428
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322555277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.1322555277
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.2482017073
Short name T702
Test name
Test status
Simulation time 48765962 ps
CPU time 1.78 seconds
Started Jul 09 05:10:23 PM PDT 24
Finished Jul 09 05:10:26 PM PDT 24
Peak memory 217660 kb
Host smart-d4a87c98-3822-4644-a2e0-eb08003f90a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482017073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.2482017073
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.1748880040
Short name T308
Test name
Test status
Simulation time 1988431276 ps
CPU time 11.61 seconds
Started Jul 09 05:10:21 PM PDT 24
Finished Jul 09 05:10:34 PM PDT 24
Peak memory 225332 kb
Host smart-8180a1b1-ea41-4931-a6d1-d2d8f65bf9ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748880040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.1748880040
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.3814558024
Short name T734
Test name
Test status
Simulation time 1419140490 ps
CPU time 13.07 seconds
Started Jul 09 05:10:20 PM PDT 24
Finished Jul 09 05:10:34 PM PDT 24
Peak memory 217560 kb
Host smart-99868065-2df7-4970-82fc-44fc4b547872
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814558024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
3814558024
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.2454876576
Short name T650
Test name
Test status
Simulation time 209262940 ps
CPU time 6.72 seconds
Started Jul 09 05:10:23 PM PDT 24
Finished Jul 09 05:10:32 PM PDT 24
Peak memory 225468 kb
Host smart-2f69149d-004a-49a7-8ab3-85af17d7d544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454876576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.2454876576
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.471858709
Short name T211
Test name
Test status
Simulation time 68379942 ps
CPU time 1.6 seconds
Started Jul 09 05:10:19 PM PDT 24
Finished Jul 09 05:10:22 PM PDT 24
Peak memory 213360 kb
Host smart-aa75b7f8-d7f1-4aa2-bc53-593323b6599f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471858709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.471858709
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.1926180169
Short name T97
Test name
Test status
Simulation time 1108393821 ps
CPU time 27.12 seconds
Started Jul 09 05:10:20 PM PDT 24
Finished Jul 09 05:10:47 PM PDT 24
Peak memory 250476 kb
Host smart-fc5d1c36-0209-4e4d-9db7-a4c79f43623a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926180169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.1926180169
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.2837872077
Short name T551
Test name
Test status
Simulation time 76802803 ps
CPU time 6.91 seconds
Started Jul 09 05:10:19 PM PDT 24
Finished Jul 09 05:10:27 PM PDT 24
Peak memory 249688 kb
Host smart-7664bfb5-5cb0-436d-bb80-1e7352729234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837872077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.2837872077
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.3692203275
Short name T257
Test name
Test status
Simulation time 711024434 ps
CPU time 10.87 seconds
Started Jul 09 05:10:20 PM PDT 24
Finished Jul 09 05:10:32 PM PDT 24
Peak memory 250348 kb
Host smart-28d5e53f-d842-4d96-8b7e-776a8b841041
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692203275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.3692203275
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.2804939345
Short name T29
Test name
Test status
Simulation time 27482652 ps
CPU time 0.81 seconds
Started Jul 09 05:10:24 PM PDT 24
Finished Jul 09 05:10:26 PM PDT 24
Peak memory 208272 kb
Host smart-1f12fabd-b907-4acb-ad9f-f68f65ff382e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804939345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.2804939345
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.2531320104
Short name T567
Test name
Test status
Simulation time 25838027 ps
CPU time 1.3 seconds
Started Jul 09 05:10:22 PM PDT 24
Finished Jul 09 05:10:24 PM PDT 24
Peak memory 208592 kb
Host smart-c13aa582-8817-443f-b8f4-641b2619738b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531320104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.2531320104
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.698161720
Short name T556
Test name
Test status
Simulation time 502165525 ps
CPU time 10.52 seconds
Started Jul 09 05:10:24 PM PDT 24
Finished Jul 09 05:10:36 PM PDT 24
Peak memory 217636 kb
Host smart-dbb8b9df-bbe2-42ab-8436-09f98c258691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698161720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.698161720
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.230290186
Short name T482
Test name
Test status
Simulation time 274587039 ps
CPU time 6.21 seconds
Started Jul 09 05:10:23 PM PDT 24
Finished Jul 09 05:10:31 PM PDT 24
Peak memory 217148 kb
Host smart-a2f1bb8c-8682-4de5-8015-77b45d37435f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230290186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.230290186
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.4164487723
Short name T503
Test name
Test status
Simulation time 131636740 ps
CPU time 3.43 seconds
Started Jul 09 05:10:23 PM PDT 24
Finished Jul 09 05:10:28 PM PDT 24
Peak memory 217708 kb
Host smart-6545b438-c8d0-466f-a3d3-da152ce50018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164487723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.4164487723
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.1576850075
Short name T309
Test name
Test status
Simulation time 395217186 ps
CPU time 15.77 seconds
Started Jul 09 05:10:22 PM PDT 24
Finished Jul 09 05:10:39 PM PDT 24
Peak memory 225516 kb
Host smart-453b066b-7f35-4934-b1a5-c5e7d5f18bdc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576850075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.1576850075
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.773167351
Short name T561
Test name
Test status
Simulation time 837011164 ps
CPU time 12.32 seconds
Started Jul 09 05:10:23 PM PDT 24
Finished Jul 09 05:10:37 PM PDT 24
Peak memory 225392 kb
Host smart-1112232f-0034-48c3-9d00-a1aadb9ae5f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773167351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_di
gest.773167351
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.591687976
Short name T760
Test name
Test status
Simulation time 4979784008 ps
CPU time 8.69 seconds
Started Jul 09 05:10:23 PM PDT 24
Finished Jul 09 05:10:33 PM PDT 24
Peak memory 217720 kb
Host smart-b848f05a-4c74-4d4b-9eee-49d73479f2cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591687976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.591687976
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.4175269206
Short name T564
Test name
Test status
Simulation time 537474357 ps
CPU time 15.82 seconds
Started Jul 09 05:10:23 PM PDT 24
Finished Jul 09 05:10:41 PM PDT 24
Peak memory 225492 kb
Host smart-0537df76-7e8f-4fb0-9f82-c42164487f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175269206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.4175269206
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.3175853618
Short name T221
Test name
Test status
Simulation time 29124955 ps
CPU time 1.57 seconds
Started Jul 09 05:10:20 PM PDT 24
Finished Jul 09 05:10:23 PM PDT 24
Peak memory 213360 kb
Host smart-23cc0782-dbe4-4feb-902d-b6d7e9dfd0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175853618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.3175853618
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.1674190871
Short name T761
Test name
Test status
Simulation time 2412886789 ps
CPU time 30.63 seconds
Started Jul 09 05:10:24 PM PDT 24
Finished Jul 09 05:10:56 PM PDT 24
Peak memory 250524 kb
Host smart-96523b48-ab69-4ba6-a9a9-7b2fa8dbc3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674190871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.1674190871
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.551553869
Short name T806
Test name
Test status
Simulation time 348584950 ps
CPU time 9.64 seconds
Started Jul 09 05:10:23 PM PDT 24
Finished Jul 09 05:10:34 PM PDT 24
Peak memory 250360 kb
Host smart-c86cddf6-4a4c-4408-a8c6-43f6e0769ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551553869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.551553869
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.2406430471
Short name T797
Test name
Test status
Simulation time 9535531939 ps
CPU time 74.94 seconds
Started Jul 09 05:10:22 PM PDT 24
Finished Jul 09 05:11:39 PM PDT 24
Peak memory 219568 kb
Host smart-2f817468-ce5c-44d3-b5aa-4c6a209911be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406430471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.2406430471
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.3735265912
Short name T136
Test name
Test status
Simulation time 18493717810 ps
CPU time 314.65 seconds
Started Jul 09 05:10:22 PM PDT 24
Finished Jul 09 05:15:38 PM PDT 24
Peak memory 277612 kb
Host smart-bb4c894a-cbe4-4d23-ad57-6d332eb18a0f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3735265912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all_with_rand_reset.3735265912
Directory /workspace/49.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.3210512779
Short name T411
Test name
Test status
Simulation time 24833771 ps
CPU time 0.93 seconds
Started Jul 09 05:10:19 PM PDT 24
Finished Jul 09 05:10:21 PM PDT 24
Peak memory 208304 kb
Host smart-e4b8cd6d-f2e5-43a7-a8c8-78a137254d79
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210512779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.3210512779
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.3969870336
Short name T813
Test name
Test status
Simulation time 17541348 ps
CPU time 0.91 seconds
Started Jul 09 05:07:48 PM PDT 24
Finished Jul 09 05:07:50 PM PDT 24
Peak memory 208344 kb
Host smart-2ab171d4-f197-4eef-bace-8411f24bedd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969870336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.3969870336
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.1655111768
Short name T850
Test name
Test status
Simulation time 69918937 ps
CPU time 0.91 seconds
Started Jul 09 05:07:48 PM PDT 24
Finished Jul 09 05:07:49 PM PDT 24
Peak memory 208268 kb
Host smart-6afdb4c4-8484-45a0-b0df-186a2ea155e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655111768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.1655111768
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.783302338
Short name T255
Test name
Test status
Simulation time 462631027 ps
CPU time 12.47 seconds
Started Jul 09 05:07:44 PM PDT 24
Finished Jul 09 05:07:57 PM PDT 24
Peak memory 217636 kb
Host smart-86506f92-8904-45fc-acd8-9b2d512b2ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783302338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.783302338
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.556461515
Short name T467
Test name
Test status
Simulation time 5552487603 ps
CPU time 6.33 seconds
Started Jul 09 05:07:47 PM PDT 24
Finished Jul 09 05:07:54 PM PDT 24
Peak memory 217316 kb
Host smart-1e468566-5709-473f-8221-ea6176e3070f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556461515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.556461515
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.2547973067
Short name T417
Test name
Test status
Simulation time 5226333367 ps
CPU time 34.03 seconds
Started Jul 09 05:07:48 PM PDT 24
Finished Jul 09 05:08:22 PM PDT 24
Peak memory 217740 kb
Host smart-a5e412e9-ddd2-41b9-afac-6521b6bb6085
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547973067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.2547973067
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.2315396775
Short name T533
Test name
Test status
Simulation time 1167216154 ps
CPU time 3.88 seconds
Started Jul 09 05:07:45 PM PDT 24
Finished Jul 09 05:07:50 PM PDT 24
Peak memory 217272 kb
Host smart-36660d7a-7305-4577-971b-bdaafdfeb804
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315396775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.2
315396775
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.1338750804
Short name T399
Test name
Test status
Simulation time 4476494129 ps
CPU time 15.67 seconds
Started Jul 09 05:07:48 PM PDT 24
Finished Jul 09 05:08:05 PM PDT 24
Peak memory 225464 kb
Host smart-6769529b-3fc7-485f-9339-3d6ccbca9e5c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338750804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.1338750804
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.838501371
Short name T4
Test name
Test status
Simulation time 3891398836 ps
CPU time 15.56 seconds
Started Jul 09 05:07:45 PM PDT 24
Finished Jul 09 05:08:01 PM PDT 24
Peak memory 217188 kb
Host smart-9e1e56f4-4ce3-4204-a552-3422e7b230e2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838501371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_regwen_during_op.838501371
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.705028726
Short name T219
Test name
Test status
Simulation time 984136827 ps
CPU time 10.66 seconds
Started Jul 09 05:07:47 PM PDT 24
Finished Jul 09 05:07:59 PM PDT 24
Peak memory 216972 kb
Host smart-be3d15db-067b-40a3-92ca-0f0514d0678a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705028726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.705028726
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.3364309100
Short name T723
Test name
Test status
Simulation time 1363175191 ps
CPU time 58.84 seconds
Started Jul 09 05:07:48 PM PDT 24
Finished Jul 09 05:08:48 PM PDT 24
Peak memory 276096 kb
Host smart-3e6b8a2e-bc50-49a9-988d-a196decac978
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364309100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.3364309100
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.2166375823
Short name T407
Test name
Test status
Simulation time 3420043571 ps
CPU time 16.53 seconds
Started Jul 09 05:07:46 PM PDT 24
Finished Jul 09 05:08:03 PM PDT 24
Peak memory 250468 kb
Host smart-80dce31d-dac0-4799-9947-f2e1effbac6a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166375823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.2166375823
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.1900131044
Short name T325
Test name
Test status
Simulation time 55317524 ps
CPU time 1.67 seconds
Started Jul 09 05:07:47 PM PDT 24
Finished Jul 09 05:07:49 PM PDT 24
Peak memory 217704 kb
Host smart-28770204-ba13-4495-9517-fbd7b8b2a927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900131044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.1900131044
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.2479075516
Short name T784
Test name
Test status
Simulation time 423450796 ps
CPU time 16.62 seconds
Started Jul 09 05:07:48 PM PDT 24
Finished Jul 09 05:08:06 PM PDT 24
Peak memory 217148 kb
Host smart-def68b5e-b3de-48f8-a81a-122f64db6f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479075516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.2479075516
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.1372575155
Short name T841
Test name
Test status
Simulation time 1255010229 ps
CPU time 30.8 seconds
Started Jul 09 05:07:52 PM PDT 24
Finished Jul 09 05:08:23 PM PDT 24
Peak memory 225452 kb
Host smart-79e2be58-d9be-487b-b5a4-67080b780499
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372575155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.1372575155
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.3217344024
Short name T820
Test name
Test status
Simulation time 518136223 ps
CPU time 9.11 seconds
Started Jul 09 05:07:51 PM PDT 24
Finished Jul 09 05:08:00 PM PDT 24
Peak memory 217600 kb
Host smart-9fc10bab-f739-4ac5-b78a-bf24bd4bfb03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217344024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.3
217344024
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.2288885645
Short name T616
Test name
Test status
Simulation time 7042927308 ps
CPU time 14.18 seconds
Started Jul 09 05:07:44 PM PDT 24
Finished Jul 09 05:07:59 PM PDT 24
Peak memory 217756 kb
Host smart-6786378c-8090-4eb6-9d48-94aff3ba3fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288885645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.2288885645
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.1745756787
Short name T789
Test name
Test status
Simulation time 479580356 ps
CPU time 1.95 seconds
Started Jul 09 05:07:45 PM PDT 24
Finished Jul 09 05:07:48 PM PDT 24
Peak memory 217176 kb
Host smart-6f97bd9d-87df-46ec-b963-572b7f1ef6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745756787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.1745756787
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.523299416
Short name T146
Test name
Test status
Simulation time 391404591 ps
CPU time 18.69 seconds
Started Jul 09 05:07:44 PM PDT 24
Finished Jul 09 05:08:03 PM PDT 24
Peak memory 250396 kb
Host smart-26bb410e-88cb-428b-88ea-cfbf815a6435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523299416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.523299416
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.3836354773
Short name T207
Test name
Test status
Simulation time 101520574 ps
CPU time 3.41 seconds
Started Jul 09 05:07:48 PM PDT 24
Finished Jul 09 05:07:52 PM PDT 24
Peak memory 225788 kb
Host smart-9619f567-6646-41f2-a8aa-814d652fddfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836354773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.3836354773
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.3613330573
Short name T622
Test name
Test status
Simulation time 3843920956 ps
CPU time 124.72 seconds
Started Jul 09 05:07:48 PM PDT 24
Finished Jul 09 05:09:54 PM PDT 24
Peak memory 250540 kb
Host smart-1506cdb5-d0ec-4244-ae2c-dee9ca49ea77
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613330573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.3613330573
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.1821698329
Short name T60
Test name
Test status
Simulation time 59765507 ps
CPU time 0.98 seconds
Started Jul 09 05:07:46 PM PDT 24
Finished Jul 09 05:07:47 PM PDT 24
Peak memory 212340 kb
Host smart-3eb4658d-effc-47bc-ab1c-8451313d6c63
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821698329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.1821698329
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.3591332940
Short name T217
Test name
Test status
Simulation time 98370547 ps
CPU time 0.97 seconds
Started Jul 09 05:07:56 PM PDT 24
Finished Jul 09 05:07:58 PM PDT 24
Peak memory 208368 kb
Host smart-9ca84764-f8cc-4354-8b8a-c7705bb3e950
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591332940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.3591332940
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.3900388690
Short name T187
Test name
Test status
Simulation time 37171741 ps
CPU time 0.93 seconds
Started Jul 09 05:07:52 PM PDT 24
Finished Jul 09 05:07:54 PM PDT 24
Peak memory 208696 kb
Host smart-7356c4ea-46e5-49f1-ae6d-285620bf68c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900388690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.3900388690
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.1707432774
Short name T150
Test name
Test status
Simulation time 831835982 ps
CPU time 10.75 seconds
Started Jul 09 05:07:53 PM PDT 24
Finished Jul 09 05:08:04 PM PDT 24
Peak memory 225440 kb
Host smart-66e38019-4cd2-4eeb-b8c5-4b2221a3b120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707432774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.1707432774
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.3986329129
Short name T408
Test name
Test status
Simulation time 2721612767 ps
CPU time 8.16 seconds
Started Jul 09 05:07:56 PM PDT 24
Finished Jul 09 05:08:04 PM PDT 24
Peak memory 217172 kb
Host smart-682e3a46-ad2b-4883-afd1-9f4c12e148b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986329129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.3986329129
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.84328740
Short name T647
Test name
Test status
Simulation time 8910621902 ps
CPU time 34.1 seconds
Started Jul 09 05:07:56 PM PDT 24
Finished Jul 09 05:08:31 PM PDT 24
Peak memory 217716 kb
Host smart-b0f705cd-f115-46fc-995a-e9bcac7e1358
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84328740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_l
c_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_erro
rs.84328740
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.1000503588
Short name T391
Test name
Test status
Simulation time 1009620691 ps
CPU time 2.57 seconds
Started Jul 09 05:07:53 PM PDT 24
Finished Jul 09 05:07:56 PM PDT 24
Peak memory 217176 kb
Host smart-18e1fc2e-b9f0-42db-b632-1a515e32a073
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000503588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.1
000503588
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.2049016717
Short name T16
Test name
Test status
Simulation time 845026791 ps
CPU time 12.94 seconds
Started Jul 09 05:07:56 PM PDT 24
Finished Jul 09 05:08:09 PM PDT 24
Peak memory 217560 kb
Host smart-fee0ae32-bd7e-430b-bd07-15a31edb8105
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049016717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.2049016717
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.2048653571
Short name T457
Test name
Test status
Simulation time 1201361869 ps
CPU time 20.08 seconds
Started Jul 09 05:07:53 PM PDT 24
Finished Jul 09 05:08:13 PM PDT 24
Peak memory 217000 kb
Host smart-a924cef4-22fb-40f6-bea1-702d55f060b5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048653571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.2048653571
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.3572857261
Short name T710
Test name
Test status
Simulation time 548381514 ps
CPU time 4.79 seconds
Started Jul 09 05:07:54 PM PDT 24
Finished Jul 09 05:08:00 PM PDT 24
Peak memory 217040 kb
Host smart-e3efa649-f54e-4722-a0c6-d585a17bb953
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572857261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
3572857261
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.1097693461
Short name T488
Test name
Test status
Simulation time 643126367 ps
CPU time 10.72 seconds
Started Jul 09 05:07:52 PM PDT 24
Finished Jul 09 05:08:03 PM PDT 24
Peak memory 246200 kb
Host smart-4082a182-7938-4938-8ec1-23f034bfc0f0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097693461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.1097693461
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.3191537234
Short name T802
Test name
Test status
Simulation time 79975389 ps
CPU time 3.71 seconds
Started Jul 09 05:07:54 PM PDT 24
Finished Jul 09 05:07:58 PM PDT 24
Peak memory 221852 kb
Host smart-3983b3f2-2dae-4bac-9851-38dd995d4556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191537234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.3191537234
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.2240279196
Short name T185
Test name
Test status
Simulation time 631278348 ps
CPU time 17.49 seconds
Started Jul 09 05:07:54 PM PDT 24
Finished Jul 09 05:08:12 PM PDT 24
Peak memory 217080 kb
Host smart-aaf5cf19-418a-412d-96fd-6b2b636725f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240279196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.2240279196
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.2990590564
Short name T758
Test name
Test status
Simulation time 828450283 ps
CPU time 13.6 seconds
Started Jul 09 05:07:54 PM PDT 24
Finished Jul 09 05:08:08 PM PDT 24
Peak memory 217736 kb
Host smart-e3db5ce6-3e1d-4a7b-b35b-fc7f67939928
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990590564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.2990590564
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.3224364407
Short name T807
Test name
Test status
Simulation time 4295153049 ps
CPU time 11.71 seconds
Started Jul 09 05:07:54 PM PDT 24
Finished Jul 09 05:08:06 PM PDT 24
Peak memory 225492 kb
Host smart-504ef605-540d-4af6-9191-6441c59af906
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224364407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.3224364407
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.3625931056
Short name T711
Test name
Test status
Simulation time 3642492716 ps
CPU time 15.11 seconds
Started Jul 09 05:07:53 PM PDT 24
Finished Jul 09 05:08:09 PM PDT 24
Peak memory 217668 kb
Host smart-45dc5106-8aef-4c8c-9d1c-e8ee3029b7f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625931056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.3
625931056
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.3202656706
Short name T528
Test name
Test status
Simulation time 1472909361 ps
CPU time 7.47 seconds
Started Jul 09 05:07:53 PM PDT 24
Finished Jul 09 05:08:01 PM PDT 24
Peak memory 224640 kb
Host smart-f30df89d-422b-4032-b51b-279ee07d781c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202656706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.3202656706
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.4126110286
Short name T790
Test name
Test status
Simulation time 18660764 ps
CPU time 1.6 seconds
Started Jul 09 05:07:49 PM PDT 24
Finished Jul 09 05:07:52 PM PDT 24
Peak memory 213724 kb
Host smart-8056e047-89b3-45c8-8457-a7505d0e7983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126110286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.4126110286
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.805604906
Short name T545
Test name
Test status
Simulation time 2459976513 ps
CPU time 21.46 seconds
Started Jul 09 05:07:49 PM PDT 24
Finished Jul 09 05:08:12 PM PDT 24
Peak memory 250548 kb
Host smart-a1f38188-7515-44f7-8c83-a44cb31f2c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805604906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.805604906
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.3456618364
Short name T1
Test name
Test status
Simulation time 171040337 ps
CPU time 7.62 seconds
Started Jul 09 05:07:49 PM PDT 24
Finished Jul 09 05:07:58 PM PDT 24
Peak memory 246216 kb
Host smart-8413131b-e2ae-402e-bbb1-f96e43a0adcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456618364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.3456618364
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.343950384
Short name T320
Test name
Test status
Simulation time 5465365883 ps
CPU time 104.66 seconds
Started Jul 09 05:07:55 PM PDT 24
Finished Jul 09 05:09:41 PM PDT 24
Peak memory 250500 kb
Host smart-96e76ad7-991b-4883-806d-08f9e90712cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343950384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.343950384
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.2694627944
Short name T154
Test name
Test status
Simulation time 39637279896 ps
CPU time 1054.08 seconds
Started Jul 09 05:07:54 PM PDT 24
Finished Jul 09 05:25:28 PM PDT 24
Peak memory 496468 kb
Host smart-fd228e66-f3b3-4ec9-8f45-d36b1092b281
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2694627944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.2694627944
Directory /workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.176995423
Short name T334
Test name
Test status
Simulation time 92329965 ps
CPU time 0.89 seconds
Started Jul 09 05:07:49 PM PDT 24
Finished Jul 09 05:07:51 PM PDT 24
Peak memory 208472 kb
Host smart-68d8eeb5-5611-4ace-9331-3cec17aecdbc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176995423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctr
l_volatile_unlock_smoke.176995423
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.276491921
Short name T473
Test name
Test status
Simulation time 35968500 ps
CPU time 0.97 seconds
Started Jul 09 05:08:03 PM PDT 24
Finished Jul 09 05:08:05 PM PDT 24
Peak memory 208452 kb
Host smart-2d02084d-ca29-45d8-8a9e-dd9d5f23ea9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276491921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.276491921
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.1574051067
Short name T595
Test name
Test status
Simulation time 11587320 ps
CPU time 0.85 seconds
Started Jul 09 05:07:56 PM PDT 24
Finished Jul 09 05:07:58 PM PDT 24
Peak memory 208268 kb
Host smart-854e2aea-b0f4-414d-9836-6005e4a40ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574051067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.1574051067
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.1812836783
Short name T766
Test name
Test status
Simulation time 297400398 ps
CPU time 14.17 seconds
Started Jul 09 05:07:57 PM PDT 24
Finished Jul 09 05:08:11 PM PDT 24
Peak memory 217636 kb
Host smart-a1dd3b27-c10d-4b4e-ac74-f38fac5939de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812836783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.1812836783
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.1936186594
Short name T294
Test name
Test status
Simulation time 683350650 ps
CPU time 5.4 seconds
Started Jul 09 05:08:02 PM PDT 24
Finished Jul 09 05:08:09 PM PDT 24
Peak memory 217168 kb
Host smart-2a0cb206-54ba-4368-b798-fade2d38e071
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936186594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.1936186594
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.4143152964
Short name T540
Test name
Test status
Simulation time 1983245051 ps
CPU time 61.9 seconds
Started Jul 09 05:08:03 PM PDT 24
Finished Jul 09 05:09:05 PM PDT 24
Peak memory 217552 kb
Host smart-b6665c7f-61ff-4445-87d4-090fd577443b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143152964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.4143152964
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.1366285339
Short name T782
Test name
Test status
Simulation time 1835776227 ps
CPU time 31.48 seconds
Started Jul 09 05:08:00 PM PDT 24
Finished Jul 09 05:08:32 PM PDT 24
Peak memory 217484 kb
Host smart-a8ab6f7c-8d31-4c9b-8385-b6fc444414b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366285339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.1
366285339
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.3566625489
Short name T360
Test name
Test status
Simulation time 876647196 ps
CPU time 12.18 seconds
Started Jul 09 05:08:00 PM PDT 24
Finished Jul 09 05:08:12 PM PDT 24
Peak memory 217648 kb
Host smart-fa6ace0f-672b-4bfe-bac6-aadd2367d5e5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566625489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.3566625489
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.4136248474
Short name T756
Test name
Test status
Simulation time 14153097367 ps
CPU time 22.44 seconds
Started Jul 09 05:08:02 PM PDT 24
Finished Jul 09 05:08:25 PM PDT 24
Peak memory 216996 kb
Host smart-70b402aa-d49a-45cb-b8e2-2604ac053568
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136248474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.4136248474
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.2434706448
Short name T610
Test name
Test status
Simulation time 401821462 ps
CPU time 5.56 seconds
Started Jul 09 05:07:58 PM PDT 24
Finished Jul 09 05:08:04 PM PDT 24
Peak memory 217008 kb
Host smart-14659bdc-333f-4aac-9609-8538f8253157
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434706448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
2434706448
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.1485233604
Short name T525
Test name
Test status
Simulation time 3519403877 ps
CPU time 48.63 seconds
Started Jul 09 05:08:00 PM PDT 24
Finished Jul 09 05:08:49 PM PDT 24
Peak memory 266736 kb
Host smart-6bf928fd-a181-4352-bb16-97cae86d41bb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485233604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.1485233604
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.3888379853
Short name T231
Test name
Test status
Simulation time 321941707 ps
CPU time 16.08 seconds
Started Jul 09 05:08:02 PM PDT 24
Finished Jul 09 05:08:19 PM PDT 24
Peak memory 250368 kb
Host smart-c202f20c-5926-479c-a67e-84956cd35e2d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888379853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.3888379853
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.353992253
Short name T507
Test name
Test status
Simulation time 140626464 ps
CPU time 2.86 seconds
Started Jul 09 05:07:57 PM PDT 24
Finished Jul 09 05:08:01 PM PDT 24
Peak memory 217620 kb
Host smart-4195d599-1680-44da-ae5d-1081c5db6e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353992253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.353992253
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.549831427
Short name T566
Test name
Test status
Simulation time 1360949058 ps
CPU time 13.17 seconds
Started Jul 09 05:08:00 PM PDT 24
Finished Jul 09 05:08:13 PM PDT 24
Peak memory 217084 kb
Host smart-3498e4e0-ca43-4758-b238-9a529e83729b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549831427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.549831427
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.368650608
Short name T404
Test name
Test status
Simulation time 379660041 ps
CPU time 16.54 seconds
Started Jul 09 05:08:02 PM PDT 24
Finished Jul 09 05:08:20 PM PDT 24
Peak memory 219484 kb
Host smart-521c7efd-fe5f-45dd-bf27-5ba41b53517d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368650608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.368650608
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.3203718443
Short name T823
Test name
Test status
Simulation time 7277630856 ps
CPU time 24.15 seconds
Started Jul 09 05:08:02 PM PDT 24
Finished Jul 09 05:08:26 PM PDT 24
Peak memory 225444 kb
Host smart-6fbb5676-9faa-4fdd-b4d6-a4ddfabf7230
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203718443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.3203718443
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.1097514646
Short name T475
Test name
Test status
Simulation time 345937878 ps
CPU time 11.15 seconds
Started Jul 09 05:08:03 PM PDT 24
Finished Jul 09 05:08:15 PM PDT 24
Peak memory 225412 kb
Host smart-a8fbca00-9db9-4eea-91ba-a3bba0861693
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097514646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.1
097514646
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.2807129027
Short name T51
Test name
Test status
Simulation time 1804251247 ps
CPU time 12.41 seconds
Started Jul 09 05:08:04 PM PDT 24
Finished Jul 09 05:08:17 PM PDT 24
Peak memory 225524 kb
Host smart-48c8ef69-6047-457c-8ed8-39a136f47e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807129027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.2807129027
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.1856825796
Short name T252
Test name
Test status
Simulation time 14046539 ps
CPU time 1.15 seconds
Started Jul 09 05:07:54 PM PDT 24
Finished Jul 09 05:07:56 PM PDT 24
Peak memory 211400 kb
Host smart-185af973-22ea-47f6-98c9-0ecaa07c5543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856825796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.1856825796
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.4126163538
Short name T13
Test name
Test status
Simulation time 172864176 ps
CPU time 17.01 seconds
Started Jul 09 05:07:56 PM PDT 24
Finished Jul 09 05:08:14 PM PDT 24
Peak memory 250344 kb
Host smart-80dc5c9f-8c97-4bbf-bee6-397189791ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126163538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.4126163538
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.184191159
Short name T10
Test name
Test status
Simulation time 112197962 ps
CPU time 6.66 seconds
Started Jul 09 05:07:57 PM PDT 24
Finished Jul 09 05:08:04 PM PDT 24
Peak memory 249960 kb
Host smart-c470144b-56da-4b13-b400-e6d4b82ac95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184191159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.184191159
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.3186973174
Short name T653
Test name
Test status
Simulation time 20842467559 ps
CPU time 65.98 seconds
Started Jul 09 05:08:05 PM PDT 24
Finished Jul 09 05:09:11 PM PDT 24
Peak memory 283228 kb
Host smart-9fa245ec-c052-4e3e-9dcd-3a2442a039f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186973174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.3186973174
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.3991458542
Short name T463
Test name
Test status
Simulation time 42001639 ps
CPU time 0.9 seconds
Started Jul 09 05:07:53 PM PDT 24
Finished Jul 09 05:07:54 PM PDT 24
Peak memory 211228 kb
Host smart-3fe42340-f42d-4324-a64c-b11a6aea6f6c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991458542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.3991458542
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.3549824204
Short name T81
Test name
Test status
Simulation time 65947985 ps
CPU time 0.84 seconds
Started Jul 09 05:08:08 PM PDT 24
Finished Jul 09 05:08:10 PM PDT 24
Peak memory 208188 kb
Host smart-57406e2e-f960-4a7b-9b56-ea67100bda07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549824204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.3549824204
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.531782954
Short name T272
Test name
Test status
Simulation time 19132344 ps
CPU time 0.83 seconds
Started Jul 09 05:08:08 PM PDT 24
Finished Jul 09 05:08:10 PM PDT 24
Peak memory 208484 kb
Host smart-879c189b-9b53-4dd5-abe5-eeee250d3a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531782954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.531782954
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.1776603588
Short name T452
Test name
Test status
Simulation time 725967634 ps
CPU time 16.46 seconds
Started Jul 09 05:08:03 PM PDT 24
Finished Jul 09 05:08:20 PM PDT 24
Peak memory 225532 kb
Host smart-b4246601-ebce-4bd7-9a09-49e956b14424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776603588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.1776603588
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.385922230
Short name T3
Test name
Test status
Simulation time 579910560 ps
CPU time 4.12 seconds
Started Jul 09 05:08:07 PM PDT 24
Finished Jul 09 05:08:12 PM PDT 24
Peak memory 217144 kb
Host smart-fc5ac1b5-ee37-47d9-b830-b7ff07f374bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385922230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.385922230
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.1756857969
Short name T505
Test name
Test status
Simulation time 4268362756 ps
CPU time 32.06 seconds
Started Jul 09 05:08:07 PM PDT 24
Finished Jul 09 05:08:39 PM PDT 24
Peak memory 218348 kb
Host smart-79864167-458c-4d29-8758-60ca3e4757a1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756857969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.1756857969
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.32651544
Short name T621
Test name
Test status
Simulation time 2439899691 ps
CPU time 18.88 seconds
Started Jul 09 05:08:06 PM PDT 24
Finished Jul 09 05:08:26 PM PDT 24
Peak memory 217124 kb
Host smart-3168bdad-1110-44df-81b4-a2a157ce4dbe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32651544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.32651544
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.1821037966
Short name T232
Test name
Test status
Simulation time 2175719509 ps
CPU time 8.22 seconds
Started Jul 09 05:08:08 PM PDT 24
Finished Jul 09 05:08:17 PM PDT 24
Peak memory 217596 kb
Host smart-e209bde9-b3e0-4e02-934f-185452c2e8ca
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821037966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.1821037966
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.1477076274
Short name T718
Test name
Test status
Simulation time 953132905 ps
CPU time 25.95 seconds
Started Jul 09 05:08:06 PM PDT 24
Finished Jul 09 05:08:32 PM PDT 24
Peak memory 217060 kb
Host smart-7ece957e-4d92-4b7f-a26f-7d303758be63
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477076274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.1477076274
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.1442929261
Short name T288
Test name
Test status
Simulation time 439519201 ps
CPU time 2.33 seconds
Started Jul 09 05:08:07 PM PDT 24
Finished Jul 09 05:08:10 PM PDT 24
Peak memory 216996 kb
Host smart-bfbd8d0b-56c7-4702-90fa-d4977f8692e9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442929261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
1442929261
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.640142915
Short name T514
Test name
Test status
Simulation time 1610377580 ps
CPU time 47.05 seconds
Started Jul 09 05:08:06 PM PDT 24
Finished Jul 09 05:08:54 PM PDT 24
Peak memory 250324 kb
Host smart-17c2c12f-17f3-4cea-bc74-f7b8d5d10979
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640142915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_state_failure.640142915
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.4228488218
Short name T842
Test name
Test status
Simulation time 969826088 ps
CPU time 14.02 seconds
Started Jul 09 05:08:05 PM PDT 24
Finished Jul 09 05:08:20 PM PDT 24
Peak memory 225784 kb
Host smart-cde2254f-ab13-4449-a9fc-337dd959100f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228488218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.4228488218
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.4192438190
Short name T383
Test name
Test status
Simulation time 382663322 ps
CPU time 3.74 seconds
Started Jul 09 05:08:03 PM PDT 24
Finished Jul 09 05:08:08 PM PDT 24
Peak memory 217688 kb
Host smart-4110a879-0817-4840-b554-7910cc482fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192438190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.4192438190
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.4025882790
Short name T681
Test name
Test status
Simulation time 979529313 ps
CPU time 8.89 seconds
Started Jul 09 05:08:02 PM PDT 24
Finished Jul 09 05:08:11 PM PDT 24
Peak memory 222336 kb
Host smart-b0d6d23a-e6cc-4abf-a7fb-a3b0ecc8080a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025882790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.4025882790
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.4217874769
Short name T456
Test name
Test status
Simulation time 246366483 ps
CPU time 13.03 seconds
Started Jul 09 05:08:08 PM PDT 24
Finished Jul 09 05:08:22 PM PDT 24
Peak memory 218244 kb
Host smart-8bdf0a43-0065-4185-8e07-71a0dbbe7b78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217874769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.4217874769
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.1042124308
Short name T799
Test name
Test status
Simulation time 803944421 ps
CPU time 12.38 seconds
Started Jul 09 05:08:07 PM PDT 24
Finished Jul 09 05:08:20 PM PDT 24
Peak memory 225524 kb
Host smart-384f559d-8fcc-4a51-a19e-594eaec7c878
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042124308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.1042124308
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.1303816624
Short name T692
Test name
Test status
Simulation time 1015711650 ps
CPU time 10.81 seconds
Started Jul 09 05:08:08 PM PDT 24
Finished Jul 09 05:08:20 PM PDT 24
Peak memory 217540 kb
Host smart-3f22d8d2-c002-432a-afee-4040d84239b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303816624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.1
303816624
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.1621083477
Short name T50
Test name
Test status
Simulation time 327402640 ps
CPU time 8.67 seconds
Started Jul 09 05:08:01 PM PDT 24
Finished Jul 09 05:08:10 PM PDT 24
Peak memory 225516 kb
Host smart-6070c2ac-4050-4550-a7cc-02ae93f909bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621083477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.1621083477
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.2786630189
Short name T828
Test name
Test status
Simulation time 67496478 ps
CPU time 2.37 seconds
Started Jul 09 05:08:04 PM PDT 24
Finished Jul 09 05:08:07 PM PDT 24
Peak memory 217128 kb
Host smart-370dd952-a9f2-431d-9576-7149daa4cfad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786630189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.2786630189
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.678186898
Short name T732
Test name
Test status
Simulation time 180119715 ps
CPU time 21.77 seconds
Started Jul 09 05:08:03 PM PDT 24
Finished Jul 09 05:08:25 PM PDT 24
Peak memory 250428 kb
Host smart-95140c3e-1c7a-469f-b5a2-6d74c39e713d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678186898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.678186898
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.523916517
Short name T342
Test name
Test status
Simulation time 77677386 ps
CPU time 3.94 seconds
Started Jul 09 05:08:04 PM PDT 24
Finished Jul 09 05:08:09 PM PDT 24
Peak memory 225836 kb
Host smart-3b00d966-fb57-4353-8ea5-0b3787e04268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523916517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.523916517
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.709164355
Short name T8
Test name
Test status
Simulation time 85636369935 ps
CPU time 166.11 seconds
Started Jul 09 05:08:06 PM PDT 24
Finished Jul 09 05:10:52 PM PDT 24
Peak memory 237572 kb
Host smart-9f77ba68-78ac-4171-bcc3-29d2a26ce6cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709164355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.709164355
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.3613967538
Short name T416
Test name
Test status
Simulation time 59548359 ps
CPU time 0.98 seconds
Started Jul 09 05:08:02 PM PDT 24
Finished Jul 09 05:08:04 PM PDT 24
Peak memory 211284 kb
Host smart-3c2589d0-d9e1-4104-b09e-00ba5d6d5b1e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613967538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.3613967538
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.616905682
Short name T220
Test name
Test status
Simulation time 23729409 ps
CPU time 1.11 seconds
Started Jul 09 05:08:11 PM PDT 24
Finished Jul 09 05:08:13 PM PDT 24
Peak memory 208476 kb
Host smart-c39db1d9-3e9b-4a9b-bee5-bbfeb92115d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616905682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.616905682
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.817477157
Short name T599
Test name
Test status
Simulation time 397714319 ps
CPU time 12.26 seconds
Started Jul 09 05:08:08 PM PDT 24
Finished Jul 09 05:08:22 PM PDT 24
Peak memory 225508 kb
Host smart-53d77328-bb04-433e-aa09-b9f43e17b35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817477157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.817477157
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.106320020
Short name T856
Test name
Test status
Simulation time 1950916367 ps
CPU time 7.16 seconds
Started Jul 09 05:08:10 PM PDT 24
Finished Jul 09 05:08:18 PM PDT 24
Peak memory 217080 kb
Host smart-77ef6965-29d8-47c4-aace-3adc00d63d74
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106320020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.106320020
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.2586731186
Short name T602
Test name
Test status
Simulation time 6129230660 ps
CPU time 65.33 seconds
Started Jul 09 05:08:11 PM PDT 24
Finished Jul 09 05:09:17 PM PDT 24
Peak memory 218280 kb
Host smart-5e39383e-ede0-493e-b88c-add4ec64346a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586731186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.2586731186
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.3702465257
Short name T260
Test name
Test status
Simulation time 281859694 ps
CPU time 4.17 seconds
Started Jul 09 05:08:12 PM PDT 24
Finished Jul 09 05:08:17 PM PDT 24
Peak memory 217120 kb
Host smart-02cfd463-fed1-44f7-a8f2-0d32662a5492
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702465257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.3
702465257
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.1937326185
Short name T268
Test name
Test status
Simulation time 1318428559 ps
CPU time 12.29 seconds
Started Jul 09 05:08:12 PM PDT 24
Finished Jul 09 05:08:25 PM PDT 24
Peak memory 217584 kb
Host smart-eeff6f70-dc34-4d55-86b7-ffe7ac8f2d2f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937326185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.1937326185
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.1552884828
Short name T200
Test name
Test status
Simulation time 1066875166 ps
CPU time 31.08 seconds
Started Jul 09 05:08:11 PM PDT 24
Finished Jul 09 05:08:42 PM PDT 24
Peak memory 217004 kb
Host smart-082d47a3-4412-4e24-8a4f-f0e129197ccd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552884828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.1552884828
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.825171351
Short name T76
Test name
Test status
Simulation time 501832249 ps
CPU time 7.03 seconds
Started Jul 09 05:08:09 PM PDT 24
Finished Jul 09 05:08:17 PM PDT 24
Peak memory 217060 kb
Host smart-d56dbe8c-f401-47c8-92c9-2760f24a7050
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825171351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.825171351
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.1996473155
Short name T397
Test name
Test status
Simulation time 1536998809 ps
CPU time 26.93 seconds
Started Jul 09 05:08:10 PM PDT 24
Finished Jul 09 05:08:38 PM PDT 24
Peak memory 250272 kb
Host smart-c7dd90b8-1867-4c6d-a960-d302a1fce56b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996473155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.1996473155
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.4011044033
Short name T592
Test name
Test status
Simulation time 570069415 ps
CPU time 16.98 seconds
Started Jul 09 05:08:09 PM PDT 24
Finished Jul 09 05:08:27 PM PDT 24
Peak memory 250320 kb
Host smart-8306548b-6b3b-4dd2-9784-c805cc05a66b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011044033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.4011044033
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.4053847837
Short name T283
Test name
Test status
Simulation time 691788717 ps
CPU time 3.12 seconds
Started Jul 09 05:08:06 PM PDT 24
Finished Jul 09 05:08:09 PM PDT 24
Peak memory 217648 kb
Host smart-3c0f601d-c659-42b4-9db3-aac2c24157bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053847837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.4053847837
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.416995856
Short name T818
Test name
Test status
Simulation time 1077876617 ps
CPU time 5.82 seconds
Started Jul 09 05:08:09 PM PDT 24
Finished Jul 09 05:08:16 PM PDT 24
Peak memory 213900 kb
Host smart-910a1d47-f99c-4126-bf12-4e4e3b72de31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416995856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.416995856
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.848783078
Short name T721
Test name
Test status
Simulation time 349509992 ps
CPU time 11.73 seconds
Started Jul 09 05:08:12 PM PDT 24
Finished Jul 09 05:08:24 PM PDT 24
Peak memory 225448 kb
Host smart-050f612c-c57d-4ecc-b2d0-41b0597c8eeb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848783078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_dig
est.848783078
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.1930307918
Short name T679
Test name
Test status
Simulation time 4790140670 ps
CPU time 11.04 seconds
Started Jul 09 05:08:10 PM PDT 24
Finished Jul 09 05:08:22 PM PDT 24
Peak memory 217648 kb
Host smart-c9ff8788-8de8-4bc6-9cec-d7b0b669ae04
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930307918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.1
930307918
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.204562545
Short name T801
Test name
Test status
Simulation time 217017345 ps
CPU time 9.16 seconds
Started Jul 09 05:08:09 PM PDT 24
Finished Jul 09 05:08:19 PM PDT 24
Peak memory 224820 kb
Host smart-e0335be5-4dac-418d-8b88-1e81e707aeca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204562545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.204562545
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.2093070502
Short name T12
Test name
Test status
Simulation time 32026408 ps
CPU time 1.56 seconds
Started Jul 09 05:08:04 PM PDT 24
Finished Jul 09 05:08:06 PM PDT 24
Peak memory 217116 kb
Host smart-44bd2e4d-84e6-47ef-8b15-35459376484c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093070502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.2093070502
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.51591947
Short name T349
Test name
Test status
Simulation time 376289840 ps
CPU time 36.2 seconds
Started Jul 09 05:08:04 PM PDT 24
Finished Jul 09 05:08:41 PM PDT 24
Peak memory 250416 kb
Host smart-021eb4c7-3842-463e-a53d-61ec1c8da093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51591947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.51591947
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.3292970019
Short name T747
Test name
Test status
Simulation time 39884043 ps
CPU time 3.18 seconds
Started Jul 09 05:08:07 PM PDT 24
Finished Jul 09 05:08:11 PM PDT 24
Peak memory 225836 kb
Host smart-217ca5ce-8af2-4897-86e2-486d124af23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292970019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.3292970019
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.3276702689
Short name T589
Test name
Test status
Simulation time 5267745188 ps
CPU time 58.49 seconds
Started Jul 09 05:08:08 PM PDT 24
Finished Jul 09 05:09:07 PM PDT 24
Peak memory 250504 kb
Host smart-e6feb98e-498c-44cf-8543-054fe4856214
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276702689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.3276702689
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.2302580799
Short name T151
Test name
Test status
Simulation time 10984839258 ps
CPU time 270.9 seconds
Started Jul 09 05:08:10 PM PDT 24
Finished Jul 09 05:12:42 PM PDT 24
Peak memory 310048 kb
Host smart-4969762c-72de-4042-849e-5bdb2611aa9c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2302580799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all_with_rand_reset.2302580799
Directory /workspace/9.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.1218986015
Short name T37
Test name
Test status
Simulation time 14120254 ps
CPU time 1.02 seconds
Started Jul 09 05:08:08 PM PDT 24
Finished Jul 09 05:08:10 PM PDT 24
Peak memory 208316 kb
Host smart-00a423fe-d9d3-4014-8073-b9ef6bc876ca
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218986015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.1218986015
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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