Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52638 |
1 |
|
|
T2 |
91 |
|
T3 |
86 |
|
T4 |
59 |
auto[1] |
1849 |
1 |
|
|
T12 |
13 |
|
T5 |
9 |
|
T36 |
10 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53927 |
1 |
|
|
T2 |
91 |
|
T3 |
86 |
|
T4 |
59 |
auto[1] |
560 |
1 |
|
|
T45 |
16 |
|
T71 |
15 |
|
T48 |
15 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52499 |
1 |
|
|
T2 |
91 |
|
T3 |
76 |
|
T4 |
59 |
auto[1] |
1988 |
1 |
|
|
T3 |
10 |
|
T6 |
14 |
|
T17 |
1 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52436 |
1 |
|
|
T2 |
91 |
|
T3 |
75 |
|
T4 |
59 |
auto[1] |
2051 |
1 |
|
|
T3 |
11 |
|
T6 |
8 |
|
T17 |
1 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52425 |
1 |
|
|
T2 |
91 |
|
T3 |
77 |
|
T4 |
59 |
auto[1] |
2062 |
1 |
|
|
T3 |
9 |
|
T6 |
9 |
|
T17 |
1 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
49082 |
1 |
|
|
T2 |
91 |
|
T3 |
86 |
|
T4 |
59 |
no_err_inj |
5405 |
1 |
|
|
T17 |
4 |
|
T11 |
6 |
|
T34 |
18 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52645 |
1 |
|
|
T2 |
91 |
|
T3 |
86 |
|
T4 |
59 |
auto[1] |
1842 |
1 |
|
|
T12 |
2 |
|
T5 |
9 |
|
T36 |
5 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53971 |
1 |
|
|
T2 |
91 |
|
T3 |
86 |
|
T4 |
59 |
auto[1] |
516 |
1 |
|
|
T45 |
23 |
|
T71 |
16 |
|
T48 |
11 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
37188 |
1 |
|
|
T2 |
91 |
|
T3 |
86 |
|
T4 |
59 |
auto[1] |
17299 |
1 |
|
|
T5 |
63 |
|
T6 |
83 |
|
T11 |
6 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52477 |
1 |
|
|
T2 |
91 |
|
T3 |
79 |
|
T4 |
59 |
auto[1] |
2010 |
1 |
|
|
T3 |
7 |
|
T6 |
7 |
|
T17 |
1 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52435 |
1 |
|
|
T2 |
91 |
|
T3 |
75 |
|
T4 |
59 |
auto[1] |
2052 |
1 |
|
|
T3 |
11 |
|
T6 |
15 |
|
T37 |
1 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52456 |
1 |
|
|
T2 |
91 |
|
T3 |
78 |
|
T4 |
59 |
auto[1] |
2031 |
1 |
|
|
T3 |
8 |
|
T6 |
9 |
|
T38 |
10 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52706 |
1 |
|
|
T2 |
91 |
|
T3 |
86 |
|
T4 |
59 |
auto[1] |
1781 |
1 |
|
|
T12 |
8 |
|
T5 |
9 |
|
T36 |
12 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52331 |
1 |
|
|
T2 |
91 |
|
T3 |
86 |
|
T4 |
59 |
auto[1] |
2156 |
1 |
|
|
T20 |
26 |
|
T66 |
4 |
|
T67 |
25 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53917 |
1 |
|
|
T2 |
91 |
|
T3 |
86 |
|
T4 |
59 |
auto[1] |
570 |
1 |
|
|
T45 |
23 |
|
T71 |
18 |
|
T48 |
7 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53910 |
1 |
|
|
T2 |
91 |
|
T3 |
86 |
|
T4 |
59 |
auto[1] |
577 |
1 |
|
|
T45 |
15 |
|
T71 |
19 |
|
T48 |
18 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53911 |
1 |
|
|
T2 |
91 |
|
T3 |
86 |
|
T4 |
59 |
auto[1] |
576 |
1 |
|
|
T45 |
19 |
|
T71 |
26 |
|
T48 |
13 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51372 |
1 |
|
|
T2 |
91 |
|
T3 |
86 |
|
T4 |
59 |
auto[1] |
3115 |
1 |
|
|
T17 |
10 |
|
T37 |
15 |
|
T20 |
62 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50795 |
1 |
|
|
T2 |
91 |
|
T3 |
86 |
|
T4 |
59 |
auto[1] |
3692 |
1 |
|
|
T16 |
58 |
|
T18 |
60 |
|
T19 |
50 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52483 |
1 |
|
|
T2 |
91 |
|
T3 |
73 |
|
T4 |
59 |
auto[1] |
2004 |
1 |
|
|
T3 |
13 |
|
T6 |
12 |
|
T17 |
1 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52431 |
1 |
|
|
T2 |
91 |
|
T3 |
77 |
|
T4 |
59 |
auto[1] |
2056 |
1 |
|
|
T3 |
9 |
|
T6 |
6 |
|
T37 |
1 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52413 |
1 |
|
|
T2 |
91 |
|
T3 |
78 |
|
T4 |
59 |
auto[1] |
2074 |
1 |
|
|
T3 |
8 |
|
T6 |
3 |
|
T17 |
1 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52662 |
1 |
|
|
T2 |
91 |
|
T3 |
86 |
|
T4 |
59 |
auto[1] |
1825 |
1 |
|
|
T12 |
13 |
|
T5 |
10 |
|
T36 |
9 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49077 |
1 |
|
|
T3 |
86 |
|
T12 |
62 |
|
T5 |
57 |
auto[1] |
5410 |
1 |
|
|
T2 |
91 |
|
T4 |
59 |
|
T12 |
5 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50732 |
1 |
|
|
T2 |
91 |
|
T3 |
86 |
|
T4 |
59 |
auto[1] |
3755 |
1 |
|
|
T68 |
51 |
|
T69 |
96 |
|
T70 |
70 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54487 |
1 |
|
|
T2 |
91 |
|
T3 |
86 |
|
T4 |
59 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52566 |
1 |
|
|
T2 |
91 |
|
T3 |
86 |
|
T4 |
59 |
auto[1] |
1921 |
1 |
|
|
T12 |
9 |
|
T5 |
7 |
|
T36 |
6 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52624 |
1 |
|
|
T2 |
91 |
|
T3 |
86 |
|
T4 |
59 |
auto[1] |
1863 |
1 |
|
|
T12 |
7 |
|
T5 |
8 |
|
T36 |
7 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52626 |
1 |
|
|
T2 |
91 |
|
T3 |
86 |
|
T4 |
59 |
auto[1] |
1861 |
1 |
|
|
T12 |
10 |
|
T5 |
5 |
|
T36 |
7 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
47525 |
1 |
|
|
T2 |
91 |
|
T3 |
86 |
|
T4 |
59 |
auto[0] |
no_err_inj |
3847 |
1 |
|
|
T11 |
6 |
|
T34 |
18 |
|
T88 |
12 |
auto[1] |
err_inj |
1557 |
1 |
|
|
T17 |
6 |
|
T37 |
6 |
|
T20 |
34 |
auto[1] |
no_err_inj |
1558 |
1 |
|
|
T17 |
4 |
|
T37 |
9 |
|
T20 |
28 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49486 |
1 |
|
|
T2 |
91 |
|
T3 |
77 |
|
T4 |
59 |
auto[0] |
auto[1] |
1886 |
1 |
|
|
T3 |
9 |
|
T6 |
6 |
|
T38 |
5 |
auto[1] |
auto[0] |
2945 |
1 |
|
|
T17 |
10 |
|
T37 |
14 |
|
T20 |
57 |
auto[1] |
auto[1] |
170 |
1 |
|
|
T37 |
1 |
|
T20 |
5 |
|
T43 |
3 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49519 |
1 |
|
|
T2 |
91 |
|
T3 |
75 |
|
T4 |
59 |
auto[0] |
auto[1] |
1853 |
1 |
|
|
T3 |
11 |
|
T6 |
15 |
|
T38 |
6 |
auto[1] |
auto[0] |
2916 |
1 |
|
|
T17 |
10 |
|
T37 |
14 |
|
T20 |
59 |
auto[1] |
auto[1] |
199 |
1 |
|
|
T37 |
1 |
|
T20 |
3 |
|
T67 |
1 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49435 |
1 |
|
|
T2 |
91 |
|
T3 |
78 |
|
T4 |
59 |
auto[0] |
auto[1] |
1937 |
1 |
|
|
T3 |
8 |
|
T6 |
3 |
|
T38 |
10 |
auto[1] |
auto[0] |
2978 |
1 |
|
|
T17 |
9 |
|
T37 |
15 |
|
T20 |
60 |
auto[1] |
auto[1] |
137 |
1 |
|
|
T17 |
1 |
|
T20 |
2 |
|
T67 |
1 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49517 |
1 |
|
|
T2 |
91 |
|
T3 |
75 |
|
T4 |
59 |
auto[0] |
auto[1] |
1855 |
1 |
|
|
T3 |
11 |
|
T6 |
8 |
|
T38 |
7 |
auto[1] |
auto[0] |
2919 |
1 |
|
|
T17 |
9 |
|
T37 |
15 |
|
T20 |
55 |
auto[1] |
auto[1] |
196 |
1 |
|
|
T17 |
1 |
|
T20 |
7 |
|
T67 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49477 |
1 |
|
|
T2 |
91 |
|
T3 |
77 |
|
T4 |
59 |
auto[0] |
auto[1] |
1895 |
1 |
|
|
T3 |
9 |
|
T6 |
9 |
|
T38 |
8 |
auto[1] |
auto[0] |
2948 |
1 |
|
|
T17 |
9 |
|
T37 |
14 |
|
T20 |
59 |
auto[1] |
auto[1] |
167 |
1 |
|
|
T17 |
1 |
|
T37 |
1 |
|
T20 |
3 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49557 |
1 |
|
|
T2 |
91 |
|
T3 |
76 |
|
T4 |
59 |
auto[0] |
auto[1] |
1815 |
1 |
|
|
T3 |
10 |
|
T6 |
14 |
|
T38 |
6 |
auto[1] |
auto[0] |
2942 |
1 |
|
|
T17 |
9 |
|
T37 |
13 |
|
T20 |
58 |
auto[1] |
auto[1] |
173 |
1 |
|
|
T17 |
1 |
|
T37 |
2 |
|
T20 |
4 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36121 |
1 |
|
|
T2 |
91 |
|
T3 |
86 |
|
T4 |
59 |
auto[0] |
auto[1] |
1067 |
1 |
|
|
T12 |
13 |
|
T36 |
10 |
|
T20 |
5 |
auto[1] |
auto[0] |
16517 |
1 |
|
|
T5 |
54 |
|
T6 |
83 |
|
T11 |
6 |
auto[1] |
auto[1] |
782 |
1 |
|
|
T5 |
9 |
|
T20 |
26 |
|
T67 |
12 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36098 |
1 |
|
|
T2 |
91 |
|
T3 |
86 |
|
T4 |
59 |
auto[0] |
auto[1] |
1090 |
1 |
|
|
T12 |
2 |
|
T36 |
5 |
|
T20 |
11 |
auto[1] |
auto[0] |
16547 |
1 |
|
|
T5 |
54 |
|
T6 |
83 |
|
T11 |
6 |
auto[1] |
auto[1] |
752 |
1 |
|
|
T5 |
9 |
|
T20 |
19 |
|
T67 |
5 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35956 |
1 |
|
|
T2 |
91 |
|
T3 |
86 |
|
T4 |
59 |
auto[0] |
auto[1] |
1232 |
1 |
|
|
T20 |
8 |
|
T66 |
4 |
|
T67 |
25 |
auto[1] |
auto[0] |
16375 |
1 |
|
|
T5 |
63 |
|
T6 |
83 |
|
T11 |
6 |
auto[1] |
auto[1] |
924 |
1 |
|
|
T20 |
18 |
|
T220 |
14 |
|
T221 |
1 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36184 |
1 |
|
|
T2 |
91 |
|
T3 |
86 |
|
T4 |
59 |
auto[0] |
auto[1] |
1004 |
1 |
|
|
T12 |
8 |
|
T36 |
12 |
|
T20 |
2 |
auto[1] |
auto[0] |
16522 |
1 |
|
|
T5 |
54 |
|
T6 |
83 |
|
T11 |
6 |
auto[1] |
auto[1] |
777 |
1 |
|
|
T5 |
9 |
|
T20 |
19 |
|
T67 |
10 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
32523 |
1 |
|
|
T3 |
86 |
|
T12 |
62 |
|
T16 |
58 |
auto[0] |
auto[1] |
4665 |
1 |
|
|
T2 |
91 |
|
T4 |
59 |
|
T12 |
5 |
auto[1] |
auto[0] |
16554 |
1 |
|
|
T5 |
57 |
|
T6 |
83 |
|
T11 |
6 |
auto[1] |
auto[1] |
745 |
1 |
|
|
T5 |
6 |
|
T20 |
25 |
|
T67 |
9 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36044 |
1 |
|
|
T2 |
91 |
|
T3 |
77 |
|
T4 |
59 |
auto[0] |
auto[1] |
1144 |
1 |
|
|
T3 |
9 |
|
T37 |
1 |
|
T38 |
5 |
auto[1] |
auto[0] |
16387 |
1 |
|
|
T5 |
63 |
|
T6 |
77 |
|
T11 |
6 |
auto[1] |
auto[1] |
912 |
1 |
|
|
T6 |
6 |
|
T20 |
32 |
|
T91 |
9 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36003 |
1 |
|
|
T2 |
91 |
|
T3 |
73 |
|
T4 |
59 |
auto[0] |
auto[1] |
1185 |
1 |
|
|
T3 |
13 |
|
T17 |
1 |
|
T37 |
1 |
auto[1] |
auto[0] |
16480 |
1 |
|
|
T5 |
63 |
|
T6 |
71 |
|
T11 |
6 |
auto[1] |
auto[1] |
819 |
1 |
|
|
T6 |
12 |
|
T20 |
25 |
|
T91 |
12 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36010 |
1 |
|
|
T2 |
91 |
|
T3 |
75 |
|
T4 |
59 |
auto[0] |
auto[1] |
1178 |
1 |
|
|
T3 |
11 |
|
T37 |
1 |
|
T38 |
6 |
auto[1] |
auto[0] |
16425 |
1 |
|
|
T5 |
63 |
|
T6 |
68 |
|
T11 |
6 |
auto[1] |
auto[1] |
874 |
1 |
|
|
T6 |
15 |
|
T20 |
25 |
|
T91 |
7 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36044 |
1 |
|
|
T2 |
91 |
|
T3 |
79 |
|
T4 |
59 |
auto[0] |
auto[1] |
1144 |
1 |
|
|
T3 |
7 |
|
T17 |
1 |
|
T38 |
12 |
auto[1] |
auto[0] |
16433 |
1 |
|
|
T5 |
63 |
|
T6 |
76 |
|
T11 |
6 |
auto[1] |
auto[1] |
866 |
1 |
|
|
T6 |
7 |
|
T20 |
32 |
|
T91 |
10 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35998 |
1 |
|
|
T2 |
91 |
|
T3 |
75 |
|
T4 |
59 |
auto[0] |
auto[1] |
1190 |
1 |
|
|
T3 |
11 |
|
T17 |
1 |
|
T38 |
7 |
auto[1] |
auto[0] |
16438 |
1 |
|
|
T5 |
63 |
|
T6 |
75 |
|
T11 |
6 |
auto[1] |
auto[1] |
861 |
1 |
|
|
T6 |
8 |
|
T20 |
31 |
|
T91 |
11 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36015 |
1 |
|
|
T2 |
91 |
|
T3 |
76 |
|
T4 |
59 |
auto[0] |
auto[1] |
1173 |
1 |
|
|
T3 |
10 |
|
T17 |
1 |
|
T37 |
2 |
auto[1] |
auto[0] |
16484 |
1 |
|
|
T5 |
63 |
|
T6 |
69 |
|
T11 |
6 |
auto[1] |
auto[1] |
815 |
1 |
|
|
T6 |
14 |
|
T20 |
26 |
|
T91 |
7 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36097 |
1 |
|
|
T2 |
91 |
|
T3 |
86 |
|
T4 |
59 |
auto[0] |
auto[1] |
1091 |
1 |
|
|
T12 |
10 |
|
T36 |
7 |
|
T20 |
4 |
auto[1] |
auto[0] |
16529 |
1 |
|
|
T5 |
58 |
|
T6 |
83 |
|
T11 |
6 |
auto[1] |
auto[1] |
770 |
1 |
|
|
T5 |
5 |
|
T20 |
18 |
|
T67 |
14 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36095 |
1 |
|
|
T2 |
91 |
|
T3 |
86 |
|
T4 |
59 |
auto[0] |
auto[1] |
1093 |
1 |
|
|
T12 |
7 |
|
T36 |
7 |
|
T20 |
6 |
auto[1] |
auto[0] |
16529 |
1 |
|
|
T5 |
55 |
|
T6 |
83 |
|
T11 |
6 |
auto[1] |
auto[1] |
770 |
1 |
|
|
T5 |
8 |
|
T20 |
27 |
|
T67 |
11 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35398 |
1 |
|
|
T2 |
91 |
|
T3 |
86 |
|
T4 |
59 |
auto[0] |
auto[1] |
1790 |
1 |
|
|
T17 |
10 |
|
T37 |
15 |
|
T20 |
25 |
auto[1] |
auto[0] |
15974 |
1 |
|
|
T5 |
63 |
|
T6 |
83 |
|
T11 |
6 |
auto[1] |
auto[1] |
1325 |
1 |
|
|
T20 |
37 |
|
T67 |
10 |
|
T43 |
11 |