Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

113907781

1

T1

1306

T2

27631

T3

29300

auto[1]

1407392

1

T3

3960

T12

693

T5

297

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

113912937

1

T1

1306

T2

27631

T3

30290

auto[1]

1402236

1

T3

2970

T12

594

T5

594

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7785515	1			T1	79		T2	8755		T3	12339
auto[IdleSt]	22739476	1			T1	1227		T2	2882		T3	1524
auto[ClkMuxSt]	35321	1			T2	91		T4	59		T12	67
auto[CntIncrSt]	34961	1			T2	91		T4	59		T12	67
auto[CntProgSt]	1701381	1			T2	1013		T4	210		T12	469
auto[TransCheckSt]	27410	1			T2	91		T4	59		T12	47
auto[TokenHashSt]	49518066	1			T2	1008		T4	65039		T12	1905
auto[FlashRmaSt]	35566	1			T12	10		T5	45		T16	44
auto[TokenCheck0St]	12701	1			T12	10		T5	19		T16	15
auto[TokenCheck1St]	9612	1			T12	8		T5	10		T16	14
auto[TransProgSt]	438711	1			T12	73		T5	20		T16	29
auto[PostTransSt]	13138145	1			T2	13700		T4	8930		T12	11062
auto[ScrapSt]	216189	1			T16	3		T19	3		T34	29
auto[EscalateSt]	7129124	1			T3	9796		T12	1823		T5	5813
auto[InvalidSt]	12490850	1			T3	9590		T6	196763		T17	395

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2145	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	12490850	1			T3	9590		T6	196763		T17	395
EscalateSt	7129124	1			T3	9796		T12	1823		T5	5813
ScrapSt	216189	1			T16	3		T19	3		T34	29
PostTransSt	13138145	1			T2	13700		T4	8930		T12	11062
TransProgSt	438711	1			T12	73		T5	20		T16	29
TokenCheck1St	9612	1			T12	8		T5	10		T16	14
TokenCheck0St	12701	1			T12	10		T5	19		T16	15
FlashRmaSt	35566	1			T12	10		T5	45		T16	44
TokenHashSt	49518066	1			T2	1008		T4	65039		T12	1905
TransCheckSt	27410	1			T2	91		T4	59		T12	47
CntProgSt	1701381	1			T2	1013		T4	210		T12	469
CntIncrSt	34961	1			T2	91		T4	59		T12	67
ClkMuxSt	35321	1			T2	91		T4	59		T12	67
IdleSt	22739476	1			T1	1227		T2	2882		T3	1524
ResetSt	7785515	1			T1	79		T2	8755		T3	12339
arcs[ResetSt=>IdleSt]	54789	1			T1	1		T2	92		T3	79
arcs[IdleSt=>ScrapSt]	297	1			T16	1		T19	1		T34	2
arcs[IdleSt=>ClkMuxSt]	35023	1			T2	91		T4	59		T12	67
arcs[ClkMuxSt=>CntIncrSt]	34961	1			T2	91		T4	59		T12	67
arcs[CntIncrSt=>PostTransSt]	1864	1			T12	7		T5	8		T36	7
arcs[CntIncrSt=>CntProgSt]	33039	1			T2	91		T4	59		T12	60
arcs[CntProgSt=>PostTransSt]	4512	1			T12	13		T5	8		T36	9
arcs[CntProgSt=>TransCheckSt]	27410	1			T2	91		T4	59		T12	47
arcs[TransCheckSt=>PostTransSt]	3759	1			T12	10		T5	5		T36	7
arcs[TransCheckSt=>TokenHashSt]	23517	1			T2	91		T4	59		T12	37
arcs[TokenHashSt=>PostTransSt]	10064	1			T2	91		T4	59		T12	27
arcs[TokenHashSt=>FlashRmaSt]	12820	1			T12	10		T5	19		T16	17
arcs[FlashRmaSt=>TokenCheck0St]	12701	1			T12	10		T5	19		T16	15
arcs[TokenCheck0St=>PostTransSt]	3054	1			T12	2		T5	9		T36	5
arcs[TokenCheck0St=>TokenCheck1St]	9612	1			T12	8		T5	10		T16	14
arcs[TokenCheck1St=>PostTransSt]	626	1			T20	2		T42	2		T43	4
arcs[TransProgSt=>PostTransSt]	8124	1			T12	8		T5	10		T17	4
arcs[IdleSt=>EscalateSt]	165	1			T16	3		T18	3		T55	9
arcs[ClkMuxSt=>EscalateSt]	62	1			T18	1		T19	1		T55	4
arcs[CntIncrSt=>EscalateSt]	58	1			T55	2		T56	2		T57	3
arcs[CntProgSt=>EscalateSt]	1117	1			T16	18		T18	27		T19	22
arcs[TransCheckSt=>EscalateSt]	134	1			T18	1		T55	1		T56	2
arcs[TokenHashSt=>EscalateSt]	633	1			T16	12		T18	6		T19	7
arcs[FlashRmaSt=>EscalateSt]	119	1			T16	2		T18	1		T19	3
arcs[TokenCheck0St=>EscalateSt]	35	1			T16	1		T61	1		T56	1
arcs[TokenCheck1St=>EscalateSt]	145	1			T16	2		T18	1		T19	7
arcs[TransProgSt=>EscalateSt]	717	1			T16	12		T18	14		T19	6
arcs[PostTransSt=>EscalateSt]	4771	1			T12	13		T5	9		T18	1
arcs[InvalidSt=>EscalateSt]	14812	1			T3	70		T6	71		T17	5

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7785351	1			T1	79		T2	8755		T3	12339
auto[0]	auto[IdleSt]	22739362	1			T1	1227		T2	2882		T3	1524
auto[0]	auto[ClkMuxSt]	35281	1			T2	91		T4	59		T12	67
auto[0]	auto[CntIncrSt]	34920	1			T2	91		T4	59		T12	67
auto[0]	auto[CntProgSt]	1700648	1			T2	1013		T4	210		T12	469
auto[0]	auto[TransCheckSt]	27330	1			T2	91		T4	59		T12	47
auto[0]	auto[TokenHashSt]	49517647	1			T2	1008		T4	65039		T12	1905
auto[0]	auto[FlashRmaSt]	35488	1			T12	10		T5	45		T16	43
auto[0]	auto[TokenCheck0St]	12681	1			T12	10		T5	19		T16	14
auto[0]	auto[TokenCheck1St]	9510	1			T12	8		T5	10		T16	13
auto[0]	auto[TransProgSt]	438241	1			T12	73		T5	20		T16	20
auto[0]	auto[PostTransSt]	13135702	1			T2	13700		T4	8930		T12	11055
auto[0]	auto[ScrapSt]	216152	1			T16	2		T19	3		T34	29
auto[0]	auto[EscalateSt]	5733895	1			T3	5876		T12	1137		T5	5519
auto[0]	auto[InvalidSt]	12483428	1			T3	9550		T6	196725		T17	393
auto[1]	auto[ResetSt]	164	1			T16	6		T18	3		T19	1
auto[1]	auto[IdleSt]	114	1			T16	2		T18	1		T55	7
auto[1]	auto[ClkMuxSt]	40	1			T18	1		T55	2		T61	1
auto[1]	auto[CntIncrSt]	41	1			T55	2		T56	2		T57	2
auto[1]	auto[CntProgSt]	733	1			T16	10		T18	16		T19	15
auto[1]	auto[TransCheckSt]	80	1			T56	1		T57	6		T119	6
auto[1]	auto[TokenHashSt]	419	1			T16	9		T18	5		T19	6
auto[1]	auto[FlashRmaSt]	78	1			T16	1		T18	1		T19	1
auto[1]	auto[TokenCheck0St]	20	1			T16	1		T61	1		T56	1
auto[1]	auto[TokenCheck1St]	102	1			T16	1		T19	5		T61	3
auto[1]	auto[TransProgSt]	470	1			T16	9		T18	9		T19	4
auto[1]	auto[PostTransSt]	2443	1			T12	7		T5	3		T36	3
auto[1]	auto[ScrapSt]	37	1			T16	1		T55	1		T61	1
auto[1]	auto[EscalateSt]	1395229	1			T3	3920		T12	686		T5	294
auto[1]	auto[InvalidSt]	7422	1			T3	40		T6	38		T17	2

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7785342	1			T1	79		T2	8755		T3	12339
auto[0]	auto[IdleSt]	22739375	1			T1	1227		T2	2882		T3	1524
auto[0]	auto[ClkMuxSt]	35280	1			T2	91		T4	59		T12	67
auto[0]	auto[CntIncrSt]	34921	1			T2	91		T4	59		T12	67
auto[0]	auto[CntProgSt]	1700656	1			T2	1013		T4	210		T12	469
auto[0]	auto[TransCheckSt]	27311	1			T2	91		T4	59		T12	47
auto[0]	auto[TokenHashSt]	49517652	1			T2	1008		T4	65039		T12	1905
auto[0]	auto[FlashRmaSt]	35492	1			T12	10		T5	45		T16	42
auto[0]	auto[TokenCheck0St]	12677	1			T12	10		T5	19		T16	14
auto[0]	auto[TokenCheck1St]	9519	1			T12	8		T5	10		T16	12
auto[0]	auto[TransProgSt]	438233	1			T12	73		T5	20		T16	21
auto[0]	auto[PostTransSt]	13135743	1			T2	13700		T4	8930		T12	11056
auto[0]	auto[ScrapSt]	216154	1			T16	3		T19	2		T34	29
auto[0]	auto[EscalateSt]	5738977	1			T3	6856		T12	1235		T5	5225
auto[0]	auto[InvalidSt]	12483460	1			T3	9560		T6	196730		T17	392
auto[1]	auto[ResetSt]	173	1			T16	3		T18	4		T19	3
auto[1]	auto[IdleSt]	101	1			T16	3		T18	3		T55	6
auto[1]	auto[ClkMuxSt]	41	1			T18	1		T19	1		T55	2
auto[1]	auto[CntIncrSt]	40	1			T55	1		T57	2		T119	1
auto[1]	auto[CntProgSt]	725	1			T16	13		T18	20		T19	15
auto[1]	auto[TransCheckSt]	99	1			T18	1		T55	1		T56	2
auto[1]	auto[TokenHashSt]	414	1			T16	7		T18	4		T19	3
auto[1]	auto[FlashRmaSt]	74	1			T16	2		T19	3		T55	2
auto[1]	auto[TokenCheck0St]	24	1			T16	1		T61	1		T219	1
auto[1]	auto[TokenCheck1St]	93	1			T16	2		T18	1		T19	4
auto[1]	auto[TransProgSt]	478	1			T16	8		T18	9		T19	4
auto[1]	auto[PostTransSt]	2402	1			T12	6		T5	6		T18	1
auto[1]	auto[ScrapSt]	35	1			T19	1		T55	2		T61	1
auto[1]	auto[EscalateSt]	1390147	1			T3	2940		T12	588		T5	588
auto[1]	auto[InvalidSt]	7390	1			T3	30		T6	33		T17	3