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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.30 97.99 96.04 93.38 100.00 98.55 99.00 96.11


Total test records in report: 990
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T809 /workspace/coverage/default/15.lc_ctrl_jtag_access.202162188 Jul 10 05:02:56 PM PDT 24 Jul 10 05:03:00 PM PDT 24 286432251 ps
T810 /workspace/coverage/default/10.lc_ctrl_jtag_errors.2321848057 Jul 10 05:02:26 PM PDT 24 Jul 10 05:02:47 PM PDT 24 987432696 ps
T811 /workspace/coverage/default/46.lc_ctrl_sec_mubi.830104323 Jul 10 05:05:11 PM PDT 24 Jul 10 05:05:25 PM PDT 24 225771632 ps
T812 /workspace/coverage/default/12.lc_ctrl_state_failure.544580025 Jul 10 05:02:44 PM PDT 24 Jul 10 05:03:09 PM PDT 24 560800264 ps
T813 /workspace/coverage/default/19.lc_ctrl_state_failure.2404130444 Jul 10 05:03:24 PM PDT 24 Jul 10 05:03:46 PM PDT 24 3591332630 ps
T814 /workspace/coverage/default/28.lc_ctrl_sec_token_digest.3744525716 Jul 10 05:03:57 PM PDT 24 Jul 10 05:04:15 PM PDT 24 429926158 ps
T815 /workspace/coverage/default/49.lc_ctrl_sec_mubi.2047066311 Jul 10 05:05:19 PM PDT 24 Jul 10 05:05:29 PM PDT 24 398698714 ps
T816 /workspace/coverage/default/26.lc_ctrl_sec_token_digest.3294534799 Jul 10 05:03:46 PM PDT 24 Jul 10 05:03:57 PM PDT 24 1380601929 ps
T817 /workspace/coverage/default/49.lc_ctrl_prog_failure.1887638764 Jul 10 05:05:20 PM PDT 24 Jul 10 05:05:24 PM PDT 24 48218118 ps
T818 /workspace/coverage/default/49.lc_ctrl_state_post_trans.1804891375 Jul 10 05:05:19 PM PDT 24 Jul 10 05:05:29 PM PDT 24 53868046 ps
T819 /workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.771824978 Jul 10 05:04:14 PM PDT 24 Jul 10 05:34:12 PM PDT 24 80687819708 ps
T820 /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.3504837486 Jul 10 05:02:11 PM PDT 24 Jul 10 05:02:18 PM PDT 24 539528448 ps
T821 /workspace/coverage/default/16.lc_ctrl_sec_token_mux.2215326672 Jul 10 05:02:57 PM PDT 24 Jul 10 05:03:12 PM PDT 24 280247149 ps
T822 /workspace/coverage/default/19.lc_ctrl_security_escalation.3225591911 Jul 10 05:03:24 PM PDT 24 Jul 10 05:03:35 PM PDT 24 235640640 ps
T823 /workspace/coverage/default/10.lc_ctrl_prog_failure.446687127 Jul 10 05:02:27 PM PDT 24 Jul 10 05:02:33 PM PDT 24 152608436 ps
T824 /workspace/coverage/default/9.lc_ctrl_sec_mubi.1381487894 Jul 10 05:02:20 PM PDT 24 Jul 10 05:02:33 PM PDT 24 2672736445 ps
T825 /workspace/coverage/default/9.lc_ctrl_alert_test.273441868 Jul 10 05:02:25 PM PDT 24 Jul 10 05:02:28 PM PDT 24 115667442 ps
T826 /workspace/coverage/default/6.lc_ctrl_jtag_access.2145446519 Jul 10 05:01:57 PM PDT 24 Jul 10 05:02:05 PM PDT 24 831353840 ps
T123 /workspace/coverage/default/42.lc_ctrl_state_post_trans.1916891270 Jul 10 05:04:54 PM PDT 24 Jul 10 05:05:02 PM PDT 24 161677256 ps
T827 /workspace/coverage/default/46.lc_ctrl_sec_token_digest.1747373227 Jul 10 05:05:09 PM PDT 24 Jul 10 05:05:32 PM PDT 24 1898907680 ps
T828 /workspace/coverage/default/23.lc_ctrl_state_post_trans.413018763 Jul 10 05:03:40 PM PDT 24 Jul 10 05:03:46 PM PDT 24 355262912 ps
T829 /workspace/coverage/default/21.lc_ctrl_state_post_trans.3947664450 Jul 10 05:03:29 PM PDT 24 Jul 10 05:03:38 PM PDT 24 242998950 ps
T830 /workspace/coverage/default/25.lc_ctrl_smoke.3519641054 Jul 10 05:03:39 PM PDT 24 Jul 10 05:03:45 PM PDT 24 39260267 ps
T831 /workspace/coverage/default/29.lc_ctrl_sec_token_mux.3277217669 Jul 10 05:03:56 PM PDT 24 Jul 10 05:04:08 PM PDT 24 328008598 ps
T832 /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.3987918137 Jul 10 05:02:41 PM PDT 24 Jul 10 05:03:49 PM PDT 24 3143679186 ps
T833 /workspace/coverage/default/6.lc_ctrl_sec_token_mux.2646967297 Jul 10 05:02:01 PM PDT 24 Jul 10 05:02:09 PM PDT 24 219732567 ps
T834 /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.2273319694 Jul 10 05:03:40 PM PDT 24 Jul 10 05:03:44 PM PDT 24 61067838 ps
T835 /workspace/coverage/default/30.lc_ctrl_smoke.3696632931 Jul 10 05:03:57 PM PDT 24 Jul 10 05:04:00 PM PDT 24 31818346 ps
T836 /workspace/coverage/default/8.lc_ctrl_sec_mubi.2216203065 Jul 10 05:02:11 PM PDT 24 Jul 10 05:02:23 PM PDT 24 782652931 ps
T837 /workspace/coverage/default/19.lc_ctrl_stress_all.3552338488 Jul 10 05:03:19 PM PDT 24 Jul 10 05:05:21 PM PDT 24 11167850362 ps
T838 /workspace/coverage/default/11.lc_ctrl_security_escalation.2283936897 Jul 10 05:02:36 PM PDT 24 Jul 10 05:02:47 PM PDT 24 2486967060 ps
T839 /workspace/coverage/default/10.lc_ctrl_sec_token_digest.977223896 Jul 10 05:02:26 PM PDT 24 Jul 10 05:02:38 PM PDT 24 1456839900 ps
T840 /workspace/coverage/default/1.lc_ctrl_state_post_trans.684069118 Jul 10 05:01:07 PM PDT 24 Jul 10 05:01:16 PM PDT 24 79613596 ps
T841 /workspace/coverage/default/28.lc_ctrl_sec_mubi.1701230944 Jul 10 05:04:02 PM PDT 24 Jul 10 05:04:14 PM PDT 24 310043394 ps
T842 /workspace/coverage/default/43.lc_ctrl_alert_test.2241114894 Jul 10 05:05:06 PM PDT 24 Jul 10 05:05:12 PM PDT 24 28588001 ps
T843 /workspace/coverage/default/7.lc_ctrl_state_post_trans.4137892670 Jul 10 05:02:03 PM PDT 24 Jul 10 05:02:12 PM PDT 24 314184763 ps
T844 /workspace/coverage/default/42.lc_ctrl_prog_failure.1128337621 Jul 10 05:04:51 PM PDT 24 Jul 10 05:04:56 PM PDT 24 176410585 ps
T845 /workspace/coverage/default/49.lc_ctrl_sec_token_mux.1438183065 Jul 10 05:05:20 PM PDT 24 Jul 10 05:05:35 PM PDT 24 369467330 ps
T846 /workspace/coverage/default/2.lc_ctrl_errors.160947280 Jul 10 05:01:17 PM PDT 24 Jul 10 05:01:33 PM PDT 24 4710903734 ps
T847 /workspace/coverage/default/15.lc_ctrl_sec_token_mux.621922340 Jul 10 05:02:57 PM PDT 24 Jul 10 05:03:15 PM PDT 24 491311809 ps
T848 /workspace/coverage/default/31.lc_ctrl_errors.4267291896 Jul 10 05:04:03 PM PDT 24 Jul 10 05:04:18 PM PDT 24 5307893450 ps
T849 /workspace/coverage/default/47.lc_ctrl_stress_all.2718061147 Jul 10 05:05:12 PM PDT 24 Jul 10 05:09:56 PM PDT 24 18363765885 ps
T850 /workspace/coverage/default/47.lc_ctrl_sec_mubi.2845895353 Jul 10 05:05:09 PM PDT 24 Jul 10 05:05:27 PM PDT 24 467915613 ps
T851 /workspace/coverage/default/19.lc_ctrl_alert_test.258513113 Jul 10 05:03:19 PM PDT 24 Jul 10 05:03:21 PM PDT 24 35704419 ps
T852 /workspace/coverage/default/24.lc_ctrl_smoke.1273411048 Jul 10 05:03:37 PM PDT 24 Jul 10 05:03:40 PM PDT 24 76410941 ps
T853 /workspace/coverage/default/17.lc_ctrl_jtag_access.272946339 Jul 10 05:03:08 PM PDT 24 Jul 10 05:03:12 PM PDT 24 50589202 ps
T854 /workspace/coverage/default/38.lc_ctrl_state_post_trans.2905193377 Jul 10 05:04:27 PM PDT 24 Jul 10 05:04:37 PM PDT 24 259115956 ps
T855 /workspace/coverage/default/24.lc_ctrl_sec_token_digest.3481034404 Jul 10 05:03:42 PM PDT 24 Jul 10 05:03:57 PM PDT 24 302209104 ps
T856 /workspace/coverage/default/4.lc_ctrl_sec_token_digest.3169041313 Jul 10 05:01:49 PM PDT 24 Jul 10 05:02:00 PM PDT 24 909804091 ps
T857 /workspace/coverage/default/25.lc_ctrl_sec_mubi.3010212036 Jul 10 05:03:42 PM PDT 24 Jul 10 05:04:00 PM PDT 24 679427805 ps
T858 /workspace/coverage/default/41.lc_ctrl_security_escalation.2359045795 Jul 10 05:04:34 PM PDT 24 Jul 10 05:04:51 PM PDT 24 787222894 ps
T859 /workspace/coverage/default/29.lc_ctrl_alert_test.3901178837 Jul 10 05:03:56 PM PDT 24 Jul 10 05:03:58 PM PDT 24 40539959 ps
T860 /workspace/coverage/default/8.lc_ctrl_state_post_trans.838577438 Jul 10 05:02:11 PM PDT 24 Jul 10 05:02:17 PM PDT 24 389486518 ps
T861 /workspace/coverage/default/7.lc_ctrl_regwen_during_op.1412215546 Jul 10 05:02:03 PM PDT 24 Jul 10 05:02:21 PM PDT 24 244844035 ps
T862 /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.439791978 Jul 10 05:02:53 PM PDT 24 Jul 10 05:02:56 PM PDT 24 15532296 ps
T137 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.943842690 Jul 10 05:15:45 PM PDT 24 Jul 10 05:16:00 PM PDT 24 27465646 ps
T131 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.576620553 Jul 10 05:15:39 PM PDT 24 Jul 10 05:15:51 PM PDT 24 18937501 ps
T161 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.4241824549 Jul 10 05:15:59 PM PDT 24 Jul 10 05:16:10 PM PDT 24 85622276 ps
T138 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3391081096 Jul 10 05:15:55 PM PDT 24 Jul 10 05:16:05 PM PDT 24 15937180 ps
T124 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.594330708 Jul 10 05:15:39 PM PDT 24 Jul 10 05:15:53 PM PDT 24 266422912 ps
T132 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1705335750 Jul 10 05:15:51 PM PDT 24 Jul 10 05:16:04 PM PDT 24 27104956 ps
T863 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1328550306 Jul 10 05:15:34 PM PDT 24 Jul 10 05:15:45 PM PDT 24 21084634 ps
T864 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.4205331205 Jul 10 05:15:41 PM PDT 24 Jul 10 05:15:54 PM PDT 24 13276507 ps
T157 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.4080324091 Jul 10 05:15:37 PM PDT 24 Jul 10 05:15:50 PM PDT 24 791826916 ps
T127 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1427407180 Jul 10 05:15:43 PM PDT 24 Jul 10 05:15:56 PM PDT 24 117279079 ps
T199 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1300209966 Jul 10 05:15:41 PM PDT 24 Jul 10 05:15:56 PM PDT 24 240495186 ps
T865 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2556977767 Jul 10 05:15:33 PM PDT 24 Jul 10 05:15:43 PM PDT 24 50633025 ps
T158 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3088471397 Jul 10 05:15:39 PM PDT 24 Jul 10 05:15:53 PM PDT 24 122613236 ps
T125 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1098314854 Jul 10 05:15:53 PM PDT 24 Jul 10 05:16:07 PM PDT 24 110516967 ps
T209 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1703957996 Jul 10 05:15:40 PM PDT 24 Jul 10 05:15:53 PM PDT 24 139250930 ps
T126 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3866743532 Jul 10 05:15:50 PM PDT 24 Jul 10 05:16:06 PM PDT 24 457675248 ps
T129 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2333557244 Jul 10 05:15:39 PM PDT 24 Jul 10 05:15:52 PM PDT 24 81002239 ps
T128 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.4105414872 Jul 10 05:15:51 PM PDT 24 Jul 10 05:16:04 PM PDT 24 61833661 ps
T160 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1246216207 Jul 10 05:15:39 PM PDT 24 Jul 10 05:15:51 PM PDT 24 95891129 ps
T147 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3489865411 Jul 10 05:15:42 PM PDT 24 Jul 10 05:15:57 PM PDT 24 322988927 ps
T130 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2107149181 Jul 10 05:15:42 PM PDT 24 Jul 10 05:15:57 PM PDT 24 83215809 ps
T210 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.927426407 Jul 10 05:15:50 PM PDT 24 Jul 10 05:16:04 PM PDT 24 154238605 ps
T866 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.899458331 Jul 10 05:15:40 PM PDT 24 Jul 10 05:16:11 PM PDT 24 2353052011 ps
T159 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3669307522 Jul 10 05:15:41 PM PDT 24 Jul 10 05:15:56 PM PDT 24 116639267 ps
T867 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2023894800 Jul 10 05:15:41 PM PDT 24 Jul 10 05:15:55 PM PDT 24 474599772 ps
T211 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.843379260 Jul 10 05:15:45 PM PDT 24 Jul 10 05:15:59 PM PDT 24 66099453 ps
T868 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.487358336 Jul 10 05:15:41 PM PDT 24 Jul 10 05:15:54 PM PDT 24 224876405 ps
T200 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.4095187489 Jul 10 05:15:41 PM PDT 24 Jul 10 05:15:54 PM PDT 24 83303030 ps
T144 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2086648326 Jul 10 05:15:47 PM PDT 24 Jul 10 05:16:03 PM PDT 24 86745752 ps
T173 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2389033143 Jul 10 05:15:40 PM PDT 24 Jul 10 05:15:55 PM PDT 24 434905177 ps
T212 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2270296338 Jul 10 05:15:42 PM PDT 24 Jul 10 05:15:56 PM PDT 24 27472779 ps
T170 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2817345788 Jul 10 05:15:38 PM PDT 24 Jul 10 05:15:50 PM PDT 24 67169854 ps
T869 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1407797362 Jul 10 05:15:45 PM PDT 24 Jul 10 05:16:19 PM PDT 24 2599419443 ps
T152 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2974018239 Jul 10 05:15:48 PM PDT 24 Jul 10 05:16:04 PM PDT 24 74485825 ps
T870 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.22695221 Jul 10 05:15:53 PM PDT 24 Jul 10 05:16:04 PM PDT 24 13930278 ps
T871 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1890796740 Jul 10 05:15:41 PM PDT 24 Jul 10 05:15:54 PM PDT 24 85388812 ps
T872 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1638956285 Jul 10 05:15:42 PM PDT 24 Jul 10 05:15:57 PM PDT 24 61037795 ps
T136 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3279764020 Jul 10 05:16:17 PM PDT 24 Jul 10 05:16:21 PM PDT 24 32313024 ps
T873 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1863776707 Jul 10 05:15:47 PM PDT 24 Jul 10 05:16:01 PM PDT 24 58484905 ps
T874 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3623973048 Jul 10 05:15:40 PM PDT 24 Jul 10 05:15:57 PM PDT 24 377182446 ps
T133 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3456743026 Jul 10 05:15:50 PM PDT 24 Jul 10 05:16:05 PM PDT 24 232723723 ps
T145 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.396349057 Jul 10 05:16:08 PM PDT 24 Jul 10 05:16:14 PM PDT 24 357326189 ps
T875 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.9165544 Jul 10 05:15:40 PM PDT 24 Jul 10 05:15:54 PM PDT 24 861259930 ps
T140 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1506799744 Jul 10 05:16:04 PM PDT 24 Jul 10 05:16:13 PM PDT 24 1023581304 ps
T876 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.3965051020 Jul 10 05:15:51 PM PDT 24 Jul 10 05:16:03 PM PDT 24 50043522 ps
T150 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.4138291277 Jul 10 05:15:59 PM PDT 24 Jul 10 05:16:10 PM PDT 24 251178468 ps
T877 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2954115345 Jul 10 05:15:34 PM PDT 24 Jul 10 05:15:45 PM PDT 24 87831440 ps
T213 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3894956252 Jul 10 05:15:39 PM PDT 24 Jul 10 05:15:51 PM PDT 24 51546395 ps
T878 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1377927331 Jul 10 05:15:48 PM PDT 24 Jul 10 05:16:15 PM PDT 24 7067911470 ps
T171 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.114689031 Jul 10 05:15:39 PM PDT 24 Jul 10 05:15:51 PM PDT 24 45722434 ps
T879 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2818397144 Jul 10 05:15:42 PM PDT 24 Jul 10 05:15:55 PM PDT 24 173101938 ps
T214 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1186175108 Jul 10 05:15:46 PM PDT 24 Jul 10 05:16:00 PM PDT 24 41447105 ps
T880 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3441185734 Jul 10 05:15:41 PM PDT 24 Jul 10 05:15:54 PM PDT 24 106670262 ps
T881 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2894407832 Jul 10 05:15:32 PM PDT 24 Jul 10 05:15:40 PM PDT 24 55438242 ps
T134 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1549091583 Jul 10 05:15:55 PM PDT 24 Jul 10 05:16:08 PM PDT 24 78425977 ps
T882 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3963622501 Jul 10 05:15:59 PM PDT 24 Jul 10 05:16:09 PM PDT 24 36304536 ps
T883 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2187285034 Jul 10 05:15:51 PM PDT 24 Jul 10 05:16:08 PM PDT 24 193527072 ps
T151 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1259557427 Jul 10 05:15:58 PM PDT 24 Jul 10 05:16:10 PM PDT 24 954844762 ps
T884 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.4073550584 Jul 10 05:15:56 PM PDT 24 Jul 10 05:16:08 PM PDT 24 25306466 ps
T885 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1986214207 Jul 10 05:15:55 PM PDT 24 Jul 10 05:16:09 PM PDT 24 2847937438 ps
T886 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.337028170 Jul 10 05:15:43 PM PDT 24 Jul 10 05:15:56 PM PDT 24 21436892 ps
T887 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.941869788 Jul 10 05:15:54 PM PDT 24 Jul 10 05:16:05 PM PDT 24 50014792 ps
T888 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1791312794 Jul 10 05:15:50 PM PDT 24 Jul 10 05:16:04 PM PDT 24 67984398 ps
T889 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1010705709 Jul 10 05:15:53 PM PDT 24 Jul 10 05:16:05 PM PDT 24 18661359 ps
T890 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1392255335 Jul 10 05:15:45 PM PDT 24 Jul 10 05:16:00 PM PDT 24 99433408 ps
T891 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1038998007 Jul 10 05:15:53 PM PDT 24 Jul 10 05:16:05 PM PDT 24 28126638 ps
T892 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2816613561 Jul 10 05:15:40 PM PDT 24 Jul 10 05:15:53 PM PDT 24 65456893 ps
T893 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.720336223 Jul 10 05:15:54 PM PDT 24 Jul 10 05:16:05 PM PDT 24 29720114 ps
T894 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.4231563959 Jul 10 05:15:44 PM PDT 24 Jul 10 05:15:58 PM PDT 24 86110409 ps
T895 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2040389820 Jul 10 05:15:39 PM PDT 24 Jul 10 05:15:53 PM PDT 24 901293995 ps
T896 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3941781540 Jul 10 05:15:50 PM PDT 24 Jul 10 05:16:04 PM PDT 24 25999067 ps
T897 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.532551654 Jul 10 05:15:32 PM PDT 24 Jul 10 05:15:41 PM PDT 24 70953014 ps
T898 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.1508408276 Jul 10 05:15:51 PM PDT 24 Jul 10 05:16:04 PM PDT 24 56517374 ps
T201 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3471780513 Jul 10 05:15:41 PM PDT 24 Jul 10 05:15:55 PM PDT 24 134534317 ps
T899 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2085133516 Jul 10 05:15:43 PM PDT 24 Jul 10 05:15:58 PM PDT 24 86993175 ps
T900 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3620633706 Jul 10 05:15:52 PM PDT 24 Jul 10 05:16:05 PM PDT 24 21382442 ps
T901 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.196908011 Jul 10 05:15:41 PM PDT 24 Jul 10 05:15:53 PM PDT 24 29580555 ps
T902 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1163267638 Jul 10 05:15:46 PM PDT 24 Jul 10 05:16:01 PM PDT 24 85898766 ps
T903 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1239798807 Jul 10 05:15:51 PM PDT 24 Jul 10 05:16:04 PM PDT 24 17334894 ps
T904 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1416678220 Jul 10 05:15:33 PM PDT 24 Jul 10 05:15:50 PM PDT 24 701352539 ps
T905 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3011249818 Jul 10 05:15:39 PM PDT 24 Jul 10 05:15:51 PM PDT 24 730727407 ps
T906 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.611010321 Jul 10 05:15:34 PM PDT 24 Jul 10 05:15:44 PM PDT 24 95522796 ps
T202 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2628864800 Jul 10 05:15:51 PM PDT 24 Jul 10 05:16:04 PM PDT 24 37522712 ps
T156 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1640570301 Jul 10 05:15:41 PM PDT 24 Jul 10 05:15:54 PM PDT 24 43851817 ps
T907 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2382008824 Jul 10 05:15:42 PM PDT 24 Jul 10 05:15:56 PM PDT 24 39082662 ps
T908 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2820965745 Jul 10 05:15:51 PM PDT 24 Jul 10 05:16:04 PM PDT 24 18052351 ps
T909 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3489420735 Jul 10 05:15:37 PM PDT 24 Jul 10 05:15:49 PM PDT 24 88756761 ps
T910 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.679560533 Jul 10 05:16:02 PM PDT 24 Jul 10 05:16:11 PM PDT 24 58939736 ps
T203 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3808858562 Jul 10 05:15:49 PM PDT 24 Jul 10 05:16:02 PM PDT 24 61861359 ps
T911 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2816991485 Jul 10 05:15:35 PM PDT 24 Jul 10 05:16:06 PM PDT 24 1672249664 ps
T146 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2017716271 Jul 10 05:15:38 PM PDT 24 Jul 10 05:15:49 PM PDT 24 54411550 ps
T912 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1936921952 Jul 10 05:15:57 PM PDT 24 Jul 10 05:16:08 PM PDT 24 170496472 ps
T149 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2230821795 Jul 10 05:15:50 PM PDT 24 Jul 10 05:16:05 PM PDT 24 110463166 ps
T913 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2235072545 Jul 10 05:15:45 PM PDT 24 Jul 10 05:15:59 PM PDT 24 128298309 ps
T914 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.740321271 Jul 10 05:15:57 PM PDT 24 Jul 10 05:16:10 PM PDT 24 134012864 ps
T915 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1659519028 Jul 10 05:15:40 PM PDT 24 Jul 10 05:15:56 PM PDT 24 359579320 ps
T916 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2640647938 Jul 10 05:15:51 PM PDT 24 Jul 10 05:16:04 PM PDT 24 24523349 ps
T148 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2337260455 Jul 10 05:15:59 PM PDT 24 Jul 10 05:16:11 PM PDT 24 234423168 ps
T917 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.299970606 Jul 10 05:15:53 PM PDT 24 Jul 10 05:16:05 PM PDT 24 104821681 ps
T918 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1377391980 Jul 10 05:15:41 PM PDT 24 Jul 10 05:16:06 PM PDT 24 2106521149 ps
T141 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2041976621 Jul 10 05:15:34 PM PDT 24 Jul 10 05:15:45 PM PDT 24 667842381 ps
T919 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3356607990 Jul 10 05:15:45 PM PDT 24 Jul 10 05:16:06 PM PDT 24 335582767 ps
T920 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1505604185 Jul 10 05:15:40 PM PDT 24 Jul 10 05:15:52 PM PDT 24 67138002 ps
T921 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2921983980 Jul 10 05:15:55 PM PDT 24 Jul 10 05:16:06 PM PDT 24 14675673 ps
T922 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1489729373 Jul 10 05:15:47 PM PDT 24 Jul 10 05:16:08 PM PDT 24 736477608 ps
T923 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2131972420 Jul 10 05:15:50 PM PDT 24 Jul 10 05:16:06 PM PDT 24 379800974 ps
T924 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3315193057 Jul 10 05:16:00 PM PDT 24 Jul 10 05:16:10 PM PDT 24 125725874 ps
T925 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.613225851 Jul 10 05:15:47 PM PDT 24 Jul 10 05:16:01 PM PDT 24 59424694 ps
T926 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2678632939 Jul 10 05:15:38 PM PDT 24 Jul 10 05:15:51 PM PDT 24 206025232 ps
T927 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2774680349 Jul 10 05:15:43 PM PDT 24 Jul 10 05:15:56 PM PDT 24 27877750 ps
T928 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2760933265 Jul 10 05:15:41 PM PDT 24 Jul 10 05:15:54 PM PDT 24 53686415 ps
T929 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.4107013473 Jul 10 05:15:41 PM PDT 24 Jul 10 05:15:56 PM PDT 24 2097975454 ps
T930 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3332243360 Jul 10 05:16:03 PM PDT 24 Jul 10 05:16:11 PM PDT 24 39021572 ps
T931 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1078713995 Jul 10 05:15:52 PM PDT 24 Jul 10 05:16:04 PM PDT 24 43567059 ps
T932 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3510327672 Jul 10 05:15:34 PM PDT 24 Jul 10 05:15:45 PM PDT 24 36422483 ps
T153 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3508367382 Jul 10 05:15:57 PM PDT 24 Jul 10 05:16:11 PM PDT 24 759966366 ps
T933 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2797289652 Jul 10 05:15:57 PM PDT 24 Jul 10 05:16:09 PM PDT 24 256230372 ps
T934 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3632779612 Jul 10 05:15:54 PM PDT 24 Jul 10 05:16:05 PM PDT 24 335880881 ps
T935 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.4012563866 Jul 10 05:15:59 PM PDT 24 Jul 10 05:16:10 PM PDT 24 143587051 ps
T936 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1734706609 Jul 10 05:15:50 PM PDT 24 Jul 10 05:16:15 PM PDT 24 3848560903 ps
T937 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.206342979 Jul 10 05:15:41 PM PDT 24 Jul 10 05:15:55 PM PDT 24 148915818 ps
T938 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2881528307 Jul 10 05:15:41 PM PDT 24 Jul 10 05:15:54 PM PDT 24 97009284 ps
T939 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.376582859 Jul 10 05:15:57 PM PDT 24 Jul 10 05:16:08 PM PDT 24 135342442 ps
T940 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1354470473 Jul 10 05:15:40 PM PDT 24 Jul 10 05:15:52 PM PDT 24 12521254 ps
T941 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3735351808 Jul 10 05:15:39 PM PDT 24 Jul 10 05:15:57 PM PDT 24 266625568 ps
T942 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2329417711 Jul 10 05:15:52 PM PDT 24 Jul 10 05:16:05 PM PDT 24 24504693 ps
T204 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2358109601 Jul 10 05:15:39 PM PDT 24 Jul 10 05:15:50 PM PDT 24 18869277 ps
T943 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.4014190641 Jul 10 05:15:42 PM PDT 24 Jul 10 05:15:56 PM PDT 24 32195122 ps
T944 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1127544217 Jul 10 05:15:52 PM PDT 24 Jul 10 05:16:04 PM PDT 24 25300124 ps
T945 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2979007758 Jul 10 05:15:59 PM PDT 24 Jul 10 05:16:09 PM PDT 24 92827555 ps
T946 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3517498037 Jul 10 05:16:02 PM PDT 24 Jul 10 05:16:11 PM PDT 24 544640457 ps
T947 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1261316972 Jul 10 05:15:45 PM PDT 24 Jul 10 05:16:05 PM PDT 24 737166371 ps
T948 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2179836441 Jul 10 05:15:46 PM PDT 24 Jul 10 05:16:01 PM PDT 24 1014503012 ps
T949 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3141125385 Jul 10 05:15:44 PM PDT 24 Jul 10 05:15:57 PM PDT 24 45170446 ps
T950 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3686451960 Jul 10 05:15:45 PM PDT 24 Jul 10 05:15:59 PM PDT 24 180179953 ps
T951 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.170761271 Jul 10 05:15:57 PM PDT 24 Jul 10 05:16:10 PM PDT 24 586918319 ps
T952 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.950713026 Jul 10 05:15:46 PM PDT 24 Jul 10 05:16:19 PM PDT 24 3397158599 ps
T953 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2613618551 Jul 10 05:15:44 PM PDT 24 Jul 10 05:15:58 PM PDT 24 52511450 ps
T954 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3375484938 Jul 10 05:15:49 PM PDT 24 Jul 10 05:16:04 PM PDT 24 81964341 ps
T154 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3386061355 Jul 10 05:15:38 PM PDT 24 Jul 10 05:15:50 PM PDT 24 235810999 ps
T955 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2373269609 Jul 10 05:15:46 PM PDT 24 Jul 10 05:16:00 PM PDT 24 333632030 ps
T205 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1367428084 Jul 10 05:15:56 PM PDT 24 Jul 10 05:16:07 PM PDT 24 12587995 ps
T956 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.3002299175 Jul 10 05:15:54 PM PDT 24 Jul 10 05:16:06 PM PDT 24 28689510 ps
T206 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.474484051 Jul 10 05:15:35 PM PDT 24 Jul 10 05:15:45 PM PDT 24 56151082 ps
T957 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.358255609 Jul 10 05:15:44 PM PDT 24 Jul 10 05:15:58 PM PDT 24 13630482 ps
T958 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.627712906 Jul 10 05:15:54 PM PDT 24 Jul 10 05:16:06 PM PDT 24 50505715 ps
T959 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.90301720 Jul 10 05:15:41 PM PDT 24 Jul 10 05:15:57 PM PDT 24 549313096 ps
T960 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.913939424 Jul 10 05:15:53 PM PDT 24 Jul 10 05:16:06 PM PDT 24 88627202 ps
T961 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2551661876 Jul 10 05:15:39 PM PDT 24 Jul 10 05:15:55 PM PDT 24 179029611 ps
T962 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.978632186 Jul 10 05:15:40 PM PDT 24 Jul 10 05:16:01 PM PDT 24 2150235666 ps
T963 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3101629124 Jul 10 05:15:54 PM PDT 24 Jul 10 05:16:06 PM PDT 24 21135910 ps
T207 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.155014652 Jul 10 05:15:39 PM PDT 24 Jul 10 05:15:51 PM PDT 24 297517754 ps
T142 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3563636625 Jul 10 05:16:00 PM PDT 24 Jul 10 05:16:11 PM PDT 24 214479344 ps
T964 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.543474227 Jul 10 05:15:46 PM PDT 24 Jul 10 05:16:02 PM PDT 24 975996739 ps
T965 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.1224546283 Jul 10 05:15:44 PM PDT 24 Jul 10 05:15:58 PM PDT 24 78367770 ps
T139 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2051581791 Jul 10 05:16:09 PM PDT 24 Jul 10 05:16:16 PM PDT 24 141713672 ps
T966 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3497263988 Jul 10 05:15:36 PM PDT 24 Jul 10 05:15:47 PM PDT 24 658459885 ps
T967 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1247681916 Jul 10 05:15:49 PM PDT 24 Jul 10 05:16:04 PM PDT 24 47069225 ps
T968 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.4238466869 Jul 10 05:15:32 PM PDT 24 Jul 10 05:15:41 PM PDT 24 159908195 ps
T969 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2928208884 Jul 10 05:16:02 PM PDT 24 Jul 10 05:16:11 PM PDT 24 73919948 ps
T970 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1596175189 Jul 10 05:15:41 PM PDT 24 Jul 10 05:16:12 PM PDT 24 8339102890 ps
T971 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3960311981 Jul 10 05:15:53 PM PDT 24 Jul 10 05:16:05 PM PDT 24 14777707 ps
T972 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3835760918 Jul 10 05:15:40 PM PDT 24 Jul 10 05:15:52 PM PDT 24 15988517 ps
T973 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.4239671414 Jul 10 05:15:45 PM PDT 24 Jul 10 05:16:02 PM PDT 24 161306080 ps
T143 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3580194900 Jul 10 05:15:56 PM PDT 24 Jul 10 05:16:09 PM PDT 24 445684469 ps
T974 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2320391391 Jul 10 05:15:51 PM PDT 24 Jul 10 05:16:05 PM PDT 24 160269261 ps
T975 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2093020369 Jul 10 05:15:51 PM PDT 24 Jul 10 05:16:05 PM PDT 24 20331679 ps
T155 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.25596847 Jul 10 05:15:50 PM PDT 24 Jul 10 05:16:05 PM PDT 24 73751479 ps
T976 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3382541283 Jul 10 05:15:40 PM PDT 24 Jul 10 05:15:54 PM PDT 24 31414278 ps
T977 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.4242343445 Jul 10 05:15:43 PM PDT 24 Jul 10 05:15:56 PM PDT 24 63393965 ps
T208 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3097548394 Jul 10 05:15:55 PM PDT 24 Jul 10 05:16:05 PM PDT 24 16072995 ps
T978 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2523522548 Jul 10 05:15:57 PM PDT 24 Jul 10 05:16:10 PM PDT 24 555784006 ps
T979 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.169441598 Jul 10 05:15:59 PM PDT 24 Jul 10 05:16:11 PM PDT 24 63855563 ps
T980 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3782695499 Jul 10 05:15:55 PM PDT 24 Jul 10 05:16:06 PM PDT 24 80157742 ps
T981 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3046133331 Jul 10 05:15:40 PM PDT 24 Jul 10 05:15:53 PM PDT 24 85195004 ps
T982 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2696528266 Jul 10 05:15:38 PM PDT 24 Jul 10 05:15:50 PM PDT 24 55639913 ps
T983 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3767776055 Jul 10 05:15:59 PM PDT 24 Jul 10 05:16:09 PM PDT 24 38652848 ps
T984 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.929311360 Jul 10 05:15:47 PM PDT 24 Jul 10 05:16:07 PM PDT 24 1122103132 ps
T985 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1399125365 Jul 10 05:15:41 PM PDT 24 Jul 10 05:15:56 PM PDT 24 563502223 ps
T135 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1945535689 Jul 10 05:15:55 PM PDT 24 Jul 10 05:16:07 PM PDT 24 116063578 ps
T986 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.291551728 Jul 10 05:15:53 PM PDT 24 Jul 10 05:16:04 PM PDT 24 63325234 ps
T987 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3102170015 Jul 10 05:16:03 PM PDT 24 Jul 10 05:16:11 PM PDT 24 40483194 ps
T988 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2346999497 Jul 10 05:15:51 PM PDT 24 Jul 10 05:16:04 PM PDT 24 26990150 ps
T989 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.445200830 Jul 10 05:15:38 PM PDT 24 Jul 10 05:15:56 PM PDT 24 735779169 ps
T990 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.48073107 Jul 10 05:15:52 PM PDT 24 Jul 10 05:16:05 PM PDT 24 18144823 ps

Test location /workspace/coverage/default/11.lc_ctrl_errors.2366572640
Short name T12
Test name
Test status
Simulation time 1201088498 ps
CPU time 9.84 seconds
Started Jul 10 05:02:35 PM PDT 24
Finished Jul 10 05:02:48 PM PDT 24
Peak memory 225460 kb
Host smart-50a42718-d6bc-4999-9aee-15d039fc2afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366572640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.2366572640
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.2407721632
Short name T20
Test name
Test status
Simulation time 20496209669 ps
CPU time 411.56 seconds
Started Jul 10 05:02:19 PM PDT 24
Finished Jul 10 05:09:12 PM PDT 24
Peak memory 437936 kb
Host smart-ed03f612-0c4e-4386-b301-5a479584c36f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2407721632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.2407721632
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.3760543809
Short name T16
Test name
Test status
Simulation time 328488801 ps
CPU time 9.83 seconds
Started Jul 10 05:04:27 PM PDT 24
Finished Jul 10 05:04:41 PM PDT 24
Peak memory 217964 kb
Host smart-0fca2436-112b-42dd-abdc-da1141e11713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760543809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.3760543809
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.3075136370
Short name T45
Test name
Test status
Simulation time 6043461762 ps
CPU time 13.75 seconds
Started Jul 10 05:04:26 PM PDT 24
Finished Jul 10 05:04:42 PM PDT 24
Peak memory 219400 kb
Host smart-a3e7b1e7-4557-4c14-9108-73664e44ae68
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075136370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.3075136370
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.1208013335
Short name T55
Test name
Test status
Simulation time 2570819436 ps
CPU time 12.06 seconds
Started Jul 10 05:04:04 PM PDT 24
Finished Jul 10 05:04:18 PM PDT 24
Peak memory 225516 kb
Host smart-920ef423-6403-4134-86b1-7c475560a5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208013335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.1208013335
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.2702346559
Short name T41
Test name
Test status
Simulation time 15048833 ps
CPU time 0.81 seconds
Started Jul 10 05:04:00 PM PDT 24
Finished Jul 10 05:04:04 PM PDT 24
Peak memory 208232 kb
Host smart-840dafb6-5152-435c-8610-aa752ef10abf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702346559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.2702346559
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1427407180
Short name T127
Test name
Test status
Simulation time 117279079 ps
CPU time 1.57 seconds
Started Jul 10 05:15:43 PM PDT 24
Finished Jul 10 05:15:56 PM PDT 24
Peak memory 222356 kb
Host smart-e0968f2c-42ba-4738-8d3a-63a7ff20d2aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427407180 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.1427407180
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.591014736
Short name T58
Test name
Test status
Simulation time 441024515 ps
CPU time 36.56 seconds
Started Jul 10 05:01:35 PM PDT 24
Finished Jul 10 05:02:13 PM PDT 24
Peak memory 282696 kb
Host smart-fbf20e98-0c6a-46ca-90e0-f7d0c7c32ade
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591014736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.591014736
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.1308077261
Short name T244
Test name
Test status
Simulation time 738058167 ps
CPU time 8.88 seconds
Started Jul 10 05:01:08 PM PDT 24
Finished Jul 10 05:01:20 PM PDT 24
Peak memory 217716 kb
Host smart-372f8343-c24f-4549-a1ce-690718476fe6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308077261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.1
308077261
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.1706635780
Short name T23
Test name
Test status
Simulation time 22584913 ps
CPU time 1.24 seconds
Started Jul 10 05:03:38 PM PDT 24
Finished Jul 10 05:03:42 PM PDT 24
Peak memory 208428 kb
Host smart-d8915cf8-4625-43e9-9711-02d20f763e35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706635780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.1706635780
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.3134806612
Short name T166
Test name
Test status
Simulation time 33600153630 ps
CPU time 607.12 seconds
Started Jul 10 05:01:51 PM PDT 24
Finished Jul 10 05:12:01 PM PDT 24
Peak memory 383404 kb
Host smart-65b92d80-4c48-4ad8-abb4-cf1cecc336ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3134806612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.3134806612
Directory /workspace/4.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.530671478
Short name T30
Test name
Test status
Simulation time 1430869300 ps
CPU time 5.19 seconds
Started Jul 10 05:03:29 PM PDT 24
Finished Jul 10 05:03:38 PM PDT 24
Peak memory 217076 kb
Host smart-69ac11ad-0076-47b3-bfe7-2e7908bd3041
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530671478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.530671478
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3456743026
Short name T133
Test name
Test status
Simulation time 232723723 ps
CPU time 3.19 seconds
Started Jul 10 05:15:50 PM PDT 24
Finished Jul 10 05:16:05 PM PDT 24
Peak memory 217460 kb
Host smart-191ccb27-ef83-400e-9ba4-4eba4966678c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456743026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.3456743026
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3471780513
Short name T201
Test name
Test status
Simulation time 134534317 ps
CPU time 1.44 seconds
Started Jul 10 05:15:41 PM PDT 24
Finished Jul 10 05:15:55 PM PDT 24
Peak memory 209228 kb
Host smart-e6031e38-0047-4a51-9c5b-9c906af47eb8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471780513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.3471780513
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3088471397
Short name T158
Test name
Test status
Simulation time 122613236 ps
CPU time 3.25 seconds
Started Jul 10 05:15:39 PM PDT 24
Finished Jul 10 05:15:53 PM PDT 24
Peak memory 217368 kb
Host smart-279162b9-dfb0-4db6-91b1-1eeed28a67d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088471397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.3088471397
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1098314854
Short name T125
Test name
Test status
Simulation time 110516967 ps
CPU time 3.27 seconds
Started Jul 10 05:15:53 PM PDT 24
Finished Jul 10 05:16:07 PM PDT 24
Peak memory 218328 kb
Host smart-6f789b50-be02-402d-bc09-01186140de23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098314854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.1098314854
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.1485552705
Short name T5
Test name
Test status
Simulation time 3053644309 ps
CPU time 59.7 seconds
Started Jul 10 05:01:51 PM PDT 24
Finished Jul 10 05:02:53 PM PDT 24
Peak memory 218400 kb
Host smart-8ce310a3-0749-44a7-af18-ff39ffcf12e0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485552705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.1485552705
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.2747628217
Short name T92
Test name
Test status
Simulation time 26004768100 ps
CPU time 637.4 seconds
Started Jul 10 05:05:09 PM PDT 24
Finished Jul 10 05:15:51 PM PDT 24
Peak memory 496332 kb
Host smart-d4faa7b6-c4a0-49e9-8f88-261782cff947
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2747628217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all_with_rand_reset.2747628217
Directory /workspace/46.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1549091583
Short name T134
Test name
Test status
Simulation time 78425977 ps
CPU time 2.82 seconds
Started Jul 10 05:15:55 PM PDT 24
Finished Jul 10 05:16:08 PM PDT 24
Peak memory 222248 kb
Host smart-0849efb7-35fc-431c-aa56-958928f5783d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549091583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.1549091583
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.835683827
Short name T13
Test name
Test status
Simulation time 47924160 ps
CPU time 0.94 seconds
Started Jul 10 05:02:11 PM PDT 24
Finished Jul 10 05:02:13 PM PDT 24
Peak memory 208288 kb
Host smart-7c4673fe-2a49-47f0-b7d5-4e9cff52d95d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835683827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctr
l_volatile_unlock_smoke.835683827
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2041976621
Short name T141
Test name
Test status
Simulation time 667842381 ps
CPU time 3.3 seconds
Started Jul 10 05:15:34 PM PDT 24
Finished Jul 10 05:15:45 PM PDT 24
Peak memory 217376 kb
Host smart-07dbeb74-8672-4fa0-a36a-34de6988fdc4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041976621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.2041976621
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.2739614455
Short name T2
Test name
Test status
Simulation time 284869526 ps
CPU time 12.62 seconds
Started Jul 10 05:05:07 PM PDT 24
Finished Jul 10 05:05:25 PM PDT 24
Peak memory 225388 kb
Host smart-d1988104-3ab9-4a7f-bbf0-ebe18806a910
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739614455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.2739614455
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.812143504
Short name T122
Test name
Test status
Simulation time 53576665608 ps
CPU time 3196.7 seconds
Started Jul 10 05:03:38 PM PDT 24
Finished Jul 10 05:56:57 PM PDT 24
Peak memory 905920 kb
Host smart-ada319ee-e812-4134-b342-145b5e051e11
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=812143504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.812143504
Directory /workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3315193057
Short name T924
Test name
Test status
Simulation time 125725874 ps
CPU time 2.18 seconds
Started Jul 10 05:16:00 PM PDT 24
Finished Jul 10 05:16:10 PM PDT 24
Peak memory 217552 kb
Host smart-26d205b0-dc2a-434d-8cf6-e4bfed3bd739
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315193057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.3315193057
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1259557427
Short name T151
Test name
Test status
Simulation time 954844762 ps
CPU time 2.81 seconds
Started Jul 10 05:15:58 PM PDT 24
Finished Jul 10 05:16:10 PM PDT 24
Peak memory 221760 kb
Host smart-de05a55b-2a29-4e17-8555-4b9e37df01cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259557427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.1259557427
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2051581791
Short name T139
Test name
Test status
Simulation time 141713672 ps
CPU time 2.54 seconds
Started Jul 10 05:16:09 PM PDT 24
Finished Jul 10 05:16:16 PM PDT 24
Peak memory 222188 kb
Host smart-0157dc4e-b962-404e-9d99-e5aba91b2e9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051581791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.2051581791
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.114689031
Short name T171
Test name
Test status
Simulation time 45722434 ps
CPU time 2 seconds
Started Jul 10 05:15:39 PM PDT 24
Finished Jul 10 05:15:51 PM PDT 24
Peak memory 211168 kb
Host smart-815404b8-94c4-4dfd-94b9-86f504070572
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114689031 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.114689031
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.3624402578
Short name T93
Test name
Test status
Simulation time 114983185759 ps
CPU time 2050.23 seconds
Started Jul 10 05:04:23 PM PDT 24
Finished Jul 10 05:38:36 PM PDT 24
Peak memory 298860 kb
Host smart-dd1dfae1-b269-40d0-9b09-c7d2a66931a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3624402578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.3624402578
Directory /workspace/36.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.3637997891
Short name T103
Test name
Test status
Simulation time 4387491687 ps
CPU time 138.65 seconds
Started Jul 10 05:05:06 PM PDT 24
Finished Jul 10 05:07:30 PM PDT 24
Peak memory 271800 kb
Host smart-72ac9968-2582-46be-a128-f0032dc94a7f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3637997891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all_with_rand_reset.3637997891
Directory /workspace/44.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.1775341432
Short name T63
Test name
Test status
Simulation time 128577125 ps
CPU time 3.91 seconds
Started Jul 10 05:02:26 PM PDT 24
Finished Jul 10 05:02:32 PM PDT 24
Peak memory 214860 kb
Host smart-c9ecfefd-63d9-4e90-8866-93691bd5fe7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775341432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.1775341432
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2337260455
Short name T148
Test name
Test status
Simulation time 234423168 ps
CPU time 2.63 seconds
Started Jul 10 05:15:59 PM PDT 24
Finished Jul 10 05:16:11 PM PDT 24
Peak memory 217496 kb
Host smart-71f10fa6-e5dd-4e95-b1d5-1b0630ea7ab3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337260455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.2337260455
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3386061355
Short name T154
Test name
Test status
Simulation time 235810999 ps
CPU time 2.14 seconds
Started Jul 10 05:15:38 PM PDT 24
Finished Jul 10 05:15:50 PM PDT 24
Peak memory 221740 kb
Host smart-58ec9b99-b268-4c6a-829b-3d2573215855
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386061355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.3386061355
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2974018239
Short name T152
Test name
Test status
Simulation time 74485825 ps
CPU time 3.48 seconds
Started Jul 10 05:15:48 PM PDT 24
Finished Jul 10 05:16:04 PM PDT 24
Peak memory 217436 kb
Host smart-4a30871d-4c64-489f-941e-d5ab108c5c81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974018239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.2974018239
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.3742995829
Short name T215
Test name
Test status
Simulation time 10570737 ps
CPU time 0.94 seconds
Started Jul 10 05:01:06 PM PDT 24
Finished Jul 10 05:01:07 PM PDT 24
Peak memory 208596 kb
Host smart-601c0e51-149b-4268-9042-2e3555e221ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742995829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.3742995829
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.3696807343
Short name T56
Test name
Test status
Simulation time 191747404 ps
CPU time 6.31 seconds
Started Jul 10 05:03:09 PM PDT 24
Finished Jul 10 05:03:18 PM PDT 24
Peak memory 223884 kb
Host smart-ebfb32ae-1e84-4304-83c0-6fdece5bdd96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696807343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.3696807343
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.1099352038
Short name T217
Test name
Test status
Simulation time 30949642 ps
CPU time 0.78 seconds
Started Jul 10 05:01:57 PM PDT 24
Finished Jul 10 05:01:59 PM PDT 24
Peak memory 208432 kb
Host smart-5bf466b9-0bcb-46e9-a019-b56c9e5666ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099352038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.1099352038
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.3177291416
Short name T218
Test name
Test status
Simulation time 69024320 ps
CPU time 0.92 seconds
Started Jul 10 05:02:24 PM PDT 24
Finished Jul 10 05:02:27 PM PDT 24
Peak memory 208300 kb
Host smart-e07d1cc8-c197-434c-8933-d12c12409ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177291416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.3177291416
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.1808923296
Short name T3
Test name
Test status
Simulation time 461977570 ps
CPU time 29.08 seconds
Started Jul 10 05:04:24 PM PDT 24
Finished Jul 10 05:04:56 PM PDT 24
Peak memory 250412 kb
Host smart-03bba788-9a3d-4e45-a622-65ff79a2f3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808923296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.1808923296
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2230821795
Short name T149
Test name
Test status
Simulation time 110463166 ps
CPU time 2.62 seconds
Started Jul 10 05:15:50 PM PDT 24
Finished Jul 10 05:16:05 PM PDT 24
Peak memory 221540 kb
Host smart-d0c5c071-94e6-4d23-a6cc-d3406049b3ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230821795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.2230821795
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.4105414872
Short name T128
Test name
Test status
Simulation time 61833661 ps
CPU time 2.01 seconds
Started Jul 10 05:15:51 PM PDT 24
Finished Jul 10 05:16:04 PM PDT 24
Peak memory 221944 kb
Host smart-c97ed2aa-da32-4b45-aaec-eba581ef98b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105414872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.4105414872
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.25596847
Short name T155
Test name
Test status
Simulation time 73751479 ps
CPU time 2.61 seconds
Started Jul 10 05:15:50 PM PDT 24
Finished Jul 10 05:16:05 PM PDT 24
Peak memory 217524 kb
Host smart-eb1b771f-10d2-460c-91cf-3c48f1c23b7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25596847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_er
r.25596847
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.2805255384
Short name T52
Test name
Test status
Simulation time 3852652435 ps
CPU time 15.07 seconds
Started Jul 10 05:01:42 PM PDT 24
Finished Jul 10 05:02:00 PM PDT 24
Peak memory 217888 kb
Host smart-39afb0f0-0916-4bf1-892a-28d3a758de4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805255384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.2805255384
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.1824625320
Short name T38
Test name
Test status
Simulation time 244745232 ps
CPU time 24.26 seconds
Started Jul 10 05:03:20 PM PDT 24
Finished Jul 10 05:03:46 PM PDT 24
Peak memory 250412 kb
Host smart-280750a9-1b2e-46d8-b7aa-37a399679b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824625320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.1824625320
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.625170764
Short name T6
Test name
Test status
Simulation time 3234574736 ps
CPU time 107.08 seconds
Started Jul 10 05:01:02 PM PDT 24
Finished Jul 10 05:02:50 PM PDT 24
Peak memory 283092 kb
Host smart-ed10ab4b-81f0-435d-a548-ddbd19969414
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625170764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_state_failure.625170764
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.576620553
Short name T131
Test name
Test status
Simulation time 18937501 ps
CPU time 1.17 seconds
Started Jul 10 05:15:39 PM PDT 24
Finished Jul 10 05:15:51 PM PDT 24
Peak memory 209176 kb
Host smart-fef61656-3daf-4b42-8ac8-7a1bca3e9a42
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576620553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasing
.576620553
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2556977767
Short name T865
Test name
Test status
Simulation time 50633025 ps
CPU time 1.53 seconds
Started Jul 10 05:15:33 PM PDT 24
Finished Jul 10 05:15:43 PM PDT 24
Peak memory 217372 kb
Host smart-ee7e3688-1596-4d45-bc2a-e21f46b8e830
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556977767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.2556977767
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1328550306
Short name T863
Test name
Test status
Simulation time 21084634 ps
CPU time 1.29 seconds
Started Jul 10 05:15:34 PM PDT 24
Finished Jul 10 05:15:45 PM PDT 24
Peak memory 211292 kb
Host smart-cbe3213d-66cb-4492-a3cb-3aa5ce3e7b2b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328550306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.1328550306
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2017716271
Short name T146
Test name
Test status
Simulation time 54411550 ps
CPU time 1.35 seconds
Started Jul 10 05:15:38 PM PDT 24
Finished Jul 10 05:15:49 PM PDT 24
Peak memory 219228 kb
Host smart-a5e5e7ff-610d-455e-afb7-7648518bc19d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017716271 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.2017716271
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2358109601
Short name T204
Test name
Test status
Simulation time 18869277 ps
CPU time 0.93 seconds
Started Jul 10 05:15:39 PM PDT 24
Finished Jul 10 05:15:50 PM PDT 24
Peak memory 209224 kb
Host smart-e589376a-853a-4c76-b8c2-c7388737ae22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358109601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.2358109601
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3497263988
Short name T966
Test name
Test status
Simulation time 658459885 ps
CPU time 1.52 seconds
Started Jul 10 05:15:36 PM PDT 24
Finished Jul 10 05:15:47 PM PDT 24
Peak memory 209032 kb
Host smart-c23c55ea-08a1-48e6-97d3-307246dd3c29
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497263988 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.3497263988
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3735351808
Short name T941
Test name
Test status
Simulation time 266625568 ps
CPU time 6.93 seconds
Started Jul 10 05:15:39 PM PDT 24
Finished Jul 10 05:15:57 PM PDT 24
Peak memory 216988 kb
Host smart-01a1557b-27d5-4d9b-b772-1796ed58e219
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735351808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.3735351808
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1416678220
Short name T904
Test name
Test status
Simulation time 701352539 ps
CPU time 8.09 seconds
Started Jul 10 05:15:33 PM PDT 24
Finished Jul 10 05:15:50 PM PDT 24
Peak memory 208736 kb
Host smart-1ef2ccc6-2e98-47d8-bb68-42a025db0d73
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416678220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.1416678220
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1246216207
Short name T160
Test name
Test status
Simulation time 95891129 ps
CPU time 1.83 seconds
Started Jul 10 05:15:39 PM PDT 24
Finished Jul 10 05:15:51 PM PDT 24
Peak memory 210772 kb
Host smart-42fa1e3d-bf3f-41d5-a1e3-fe482524f795
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246216207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.1246216207
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2954115345
Short name T877
Test name
Test status
Simulation time 87831440 ps
CPU time 2.3 seconds
Started Jul 10 05:15:34 PM PDT 24
Finished Jul 10 05:15:45 PM PDT 24
Peak memory 218976 kb
Host smart-99ed4c46-4a50-499b-aca8-6a2887de8443
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295411
5345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2954115345
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2894407832
Short name T881
Test name
Test status
Simulation time 55438242 ps
CPU time 1.27 seconds
Started Jul 10 05:15:32 PM PDT 24
Finished Jul 10 05:15:40 PM PDT 24
Peak memory 209016 kb
Host smart-40c52a60-6596-47cb-8943-4fda2e244905
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894407832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.2894407832
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3489420735
Short name T909
Test name
Test status
Simulation time 88756761 ps
CPU time 1.38 seconds
Started Jul 10 05:15:37 PM PDT 24
Finished Jul 10 05:15:49 PM PDT 24
Peak memory 209128 kb
Host smart-b67e0b23-775b-43d1-87b9-dae0ba752765
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489420735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.3489420735
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3510327672
Short name T932
Test name
Test status
Simulation time 36422483 ps
CPU time 2.18 seconds
Started Jul 10 05:15:34 PM PDT 24
Finished Jul 10 05:15:45 PM PDT 24
Peak memory 218552 kb
Host smart-8eef68ed-3d3c-46cf-8b17-9421255987b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510327672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.3510327672
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.594330708
Short name T124
Test name
Test status
Simulation time 266422912 ps
CPU time 3.33 seconds
Started Jul 10 05:15:39 PM PDT 24
Finished Jul 10 05:15:53 PM PDT 24
Peak memory 217456 kb
Host smart-a1852530-71c6-4450-95fc-57fda801266b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594330708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_e
rr.594330708
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.155014652
Short name T207
Test name
Test status
Simulation time 297517754 ps
CPU time 1.28 seconds
Started Jul 10 05:15:39 PM PDT 24
Finished Jul 10 05:15:51 PM PDT 24
Peak memory 209304 kb
Host smart-50d7914e-564f-4adf-88c4-801169a55db6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155014652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasing
.155014652
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.532551654
Short name T897
Test name
Test status
Simulation time 70953014 ps
CPU time 1.87 seconds
Started Jul 10 05:15:32 PM PDT 24
Finished Jul 10 05:15:41 PM PDT 24
Peak memory 209184 kb
Host smart-950a3e85-c755-4dc1-8cd3-f09c3f919fe8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532551654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bash
.532551654
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.4238466869
Short name T968
Test name
Test status
Simulation time 159908195 ps
CPU time 1.16 seconds
Started Jul 10 05:15:32 PM PDT 24
Finished Jul 10 05:15:41 PM PDT 24
Peak memory 211532 kb
Host smart-3f93515b-8988-4515-9d2a-452fa6b868b6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238466869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.4238466869
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2817345788
Short name T170
Test name
Test status
Simulation time 67169854 ps
CPU time 1.22 seconds
Started Jul 10 05:15:38 PM PDT 24
Finished Jul 10 05:15:50 PM PDT 24
Peak memory 217572 kb
Host smart-c4c22c30-6092-4731-aea2-7c573cc4b782
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817345788 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.2817345788
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.474484051
Short name T206
Test name
Test status
Simulation time 56151082 ps
CPU time 0.9 seconds
Started Jul 10 05:15:35 PM PDT 24
Finished Jul 10 05:15:45 PM PDT 24
Peak memory 209168 kb
Host smart-b5893eaf-2179-4c6c-a9e3-21a3f330e1cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474484051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.474484051
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2696528266
Short name T982
Test name
Test status
Simulation time 55639913 ps
CPU time 1.58 seconds
Started Jul 10 05:15:38 PM PDT 24
Finished Jul 10 05:15:50 PM PDT 24
Peak memory 209084 kb
Host smart-003ac9ff-3b06-4857-9402-37166cd2ea37
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696528266 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.2696528266
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.445200830
Short name T989
Test name
Test status
Simulation time 735779169 ps
CPU time 7.46 seconds
Started Jul 10 05:15:38 PM PDT 24
Finished Jul 10 05:15:56 PM PDT 24
Peak memory 209160 kb
Host smart-2ac3e758-04fe-4684-a559-d09903036d7d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445200830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.445200830
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2816991485
Short name T911
Test name
Test status
Simulation time 1672249664 ps
CPU time 21.03 seconds
Started Jul 10 05:15:35 PM PDT 24
Finished Jul 10 05:16:06 PM PDT 24
Peak memory 208784 kb
Host smart-7affd3bb-d24f-471d-90ff-78adbb7f2514
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816991485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.2816991485
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.611010321
Short name T906
Test name
Test status
Simulation time 95522796 ps
CPU time 1.79 seconds
Started Jul 10 05:15:34 PM PDT 24
Finished Jul 10 05:15:44 PM PDT 24
Peak memory 210740 kb
Host smart-96e90bf7-971e-4abd-99fb-cc0927d8bc0b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611010321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.611010321
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2678632939
Short name T926
Test name
Test status
Simulation time 206025232 ps
CPU time 1.93 seconds
Started Jul 10 05:15:38 PM PDT 24
Finished Jul 10 05:15:51 PM PDT 24
Peak memory 217580 kb
Host smart-3dc91ad6-e640-4e28-934e-f2ad25fc984d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267863
2939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2678632939
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3894956252
Short name T213
Test name
Test status
Simulation time 51546395 ps
CPU time 1.09 seconds
Started Jul 10 05:15:39 PM PDT 24
Finished Jul 10 05:15:51 PM PDT 24
Peak memory 209180 kb
Host smart-bcb10002-5d06-4d9d-908c-b8ca788a8e57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894956252 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.3894956252
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2382008824
Short name T907
Test name
Test status
Simulation time 39082662 ps
CPU time 1.25 seconds
Started Jul 10 05:15:42 PM PDT 24
Finished Jul 10 05:15:56 PM PDT 24
Peak memory 209136 kb
Host smart-05d0ad20-a2bc-48a9-83f7-88bb19ea6d40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382008824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.2382008824
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2107149181
Short name T130
Test name
Test status
Simulation time 83215809 ps
CPU time 3.02 seconds
Started Jul 10 05:15:42 PM PDT 24
Finished Jul 10 05:15:57 PM PDT 24
Peak memory 217940 kb
Host smart-b1f790f9-bca5-4173-bd43-a4f3e7d1aff9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107149181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.2107149181
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2820965745
Short name T908
Test name
Test status
Simulation time 18052351 ps
CPU time 1.33 seconds
Started Jul 10 05:15:51 PM PDT 24
Finished Jul 10 05:16:04 PM PDT 24
Peak memory 217568 kb
Host smart-3bdd783b-9983-4c6f-a3a8-f7a0c5b5807b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820965745 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.2820965745
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1127544217
Short name T944
Test name
Test status
Simulation time 25300124 ps
CPU time 1.02 seconds
Started Jul 10 05:15:52 PM PDT 24
Finished Jul 10 05:16:04 PM PDT 24
Peak memory 209172 kb
Host smart-db2acdeb-342e-4532-860c-9ce58bf6254f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127544217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.1127544217
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.927426407
Short name T210
Test name
Test status
Simulation time 154238605 ps
CPU time 1.83 seconds
Started Jul 10 05:15:50 PM PDT 24
Finished Jul 10 05:16:04 PM PDT 24
Peak memory 211172 kb
Host smart-43b46f08-f7cd-4d2d-93ec-90d1928d3698
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927426407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_same_csr_outstanding.927426407
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3375484938
Short name T954
Test name
Test status
Simulation time 81964341 ps
CPU time 2.77 seconds
Started Jul 10 05:15:49 PM PDT 24
Finished Jul 10 05:16:04 PM PDT 24
Peak memory 217436 kb
Host smart-fb69537e-96ca-46a2-91de-3e5121200545
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375484938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.3375484938
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3563636625
Short name T142
Test name
Test status
Simulation time 214479344 ps
CPU time 2.83 seconds
Started Jul 10 05:16:00 PM PDT 24
Finished Jul 10 05:16:11 PM PDT 24
Peak memory 221912 kb
Host smart-e700bfcf-d2b2-4869-855e-ae79990f50d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563636625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.3563636625
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2640647938
Short name T916
Test name
Test status
Simulation time 24523349 ps
CPU time 1.1 seconds
Started Jul 10 05:15:51 PM PDT 24
Finished Jul 10 05:16:04 PM PDT 24
Peak memory 217580 kb
Host smart-f8a83c16-035d-4968-82f2-041da6277a40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640647938 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.2640647938
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3097548394
Short name T208
Test name
Test status
Simulation time 16072995 ps
CPU time 1.11 seconds
Started Jul 10 05:15:55 PM PDT 24
Finished Jul 10 05:16:05 PM PDT 24
Peak memory 209212 kb
Host smart-20f112bc-3e5a-417f-bc94-bea1637c18e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097548394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.3097548394
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2329417711
Short name T942
Test name
Test status
Simulation time 24504693 ps
CPU time 1.47 seconds
Started Jul 10 05:15:52 PM PDT 24
Finished Jul 10 05:16:05 PM PDT 24
Peak memory 209176 kb
Host smart-6f5e532d-baba-461f-84d8-e018e064096b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329417711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.2329417711
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2797289652
Short name T933
Test name
Test status
Simulation time 256230372 ps
CPU time 2.07 seconds
Started Jul 10 05:15:57 PM PDT 24
Finished Jul 10 05:16:09 PM PDT 24
Peak memory 217616 kb
Host smart-9ea80583-9999-4054-b1c6-bd5a97660022
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797289652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.2797289652
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.48073107
Short name T990
Test name
Test status
Simulation time 18144823 ps
CPU time 1.29 seconds
Started Jul 10 05:15:52 PM PDT 24
Finished Jul 10 05:16:05 PM PDT 24
Peak memory 217544 kb
Host smart-3a0d885e-966a-471f-9955-576d25a86530
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48073107 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.48073107
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1239798807
Short name T903
Test name
Test status
Simulation time 17334894 ps
CPU time 0.94 seconds
Started Jul 10 05:15:51 PM PDT 24
Finished Jul 10 05:16:04 PM PDT 24
Peak memory 209168 kb
Host smart-4ca4e8c3-064a-4eb2-a8c7-a2f3b87b5822
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239798807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.1239798807
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1705335750
Short name T132
Test name
Test status
Simulation time 27104956 ps
CPU time 1.18 seconds
Started Jul 10 05:15:51 PM PDT 24
Finished Jul 10 05:16:04 PM PDT 24
Peak memory 209236 kb
Host smart-62f032bd-249b-4666-bcab-d9a261f160cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705335750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.1705335750
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.4138291277
Short name T150
Test name
Test status
Simulation time 251178468 ps
CPU time 1.9 seconds
Started Jul 10 05:15:59 PM PDT 24
Finished Jul 10 05:16:10 PM PDT 24
Peak memory 221736 kb
Host smart-984fc954-fff6-4659-afd9-919b717dc3d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138291277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.4138291277
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2093020369
Short name T975
Test name
Test status
Simulation time 20331679 ps
CPU time 1.58 seconds
Started Jul 10 05:15:51 PM PDT 24
Finished Jul 10 05:16:05 PM PDT 24
Peak memory 217432 kb
Host smart-d6f67eb5-2238-495e-bc95-d7633946b2fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093020369 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.2093020369
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3808858562
Short name T203
Test name
Test status
Simulation time 61861359 ps
CPU time 0.92 seconds
Started Jul 10 05:15:49 PM PDT 24
Finished Jul 10 05:16:02 PM PDT 24
Peak memory 209224 kb
Host smart-4c2ea7c5-b498-4da3-bc38-e7ef07c817e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808858562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.3808858562
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.1508408276
Short name T898
Test name
Test status
Simulation time 56517374 ps
CPU time 1.03 seconds
Started Jul 10 05:15:51 PM PDT 24
Finished Jul 10 05:16:04 PM PDT 24
Peak memory 209236 kb
Host smart-0f954bbe-0228-4abf-bdda-0ed1385a3f59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508408276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.1508408276
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.170761271
Short name T951
Test name
Test status
Simulation time 586918319 ps
CPU time 3.45 seconds
Started Jul 10 05:15:57 PM PDT 24
Finished Jul 10 05:16:10 PM PDT 24
Peak memory 217960 kb
Host smart-a52be499-6009-47a4-a50d-2ced3c069a2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170761271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.170761271
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.679560533
Short name T910
Test name
Test status
Simulation time 58939736 ps
CPU time 1.25 seconds
Started Jul 10 05:16:02 PM PDT 24
Finished Jul 10 05:16:11 PM PDT 24
Peak memory 219252 kb
Host smart-27f0ab69-abd4-4154-9f7f-ac6b7c17b2cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679560533 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.679560533
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.720336223
Short name T893
Test name
Test status
Simulation time 29720114 ps
CPU time 1.02 seconds
Started Jul 10 05:15:54 PM PDT 24
Finished Jul 10 05:16:05 PM PDT 24
Peak memory 209172 kb
Host smart-c77648cd-4c0c-4f03-af0f-3a0dcb31426c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720336223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.720336223
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3941781540
Short name T896
Test name
Test status
Simulation time 25999067 ps
CPU time 1.43 seconds
Started Jul 10 05:15:50 PM PDT 24
Finished Jul 10 05:16:04 PM PDT 24
Peak memory 209236 kb
Host smart-bcd8cc99-ad3e-4e53-b94b-6026c91ae5be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941781540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.3941781540
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.169441598
Short name T979
Test name
Test status
Simulation time 63855563 ps
CPU time 2.94 seconds
Started Jul 10 05:15:59 PM PDT 24
Finished Jul 10 05:16:11 PM PDT 24
Peak memory 217432 kb
Host smart-c67b0e3c-8c56-45c1-b7eb-268dcd4fb4e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169441598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.169441598
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3866743532
Short name T126
Test name
Test status
Simulation time 457675248 ps
CPU time 3.23 seconds
Started Jul 10 05:15:50 PM PDT 24
Finished Jul 10 05:16:06 PM PDT 24
Peak memory 222172 kb
Host smart-e310ab0c-e128-4a64-9107-67f8ae99088d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866743532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.3866743532
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.376582859
Short name T939
Test name
Test status
Simulation time 135342442 ps
CPU time 1.52 seconds
Started Jul 10 05:15:57 PM PDT 24
Finished Jul 10 05:16:08 PM PDT 24
Peak memory 219336 kb
Host smart-ed414eda-aba3-4fb1-ad58-3cf8c53bc78d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376582859 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.376582859
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2921983980
Short name T921
Test name
Test status
Simulation time 14675673 ps
CPU time 1.1 seconds
Started Jul 10 05:15:55 PM PDT 24
Finished Jul 10 05:16:06 PM PDT 24
Peak memory 209232 kb
Host smart-0973305c-8bea-41d7-b072-cd0d3760d425
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921983980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.2921983980
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.3002299175
Short name T956
Test name
Test status
Simulation time 28689510 ps
CPU time 1.1 seconds
Started Jul 10 05:15:54 PM PDT 24
Finished Jul 10 05:16:06 PM PDT 24
Peak memory 209272 kb
Host smart-cd69d102-535b-4c35-9daf-3ec4d5aa78d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002299175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.3002299175
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1506799744
Short name T140
Test name
Test status
Simulation time 1023581304 ps
CPU time 2.2 seconds
Started Jul 10 05:16:04 PM PDT 24
Finished Jul 10 05:16:13 PM PDT 24
Peak memory 218224 kb
Host smart-01970906-d9f0-47e8-aaaf-7fe96273ecf5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506799744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.1506799744
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3101629124
Short name T963
Test name
Test status
Simulation time 21135910 ps
CPU time 1.73 seconds
Started Jul 10 05:15:54 PM PDT 24
Finished Jul 10 05:16:06 PM PDT 24
Peak memory 217632 kb
Host smart-b80c6a3a-6c7a-4646-b5d9-e210985829eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101629124 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.3101629124
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3782695499
Short name T980
Test name
Test status
Simulation time 80157742 ps
CPU time 1.02 seconds
Started Jul 10 05:15:55 PM PDT 24
Finished Jul 10 05:16:06 PM PDT 24
Peak memory 209236 kb
Host smart-57a6ebf2-915b-4379-b60d-e518a422864b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782695499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.3782695499
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3632779612
Short name T934
Test name
Test status
Simulation time 335880881 ps
CPU time 1.07 seconds
Started Jul 10 05:15:54 PM PDT 24
Finished Jul 10 05:16:05 PM PDT 24
Peak memory 209280 kb
Host smart-742ff62d-a6f4-4ec4-8a12-34828bf797ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632779612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.3632779612
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3279764020
Short name T136
Test name
Test status
Simulation time 32313024 ps
CPU time 2.38 seconds
Started Jul 10 05:16:17 PM PDT 24
Finished Jul 10 05:16:21 PM PDT 24
Peak memory 218016 kb
Host smart-a864f162-c0b3-4716-af0c-3dbb6f5394f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279764020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.3279764020
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1936921952
Short name T912
Test name
Test status
Simulation time 170496472 ps
CPU time 1.99 seconds
Started Jul 10 05:15:57 PM PDT 24
Finished Jul 10 05:16:08 PM PDT 24
Peak memory 217588 kb
Host smart-7139b8fe-c81c-446f-ab52-87fc82e02358
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936921952 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.1936921952
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1367428084
Short name T205
Test name
Test status
Simulation time 12587995 ps
CPU time 0.99 seconds
Started Jul 10 05:15:56 PM PDT 24
Finished Jul 10 05:16:07 PM PDT 24
Peak memory 209232 kb
Host smart-6e6b3096-e788-4fea-b12d-bada54dca95d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367428084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.1367428084
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.941869788
Short name T887
Test name
Test status
Simulation time 50014792 ps
CPU time 1.49 seconds
Started Jul 10 05:15:54 PM PDT 24
Finished Jul 10 05:16:05 PM PDT 24
Peak memory 211076 kb
Host smart-8633079c-b0f7-48b2-af68-a1940cf44005
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941869788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_same_csr_outstanding.941869788
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2523522548
Short name T978
Test name
Test status
Simulation time 555784006 ps
CPU time 3.39 seconds
Started Jul 10 05:15:57 PM PDT 24
Finished Jul 10 05:16:10 PM PDT 24
Peak memory 217460 kb
Host smart-af88d288-afb5-46c4-8dec-ade84c0d37de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523522548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.2523522548
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3580194900
Short name T143
Test name
Test status
Simulation time 445684469 ps
CPU time 2.94 seconds
Started Jul 10 05:15:56 PM PDT 24
Finished Jul 10 05:16:09 PM PDT 24
Peak memory 222124 kb
Host smart-50d14a0e-31d5-4334-99e4-c8102216e96b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580194900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.3580194900
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.913939424
Short name T960
Test name
Test status
Simulation time 88627202 ps
CPU time 1.7 seconds
Started Jul 10 05:15:53 PM PDT 24
Finished Jul 10 05:16:06 PM PDT 24
Peak memory 219032 kb
Host smart-11c0abba-5746-4ef0-8c6a-1428480ba352
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913939424 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.913939424
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3391081096
Short name T138
Test name
Test status
Simulation time 15937180 ps
CPU time 1.07 seconds
Started Jul 10 05:15:55 PM PDT 24
Finished Jul 10 05:16:05 PM PDT 24
Peak memory 217292 kb
Host smart-2abe5dbe-76a6-4fe3-90cb-390a1cc44225
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391081096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.3391081096
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2979007758
Short name T945
Test name
Test status
Simulation time 92827555 ps
CPU time 1.12 seconds
Started Jul 10 05:15:59 PM PDT 24
Finished Jul 10 05:16:09 PM PDT 24
Peak memory 209236 kb
Host smart-a1439747-465d-4b3a-8c4a-37f6ed54a67c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979007758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.2979007758
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.396349057
Short name T145
Test name
Test status
Simulation time 357326189 ps
CPU time 1.63 seconds
Started Jul 10 05:16:08 PM PDT 24
Finished Jul 10 05:16:14 PM PDT 24
Peak memory 217640 kb
Host smart-cb3620ae-059c-4a4d-8188-bd134498585a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396349057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.396349057
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3332243360
Short name T930
Test name
Test status
Simulation time 39021572 ps
CPU time 1.19 seconds
Started Jul 10 05:16:03 PM PDT 24
Finished Jul 10 05:16:11 PM PDT 24
Peak memory 217748 kb
Host smart-4ca77bf2-2597-4068-b568-7509b51ded10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332243360 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.3332243360
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.22695221
Short name T870
Test name
Test status
Simulation time 13930278 ps
CPU time 0.98 seconds
Started Jul 10 05:15:53 PM PDT 24
Finished Jul 10 05:16:04 PM PDT 24
Peak memory 208992 kb
Host smart-f6e424df-114d-44a6-8fb9-d0e5517228d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22695221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.22695221
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.627712906
Short name T958
Test name
Test status
Simulation time 50505715 ps
CPU time 1.11 seconds
Started Jul 10 05:15:54 PM PDT 24
Finished Jul 10 05:16:06 PM PDT 24
Peak memory 209236 kb
Host smart-fe7c9f61-52e6-4f1e-9a3c-939310157d38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627712906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_same_csr_outstanding.627712906
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.4012563866
Short name T935
Test name
Test status
Simulation time 143587051 ps
CPU time 2.4 seconds
Started Jul 10 05:15:59 PM PDT 24
Finished Jul 10 05:16:10 PM PDT 24
Peak memory 218464 kb
Host smart-7ba03ddf-2342-4503-8a28-4cb7a66e99f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012563866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.4012563866
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1945535689
Short name T135
Test name
Test status
Simulation time 116063578 ps
CPU time 1.81 seconds
Started Jul 10 05:15:55 PM PDT 24
Finished Jul 10 05:16:07 PM PDT 24
Peak memory 221660 kb
Host smart-f55144ee-e6f1-412b-ab18-18c52ed6ec1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945535689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.1945535689
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3382541283
Short name T976
Test name
Test status
Simulation time 31414278 ps
CPU time 1.75 seconds
Started Jul 10 05:15:40 PM PDT 24
Finished Jul 10 05:15:54 PM PDT 24
Peak memory 209224 kb
Host smart-19e735f6-7960-40b9-8028-e1145918bc05
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382541283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.3382541283
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3046133331
Short name T981
Test name
Test status
Simulation time 85195004 ps
CPU time 1.96 seconds
Started Jul 10 05:15:40 PM PDT 24
Finished Jul 10 05:15:53 PM PDT 24
Peak memory 209056 kb
Host smart-1cee04a9-5fca-4325-997f-97c0ad43232a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046133331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.3046133331
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2760933265
Short name T928
Test name
Test status
Simulation time 53686415 ps
CPU time 1.1 seconds
Started Jul 10 05:15:41 PM PDT 24
Finished Jul 10 05:15:54 PM PDT 24
Peak memory 209764 kb
Host smart-b0648970-8da4-4327-97cf-4cb94b054449
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760933265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.2760933265
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2816613561
Short name T892
Test name
Test status
Simulation time 65456893 ps
CPU time 1.26 seconds
Started Jul 10 05:15:40 PM PDT 24
Finished Jul 10 05:15:53 PM PDT 24
Peak memory 217516 kb
Host smart-1a1303d7-b464-4235-b6b0-d05dcb841c16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816613561 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.2816613561
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1354470473
Short name T940
Test name
Test status
Simulation time 12521254 ps
CPU time 0.97 seconds
Started Jul 10 05:15:40 PM PDT 24
Finished Jul 10 05:15:52 PM PDT 24
Peak memory 209232 kb
Host smart-508c5e8a-6b9c-4039-af2c-8f7054dded54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354470473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.1354470473
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1505604185
Short name T920
Test name
Test status
Simulation time 67138002 ps
CPU time 1.08 seconds
Started Jul 10 05:15:40 PM PDT 24
Finished Jul 10 05:15:52 PM PDT 24
Peak memory 208540 kb
Host smart-1357c9ad-7628-4c15-aace-af9ccdec1c60
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505604185 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.1505604185
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3623973048
Short name T874
Test name
Test status
Simulation time 377182446 ps
CPU time 5.67 seconds
Started Jul 10 05:15:40 PM PDT 24
Finished Jul 10 05:15:57 PM PDT 24
Peak memory 209192 kb
Host smart-bc4b4388-241c-428d-b324-5a633a82d894
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623973048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.3623973048
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.978632186
Short name T962
Test name
Test status
Simulation time 2150235666 ps
CPU time 9.98 seconds
Started Jul 10 05:15:40 PM PDT 24
Finished Jul 10 05:16:01 PM PDT 24
Peak memory 209236 kb
Host smart-5aebd605-52ee-4ac5-87dd-b9432b9e3c33
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978632186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.978632186
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2818397144
Short name T879
Test name
Test status
Simulation time 173101938 ps
CPU time 1.11 seconds
Started Jul 10 05:15:42 PM PDT 24
Finished Jul 10 05:15:55 PM PDT 24
Peak memory 210532 kb
Host smart-b5baa08d-0c30-47d0-96f6-d31a1196ebc0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818397144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.2818397144
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2389033143
Short name T173
Test name
Test status
Simulation time 434905177 ps
CPU time 3.69 seconds
Started Jul 10 05:15:40 PM PDT 24
Finished Jul 10 05:15:55 PM PDT 24
Peak memory 217600 kb
Host smart-0521dbc1-7aad-4360-b82b-771fa4865627
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238903
3143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2389033143
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.4080324091
Short name T157
Test name
Test status
Simulation time 791826916 ps
CPU time 4.09 seconds
Started Jul 10 05:15:37 PM PDT 24
Finished Jul 10 05:15:50 PM PDT 24
Peak memory 209148 kb
Host smart-68c5d3b2-c1e4-4750-be89-49ace1b187f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080324091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.4080324091
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2881528307
Short name T938
Test name
Test status
Simulation time 97009284 ps
CPU time 1.34 seconds
Started Jul 10 05:15:41 PM PDT 24
Finished Jul 10 05:15:54 PM PDT 24
Peak memory 217496 kb
Host smart-1c22c3bd-ca8c-489f-97e0-68394be4bd56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881528307 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.2881528307
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3141125385
Short name T949
Test name
Test status
Simulation time 45170446 ps
CPU time 0.99 seconds
Started Jul 10 05:15:44 PM PDT 24
Finished Jul 10 05:15:57 PM PDT 24
Peak memory 209256 kb
Host smart-98cf641f-dc3a-48ed-8baf-5433ac051d11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141125385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.3141125385
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2320391391
Short name T974
Test name
Test status
Simulation time 160269261 ps
CPU time 3.13 seconds
Started Jul 10 05:15:51 PM PDT 24
Finished Jul 10 05:16:05 PM PDT 24
Peak memory 217444 kb
Host smart-ab17c064-ce8c-4f0b-9d8c-4d90a3fdecf8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320391391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.2320391391
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3489865411
Short name T147
Test name
Test status
Simulation time 322988927 ps
CPU time 3.11 seconds
Started Jul 10 05:15:42 PM PDT 24
Finished Jul 10 05:15:57 PM PDT 24
Peak memory 222360 kb
Host smart-331d9fe0-4e13-43e7-8b2a-f6431f0db266
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489865411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.3489865411
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1300209966
Short name T199
Test name
Test status
Simulation time 240495186 ps
CPU time 2.48 seconds
Started Jul 10 05:15:41 PM PDT 24
Finished Jul 10 05:15:56 PM PDT 24
Peak memory 217388 kb
Host smart-bcd9f870-3d99-41e4-a4d5-83db6c02dcd5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300209966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.1300209966
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.4095187489
Short name T200
Test name
Test status
Simulation time 83303030 ps
CPU time 1.05 seconds
Started Jul 10 05:15:41 PM PDT 24
Finished Jul 10 05:15:54 PM PDT 24
Peak memory 210220 kb
Host smart-21a549e9-5441-4346-bc98-f5a5a21eae87
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095187489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.4095187489
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.3965051020
Short name T876
Test name
Test status
Simulation time 50043522 ps
CPU time 0.85 seconds
Started Jul 10 05:15:51 PM PDT 24
Finished Jul 10 05:16:03 PM PDT 24
Peak memory 209256 kb
Host smart-4111286d-354a-495c-9f5b-33b235792e54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965051020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.3965051020
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.196908011
Short name T901
Test name
Test status
Simulation time 29580555 ps
CPU time 0.89 seconds
Started Jul 10 05:15:41 PM PDT 24
Finished Jul 10 05:15:53 PM PDT 24
Peak memory 208900 kb
Host smart-589179a9-583f-4dbf-bb80-6531f7516e63
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196908011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.lc_ctrl_jtag_alert_test.196908011
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.4107013473
Short name T929
Test name
Test status
Simulation time 2097975454 ps
CPU time 3.35 seconds
Started Jul 10 05:15:41 PM PDT 24
Finished Jul 10 05:15:56 PM PDT 24
Peak memory 208924 kb
Host smart-77aaed41-6343-49e5-b4fe-665b7cc7e06d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107013473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.4107013473
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1659519028
Short name T915
Test name
Test status
Simulation time 359579320 ps
CPU time 4.58 seconds
Started Jul 10 05:15:40 PM PDT 24
Finished Jul 10 05:15:56 PM PDT 24
Peak memory 209124 kb
Host smart-b49931de-7c69-4fc4-9e6d-4417815004cb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659519028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.1659519028
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.487358336
Short name T868
Test name
Test status
Simulation time 224876405 ps
CPU time 1.87 seconds
Started Jul 10 05:15:41 PM PDT 24
Finished Jul 10 05:15:54 PM PDT 24
Peak memory 210572 kb
Host smart-5a240fb4-f8d2-4f43-9ff6-2d31ba3ce4f2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487358336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.487358336
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2551661876
Short name T961
Test name
Test status
Simulation time 179029611 ps
CPU time 5.51 seconds
Started Jul 10 05:15:39 PM PDT 24
Finished Jul 10 05:15:55 PM PDT 24
Peak memory 217488 kb
Host smart-220db868-0528-47d1-ae18-13a21771161f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255166
1876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2551661876
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.90301720
Short name T959
Test name
Test status
Simulation time 549313096 ps
CPU time 3.8 seconds
Started Jul 10 05:15:41 PM PDT 24
Finished Jul 10 05:15:57 PM PDT 24
Peak memory 209172 kb
Host smart-2d311aa7-370c-4159-8e21-bc273647c017
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90301720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test
+UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 3.lc_ctrl_jtag_csr_rw.90301720
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1703957996
Short name T209
Test name
Test status
Simulation time 139250930 ps
CPU time 1.98 seconds
Started Jul 10 05:15:40 PM PDT 24
Finished Jul 10 05:15:53 PM PDT 24
Peak memory 217380 kb
Host smart-197c88a7-1122-4930-8c3a-e2eadb5a30b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703957996 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.1703957996
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2270296338
Short name T212
Test name
Test status
Simulation time 27472779 ps
CPU time 1.43 seconds
Started Jul 10 05:15:42 PM PDT 24
Finished Jul 10 05:15:56 PM PDT 24
Peak memory 209236 kb
Host smart-2eeb55ff-8e3f-4824-a8c0-6d252c47e4a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270296338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.2270296338
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2333557244
Short name T129
Test name
Test status
Simulation time 81002239 ps
CPU time 1.65 seconds
Started Jul 10 05:15:39 PM PDT 24
Finished Jul 10 05:15:52 PM PDT 24
Peak memory 217380 kb
Host smart-dba5f929-41e0-4550-a5c3-fea695f2a8be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333557244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.2333557244
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1640570301
Short name T156
Test name
Test status
Simulation time 43851817 ps
CPU time 1.86 seconds
Started Jul 10 05:15:41 PM PDT 24
Finished Jul 10 05:15:54 PM PDT 24
Peak memory 221452 kb
Host smart-5680cfe6-ce0e-486b-8967-e1a842f259c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640570301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.1640570301
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.4205331205
Short name T864
Test name
Test status
Simulation time 13276507 ps
CPU time 1.16 seconds
Started Jul 10 05:15:41 PM PDT 24
Finished Jul 10 05:15:54 PM PDT 24
Peak memory 209232 kb
Host smart-64ca2b45-ec1f-443c-a240-a8e8f1185312
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205331205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.4205331205
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2085133516
Short name T899
Test name
Test status
Simulation time 86993175 ps
CPU time 1.96 seconds
Started Jul 10 05:15:43 PM PDT 24
Finished Jul 10 05:15:58 PM PDT 24
Peak memory 209040 kb
Host smart-704bc424-7254-42c9-86e6-882a27140979
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085133516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.2085133516
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2628864800
Short name T202
Test name
Test status
Simulation time 37522712 ps
CPU time 1.22 seconds
Started Jul 10 05:15:51 PM PDT 24
Finished Jul 10 05:16:04 PM PDT 24
Peak memory 217908 kb
Host smart-4343af29-a932-4292-b3ef-8ba2e6071974
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628864800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.2628864800
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1890796740
Short name T871
Test name
Test status
Simulation time 85388812 ps
CPU time 1.43 seconds
Started Jul 10 05:15:41 PM PDT 24
Finished Jul 10 05:15:54 PM PDT 24
Peak memory 217492 kb
Host smart-76a4e8b9-19e0-4545-8d7e-c093d4a58680
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890796740 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.1890796740
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3835760918
Short name T972
Test name
Test status
Simulation time 15988517 ps
CPU time 1.01 seconds
Started Jul 10 05:15:40 PM PDT 24
Finished Jul 10 05:15:52 PM PDT 24
Peak memory 209112 kb
Host smart-bc03d332-e057-420c-afa3-a5856d9e4e28
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835760918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.3835760918
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3011249818
Short name T905
Test name
Test status
Simulation time 730727407 ps
CPU time 1.29 seconds
Started Jul 10 05:15:39 PM PDT 24
Finished Jul 10 05:15:51 PM PDT 24
Peak memory 209080 kb
Host smart-58e9a977-aea0-4fd5-a8a8-a3abc4c71815
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011249818 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.3011249818
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.9165544
Short name T875
Test name
Test status
Simulation time 861259930 ps
CPU time 2.89 seconds
Started Jul 10 05:15:40 PM PDT 24
Finished Jul 10 05:15:54 PM PDT 24
Peak memory 209080 kb
Host smart-7909d3e3-7907-400b-b36f-5a47ac602080
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9165544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base
_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 4.lc_ctrl_jtag_csr_aliasing.9165544
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.899458331
Short name T866
Test name
Test status
Simulation time 2353052011 ps
CPU time 19.12 seconds
Started Jul 10 05:15:40 PM PDT 24
Finished Jul 10 05:16:11 PM PDT 24
Peak memory 217264 kb
Host smart-f97e0125-640e-4def-8c6f-6ddf292d6eab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899458331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.899458331
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2040389820
Short name T895
Test name
Test status
Simulation time 901293995 ps
CPU time 2.94 seconds
Started Jul 10 05:15:39 PM PDT 24
Finished Jul 10 05:15:53 PM PDT 24
Peak memory 210796 kb
Host smart-9f73bfc5-711b-4839-90a9-4c7e2e0050d6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040389820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.2040389820
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.206342979
Short name T937
Test name
Test status
Simulation time 148915818 ps
CPU time 2.65 seconds
Started Jul 10 05:15:41 PM PDT 24
Finished Jul 10 05:15:55 PM PDT 24
Peak memory 218004 kb
Host smart-32bc50ea-47b5-4394-b7f4-ee5c40802cc2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206342
979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.206342979
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1638956285
Short name T872
Test name
Test status
Simulation time 61037795 ps
CPU time 2.07 seconds
Started Jul 10 05:15:42 PM PDT 24
Finished Jul 10 05:15:57 PM PDT 24
Peak memory 209108 kb
Host smart-ee0c33fe-dbde-4b6e-8884-de447cc9cd4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638956285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.1638956285
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.4242343445
Short name T977
Test name
Test status
Simulation time 63393965 ps
CPU time 1.12 seconds
Started Jul 10 05:15:43 PM PDT 24
Finished Jul 10 05:15:56 PM PDT 24
Peak memory 209332 kb
Host smart-5bb4801f-9215-4696-a7d6-c17b7d0fb75f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242343445 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.4242343445
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3441185734
Short name T880
Test name
Test status
Simulation time 106670262 ps
CPU time 1.13 seconds
Started Jul 10 05:15:41 PM PDT 24
Finished Jul 10 05:15:54 PM PDT 24
Peak memory 209228 kb
Host smart-eccb9dcc-6529-415f-84ad-306e9acd9e23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441185734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.3441185734
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1399125365
Short name T985
Test name
Test status
Simulation time 563502223 ps
CPU time 3.16 seconds
Started Jul 10 05:15:41 PM PDT 24
Finished Jul 10 05:15:56 PM PDT 24
Peak memory 217676 kb
Host smart-d27e3bce-05fc-4513-8b0a-f51b6bffc1c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399125365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.1399125365
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.337028170
Short name T886
Test name
Test status
Simulation time 21436892 ps
CPU time 1.06 seconds
Started Jul 10 05:15:43 PM PDT 24
Finished Jul 10 05:15:56 PM PDT 24
Peak memory 217484 kb
Host smart-dd0a8900-d459-47f0-9fa2-b54693c25ed0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337028170 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.337028170
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1010705709
Short name T889
Test name
Test status
Simulation time 18661359 ps
CPU time 0.87 seconds
Started Jul 10 05:15:53 PM PDT 24
Finished Jul 10 05:16:05 PM PDT 24
Peak memory 208972 kb
Host smart-d5c3c128-36ff-48cc-8d1c-94c4d8b687fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010705709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.1010705709
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1791312794
Short name T888
Test name
Test status
Simulation time 67984398 ps
CPU time 1.29 seconds
Started Jul 10 05:15:50 PM PDT 24
Finished Jul 10 05:16:04 PM PDT 24
Peak memory 209332 kb
Host smart-a18824a3-8f0f-480a-a13d-1ec59bb658e9
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791312794 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.1791312794
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1377391980
Short name T918
Test name
Test status
Simulation time 2106521149 ps
CPU time 13.33 seconds
Started Jul 10 05:15:41 PM PDT 24
Finished Jul 10 05:16:06 PM PDT 24
Peak memory 209116 kb
Host smart-5fba4cb2-9789-4d11-bda7-d554d7f30dd7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377391980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.1377391980
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1596175189
Short name T970
Test name
Test status
Simulation time 8339102890 ps
CPU time 20.15 seconds
Started Jul 10 05:15:41 PM PDT 24
Finished Jul 10 05:16:12 PM PDT 24
Peak memory 209224 kb
Host smart-372a3820-fac8-4ba3-9e2b-1a68816c12f2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596175189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.1596175189
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2023894800
Short name T867
Test name
Test status
Simulation time 474599772 ps
CPU time 2.41 seconds
Started Jul 10 05:15:41 PM PDT 24
Finished Jul 10 05:15:55 PM PDT 24
Peak memory 217320 kb
Host smart-12799a2b-e6ef-4bb6-9aa3-d7c8979eab6b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023894800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.2023894800
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.543474227
Short name T964
Test name
Test status
Simulation time 975996739 ps
CPU time 2.8 seconds
Started Jul 10 05:15:46 PM PDT 24
Finished Jul 10 05:16:02 PM PDT 24
Peak memory 217552 kb
Host smart-0dba1be9-059a-4dd3-bd38-4f4cd242eaff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543474
227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.543474227
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3669307522
Short name T159
Test name
Test status
Simulation time 116639267 ps
CPU time 2.05 seconds
Started Jul 10 05:15:41 PM PDT 24
Finished Jul 10 05:15:56 PM PDT 24
Peak memory 217248 kb
Host smart-0330ecce-579e-44c7-8fa0-41c62a3851c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669307522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.3669307522
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2774680349
Short name T927
Test name
Test status
Simulation time 27877750 ps
CPU time 0.92 seconds
Started Jul 10 05:15:43 PM PDT 24
Finished Jul 10 05:15:56 PM PDT 24
Peak memory 209264 kb
Host smart-20083815-13c8-46b8-b869-f32b768a292e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774680349 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.2774680349
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.943842690
Short name T137
Test name
Test status
Simulation time 27465646 ps
CPU time 1.44 seconds
Started Jul 10 05:15:45 PM PDT 24
Finished Jul 10 05:16:00 PM PDT 24
Peak memory 209044 kb
Host smart-0cbfcab7-9ae3-4e19-87cf-cb837de5d9a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943842690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
same_csr_outstanding.943842690
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2086648326
Short name T144
Test name
Test status
Simulation time 86745752 ps
CPU time 3.69 seconds
Started Jul 10 05:15:47 PM PDT 24
Finished Jul 10 05:16:03 PM PDT 24
Peak memory 217384 kb
Host smart-17926c00-d9a5-4e19-93c4-690e4cd8628b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086648326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.2086648326
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1038998007
Short name T891
Test name
Test status
Simulation time 28126638 ps
CPU time 1.7 seconds
Started Jul 10 05:15:53 PM PDT 24
Finished Jul 10 05:16:05 PM PDT 24
Peak memory 216868 kb
Host smart-6dddff4a-d535-4c7e-8c41-e5998f599f5a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038998007 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.1038998007
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3960311981
Short name T971
Test name
Test status
Simulation time 14777707 ps
CPU time 1.13 seconds
Started Jul 10 05:15:53 PM PDT 24
Finished Jul 10 05:16:05 PM PDT 24
Peak memory 209232 kb
Host smart-e2eef940-657e-4f65-a7c5-054637c8e8f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960311981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.3960311981
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.299970606
Short name T917
Test name
Test status
Simulation time 104821681 ps
CPU time 1.24 seconds
Started Jul 10 05:15:53 PM PDT 24
Finished Jul 10 05:16:05 PM PDT 24
Peak memory 207724 kb
Host smart-3513eb30-6162-40a4-8183-febda0ff956c
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299970606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.lc_ctrl_jtag_alert_test.299970606
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1489729373
Short name T922
Test name
Test status
Simulation time 736477608 ps
CPU time 7.92 seconds
Started Jul 10 05:15:47 PM PDT 24
Finished Jul 10 05:16:08 PM PDT 24
Peak memory 209108 kb
Host smart-6b141283-2f05-472a-9545-32677ce68c72
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489729373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.1489729373
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.950713026
Short name T952
Test name
Test status
Simulation time 3397158599 ps
CPU time 20.04 seconds
Started Jul 10 05:15:46 PM PDT 24
Finished Jul 10 05:16:19 PM PDT 24
Peak memory 217264 kb
Host smart-242004fa-312d-4a86-b2e8-f4afd0e22ceb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950713026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.950713026
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2179836441
Short name T948
Test name
Test status
Simulation time 1014503012 ps
CPU time 3.21 seconds
Started Jul 10 05:15:46 PM PDT 24
Finished Jul 10 05:16:01 PM PDT 24
Peak memory 210892 kb
Host smart-67b6ed7d-2a9b-4c93-ad8e-6ba8da9920b1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179836441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.2179836441
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.740321271
Short name T914
Test name
Test status
Simulation time 134012864 ps
CPU time 3.91 seconds
Started Jul 10 05:15:57 PM PDT 24
Finished Jul 10 05:16:10 PM PDT 24
Peak memory 218572 kb
Host smart-da9ab1a2-62cd-4d8e-b21b-4db2528e880f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740321
271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.740321271
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.4239671414
Short name T973
Test name
Test status
Simulation time 161306080 ps
CPU time 4.38 seconds
Started Jul 10 05:15:45 PM PDT 24
Finished Jul 10 05:16:02 PM PDT 24
Peak memory 217288 kb
Host smart-ece34962-a9ed-49f6-9c4f-d08e67268779
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239671414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.4239671414
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.843379260
Short name T211
Test name
Test status
Simulation time 66099453 ps
CPU time 1.3 seconds
Started Jul 10 05:15:45 PM PDT 24
Finished Jul 10 05:15:59 PM PDT 24
Peak memory 217556 kb
Host smart-9a3ea9f5-3238-4ad3-9ab9-66302757f6c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843379260 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.843379260
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.4014190641
Short name T943
Test name
Test status
Simulation time 32195122 ps
CPU time 1.56 seconds
Started Jul 10 05:15:42 PM PDT 24
Finished Jul 10 05:15:56 PM PDT 24
Peak memory 209212 kb
Host smart-0d7c6980-0859-4179-87dd-3bbf8aac7beb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014190641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.4014190641
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2131972420
Short name T923
Test name
Test status
Simulation time 379800974 ps
CPU time 2.94 seconds
Started Jul 10 05:15:50 PM PDT 24
Finished Jul 10 05:16:06 PM PDT 24
Peak memory 218588 kb
Host smart-c000880e-7d06-42e9-ac5a-36384441bcac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131972420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.2131972420
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3686451960
Short name T950
Test name
Test status
Simulation time 180179953 ps
CPU time 1.3 seconds
Started Jul 10 05:15:45 PM PDT 24
Finished Jul 10 05:15:59 PM PDT 24
Peak memory 217612 kb
Host smart-6c84d572-5bdd-44f0-b39f-71d568228b74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686451960 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.3686451960
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.358255609
Short name T957
Test name
Test status
Simulation time 13630482 ps
CPU time 1.03 seconds
Started Jul 10 05:15:44 PM PDT 24
Finished Jul 10 05:15:58 PM PDT 24
Peak memory 208964 kb
Host smart-eeb62ca2-0adf-48ee-81e6-1ebb8ad1ab15
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358255609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.358255609
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1392255335
Short name T890
Test name
Test status
Simulation time 99433408 ps
CPU time 1.97 seconds
Started Jul 10 05:15:45 PM PDT 24
Finished Jul 10 05:16:00 PM PDT 24
Peak memory 209076 kb
Host smart-87caeba0-43a9-4b2e-802b-24df9dbb81cf
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392255335 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.1392255335
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3356607990
Short name T919
Test name
Test status
Simulation time 335582767 ps
CPU time 8.18 seconds
Started Jul 10 05:15:45 PM PDT 24
Finished Jul 10 05:16:06 PM PDT 24
Peak memory 217032 kb
Host smart-142eef95-8351-42cd-9931-32f0db936078
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356607990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.3356607990
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1407797362
Short name T869
Test name
Test status
Simulation time 2599419443 ps
CPU time 21.55 seconds
Started Jul 10 05:15:45 PM PDT 24
Finished Jul 10 05:16:19 PM PDT 24
Peak memory 209000 kb
Host smart-27268245-9a0c-4cce-b2c7-55f4751a7c24
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407797362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.1407797362
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2373269609
Short name T955
Test name
Test status
Simulation time 333632030 ps
CPU time 1.8 seconds
Started Jul 10 05:15:46 PM PDT 24
Finished Jul 10 05:16:00 PM PDT 24
Peak memory 217368 kb
Host smart-00fee31c-1aab-4125-ad6b-780da782fb33
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373269609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.2373269609
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.613225851
Short name T925
Test name
Test status
Simulation time 59424694 ps
CPU time 1.74 seconds
Started Jul 10 05:15:47 PM PDT 24
Finished Jul 10 05:16:01 PM PDT 24
Peak memory 219028 kb
Host smart-59b2b7d0-b5f8-4fb9-acb8-b7ce370e3f19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613225
851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.613225851
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3767776055
Short name T983
Test name
Test status
Simulation time 38652848 ps
CPU time 1.59 seconds
Started Jul 10 05:15:59 PM PDT 24
Finished Jul 10 05:16:09 PM PDT 24
Peak memory 209120 kb
Host smart-bec0a99f-92fe-4c90-902f-b57925754409
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767776055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.3767776055
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2613618551
Short name T953
Test name
Test status
Simulation time 52511450 ps
CPU time 1.05 seconds
Started Jul 10 05:15:44 PM PDT 24
Finished Jul 10 05:15:58 PM PDT 24
Peak memory 209300 kb
Host smart-fd8931f8-1637-4e98-aee2-80a5e20ed446
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613618551 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.2613618551
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3963622501
Short name T882
Test name
Test status
Simulation time 36304536 ps
CPU time 1.34 seconds
Started Jul 10 05:15:59 PM PDT 24
Finished Jul 10 05:16:09 PM PDT 24
Peak memory 211240 kb
Host smart-7e1780fc-9398-45e7-aa2e-462c1ade300a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963622501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.3963622501
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1163267638
Short name T902
Test name
Test status
Simulation time 85898766 ps
CPU time 2.03 seconds
Started Jul 10 05:15:46 PM PDT 24
Finished Jul 10 05:16:01 PM PDT 24
Peak memory 217444 kb
Host smart-add004cd-ef54-4224-84a5-a348615cbe8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163267638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.1163267638
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.4073550584
Short name T884
Test name
Test status
Simulation time 25306466 ps
CPU time 1.89 seconds
Started Jul 10 05:15:56 PM PDT 24
Finished Jul 10 05:16:08 PM PDT 24
Peak memory 217564 kb
Host smart-68056893-dc41-42f4-ac31-fc776ad38962
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073550584 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.4073550584
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.291551728
Short name T986
Test name
Test status
Simulation time 63325234 ps
CPU time 0.92 seconds
Started Jul 10 05:15:53 PM PDT 24
Finished Jul 10 05:16:04 PM PDT 24
Peak memory 209028 kb
Host smart-52599754-1380-4170-9c2a-2b242bd395b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291551728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.291551728
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2235072545
Short name T913
Test name
Test status
Simulation time 128298309 ps
CPU time 1.83 seconds
Started Jul 10 05:15:45 PM PDT 24
Finished Jul 10 05:15:59 PM PDT 24
Peak memory 209064 kb
Host smart-131c04b4-6707-42a3-b21f-fafaf52feb9b
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235072545 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.2235072545
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1261316972
Short name T947
Test name
Test status
Simulation time 737166371 ps
CPU time 7.23 seconds
Started Jul 10 05:15:45 PM PDT 24
Finished Jul 10 05:16:05 PM PDT 24
Peak memory 209108 kb
Host smart-f5a2f6c9-7055-4061-bddd-b163485ff4fb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261316972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.1261316972
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1734706609
Short name T936
Test name
Test status
Simulation time 3848560903 ps
CPU time 12.11 seconds
Started Jul 10 05:15:50 PM PDT 24
Finished Jul 10 05:16:15 PM PDT 24
Peak memory 209208 kb
Host smart-14b61a9b-3cc4-413c-adfa-01cc0607adf1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734706609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.1734706609
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1863776707
Short name T873
Test name
Test status
Simulation time 58484905 ps
CPU time 2.02 seconds
Started Jul 10 05:15:47 PM PDT 24
Finished Jul 10 05:16:01 PM PDT 24
Peak memory 210312 kb
Host smart-7505e7e9-5f31-4354-a56d-047f3717cb4d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863776707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.1863776707
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.929311360
Short name T984
Test name
Test status
Simulation time 1122103132 ps
CPU time 6.87 seconds
Started Jul 10 05:15:47 PM PDT 24
Finished Jul 10 05:16:07 PM PDT 24
Peak memory 218516 kb
Host smart-56c1f774-e368-45c9-9d88-85bb7ec67eb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929311
360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.929311360
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.1224546283
Short name T965
Test name
Test status
Simulation time 78367770 ps
CPU time 1.46 seconds
Started Jul 10 05:15:44 PM PDT 24
Finished Jul 10 05:15:58 PM PDT 24
Peak memory 217416 kb
Host smart-e02a2329-6044-433a-8d3a-7d3ca8928c7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224546283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.1224546283
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1186175108
Short name T214
Test name
Test status
Simulation time 41447105 ps
CPU time 1.47 seconds
Started Jul 10 05:15:46 PM PDT 24
Finished Jul 10 05:16:00 PM PDT 24
Peak memory 217572 kb
Host smart-c1675721-3cea-4150-8b60-8ea16d19860f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186175108 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.1186175108
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.4231563959
Short name T894
Test name
Test status
Simulation time 86110409 ps
CPU time 1.04 seconds
Started Jul 10 05:15:44 PM PDT 24
Finished Jul 10 05:15:58 PM PDT 24
Peak memory 209236 kb
Host smart-da304f64-b253-4aa7-8006-2f379e8071ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231563959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.4231563959
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3102170015
Short name T987
Test name
Test status
Simulation time 40483194 ps
CPU time 1.32 seconds
Started Jul 10 05:16:03 PM PDT 24
Finished Jul 10 05:16:11 PM PDT 24
Peak memory 217712 kb
Host smart-8207b8cf-6906-4137-a810-7e5c5f81e19b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102170015 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.3102170015
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1078713995
Short name T931
Test name
Test status
Simulation time 43567059 ps
CPU time 0.92 seconds
Started Jul 10 05:15:52 PM PDT 24
Finished Jul 10 05:16:04 PM PDT 24
Peak memory 209168 kb
Host smart-a88c57b6-2a89-4d05-91de-98e0e4742279
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078713995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.1078713995
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.4241824549
Short name T161
Test name
Test status
Simulation time 85622276 ps
CPU time 1.57 seconds
Started Jul 10 05:15:59 PM PDT 24
Finished Jul 10 05:16:10 PM PDT 24
Peak memory 208540 kb
Host smart-12484a23-a364-4223-94ca-de2cbccede53
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241824549 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.4241824549
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2187285034
Short name T883
Test name
Test status
Simulation time 193527072 ps
CPU time 5.73 seconds
Started Jul 10 05:15:51 PM PDT 24
Finished Jul 10 05:16:08 PM PDT 24
Peak memory 209160 kb
Host smart-f07142dc-eb1e-4c41-a487-52c08fc7ec09
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187285034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.2187285034
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1377927331
Short name T878
Test name
Test status
Simulation time 7067911470 ps
CPU time 14.36 seconds
Started Jul 10 05:15:48 PM PDT 24
Finished Jul 10 05:16:15 PM PDT 24
Peak memory 209208 kb
Host smart-ece61fd9-d0c9-40ec-954f-6415707359fa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377927331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.1377927331
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3517498037
Short name T946
Test name
Test status
Simulation time 544640457 ps
CPU time 1.54 seconds
Started Jul 10 05:16:02 PM PDT 24
Finished Jul 10 05:16:11 PM PDT 24
Peak memory 217316 kb
Host smart-199a8f7a-6bda-4902-bf2e-e1faff821997
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517498037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.3517498037
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2928208884
Short name T969
Test name
Test status
Simulation time 73919948 ps
CPU time 1.69 seconds
Started Jul 10 05:16:02 PM PDT 24
Finished Jul 10 05:16:11 PM PDT 24
Peak memory 217716 kb
Host smart-3b1cb955-6189-4706-a441-bf16583b8911
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292820
8884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2928208884
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1986214207
Short name T885
Test name
Test status
Simulation time 2847937438 ps
CPU time 4.49 seconds
Started Jul 10 05:15:55 PM PDT 24
Finished Jul 10 05:16:09 PM PDT 24
Peak memory 209216 kb
Host smart-c548fee0-cb0d-4116-9dfb-0f5a034e5176
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986214207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.1986214207
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3620633706
Short name T900
Test name
Test status
Simulation time 21382442 ps
CPU time 1.27 seconds
Started Jul 10 05:15:52 PM PDT 24
Finished Jul 10 05:16:05 PM PDT 24
Peak memory 211192 kb
Host smart-da402fb0-35d3-4504-b338-9ef1270e96b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620633706 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.3620633706
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2346999497
Short name T988
Test name
Test status
Simulation time 26990150 ps
CPU time 1.42 seconds
Started Jul 10 05:15:51 PM PDT 24
Finished Jul 10 05:16:04 PM PDT 24
Peak memory 217292 kb
Host smart-c435e681-185a-4c31-a138-b865cc697dea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346999497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.2346999497
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1247681916
Short name T967
Test name
Test status
Simulation time 47069225 ps
CPU time 3.1 seconds
Started Jul 10 05:15:49 PM PDT 24
Finished Jul 10 05:16:04 PM PDT 24
Peak memory 217440 kb
Host smart-2462f6b6-dff9-4df2-9a33-c15d423e94df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247681916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.1247681916
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3508367382
Short name T153
Test name
Test status
Simulation time 759966366 ps
CPU time 5.19 seconds
Started Jul 10 05:15:57 PM PDT 24
Finished Jul 10 05:16:11 PM PDT 24
Peak memory 217676 kb
Host smart-0d468300-4774-424f-9362-ba820ffa2f6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508367382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.3508367382
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.2543913424
Short name T526
Test name
Test status
Simulation time 26169300 ps
CPU time 1.03 seconds
Started Jul 10 05:00:58 PM PDT 24
Finished Jul 10 05:01:00 PM PDT 24
Peak memory 208456 kb
Host smart-c45a2c54-b94f-4a0a-8220-bfb1ee7223ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543913424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.2543913424
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.1075840588
Short name T26
Test name
Test status
Simulation time 133749303 ps
CPU time 0.82 seconds
Started Jul 10 05:00:57 PM PDT 24
Finished Jul 10 05:00:59 PM PDT 24
Peak memory 208448 kb
Host smart-1f4f443a-c63e-458c-a3ee-e73d00737459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075840588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.1075840588
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.1867108358
Short name T612
Test name
Test status
Simulation time 985397332 ps
CPU time 9 seconds
Started Jul 10 05:00:57 PM PDT 24
Finished Jul 10 05:01:07 PM PDT 24
Peak memory 225456 kb
Host smart-a99546cc-7a78-44d3-8963-6199b2cf4d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867108358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.1867108358
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.3023366249
Short name T302
Test name
Test status
Simulation time 393021571 ps
CPU time 4.11 seconds
Started Jul 10 05:01:02 PM PDT 24
Finished Jul 10 05:01:07 PM PDT 24
Peak memory 217084 kb
Host smart-840c1980-2c82-4512-8582-001814870f4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023366249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.3023366249
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.3506436053
Short name T757
Test name
Test status
Simulation time 6478781961 ps
CPU time 48.42 seconds
Started Jul 10 05:00:59 PM PDT 24
Finished Jul 10 05:01:49 PM PDT 24
Peak memory 218288 kb
Host smart-b70a9811-c41c-4e48-b144-67f8efb51ef0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506436053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.3506436053
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.1484534144
Short name T417
Test name
Test status
Simulation time 187301382 ps
CPU time 2.95 seconds
Started Jul 10 05:00:59 PM PDT 24
Finished Jul 10 05:01:04 PM PDT 24
Peak memory 217052 kb
Host smart-c8440704-47ce-4511-8ee8-76311c633f0e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484534144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.1
484534144
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.3723166146
Short name T680
Test name
Test status
Simulation time 221523291 ps
CPU time 2.59 seconds
Started Jul 10 05:00:57 PM PDT 24
Finished Jul 10 05:01:00 PM PDT 24
Peak memory 220912 kb
Host smart-4565bc65-4700-422a-a5ac-5649fda47ead
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723166146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.3723166146
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.1983240173
Short name T350
Test name
Test status
Simulation time 2009142126 ps
CPU time 20.46 seconds
Started Jul 10 05:00:59 PM PDT 24
Finished Jul 10 05:01:21 PM PDT 24
Peak memory 217344 kb
Host smart-660dccc3-dc7d-4bbc-a8b7-2a10bd4a1fe0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983240173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.1983240173
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.1600615997
Short name T462
Test name
Test status
Simulation time 377802592 ps
CPU time 4.59 seconds
Started Jul 10 05:01:02 PM PDT 24
Finished Jul 10 05:01:08 PM PDT 24
Peak memory 216992 kb
Host smart-8533c0fc-33db-480b-808e-36ea86445dae
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600615997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
1600615997
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.2319491995
Short name T572
Test name
Test status
Simulation time 3384348698 ps
CPU time 31.52 seconds
Started Jul 10 05:00:59 PM PDT 24
Finished Jul 10 05:01:33 PM PDT 24
Peak memory 250392 kb
Host smart-1dc866e6-57fd-4a0b-9cd1-37b191a5de17
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319491995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.2319491995
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.3564026820
Short name T763
Test name
Test status
Simulation time 51331456 ps
CPU time 2.41 seconds
Started Jul 10 05:01:02 PM PDT 24
Finished Jul 10 05:01:05 PM PDT 24
Peak memory 221604 kb
Host smart-9e184e1f-b86d-4842-9a61-c8817f2ba3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564026820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.3564026820
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.3030731158
Short name T354
Test name
Test status
Simulation time 809404030 ps
CPU time 22.78 seconds
Started Jul 10 05:00:59 PM PDT 24
Finished Jul 10 05:01:24 PM PDT 24
Peak memory 217180 kb
Host smart-f58da2da-c30a-4cc9-a3db-f9ac6a833591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030731158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.3030731158
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.230160620
Short name T114
Test name
Test status
Simulation time 3296221394 ps
CPU time 40.09 seconds
Started Jul 10 05:00:58 PM PDT 24
Finished Jul 10 05:01:40 PM PDT 24
Peak memory 283432 kb
Host smart-171542ac-69f8-4f3a-a8c7-99a703cb2669
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230160620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.230160620
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.1289690211
Short name T668
Test name
Test status
Simulation time 702889842 ps
CPU time 12.43 seconds
Started Jul 10 05:00:57 PM PDT 24
Finished Jul 10 05:01:11 PM PDT 24
Peak memory 225364 kb
Host smart-1cf9a6fe-8402-4d93-97ab-3bf45799ea88
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289690211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.1289690211
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.2043104749
Short name T68
Test name
Test status
Simulation time 1539791182 ps
CPU time 12.3 seconds
Started Jul 10 05:00:58 PM PDT 24
Finished Jul 10 05:01:11 PM PDT 24
Peak memory 217596 kb
Host smart-d8332081-2544-4677-a415-b046bc75f57c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043104749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.2
043104749
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.2589046874
Short name T689
Test name
Test status
Simulation time 2407219595 ps
CPU time 8.14 seconds
Started Jul 10 05:01:02 PM PDT 24
Finished Jul 10 05:01:11 PM PDT 24
Peak memory 224404 kb
Host smart-7d45b6a7-1d67-4dd0-9b3f-6e531d5f634c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589046874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.2589046874
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.1628544198
Short name T614
Test name
Test status
Simulation time 121500863 ps
CPU time 2.57 seconds
Started Jul 10 05:00:51 PM PDT 24
Finished Jul 10 05:00:54 PM PDT 24
Peak memory 214100 kb
Host smart-d907faf3-f5ea-47dc-8501-ca47747276f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628544198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.1628544198
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.2992371926
Short name T796
Test name
Test status
Simulation time 267309416 ps
CPU time 29.98 seconds
Started Jul 10 05:01:00 PM PDT 24
Finished Jul 10 05:01:31 PM PDT 24
Peak memory 250380 kb
Host smart-d9471077-3391-4c9b-9411-f14504929a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992371926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.2992371926
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.3522960584
Short name T284
Test name
Test status
Simulation time 75362979 ps
CPU time 8.65 seconds
Started Jul 10 05:00:58 PM PDT 24
Finished Jul 10 05:01:07 PM PDT 24
Peak memory 250360 kb
Host smart-d26e7765-b161-4b97-a76e-972f41b643c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522960584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.3522960584
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.3808670551
Short name T187
Test name
Test status
Simulation time 8229221038 ps
CPU time 92.66 seconds
Started Jul 10 05:00:59 PM PDT 24
Finished Jul 10 05:02:33 PM PDT 24
Peak memory 266524 kb
Host smart-9146be9a-0bfc-4ca2-b5fc-cb08ead796f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808670551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.3808670551
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.3820138551
Short name T251
Test name
Test status
Simulation time 21696261 ps
CPU time 0.94 seconds
Started Jul 10 05:00:57 PM PDT 24
Finished Jul 10 05:00:59 PM PDT 24
Peak memory 208468 kb
Host smart-a0b1e596-b7e3-443b-bac9-3386213a47b6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820138551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.3820138551
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.2561610023
Short name T605
Test name
Test status
Simulation time 21559559 ps
CPU time 1.19 seconds
Started Jul 10 05:01:13 PM PDT 24
Finished Jul 10 05:01:15 PM PDT 24
Peak memory 208432 kb
Host smart-a007450c-2f4f-41d5-ad27-2d79bae0c9ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561610023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.2561610023
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.1326341022
Short name T311
Test name
Test status
Simulation time 1657727688 ps
CPU time 14.11 seconds
Started Jul 10 05:01:06 PM PDT 24
Finished Jul 10 05:01:22 PM PDT 24
Peak memory 217660 kb
Host smart-155ca1ad-32a5-44f4-a848-3521f76dea2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326341022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.1326341022
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.1370352121
Short name T570
Test name
Test status
Simulation time 854364781 ps
CPU time 10.93 seconds
Started Jul 10 05:01:07 PM PDT 24
Finished Jul 10 05:01:19 PM PDT 24
Peak memory 217092 kb
Host smart-3143cdea-c2e5-4f6d-a54b-c96ea1c23d4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370352121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.1370352121
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.3170978098
Short name T630
Test name
Test status
Simulation time 5206862174 ps
CPU time 49.24 seconds
Started Jul 10 05:01:06 PM PDT 24
Finished Jul 10 05:01:57 PM PDT 24
Peak memory 218480 kb
Host smart-fa772a38-4627-4756-8ee4-bef6cc74bb81
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170978098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.3170978098
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.3874700910
Short name T611
Test name
Test status
Simulation time 9813817994 ps
CPU time 54.55 seconds
Started Jul 10 05:01:08 PM PDT 24
Finished Jul 10 05:02:04 PM PDT 24
Peak memory 217196 kb
Host smart-3825bb96-7a57-4087-b3b5-9b1e135e90a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874700910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.3
874700910
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.1602527554
Short name T116
Test name
Test status
Simulation time 338467590 ps
CPU time 5.28 seconds
Started Jul 10 05:01:08 PM PDT 24
Finished Jul 10 05:01:16 PM PDT 24
Peak memory 222388 kb
Host smart-760891c0-75df-473a-ba30-bd1ebf388f5f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602527554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.1602527554
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.4123726307
Short name T11
Test name
Test status
Simulation time 1908665557 ps
CPU time 13.64 seconds
Started Jul 10 05:01:11 PM PDT 24
Finished Jul 10 05:01:26 PM PDT 24
Peak memory 217052 kb
Host smart-1e16c800-c63f-4803-98a9-f25187f0eefd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123726307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.4123726307
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.2408124393
Short name T303
Test name
Test status
Simulation time 1536181909 ps
CPU time 8.36 seconds
Started Jul 10 05:01:07 PM PDT 24
Finished Jul 10 05:01:18 PM PDT 24
Peak memory 216976 kb
Host smart-e54a5594-df7a-4ae6-b10f-8e90b1e60ad8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408124393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
2408124393
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.2422855542
Short name T268
Test name
Test status
Simulation time 779429174 ps
CPU time 26.44 seconds
Started Jul 10 05:01:05 PM PDT 24
Finished Jul 10 05:01:32 PM PDT 24
Peak memory 250380 kb
Host smart-de9b3c57-c729-43f2-aaee-65223d195441
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422855542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.2422855542
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.2703130349
Short name T382
Test name
Test status
Simulation time 1728221972 ps
CPU time 17.01 seconds
Started Jul 10 05:01:07 PM PDT 24
Finished Jul 10 05:01:26 PM PDT 24
Peak memory 249524 kb
Host smart-d88dfe5f-667b-4870-bf50-e4d169806e28
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703130349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.2703130349
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.2457628853
Short name T789
Test name
Test status
Simulation time 21022956 ps
CPU time 1.92 seconds
Started Jul 10 05:01:07 PM PDT 24
Finished Jul 10 05:01:11 PM PDT 24
Peak memory 217648 kb
Host smart-f6c63e57-9b5e-4a68-8bfe-79c6dc4a7b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457628853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.2457628853
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.3829059587
Short name T489
Test name
Test status
Simulation time 352027432 ps
CPU time 12.71 seconds
Started Jul 10 05:01:10 PM PDT 24
Finished Jul 10 05:01:25 PM PDT 24
Peak memory 217132 kb
Host smart-4bc56ef0-4f25-403e-8207-aa6383db17e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829059587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.3829059587
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.1728177066
Short name T113
Test name
Test status
Simulation time 127060658 ps
CPU time 26.07 seconds
Started Jul 10 05:01:15 PM PDT 24
Finished Jul 10 05:01:43 PM PDT 24
Peak memory 281900 kb
Host smart-aba7162d-970a-427d-a6d1-c9d7440ffe85
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728177066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.1728177066
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.3039726803
Short name T71
Test name
Test status
Simulation time 372029916 ps
CPU time 17.15 seconds
Started Jul 10 05:01:06 PM PDT 24
Finished Jul 10 05:01:25 PM PDT 24
Peak memory 218364 kb
Host smart-4ecac8ac-5c76-4527-bb5b-dbef0e0665b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039726803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.3039726803
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.1207942955
Short name T369
Test name
Test status
Simulation time 476344546 ps
CPU time 7.4 seconds
Started Jul 10 05:01:16 PM PDT 24
Finished Jul 10 05:01:24 PM PDT 24
Peak memory 225392 kb
Host smart-bd2326ee-90f9-40b5-ada4-fd83f1539f42
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207942955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.1207942955
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.3260256183
Short name T805
Test name
Test status
Simulation time 1183336735 ps
CPU time 11.18 seconds
Started Jul 10 05:01:07 PM PDT 24
Finished Jul 10 05:01:20 PM PDT 24
Peak memory 224532 kb
Host smart-15e92cbf-208e-4cd5-8472-0dc849f2609e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260256183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.3260256183
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.2633432263
Short name T89
Test name
Test status
Simulation time 50552232 ps
CPU time 2.89 seconds
Started Jul 10 05:00:59 PM PDT 24
Finished Jul 10 05:01:03 PM PDT 24
Peak memory 214100 kb
Host smart-1aedb0d1-c199-41b3-8fc8-23cf41515300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633432263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.2633432263
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.3584777602
Short name T532
Test name
Test status
Simulation time 161102756 ps
CPU time 19.63 seconds
Started Jul 10 05:01:07 PM PDT 24
Finished Jul 10 05:01:28 PM PDT 24
Peak memory 250496 kb
Host smart-5408422b-88ea-4665-95de-27bbb8f6565e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584777602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.3584777602
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.684069118
Short name T840
Test name
Test status
Simulation time 79613596 ps
CPU time 6.47 seconds
Started Jul 10 05:01:07 PM PDT 24
Finished Jul 10 05:01:16 PM PDT 24
Peak memory 243956 kb
Host smart-974c5b48-dda0-42fd-9e96-6d1db1d25f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684069118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.684069118
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.3850446864
Short name T413
Test name
Test status
Simulation time 10783951434 ps
CPU time 165.09 seconds
Started Jul 10 05:01:15 PM PDT 24
Finished Jul 10 05:04:02 PM PDT 24
Peak memory 279192 kb
Host smart-15ce665a-7e05-47cf-9e79-d0175395a176
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850446864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.3850446864
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.3883184572
Short name T99
Test name
Test status
Simulation time 15086872 ps
CPU time 1.05 seconds
Started Jul 10 05:00:59 PM PDT 24
Finished Jul 10 05:01:02 PM PDT 24
Peak memory 211252 kb
Host smart-ffb5b17c-2591-47cf-8aa6-462243e4e7ba
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883184572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.3883184572
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.2058498768
Short name T168
Test name
Test status
Simulation time 22957572 ps
CPU time 1.11 seconds
Started Jul 10 05:02:27 PM PDT 24
Finished Jul 10 05:02:31 PM PDT 24
Peak memory 208416 kb
Host smart-20c271f5-b3b2-44ec-a5c3-269ff482102c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058498768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.2058498768
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.1951403121
Short name T724
Test name
Test status
Simulation time 2314353890 ps
CPU time 12.66 seconds
Started Jul 10 05:02:25 PM PDT 24
Finished Jul 10 05:02:40 PM PDT 24
Peak memory 217776 kb
Host smart-82f65e14-8a8e-454e-85b3-cf4aab13b55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951403121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.1951403121
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.4044890866
Short name T189
Test name
Test status
Simulation time 1878241172 ps
CPU time 10.39 seconds
Started Jul 10 05:02:27 PM PDT 24
Finished Jul 10 05:02:40 PM PDT 24
Peak memory 217076 kb
Host smart-b65b7559-48e1-430d-89a4-89875b36e74f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044890866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.4044890866
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.2321848057
Short name T810
Test name
Test status
Simulation time 987432696 ps
CPU time 17.55 seconds
Started Jul 10 05:02:26 PM PDT 24
Finished Jul 10 05:02:47 PM PDT 24
Peak memory 217596 kb
Host smart-61b787c4-4307-4e00-bedf-200042b3f599
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321848057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.2321848057
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.3268174874
Short name T691
Test name
Test status
Simulation time 356472788 ps
CPU time 5.58 seconds
Started Jul 10 05:02:26 PM PDT 24
Finished Jul 10 05:02:35 PM PDT 24
Peak memory 217644 kb
Host smart-dc84a25c-0e3d-4e23-909d-35e453962910
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268174874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.3268174874
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.2335780267
Short name T75
Test name
Test status
Simulation time 912026048 ps
CPU time 6.89 seconds
Started Jul 10 05:02:27 PM PDT 24
Finished Jul 10 05:02:38 PM PDT 24
Peak memory 217076 kb
Host smart-ee5e0d12-de82-453d-bc7a-2d41295dfab5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335780267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.2335780267
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.1621083131
Short name T366
Test name
Test status
Simulation time 5159626938 ps
CPU time 91.05 seconds
Started Jul 10 05:02:25 PM PDT 24
Finished Jul 10 05:03:59 PM PDT 24
Peak memory 280976 kb
Host smart-10ea765c-813e-40d8-bef1-14b27de3cac1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621083131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.1621083131
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.3010511282
Short name T316
Test name
Test status
Simulation time 4800666138 ps
CPU time 21.13 seconds
Started Jul 10 05:02:27 PM PDT 24
Finished Jul 10 05:02:52 PM PDT 24
Peak memory 245492 kb
Host smart-8477963f-9da0-4048-a106-ae1538aa54fd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010511282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.3010511282
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.446687127
Short name T823
Test name
Test status
Simulation time 152608436 ps
CPU time 2.73 seconds
Started Jul 10 05:02:27 PM PDT 24
Finished Jul 10 05:02:33 PM PDT 24
Peak memory 217648 kb
Host smart-18539afb-278f-4d79-9cc7-b32afaeef3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446687127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.446687127
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.3466158412
Short name T585
Test name
Test status
Simulation time 353606614 ps
CPU time 9.77 seconds
Started Jul 10 05:02:26 PM PDT 24
Finished Jul 10 05:02:39 PM PDT 24
Peak memory 218304 kb
Host smart-68dfb79f-a50c-4f9a-af60-e7db7d742729
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466158412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.3466158412
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.977223896
Short name T839
Test name
Test status
Simulation time 1456839900 ps
CPU time 9.11 seconds
Started Jul 10 05:02:26 PM PDT 24
Finished Jul 10 05:02:38 PM PDT 24
Peak memory 225444 kb
Host smart-d7e8189f-6182-4d41-88f2-77a7d99c8272
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977223896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_di
gest.977223896
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.1440176618
Short name T751
Test name
Test status
Simulation time 867623077 ps
CPU time 11.29 seconds
Started Jul 10 05:02:25 PM PDT 24
Finished Jul 10 05:02:39 PM PDT 24
Peak memory 217720 kb
Host smart-65f75f3d-4eef-44c2-bdb1-cbf36646b667
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440176618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
1440176618
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.2936852826
Short name T610
Test name
Test status
Simulation time 716010300 ps
CPU time 12.65 seconds
Started Jul 10 05:02:24 PM PDT 24
Finished Jul 10 05:02:38 PM PDT 24
Peak memory 225116 kb
Host smart-749609b3-51bc-48a4-a31d-1bea3f6f7f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936852826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.2936852826
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.1598652445
Short name T400
Test name
Test status
Simulation time 895913315 ps
CPU time 20.81 seconds
Started Jul 10 05:02:28 PM PDT 24
Finished Jul 10 05:02:52 PM PDT 24
Peak memory 250480 kb
Host smart-cfd28dbc-3135-47ef-b5ec-415e46f983e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598652445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.1598652445
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.2628487701
Short name T388
Test name
Test status
Simulation time 495245589 ps
CPU time 7.12 seconds
Started Jul 10 05:02:27 PM PDT 24
Finished Jul 10 05:02:37 PM PDT 24
Peak memory 249816 kb
Host smart-21db0bd6-94a3-40da-b707-09c391dde82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628487701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.2628487701
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.1030966450
Short name T108
Test name
Test status
Simulation time 14112010261 ps
CPU time 138.3 seconds
Started Jul 10 05:02:26 PM PDT 24
Finished Jul 10 05:04:48 PM PDT 24
Peak memory 275704 kb
Host smart-6dad1941-6a90-472a-918d-0f6de4aa9f20
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030966450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.1030966450
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.1034246531
Short name T464
Test name
Test status
Simulation time 12994659572 ps
CPU time 465.52 seconds
Started Jul 10 05:02:25 PM PDT 24
Finished Jul 10 05:10:12 PM PDT 24
Peak memory 372448 kb
Host smart-ae379a5d-3f36-4526-a000-aa1c24616873
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1034246531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.1034246531
Directory /workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.761201797
Short name T604
Test name
Test status
Simulation time 19540030 ps
CPU time 1.18 seconds
Started Jul 10 05:02:25 PM PDT 24
Finished Jul 10 05:02:28 PM PDT 24
Peak memory 217184 kb
Host smart-3e86c25f-5f22-4390-8e19-57cbf3c42cc8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761201797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ct
rl_volatile_unlock_smoke.761201797
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.290776320
Short name T446
Test name
Test status
Simulation time 197111923 ps
CPU time 0.98 seconds
Started Jul 10 05:02:34 PM PDT 24
Finished Jul 10 05:02:36 PM PDT 24
Peak memory 208472 kb
Host smart-ad31be74-b238-47d9-beda-e169b9f2c906
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290776320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.290776320
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.3832326403
Short name T613
Test name
Test status
Simulation time 345799110 ps
CPU time 9.98 seconds
Started Jul 10 05:02:36 PM PDT 24
Finished Jul 10 05:02:49 PM PDT 24
Peak memory 216852 kb
Host smart-1d4b4978-d82b-4955-96ed-310e338210b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832326403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.3832326403
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.3651353907
Short name T419
Test name
Test status
Simulation time 9734374702 ps
CPU time 37.46 seconds
Started Jul 10 05:02:34 PM PDT 24
Finished Jul 10 05:03:12 PM PDT 24
Peak memory 218316 kb
Host smart-a46ce9e3-772c-4c24-8d25-9e17567881f7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651353907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.3651353907
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.4182337533
Short name T256
Test name
Test status
Simulation time 1839985122 ps
CPU time 13.65 seconds
Started Jul 10 05:02:36 PM PDT 24
Finished Jul 10 05:02:52 PM PDT 24
Peak memory 217596 kb
Host smart-5598d8c5-d7fa-46e7-9f82-c5d12c27cdb2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182337533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.4182337533
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.742892926
Short name T426
Test name
Test status
Simulation time 1731108659 ps
CPU time 11.57 seconds
Started Jul 10 05:02:36 PM PDT 24
Finished Jul 10 05:02:50 PM PDT 24
Peak memory 217004 kb
Host smart-b7296cd7-ed74-4a0d-b38b-ea5020e7a16e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742892926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke.
742892926
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.977328138
Short name T505
Test name
Test status
Simulation time 6177316656 ps
CPU time 40.84 seconds
Started Jul 10 05:02:34 PM PDT 24
Finished Jul 10 05:03:17 PM PDT 24
Peak memory 267760 kb
Host smart-b3cf484a-1530-470e-b1ba-2cdfaf962f1b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977328138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_state_failure.977328138
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.154299141
Short name T271
Test name
Test status
Simulation time 2434866336 ps
CPU time 15.45 seconds
Started Jul 10 05:02:35 PM PDT 24
Finished Jul 10 05:02:53 PM PDT 24
Peak memory 246116 kb
Host smart-2bec636e-086c-4c8a-90ff-8ef0ae0d0dad
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154299141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_
jtag_state_post_trans.154299141
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.3848786481
Short name T348
Test name
Test status
Simulation time 134457818 ps
CPU time 3.63 seconds
Started Jul 10 05:02:35 PM PDT 24
Finished Jul 10 05:02:41 PM PDT 24
Peak memory 217672 kb
Host smart-fad8b7da-b59a-4cf5-870b-4e586afc6772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848786481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.3848786481
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.1766979493
Short name T699
Test name
Test status
Simulation time 492858512 ps
CPU time 12.17 seconds
Started Jul 10 05:02:34 PM PDT 24
Finished Jul 10 05:02:48 PM PDT 24
Peak memory 225256 kb
Host smart-3a9484f5-1365-421c-a105-4cafc7923eff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766979493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.1766979493
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.1114653222
Short name T430
Test name
Test status
Simulation time 805215669 ps
CPU time 8.31 seconds
Started Jul 10 05:02:36 PM PDT 24
Finished Jul 10 05:02:47 PM PDT 24
Peak memory 217840 kb
Host smart-35b8ea4c-c6ba-4b26-97d4-efd1128fd8a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114653222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
1114653222
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.2283936897
Short name T838
Test name
Test status
Simulation time 2486967060 ps
CPU time 8.81 seconds
Started Jul 10 05:02:36 PM PDT 24
Finished Jul 10 05:02:47 PM PDT 24
Peak memory 225520 kb
Host smart-a7581abb-56b4-48a4-814f-394afdda8f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283936897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.2283936897
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.2399358367
Short name T473
Test name
Test status
Simulation time 538408479 ps
CPU time 2.75 seconds
Started Jul 10 05:02:27 PM PDT 24
Finished Jul 10 05:02:33 PM PDT 24
Peak memory 214348 kb
Host smart-4722a863-4b84-453e-8813-214db72fa0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399358367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.2399358367
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.2255585999
Short name T252
Test name
Test status
Simulation time 680376655 ps
CPU time 29.31 seconds
Started Jul 10 05:02:34 PM PDT 24
Finished Jul 10 05:03:05 PM PDT 24
Peak memory 250448 kb
Host smart-b528bcfc-e3c4-4756-9a2f-898cd7c28160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255585999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.2255585999
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.4009514876
Short name T752
Test name
Test status
Simulation time 74845602 ps
CPU time 9.17 seconds
Started Jul 10 05:02:37 PM PDT 24
Finished Jul 10 05:02:49 PM PDT 24
Peak memory 250472 kb
Host smart-7a90e6a9-8eea-4a3f-aa07-ac32af851508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009514876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.4009514876
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.3257672748
Short name T739
Test name
Test status
Simulation time 55363245234 ps
CPU time 223.39 seconds
Started Jul 10 05:02:35 PM PDT 24
Finished Jul 10 05:06:21 PM PDT 24
Peak memory 252136 kb
Host smart-69667f7d-3e2e-4c4e-be27-447747eda451
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257672748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.3257672748
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.3612858425
Short name T162
Test name
Test status
Simulation time 5639159774 ps
CPU time 79.58 seconds
Started Jul 10 05:02:35 PM PDT 24
Finished Jul 10 05:03:56 PM PDT 24
Peak memory 276520 kb
Host smart-74b221a6-2de0-4d90-a552-cb23db0b512f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3612858425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all_with_rand_reset.3612858425
Directory /workspace/11.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.1560090274
Short name T755
Test name
Test status
Simulation time 76235290 ps
CPU time 1.04 seconds
Started Jul 10 05:02:35 PM PDT 24
Finished Jul 10 05:02:37 PM PDT 24
Peak memory 217256 kb
Host smart-ee696299-41e2-4dd1-a37e-f78f1c2c8454
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560090274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.1560090274
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.3387821518
Short name T762
Test name
Test status
Simulation time 18821430 ps
CPU time 0.82 seconds
Started Jul 10 05:02:41 PM PDT 24
Finished Jul 10 05:02:43 PM PDT 24
Peak memory 208284 kb
Host smart-a45fdaa1-de29-48e7-a0ca-8cf841693ab7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387821518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.3387821518
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.2767514742
Short name T678
Test name
Test status
Simulation time 273900705 ps
CPU time 12.32 seconds
Started Jul 10 05:02:41 PM PDT 24
Finished Jul 10 05:02:55 PM PDT 24
Peak memory 217652 kb
Host smart-f84bc714-63d7-4990-8a6a-54d574c5a0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767514742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.2767514742
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.3426429451
Short name T97
Test name
Test status
Simulation time 1799008431 ps
CPU time 11.7 seconds
Started Jul 10 05:02:43 PM PDT 24
Finished Jul 10 05:02:57 PM PDT 24
Peak memory 217100 kb
Host smart-57da0862-1048-4218-ac84-f436d6dda6a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426429451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.3426429451
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.1859010422
Short name T719
Test name
Test status
Simulation time 6812887314 ps
CPU time 47.62 seconds
Started Jul 10 05:02:42 PM PDT 24
Finished Jul 10 05:03:32 PM PDT 24
Peak memory 219188 kb
Host smart-ea09a289-7529-4947-b077-f6b3bd151d4d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859010422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.1859010422
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.1913808918
Short name T592
Test name
Test status
Simulation time 458021341 ps
CPU time 7.52 seconds
Started Jul 10 05:02:41 PM PDT 24
Finished Jul 10 05:02:50 PM PDT 24
Peak memory 217596 kb
Host smart-3f79e0f3-fb2b-4461-ad3b-695757024720
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913808918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.1913808918
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.2687113454
Short name T741
Test name
Test status
Simulation time 398196614 ps
CPU time 8.58 seconds
Started Jul 10 05:02:44 PM PDT 24
Finished Jul 10 05:02:55 PM PDT 24
Peak memory 216992 kb
Host smart-510ba092-0442-404d-9208-e17729308048
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687113454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.2687113454
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.1110955435
Short name T380
Test name
Test status
Simulation time 4669699761 ps
CPU time 55.64 seconds
Started Jul 10 05:02:42 PM PDT 24
Finished Jul 10 05:03:40 PM PDT 24
Peak memory 279576 kb
Host smart-2716b1fa-b2cd-41a7-83c0-8d53035da253
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110955435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.1110955435
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.3164049731
Short name T556
Test name
Test status
Simulation time 1098445633 ps
CPU time 35.18 seconds
Started Jul 10 05:02:42 PM PDT 24
Finished Jul 10 05:03:20 PM PDT 24
Peak memory 250316 kb
Host smart-8bdc500e-5c28-4e1e-95e2-727902b2ee0d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164049731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.3164049731
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.3659538970
Short name T538
Test name
Test status
Simulation time 56252513 ps
CPU time 3.13 seconds
Started Jul 10 05:02:43 PM PDT 24
Finished Jul 10 05:02:49 PM PDT 24
Peak memory 217660 kb
Host smart-2b52f203-3809-4ec3-a763-400f9acbb39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659538970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.3659538970
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.3194805637
Short name T100
Test name
Test status
Simulation time 1157865773 ps
CPU time 13.1 seconds
Started Jul 10 05:02:44 PM PDT 24
Finished Jul 10 05:03:00 PM PDT 24
Peak memory 218348 kb
Host smart-9ed32175-5056-4d88-ac8b-834f7ededee2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194805637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.3194805637
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.4072711022
Short name T342
Test name
Test status
Simulation time 2001445487 ps
CPU time 15.04 seconds
Started Jul 10 05:02:43 PM PDT 24
Finished Jul 10 05:03:00 PM PDT 24
Peak memory 225392 kb
Host smart-86f0ee17-8f3f-4aa5-8491-7f44d141bd37
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072711022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.4072711022
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.2287435311
Short name T679
Test name
Test status
Simulation time 462293378 ps
CPU time 11.97 seconds
Started Jul 10 05:02:41 PM PDT 24
Finished Jul 10 05:02:56 PM PDT 24
Peak memory 225364 kb
Host smart-da47386a-a781-4edd-aff2-6f15f9fc54a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287435311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
2287435311
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.1048093586
Short name T779
Test name
Test status
Simulation time 312722957 ps
CPU time 7.49 seconds
Started Jul 10 05:02:42 PM PDT 24
Finished Jul 10 05:02:52 PM PDT 24
Peak memory 224316 kb
Host smart-63359f47-22ae-4908-9195-7cedcbe8859a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048093586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.1048093586
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.950886710
Short name T491
Test name
Test status
Simulation time 746522342 ps
CPU time 3.03 seconds
Started Jul 10 05:02:34 PM PDT 24
Finished Jul 10 05:02:38 PM PDT 24
Peak memory 217076 kb
Host smart-10fc6c8a-fd87-4663-b4bb-7e5cfb5788ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950886710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.950886710
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.544580025
Short name T812
Test name
Test status
Simulation time 560800264 ps
CPU time 22.64 seconds
Started Jul 10 05:02:44 PM PDT 24
Finished Jul 10 05:03:09 PM PDT 24
Peak memory 250376 kb
Host smart-3a9cae64-8887-4565-9b3b-40f96d0f08b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544580025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.544580025
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.1092616862
Short name T336
Test name
Test status
Simulation time 371891711 ps
CPU time 7.82 seconds
Started Jul 10 05:02:41 PM PDT 24
Finished Jul 10 05:02:51 PM PDT 24
Peak memory 250464 kb
Host smart-a84684a5-ec2c-4067-b5e4-2ffa6927e5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092616862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.1092616862
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.614832983
Short name T694
Test name
Test status
Simulation time 55383454273 ps
CPU time 258.75 seconds
Started Jul 10 05:02:42 PM PDT 24
Finished Jul 10 05:07:03 PM PDT 24
Peak memory 315992 kb
Host smart-ae292d94-6732-4991-9bd1-a70fa32a67ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614832983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.614832983
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.3064533369
Short name T241
Test name
Test status
Simulation time 42856283 ps
CPU time 0.79 seconds
Started Jul 10 05:02:41 PM PDT 24
Finished Jul 10 05:02:44 PM PDT 24
Peak memory 208244 kb
Host smart-183c4427-6f73-4308-bcb2-693177ca1de3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064533369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.3064533369
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.938994127
Short name T465
Test name
Test status
Simulation time 20530089 ps
CPU time 0.94 seconds
Started Jul 10 05:02:47 PM PDT 24
Finished Jul 10 05:02:50 PM PDT 24
Peak memory 208364 kb
Host smart-46f31e53-f180-49c1-8121-28c7e8379415
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938994127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.938994127
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.1101118998
Short name T695
Test name
Test status
Simulation time 387935828 ps
CPU time 16.85 seconds
Started Jul 10 05:02:43 PM PDT 24
Finished Jul 10 05:03:03 PM PDT 24
Peak memory 225508 kb
Host smart-5d3fa4c2-2c49-4ab0-aa16-43a98e94f935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101118998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.1101118998
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.3002826703
Short name T375
Test name
Test status
Simulation time 637636164 ps
CPU time 1.3 seconds
Started Jul 10 05:02:43 PM PDT 24
Finished Jul 10 05:02:47 PM PDT 24
Peak memory 217124 kb
Host smart-74dff637-e319-4b2f-9b97-adbb614d6531
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002826703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.3002826703
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.1906641421
Short name T235
Test name
Test status
Simulation time 1873691026 ps
CPU time 21.83 seconds
Started Jul 10 05:02:43 PM PDT 24
Finished Jul 10 05:03:07 PM PDT 24
Peak memory 217600 kb
Host smart-42450c95-39e1-4dd7-8af0-152cbfe4cba6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906641421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.1906641421
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.2113834069
Short name T239
Test name
Test status
Simulation time 917219444 ps
CPU time 6.89 seconds
Started Jul 10 05:02:41 PM PDT 24
Finished Jul 10 05:02:51 PM PDT 24
Peak memory 222672 kb
Host smart-5d8540e8-349d-42c2-b8fc-355256fee719
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113834069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.2113834069
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.2677482699
Short name T788
Test name
Test status
Simulation time 207941706 ps
CPU time 5.98 seconds
Started Jul 10 05:02:43 PM PDT 24
Finished Jul 10 05:02:51 PM PDT 24
Peak memory 216984 kb
Host smart-a321cea9-277f-483a-ab3a-25e4217ac4f9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677482699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.2677482699
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.3987918137
Short name T832
Test name
Test status
Simulation time 3143679186 ps
CPU time 65.52 seconds
Started Jul 10 05:02:41 PM PDT 24
Finished Jul 10 05:03:49 PM PDT 24
Peak memory 252504 kb
Host smart-44400f1b-1397-46a2-82f8-a05d77bc6969
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987918137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.3987918137
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.3416144184
Short name T291
Test name
Test status
Simulation time 396966190 ps
CPU time 16.74 seconds
Started Jul 10 05:02:43 PM PDT 24
Finished Jul 10 05:03:03 PM PDT 24
Peak memory 249984 kb
Host smart-42cd5cad-c5be-4ffb-b3f6-127b8669d245
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416144184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.3416144184
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.1113748422
Short name T480
Test name
Test status
Simulation time 451251354 ps
CPU time 4.89 seconds
Started Jul 10 05:02:41 PM PDT 24
Finished Jul 10 05:02:48 PM PDT 24
Peak memory 217708 kb
Host smart-da0e5d23-7adb-4c6c-b948-a277264925e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113748422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.1113748422
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.80042546
Short name T793
Test name
Test status
Simulation time 647442111 ps
CPU time 16.74 seconds
Started Jul 10 05:02:45 PM PDT 24
Finished Jul 10 05:03:04 PM PDT 24
Peak memory 225508 kb
Host smart-6f0f0f62-7e02-415d-a4cd-822bf7fa3e80
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80042546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.80042546
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.3002655787
Short name T274
Test name
Test status
Simulation time 814511377 ps
CPU time 9.23 seconds
Started Jul 10 05:02:43 PM PDT 24
Finished Jul 10 05:02:55 PM PDT 24
Peak memory 225012 kb
Host smart-9567825e-dddc-47cb-b0f2-2feab54a57a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002655787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.3002655787
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.264315142
Short name T512
Test name
Test status
Simulation time 507644756 ps
CPU time 15.11 seconds
Started Jul 10 05:02:42 PM PDT 24
Finished Jul 10 05:03:00 PM PDT 24
Peak memory 217628 kb
Host smart-0051472f-99b9-4417-adb4-2135ebbceba6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264315142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.264315142
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.3074279745
Short name T482
Test name
Test status
Simulation time 603941701 ps
CPU time 13.32 seconds
Started Jul 10 05:02:42 PM PDT 24
Finished Jul 10 05:02:58 PM PDT 24
Peak memory 225452 kb
Host smart-2137ef25-7c39-4967-84ec-27e463299bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074279745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.3074279745
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.3488611530
Short name T81
Test name
Test status
Simulation time 82167009 ps
CPU time 1.57 seconds
Started Jul 10 05:02:42 PM PDT 24
Finished Jul 10 05:02:46 PM PDT 24
Peak memory 213160 kb
Host smart-06a6384f-e9f2-4c33-99e5-22318abab246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488611530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.3488611530
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.3950542701
Short name T393
Test name
Test status
Simulation time 925578919 ps
CPU time 25.51 seconds
Started Jul 10 05:02:43 PM PDT 24
Finished Jul 10 05:03:11 PM PDT 24
Peak memory 250412 kb
Host smart-708d4288-dd02-4708-b389-32d508ebf0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950542701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.3950542701
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.1712220137
Short name T421
Test name
Test status
Simulation time 885474185 ps
CPU time 6.03 seconds
Started Jul 10 05:02:41 PM PDT 24
Finished Jul 10 05:02:50 PM PDT 24
Peak memory 246128 kb
Host smart-20a86749-8225-4cb3-86ec-967a92c17f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712220137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.1712220137
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.541141221
Short name T704
Test name
Test status
Simulation time 673903546 ps
CPU time 43.24 seconds
Started Jul 10 05:02:50 PM PDT 24
Finished Jul 10 05:03:36 PM PDT 24
Peak memory 266796 kb
Host smart-3712d90a-3aa8-4fb2-9b94-331d3a0eb379
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541141221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.541141221
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.2710642290
Short name T257
Test name
Test status
Simulation time 13371249 ps
CPU time 0.96 seconds
Started Jul 10 05:02:43 PM PDT 24
Finished Jul 10 05:02:47 PM PDT 24
Peak memory 208392 kb
Host smart-b6b229cb-c21f-45fe-aa20-eb0a0e7ec2ea
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710642290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.2710642290
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.3338441861
Short name T25
Test name
Test status
Simulation time 31129278 ps
CPU time 0.94 seconds
Started Jul 10 05:02:53 PM PDT 24
Finished Jul 10 05:02:56 PM PDT 24
Peak memory 208460 kb
Host smart-abc028ed-d63b-45b8-b68e-20be952cb90c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338441861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.3338441861
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.3752570233
Short name T477
Test name
Test status
Simulation time 2742843576 ps
CPU time 12.4 seconds
Started Jul 10 05:02:47 PM PDT 24
Finished Jul 10 05:03:02 PM PDT 24
Peak memory 218364 kb
Host smart-d8a29fb5-ffb3-4a86-847d-1fd5a0402459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752570233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.3752570233
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.930149654
Short name T21
Test name
Test status
Simulation time 63412423 ps
CPU time 1.3 seconds
Started Jul 10 05:02:51 PM PDT 24
Finished Jul 10 05:02:55 PM PDT 24
Peak memory 216476 kb
Host smart-32eb11f5-3eda-4d0b-ac4f-fbafee498f6e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930149654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.930149654
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.1430433431
Short name T488
Test name
Test status
Simulation time 5071352895 ps
CPU time 38.43 seconds
Started Jul 10 05:02:48 PM PDT 24
Finished Jul 10 05:03:29 PM PDT 24
Peak memory 218300 kb
Host smart-1468af5c-54b8-49db-a44c-0eed97cd03f0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430433431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.1430433431
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.1272842372
Short name T220
Test name
Test status
Simulation time 267161068 ps
CPU time 5.59 seconds
Started Jul 10 05:02:48 PM PDT 24
Finished Jul 10 05:02:56 PM PDT 24
Peak memory 222424 kb
Host smart-513fb588-3d7e-4586-84c6-f0020ac078ba
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272842372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.1272842372
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.577804999
Short name T83
Test name
Test status
Simulation time 313243369 ps
CPU time 6.55 seconds
Started Jul 10 05:02:50 PM PDT 24
Finished Jul 10 05:02:59 PM PDT 24
Peak memory 217004 kb
Host smart-8b67c08b-e8db-4e13-867d-62ec9203e1b9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577804999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke.
577804999
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.2700144606
Short name T254
Test name
Test status
Simulation time 1816702643 ps
CPU time 42.66 seconds
Started Jul 10 05:02:52 PM PDT 24
Finished Jul 10 05:03:38 PM PDT 24
Peak memory 250344 kb
Host smart-5e048da3-7a1f-4aa8-9569-3de3f3e0ca43
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700144606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.2700144606
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.2097503450
Short name T397
Test name
Test status
Simulation time 5293317209 ps
CPU time 10.86 seconds
Started Jul 10 05:02:48 PM PDT 24
Finished Jul 10 05:03:02 PM PDT 24
Peak memory 225116 kb
Host smart-12951363-7c96-451a-86e2-846ede42bf9c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097503450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.2097503450
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.2386887923
Short name T224
Test name
Test status
Simulation time 19425977 ps
CPU time 1.73 seconds
Started Jul 10 05:02:51 PM PDT 24
Finished Jul 10 05:02:55 PM PDT 24
Peak memory 217664 kb
Host smart-c8fd0a05-ffef-4879-bfc8-808fac9241a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386887923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.2386887923
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.4290574192
Short name T249
Test name
Test status
Simulation time 829142522 ps
CPU time 8.49 seconds
Started Jul 10 05:02:51 PM PDT 24
Finished Jul 10 05:03:03 PM PDT 24
Peak memory 225468 kb
Host smart-ab5d42ee-1d97-49eb-b76c-92273c729534
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290574192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.4290574192
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.861557386
Short name T726
Test name
Test status
Simulation time 189573940 ps
CPU time 6.03 seconds
Started Jul 10 05:02:51 PM PDT 24
Finished Jul 10 05:02:59 PM PDT 24
Peak memory 224216 kb
Host smart-65a84064-c487-4f65-9ab3-331ba6bdf076
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861557386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.861557386
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.2883614382
Short name T330
Test name
Test status
Simulation time 860550358 ps
CPU time 16.71 seconds
Started Jul 10 05:02:52 PM PDT 24
Finished Jul 10 05:03:11 PM PDT 24
Peak memory 225492 kb
Host smart-6bd2af63-b816-4ed3-84bc-23ff589bc0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883614382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.2883614382
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.386679329
Short name T573
Test name
Test status
Simulation time 377154931 ps
CPU time 2.37 seconds
Started Jul 10 05:02:52 PM PDT 24
Finished Jul 10 05:02:57 PM PDT 24
Peak memory 217084 kb
Host smart-61a19d38-a8e6-41e3-afc4-26c55301c550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386679329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.386679329
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.1707633742
Short name T349
Test name
Test status
Simulation time 338795831 ps
CPU time 38.09 seconds
Started Jul 10 05:02:50 PM PDT 24
Finished Jul 10 05:03:30 PM PDT 24
Peak memory 250412 kb
Host smart-c50b97d6-3147-4176-8b0a-49a2654f1e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707633742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.1707633742
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.395412293
Short name T356
Test name
Test status
Simulation time 123927764 ps
CPU time 2.97 seconds
Started Jul 10 05:02:49 PM PDT 24
Finished Jul 10 05:02:54 PM PDT 24
Peak memory 225832 kb
Host smart-f8fa1712-ee1a-42d3-8e1a-d576e264a761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395412293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.395412293
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.4215679729
Short name T275
Test name
Test status
Simulation time 5589567680 ps
CPU time 211.35 seconds
Started Jul 10 05:02:48 PM PDT 24
Finished Jul 10 05:06:22 PM PDT 24
Peak memory 282204 kb
Host smart-cefb7b49-642f-4122-a4b5-a139ac633adf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215679729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.4215679729
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.1350517822
Short name T163
Test name
Test status
Simulation time 105860972856 ps
CPU time 819.21 seconds
Started Jul 10 05:02:51 PM PDT 24
Finished Jul 10 05:16:33 PM PDT 24
Peak memory 283328 kb
Host smart-baf81235-7c8b-40cf-af2a-4e4c34e2bc01
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1350517822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all_with_rand_reset.1350517822
Directory /workspace/14.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.439791978
Short name T862
Test name
Test status
Simulation time 15532296 ps
CPU time 0.98 seconds
Started Jul 10 05:02:53 PM PDT 24
Finished Jul 10 05:02:56 PM PDT 24
Peak memory 211388 kb
Host smart-a1d03cb0-aa73-4a56-9f1a-d24aa9cdabff
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439791978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ct
rl_volatile_unlock_smoke.439791978
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.1259908502
Short name T765
Test name
Test status
Simulation time 70110516 ps
CPU time 1.12 seconds
Started Jul 10 05:02:57 PM PDT 24
Finished Jul 10 05:03:02 PM PDT 24
Peak memory 208492 kb
Host smart-319194aa-ee74-41de-ac26-832192dcec3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259908502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.1259908502
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.974030281
Short name T517
Test name
Test status
Simulation time 364218025 ps
CPU time 9.92 seconds
Started Jul 10 05:02:56 PM PDT 24
Finished Jul 10 05:03:09 PM PDT 24
Peak memory 217620 kb
Host smart-4ead7919-d6b6-4afe-a6d9-0f09c9e11567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974030281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.974030281
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.202162188
Short name T809
Test name
Test status
Simulation time 286432251 ps
CPU time 1.3 seconds
Started Jul 10 05:02:56 PM PDT 24
Finished Jul 10 05:03:00 PM PDT 24
Peak memory 216984 kb
Host smart-e4e37c31-e607-4688-9376-1adf496bcd38
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202162188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.202162188
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.4102169964
Short name T50
Test name
Test status
Simulation time 1314364095 ps
CPU time 25.58 seconds
Started Jul 10 05:03:00 PM PDT 24
Finished Jul 10 05:03:28 PM PDT 24
Peak memory 218272 kb
Host smart-79d6a433-5ec9-4e1e-9c08-64ae964827b0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102169964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.4102169964
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.3440822492
Short name T318
Test name
Test status
Simulation time 252387589 ps
CPU time 5.6 seconds
Started Jul 10 05:02:57 PM PDT 24
Finished Jul 10 05:03:06 PM PDT 24
Peak memory 222192 kb
Host smart-c9d50d5e-1aa7-41c4-8c5b-1517b1649ce1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440822492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.3440822492
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.3895725451
Short name T807
Test name
Test status
Simulation time 190880559 ps
CPU time 2.16 seconds
Started Jul 10 05:02:58 PM PDT 24
Finished Jul 10 05:03:04 PM PDT 24
Peak memory 217000 kb
Host smart-308b9462-d160-41a8-a7eb-9f533caf49fa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895725451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.3895725451
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.576931850
Short name T341
Test name
Test status
Simulation time 845722709 ps
CPU time 35.65 seconds
Started Jul 10 05:02:59 PM PDT 24
Finished Jul 10 05:03:38 PM PDT 24
Peak memory 250320 kb
Host smart-ee833c46-0ede-4b6c-b95b-01eb1eea6ada
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576931850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_state_failure.576931850
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.2459532338
Short name T298
Test name
Test status
Simulation time 1617813207 ps
CPU time 14.76 seconds
Started Jul 10 05:02:56 PM PDT 24
Finished Jul 10 05:03:14 PM PDT 24
Peak memory 250384 kb
Host smart-ea27edef-b867-41ea-a09a-c3e0a9629dc1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459532338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.2459532338
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.2875191204
Short name T654
Test name
Test status
Simulation time 80097881 ps
CPU time 3.3 seconds
Started Jul 10 05:02:57 PM PDT 24
Finished Jul 10 05:03:04 PM PDT 24
Peak memory 222020 kb
Host smart-cd2bb79d-782c-447a-8bd4-195288faaa8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875191204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.2875191204
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.2530024602
Short name T587
Test name
Test status
Simulation time 628920873 ps
CPU time 13.08 seconds
Started Jul 10 05:02:56 PM PDT 24
Finished Jul 10 05:03:12 PM PDT 24
Peak memory 225380 kb
Host smart-3ddc7dde-67d1-47ed-8dd5-5ebf513bf9b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530024602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.2530024602
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.621922340
Short name T847
Test name
Test status
Simulation time 491311809 ps
CPU time 14.52 seconds
Started Jul 10 05:02:57 PM PDT 24
Finished Jul 10 05:03:15 PM PDT 24
Peak memory 217656 kb
Host smart-5ae05505-f5a3-45ea-85dd-b18376312a00
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621922340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.621922340
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.3349315130
Short name T457
Test name
Test status
Simulation time 335842446 ps
CPU time 13.26 seconds
Started Jul 10 05:02:56 PM PDT 24
Finished Jul 10 05:03:13 PM PDT 24
Peak memory 217728 kb
Host smart-653ea4d5-d63c-472a-b97c-82c38be5b7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349315130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.3349315130
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.408876154
Short name T85
Test name
Test status
Simulation time 31371041 ps
CPU time 2.46 seconds
Started Jul 10 05:02:47 PM PDT 24
Finished Jul 10 05:02:52 PM PDT 24
Peak memory 217096 kb
Host smart-0d057b20-c21c-40e4-9181-32ef2281e81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408876154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.408876154
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.955306409
Short name T117
Test name
Test status
Simulation time 451164984 ps
CPU time 34.47 seconds
Started Jul 10 05:02:48 PM PDT 24
Finished Jul 10 05:03:25 PM PDT 24
Peak memory 250392 kb
Host smart-a1999016-d5a4-45b5-8aae-5733416f13f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955306409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.955306409
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.3678260253
Short name T603
Test name
Test status
Simulation time 240544289 ps
CPU time 3.51 seconds
Started Jul 10 05:02:46 PM PDT 24
Finished Jul 10 05:02:52 PM PDT 24
Peak memory 221892 kb
Host smart-986632d3-8b4b-4cb1-a1ab-1375a5fb8f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678260253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.3678260253
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.3744507711
Short name T500
Test name
Test status
Simulation time 64339307616 ps
CPU time 464.34 seconds
Started Jul 10 05:02:59 PM PDT 24
Finished Jul 10 05:10:46 PM PDT 24
Peak memory 250364 kb
Host smart-a5ab38a1-445e-4b18-9de1-85e4ceac1d9b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744507711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.3744507711
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.34521995
Short name T492
Test name
Test status
Simulation time 15122751 ps
CPU time 0.79 seconds
Started Jul 10 05:02:50 PM PDT 24
Finished Jul 10 05:02:52 PM PDT 24
Peak memory 208244 kb
Host smart-afc11490-1f68-4b7c-8def-b58d943fc803
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34521995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_volatile_unlock_smoke.34521995
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.929780727
Short name T372
Test name
Test status
Simulation time 58093868 ps
CPU time 0.91 seconds
Started Jul 10 05:03:10 PM PDT 24
Finished Jul 10 05:03:13 PM PDT 24
Peak memory 208408 kb
Host smart-8d84d291-3dfa-4f3e-a05c-2b74b0be937f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929780727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.929780727
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.3863310703
Short name T637
Test name
Test status
Simulation time 7010559794 ps
CPU time 13.67 seconds
Started Jul 10 05:02:56 PM PDT 24
Finished Jul 10 05:03:13 PM PDT 24
Peak memory 225540 kb
Host smart-0a8f2cb8-2945-4b8f-9cf3-aa4d149e2a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863310703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.3863310703
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.1854910636
Short name T31
Test name
Test status
Simulation time 324818653 ps
CPU time 1.96 seconds
Started Jul 10 05:02:55 PM PDT 24
Finished Jul 10 05:03:00 PM PDT 24
Peak memory 217060 kb
Host smart-dd1390f1-7108-46ad-8df4-999440850119
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854910636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.1854910636
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.3888198987
Short name T433
Test name
Test status
Simulation time 5465045288 ps
CPU time 47.18 seconds
Started Jul 10 05:02:57 PM PDT 24
Finished Jul 10 05:03:48 PM PDT 24
Peak memory 218660 kb
Host smart-b3e11441-b636-4814-a63c-94d04e5cd659
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888198987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.3888198987
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1222861691
Short name T317
Test name
Test status
Simulation time 499158885 ps
CPU time 4.9 seconds
Started Jul 10 05:03:00 PM PDT 24
Finished Jul 10 05:03:07 PM PDT 24
Peak memory 217592 kb
Host smart-5f8c9659-b473-4b65-bf38-ed2f2b210208
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222861691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.1222861691
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.625365620
Short name T79
Test name
Test status
Simulation time 266817286 ps
CPU time 5.15 seconds
Started Jul 10 05:02:56 PM PDT 24
Finished Jul 10 05:03:05 PM PDT 24
Peak memory 217004 kb
Host smart-29edf9a6-7d06-4e4d-8bf4-0185634f9cf1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625365620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke.
625365620
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.642176131
Short name T283
Test name
Test status
Simulation time 1447348753 ps
CPU time 57.46 seconds
Started Jul 10 05:02:57 PM PDT 24
Finished Jul 10 05:03:58 PM PDT 24
Peak memory 276836 kb
Host smart-87c6d4db-fe63-4866-ab00-7d066d5c082b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642176131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_state_failure.642176131
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.1564150954
Short name T449
Test name
Test status
Simulation time 2061031001 ps
CPU time 21.69 seconds
Started Jul 10 05:02:56 PM PDT 24
Finished Jul 10 05:03:21 PM PDT 24
Peak memory 250260 kb
Host smart-d18b9635-c167-439a-af51-a1637c334a5a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564150954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.1564150954
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.113471678
Short name T774
Test name
Test status
Simulation time 57839034 ps
CPU time 3.19 seconds
Started Jul 10 05:02:59 PM PDT 24
Finished Jul 10 05:03:05 PM PDT 24
Peak memory 217616 kb
Host smart-ac9ccca7-0519-420e-9822-810e57332f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113471678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.113471678
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.4012414817
Short name T312
Test name
Test status
Simulation time 1229448193 ps
CPU time 9.02 seconds
Started Jul 10 05:03:01 PM PDT 24
Finished Jul 10 05:03:12 PM PDT 24
Peak memory 225388 kb
Host smart-611b16f7-0ad2-4327-87b0-46ec1fbab66c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012414817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.4012414817
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.2215326672
Short name T821
Test name
Test status
Simulation time 280247149 ps
CPU time 10.9 seconds
Started Jul 10 05:02:57 PM PDT 24
Finished Jul 10 05:03:12 PM PDT 24
Peak memory 217612 kb
Host smart-6f110846-17b6-4aea-80c0-f91884b31006
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215326672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
2215326672
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.4023613482
Short name T387
Test name
Test status
Simulation time 396855667 ps
CPU time 9.15 seconds
Started Jul 10 05:03:01 PM PDT 24
Finished Jul 10 05:03:12 PM PDT 24
Peak memory 225112 kb
Host smart-402a2e90-d03d-455a-9fd9-669473f5fa3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023613482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.4023613482
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.895106685
Short name T499
Test name
Test status
Simulation time 21003265 ps
CPU time 1.46 seconds
Started Jul 10 05:03:00 PM PDT 24
Finished Jul 10 05:03:04 PM PDT 24
Peak memory 213176 kb
Host smart-2667e78e-7a2b-44b8-ae27-cea5280fb647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895106685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.895106685
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.3484286728
Short name T732
Test name
Test status
Simulation time 414739785 ps
CPU time 28.88 seconds
Started Jul 10 05:02:58 PM PDT 24
Finished Jul 10 05:03:30 PM PDT 24
Peak memory 245484 kb
Host smart-c8c79ce3-9478-4424-8833-a85edf866b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484286728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.3484286728
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.189144748
Short name T37
Test name
Test status
Simulation time 95091644 ps
CPU time 9.78 seconds
Started Jul 10 05:02:57 PM PDT 24
Finished Jul 10 05:03:10 PM PDT 24
Peak memory 250420 kb
Host smart-8f515bc7-2a79-47e3-b456-4bec7e33b6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189144748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.189144748
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.3478951114
Short name T376
Test name
Test status
Simulation time 46225164641 ps
CPU time 295.17 seconds
Started Jul 10 05:02:56 PM PDT 24
Finished Jul 10 05:07:55 PM PDT 24
Peak memory 512548 kb
Host smart-e4b195df-fb80-4781-b56b-291f0bce55ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478951114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.3478951114
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.2534288185
Short name T104
Test name
Test status
Simulation time 48451886 ps
CPU time 0.82 seconds
Started Jul 10 05:02:57 PM PDT 24
Finished Jul 10 05:03:02 PM PDT 24
Peak memory 208424 kb
Host smart-0cc7cc11-c0d7-44ce-a9ff-8360064eacf1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534288185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.2534288185
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.3596143036
Short name T562
Test name
Test status
Simulation time 24497816 ps
CPU time 0.93 seconds
Started Jul 10 05:03:11 PM PDT 24
Finished Jul 10 05:03:14 PM PDT 24
Peak memory 208280 kb
Host smart-d878e1ca-abb6-40f5-98a0-41bda8f599b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596143036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.3596143036
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.2010891459
Short name T448
Test name
Test status
Simulation time 320119416 ps
CPU time 9.5 seconds
Started Jul 10 05:03:11 PM PDT 24
Finished Jul 10 05:03:23 PM PDT 24
Peak memory 225352 kb
Host smart-ade81f88-bdda-404a-bf22-c810a0f5cf76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010891459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.2010891459
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.272946339
Short name T853
Test name
Test status
Simulation time 50589202 ps
CPU time 2.2 seconds
Started Jul 10 05:03:08 PM PDT 24
Finished Jul 10 05:03:12 PM PDT 24
Peak memory 217080 kb
Host smart-57ceb10a-ba23-4618-8e09-71bec14f8cde
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272946339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.272946339
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.583679662
Short name T746
Test name
Test status
Simulation time 10238643225 ps
CPU time 33.97 seconds
Started Jul 10 05:03:11 PM PDT 24
Finished Jul 10 05:03:47 PM PDT 24
Peak memory 218180 kb
Host smart-cbfb7a60-6fe5-4200-b0c2-265daec80c20
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583679662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_er
rors.583679662
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.2449047109
Short name T711
Test name
Test status
Simulation time 276962359 ps
CPU time 2.04 seconds
Started Jul 10 05:03:08 PM PDT 24
Finished Jul 10 05:03:12 PM PDT 24
Peak memory 217664 kb
Host smart-25e90718-1928-4340-890a-cdbb7f7100d9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449047109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.2449047109
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.3948326660
Short name T495
Test name
Test status
Simulation time 233039150 ps
CPU time 1.44 seconds
Started Jul 10 05:03:10 PM PDT 24
Finished Jul 10 05:03:14 PM PDT 24
Peak memory 217124 kb
Host smart-c7000259-4fe4-4da7-a35f-ae275adc7f8e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948326660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.3948326660
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.1652274241
Short name T536
Test name
Test status
Simulation time 1762132515 ps
CPU time 44.12 seconds
Started Jul 10 05:03:09 PM PDT 24
Finished Jul 10 05:03:55 PM PDT 24
Peak memory 283080 kb
Host smart-b259d887-1b59-4125-a9e4-37df4d61686d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652274241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.1652274241
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.833934482
Short name T392
Test name
Test status
Simulation time 13173301816 ps
CPU time 23.6 seconds
Started Jul 10 05:03:07 PM PDT 24
Finished Jul 10 05:03:32 PM PDT 24
Peak memory 250164 kb
Host smart-22ac1643-6f93-4481-80cf-91c8867017c7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833934482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_
jtag_state_post_trans.833934482
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.2638700085
Short name T577
Test name
Test status
Simulation time 43501584 ps
CPU time 2.34 seconds
Started Jul 10 05:03:10 PM PDT 24
Finished Jul 10 05:03:15 PM PDT 24
Peak memory 217708 kb
Host smart-97ccc197-483b-4b9e-b2c0-3b4c7fcfb011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638700085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.2638700085
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.1539217096
Short name T778
Test name
Test status
Simulation time 675792974 ps
CPU time 10.74 seconds
Started Jul 10 05:03:09 PM PDT 24
Finished Jul 10 05:03:22 PM PDT 24
Peak memory 225508 kb
Host smart-80fde38d-71b0-4a87-b338-a00ca7ff151d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539217096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.1539217096
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.1561290147
Short name T619
Test name
Test status
Simulation time 163706837 ps
CPU time 7.48 seconds
Started Jul 10 05:03:08 PM PDT 24
Finished Jul 10 05:03:17 PM PDT 24
Peak memory 217656 kb
Host smart-6f896ffe-7837-45ec-9a36-f8f7926cb525
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561290147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.1561290147
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.1545868445
Short name T754
Test name
Test status
Simulation time 278249251 ps
CPU time 8.85 seconds
Started Jul 10 05:03:09 PM PDT 24
Finished Jul 10 05:03:19 PM PDT 24
Peak memory 217644 kb
Host smart-74b0c919-be7a-4a66-a1e3-6722ecbcb178
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545868445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
1545868445
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.1185230017
Short name T797
Test name
Test status
Simulation time 22887558 ps
CPU time 1.19 seconds
Started Jul 10 05:03:07 PM PDT 24
Finished Jul 10 05:03:10 PM PDT 24
Peak memory 217096 kb
Host smart-4cd1e6d9-2193-4f09-9cd8-aea77908cb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185230017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.1185230017
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.3540657141
Short name T780
Test name
Test status
Simulation time 312296942 ps
CPU time 35.1 seconds
Started Jul 10 05:03:11 PM PDT 24
Finished Jul 10 05:03:48 PM PDT 24
Peak memory 250396 kb
Host smart-5180c390-cf76-4f37-aad1-03e31b257289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540657141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.3540657141
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.3309804468
Short name T264
Test name
Test status
Simulation time 70522224 ps
CPU time 6.29 seconds
Started Jul 10 05:03:09 PM PDT 24
Finished Jul 10 05:03:17 PM PDT 24
Peak memory 250404 kb
Host smart-68a14b01-57c8-4e38-8d1b-ebb43530f2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309804468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.3309804468
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.444842920
Short name T411
Test name
Test status
Simulation time 30558048611 ps
CPU time 233.68 seconds
Started Jul 10 05:03:10 PM PDT 24
Finished Jul 10 05:07:06 PM PDT 24
Peak memory 270868 kb
Host smart-13bb5324-6eed-4b93-a88d-ae81d29c7a94
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444842920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.444842920
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.1756145203
Short name T519
Test name
Test status
Simulation time 13524889 ps
CPU time 1.09 seconds
Started Jul 10 05:03:12 PM PDT 24
Finished Jul 10 05:03:15 PM PDT 24
Peak memory 208408 kb
Host smart-3c928025-f5d5-450d-acfb-605e8c2164d6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756145203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.1756145203
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.2855101205
Short name T222
Test name
Test status
Simulation time 15388484 ps
CPU time 0.89 seconds
Started Jul 10 05:03:20 PM PDT 24
Finished Jul 10 05:03:22 PM PDT 24
Peak memory 208432 kb
Host smart-0b2eed8e-273c-4dfa-b856-be35e6da1d12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855101205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.2855101205
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.2674740250
Short name T723
Test name
Test status
Simulation time 410246864 ps
CPU time 17.64 seconds
Started Jul 10 05:03:10 PM PDT 24
Finished Jul 10 05:03:30 PM PDT 24
Peak memory 217704 kb
Host smart-4c212fbe-5239-416c-88c6-f85cb7bededb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674740250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.2674740250
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.1294809856
Short name T8
Test name
Test status
Simulation time 1886410617 ps
CPU time 8.83 seconds
Started Jul 10 05:03:20 PM PDT 24
Finished Jul 10 05:03:31 PM PDT 24
Peak memory 217112 kb
Host smart-5e3eeec2-9b24-4e6b-8817-df547c3c6a21
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294809856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.1294809856
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.269074842
Short name T582
Test name
Test status
Simulation time 7941640292 ps
CPU time 57.84 seconds
Started Jul 10 05:03:20 PM PDT 24
Finished Jul 10 05:04:20 PM PDT 24
Peak memory 217584 kb
Host smart-3b3f9c92-ac3d-47c5-a00d-9f373882c74b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269074842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_er
rors.269074842
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.188534936
Short name T176
Test name
Test status
Simulation time 3251560526 ps
CPU time 20.77 seconds
Started Jul 10 05:03:16 PM PDT 24
Finished Jul 10 05:03:39 PM PDT 24
Peak memory 217668 kb
Host smart-8c02763d-418c-4e8a-88ad-27deb37a3f4f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188534936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag
_prog_failure.188534936
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.2373410972
Short name T530
Test name
Test status
Simulation time 178612987 ps
CPU time 3.58 seconds
Started Jul 10 05:03:18 PM PDT 24
Finished Jul 10 05:03:22 PM PDT 24
Peak memory 217060 kb
Host smart-52f4adcf-3f14-4272-bbb9-90319a24c2d6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373410972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.2373410972
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.1039721902
Short name T771
Test name
Test status
Simulation time 2912825597 ps
CPU time 39.96 seconds
Started Jul 10 05:03:21 PM PDT 24
Finished Jul 10 05:04:03 PM PDT 24
Peak memory 250408 kb
Host smart-82320048-64b8-4b24-8274-2115868ccedb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039721902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.1039721902
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.1419989977
Short name T287
Test name
Test status
Simulation time 679123398 ps
CPU time 10.96 seconds
Started Jul 10 05:03:21 PM PDT 24
Finished Jul 10 05:03:34 PM PDT 24
Peak memory 224152 kb
Host smart-511952db-ab74-4832-8d89-d8169ae4d589
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419989977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.1419989977
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.3210044603
Short name T591
Test name
Test status
Simulation time 279312688 ps
CPU time 2.67 seconds
Started Jul 10 05:03:09 PM PDT 24
Finished Jul 10 05:03:14 PM PDT 24
Peak memory 217708 kb
Host smart-d9ab40e3-0e1c-4a5b-ae88-b5d0f2ff3699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210044603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.3210044603
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.1796627111
Short name T497
Test name
Test status
Simulation time 919635654 ps
CPU time 13.86 seconds
Started Jul 10 05:03:16 PM PDT 24
Finished Jul 10 05:03:31 PM PDT 24
Peak memory 217736 kb
Host smart-eb68080a-410d-4a1d-92ce-a600ee548cae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796627111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.1796627111
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.470203155
Short name T800
Test name
Test status
Simulation time 2926850053 ps
CPU time 17.13 seconds
Started Jul 10 05:03:17 PM PDT 24
Finished Jul 10 05:03:35 PM PDT 24
Peak memory 225464 kb
Host smart-eff039d5-3b25-4f26-beb2-5686a7fe6964
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470203155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_di
gest.470203155
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.911258240
Short name T594
Test name
Test status
Simulation time 312580954 ps
CPU time 10.55 seconds
Started Jul 10 05:03:18 PM PDT 24
Finished Jul 10 05:03:29 PM PDT 24
Peak memory 217656 kb
Host smart-d477d0e7-d2c6-469f-ba76-13240cbf5031
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911258240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.911258240
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.2917256557
Short name T326
Test name
Test status
Simulation time 361770745 ps
CPU time 13.43 seconds
Started Jul 10 05:03:20 PM PDT 24
Finished Jul 10 05:03:35 PM PDT 24
Peak memory 217772 kb
Host smart-c134966e-3738-4231-ad85-5b8e6ff98693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917256557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.2917256557
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.845736491
Short name T483
Test name
Test status
Simulation time 162639796 ps
CPU time 2.83 seconds
Started Jul 10 05:03:10 PM PDT 24
Finished Jul 10 05:03:15 PM PDT 24
Peak memory 217104 kb
Host smart-d559c63f-1191-4d21-bfc4-154b6f6bca45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845736491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.845736491
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.816515994
Short name T407
Test name
Test status
Simulation time 1103525685 ps
CPU time 23.64 seconds
Started Jul 10 05:03:10 PM PDT 24
Finished Jul 10 05:03:36 PM PDT 24
Peak memory 250416 kb
Host smart-143eef25-dc23-4bfe-9df5-c40d69775b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816515994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.816515994
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.1043249127
Short name T568
Test name
Test status
Simulation time 134806492 ps
CPU time 3.8 seconds
Started Jul 10 05:03:08 PM PDT 24
Finished Jul 10 05:03:13 PM PDT 24
Peak memory 225892 kb
Host smart-8ff5fdfd-ce37-4c60-9933-f205d32fe402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043249127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.1043249127
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.2648720834
Short name T672
Test name
Test status
Simulation time 32030460893 ps
CPU time 124.67 seconds
Started Jul 10 05:03:21 PM PDT 24
Finished Jul 10 05:05:28 PM PDT 24
Peak memory 258808 kb
Host smart-489911ee-514c-49f0-a0bc-29fd43a9965f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648720834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.2648720834
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.1095316266
Short name T683
Test name
Test status
Simulation time 163497173724 ps
CPU time 599.93 seconds
Started Jul 10 05:03:20 PM PDT 24
Finished Jul 10 05:13:21 PM PDT 24
Peak memory 310688 kb
Host smart-650c62e0-2483-41f6-af47-32f3df794aa7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1095316266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.1095316266
Directory /workspace/18.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.827586209
Short name T40
Test name
Test status
Simulation time 66474399 ps
CPU time 0.91 seconds
Started Jul 10 05:03:08 PM PDT 24
Finished Jul 10 05:03:10 PM PDT 24
Peak memory 211328 kb
Host smart-f7dda306-f6b5-451c-84c0-d901efcf50e9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827586209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ct
rl_volatile_unlock_smoke.827586209
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.258513113
Short name T851
Test name
Test status
Simulation time 35704419 ps
CPU time 0.93 seconds
Started Jul 10 05:03:19 PM PDT 24
Finished Jul 10 05:03:21 PM PDT 24
Peak memory 208404 kb
Host smart-32da715e-0446-49c0-82a9-62b19d178481
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258513113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.258513113
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.3628094133
Short name T333
Test name
Test status
Simulation time 1421683903 ps
CPU time 14.56 seconds
Started Jul 10 05:03:20 PM PDT 24
Finished Jul 10 05:03:36 PM PDT 24
Peak memory 225460 kb
Host smart-28ac5c80-0f6f-4570-9afb-f0ecc70ee451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628094133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.3628094133
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.901210537
Short name T405
Test name
Test status
Simulation time 732996052 ps
CPU time 3.9 seconds
Started Jul 10 05:03:19 PM PDT 24
Finished Jul 10 05:03:23 PM PDT 24
Peak memory 217032 kb
Host smart-5a497bb8-97f8-494b-8a5d-2e4ecafb0e62
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901210537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.901210537
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.3054094700
Short name T667
Test name
Test status
Simulation time 3098907809 ps
CPU time 50.33 seconds
Started Jul 10 05:03:18 PM PDT 24
Finished Jul 10 05:04:09 PM PDT 24
Peak memory 217680 kb
Host smart-212d5bfd-6a58-4284-adf6-4773d620e5b1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054094700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.3054094700
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.93531009
Short name T749
Test name
Test status
Simulation time 641657796 ps
CPU time 10.2 seconds
Started Jul 10 05:03:20 PM PDT 24
Finished Jul 10 05:03:32 PM PDT 24
Peak memory 217596 kb
Host smart-3a4806ca-607f-4790-a452-589916e873a2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93531009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p
rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_
prog_failure.93531009
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.3670581779
Short name T22
Test name
Test status
Simulation time 151432308 ps
CPU time 2.97 seconds
Started Jul 10 05:03:19 PM PDT 24
Finished Jul 10 05:03:23 PM PDT 24
Peak memory 217020 kb
Host smart-2478acfb-4321-41fb-ae5f-3337d53358a6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670581779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.3670581779
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.1896314500
Short name T731
Test name
Test status
Simulation time 8758319015 ps
CPU time 49.94 seconds
Started Jul 10 05:03:18 PM PDT 24
Finished Jul 10 05:04:09 PM PDT 24
Peak memory 283208 kb
Host smart-1ea74394-cf97-42f9-83b0-7907ffc49fed
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896314500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.1896314500
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.940807393
Short name T761
Test name
Test status
Simulation time 929178190 ps
CPU time 9.06 seconds
Started Jul 10 05:03:24 PM PDT 24
Finished Jul 10 05:03:35 PM PDT 24
Peak memory 223468 kb
Host smart-31fa818f-4c97-4906-b5a5-db54f9d08387
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940807393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_
jtag_state_post_trans.940807393
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.3406073811
Short name T518
Test name
Test status
Simulation time 151202255 ps
CPU time 3.81 seconds
Started Jul 10 05:03:23 PM PDT 24
Finished Jul 10 05:03:28 PM PDT 24
Peak memory 221724 kb
Host smart-af2e9e1f-55e3-46c2-9e35-72c4d7349995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406073811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.3406073811
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.4195700408
Short name T269
Test name
Test status
Simulation time 543585727 ps
CPU time 17.2 seconds
Started Jul 10 05:03:20 PM PDT 24
Finished Jul 10 05:03:40 PM PDT 24
Peak memory 218376 kb
Host smart-bff50d39-bc7e-4cda-8050-bfbe0fcf80ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195700408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.4195700408
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.3326830974
Short name T4
Test name
Test status
Simulation time 1705158842 ps
CPU time 21.08 seconds
Started Jul 10 05:03:23 PM PDT 24
Finished Jul 10 05:03:46 PM PDT 24
Peak memory 225392 kb
Host smart-b73d3ac6-35e6-42a8-9654-c78a7721339f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326830974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.3326830974
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.4119370946
Short name T469
Test name
Test status
Simulation time 1538544584 ps
CPU time 9.29 seconds
Started Jul 10 05:03:17 PM PDT 24
Finished Jul 10 05:03:28 PM PDT 24
Peak memory 217608 kb
Host smart-5fd52e0b-ab0a-456d-8263-1121e1b40869
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119370946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
4119370946
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.3225591911
Short name T822
Test name
Test status
Simulation time 235640640 ps
CPU time 9.25 seconds
Started Jul 10 05:03:24 PM PDT 24
Finished Jul 10 05:03:35 PM PDT 24
Peak memory 225436 kb
Host smart-ee0d1337-a42e-4df6-b4a8-c8e6b8dc2a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225591911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.3225591911
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.708390972
Short name T179
Test name
Test status
Simulation time 87948537 ps
CPU time 1.98 seconds
Started Jul 10 05:03:20 PM PDT 24
Finished Jul 10 05:03:24 PM PDT 24
Peak memory 217124 kb
Host smart-f9b2c43a-5620-4ada-9d3c-f4da3f1b4d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708390972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.708390972
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.2404130444
Short name T813
Test name
Test status
Simulation time 3591332630 ps
CPU time 20.79 seconds
Started Jul 10 05:03:24 PM PDT 24
Finished Jul 10 05:03:46 PM PDT 24
Peak memory 250464 kb
Host smart-d193c607-b9f8-4469-ac44-347b0e2f60a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404130444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.2404130444
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.819836240
Short name T801
Test name
Test status
Simulation time 564286440 ps
CPU time 7.12 seconds
Started Jul 10 05:03:19 PM PDT 24
Finished Jul 10 05:03:27 PM PDT 24
Peak memory 250360 kb
Host smart-9dbff290-89e4-44e9-a175-b63134efbc73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819836240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.819836240
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.3552338488
Short name T837
Test name
Test status
Simulation time 11167850362 ps
CPU time 121.2 seconds
Started Jul 10 05:03:19 PM PDT 24
Finished Jul 10 05:05:21 PM PDT 24
Peak memory 270504 kb
Host smart-e89d8862-3973-4404-b217-37bc7e88c031
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552338488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.3552338488
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.469864724
Short name T601
Test name
Test status
Simulation time 26871300 ps
CPU time 0.94 seconds
Started Jul 10 05:03:19 PM PDT 24
Finished Jul 10 05:03:21 PM PDT 24
Peak memory 217268 kb
Host smart-ae46e6e7-e383-41c7-8ef8-7f39033c53f2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469864724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ct
rl_volatile_unlock_smoke.469864724
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.2353253072
Short name T635
Test name
Test status
Simulation time 59538690 ps
CPU time 1.11 seconds
Started Jul 10 05:01:28 PM PDT 24
Finished Jul 10 05:01:31 PM PDT 24
Peak memory 208376 kb
Host smart-6a4518fa-df64-4c41-8102-4b8df815035b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353253072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.2353253072
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.824792227
Short name T734
Test name
Test status
Simulation time 27071736 ps
CPU time 0.78 seconds
Started Jul 10 05:01:21 PM PDT 24
Finished Jul 10 05:01:23 PM PDT 24
Peak memory 208388 kb
Host smart-2250957c-f868-4e16-9bef-78c2eddd51be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824792227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.824792227
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.160947280
Short name T846
Test name
Test status
Simulation time 4710903734 ps
CPU time 14.97 seconds
Started Jul 10 05:01:17 PM PDT 24
Finished Jul 10 05:01:33 PM PDT 24
Peak memory 218440 kb
Host smart-76b9e914-d8ce-4c16-ad3e-e7e4b983c91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160947280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.160947280
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.1191929753
Short name T677
Test name
Test status
Simulation time 131652416 ps
CPU time 2.48 seconds
Started Jul 10 05:01:21 PM PDT 24
Finished Jul 10 05:01:25 PM PDT 24
Peak memory 217068 kb
Host smart-0336c3af-2034-4189-81ed-c6fc1ea8b7ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191929753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.1191929753
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.2339006987
Short name T553
Test name
Test status
Simulation time 10305462571 ps
CPU time 46.52 seconds
Started Jul 10 05:01:20 PM PDT 24
Finished Jul 10 05:02:07 PM PDT 24
Peak memory 218296 kb
Host smart-bf79fbe1-8b87-4ecc-80df-090a04ff1f4d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339006987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.2339006987
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.3514655255
Short name T420
Test name
Test status
Simulation time 7211185376 ps
CPU time 4.29 seconds
Started Jul 10 05:01:21 PM PDT 24
Finished Jul 10 05:01:27 PM PDT 24
Peak memory 217232 kb
Host smart-454e66c2-92cc-4fe4-a8fb-9227520bbd4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514655255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.3
514655255
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.3116112348
Short name T221
Test name
Test status
Simulation time 54263471 ps
CPU time 1.96 seconds
Started Jul 10 05:01:22 PM PDT 24
Finished Jul 10 05:01:25 PM PDT 24
Peak memory 217564 kb
Host smart-b2455d60-17d3-43f9-b231-e3c17187aefe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116112348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.3116112348
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.1416866327
Short name T223
Test name
Test status
Simulation time 1423977941 ps
CPU time 18.81 seconds
Started Jul 10 05:01:27 PM PDT 24
Finished Jul 10 05:01:47 PM PDT 24
Peak memory 217008 kb
Host smart-88210ae4-cb91-4892-8a7f-94b0bc54df4d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416866327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.1416866327
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.2066726687
Short name T675
Test name
Test status
Simulation time 185256377 ps
CPU time 5.79 seconds
Started Jul 10 05:01:20 PM PDT 24
Finished Jul 10 05:01:27 PM PDT 24
Peak memory 217080 kb
Host smart-e674400c-e475-475f-bf1b-a37c57d301d6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066726687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
2066726687
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.2291697740
Short name T445
Test name
Test status
Simulation time 2379104243 ps
CPU time 45.4 seconds
Started Jul 10 05:01:21 PM PDT 24
Finished Jul 10 05:02:08 PM PDT 24
Peak memory 278304 kb
Host smart-f4fff047-8343-4c4f-b110-92d51daa9c74
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291697740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.2291697740
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.2842732861
Short name T742
Test name
Test status
Simulation time 5137834341 ps
CPU time 20.7 seconds
Started Jul 10 05:01:22 PM PDT 24
Finished Jul 10 05:01:44 PM PDT 24
Peak memory 250292 kb
Host smart-9f9181d2-da29-440c-83a7-1ad3cf0d4c50
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842732861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.2842732861
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.3002925908
Short name T792
Test name
Test status
Simulation time 47204831 ps
CPU time 2.53 seconds
Started Jul 10 05:01:16 PM PDT 24
Finished Jul 10 05:01:20 PM PDT 24
Peak memory 217640 kb
Host smart-438f1ca0-f201-4110-8368-7cef210a421c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002925908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.3002925908
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.3492199437
Short name T441
Test name
Test status
Simulation time 1878349577 ps
CPU time 13.72 seconds
Started Jul 10 05:01:15 PM PDT 24
Finished Jul 10 05:01:30 PM PDT 24
Peak memory 214096 kb
Host smart-29dc25c0-01f2-40ec-aa69-c313d9720ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492199437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.3492199437
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.3763177787
Short name T59
Test name
Test status
Simulation time 231966707 ps
CPU time 38.78 seconds
Started Jul 10 05:01:35 PM PDT 24
Finished Jul 10 05:02:16 PM PDT 24
Peak memory 269504 kb
Host smart-839fcb25-85ff-4b33-b080-f3f86fb80780
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763177787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.3763177787
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.3968238040
Short name T408
Test name
Test status
Simulation time 440659483 ps
CPU time 18.46 seconds
Started Jul 10 05:01:28 PM PDT 24
Finished Jul 10 05:01:48 PM PDT 24
Peak memory 217916 kb
Host smart-e125d0ce-b86e-4567-a1ca-961702fdec40
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968238040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.3968238040
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.1664057412
Short name T258
Test name
Test status
Simulation time 367727966 ps
CPU time 11.77 seconds
Started Jul 10 05:01:28 PM PDT 24
Finished Jul 10 05:01:41 PM PDT 24
Peak memory 225404 kb
Host smart-2152869f-49f7-48de-a0db-ef1ebf918390
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664057412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.1664057412
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.2099451785
Short name T440
Test name
Test status
Simulation time 999182117 ps
CPU time 11.38 seconds
Started Jul 10 05:01:28 PM PDT 24
Finished Jul 10 05:01:41 PM PDT 24
Peak memory 225388 kb
Host smart-3e1236ee-4db5-43db-8f66-bf4a866049e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099451785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.2
099451785
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.2225337643
Short name T443
Test name
Test status
Simulation time 242959725 ps
CPU time 10.44 seconds
Started Jul 10 05:01:17 PM PDT 24
Finished Jul 10 05:01:29 PM PDT 24
Peak memory 217728 kb
Host smart-57b6da8d-2260-4378-87e2-507dc6e83d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225337643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.2225337643
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.4139773371
Short name T569
Test name
Test status
Simulation time 40909289 ps
CPU time 3.33 seconds
Started Jul 10 05:01:17 PM PDT 24
Finished Jul 10 05:01:22 PM PDT 24
Peak memory 223620 kb
Host smart-ad19a576-f87d-4aff-b7c3-d231def51840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139773371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.4139773371
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.1719795323
Short name T272
Test name
Test status
Simulation time 372667689 ps
CPU time 21.53 seconds
Started Jul 10 05:01:16 PM PDT 24
Finished Jul 10 05:01:39 PM PDT 24
Peak memory 250404 kb
Host smart-a2083e5f-30a4-467f-8f2e-c1342c423daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719795323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.1719795323
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.3053358028
Short name T436
Test name
Test status
Simulation time 430225328 ps
CPU time 3.49 seconds
Started Jul 10 05:01:16 PM PDT 24
Finished Jul 10 05:01:21 PM PDT 24
Peak memory 222160 kb
Host smart-8a081724-259d-4542-a14d-73b35ba5f75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053358028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.3053358028
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.1398649732
Short name T466
Test name
Test status
Simulation time 4589996227 ps
CPU time 49.61 seconds
Started Jul 10 05:01:28 PM PDT 24
Finished Jul 10 05:02:19 PM PDT 24
Peak memory 250560 kb
Host smart-7d6feb06-f31b-4274-83ed-9719d22524dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398649732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.1398649732
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.160398000
Short name T165
Test name
Test status
Simulation time 167578266705 ps
CPU time 993.52 seconds
Started Jul 10 05:01:28 PM PDT 24
Finished Jul 10 05:18:04 PM PDT 24
Peak memory 437988 kb
Host smart-0523630c-a1fc-4978-bb76-1bd2a9400f0f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=160398000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.160398000
Directory /workspace/2.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.1263470622
Short name T708
Test name
Test status
Simulation time 10503503 ps
CPU time 0.73 seconds
Started Jul 10 05:01:14 PM PDT 24
Finished Jul 10 05:01:16 PM PDT 24
Peak memory 206512 kb
Host smart-9e5ae622-11d8-4225-9c39-26714befee31
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263470622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.1263470622
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.4237615454
Short name T471
Test name
Test status
Simulation time 25922946 ps
CPU time 0.88 seconds
Started Jul 10 05:03:30 PM PDT 24
Finished Jul 10 05:03:34 PM PDT 24
Peak memory 208328 kb
Host smart-7e2c0657-2775-4bae-8a62-e271566e01c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237615454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.4237615454
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.2798339093
Short name T721
Test name
Test status
Simulation time 1328905917 ps
CPU time 14.97 seconds
Started Jul 10 05:03:23 PM PDT 24
Finished Jul 10 05:03:40 PM PDT 24
Peak memory 217648 kb
Host smart-a9ae169e-8d96-428d-a76f-387d1ce457d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798339093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.2798339093
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.1532016054
Short name T32
Test name
Test status
Simulation time 482311071 ps
CPU time 3.99 seconds
Started Jul 10 05:03:19 PM PDT 24
Finished Jul 10 05:03:24 PM PDT 24
Peak memory 217152 kb
Host smart-ff591f51-a6b5-49f6-b65c-6761687e3d76
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532016054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.1532016054
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.186167227
Short name T670
Test name
Test status
Simulation time 70624415 ps
CPU time 3.65 seconds
Started Jul 10 05:03:21 PM PDT 24
Finished Jul 10 05:03:26 PM PDT 24
Peak memory 221896 kb
Host smart-d2570517-75a1-421c-b7c8-0e8f5a019b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186167227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.186167227
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.559355289
Short name T185
Test name
Test status
Simulation time 217871746 ps
CPU time 8.2 seconds
Started Jul 10 05:03:31 PM PDT 24
Finished Jul 10 05:03:41 PM PDT 24
Peak memory 225440 kb
Host smart-87917a4c-a899-48db-aad9-448b70dc1e79
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559355289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_di
gest.559355289
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.927111261
Short name T745
Test name
Test status
Simulation time 615048911 ps
CPU time 12.07 seconds
Started Jul 10 05:03:25 PM PDT 24
Finished Jul 10 05:03:38 PM PDT 24
Peak memory 225372 kb
Host smart-9c8cd8ac-ecde-45bf-8e10-1a9bee7b426b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927111261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.927111261
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.711965073
Short name T57
Test name
Test status
Simulation time 347838626 ps
CPU time 8.86 seconds
Started Jul 10 05:03:17 PM PDT 24
Finished Jul 10 05:03:27 PM PDT 24
Peak memory 225528 kb
Host smart-7f76da0a-5511-42ef-a7d6-de615691c80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711965073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.711965073
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.936383024
Short name T358
Test name
Test status
Simulation time 85626655 ps
CPU time 3.26 seconds
Started Jul 10 05:03:22 PM PDT 24
Finished Jul 10 05:03:27 PM PDT 24
Peak memory 223712 kb
Host smart-55753576-5e6b-4468-9798-6a1629446767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936383024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.936383024
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.2006110480
Short name T475
Test name
Test status
Simulation time 332191646 ps
CPU time 7.03 seconds
Started Jul 10 05:03:19 PM PDT 24
Finished Jul 10 05:03:28 PM PDT 24
Peak memory 250452 kb
Host smart-12982037-1d75-4bc5-9727-aec274a1fff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006110480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.2006110480
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.1863165401
Short name T355
Test name
Test status
Simulation time 15965684894 ps
CPU time 500.51 seconds
Started Jul 10 05:03:30 PM PDT 24
Finished Jul 10 05:11:53 PM PDT 24
Peak memory 225564 kb
Host smart-b91cf667-5986-47d2-ad3e-3e8ef9d361f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863165401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.1863165401
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.641847385
Short name T101
Test name
Test status
Simulation time 38492945 ps
CPU time 0.98 seconds
Started Jul 10 05:03:20 PM PDT 24
Finished Jul 10 05:03:23 PM PDT 24
Peak memory 211060 kb
Host smart-d93b2690-ff51-4853-91cf-74e5603f48dd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641847385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ct
rl_volatile_unlock_smoke.641847385
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.2824261706
Short name T35
Test name
Test status
Simulation time 73674395 ps
CPU time 1.04 seconds
Started Jul 10 05:03:31 PM PDT 24
Finished Jul 10 05:03:34 PM PDT 24
Peak memory 208440 kb
Host smart-19defd19-7452-42e6-b729-a9b25bcdf194
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824261706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.2824261706
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.62077084
Short name T513
Test name
Test status
Simulation time 1209293044 ps
CPU time 14.32 seconds
Started Jul 10 05:03:31 PM PDT 24
Finished Jul 10 05:03:47 PM PDT 24
Peak memory 217960 kb
Host smart-ac77c7fc-0923-4493-93d1-3c151103b284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62077084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.62077084
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.3233915198
Short name T197
Test name
Test status
Simulation time 94559328 ps
CPU time 1.85 seconds
Started Jul 10 05:03:29 PM PDT 24
Finished Jul 10 05:03:33 PM PDT 24
Peak memory 217068 kb
Host smart-cd3b019a-e867-4bb8-b2cf-3a9d2b5470f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233915198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.3233915198
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.2533049219
Short name T539
Test name
Test status
Simulation time 64332290 ps
CPU time 2.68 seconds
Started Jul 10 05:03:27 PM PDT 24
Finished Jul 10 05:03:32 PM PDT 24
Peak memory 217656 kb
Host smart-400f0f7a-f326-4055-8638-ba195e674d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533049219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.2533049219
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.2431547766
Short name T248
Test name
Test status
Simulation time 456170144 ps
CPU time 11.27 seconds
Started Jul 10 05:03:29 PM PDT 24
Finished Jul 10 05:03:43 PM PDT 24
Peak memory 225396 kb
Host smart-204d48ae-3430-4b45-94e5-89f467f34681
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431547766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.2431547766
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.3575533945
Short name T304
Test name
Test status
Simulation time 707164649 ps
CPU time 9.79 seconds
Started Jul 10 05:03:29 PM PDT 24
Finished Jul 10 05:03:42 PM PDT 24
Peak memory 217608 kb
Host smart-cfeb706f-3cd5-4a5f-a67c-6603ab0d9cfc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575533945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
3575533945
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.437859496
Short name T442
Test name
Test status
Simulation time 451592713 ps
CPU time 9.49 seconds
Started Jul 10 05:03:36 PM PDT 24
Finished Jul 10 05:03:46 PM PDT 24
Peak memory 217712 kb
Host smart-7929db41-c89b-4a75-9af2-67a23fc3e706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437859496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.437859496
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.914992510
Short name T625
Test name
Test status
Simulation time 21044321 ps
CPU time 1.43 seconds
Started Jul 10 05:03:29 PM PDT 24
Finished Jul 10 05:03:34 PM PDT 24
Peak memory 217344 kb
Host smart-6a588945-9c44-4c17-92a4-cb750c11e975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914992510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.914992510
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.3574382053
Short name T785
Test name
Test status
Simulation time 219738358 ps
CPU time 20.74 seconds
Started Jul 10 05:03:30 PM PDT 24
Finished Jul 10 05:03:53 PM PDT 24
Peak memory 250412 kb
Host smart-ab2b5da5-13c2-4c74-b841-216fa559c35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574382053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.3574382053
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.3947664450
Short name T829
Test name
Test status
Simulation time 242998950 ps
CPU time 6.65 seconds
Started Jul 10 05:03:29 PM PDT 24
Finished Jul 10 05:03:38 PM PDT 24
Peak memory 246540 kb
Host smart-2761851e-b450-4dda-8539-a7f6c83db70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947664450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.3947664450
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.4269139515
Short name T67
Test name
Test status
Simulation time 20580865015 ps
CPU time 321.72 seconds
Started Jul 10 05:03:28 PM PDT 24
Finished Jul 10 05:08:52 PM PDT 24
Peak memory 282840 kb
Host smart-da57975b-f55b-4506-8ee6-36727ff7832f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269139515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.4269139515
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.2457755012
Short name T781
Test name
Test status
Simulation time 126039666 ps
CPU time 0.83 seconds
Started Jul 10 05:03:28 PM PDT 24
Finished Jul 10 05:03:31 PM PDT 24
Peak memory 208476 kb
Host smart-2d756369-77d4-4263-95ac-3c7b121b5d87
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457755012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.2457755012
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.2503497425
Short name T36
Test name
Test status
Simulation time 1601341522 ps
CPU time 9.94 seconds
Started Jul 10 05:03:31 PM PDT 24
Finished Jul 10 05:03:43 PM PDT 24
Peak memory 225584 kb
Host smart-cbe1d40a-a20d-4888-bf9a-2c1bec705616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503497425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.2503497425
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.1809092190
Short name T546
Test name
Test status
Simulation time 282464815 ps
CPU time 3.54 seconds
Started Jul 10 05:03:29 PM PDT 24
Finished Jul 10 05:03:35 PM PDT 24
Peak memory 222088 kb
Host smart-60391078-513f-4af4-90ec-7d90d4b59b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809092190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.1809092190
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.3343883932
Short name T718
Test name
Test status
Simulation time 333936193 ps
CPU time 10.73 seconds
Started Jul 10 05:03:30 PM PDT 24
Finished Jul 10 05:03:43 PM PDT 24
Peak memory 225392 kb
Host smart-40993dc7-9bda-4234-9d57-20af3a822328
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343883932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.3343883932
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.3372877184
Short name T583
Test name
Test status
Simulation time 3519736974 ps
CPU time 6.6 seconds
Started Jul 10 05:03:29 PM PDT 24
Finished Jul 10 05:03:38 PM PDT 24
Peak memory 225508 kb
Host smart-9508fc3e-39b7-4959-92d4-8528d7646c22
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372877184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
3372877184
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.337864394
Short name T716
Test name
Test status
Simulation time 218828628 ps
CPU time 6.85 seconds
Started Jul 10 05:03:27 PM PDT 24
Finished Jul 10 05:03:35 PM PDT 24
Peak memory 217724 kb
Host smart-e6b70d43-1350-4062-9968-3ef1eb0cb932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337864394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.337864394
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.1861448227
Short name T335
Test name
Test status
Simulation time 40382645 ps
CPU time 1.83 seconds
Started Jul 10 05:03:30 PM PDT 24
Finished Jul 10 05:03:34 PM PDT 24
Peak memory 222712 kb
Host smart-745c7f69-b133-4310-bf64-91c88e7870cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861448227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.1861448227
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.1903605355
Short name T650
Test name
Test status
Simulation time 237549608 ps
CPU time 24.03 seconds
Started Jul 10 05:03:28 PM PDT 24
Finished Jul 10 05:03:54 PM PDT 24
Peak memory 250416 kb
Host smart-40b2637f-4886-4e71-acd3-7ee8edd370d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903605355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.1903605355
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.185494447
Short name T250
Test name
Test status
Simulation time 215292804 ps
CPU time 6.78 seconds
Started Jul 10 05:03:27 PM PDT 24
Finished Jul 10 05:03:36 PM PDT 24
Peak memory 249824 kb
Host smart-882c49d7-dbae-449f-890e-b1a0dd65f090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185494447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.185494447
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.1571335016
Short name T332
Test name
Test status
Simulation time 33419098983 ps
CPU time 98.55 seconds
Started Jul 10 05:03:29 PM PDT 24
Finished Jul 10 05:05:10 PM PDT 24
Peak memory 325992 kb
Host smart-e6d598b2-091a-430d-bb1a-56db0a15e48a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571335016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.1571335016
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.765563456
Short name T76
Test name
Test status
Simulation time 43091115 ps
CPU time 1.06 seconds
Started Jul 10 05:03:27 PM PDT 24
Finished Jul 10 05:03:31 PM PDT 24
Peak memory 211376 kb
Host smart-a7df1474-1fff-47bc-b87b-a56501eaea77
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765563456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ct
rl_volatile_unlock_smoke.765563456
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.680248479
Short name T806
Test name
Test status
Simulation time 70299226 ps
CPU time 1.21 seconds
Started Jul 10 05:03:38 PM PDT 24
Finished Jul 10 05:03:42 PM PDT 24
Peak memory 208656 kb
Host smart-0eb02e76-7274-4942-b4d4-17c7ddbc47c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680248479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.680248479
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.2588694255
Short name T504
Test name
Test status
Simulation time 611933061 ps
CPU time 15.91 seconds
Started Jul 10 05:03:39 PM PDT 24
Finished Jul 10 05:03:57 PM PDT 24
Peak memory 217664 kb
Host smart-68659c8b-3c80-4959-b285-57a3aa2b09fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588694255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.2588694255
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.2079193653
Short name T10
Test name
Test status
Simulation time 390715353 ps
CPU time 11.06 seconds
Started Jul 10 05:03:39 PM PDT 24
Finished Jul 10 05:03:53 PM PDT 24
Peak memory 216800 kb
Host smart-765d68e3-490c-4d49-aff0-fde0fd30ff3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079193653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.2079193653
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.4018097185
Short name T701
Test name
Test status
Simulation time 99816282 ps
CPU time 1.97 seconds
Started Jul 10 05:03:38 PM PDT 24
Finished Jul 10 05:03:43 PM PDT 24
Peak memory 221508 kb
Host smart-3db4f843-84ac-4001-a326-313cce42d35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018097185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.4018097185
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.757907957
Short name T49
Test name
Test status
Simulation time 245257264 ps
CPU time 11.89 seconds
Started Jul 10 05:03:40 PM PDT 24
Finished Jul 10 05:03:55 PM PDT 24
Peak memory 225464 kb
Host smart-f3432a5e-ef31-483e-bc7f-ca69c329e01c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757907957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.757907957
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.584326589
Short name T653
Test name
Test status
Simulation time 1689167656 ps
CPU time 17.45 seconds
Started Jul 10 05:03:40 PM PDT 24
Finished Jul 10 05:04:00 PM PDT 24
Peak memory 225392 kb
Host smart-e0dd6a11-0750-49db-9dff-853fa6a920be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584326589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_di
gest.584326589
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.2706995749
Short name T551
Test name
Test status
Simulation time 275594136 ps
CPU time 9.79 seconds
Started Jul 10 05:03:38 PM PDT 24
Finished Jul 10 05:03:50 PM PDT 24
Peak memory 217672 kb
Host smart-e1cfc959-0d62-4158-830a-fa100b588b17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706995749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
2706995749
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.2879976150
Short name T527
Test name
Test status
Simulation time 1132184843 ps
CPU time 8.69 seconds
Started Jul 10 05:03:39 PM PDT 24
Finished Jul 10 05:03:51 PM PDT 24
Peak memory 225452 kb
Host smart-51e6eaf5-ee33-492b-a053-6002be2d61e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879976150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.2879976150
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.1755802709
Short name T735
Test name
Test status
Simulation time 198953647 ps
CPU time 2.32 seconds
Started Jul 10 05:03:37 PM PDT 24
Finished Jul 10 05:03:42 PM PDT 24
Peak memory 217112 kb
Host smart-2f52588a-5f28-4bf0-b1dc-7f2f5e353bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755802709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.1755802709
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.1127352904
Short name T709
Test name
Test status
Simulation time 234221153 ps
CPU time 27.6 seconds
Started Jul 10 05:03:38 PM PDT 24
Finished Jul 10 05:04:09 PM PDT 24
Peak memory 250472 kb
Host smart-46440f38-26c1-4228-9eb9-1134fe7fd89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127352904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.1127352904
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.413018763
Short name T828
Test name
Test status
Simulation time 355262912 ps
CPU time 3.75 seconds
Started Jul 10 05:03:40 PM PDT 24
Finished Jul 10 05:03:46 PM PDT 24
Peak memory 221888 kb
Host smart-8d692fd6-dbba-4e10-89c1-cd74eefa324d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413018763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.413018763
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.1073076234
Short name T418
Test name
Test status
Simulation time 21239014579 ps
CPU time 121.5 seconds
Started Jul 10 05:03:42 PM PDT 24
Finished Jul 10 05:05:46 PM PDT 24
Peak memory 267576 kb
Host smart-a5bf0635-b528-4426-98cd-cbc8a05f990f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073076234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.1073076234
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3987494403
Short name T343
Test name
Test status
Simulation time 37676727 ps
CPU time 1.05 seconds
Started Jul 10 05:03:39 PM PDT 24
Finished Jul 10 05:03:43 PM PDT 24
Peak memory 211320 kb
Host smart-4879100f-4a45-4ec4-80cd-cd726ab66c9c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987494403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.3987494403
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.923294538
Short name T238
Test name
Test status
Simulation time 15779290 ps
CPU time 0.95 seconds
Started Jul 10 05:03:40 PM PDT 24
Finished Jul 10 05:03:44 PM PDT 24
Peak memory 208408 kb
Host smart-766b8d9c-5f57-4aa5-839c-f635f4e138bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923294538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.923294538
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.1840278848
Short name T621
Test name
Test status
Simulation time 1096570606 ps
CPU time 13.43 seconds
Started Jul 10 05:03:38 PM PDT 24
Finished Jul 10 05:03:54 PM PDT 24
Peak memory 217632 kb
Host smart-ca95fd99-cd81-4f17-baa6-4c09de52ec07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840278848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.1840278848
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.1601520314
Short name T521
Test name
Test status
Simulation time 3698291613 ps
CPU time 9.67 seconds
Started Jul 10 05:03:39 PM PDT 24
Finished Jul 10 05:03:51 PM PDT 24
Peak memory 217144 kb
Host smart-2acef8d1-8513-4872-8125-4d7771f59988
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601520314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.1601520314
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.108348461
Short name T494
Test name
Test status
Simulation time 64481567 ps
CPU time 3.4 seconds
Started Jul 10 05:03:40 PM PDT 24
Finished Jul 10 05:03:46 PM PDT 24
Peak memory 221712 kb
Host smart-73fa8e5b-ada8-4c1c-8165-6ce84889960a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108348461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.108348461
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.4293263821
Short name T722
Test name
Test status
Simulation time 1471966801 ps
CPU time 12.06 seconds
Started Jul 10 05:03:38 PM PDT 24
Finished Jul 10 05:03:52 PM PDT 24
Peak memory 225460 kb
Host smart-2ef1a035-7d0c-4669-9d90-64797abb9695
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293263821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.4293263821
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.3481034404
Short name T855
Test name
Test status
Simulation time 302209104 ps
CPU time 12.66 seconds
Started Jul 10 05:03:42 PM PDT 24
Finished Jul 10 05:03:57 PM PDT 24
Peak memory 225384 kb
Host smart-91d1e82f-f082-4c30-9874-c97ad25411a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481034404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.3481034404
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.375143740
Short name T290
Test name
Test status
Simulation time 2129793806 ps
CPU time 11.09 seconds
Started Jul 10 05:03:40 PM PDT 24
Finished Jul 10 05:03:54 PM PDT 24
Peak memory 217592 kb
Host smart-8a789394-d59c-4b04-8e20-12ab8019de4c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375143740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.375143740
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.1397679421
Short name T437
Test name
Test status
Simulation time 392194290 ps
CPU time 15.61 seconds
Started Jul 10 05:03:39 PM PDT 24
Finished Jul 10 05:03:57 PM PDT 24
Peak memory 225456 kb
Host smart-78df79af-19f7-4b5b-86f8-91b48e77817e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397679421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.1397679421
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.1273411048
Short name T852
Test name
Test status
Simulation time 76410941 ps
CPU time 1.65 seconds
Started Jul 10 05:03:37 PM PDT 24
Finished Jul 10 05:03:40 PM PDT 24
Peak memory 213388 kb
Host smart-d366fac1-2f74-4763-826a-57d6f8ea2fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273411048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.1273411048
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.3166243528
Short name T278
Test name
Test status
Simulation time 327477533 ps
CPU time 28.81 seconds
Started Jul 10 05:03:38 PM PDT 24
Finished Jul 10 05:04:10 PM PDT 24
Peak memory 250712 kb
Host smart-e0ccd06c-7fec-4600-af27-1d4774da9058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166243528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.3166243528
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.32709288
Short name T262
Test name
Test status
Simulation time 184394150 ps
CPU time 6.13 seconds
Started Jul 10 05:03:38 PM PDT 24
Finished Jul 10 05:03:46 PM PDT 24
Peak memory 246296 kb
Host smart-790a5324-39d6-4237-862d-f82c56127f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32709288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.32709288
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.2202227966
Short name T558
Test name
Test status
Simulation time 15100058818 ps
CPU time 246.73 seconds
Started Jul 10 05:03:41 PM PDT 24
Finished Jul 10 05:07:51 PM PDT 24
Peak memory 277812 kb
Host smart-674d2822-39c8-4650-ba7a-12d50622fd04
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202227966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.2202227966
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.250358357
Short name T105
Test name
Test status
Simulation time 46484722598 ps
CPU time 303.2 seconds
Started Jul 10 05:03:38 PM PDT 24
Finished Jul 10 05:08:44 PM PDT 24
Peak memory 283472 kb
Host smart-1624c07b-8a43-4dff-9956-60ec730a3b50
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=250358357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all_with_rand_reset.250358357
Directory /workspace/24.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.2273319694
Short name T834
Test name
Test status
Simulation time 61067838 ps
CPU time 1.05 seconds
Started Jul 10 05:03:40 PM PDT 24
Finished Jul 10 05:03:44 PM PDT 24
Peak memory 212296 kb
Host smart-67cb215e-ebe1-4f02-848c-11453004490e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273319694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.2273319694
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.893098776
Short name T78
Test name
Test status
Simulation time 18098593 ps
CPU time 1.11 seconds
Started Jul 10 05:03:52 PM PDT 24
Finished Jul 10 05:03:55 PM PDT 24
Peak memory 208396 kb
Host smart-8b466ad3-ffd7-4dec-a2af-7db577066e8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893098776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.893098776
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.145494106
Short name T760
Test name
Test status
Simulation time 1242889255 ps
CPU time 12.25 seconds
Started Jul 10 05:03:40 PM PDT 24
Finished Jul 10 05:03:55 PM PDT 24
Peak memory 217664 kb
Host smart-190e488d-adbb-4eda-b0d4-5c6e3f05312a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145494106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.145494106
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.3004076540
Short name T320
Test name
Test status
Simulation time 784061857 ps
CPU time 4.38 seconds
Started Jul 10 05:03:39 PM PDT 24
Finished Jul 10 05:03:46 PM PDT 24
Peak memory 217112 kb
Host smart-f2cb5b9f-1493-4431-832e-71f4ce128b12
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004076540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.3004076540
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.1537633470
Short name T273
Test name
Test status
Simulation time 58531090 ps
CPU time 2.47 seconds
Started Jul 10 05:03:40 PM PDT 24
Finished Jul 10 05:03:46 PM PDT 24
Peak memory 217712 kb
Host smart-00f6a0cd-5747-485d-a89d-6dceb085beb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537633470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.1537633470
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.3010212036
Short name T857
Test name
Test status
Simulation time 679427805 ps
CPU time 15.24 seconds
Started Jul 10 05:03:42 PM PDT 24
Finished Jul 10 05:04:00 PM PDT 24
Peak memory 217708 kb
Host smart-ee266339-1060-4b90-97fe-5ff953818131
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010212036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.3010212036
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.481722503
Short name T727
Test name
Test status
Simulation time 1323254830 ps
CPU time 8.57 seconds
Started Jul 10 05:03:39 PM PDT 24
Finished Jul 10 05:03:51 PM PDT 24
Peak memory 225392 kb
Host smart-7e051eb3-cc46-45cc-ad36-10c6b5be307d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481722503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_di
gest.481722503
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.2387684605
Short name T767
Test name
Test status
Simulation time 206233152 ps
CPU time 8.02 seconds
Started Jul 10 05:03:41 PM PDT 24
Finished Jul 10 05:03:52 PM PDT 24
Peak memory 224352 kb
Host smart-db5badaf-d686-45e2-8ae8-9164c36262b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387684605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
2387684605
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.466054807
Short name T631
Test name
Test status
Simulation time 514191558 ps
CPU time 13.58 seconds
Started Jul 10 05:03:41 PM PDT 24
Finished Jul 10 05:03:57 PM PDT 24
Peak memory 217780 kb
Host smart-6c2698a1-af25-4ade-8ad3-05d1d5c36ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466054807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.466054807
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.3519641054
Short name T830
Test name
Test status
Simulation time 39260267 ps
CPU time 3.08 seconds
Started Jul 10 05:03:39 PM PDT 24
Finished Jul 10 05:03:45 PM PDT 24
Peak memory 214400 kb
Host smart-082e0326-5175-4e34-988b-accaff9ebffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519641054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.3519641054
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.1424733894
Short name T444
Test name
Test status
Simulation time 1241342051 ps
CPU time 31.79 seconds
Started Jul 10 05:03:38 PM PDT 24
Finished Jul 10 05:04:13 PM PDT 24
Peak memory 250480 kb
Host smart-91d08522-307f-4db7-ac02-fe4fdff5bb6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424733894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.1424733894
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.1585684712
Short name T120
Test name
Test status
Simulation time 110472934 ps
CPU time 6.38 seconds
Started Jul 10 05:03:42 PM PDT 24
Finished Jul 10 05:03:51 PM PDT 24
Peak memory 249880 kb
Host smart-f12e7d7c-5f92-4274-8270-6f473c1c1c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585684712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.1585684712
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.962662950
Short name T725
Test name
Test status
Simulation time 11540493397 ps
CPU time 320.89 seconds
Started Jul 10 05:03:37 PM PDT 24
Finished Jul 10 05:09:00 PM PDT 24
Peak memory 258616 kb
Host smart-cde0d57f-53a1-4bfc-a580-ed325bf29178
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962662950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.962662950
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.3398765437
Short name T327
Test name
Test status
Simulation time 27216494 ps
CPU time 0.99 seconds
Started Jul 10 05:03:39 PM PDT 24
Finished Jul 10 05:03:42 PM PDT 24
Peak memory 211320 kb
Host smart-00628595-3a35-4d4f-88c5-9ac5e3cf88a9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398765437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.3398765437
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.1748318434
Short name T227
Test name
Test status
Simulation time 75960690 ps
CPU time 0.97 seconds
Started Jul 10 05:03:47 PM PDT 24
Finished Jul 10 05:03:50 PM PDT 24
Peak memory 208524 kb
Host smart-be4f23f6-bc49-40de-9f8a-a7c0183be734
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748318434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.1748318434
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.659317760
Short name T463
Test name
Test status
Simulation time 424495278 ps
CPU time 6.89 seconds
Started Jul 10 05:03:51 PM PDT 24
Finished Jul 10 05:04:00 PM PDT 24
Peak memory 217656 kb
Host smart-5a4e3364-2638-4395-b4ff-b0f0229d3958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659317760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.659317760
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.1418985103
Short name T29
Test name
Test status
Simulation time 717793149 ps
CPU time 5.12 seconds
Started Jul 10 05:03:46 PM PDT 24
Finished Jul 10 05:03:53 PM PDT 24
Peak memory 216856 kb
Host smart-989f86a0-24f0-405d-a75f-ac2b556fc818
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418985103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.1418985103
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.1039531409
Short name T321
Test name
Test status
Simulation time 652898469 ps
CPU time 2.52 seconds
Started Jul 10 05:03:52 PM PDT 24
Finished Jul 10 05:03:57 PM PDT 24
Peak memory 217660 kb
Host smart-fc4db5bd-d7b9-4798-a480-331a5febcfd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039531409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.1039531409
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.419581982
Short name T409
Test name
Test status
Simulation time 1181248210 ps
CPU time 10.23 seconds
Started Jul 10 05:03:49 PM PDT 24
Finished Jul 10 05:04:01 PM PDT 24
Peak memory 218364 kb
Host smart-7f988731-dcba-4d5f-8dd9-19d65d25d2e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419581982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.419581982
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.3294534799
Short name T816
Test name
Test status
Simulation time 1380601929 ps
CPU time 8.89 seconds
Started Jul 10 05:03:46 PM PDT 24
Finished Jul 10 05:03:57 PM PDT 24
Peak memory 225044 kb
Host smart-5606f26b-aa5e-41b9-a7e3-bc71a2605045
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294534799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.3294534799
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.2099362004
Short name T534
Test name
Test status
Simulation time 1060098329 ps
CPU time 7.4 seconds
Started Jul 10 05:03:47 PM PDT 24
Finished Jul 10 05:03:57 PM PDT 24
Peak memory 217652 kb
Host smart-5d7a83d5-abdb-40ea-b138-9ebf38897e9b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099362004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
2099362004
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.835852116
Short name T308
Test name
Test status
Simulation time 203301718 ps
CPU time 8.43 seconds
Started Jul 10 05:03:48 PM PDT 24
Finished Jul 10 05:03:59 PM PDT 24
Peak memory 224284 kb
Host smart-71a8756f-5918-4917-87d1-ee6b3d46c61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835852116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.835852116
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.2110482351
Short name T87
Test name
Test status
Simulation time 188619069 ps
CPU time 2.23 seconds
Started Jul 10 05:03:48 PM PDT 24
Finished Jul 10 05:03:52 PM PDT 24
Peak memory 222076 kb
Host smart-9b23dd36-dbcd-4401-916c-0ad485f31f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110482351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.2110482351
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.2040079679
Short name T634
Test name
Test status
Simulation time 333770588 ps
CPU time 30.39 seconds
Started Jul 10 05:03:50 PM PDT 24
Finished Jul 10 05:04:23 PM PDT 24
Peak memory 250408 kb
Host smart-c0990608-03f9-45bd-8bea-cce71d1f1329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040079679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.2040079679
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.4279940976
Short name T115
Test name
Test status
Simulation time 554389112 ps
CPU time 7.05 seconds
Started Jul 10 05:03:50 PM PDT 24
Finished Jul 10 05:03:59 PM PDT 24
Peak memory 250396 kb
Host smart-39f00897-f98a-46dc-a7ab-276ded91513c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279940976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.4279940976
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.3611857954
Short name T676
Test name
Test status
Simulation time 8938026946 ps
CPU time 86.42 seconds
Started Jul 10 05:03:46 PM PDT 24
Finished Jul 10 05:05:14 PM PDT 24
Peak memory 278012 kb
Host smart-e2d2009d-5312-4e0b-9cb4-7747ef228cf8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611857954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.3611857954
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.6128241
Short name T403
Test name
Test status
Simulation time 22330357 ps
CPU time 1 seconds
Started Jul 10 05:03:49 PM PDT 24
Finished Jul 10 05:03:52 PM PDT 24
Peak memory 211352 kb
Host smart-e74139c4-c9ed-4246-bc72-ec2d1ba3decf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6128241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vola
tile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl
_volatile_unlock_smoke.6128241
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.1586354245
Short name T647
Test name
Test status
Simulation time 260849982 ps
CPU time 0.9 seconds
Started Jul 10 05:03:48 PM PDT 24
Finished Jul 10 05:03:51 PM PDT 24
Peak memory 208376 kb
Host smart-2fde7bcc-ebe6-4d65-bb90-8288ba685bff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586354245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.1586354245
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.2186849504
Short name T276
Test name
Test status
Simulation time 1558414415 ps
CPU time 13.12 seconds
Started Jul 10 05:03:52 PM PDT 24
Finished Jul 10 05:04:07 PM PDT 24
Peak memory 217668 kb
Host smart-6577c9af-40cf-4d4c-b4e6-51a318ef312a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186849504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.2186849504
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.3392537369
Short name T9
Test name
Test status
Simulation time 1579632318 ps
CPU time 3.39 seconds
Started Jul 10 05:03:46 PM PDT 24
Finished Jul 10 05:03:51 PM PDT 24
Peak memory 216552 kb
Host smart-3005f92c-e9bd-40ed-9412-23f07dc7b3f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392537369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.3392537369
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.3812138710
Short name T618
Test name
Test status
Simulation time 220924085 ps
CPU time 3.13 seconds
Started Jul 10 05:03:49 PM PDT 24
Finished Jul 10 05:03:55 PM PDT 24
Peak memory 221792 kb
Host smart-08407699-a2ce-4d92-b1c2-12a6b312024e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812138710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.3812138710
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.498060131
Short name T410
Test name
Test status
Simulation time 269913786 ps
CPU time 11.17 seconds
Started Jul 10 05:03:48 PM PDT 24
Finished Jul 10 05:04:01 PM PDT 24
Peak memory 225460 kb
Host smart-939bfa19-abd0-4621-b83b-5067c4a0277a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498060131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.498060131
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.2068565409
Short name T357
Test name
Test status
Simulation time 241348989 ps
CPU time 9 seconds
Started Jul 10 05:03:49 PM PDT 24
Finished Jul 10 05:04:01 PM PDT 24
Peak memory 225388 kb
Host smart-33200fb5-0dd8-40fd-ae2c-a75c19e732f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068565409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.2068565409
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.4227834119
Short name T110
Test name
Test status
Simulation time 292118143 ps
CPU time 11.98 seconds
Started Jul 10 05:03:49 PM PDT 24
Finished Jul 10 05:04:03 PM PDT 24
Peak memory 217656 kb
Host smart-a9de46bb-d0ce-4881-bf76-d9319307ba33
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227834119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
4227834119
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.1709233064
Short name T96
Test name
Test status
Simulation time 473751438 ps
CPU time 9.26 seconds
Started Jul 10 05:03:52 PM PDT 24
Finished Jul 10 05:04:03 PM PDT 24
Peak memory 224344 kb
Host smart-65340bbe-5ea5-438e-8735-a70dfca72469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709233064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.1709233064
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.1771648167
Short name T384
Test name
Test status
Simulation time 176983554 ps
CPU time 2.12 seconds
Started Jul 10 05:03:50 PM PDT 24
Finished Jul 10 05:03:55 PM PDT 24
Peak memory 213560 kb
Host smart-547df3a9-40e4-4a49-8a47-9d99603225f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771648167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.1771648167
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.493649814
Short name T292
Test name
Test status
Simulation time 222346879 ps
CPU time 21.27 seconds
Started Jul 10 05:03:47 PM PDT 24
Finished Jul 10 05:04:11 PM PDT 24
Peak memory 250412 kb
Host smart-5e2394a0-c29c-40d3-9383-9d48f009e73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493649814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.493649814
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.3561650709
Short name T422
Test name
Test status
Simulation time 165065494 ps
CPU time 2.5 seconds
Started Jul 10 05:03:51 PM PDT 24
Finished Jul 10 05:03:56 PM PDT 24
Peak memory 223420 kb
Host smart-cb17e603-8a8f-4fb7-9418-0f207503dd7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561650709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.3561650709
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.204678458
Short name T82
Test name
Test status
Simulation time 7532414727 ps
CPU time 60.02 seconds
Started Jul 10 05:03:52 PM PDT 24
Finished Jul 10 05:04:54 PM PDT 24
Peak memory 248616 kb
Host smart-edd23a86-2c14-4bf7-92ae-c84ce3dc3114
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204678458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.204678458
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.425200686
Short name T167
Test name
Test status
Simulation time 216960828182 ps
CPU time 456.85 seconds
Started Jul 10 05:03:49 PM PDT 24
Finished Jul 10 05:11:29 PM PDT 24
Peak memory 352308 kb
Host smart-ed994c3e-1364-49cc-9f79-c35ba20a9ca5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=425200686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all_with_rand_reset.425200686
Directory /workspace/27.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.2521701355
Short name T118
Test name
Test status
Simulation time 28005545 ps
CPU time 1.13 seconds
Started Jul 10 05:03:48 PM PDT 24
Finished Jul 10 05:03:52 PM PDT 24
Peak memory 211340 kb
Host smart-0d8f0e9c-bc5d-4d74-9303-2652619b743b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521701355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.2521701355
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.3103635411
Short name T24
Test name
Test status
Simulation time 45178419 ps
CPU time 0.89 seconds
Started Jul 10 05:03:56 PM PDT 24
Finished Jul 10 05:03:59 PM PDT 24
Peak memory 208388 kb
Host smart-61aa93c0-4cb7-49b6-b2e5-5869926fef54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103635411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.3103635411
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.2226645856
Short name T549
Test name
Test status
Simulation time 1283731750 ps
CPU time 11.82 seconds
Started Jul 10 05:03:56 PM PDT 24
Finished Jul 10 05:04:09 PM PDT 24
Peak memory 217720 kb
Host smart-278993a7-51b1-4019-94bc-f8245223d1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226645856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.2226645856
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.1098716673
Short name T28
Test name
Test status
Simulation time 2898186080 ps
CPU time 15.44 seconds
Started Jul 10 05:03:59 PM PDT 24
Finished Jul 10 05:04:17 PM PDT 24
Peak memory 216856 kb
Host smart-b47dce73-2752-4404-b9d8-0003ef892c5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098716673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.1098716673
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.968913510
Short name T773
Test name
Test status
Simulation time 48059495 ps
CPU time 2.24 seconds
Started Jul 10 05:03:57 PM PDT 24
Finished Jul 10 05:04:02 PM PDT 24
Peak memory 221644 kb
Host smart-d3c285bb-6faa-447b-9912-93ca8bd646a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968913510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.968913510
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.1701230944
Short name T841
Test name
Test status
Simulation time 310043394 ps
CPU time 10.56 seconds
Started Jul 10 05:04:02 PM PDT 24
Finished Jul 10 05:04:14 PM PDT 24
Peak memory 225356 kb
Host smart-e707e71d-838d-4e6c-b831-7e7459108ab1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701230944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.1701230944
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.3744525716
Short name T814
Test name
Test status
Simulation time 429926158 ps
CPU time 15.63 seconds
Started Jul 10 05:03:57 PM PDT 24
Finished Jul 10 05:04:15 PM PDT 24
Peak memory 225384 kb
Host smart-c1d504ee-3f6a-46b7-a1d5-08d82f87d919
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744525716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.3744525716
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.1426536881
Short name T253
Test name
Test status
Simulation time 961417657 ps
CPU time 9.04 seconds
Started Jul 10 05:03:58 PM PDT 24
Finished Jul 10 05:04:10 PM PDT 24
Peak memory 217548 kb
Host smart-dcc3115a-981c-4899-b5cb-ecea13570600
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426536881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
1426536881
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.2160336046
Short name T309
Test name
Test status
Simulation time 533372898 ps
CPU time 10.41 seconds
Started Jul 10 05:03:58 PM PDT 24
Finished Jul 10 05:04:11 PM PDT 24
Peak memory 225432 kb
Host smart-0ed0dd7e-a2d7-4678-a708-3ae91cb09b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160336046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.2160336046
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.115028315
Short name T525
Test name
Test status
Simulation time 37985787 ps
CPU time 2.89 seconds
Started Jul 10 05:03:48 PM PDT 24
Finished Jul 10 05:03:53 PM PDT 24
Peak memory 223308 kb
Host smart-22987cac-274b-48d9-a3fe-3659d77486e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115028315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.115028315
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.1925502860
Short name T364
Test name
Test status
Simulation time 297731659 ps
CPU time 35.38 seconds
Started Jul 10 05:03:57 PM PDT 24
Finished Jul 10 05:04:35 PM PDT 24
Peak memory 250460 kb
Host smart-123f8681-23ef-4ebb-bc83-1d7d92f99af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925502860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.1925502860
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.2577431715
Short name T225
Test name
Test status
Simulation time 114188662 ps
CPU time 4.5 seconds
Started Jul 10 05:03:56 PM PDT 24
Finished Jul 10 05:04:02 PM PDT 24
Peak memory 225824 kb
Host smart-744f8ced-7de3-4077-9758-3a59348a491d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577431715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.2577431715
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.1931174185
Short name T740
Test name
Test status
Simulation time 2048330771 ps
CPU time 46.02 seconds
Started Jul 10 05:03:58 PM PDT 24
Finished Jul 10 05:04:47 PM PDT 24
Peak memory 248136 kb
Host smart-4bef320e-5ad9-44bb-9d6c-8307c9a794d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931174185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.1931174185
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.3901178837
Short name T859
Test name
Test status
Simulation time 40539959 ps
CPU time 1.19 seconds
Started Jul 10 05:03:56 PM PDT 24
Finished Jul 10 05:03:58 PM PDT 24
Peak memory 208464 kb
Host smart-17306de9-13ef-46c9-9d6c-b9081df0fb54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901178837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.3901178837
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.3923962320
Short name T472
Test name
Test status
Simulation time 1431740557 ps
CPU time 15.24 seconds
Started Jul 10 05:03:58 PM PDT 24
Finished Jul 10 05:04:15 PM PDT 24
Peak memory 217656 kb
Host smart-a19cf57d-3e4b-441e-8757-ac4aeea59064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923962320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.3923962320
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.3282342177
Short name T717
Test name
Test status
Simulation time 2528424524 ps
CPU time 12.77 seconds
Started Jul 10 05:03:56 PM PDT 24
Finished Jul 10 05:04:10 PM PDT 24
Peak memory 217236 kb
Host smart-5237a407-150f-434e-a2f6-fbd2d51cf6b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282342177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.3282342177
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.346301863
Short name T750
Test name
Test status
Simulation time 64305004 ps
CPU time 2.28 seconds
Started Jul 10 05:03:57 PM PDT 24
Finished Jul 10 05:04:01 PM PDT 24
Peak memory 221736 kb
Host smart-c3f7de49-ae36-4263-97a8-2401ef21474f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346301863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.346301863
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.687534538
Short name T48
Test name
Test status
Simulation time 274929073 ps
CPU time 12.47 seconds
Started Jul 10 05:03:56 PM PDT 24
Finished Jul 10 05:04:11 PM PDT 24
Peak memory 225008 kb
Host smart-1f380615-9823-4b4e-a02e-3c1019719c1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687534538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.687534538
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.2730670267
Short name T424
Test name
Test status
Simulation time 2467032248 ps
CPU time 20.58 seconds
Started Jul 10 05:03:59 PM PDT 24
Finished Jul 10 05:04:23 PM PDT 24
Peak memory 225456 kb
Host smart-8c42ffac-f079-4295-b5f0-92842f8e9eed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730670267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.2730670267
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.3277217669
Short name T831
Test name
Test status
Simulation time 328008598 ps
CPU time 9.63 seconds
Started Jul 10 05:03:56 PM PDT 24
Finished Jul 10 05:04:08 PM PDT 24
Peak memory 217596 kb
Host smart-21a5b1c3-f2d9-46ac-b510-ac1fdf03b0e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277217669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
3277217669
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.3892071484
Short name T293
Test name
Test status
Simulation time 541402426 ps
CPU time 11.07 seconds
Started Jul 10 05:03:55 PM PDT 24
Finished Jul 10 05:04:07 PM PDT 24
Peak memory 217728 kb
Host smart-72095c84-9051-4e37-b000-cb010f373fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892071484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.3892071484
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.1955912197
Short name T386
Test name
Test status
Simulation time 148163662 ps
CPU time 3.1 seconds
Started Jul 10 05:03:58 PM PDT 24
Finished Jul 10 05:04:03 PM PDT 24
Peak memory 214076 kb
Host smart-6b269a4a-a591-450e-9e03-bf6ef58f83c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955912197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.1955912197
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.758515292
Short name T485
Test name
Test status
Simulation time 826725957 ps
CPU time 32.46 seconds
Started Jul 10 05:03:58 PM PDT 24
Finished Jul 10 05:04:33 PM PDT 24
Peak memory 250404 kb
Host smart-4d072e04-4a8d-4bc4-9909-5d63bd2aba2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758515292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.758515292
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.3979678541
Short name T537
Test name
Test status
Simulation time 52223764 ps
CPU time 6.26 seconds
Started Jul 10 05:03:58 PM PDT 24
Finished Jul 10 05:04:06 PM PDT 24
Peak memory 250016 kb
Host smart-e0794eab-e0a3-46ac-b7fe-37fe10989500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979678541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.3979678541
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.1777985101
Short name T260
Test name
Test status
Simulation time 38360957562 ps
CPU time 242.64 seconds
Started Jul 10 05:03:56 PM PDT 24
Finished Jul 10 05:08:01 PM PDT 24
Peak memory 281548 kb
Host smart-3dcb5594-217c-4576-b59c-3a11230daca9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777985101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.1777985101
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.2047033624
Short name T608
Test name
Test status
Simulation time 54195351 ps
CPU time 0.94 seconds
Started Jul 10 05:04:02 PM PDT 24
Finished Jul 10 05:04:05 PM PDT 24
Peak memory 217152 kb
Host smart-8ee7317a-a274-4e93-85aa-1d0cbff6c5ae
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047033624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.2047033624
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.1394106388
Short name T693
Test name
Test status
Simulation time 19105063 ps
CPU time 0.87 seconds
Started Jul 10 05:01:43 PM PDT 24
Finished Jul 10 05:01:47 PM PDT 24
Peak memory 208456 kb
Host smart-e13fbbe8-e140-461d-8331-235ebcf9b606
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394106388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.1394106388
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.868067750
Short name T216
Test name
Test status
Simulation time 12947641 ps
CPU time 0.99 seconds
Started Jul 10 05:01:33 PM PDT 24
Finished Jul 10 05:01:36 PM PDT 24
Peak memory 208636 kb
Host smart-7a530213-9232-4a8c-8517-428d51f429b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868067750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.868067750
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.959155043
Short name T772
Test name
Test status
Simulation time 247186431 ps
CPU time 8.48 seconds
Started Jul 10 05:01:27 PM PDT 24
Finished Jul 10 05:01:37 PM PDT 24
Peak memory 217716 kb
Host smart-87262969-6f0e-48fc-9a65-9a7244efe3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959155043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.959155043
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.1808693503
Short name T523
Test name
Test status
Simulation time 949508204 ps
CPU time 10.08 seconds
Started Jul 10 05:01:33 PM PDT 24
Finished Jul 10 05:01:44 PM PDT 24
Peak memory 217068 kb
Host smart-414b4a20-cfd3-4e00-a265-c7da7c6f27e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808693503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.1808693503
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.2596033326
Short name T230
Test name
Test status
Simulation time 3501574457 ps
CPU time 54.04 seconds
Started Jul 10 05:01:37 PM PDT 24
Finished Jul 10 05:02:32 PM PDT 24
Peak memory 217948 kb
Host smart-a6953faa-a3ac-42f6-9f47-de6020caba9e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596033326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.2596033326
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.306992324
Short name T486
Test name
Test status
Simulation time 1525531910 ps
CPU time 10.2 seconds
Started Jul 10 05:01:34 PM PDT 24
Finished Jul 10 05:01:45 PM PDT 24
Peak memory 217144 kb
Host smart-cdf7a866-2bcb-4c77-b99f-3b1656cff047
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306992324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.306992324
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.3831184917
Short name T112
Test name
Test status
Simulation time 220340604 ps
CPU time 4.7 seconds
Started Jul 10 05:01:36 PM PDT 24
Finished Jul 10 05:01:42 PM PDT 24
Peak memory 222364 kb
Host smart-603c2060-2c53-46a6-9bfc-4d77ba3256a0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831184917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.3831184917
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1557489245
Short name T301
Test name
Test status
Simulation time 10700105018 ps
CPU time 11.2 seconds
Started Jul 10 05:01:35 PM PDT 24
Finished Jul 10 05:01:47 PM PDT 24
Peak memory 217160 kb
Host smart-dbbdd4d2-76e5-4c12-b841-e359469a9af1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557489245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.1557489245
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.1714491554
Short name T86
Test name
Test status
Simulation time 89342177 ps
CPU time 2.88 seconds
Started Jul 10 05:01:34 PM PDT 24
Finished Jul 10 05:01:39 PM PDT 24
Peak memory 216988 kb
Host smart-6db24e6d-bcaf-4835-9e61-2af3fc37360e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714491554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
1714491554
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.3813099335
Short name T91
Test name
Test status
Simulation time 1592469044 ps
CPU time 47.11 seconds
Started Jul 10 05:01:34 PM PDT 24
Finished Jul 10 05:02:23 PM PDT 24
Peak memory 274924 kb
Host smart-700cd1e9-2876-4672-a58f-c1b3336d56c8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813099335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.3813099335
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.2935901862
Short name T799
Test name
Test status
Simulation time 814815149 ps
CPU time 16.73 seconds
Started Jul 10 05:01:35 PM PDT 24
Finished Jul 10 05:01:53 PM PDT 24
Peak memory 250384 kb
Host smart-5daacf6a-e56d-4d76-9020-9d0a4b4d598f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935901862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.2935901862
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.2683084074
Short name T414
Test name
Test status
Simulation time 230776134 ps
CPU time 3.27 seconds
Started Jul 10 05:01:35 PM PDT 24
Finished Jul 10 05:01:41 PM PDT 24
Peak memory 217704 kb
Host smart-fa364a71-e57e-4ea4-8afa-c63503b0bf81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683084074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.2683084074
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.626814269
Short name T73
Test name
Test status
Simulation time 192029500 ps
CPU time 13.36 seconds
Started Jul 10 05:01:39 PM PDT 24
Finished Jul 10 05:01:56 PM PDT 24
Peak memory 217088 kb
Host smart-a7caef95-c864-4cc0-8b13-54f6759f0882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626814269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.626814269
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.185683092
Short name T508
Test name
Test status
Simulation time 1211610377 ps
CPU time 9.13 seconds
Started Jul 10 05:01:36 PM PDT 24
Finished Jul 10 05:01:47 PM PDT 24
Peak memory 225460 kb
Host smart-61a58688-8cfe-4355-9353-907d1fa2266c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185683092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_dig
est.185683092
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.4185600136
Short name T70
Test name
Test status
Simulation time 1010337148 ps
CPU time 8.05 seconds
Started Jul 10 05:01:34 PM PDT 24
Finished Jul 10 05:01:43 PM PDT 24
Peak memory 217604 kb
Host smart-702d007c-eb61-433e-ba8c-efbaae7862d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185600136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.4
185600136
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.3926296322
Short name T730
Test name
Test status
Simulation time 1288687362 ps
CPU time 7.48 seconds
Started Jul 10 05:01:28 PM PDT 24
Finished Jul 10 05:01:37 PM PDT 24
Peak memory 217728 kb
Host smart-62777209-4924-4b87-be7f-48c37153f41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926296322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.3926296322
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.922176331
Short name T439
Test name
Test status
Simulation time 92618717 ps
CPU time 1.67 seconds
Started Jul 10 05:01:36 PM PDT 24
Finished Jul 10 05:01:39 PM PDT 24
Peak memory 213260 kb
Host smart-8c8550cf-5b6f-46a4-8426-d6e7fdfeedf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922176331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.922176331
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.3292223707
Short name T687
Test name
Test status
Simulation time 1191576046 ps
CPU time 27.97 seconds
Started Jul 10 05:01:36 PM PDT 24
Finished Jul 10 05:02:05 PM PDT 24
Peak memory 250404 kb
Host smart-3b3271c5-78e3-4425-9bee-7b0d94679626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292223707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.3292223707
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.2106889653
Short name T383
Test name
Test status
Simulation time 140731494 ps
CPU time 6.27 seconds
Started Jul 10 05:01:29 PM PDT 24
Finished Jul 10 05:01:37 PM PDT 24
Peak memory 249848 kb
Host smart-f65a1856-7ca3-4676-a573-a264d93cfbc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106889653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.2106889653
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.3518542662
Short name T359
Test name
Test status
Simulation time 3168510270 ps
CPU time 71.42 seconds
Started Jul 10 05:01:34 PM PDT 24
Finished Jul 10 05:02:47 PM PDT 24
Peak memory 252032 kb
Host smart-8707fa4b-945d-41c5-b483-25a41befe630
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518542662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.3518542662
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.803690639
Short name T632
Test name
Test status
Simulation time 14449469 ps
CPU time 1.11 seconds
Started Jul 10 05:01:27 PM PDT 24
Finished Jul 10 05:01:29 PM PDT 24
Peak memory 211312 kb
Host smart-4fcf918f-838a-4bba-b5f5-63e22689cee3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803690639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctr
l_volatile_unlock_smoke.803690639
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.1516284218
Short name T232
Test name
Test status
Simulation time 149718912 ps
CPU time 1.26 seconds
Started Jul 10 05:04:06 PM PDT 24
Finished Jul 10 05:04:10 PM PDT 24
Peak memory 208404 kb
Host smart-3ce14e77-61af-46f1-b5b5-305ad880f75f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516284218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.1516284218
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.1181720800
Short name T596
Test name
Test status
Simulation time 1080207312 ps
CPU time 16.69 seconds
Started Jul 10 05:03:56 PM PDT 24
Finished Jul 10 05:04:14 PM PDT 24
Peak memory 225476 kb
Host smart-427d8c40-642f-4507-9956-f438a0f41c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181720800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.1181720800
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.2014490209
Short name T423
Test name
Test status
Simulation time 926719970 ps
CPU time 3.01 seconds
Started Jul 10 05:03:58 PM PDT 24
Finished Jul 10 05:04:03 PM PDT 24
Peak memory 217012 kb
Host smart-89019e2a-974c-403e-9fff-b866d69938f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014490209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.2014490209
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.714797469
Short name T574
Test name
Test status
Simulation time 52486451 ps
CPU time 1.72 seconds
Started Jul 10 05:03:58 PM PDT 24
Finished Jul 10 05:04:03 PM PDT 24
Peak memory 217712 kb
Host smart-8077b7e5-963d-40e3-bf67-49780d7578f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714797469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.714797469
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.3791772248
Short name T593
Test name
Test status
Simulation time 1243216964 ps
CPU time 13.07 seconds
Started Jul 10 05:04:02 PM PDT 24
Finished Jul 10 05:04:17 PM PDT 24
Peak memory 218244 kb
Host smart-af639eee-ae41-4fc4-a990-ec7c89320892
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791772248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.3791772248
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.1776175850
Short name T169
Test name
Test status
Simulation time 1446426260 ps
CPU time 13.49 seconds
Started Jul 10 05:04:04 PM PDT 24
Finished Jul 10 05:04:19 PM PDT 24
Peak memory 225376 kb
Host smart-d7fd5c4a-b8ce-4fbb-bb89-15d77a48c974
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776175850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.1776175850
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.1387055875
Short name T713
Test name
Test status
Simulation time 502834283 ps
CPU time 8.33 seconds
Started Jul 10 05:03:55 PM PDT 24
Finished Jul 10 05:04:05 PM PDT 24
Peak memory 217608 kb
Host smart-8aa25bec-ee14-472f-960c-bb9d89a921d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387055875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
1387055875
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.1390525582
Short name T520
Test name
Test status
Simulation time 240899130 ps
CPU time 6.86 seconds
Started Jul 10 05:03:56 PM PDT 24
Finished Jul 10 05:04:04 PM PDT 24
Peak memory 225432 kb
Host smart-26d624b6-8ac9-4514-a98c-cf8ad5ee815e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390525582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.1390525582
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.3696632931
Short name T835
Test name
Test status
Simulation time 31818346 ps
CPU time 1.35 seconds
Started Jul 10 05:03:57 PM PDT 24
Finished Jul 10 05:04:00 PM PDT 24
Peak memory 217080 kb
Host smart-70705b36-3917-49ea-b92e-91b3425a5a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696632931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.3696632931
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.2665505508
Short name T803
Test name
Test status
Simulation time 246418839 ps
CPU time 25.02 seconds
Started Jul 10 05:03:56 PM PDT 24
Finished Jul 10 05:04:22 PM PDT 24
Peak memory 250468 kb
Host smart-b93ad5e1-8109-4b5c-aa44-f8c24c76ca05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665505508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.2665505508
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.3919818692
Short name T314
Test name
Test status
Simulation time 74706426 ps
CPU time 7.44 seconds
Started Jul 10 05:03:58 PM PDT 24
Finished Jul 10 05:04:07 PM PDT 24
Peak memory 246876 kb
Host smart-66bcdfb9-b480-4392-a9dc-0040d8dff35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919818692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.3919818692
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.3015751019
Short name T456
Test name
Test status
Simulation time 10895993804 ps
CPU time 55.44 seconds
Started Jul 10 05:04:05 PM PDT 24
Finished Jul 10 05:05:02 PM PDT 24
Peak memory 250468 kb
Host smart-b741392f-8ad2-4562-bf20-7cf9f0138311
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015751019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.3015751019
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.4148306721
Short name T712
Test name
Test status
Simulation time 17965064 ps
CPU time 1.16 seconds
Started Jul 10 05:03:59 PM PDT 24
Finished Jul 10 05:04:03 PM PDT 24
Peak memory 217552 kb
Host smart-c2ca6d6d-ed31-4bdc-8c6b-0a47d32af88c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148306721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.4148306721
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.1453541111
Short name T685
Test name
Test status
Simulation time 54275037 ps
CPU time 1.1 seconds
Started Jul 10 05:04:04 PM PDT 24
Finished Jul 10 05:04:06 PM PDT 24
Peak memory 208412 kb
Host smart-ac8af2a0-e258-4841-b3e7-a9a4fb87babe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453541111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.1453541111
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.4267291896
Short name T848
Test name
Test status
Simulation time 5307893450 ps
CPU time 13 seconds
Started Jul 10 05:04:03 PM PDT 24
Finished Jul 10 05:04:18 PM PDT 24
Peak memory 225648 kb
Host smart-90fee39c-bacb-4e3b-a7a4-eb8af31a3a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267291896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.4267291896
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.3013204999
Short name T196
Test name
Test status
Simulation time 493345082 ps
CPU time 3.59 seconds
Started Jul 10 05:04:04 PM PDT 24
Finished Jul 10 05:04:09 PM PDT 24
Peak memory 217052 kb
Host smart-df750d47-f24a-43bc-8150-b75777230059
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013204999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.3013204999
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.2990416719
Short name T599
Test name
Test status
Simulation time 129748883 ps
CPU time 3.59 seconds
Started Jul 10 05:04:11 PM PDT 24
Finished Jul 10 05:04:17 PM PDT 24
Peak memory 217696 kb
Host smart-84a494c8-13a0-4249-b38f-913282d138a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990416719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.2990416719
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.446103439
Short name T432
Test name
Test status
Simulation time 375990966 ps
CPU time 10.19 seconds
Started Jul 10 05:04:08 PM PDT 24
Finished Jul 10 05:04:22 PM PDT 24
Peak memory 217728 kb
Host smart-22f2d702-6814-4da8-b290-cc9d6c4a2def
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446103439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.446103439
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.3712264140
Short name T501
Test name
Test status
Simulation time 873790878 ps
CPU time 10.39 seconds
Started Jul 10 05:04:05 PM PDT 24
Finished Jul 10 05:04:17 PM PDT 24
Peak memory 225436 kb
Host smart-2587be4b-f38c-4db5-b3cc-9f4faf171e20
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712264140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.3712264140
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.2950660178
Short name T313
Test name
Test status
Simulation time 384735660 ps
CPU time 9.64 seconds
Started Jul 10 05:04:05 PM PDT 24
Finished Jul 10 05:04:17 PM PDT 24
Peak memory 217628 kb
Host smart-8aebd4b9-2d81-4252-b979-3ae3136c9be5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950660178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
2950660178
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.3291096049
Short name T454
Test name
Test status
Simulation time 206684110 ps
CPU time 4.94 seconds
Started Jul 10 05:04:05 PM PDT 24
Finished Jul 10 05:04:12 PM PDT 24
Peak memory 217084 kb
Host smart-2b1fb6ab-8272-41d5-832a-4cceeeb98de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291096049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.3291096049
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.2910543898
Short name T109
Test name
Test status
Simulation time 207999280 ps
CPU time 21.81 seconds
Started Jul 10 05:04:04 PM PDT 24
Finished Jul 10 05:04:28 PM PDT 24
Peak memory 250464 kb
Host smart-5a3727f1-eeb2-46fc-b23c-42bc27f2c82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910543898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.2910543898
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.451703891
Short name T226
Test name
Test status
Simulation time 65172361 ps
CPU time 6.94 seconds
Started Jul 10 05:04:11 PM PDT 24
Finished Jul 10 05:04:20 PM PDT 24
Peak memory 250448 kb
Host smart-81c1c58e-69b3-44c9-ae7f-966e29c5c2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451703891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.451703891
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.3713217853
Short name T427
Test name
Test status
Simulation time 20619592578 ps
CPU time 373.77 seconds
Started Jul 10 05:04:07 PM PDT 24
Finished Jul 10 05:10:24 PM PDT 24
Peak memory 250464 kb
Host smart-657ecde1-e886-4cb6-9e02-1aea86c303f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713217853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.3713217853
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.1579764919
Short name T228
Test name
Test status
Simulation time 24407551 ps
CPU time 0.91 seconds
Started Jul 10 05:04:05 PM PDT 24
Finished Jul 10 05:04:07 PM PDT 24
Peak memory 208324 kb
Host smart-a140904c-0d5a-48b3-a33c-22243929ec38
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579764919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.1579764919
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.3490827195
Short name T1
Test name
Test status
Simulation time 25643651 ps
CPU time 0.85 seconds
Started Jul 10 05:04:13 PM PDT 24
Finished Jul 10 05:04:18 PM PDT 24
Peak memory 208548 kb
Host smart-49150ece-0ecb-4ee7-9a50-054400f92ade
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490827195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.3490827195
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.2285649563
Short name T529
Test name
Test status
Simulation time 2317226844 ps
CPU time 12.57 seconds
Started Jul 10 05:04:13 PM PDT 24
Finished Jul 10 05:04:30 PM PDT 24
Peak memory 217656 kb
Host smart-f7b7e6c5-4274-421d-962c-f9ccfd368533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285649563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.2285649563
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.846399499
Short name T323
Test name
Test status
Simulation time 2294773244 ps
CPU time 5.75 seconds
Started Jul 10 05:04:12 PM PDT 24
Finished Jul 10 05:04:21 PM PDT 24
Peak memory 217192 kb
Host smart-875f2ee7-4814-4d1d-bf9b-6dc5acb9df8b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846399499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.846399499
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.3036822570
Short name T286
Test name
Test status
Simulation time 1481474498 ps
CPU time 3.96 seconds
Started Jul 10 05:04:06 PM PDT 24
Finished Jul 10 05:04:13 PM PDT 24
Peak memory 217652 kb
Host smart-515f0950-1f5f-472a-8dd7-346a34103385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036822570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.3036822570
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.4147189235
Short name T192
Test name
Test status
Simulation time 872924530 ps
CPU time 10.2 seconds
Started Jul 10 05:04:12 PM PDT 24
Finished Jul 10 05:04:26 PM PDT 24
Peak memory 218356 kb
Host smart-5f55de8a-6170-4199-816d-285d8c84316b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147189235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.4147189235
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.1164780510
Short name T702
Test name
Test status
Simulation time 436528339 ps
CPU time 12.4 seconds
Started Jul 10 05:04:16 PM PDT 24
Finished Jul 10 05:04:33 PM PDT 24
Peak memory 225392 kb
Host smart-fad41c24-f608-46b6-87d8-ae7202658f5d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164780510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.1164780510
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.3394167530
Short name T319
Test name
Test status
Simulation time 461105143 ps
CPU time 10.74 seconds
Started Jul 10 05:04:12 PM PDT 24
Finished Jul 10 05:04:26 PM PDT 24
Peak memory 217608 kb
Host smart-95db0afc-6c64-4834-956a-8d59c7700cca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394167530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
3394167530
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.326133783
Short name T219
Test name
Test status
Simulation time 352702307 ps
CPU time 8.45 seconds
Started Jul 10 05:04:13 PM PDT 24
Finished Jul 10 05:04:25 PM PDT 24
Peak memory 225484 kb
Host smart-de7eae3d-bb22-4fcc-8e1f-c8dd96336638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326133783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.326133783
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.1913477647
Short name T184
Test name
Test status
Simulation time 95404410 ps
CPU time 2.86 seconds
Started Jul 10 05:04:04 PM PDT 24
Finished Jul 10 05:04:08 PM PDT 24
Peak memory 217144 kb
Host smart-e9cff820-3e44-4416-beef-19f9411fec22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913477647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.1913477647
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.1735158977
Short name T638
Test name
Test status
Simulation time 135792751 ps
CPU time 17.11 seconds
Started Jul 10 05:04:08 PM PDT 24
Finished Jul 10 05:04:27 PM PDT 24
Peak memory 250460 kb
Host smart-2c940a16-ec7b-4afd-a892-47de3f31e407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735158977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.1735158977
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.3157418559
Short name T714
Test name
Test status
Simulation time 66559389 ps
CPU time 7.66 seconds
Started Jul 10 05:04:05 PM PDT 24
Finished Jul 10 05:04:15 PM PDT 24
Peak memory 250404 kb
Host smart-8ccba76b-bdc0-4b10-ac48-ca68364bbe58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157418559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.3157418559
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.983877923
Short name T172
Test name
Test status
Simulation time 15924810665 ps
CPU time 258 seconds
Started Jul 10 05:04:12 PM PDT 24
Finished Jul 10 05:08:33 PM PDT 24
Peak memory 275312 kb
Host smart-29f20a92-8113-4cbd-88b4-3eb9cd9933bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983877923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.983877923
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.771824978
Short name T819
Test name
Test status
Simulation time 80687819708 ps
CPU time 1794.11 seconds
Started Jul 10 05:04:14 PM PDT 24
Finished Jul 10 05:34:12 PM PDT 24
Peak memory 936112 kb
Host smart-f15da438-9786-4eb5-81af-e5d4a03a1dd9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=771824978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.771824978
Directory /workspace/32.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.2770824387
Short name T673
Test name
Test status
Simulation time 12902795 ps
CPU time 0.96 seconds
Started Jul 10 05:04:06 PM PDT 24
Finished Jul 10 05:04:09 PM PDT 24
Peak memory 211324 kb
Host smart-8f752605-8e97-432d-ba67-4688885411e8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770824387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.2770824387
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.2334552623
Short name T247
Test name
Test status
Simulation time 20351801 ps
CPU time 0.85 seconds
Started Jul 10 05:04:12 PM PDT 24
Finished Jul 10 05:04:16 PM PDT 24
Peak memory 208516 kb
Host smart-56973968-4f3e-4d4a-91f4-7037fd048193
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334552623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.2334552623
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.2306325817
Short name T710
Test name
Test status
Simulation time 280207847 ps
CPU time 11.8 seconds
Started Jul 10 05:04:14 PM PDT 24
Finished Jul 10 05:04:30 PM PDT 24
Peak memory 217724 kb
Host smart-57f66831-59ab-48ec-9af1-42729b402e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306325817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.2306325817
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.1911641305
Short name T663
Test name
Test status
Simulation time 683279702 ps
CPU time 6.1 seconds
Started Jul 10 05:04:11 PM PDT 24
Finished Jul 10 05:04:20 PM PDT 24
Peak memory 217044 kb
Host smart-3e19fd01-67aa-454c-9e96-020f7750a674
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911641305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.1911641305
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.4279144885
Short name T66
Test name
Test status
Simulation time 355301980 ps
CPU time 1.91 seconds
Started Jul 10 05:04:12 PM PDT 24
Finished Jul 10 05:04:17 PM PDT 24
Peak memory 217660 kb
Host smart-7ac2e274-a9c2-40a0-bf8f-3316cb0779a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279144885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.4279144885
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.1742716978
Short name T340
Test name
Test status
Simulation time 283895262 ps
CPU time 15.06 seconds
Started Jul 10 05:04:14 PM PDT 24
Finished Jul 10 05:04:33 PM PDT 24
Peak memory 219376 kb
Host smart-d7e30cce-268c-4ac6-9cc9-e4f3b9f1c3fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742716978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.1742716978
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.1107573330
Short name T352
Test name
Test status
Simulation time 350985557 ps
CPU time 13.92 seconds
Started Jul 10 05:04:10 PM PDT 24
Finished Jul 10 05:04:27 PM PDT 24
Peak memory 225360 kb
Host smart-5add1c49-6b7a-4e8a-989f-7e6fa51a0ebc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107573330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.1107573330
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.1222699131
Short name T428
Test name
Test status
Simulation time 2730388117 ps
CPU time 13.52 seconds
Started Jul 10 05:04:12 PM PDT 24
Finished Jul 10 05:04:30 PM PDT 24
Peak memory 217736 kb
Host smart-93e8405e-4ffd-4ebf-8b23-a29183585dbb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222699131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
1222699131
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.2399768676
Short name T624
Test name
Test status
Simulation time 1518669246 ps
CPU time 9.62 seconds
Started Jul 10 05:04:13 PM PDT 24
Finished Jul 10 05:04:26 PM PDT 24
Peak memory 225256 kb
Host smart-c543eac5-96e7-41be-9895-10318ef8d545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399768676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.2399768676
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.3416212648
Short name T378
Test name
Test status
Simulation time 83221682 ps
CPU time 1.76 seconds
Started Jul 10 05:04:17 PM PDT 24
Finished Jul 10 05:04:23 PM PDT 24
Peak memory 217080 kb
Host smart-5701bbb0-8e49-481d-9dd4-58722e079326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416212648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.3416212648
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.2883759345
Short name T255
Test name
Test status
Simulation time 296739796 ps
CPU time 31.79 seconds
Started Jul 10 05:04:13 PM PDT 24
Finished Jul 10 05:04:49 PM PDT 24
Peak memory 250460 kb
Host smart-fc4c3c5b-6a11-4e17-afb1-67bae81f0b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883759345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.2883759345
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.839845525
Short name T697
Test name
Test status
Simulation time 136671034 ps
CPU time 7.69 seconds
Started Jul 10 05:04:13 PM PDT 24
Finished Jul 10 05:04:24 PM PDT 24
Peak memory 250428 kb
Host smart-22d46b10-a4f6-46f8-85b0-4501dfab9531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839845525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.839845525
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.2061259274
Short name T106
Test name
Test status
Simulation time 4124019130 ps
CPU time 39.88 seconds
Started Jul 10 05:04:13 PM PDT 24
Finished Jul 10 05:04:57 PM PDT 24
Peak memory 250456 kb
Host smart-48788c11-636e-4574-ab9f-5257b22ab504
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061259274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.2061259274
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.621752536
Short name T720
Test name
Test status
Simulation time 23037745 ps
CPU time 1.03 seconds
Started Jul 10 05:04:13 PM PDT 24
Finished Jul 10 05:04:18 PM PDT 24
Peak memory 217072 kb
Host smart-43d35f26-b401-4288-bf68-e8b56464e363
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621752536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ct
rl_volatile_unlock_smoke.621752536
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.1979012574
Short name T557
Test name
Test status
Simulation time 402965410 ps
CPU time 1.02 seconds
Started Jul 10 05:04:14 PM PDT 24
Finished Jul 10 05:04:20 PM PDT 24
Peak memory 208388 kb
Host smart-35f68ea0-cc2d-430b-a85c-61d1ae68f2de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979012574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.1979012574
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.1231195528
Short name T288
Test name
Test status
Simulation time 1509863866 ps
CPU time 11.32 seconds
Started Jul 10 05:04:14 PM PDT 24
Finished Jul 10 05:04:29 PM PDT 24
Peak memory 217700 kb
Host smart-9dd382a9-98c4-4e71-95f1-51f62204da51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231195528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.1231195528
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.2205685308
Short name T33
Test name
Test status
Simulation time 605176808 ps
CPU time 6.99 seconds
Started Jul 10 05:04:13 PM PDT 24
Finished Jul 10 05:04:24 PM PDT 24
Peak memory 217076 kb
Host smart-e488f8d2-1186-44e6-9373-9be624a01f4b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205685308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.2205685308
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.1410559371
Short name T398
Test name
Test status
Simulation time 33443182 ps
CPU time 1.96 seconds
Started Jul 10 05:04:13 PM PDT 24
Finished Jul 10 05:04:19 PM PDT 24
Peak memory 221616 kb
Host smart-332770a5-b46c-48b2-ad77-127b0e825dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410559371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.1410559371
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.3455130843
Short name T564
Test name
Test status
Simulation time 280498407 ps
CPU time 9.13 seconds
Started Jul 10 05:04:12 PM PDT 24
Finished Jul 10 05:04:24 PM PDT 24
Peak memory 219348 kb
Host smart-a7dc28d5-51a4-4ca2-8b61-94c8eac5bf7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455130843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.3455130843
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.2711423405
Short name T659
Test name
Test status
Simulation time 778103818 ps
CPU time 9.48 seconds
Started Jul 10 05:04:12 PM PDT 24
Finished Jul 10 05:04:26 PM PDT 24
Peak memory 225428 kb
Host smart-7d11e138-e123-4075-82fc-389ef071d4bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711423405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.2711423405
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.918815604
Short name T329
Test name
Test status
Simulation time 582869256 ps
CPU time 8.93 seconds
Started Jul 10 05:04:14 PM PDT 24
Finished Jul 10 05:04:27 PM PDT 24
Peak memory 225364 kb
Host smart-f49e18d7-82e5-49ca-89f7-f8611923aff2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918815604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.918815604
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.589219860
Short name T535
Test name
Test status
Simulation time 370102321 ps
CPU time 10.15 seconds
Started Jul 10 05:04:14 PM PDT 24
Finished Jul 10 05:04:28 PM PDT 24
Peak memory 225508 kb
Host smart-edfe0d28-becb-46d1-9761-bc7b2158729c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589219860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.589219860
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.1438863877
Short name T72
Test name
Test status
Simulation time 79762733 ps
CPU time 2.02 seconds
Started Jul 10 05:04:11 PM PDT 24
Finished Jul 10 05:04:17 PM PDT 24
Peak memory 213632 kb
Host smart-2ea3a976-3c01-4c16-a856-2fac34a62358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438863877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.1438863877
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.261803342
Short name T381
Test name
Test status
Simulation time 485124240 ps
CPU time 27.4 seconds
Started Jul 10 05:04:12 PM PDT 24
Finished Jul 10 05:04:43 PM PDT 24
Peak memory 250616 kb
Host smart-cc7f3412-9419-4d91-8871-9e91372fd880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261803342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.261803342
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.4153892996
Short name T484
Test name
Test status
Simulation time 66302101 ps
CPU time 6.87 seconds
Started Jul 10 05:04:17 PM PDT 24
Finished Jul 10 05:04:28 PM PDT 24
Peak memory 246824 kb
Host smart-65b41039-9705-4278-8179-af0b8eea5127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153892996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.4153892996
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.2727081161
Short name T198
Test name
Test status
Simulation time 12347976337 ps
CPU time 256.14 seconds
Started Jul 10 05:04:15 PM PDT 24
Finished Jul 10 05:08:35 PM PDT 24
Peak memory 272896 kb
Host smart-b4d92699-215b-4f43-a93a-cd1c7d92da4c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727081161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.2727081161
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.3211945684
Short name T399
Test name
Test status
Simulation time 26477534 ps
CPU time 0.99 seconds
Started Jul 10 05:04:12 PM PDT 24
Finished Jul 10 05:04:17 PM PDT 24
Peak memory 211296 kb
Host smart-db3ce69f-88f3-4147-8a96-7ce1c865c835
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211945684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.3211945684
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.2344936909
Short name T281
Test name
Test status
Simulation time 23798245 ps
CPU time 0.92 seconds
Started Jul 10 05:04:20 PM PDT 24
Finished Jul 10 05:04:24 PM PDT 24
Peak memory 208400 kb
Host smart-b36e6eab-0443-4366-9f18-3034f7aa91e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344936909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.2344936909
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.3854139167
Short name T560
Test name
Test status
Simulation time 226438240 ps
CPU time 10.32 seconds
Started Jul 10 05:04:23 PM PDT 24
Finished Jul 10 05:04:37 PM PDT 24
Peak memory 217664 kb
Host smart-212f018f-489f-45da-be62-ffc63f13df24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854139167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.3854139167
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.887874211
Short name T322
Test name
Test status
Simulation time 2398944410 ps
CPU time 27.06 seconds
Started Jul 10 05:04:24 PM PDT 24
Finished Jul 10 05:04:54 PM PDT 24
Peak memory 217140 kb
Host smart-b6f4f6bb-4899-4103-b18c-765a1dd6c48d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887874211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.887874211
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.3365537093
Short name T266
Test name
Test status
Simulation time 140387064 ps
CPU time 2.36 seconds
Started Jul 10 05:04:23 PM PDT 24
Finished Jul 10 05:04:29 PM PDT 24
Peak memory 217676 kb
Host smart-d44d0f57-c95b-432f-ba8f-3b5065b1ab61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365537093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.3365537093
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.1332383499
Short name T44
Test name
Test status
Simulation time 403993154 ps
CPU time 11.85 seconds
Started Jul 10 05:04:20 PM PDT 24
Finished Jul 10 05:04:36 PM PDT 24
Peak memory 225404 kb
Host smart-92f6d3b0-7d70-40b5-a5a5-5d6ed2de6d00
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332383499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.1332383499
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.778755223
Short name T748
Test name
Test status
Simulation time 317532353 ps
CPU time 8.33 seconds
Started Jul 10 05:04:23 PM PDT 24
Finished Jul 10 05:04:34 PM PDT 24
Peak memory 217604 kb
Host smart-798002ee-258d-47a0-9916-5d42e5b5ee91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778755223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.778755223
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.3630561239
Short name T620
Test name
Test status
Simulation time 1550806614 ps
CPU time 11.57 seconds
Started Jul 10 05:04:21 PM PDT 24
Finished Jul 10 05:04:36 PM PDT 24
Peak memory 224672 kb
Host smart-d45f7dab-aa8f-4f29-9b8d-89c5a291445a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630561239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.3630561239
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.281215805
Short name T642
Test name
Test status
Simulation time 31313766 ps
CPU time 2.02 seconds
Started Jul 10 05:04:14 PM PDT 24
Finished Jul 10 05:04:20 PM PDT 24
Peak memory 213488 kb
Host smart-3c7db41e-d38a-41af-8b63-cf295b93ce3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281215805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.281215805
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.2719577142
Short name T548
Test name
Test status
Simulation time 215408971 ps
CPU time 25.21 seconds
Started Jul 10 05:04:15 PM PDT 24
Finished Jul 10 05:04:44 PM PDT 24
Peak memory 250404 kb
Host smart-f1f48016-f12c-400d-81f0-3551b05e7e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719577142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.2719577142
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.3430103129
Short name T181
Test name
Test status
Simulation time 95385247 ps
CPU time 3.64 seconds
Started Jul 10 05:04:14 PM PDT 24
Finished Jul 10 05:04:22 PM PDT 24
Peak memory 222196 kb
Host smart-1bd08184-0a2b-47c0-9048-6dda83aa4567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430103129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.3430103129
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.1860754001
Short name T602
Test name
Test status
Simulation time 18060106307 ps
CPU time 84.57 seconds
Started Jul 10 05:04:21 PM PDT 24
Finished Jul 10 05:05:49 PM PDT 24
Peak memory 258596 kb
Host smart-1ea87e15-44d6-41ce-8886-5853cad97e82
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860754001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.1860754001
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.1162488830
Short name T516
Test name
Test status
Simulation time 41897561 ps
CPU time 0.75 seconds
Started Jul 10 05:04:13 PM PDT 24
Finished Jul 10 05:04:18 PM PDT 24
Peak memory 208156 kb
Host smart-2b6a1727-6c76-4aeb-9f37-f0f33c76232a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162488830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.1162488830
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.1469868143
Short name T514
Test name
Test status
Simulation time 40922140 ps
CPU time 0.82 seconds
Started Jul 10 05:04:23 PM PDT 24
Finished Jul 10 05:04:27 PM PDT 24
Peak memory 208780 kb
Host smart-e1f4e22b-c27c-49fe-b908-ca53ca315bc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469868143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.1469868143
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.2700291501
Short name T282
Test name
Test status
Simulation time 936402867 ps
CPU time 12.13 seconds
Started Jul 10 05:04:19 PM PDT 24
Finished Jul 10 05:04:35 PM PDT 24
Peak memory 225496 kb
Host smart-bd835a42-b26c-41b8-b54b-cd70aa4357e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700291501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.2700291501
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.2858035160
Short name T27
Test name
Test status
Simulation time 9561497341 ps
CPU time 35.06 seconds
Started Jul 10 05:04:21 PM PDT 24
Finished Jul 10 05:04:59 PM PDT 24
Peak memory 217144 kb
Host smart-534ef219-3ded-4fdd-a30d-26b59f6dbc83
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858035160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.2858035160
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.3640657194
Short name T705
Test name
Test status
Simulation time 143311798 ps
CPU time 2.35 seconds
Started Jul 10 05:04:21 PM PDT 24
Finished Jul 10 05:04:26 PM PDT 24
Peak memory 221668 kb
Host smart-1a4b816a-28c8-4adb-87c0-2d602769982d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640657194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.3640657194
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.2939006231
Short name T370
Test name
Test status
Simulation time 1496410267 ps
CPU time 12.24 seconds
Started Jul 10 05:04:23 PM PDT 24
Finished Jul 10 05:04:38 PM PDT 24
Peak memory 218380 kb
Host smart-1dbc0afe-ed52-436f-8fbe-715925ed66aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939006231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.2939006231
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.432093693
Short name T507
Test name
Test status
Simulation time 367933111 ps
CPU time 11.11 seconds
Started Jul 10 05:04:24 PM PDT 24
Finished Jul 10 05:04:38 PM PDT 24
Peak memory 225436 kb
Host smart-c3d86738-89d1-495b-82d4-a8073568408e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432093693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_di
gest.432093693
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.331129145
Short name T450
Test name
Test status
Simulation time 1585659898 ps
CPU time 9.17 seconds
Started Jul 10 05:04:21 PM PDT 24
Finished Jul 10 05:04:33 PM PDT 24
Peak memory 225392 kb
Host smart-16533c20-0563-4989-bfc8-f079bdc3a10e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331129145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.331129145
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.2119529164
Short name T490
Test name
Test status
Simulation time 373145125 ps
CPU time 9.08 seconds
Started Jul 10 05:04:21 PM PDT 24
Finished Jul 10 05:04:33 PM PDT 24
Peak memory 217732 kb
Host smart-9397ec12-1b55-4fe2-9f07-512442960ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119529164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.2119529164
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.845776236
Short name T331
Test name
Test status
Simulation time 1525973422 ps
CPU time 11.23 seconds
Started Jul 10 05:04:23 PM PDT 24
Finished Jul 10 05:04:37 PM PDT 24
Peak memory 217084 kb
Host smart-7543f174-2192-4f6f-a2d0-efa21abaaaa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845776236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.845776236
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.1137229385
Short name T17
Test name
Test status
Simulation time 299962679 ps
CPU time 7.05 seconds
Started Jul 10 05:04:24 PM PDT 24
Finished Jul 10 05:04:34 PM PDT 24
Peak memory 250408 kb
Host smart-00fb871a-4b4e-40d9-acec-2e0f4eb07e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137229385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.1137229385
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.391357565
Short name T584
Test name
Test status
Simulation time 155900822080 ps
CPU time 296.69 seconds
Started Jul 10 05:04:21 PM PDT 24
Finished Jul 10 05:09:21 PM PDT 24
Peak memory 225500 kb
Host smart-875133bf-0ca9-4dbf-a0dd-250f0ba86cd4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391357565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.391357565
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.3137309376
Short name T377
Test name
Test status
Simulation time 13759528 ps
CPU time 0.83 seconds
Started Jul 10 05:04:20 PM PDT 24
Finished Jul 10 05:04:24 PM PDT 24
Peak memory 208244 kb
Host smart-a1ceeb46-b61c-4ae0-8d19-4e9f6a937df0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137309376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.3137309376
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.4160894222
Short name T775
Test name
Test status
Simulation time 65916032 ps
CPU time 1.43 seconds
Started Jul 10 05:04:27 PM PDT 24
Finished Jul 10 05:04:32 PM PDT 24
Peak memory 208464 kb
Host smart-b4fe076b-9c6e-4d82-9e34-b94994faf42a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160894222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.4160894222
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.1517708451
Short name T468
Test name
Test status
Simulation time 298661979 ps
CPU time 13.85 seconds
Started Jul 10 05:04:26 PM PDT 24
Finished Jul 10 05:04:43 PM PDT 24
Peak memory 217664 kb
Host smart-bde755c0-7116-42b9-83e2-d6f60830fcf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517708451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.1517708451
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.4224875203
Short name T415
Test name
Test status
Simulation time 774484038 ps
CPU time 4.25 seconds
Started Jul 10 05:04:27 PM PDT 24
Finished Jul 10 05:04:35 PM PDT 24
Peak memory 217072 kb
Host smart-5b1a30f3-3014-4f6c-ac6d-5dfaee2e23ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224875203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.4224875203
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.3178225918
Short name T595
Test name
Test status
Simulation time 70780144 ps
CPU time 3.88 seconds
Started Jul 10 05:04:21 PM PDT 24
Finished Jul 10 05:04:28 PM PDT 24
Peak memory 217644 kb
Host smart-b6952801-d029-42e4-aea4-084cc0f2f8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178225918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.3178225918
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.2271141952
Short name T571
Test name
Test status
Simulation time 252072973 ps
CPU time 12.83 seconds
Started Jul 10 05:04:26 PM PDT 24
Finished Jul 10 05:04:42 PM PDT 24
Peak memory 218308 kb
Host smart-c0765479-f9b0-497d-b301-e871f02772b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271141952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.2271141952
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.4235657217
Short name T300
Test name
Test status
Simulation time 1490018969 ps
CPU time 13.67 seconds
Started Jul 10 05:04:27 PM PDT 24
Finished Jul 10 05:04:44 PM PDT 24
Peak memory 225388 kb
Host smart-1ab8f5fa-d20e-4ceb-865c-457996cd36eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235657217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.4235657217
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.673791441
Short name T686
Test name
Test status
Simulation time 1098714205 ps
CPU time 10.44 seconds
Started Jul 10 05:04:28 PM PDT 24
Finished Jul 10 05:04:42 PM PDT 24
Peak memory 225396 kb
Host smart-45af8f6d-25bf-4da2-a581-a115ed6667eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673791441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.673791441
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.3924908331
Short name T371
Test name
Test status
Simulation time 3687063089 ps
CPU time 14.25 seconds
Started Jul 10 05:04:32 PM PDT 24
Finished Jul 10 05:04:48 PM PDT 24
Peak memory 225228 kb
Host smart-34adda41-d156-4feb-8976-acacb1c9a23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924908331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.3924908331
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.2257491702
Short name T88
Test name
Test status
Simulation time 283931645 ps
CPU time 4.1 seconds
Started Jul 10 05:04:24 PM PDT 24
Finished Jul 10 05:04:31 PM PDT 24
Peak memory 213684 kb
Host smart-34907857-6416-4962-9e66-dfa38e96345c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257491702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.2257491702
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.893160268
Short name T431
Test name
Test status
Simulation time 852032643 ps
CPU time 21.77 seconds
Started Jul 10 05:04:21 PM PDT 24
Finished Jul 10 05:04:46 PM PDT 24
Peak memory 250404 kb
Host smart-b375e2d7-e539-4460-82d0-7e34b022c456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893160268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.893160268
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.3159058261
Short name T190
Test name
Test status
Simulation time 361945686 ps
CPU time 3.37 seconds
Started Jul 10 05:04:21 PM PDT 24
Finished Jul 10 05:04:27 PM PDT 24
Peak memory 221704 kb
Host smart-76db9475-605c-4079-a856-2fa85c32d5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159058261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.3159058261
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.2995645973
Short name T458
Test name
Test status
Simulation time 11270071128 ps
CPU time 103.98 seconds
Started Jul 10 05:04:27 PM PDT 24
Finished Jul 10 05:06:14 PM PDT 24
Peak memory 270808 kb
Host smart-8e99189c-17de-42a8-addd-092a357c4308
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995645973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.2995645973
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.2408212516
Short name T600
Test name
Test status
Simulation time 29325314137 ps
CPU time 300.54 seconds
Started Jul 10 05:04:27 PM PDT 24
Finished Jul 10 05:09:31 PM PDT 24
Peak memory 331728 kb
Host smart-2e6895a3-e847-4d1c-9ede-60afcc76a3bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2408212516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.2408212516
Directory /workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.2510658346
Short name T295
Test name
Test status
Simulation time 15315631 ps
CPU time 1.11 seconds
Started Jul 10 05:04:21 PM PDT 24
Finished Jul 10 05:04:25 PM PDT 24
Peak memory 211368 kb
Host smart-fb4d4b44-1b96-4da9-9a0f-79535b23fb68
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510658346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.2510658346
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.3181064143
Short name T627
Test name
Test status
Simulation time 18280762 ps
CPU time 0.95 seconds
Started Jul 10 05:04:31 PM PDT 24
Finished Jul 10 05:04:35 PM PDT 24
Peak memory 208388 kb
Host smart-5d9c4fd4-5f07-43b6-a818-9c509337f073
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181064143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.3181064143
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.10080656
Short name T640
Test name
Test status
Simulation time 881882340 ps
CPU time 9.72 seconds
Started Jul 10 05:04:27 PM PDT 24
Finished Jul 10 05:04:41 PM PDT 24
Peak memory 225464 kb
Host smart-b0bf3508-8ae3-4e64-8da5-a6c869ddb54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10080656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.10080656
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.2429592226
Short name T533
Test name
Test status
Simulation time 4766548568 ps
CPU time 4.87 seconds
Started Jul 10 05:04:25 PM PDT 24
Finished Jul 10 05:04:34 PM PDT 24
Peak memory 217192 kb
Host smart-2d5df7da-44bc-4242-8100-f9be905362d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429592226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.2429592226
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.571796083
Short name T703
Test name
Test status
Simulation time 84941873 ps
CPU time 2.83 seconds
Started Jul 10 05:04:26 PM PDT 24
Finished Jul 10 05:04:32 PM PDT 24
Peak memory 217660 kb
Host smart-08e0cf08-d373-4932-b060-daa88850ae90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571796083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.571796083
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.1542042116
Short name T476
Test name
Test status
Simulation time 309218496 ps
CPU time 10.47 seconds
Started Jul 10 05:04:29 PM PDT 24
Finished Jul 10 05:04:43 PM PDT 24
Peak memory 225380 kb
Host smart-37d55d79-4f81-40b0-b1e9-c3e0172fbcee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542042116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.1542042116
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.2883907946
Short name T69
Test name
Test status
Simulation time 817602888 ps
CPU time 15.01 seconds
Started Jul 10 05:04:27 PM PDT 24
Finished Jul 10 05:04:46 PM PDT 24
Peak memory 217908 kb
Host smart-ded8a8ef-6c2e-41cb-b167-30e63bc250af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883907946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
2883907946
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.3553653317
Short name T363
Test name
Test status
Simulation time 363288178 ps
CPU time 9.07 seconds
Started Jul 10 05:04:27 PM PDT 24
Finished Jul 10 05:04:40 PM PDT 24
Peak memory 225752 kb
Host smart-e923af62-7cd4-45eb-9a4f-da59f3d00c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553653317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.3553653317
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.3939990485
Short name T183
Test name
Test status
Simulation time 86557366 ps
CPU time 1.98 seconds
Started Jul 10 05:04:27 PM PDT 24
Finished Jul 10 05:04:32 PM PDT 24
Peak memory 222508 kb
Host smart-bc18511d-e0e8-4e7f-a0c3-f3780183e265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939990485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.3939990485
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.3309194072
Short name T425
Test name
Test status
Simulation time 3869869542 ps
CPU time 34.07 seconds
Started Jul 10 05:04:31 PM PDT 24
Finished Jul 10 05:05:08 PM PDT 24
Peak memory 250476 kb
Host smart-307ddd9c-fc25-4c3c-91c1-e0e941d95ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309194072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.3309194072
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.2905193377
Short name T854
Test name
Test status
Simulation time 259115956 ps
CPU time 6.72 seconds
Started Jul 10 05:04:27 PM PDT 24
Finished Jul 10 05:04:37 PM PDT 24
Peak memory 249848 kb
Host smart-da9be16e-5e44-4405-adf2-a5df16958839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905193377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.2905193377
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.2122872323
Short name T496
Test name
Test status
Simulation time 977561685 ps
CPU time 49.42 seconds
Started Jul 10 05:04:28 PM PDT 24
Finished Jul 10 05:05:21 PM PDT 24
Peak memory 250344 kb
Host smart-a7f1b356-e840-4ec0-844b-141d3bf91560
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122872323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.2122872323
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.297455800
Short name T588
Test name
Test status
Simulation time 50079158 ps
CPU time 0.8 seconds
Started Jul 10 05:04:28 PM PDT 24
Finished Jul 10 05:04:32 PM PDT 24
Peak memory 208276 kb
Host smart-9ccd67d0-afd8-4fba-83dc-04cee5337ccd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297455800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ct
rl_volatile_unlock_smoke.297455800
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.172042368
Short name T615
Test name
Test status
Simulation time 33282816 ps
CPU time 0.88 seconds
Started Jul 10 05:04:34 PM PDT 24
Finished Jul 10 05:04:36 PM PDT 24
Peak memory 208432 kb
Host smart-abdb036d-5721-4d06-be88-b2074310b6e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172042368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.172042368
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.3652803601
Short name T655
Test name
Test status
Simulation time 871020586 ps
CPU time 11.53 seconds
Started Jul 10 05:04:29 PM PDT 24
Finished Jul 10 05:04:44 PM PDT 24
Peak memory 225456 kb
Host smart-d8da6ba2-cc89-4f56-9944-297403051179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652803601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.3652803601
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.3040076011
Short name T511
Test name
Test status
Simulation time 374912715 ps
CPU time 2.89 seconds
Started Jul 10 05:04:30 PM PDT 24
Finished Jul 10 05:04:36 PM PDT 24
Peak memory 217096 kb
Host smart-73027bbb-18cb-4d16-975e-b44351b520d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040076011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.3040076011
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.226669851
Short name T175
Test name
Test status
Simulation time 63282595 ps
CPU time 3.18 seconds
Started Jul 10 05:04:29 PM PDT 24
Finished Jul 10 05:04:35 PM PDT 24
Peak memory 217712 kb
Host smart-d69170c2-ecaa-4dbf-943c-26bb7ac1487b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226669851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.226669851
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.1286319010
Short name T706
Test name
Test status
Simulation time 571347577 ps
CPU time 11.81 seconds
Started Jul 10 05:04:26 PM PDT 24
Finished Jul 10 05:04:42 PM PDT 24
Peak memory 225368 kb
Host smart-17797a05-6e70-4e68-a67a-8575c92285a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286319010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.1286319010
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.3619653922
Short name T438
Test name
Test status
Simulation time 476573472 ps
CPU time 16.81 seconds
Started Jul 10 05:04:28 PM PDT 24
Finished Jul 10 05:04:48 PM PDT 24
Peak memory 217540 kb
Host smart-8adfce79-8785-4026-a3ca-4642fa5470be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619653922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
3619653922
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.4097444710
Short name T528
Test name
Test status
Simulation time 280713637 ps
CPU time 1.96 seconds
Started Jul 10 05:04:27 PM PDT 24
Finished Jul 10 05:04:33 PM PDT 24
Peak memory 221708 kb
Host smart-e047d672-42c7-4937-937f-2d7f287e00b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097444710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.4097444710
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.1762119785
Short name T579
Test name
Test status
Simulation time 864900466 ps
CPU time 25.26 seconds
Started Jul 10 05:04:28 PM PDT 24
Finished Jul 10 05:04:57 PM PDT 24
Peak memory 250468 kb
Host smart-c10a5493-aa59-42e6-8e69-6b998241a6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762119785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.1762119785
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.643865271
Short name T246
Test name
Test status
Simulation time 66594415 ps
CPU time 5.97 seconds
Started Jul 10 05:04:27 PM PDT 24
Finished Jul 10 05:04:36 PM PDT 24
Peak memory 246252 kb
Host smart-cf1f6d06-fff7-4784-a05a-b396eacdc3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643865271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.643865271
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.3967497891
Short name T580
Test name
Test status
Simulation time 6786970994 ps
CPU time 301.84 seconds
Started Jul 10 05:04:30 PM PDT 24
Finished Jul 10 05:09:35 PM PDT 24
Peak memory 250460 kb
Host smart-e0152a5f-fe00-405a-945c-0925697ee0cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967497891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.3967497891
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.4169242994
Short name T633
Test name
Test status
Simulation time 4933039186 ps
CPU time 130.6 seconds
Started Jul 10 05:04:35 PM PDT 24
Finished Jul 10 05:06:47 PM PDT 24
Peak memory 272368 kb
Host smart-a123048f-35b6-4e89-a38f-58062fedf976
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4169242994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.4169242994
Directory /workspace/39.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.3586873771
Short name T467
Test name
Test status
Simulation time 30802423 ps
CPU time 0.78 seconds
Started Jul 10 05:04:28 PM PDT 24
Finished Jul 10 05:04:32 PM PDT 24
Peak memory 208128 kb
Host smart-4b612ae9-cdea-4de7-adcd-56df013c1f00
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586873771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.3586873771
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.2570177086
Short name T758
Test name
Test status
Simulation time 15111053 ps
CPU time 0.84 seconds
Started Jul 10 05:01:50 PM PDT 24
Finished Jul 10 05:01:53 PM PDT 24
Peak memory 208284 kb
Host smart-ecb3dde2-9fad-4691-9a8d-491d1a65b426
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570177086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.2570177086
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.1131340932
Short name T715
Test name
Test status
Simulation time 21374497 ps
CPU time 0.91 seconds
Started Jul 10 05:01:41 PM PDT 24
Finished Jul 10 05:01:45 PM PDT 24
Peak memory 208644 kb
Host smart-fb0cb9b0-651b-456f-ac6b-7b77e8004af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131340932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.1131340932
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.4208467507
Short name T684
Test name
Test status
Simulation time 475518977 ps
CPU time 4.23 seconds
Started Jul 10 05:01:44 PM PDT 24
Finished Jul 10 05:01:51 PM PDT 24
Peak memory 217076 kb
Host smart-0ee267f0-383e-4f8c-a2f4-6012df0de37f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208467507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.4208467507
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.524339058
Short name T191
Test name
Test status
Simulation time 7271108284 ps
CPU time 28.96 seconds
Started Jul 10 05:01:42 PM PDT 24
Finished Jul 10 05:02:15 PM PDT 24
Peak memory 218116 kb
Host smart-29ae95ce-a29d-4c52-9efb-2df447ae8ec9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524339058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_err
ors.524339058
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.83896
Short name T707
Test name
Test status
Simulation time 2310886068 ps
CPU time 15.36 seconds
Started Jul 10 05:01:43 PM PDT 24
Finished Jul 10 05:02:02 PM PDT 24
Peak memory 217256 kb
Host smart-9280d22d-af31-4381-b49a-c0ce6c3c47c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.83896
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.2216635995
Short name T651
Test name
Test status
Simulation time 455291670 ps
CPU time 7.9 seconds
Started Jul 10 05:01:42 PM PDT 24
Finished Jul 10 05:01:53 PM PDT 24
Peak memory 217844 kb
Host smart-cce807ca-ef13-4da7-8793-352183465ac9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216635995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.2216635995
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.3053954479
Short name T337
Test name
Test status
Simulation time 1296789751 ps
CPU time 21.4 seconds
Started Jul 10 05:01:41 PM PDT 24
Finished Jul 10 05:02:05 PM PDT 24
Peak memory 216992 kb
Host smart-7422ce6a-8cd7-4115-8dce-001902007942
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053954479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.3053954479
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.130035274
Short name T84
Test name
Test status
Simulation time 1193341183 ps
CPU time 9.21 seconds
Started Jul 10 05:01:47 PM PDT 24
Finished Jul 10 05:01:58 PM PDT 24
Peak memory 217056 kb
Host smart-5cee771b-9cc8-4a01-9891-2d8c83fd1004
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130035274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.130035274
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.4231355947
Short name T622
Test name
Test status
Simulation time 6570224909 ps
CPU time 37.1 seconds
Started Jul 10 05:01:42 PM PDT 24
Finished Jul 10 05:02:22 PM PDT 24
Peak memory 250416 kb
Host smart-60ded674-621c-4c65-9a82-c89a6e79ba00
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231355947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.4231355947
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.2897005289
Short name T460
Test name
Test status
Simulation time 1380122325 ps
CPU time 10.49 seconds
Started Jul 10 05:01:42 PM PDT 24
Finished Jul 10 05:01:55 PM PDT 24
Peak memory 249884 kb
Host smart-9cbce067-2bac-47a6-bb80-40ddc262245d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897005289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.2897005289
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.1985399731
Short name T728
Test name
Test status
Simulation time 45199928 ps
CPU time 2.02 seconds
Started Jul 10 05:01:42 PM PDT 24
Finished Jul 10 05:01:47 PM PDT 24
Peak memory 221692 kb
Host smart-6e733a17-a9c2-49e3-a98b-2a340bba601b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985399731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.1985399731
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.1613506787
Short name T700
Test name
Test status
Simulation time 1382619700 ps
CPU time 13.36 seconds
Started Jul 10 05:01:44 PM PDT 24
Finished Jul 10 05:02:00 PM PDT 24
Peak memory 214176 kb
Host smart-f2c2ba92-c51c-4ea1-9169-8d3b1479eb71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613506787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.1613506787
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.2526236683
Short name T60
Test name
Test status
Simulation time 907968977 ps
CPU time 40.59 seconds
Started Jul 10 05:01:52 PM PDT 24
Finished Jul 10 05:02:34 PM PDT 24
Peak memory 283544 kb
Host smart-12a0ed82-9c71-486e-9724-35781e631c8d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526236683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.2526236683
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.415602241
Short name T510
Test name
Test status
Simulation time 1453827052 ps
CPU time 16.74 seconds
Started Jul 10 05:01:46 PM PDT 24
Finished Jul 10 05:02:05 PM PDT 24
Peak memory 218476 kb
Host smart-33725f1b-b596-4bf7-bda2-86525634ceaa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415602241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.415602241
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.3169041313
Short name T856
Test name
Test status
Simulation time 909804091 ps
CPU time 9.62 seconds
Started Jul 10 05:01:49 PM PDT 24
Finished Jul 10 05:02:00 PM PDT 24
Peak memory 225380 kb
Host smart-bca41537-c74e-4979-bcd9-f0c77e1654cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169041313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.3169041313
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.678871826
Short name T782
Test name
Test status
Simulation time 770246677 ps
CPU time 7.4 seconds
Started Jul 10 05:01:44 PM PDT 24
Finished Jul 10 05:01:54 PM PDT 24
Peak memory 225396 kb
Host smart-3222f32d-ec47-4679-8898-a4eb10982ed2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678871826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.678871826
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.2256653140
Short name T626
Test name
Test status
Simulation time 342884378 ps
CPU time 11.87 seconds
Started Jul 10 05:01:44 PM PDT 24
Finished Jul 10 05:01:58 PM PDT 24
Peak memory 225464 kb
Host smart-f5330793-084a-42d7-bfaf-0a6b22c3cee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256653140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.2256653140
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.620630537
Short name T406
Test name
Test status
Simulation time 23822097 ps
CPU time 1.32 seconds
Started Jul 10 05:01:43 PM PDT 24
Finished Jul 10 05:01:48 PM PDT 24
Peak memory 217068 kb
Host smart-4dd9b415-60f2-46eb-afe9-0a6d66a5f38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620630537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.620630537
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.25722249
Short name T245
Test name
Test status
Simulation time 247093108 ps
CPU time 34.1 seconds
Started Jul 10 05:01:40 PM PDT 24
Finished Jul 10 05:02:17 PM PDT 24
Peak memory 250396 kb
Host smart-5071405e-8def-4501-822d-67ee9eb2b5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25722249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.25722249
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.3045875785
Short name T434
Test name
Test status
Simulation time 141450062 ps
CPU time 7.29 seconds
Started Jul 10 05:01:41 PM PDT 24
Finished Jul 10 05:01:51 PM PDT 24
Peak memory 250300 kb
Host smart-a638f267-f564-43b5-9a58-960dccf4e093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045875785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.3045875785
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.399975506
Short name T64
Test name
Test status
Simulation time 4530975105 ps
CPU time 107.04 seconds
Started Jul 10 05:01:50 PM PDT 24
Finished Jul 10 05:03:40 PM PDT 24
Peak memory 283268 kb
Host smart-382a6e0c-b4cc-4099-9eac-8a3d05c42c74
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399975506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.399975506
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.905142315
Short name T95
Test name
Test status
Simulation time 20851716 ps
CPU time 1.01 seconds
Started Jul 10 05:01:42 PM PDT 24
Finished Jul 10 05:01:46 PM PDT 24
Peak memory 211268 kb
Host smart-8bb763fe-7ac5-41f1-9514-23612f239e58
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905142315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctr
l_volatile_unlock_smoke.905142315
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.1561043292
Short name T299
Test name
Test status
Simulation time 87266323 ps
CPU time 1.17 seconds
Started Jul 10 05:04:36 PM PDT 24
Finished Jul 10 05:04:39 PM PDT 24
Peak memory 208436 kb
Host smart-127f4cf3-d0fb-44d4-8e13-3d4ada36d824
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561043292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.1561043292
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.391082276
Short name T305
Test name
Test status
Simulation time 289931089 ps
CPU time 9.95 seconds
Started Jul 10 05:04:36 PM PDT 24
Finished Jul 10 05:04:48 PM PDT 24
Peak memory 217664 kb
Host smart-111f5678-403c-41b4-8407-abcbee4145ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391082276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.391082276
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.1241866422
Short name T297
Test name
Test status
Simulation time 1767235645 ps
CPU time 11.51 seconds
Started Jul 10 05:04:34 PM PDT 24
Finished Jul 10 05:04:48 PM PDT 24
Peak memory 217088 kb
Host smart-61c35c6b-7583-49b4-8087-c77c87ec5bc8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241866422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.1241866422
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.4246995416
Short name T237
Test name
Test status
Simulation time 98605024 ps
CPU time 2.78 seconds
Started Jul 10 05:04:34 PM PDT 24
Finished Jul 10 05:04:39 PM PDT 24
Peak memory 217660 kb
Host smart-ca1d49ce-b09c-4f46-81da-21a894662fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246995416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.4246995416
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.2574121254
Short name T451
Test name
Test status
Simulation time 259402762 ps
CPU time 9.1 seconds
Started Jul 10 05:04:37 PM PDT 24
Finished Jul 10 05:04:48 PM PDT 24
Peak memory 218360 kb
Host smart-517b432d-177d-45c1-bbe9-a9fec664c34f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574121254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.2574121254
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.582161448
Short name T487
Test name
Test status
Simulation time 2119069654 ps
CPU time 14.78 seconds
Started Jul 10 05:04:35 PM PDT 24
Finished Jul 10 05:04:52 PM PDT 24
Peak memory 225428 kb
Host smart-1ecf7782-ee3a-43a6-960b-6ca55494e360
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582161448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_di
gest.582161448
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.1960547267
Short name T759
Test name
Test status
Simulation time 345061546 ps
CPU time 11.93 seconds
Started Jul 10 05:04:35 PM PDT 24
Finished Jul 10 05:04:49 PM PDT 24
Peak memory 217608 kb
Host smart-341cd963-5a90-413a-bcbb-80f3475401c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960547267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
1960547267
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.495116820
Short name T795
Test name
Test status
Simulation time 755895155 ps
CPU time 9.83 seconds
Started Jul 10 05:04:37 PM PDT 24
Finished Jul 10 05:04:49 PM PDT 24
Peak memory 224820 kb
Host smart-2e8dcde2-2206-4cf6-9c56-ea77ed281e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495116820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.495116820
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.3444196848
Short name T361
Test name
Test status
Simulation time 132075968 ps
CPU time 2.66 seconds
Started Jul 10 05:04:34 PM PDT 24
Finished Jul 10 05:04:38 PM PDT 24
Peak memory 214380 kb
Host smart-4ccf6065-3d40-46d7-a224-5ef5f450c63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444196848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.3444196848
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.3355757818
Short name T455
Test name
Test status
Simulation time 825183541 ps
CPU time 28.31 seconds
Started Jul 10 05:04:35 PM PDT 24
Finished Jul 10 05:05:06 PM PDT 24
Peak memory 250412 kb
Host smart-a60ce443-ba6b-421a-9a47-eac1484f411c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355757818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.3355757818
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.90924023
Short name T737
Test name
Test status
Simulation time 46641493 ps
CPU time 6.57 seconds
Started Jul 10 05:04:35 PM PDT 24
Finished Jul 10 05:04:43 PM PDT 24
Peak memory 248128 kb
Host smart-ab365081-d9c0-44ea-b073-1bd885c03b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90924023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.90924023
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.1064514825
Short name T609
Test name
Test status
Simulation time 10915112553 ps
CPU time 175.25 seconds
Started Jul 10 05:04:38 PM PDT 24
Finished Jul 10 05:07:35 PM PDT 24
Peak memory 250456 kb
Host smart-0480ef6a-1103-44b2-88e1-73819e09ba40
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064514825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.1064514825
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.873461093
Short name T561
Test name
Test status
Simulation time 87214836860 ps
CPU time 850.28 seconds
Started Jul 10 05:04:34 PM PDT 24
Finished Jul 10 05:18:46 PM PDT 24
Peak memory 316084 kb
Host smart-8f0d5dc2-a166-4aa4-93d2-da126928763b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=873461093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all_with_rand_reset.873461093
Directory /workspace/40.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.3968023174
Short name T733
Test name
Test status
Simulation time 14464990 ps
CPU time 0.83 seconds
Started Jul 10 05:04:36 PM PDT 24
Finished Jul 10 05:04:39 PM PDT 24
Peak memory 208212 kb
Host smart-a95813f6-a0bb-498c-a38b-38bd71e01f4f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968023174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.3968023174
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.3751737170
Short name T481
Test name
Test status
Simulation time 21086870 ps
CPU time 1.03 seconds
Started Jul 10 05:04:36 PM PDT 24
Finished Jul 10 05:04:39 PM PDT 24
Peak memory 208392 kb
Host smart-9a467be6-142d-486e-80c5-a6aec2d94b2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751737170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.3751737170
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.1744697397
Short name T541
Test name
Test status
Simulation time 1169402032 ps
CPU time 9.8 seconds
Started Jul 10 05:04:37 PM PDT 24
Finished Jul 10 05:04:50 PM PDT 24
Peak memory 217784 kb
Host smart-a5fccdcf-e607-49c3-b392-f472c864bfd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744697397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.1744697397
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.2345729468
Short name T784
Test name
Test status
Simulation time 79279290 ps
CPU time 1.51 seconds
Started Jul 10 05:04:34 PM PDT 24
Finished Jul 10 05:04:38 PM PDT 24
Peak memory 216468 kb
Host smart-bb09159f-f960-437d-9bb7-dd26f85abe76
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345729468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.2345729468
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.3127870128
Short name T435
Test name
Test status
Simulation time 76744198 ps
CPU time 2.67 seconds
Started Jul 10 05:04:35 PM PDT 24
Finished Jul 10 05:04:40 PM PDT 24
Peak memory 217660 kb
Host smart-0d2cbe96-bcc8-4ed3-96f9-2b5ef79b6920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127870128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.3127870128
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.4235094978
Short name T522
Test name
Test status
Simulation time 564021202 ps
CPU time 13.82 seconds
Started Jul 10 05:04:36 PM PDT 24
Finished Jul 10 05:04:52 PM PDT 24
Peak memory 218308 kb
Host smart-0c99318a-4d68-4c4f-8754-0cd6e9743734
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235094978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.4235094978
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.3766828544
Short name T674
Test name
Test status
Simulation time 610905722 ps
CPU time 10.67 seconds
Started Jul 10 05:04:37 PM PDT 24
Finished Jul 10 05:04:49 PM PDT 24
Peak memory 224868 kb
Host smart-1e51c3f5-d2b4-4748-8e39-b473c30ac73c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766828544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.3766828544
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.4134743633
Short name T334
Test name
Test status
Simulation time 262291156 ps
CPU time 7.14 seconds
Started Jul 10 05:04:37 PM PDT 24
Finished Jul 10 05:04:47 PM PDT 24
Peak memory 217612 kb
Host smart-63cb0240-bb58-4090-82e1-9e2125f3f592
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134743633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
4134743633
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.2359045795
Short name T858
Test name
Test status
Simulation time 787222894 ps
CPU time 15.22 seconds
Started Jul 10 05:04:34 PM PDT 24
Finished Jul 10 05:04:51 PM PDT 24
Peak memory 225496 kb
Host smart-5d28bbc9-323e-4f75-9cf1-e0d85c1969fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359045795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.2359045795
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.4269901103
Short name T34
Test name
Test status
Simulation time 375886184 ps
CPU time 6 seconds
Started Jul 10 05:04:35 PM PDT 24
Finished Jul 10 05:04:43 PM PDT 24
Peak memory 217188 kb
Host smart-be7b1fc2-bf5c-4b19-b7e4-1c369fbde3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269901103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.4269901103
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.2051088293
Short name T769
Test name
Test status
Simulation time 994226565 ps
CPU time 24.31 seconds
Started Jul 10 05:04:35 PM PDT 24
Finished Jul 10 05:05:02 PM PDT 24
Peak memory 246720 kb
Host smart-c53123de-3c50-4623-a3f5-92282f50aceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051088293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.2051088293
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.210546541
Short name T374
Test name
Test status
Simulation time 180849731 ps
CPU time 6.58 seconds
Started Jul 10 05:04:37 PM PDT 24
Finished Jul 10 05:04:46 PM PDT 24
Peak memory 246436 kb
Host smart-a81b5d02-ada6-444d-88d7-90f44f18524a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210546541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.210546541
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.2802215580
Short name T566
Test name
Test status
Simulation time 35112510386 ps
CPU time 191.36 seconds
Started Jul 10 05:04:37 PM PDT 24
Finished Jul 10 05:07:51 PM PDT 24
Peak memory 265832 kb
Host smart-a1323583-bac2-4339-9a4a-6e64a66e88f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802215580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.2802215580
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.1709510915
Short name T39
Test name
Test status
Simulation time 45383775 ps
CPU time 0.85 seconds
Started Jul 10 05:04:34 PM PDT 24
Finished Jul 10 05:04:36 PM PDT 24
Peak memory 208516 kb
Host smart-eb7bba72-ca12-43ce-ae93-02d5967bd498
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709510915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.1709510915
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.79102159
Short name T555
Test name
Test status
Simulation time 32462616 ps
CPU time 1.09 seconds
Started Jul 10 05:04:52 PM PDT 24
Finished Jul 10 05:04:55 PM PDT 24
Peak memory 208500 kb
Host smart-31432ba5-12d7-4c05-8cde-44bf07e75b88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79102159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.79102159
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.1687565096
Short name T736
Test name
Test status
Simulation time 905204750 ps
CPU time 9.21 seconds
Started Jul 10 05:04:55 PM PDT 24
Finished Jul 10 05:05:06 PM PDT 24
Peak memory 217644 kb
Host smart-7a403c0d-7c11-4b90-b337-80a7fd2f93a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687565096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.1687565096
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.2357841147
Short name T639
Test name
Test status
Simulation time 2697494929 ps
CPU time 10.22 seconds
Started Jul 10 05:04:51 PM PDT 24
Finished Jul 10 05:05:04 PM PDT 24
Peak memory 217180 kb
Host smart-fff85acc-360e-4daa-9c1e-a4c7b1be3cf4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357841147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.2357841147
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.1128337621
Short name T844
Test name
Test status
Simulation time 176410585 ps
CPU time 2.09 seconds
Started Jul 10 05:04:51 PM PDT 24
Finished Jul 10 05:04:56 PM PDT 24
Peak memory 217696 kb
Host smart-53e96374-0bbb-4de5-af7e-ec63e342e9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128337621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.1128337621
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.3257522009
Short name T351
Test name
Test status
Simulation time 405284512 ps
CPU time 13.49 seconds
Started Jul 10 05:04:51 PM PDT 24
Finished Jul 10 05:05:07 PM PDT 24
Peak memory 218304 kb
Host smart-f00e625b-7489-4490-87c2-64f5ae0e44b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257522009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.3257522009
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.1705741505
Short name T188
Test name
Test status
Simulation time 6162771968 ps
CPU time 20.4 seconds
Started Jul 10 05:04:50 PM PDT 24
Finished Jul 10 05:05:12 PM PDT 24
Peak memory 225524 kb
Host smart-b26a7e62-5d43-467f-a8ad-2b08ac2e5589
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705741505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.1705741505
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.2640391323
Short name T764
Test name
Test status
Simulation time 350566825 ps
CPU time 9.69 seconds
Started Jul 10 05:04:53 PM PDT 24
Finished Jul 10 05:05:05 PM PDT 24
Peak memory 217596 kb
Host smart-01f05da5-4c61-44b9-95cd-5e2fb729e4da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640391323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
2640391323
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.1710565919
Short name T119
Test name
Test status
Simulation time 355800712 ps
CPU time 6.29 seconds
Started Jul 10 05:04:53 PM PDT 24
Finished Jul 10 05:05:01 PM PDT 24
Peak memory 224580 kb
Host smart-02795ea2-fa69-4522-8076-dbf274fa929e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710565919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.1710565919
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.1611795041
Short name T589
Test name
Test status
Simulation time 37690637 ps
CPU time 2.13 seconds
Started Jul 10 05:04:34 PM PDT 24
Finished Jul 10 05:04:38 PM PDT 24
Peak memory 217072 kb
Host smart-3126c99d-19d1-4044-a7b4-1195d2482914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611795041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.1611795041
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.3326317110
Short name T452
Test name
Test status
Simulation time 690766752 ps
CPU time 19.66 seconds
Started Jul 10 05:04:54 PM PDT 24
Finished Jul 10 05:05:15 PM PDT 24
Peak memory 250404 kb
Host smart-35e08514-e591-44d5-9a2b-86715fdc007f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326317110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.3326317110
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.1916891270
Short name T123
Test name
Test status
Simulation time 161677256 ps
CPU time 6.68 seconds
Started Jul 10 05:04:54 PM PDT 24
Finished Jul 10 05:05:02 PM PDT 24
Peak memory 246536 kb
Host smart-2e169823-47fa-4034-89eb-20c6748ef1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916891270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.1916891270
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.616380447
Short name T263
Test name
Test status
Simulation time 14555517658 ps
CPU time 154.06 seconds
Started Jul 10 05:04:51 PM PDT 24
Finished Jul 10 05:07:27 PM PDT 24
Peak memory 445628 kb
Host smart-ab14219a-3811-4ccc-915d-f8768d3e66bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616380447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.616380447
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.595809893
Short name T53
Test name
Test status
Simulation time 223616656117 ps
CPU time 1278.63 seconds
Started Jul 10 05:04:51 PM PDT 24
Finished Jul 10 05:26:12 PM PDT 24
Peak memory 421572 kb
Host smart-55e362f5-ed78-4af3-aa99-7ece535c7d2b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=595809893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.595809893
Directory /workspace/42.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.288813719
Short name T802
Test name
Test status
Simulation time 16817643 ps
CPU time 0.75 seconds
Started Jul 10 05:04:51 PM PDT 24
Finished Jul 10 05:04:54 PM PDT 24
Peak memory 208152 kb
Host smart-678e74bf-a122-458c-a2f5-2994b966d6e7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288813719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ct
rl_volatile_unlock_smoke.288813719
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.2241114894
Short name T842
Test name
Test status
Simulation time 28588001 ps
CPU time 0.88 seconds
Started Jul 10 05:05:06 PM PDT 24
Finished Jul 10 05:05:12 PM PDT 24
Peak memory 208484 kb
Host smart-45b8414c-88ec-4bca-ae8f-f8aa4846e559
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241114894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.2241114894
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.4290653905
Short name T531
Test name
Test status
Simulation time 299200328 ps
CPU time 10.16 seconds
Started Jul 10 05:04:50 PM PDT 24
Finished Jul 10 05:05:01 PM PDT 24
Peak memory 217664 kb
Host smart-af9be1d9-a2a8-4500-abe4-2a2cb5810f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290653905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.4290653905
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.1421117323
Short name T744
Test name
Test status
Simulation time 1518401463 ps
CPU time 5.49 seconds
Started Jul 10 05:04:53 PM PDT 24
Finished Jul 10 05:05:00 PM PDT 24
Peak memory 216848 kb
Host smart-3196feb3-a0de-4664-a9d9-5359cc3e8b77
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421117323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.1421117323
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.497605605
Short name T367
Test name
Test status
Simulation time 481585561 ps
CPU time 3.64 seconds
Started Jul 10 05:04:51 PM PDT 24
Finished Jul 10 05:04:57 PM PDT 24
Peak memory 217652 kb
Host smart-891630bf-af47-4d76-aa65-529d552267c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497605605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.497605605
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.42953487
Short name T559
Test name
Test status
Simulation time 6140814641 ps
CPU time 15.07 seconds
Started Jul 10 05:04:55 PM PDT 24
Finished Jul 10 05:05:11 PM PDT 24
Peak memory 225508 kb
Host smart-678b80b1-c2ef-4e4b-a560-f942646218e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42953487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.42953487
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.3799811529
Short name T360
Test name
Test status
Simulation time 3213325738 ps
CPU time 10.26 seconds
Started Jul 10 05:04:56 PM PDT 24
Finished Jul 10 05:05:08 PM PDT 24
Peak memory 225444 kb
Host smart-2d659668-4586-4efb-b8a8-44e7f83f92ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799811529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.3799811529
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.2689983840
Short name T576
Test name
Test status
Simulation time 1934133508 ps
CPU time 17.79 seconds
Started Jul 10 05:04:51 PM PDT 24
Finished Jul 10 05:05:10 PM PDT 24
Peak memory 217616 kb
Host smart-3a2aa9b0-3f22-4b9a-a2a1-f21cb91d0582
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689983840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
2689983840
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.3022475981
Short name T19
Test name
Test status
Simulation time 166664561 ps
CPU time 7.27 seconds
Started Jul 10 05:04:52 PM PDT 24
Finished Jul 10 05:05:01 PM PDT 24
Peak memory 224192 kb
Host smart-f40dddf9-6c6c-42ce-98a9-d446c3dd3d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022475981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.3022475981
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.3726400227
Short name T90
Test name
Test status
Simulation time 245941398 ps
CPU time 4.36 seconds
Started Jul 10 05:04:52 PM PDT 24
Finished Jul 10 05:04:58 PM PDT 24
Peak memory 217056 kb
Host smart-990cef00-75af-408e-b2ae-ec233af7755b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726400227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.3726400227
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.11474326
Short name T542
Test name
Test status
Simulation time 300915365 ps
CPU time 30.54 seconds
Started Jul 10 05:04:50 PM PDT 24
Finished Jul 10 05:05:23 PM PDT 24
Peak memory 250400 kb
Host smart-2c44efa5-e97c-4008-82b4-c823aa71b476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11474326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.11474326
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.3569332206
Short name T649
Test name
Test status
Simulation time 62932942 ps
CPU time 3.81 seconds
Started Jul 10 05:04:52 PM PDT 24
Finished Jul 10 05:04:58 PM PDT 24
Peak memory 222228 kb
Host smart-14586110-1c62-4f2d-8f8a-cd9fb61a5028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569332206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.3569332206
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.3801309999
Short name T121
Test name
Test status
Simulation time 18634486801 ps
CPU time 126.4 seconds
Started Jul 10 05:04:55 PM PDT 24
Finished Jul 10 05:07:03 PM PDT 24
Peak memory 283212 kb
Host smart-4d506023-a618-4a98-88f3-d1829f70a02c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801309999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.3801309999
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.2791168780
Short name T65
Test name
Test status
Simulation time 36638037481 ps
CPU time 702.68 seconds
Started Jul 10 05:04:50 PM PDT 24
Finished Jul 10 05:16:34 PM PDT 24
Peak memory 267820 kb
Host smart-8bea19b0-8aa9-465e-9c45-2afb7e9666ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2791168780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.2791168780
Directory /workspace/43.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.2701572066
Short name T692
Test name
Test status
Simulation time 20716975 ps
CPU time 0.78 seconds
Started Jul 10 05:04:50 PM PDT 24
Finished Jul 10 05:04:52 PM PDT 24
Peak memory 208332 kb
Host smart-3a509600-2671-486b-868d-315d604f7b1b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701572066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.2701572066
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.420156120
Short name T15
Test name
Test status
Simulation time 17631918 ps
CPU time 1.14 seconds
Started Jul 10 05:05:04 PM PDT 24
Finished Jul 10 05:05:10 PM PDT 24
Peak memory 208376 kb
Host smart-8c6c0a65-6b48-42e4-b241-f73709a9dc17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420156120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.420156120
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.2003900724
Short name T54
Test name
Test status
Simulation time 215569212 ps
CPU time 8.37 seconds
Started Jul 10 05:05:04 PM PDT 24
Finished Jul 10 05:05:18 PM PDT 24
Peak memory 217664 kb
Host smart-fc8c396b-e36a-48db-bbb1-b387332d0fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003900724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.2003900724
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.1083445540
Short name T524
Test name
Test status
Simulation time 966190119 ps
CPU time 4.09 seconds
Started Jul 10 05:05:04 PM PDT 24
Finished Jul 10 05:05:13 PM PDT 24
Peak memory 216576 kb
Host smart-e633644f-cc79-403f-b92a-ca52a74e6f6a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083445540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.1083445540
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.731352837
Short name T509
Test name
Test status
Simulation time 49858397 ps
CPU time 1.39 seconds
Started Jul 10 05:05:06 PM PDT 24
Finished Jul 10 05:05:13 PM PDT 24
Peak memory 217648 kb
Host smart-731f5c85-d9ea-4812-a97d-a75adcf51022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731352837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.731352837
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.416219200
Short name T682
Test name
Test status
Simulation time 519842704 ps
CPU time 10.12 seconds
Started Jul 10 05:05:05 PM PDT 24
Finished Jul 10 05:05:20 PM PDT 24
Peak memory 225500 kb
Host smart-4697e6ab-801a-4cf2-82ee-6efda81719a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416219200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.416219200
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.4017850425
Short name T107
Test name
Test status
Simulation time 397998816 ps
CPU time 11.36 seconds
Started Jul 10 05:05:04 PM PDT 24
Finished Jul 10 05:05:19 PM PDT 24
Peak memory 217700 kb
Host smart-895fdefc-2b56-4a42-9725-c85c056cce74
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017850425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.4017850425
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.1201012797
Short name T429
Test name
Test status
Simulation time 2503693950 ps
CPU time 7.49 seconds
Started Jul 10 05:05:04 PM PDT 24
Finished Jul 10 05:05:16 PM PDT 24
Peak memory 217908 kb
Host smart-564d7158-8084-4a5f-9e20-0b6fcb27276a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201012797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
1201012797
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.3080138308
Short name T646
Test name
Test status
Simulation time 394552136 ps
CPU time 12.35 seconds
Started Jul 10 05:05:06 PM PDT 24
Finished Jul 10 05:05:24 PM PDT 24
Peak memory 224908 kb
Host smart-00cb4ff9-b43a-490f-b179-c8cfecfed79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080138308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.3080138308
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.253231046
Short name T379
Test name
Test status
Simulation time 91972049 ps
CPU time 5.87 seconds
Started Jul 10 05:05:03 PM PDT 24
Finished Jul 10 05:05:13 PM PDT 24
Peak memory 217080 kb
Host smart-b8cbd6f8-f70b-45c2-bdb9-5bfa4fa94b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253231046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.253231046
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.4232371629
Short name T395
Test name
Test status
Simulation time 332836563 ps
CPU time 26.37 seconds
Started Jul 10 05:05:04 PM PDT 24
Finished Jul 10 05:05:36 PM PDT 24
Peak memory 250380 kb
Host smart-b9f68c61-1e9a-459f-ab20-4132ad6b6654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232371629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.4232371629
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.584156014
Short name T459
Test name
Test status
Simulation time 68847832 ps
CPU time 7.92 seconds
Started Jul 10 05:05:02 PM PDT 24
Finished Jul 10 05:05:12 PM PDT 24
Peak memory 250460 kb
Host smart-334010e9-b462-4ca9-8dd2-c2cf9421bc1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584156014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.584156014
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.299747667
Short name T696
Test name
Test status
Simulation time 19888981107 ps
CPU time 80.86 seconds
Started Jul 10 05:05:05 PM PDT 24
Finished Jul 10 05:06:31 PM PDT 24
Peak memory 271588 kb
Host smart-e66ab01d-b2e2-4ce3-ae16-5685b793ca9f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299747667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.299747667
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.3737871364
Short name T339
Test name
Test status
Simulation time 51969455 ps
CPU time 0.88 seconds
Started Jul 10 05:05:04 PM PDT 24
Finished Jul 10 05:05:10 PM PDT 24
Peak memory 208292 kb
Host smart-c46e7b68-c655-4848-a3f8-25a8754a66c5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737871364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.3737871364
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.2860773439
Short name T729
Test name
Test status
Simulation time 44297947 ps
CPU time 0.98 seconds
Started Jul 10 05:05:07 PM PDT 24
Finished Jul 10 05:05:13 PM PDT 24
Peak memory 208404 kb
Host smart-95feb024-af6f-4e8e-a424-4d3f8ea0060f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860773439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.2860773439
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.1481416930
Short name T391
Test name
Test status
Simulation time 1443354343 ps
CPU time 12.87 seconds
Started Jul 10 05:05:06 PM PDT 24
Finished Jul 10 05:05:24 PM PDT 24
Peak memory 217752 kb
Host smart-5a622869-611d-49f5-aec8-f8c847424dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481416930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.1481416930
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.893424328
Short name T794
Test name
Test status
Simulation time 623456738 ps
CPU time 3.9 seconds
Started Jul 10 05:05:04 PM PDT 24
Finished Jul 10 05:05:13 PM PDT 24
Peak memory 216644 kb
Host smart-4ae400d2-2782-4120-acf3-bac1655d6fb9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893424328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.893424328
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.3514472050
Short name T402
Test name
Test status
Simulation time 100972994 ps
CPU time 2.17 seconds
Started Jul 10 05:05:04 PM PDT 24
Finished Jul 10 05:05:12 PM PDT 24
Peak memory 217660 kb
Host smart-2bb118df-bbd5-4be0-b4c5-19ed11adc4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514472050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.3514472050
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.1186425087
Short name T662
Test name
Test status
Simulation time 215152907 ps
CPU time 10.92 seconds
Started Jul 10 05:05:06 PM PDT 24
Finished Jul 10 05:05:22 PM PDT 24
Peak memory 217916 kb
Host smart-73f03ce0-a9b9-4b63-a1f4-f697cc212bc5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186425087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.1186425087
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.1110499328
Short name T177
Test name
Test status
Simulation time 420713515 ps
CPU time 15.29 seconds
Started Jul 10 05:05:05 PM PDT 24
Finished Jul 10 05:05:25 PM PDT 24
Peak memory 225392 kb
Host smart-2370f735-47f9-48b3-ae87-62d5c58742ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110499328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
1110499328
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.2676433017
Short name T743
Test name
Test status
Simulation time 3064847836 ps
CPU time 6.7 seconds
Started Jul 10 05:05:07 PM PDT 24
Finished Jul 10 05:05:19 PM PDT 24
Peak memory 225816 kb
Host smart-99be2a52-a8c9-45c1-84e8-a24b14131d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676433017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.2676433017
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.4205097131
Short name T766
Test name
Test status
Simulation time 17722668 ps
CPU time 1.55 seconds
Started Jul 10 05:05:03 PM PDT 24
Finished Jul 10 05:05:09 PM PDT 24
Peak memory 213280 kb
Host smart-640fc13b-46ad-4130-9ac8-57a97be55311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205097131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.4205097131
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.4224078671
Short name T461
Test name
Test status
Simulation time 168376348 ps
CPU time 21.48 seconds
Started Jul 10 05:05:05 PM PDT 24
Finished Jul 10 05:05:31 PM PDT 24
Peak memory 243740 kb
Host smart-6e230207-4900-4b44-92ae-ce269125939e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224078671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.4224078671
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.941697318
Short name T575
Test name
Test status
Simulation time 50189417 ps
CPU time 3.23 seconds
Started Jul 10 05:05:02 PM PDT 24
Finished Jul 10 05:05:07 PM PDT 24
Peak memory 217656 kb
Host smart-d5999900-6782-41ea-b284-5ac54454e7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941697318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.941697318
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.275069743
Short name T195
Test name
Test status
Simulation time 7873826053 ps
CPU time 257.11 seconds
Started Jul 10 05:05:03 PM PDT 24
Finished Jul 10 05:09:25 PM PDT 24
Peak memory 266860 kb
Host smart-60fed7e4-27a3-4642-b1e7-5a531d5a728d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275069743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.275069743
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.3831875901
Short name T43
Test name
Test status
Simulation time 191068562050 ps
CPU time 1036.39 seconds
Started Jul 10 05:05:03 PM PDT 24
Finished Jul 10 05:22:24 PM PDT 24
Peak memory 283372 kb
Host smart-c627342e-c9db-4c46-94ca-0373cd84ef2c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3831875901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all_with_rand_reset.3831875901
Directory /workspace/45.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.3525583605
Short name T14
Test name
Test status
Simulation time 18852580 ps
CPU time 0.76 seconds
Started Jul 10 05:05:06 PM PDT 24
Finished Jul 10 05:05:12 PM PDT 24
Peak memory 206952 kb
Host smart-5f8cbe8c-f96a-4d65-9ed2-549b45d79adc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525583605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.3525583605
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.729397328
Short name T669
Test name
Test status
Simulation time 95520242 ps
CPU time 0.91 seconds
Started Jul 10 05:05:11 PM PDT 24
Finished Jul 10 05:05:16 PM PDT 24
Peak memory 208460 kb
Host smart-20788b1b-b53c-47f5-a99d-3d2097eb3b17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729397328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.729397328
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.149925816
Short name T344
Test name
Test status
Simulation time 175777024 ps
CPU time 7.3 seconds
Started Jul 10 05:05:10 PM PDT 24
Finished Jul 10 05:05:22 PM PDT 24
Peak memory 217752 kb
Host smart-1271b596-11be-44e3-9e20-d403aa04ac85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149925816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.149925816
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.3824261967
Short name T636
Test name
Test status
Simulation time 917390803 ps
CPU time 5.73 seconds
Started Jul 10 05:05:10 PM PDT 24
Finished Jul 10 05:05:20 PM PDT 24
Peak memory 217080 kb
Host smart-500e0f6a-8f40-418a-81ec-37e480784b03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824261967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.3824261967
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.68727642
Short name T698
Test name
Test status
Simulation time 154305404 ps
CPU time 3.33 seconds
Started Jul 10 05:05:12 PM PDT 24
Finished Jul 10 05:05:19 PM PDT 24
Peak memory 217128 kb
Host smart-d134f50a-9dfb-4df6-bc8f-3c5e5fffe346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68727642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.68727642
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.830104323
Short name T811
Test name
Test status
Simulation time 225771632 ps
CPU time 9.48 seconds
Started Jul 10 05:05:11 PM PDT 24
Finished Jul 10 05:05:25 PM PDT 24
Peak memory 218180 kb
Host smart-6b6aff4a-b209-469d-a831-def7faf0c34c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830104323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.830104323
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.1747373227
Short name T827
Test name
Test status
Simulation time 1898907680 ps
CPU time 18.52 seconds
Started Jul 10 05:05:09 PM PDT 24
Finished Jul 10 05:05:32 PM PDT 24
Peak memory 225396 kb
Host smart-6d56c44d-6758-4b69-ae45-c07df5954bda
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747373227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.1747373227
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.15044472
Short name T657
Test name
Test status
Simulation time 537325205 ps
CPU time 6.95 seconds
Started Jul 10 05:05:12 PM PDT 24
Finished Jul 10 05:05:23 PM PDT 24
Peak memory 225396 kb
Host smart-442114d0-2d7b-4568-a1b2-ccd9195a2437
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15044472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.15044472
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.3919282249
Short name T18
Test name
Test status
Simulation time 550262993 ps
CPU time 7.54 seconds
Started Jul 10 05:05:11 PM PDT 24
Finished Jul 10 05:05:22 PM PDT 24
Peak memory 224728 kb
Host smart-3fcc975a-05da-40cf-8cdc-5d27763a6da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919282249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.3919282249
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.609511506
Short name T563
Test name
Test status
Simulation time 245410008 ps
CPU time 2.36 seconds
Started Jul 10 05:05:02 PM PDT 24
Finished Jul 10 05:05:06 PM PDT 24
Peak memory 213860 kb
Host smart-052e6bc6-df9e-4f94-98d3-c91a4e212863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609511506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.609511506
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.47326098
Short name T315
Test name
Test status
Simulation time 246165862 ps
CPU time 22.51 seconds
Started Jul 10 05:05:08 PM PDT 24
Finished Jul 10 05:05:35 PM PDT 24
Peak memory 250516 kb
Host smart-e6f77a03-7f34-4511-aee5-5b2ce3304d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47326098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.47326098
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.1412998058
Short name T550
Test name
Test status
Simulation time 314618722 ps
CPU time 6.25 seconds
Started Jul 10 05:05:06 PM PDT 24
Finished Jul 10 05:05:17 PM PDT 24
Peak memory 246392 kb
Host smart-2e95fa4e-1809-454e-9ec7-fad992885c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412998058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.1412998058
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.2320769212
Short name T777
Test name
Test status
Simulation time 6531927378 ps
CPU time 87.48 seconds
Started Jul 10 05:05:09 PM PDT 24
Finished Jul 10 05:06:41 PM PDT 24
Peak memory 275116 kb
Host smart-6fc13d40-6b7e-44e5-8ec9-62b7d310d682
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320769212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.2320769212
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.92625930
Short name T186
Test name
Test status
Simulation time 28147722 ps
CPU time 0.93 seconds
Started Jul 10 05:05:03 PM PDT 24
Finished Jul 10 05:05:09 PM PDT 24
Peak memory 208476 kb
Host smart-e1b741ba-dd57-4ded-a1ae-149e895abb55
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92625930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctr
l_volatile_unlock_smoke.92625930
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.2607241487
Short name T267
Test name
Test status
Simulation time 57267528 ps
CPU time 0.88 seconds
Started Jul 10 05:05:09 PM PDT 24
Finished Jul 10 05:05:15 PM PDT 24
Peak memory 208384 kb
Host smart-0199b2a9-0523-4049-860a-0a06c277d646
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607241487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.2607241487
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.3046107353
Short name T498
Test name
Test status
Simulation time 1189074839 ps
CPU time 9.94 seconds
Started Jul 10 05:05:08 PM PDT 24
Finished Jul 10 05:05:23 PM PDT 24
Peak memory 217736 kb
Host smart-c468dba2-92ba-4ac0-9cf1-60fc99eda63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046107353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.3046107353
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.2480675177
Short name T648
Test name
Test status
Simulation time 1982650071 ps
CPU time 22.77 seconds
Started Jul 10 05:05:11 PM PDT 24
Finished Jul 10 05:05:38 PM PDT 24
Peak memory 217096 kb
Host smart-1112eed7-cf11-4cf7-9261-6c089cd913ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480675177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.2480675177
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.4214797260
Short name T474
Test name
Test status
Simulation time 25904640 ps
CPU time 2.01 seconds
Started Jul 10 05:05:08 PM PDT 24
Finished Jul 10 05:05:15 PM PDT 24
Peak memory 221544 kb
Host smart-3c6e67fd-7fdf-4259-8d15-d37b30f338e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214797260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.4214797260
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.2845895353
Short name T850
Test name
Test status
Simulation time 467915613 ps
CPU time 13.76 seconds
Started Jul 10 05:05:09 PM PDT 24
Finished Jul 10 05:05:27 PM PDT 24
Peak memory 218364 kb
Host smart-12a25bda-488e-443f-b061-05b88ecf55dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845895353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.2845895353
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.1630002036
Short name T346
Test name
Test status
Simulation time 1121966176 ps
CPU time 12.13 seconds
Started Jul 10 05:05:11 PM PDT 24
Finished Jul 10 05:05:27 PM PDT 24
Peak memory 217652 kb
Host smart-f6216812-31fd-47e7-b8b8-9d140105108d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630002036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.1630002036
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.3531736188
Short name T98
Test name
Test status
Simulation time 254799868 ps
CPU time 8.94 seconds
Started Jul 10 05:05:08 PM PDT 24
Finished Jul 10 05:05:22 PM PDT 24
Peak memory 217612 kb
Host smart-78dd505e-b5cb-44ce-8a45-e592dde40033
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531736188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
3531736188
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.3991098725
Short name T61
Test name
Test status
Simulation time 264073859 ps
CPU time 7.11 seconds
Started Jul 10 05:05:11 PM PDT 24
Finished Jul 10 05:05:22 PM PDT 24
Peak memory 224640 kb
Host smart-e9b5219e-2492-496d-9219-49d5af54e0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991098725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.3991098725
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.1374887480
Short name T641
Test name
Test status
Simulation time 194617901 ps
CPU time 3.3 seconds
Started Jul 10 05:05:10 PM PDT 24
Finished Jul 10 05:05:18 PM PDT 24
Peak memory 214540 kb
Host smart-af3d0846-897c-4f44-ac80-962f3703a2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374887480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.1374887480
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.2333644559
Short name T770
Test name
Test status
Simulation time 233538863 ps
CPU time 18.68 seconds
Started Jul 10 05:05:11 PM PDT 24
Finished Jul 10 05:05:34 PM PDT 24
Peak memory 246720 kb
Host smart-b0700324-5f29-42ad-8b77-4e56b0b769a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333644559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.2333644559
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.2571592853
Short name T270
Test name
Test status
Simulation time 205834475 ps
CPU time 7.76 seconds
Started Jul 10 05:05:12 PM PDT 24
Finished Jul 10 05:05:23 PM PDT 24
Peak memory 249896 kb
Host smart-78a2b93b-40e9-413b-a90b-636c21e68449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571592853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.2571592853
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.2718061147
Short name T849
Test name
Test status
Simulation time 18363765885 ps
CPU time 280.01 seconds
Started Jul 10 05:05:12 PM PDT 24
Finished Jul 10 05:09:56 PM PDT 24
Peak memory 347880 kb
Host smart-d70bb09c-344f-4b54-a1c0-35c008f97701
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718061147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.2718061147
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.3087552662
Short name T665
Test name
Test status
Simulation time 37626203 ps
CPU time 1.04 seconds
Started Jul 10 05:05:09 PM PDT 24
Finished Jul 10 05:05:15 PM PDT 24
Peak memory 211320 kb
Host smart-9c56728c-533d-4676-b18a-d848651bc643
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087552662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.3087552662
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.3126406228
Short name T353
Test name
Test status
Simulation time 35354067 ps
CPU time 0.89 seconds
Started Jul 10 05:05:19 PM PDT 24
Finished Jul 10 05:05:22 PM PDT 24
Peak memory 208452 kb
Host smart-858075dc-79fd-473c-a66b-c00a301affdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126406228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.3126406228
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.1082155795
Short name T51
Test name
Test status
Simulation time 1122325503 ps
CPU time 12.85 seconds
Started Jul 10 05:05:10 PM PDT 24
Finished Jul 10 05:05:27 PM PDT 24
Peak memory 217664 kb
Host smart-07e2a46b-c4e0-4a07-9b8d-b272d6a41843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082155795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.1082155795
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.2291443461
Short name T786
Test name
Test status
Simulation time 321633128 ps
CPU time 4.95 seconds
Started Jul 10 05:05:11 PM PDT 24
Finished Jul 10 05:05:20 PM PDT 24
Peak memory 217172 kb
Host smart-08415b37-e2d4-44ef-9633-75a85465b158
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291443461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.2291443461
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.820769788
Short name T552
Test name
Test status
Simulation time 879096139 ps
CPU time 8.05 seconds
Started Jul 10 05:05:11 PM PDT 24
Finished Jul 10 05:05:23 PM PDT 24
Peak memory 217632 kb
Host smart-ec0282ba-9b65-47f4-9377-25c7c85d5e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820769788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.820769788
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.3516600375
Short name T586
Test name
Test status
Simulation time 270814635 ps
CPU time 10.87 seconds
Started Jul 10 05:05:19 PM PDT 24
Finished Jul 10 05:05:32 PM PDT 24
Peak memory 219412 kb
Host smart-eee84cd8-4ed2-4629-8f45-44e285a6efed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516600375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.3516600375
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.499438119
Short name T756
Test name
Test status
Simulation time 1400974425 ps
CPU time 11.28 seconds
Started Jul 10 05:05:17 PM PDT 24
Finished Jul 10 05:05:30 PM PDT 24
Peak memory 225392 kb
Host smart-e18f5da0-0284-4d2e-ada6-14c07782cde3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499438119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_di
gest.499438119
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.3822006056
Short name T396
Test name
Test status
Simulation time 751154609 ps
CPU time 9.38 seconds
Started Jul 10 05:05:17 PM PDT 24
Finished Jul 10 05:05:28 PM PDT 24
Peak memory 224736 kb
Host smart-73112645-217c-4fc8-a26c-4486fd73ca4b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822006056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
3822006056
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.4030687230
Short name T296
Test name
Test status
Simulation time 1142437690 ps
CPU time 8.22 seconds
Started Jul 10 05:05:09 PM PDT 24
Finished Jul 10 05:05:22 PM PDT 24
Peak memory 217772 kb
Host smart-fb67849f-ec4a-4e9a-875c-7e2e3cf3a25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030687230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.4030687230
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.4200524114
Short name T80
Test name
Test status
Simulation time 45769555 ps
CPU time 1.78 seconds
Started Jul 10 05:05:09 PM PDT 24
Finished Jul 10 05:05:15 PM PDT 24
Peak memory 217128 kb
Host smart-a1151e0f-11c4-4786-bd76-338995dbff87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200524114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.4200524114
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.70902074
Short name T681
Test name
Test status
Simulation time 260127749 ps
CPU time 26.3 seconds
Started Jul 10 05:05:11 PM PDT 24
Finished Jul 10 05:05:42 PM PDT 24
Peak memory 250452 kb
Host smart-359d0094-6e6d-4ba7-aa0d-8310f72e9f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70902074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.70902074
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.1123441242
Short name T261
Test name
Test status
Simulation time 224674282 ps
CPU time 6.67 seconds
Started Jul 10 05:05:09 PM PDT 24
Finished Jul 10 05:05:20 PM PDT 24
Peak memory 247000 kb
Host smart-92df5a38-102c-465e-867e-1502c735a041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123441242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.1123441242
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.2022510370
Short name T660
Test name
Test status
Simulation time 19146907743 ps
CPU time 385.24 seconds
Started Jul 10 05:05:18 PM PDT 24
Finished Jul 10 05:11:45 PM PDT 24
Peak memory 250572 kb
Host smart-2e88ebb7-f88f-4f95-9275-15750f7e8461
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022510370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.2022510370
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.1035915803
Short name T783
Test name
Test status
Simulation time 20915673636 ps
CPU time 865.33 seconds
Started Jul 10 05:05:21 PM PDT 24
Finished Jul 10 05:19:48 PM PDT 24
Peak memory 496300 kb
Host smart-effc312a-dbf8-49b5-96e2-314318a63647
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1035915803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.1035915803
Directory /workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.1090756066
Short name T294
Test name
Test status
Simulation time 77562314 ps
CPU time 1.25 seconds
Started Jul 10 05:05:07 PM PDT 24
Finished Jul 10 05:05:14 PM PDT 24
Peak memory 217272 kb
Host smart-4c0f7812-457a-4ac0-b4e1-9e9eee6631bd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090756066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.1090756066
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.2737916693
Short name T265
Test name
Test status
Simulation time 38405704 ps
CPU time 0.88 seconds
Started Jul 10 05:05:18 PM PDT 24
Finished Jul 10 05:05:21 PM PDT 24
Peak memory 208496 kb
Host smart-082d8a9a-3295-47a4-80dc-230247402f7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737916693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.2737916693
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.3551923611
Short name T493
Test name
Test status
Simulation time 342290239 ps
CPU time 14.31 seconds
Started Jul 10 05:05:18 PM PDT 24
Finished Jul 10 05:05:35 PM PDT 24
Peak memory 217780 kb
Host smart-33a2d9d0-f26b-4e76-afcb-09ad1c050670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551923611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.3551923611
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.2955234638
Short name T690
Test name
Test status
Simulation time 944412444 ps
CPU time 11.84 seconds
Started Jul 10 05:05:17 PM PDT 24
Finished Jul 10 05:05:30 PM PDT 24
Peak memory 217060 kb
Host smart-9452ed19-930e-4447-a634-284d92fb4124
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955234638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.2955234638
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.1887638764
Short name T817
Test name
Test status
Simulation time 48218118 ps
CPU time 2.35 seconds
Started Jul 10 05:05:20 PM PDT 24
Finished Jul 10 05:05:24 PM PDT 24
Peak memory 217660 kb
Host smart-83d8251e-094d-469c-8c45-cf1fbab3ab5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887638764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.1887638764
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.2047066311
Short name T815
Test name
Test status
Simulation time 398698714 ps
CPU time 8.1 seconds
Started Jul 10 05:05:19 PM PDT 24
Finished Jul 10 05:05:29 PM PDT 24
Peak memory 224832 kb
Host smart-536d6c2d-ab76-4bf4-bbe1-96c5a5329fc4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047066311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.2047066311
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.1474189989
Short name T453
Test name
Test status
Simulation time 529563271 ps
CPU time 8.85 seconds
Started Jul 10 05:05:18 PM PDT 24
Finished Jul 10 05:05:29 PM PDT 24
Peak memory 225488 kb
Host smart-44b81b67-fb38-4c75-b7a6-8ac1abfec6cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474189989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.1474189989
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.1438183065
Short name T845
Test name
Test status
Simulation time 369467330 ps
CPU time 12.87 seconds
Started Jul 10 05:05:20 PM PDT 24
Finished Jul 10 05:05:35 PM PDT 24
Peak memory 217524 kb
Host smart-3d1c3c72-8f88-48e3-831f-11555107a841
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438183065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
1438183065
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.3907088518
Short name T597
Test name
Test status
Simulation time 814921868 ps
CPU time 8.92 seconds
Started Jul 10 05:05:18 PM PDT 24
Finished Jul 10 05:05:30 PM PDT 24
Peak memory 224188 kb
Host smart-9ff1823b-5055-41cc-8dae-a9d0fe895e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907088518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.3907088518
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.3398468706
Short name T515
Test name
Test status
Simulation time 71543073 ps
CPU time 1.48 seconds
Started Jul 10 05:05:17 PM PDT 24
Finished Jul 10 05:05:19 PM PDT 24
Peak memory 213540 kb
Host smart-45a3f63b-d9cc-47f2-8ae1-121d73324287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398468706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.3398468706
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.1167284245
Short name T390
Test name
Test status
Simulation time 1289914326 ps
CPU time 20.78 seconds
Started Jul 10 05:05:18 PM PDT 24
Finished Jul 10 05:05:41 PM PDT 24
Peak memory 250520 kb
Host smart-27e772f1-cead-4ed0-8e33-86179b214807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167284245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.1167284245
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.1804891375
Short name T818
Test name
Test status
Simulation time 53868046 ps
CPU time 7.48 seconds
Started Jul 10 05:05:19 PM PDT 24
Finished Jul 10 05:05:29 PM PDT 24
Peak memory 250388 kb
Host smart-e1eec589-8743-4d60-bc2e-d2a7d1827bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804891375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.1804891375
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.3195102031
Short name T808
Test name
Test status
Simulation time 7688729105 ps
CPU time 133.51 seconds
Started Jul 10 05:05:19 PM PDT 24
Finished Jul 10 05:07:35 PM PDT 24
Peak memory 249028 kb
Host smart-849bf4ae-3627-4483-8a64-5d4ca5264417
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195102031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.3195102031
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.3180331692
Short name T643
Test name
Test status
Simulation time 24597485 ps
CPU time 0.9 seconds
Started Jul 10 05:05:20 PM PDT 24
Finished Jul 10 05:05:23 PM PDT 24
Peak memory 211188 kb
Host smart-73619f4d-3693-499a-bf6c-57befcbeb11e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180331692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.3180331692
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.1233921260
Short name T310
Test name
Test status
Simulation time 30039733 ps
CPU time 0.91 seconds
Started Jul 10 05:01:50 PM PDT 24
Finished Jul 10 05:01:53 PM PDT 24
Peak memory 208404 kb
Host smart-6575f12c-be8c-4e1f-b01a-4539ea4e010e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233921260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.1233921260
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.2288219245
Short name T306
Test name
Test status
Simulation time 18346131 ps
CPU time 0.81 seconds
Started Jul 10 05:01:52 PM PDT 24
Finished Jul 10 05:01:55 PM PDT 24
Peak memory 208480 kb
Host smart-3dcd34d7-c9d2-4bb6-9473-ccdcbb7fb52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288219245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.2288219245
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.3759978321
Short name T42
Test name
Test status
Simulation time 1464523664 ps
CPU time 15.76 seconds
Started Jul 10 05:01:50 PM PDT 24
Finished Jul 10 05:02:07 PM PDT 24
Peak memory 217652 kb
Host smart-a3a856c9-8a85-4944-8439-3aa1bd4d8ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759978321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.3759978321
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.1418850765
Short name T798
Test name
Test status
Simulation time 1833296647 ps
CPU time 6.97 seconds
Started Jul 10 05:01:51 PM PDT 24
Finished Jul 10 05:02:00 PM PDT 24
Peak memory 216860 kb
Host smart-1972e963-0e9d-45bb-a29b-cb51ffc69ef5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418850765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.1418850765
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.397048554
Short name T194
Test name
Test status
Simulation time 1513670111 ps
CPU time 9.43 seconds
Started Jul 10 05:01:50 PM PDT 24
Finished Jul 10 05:02:00 PM PDT 24
Peak memory 217132 kb
Host smart-8ccb872c-55c1-43e2-ac5e-ded19eb1b033
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397048554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.397048554
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.1994362960
Short name T598
Test name
Test status
Simulation time 564556515 ps
CPU time 16.42 seconds
Started Jul 10 05:01:50 PM PDT 24
Finished Jul 10 05:02:09 PM PDT 24
Peak memory 217600 kb
Host smart-dea13380-8c09-452f-97b4-40dfb05b0aaa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994362960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.1994362960
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.3198619426
Short name T62
Test name
Test status
Simulation time 1434481308 ps
CPU time 18.61 seconds
Started Jul 10 05:01:51 PM PDT 24
Finished Jul 10 05:02:12 PM PDT 24
Peak memory 217052 kb
Host smart-a0fb6370-e86f-4275-b10a-836bd8223027
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198619426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.3198619426
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.2581588536
Short name T193
Test name
Test status
Simulation time 169113448 ps
CPU time 5.13 seconds
Started Jul 10 05:01:53 PM PDT 24
Finished Jul 10 05:02:00 PM PDT 24
Peak memory 217000 kb
Host smart-42b1bb2f-748d-4b0d-b57d-83f4be377152
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581588536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
2581588536
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.2182726319
Short name T416
Test name
Test status
Simulation time 1265610703 ps
CPU time 52.95 seconds
Started Jul 10 05:01:51 PM PDT 24
Finished Jul 10 05:02:47 PM PDT 24
Peak memory 266896 kb
Host smart-0e0b8961-b623-4ffb-9616-3145da268192
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182726319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.2182726319
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.2291698023
Short name T401
Test name
Test status
Simulation time 967286057 ps
CPU time 33.21 seconds
Started Jul 10 05:01:52 PM PDT 24
Finished Jul 10 05:02:27 PM PDT 24
Peak memory 250636 kb
Host smart-8ecc7d89-6b4d-4221-b2cb-cb7eff21dfd5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291698023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.2291698023
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.1983972771
Short name T328
Test name
Test status
Simulation time 401020236 ps
CPU time 4.28 seconds
Started Jul 10 05:01:54 PM PDT 24
Finished Jul 10 05:01:59 PM PDT 24
Peak memory 217652 kb
Host smart-980a538d-8ed3-46c5-a7bf-142191450138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983972771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.1983972771
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.1512339417
Short name T688
Test name
Test status
Simulation time 947358373 ps
CPU time 12.84 seconds
Started Jul 10 05:01:50 PM PDT 24
Finished Jul 10 05:02:05 PM PDT 24
Peak memory 217076 kb
Host smart-7f78f701-c43d-4767-a1a6-e834307ee547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512339417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.1512339417
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.1309600236
Short name T389
Test name
Test status
Simulation time 526365664 ps
CPU time 20.95 seconds
Started Jul 10 05:01:51 PM PDT 24
Finished Jul 10 05:02:14 PM PDT 24
Peak memory 218372 kb
Host smart-3914c06e-5bb6-4aa4-be7c-ecdd6185d0e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309600236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.1309600236
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.3652204510
Short name T652
Test name
Test status
Simulation time 740391957 ps
CPU time 10.42 seconds
Started Jul 10 05:01:50 PM PDT 24
Finished Jul 10 05:02:02 PM PDT 24
Peak memory 225448 kb
Host smart-f79ed384-a36b-4c15-9a45-e21bfb6f9e28
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652204510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.3652204510
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.1172136147
Short name T791
Test name
Test status
Simulation time 976793565 ps
CPU time 7.65 seconds
Started Jul 10 05:01:50 PM PDT 24
Finished Jul 10 05:01:59 PM PDT 24
Peak memory 225388 kb
Host smart-6ec9c005-68ac-4ecf-8214-be942fc8ff77
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172136147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.1
172136147
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.1255401150
Short name T373
Test name
Test status
Simulation time 1619894745 ps
CPU time 10.87 seconds
Started Jul 10 05:01:53 PM PDT 24
Finished Jul 10 05:02:06 PM PDT 24
Peak memory 225460 kb
Host smart-4370082f-0868-461d-ad91-20f7aabfed78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255401150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.1255401150
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.3468263764
Short name T338
Test name
Test status
Simulation time 1040407524 ps
CPU time 4.72 seconds
Started Jul 10 05:01:49 PM PDT 24
Finished Jul 10 05:01:56 PM PDT 24
Peak memory 217080 kb
Host smart-10bf5c3c-01b6-4280-8e4b-95d49e58d973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468263764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.3468263764
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.1957057000
Short name T671
Test name
Test status
Simulation time 1134951360 ps
CPU time 25.03 seconds
Started Jul 10 05:01:51 PM PDT 24
Finished Jul 10 05:02:18 PM PDT 24
Peak memory 250412 kb
Host smart-7ce5a180-c911-4fd9-98bc-4b6e350d5e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957057000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.1957057000
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.4109074451
Short name T234
Test name
Test status
Simulation time 1210055164 ps
CPU time 10.93 seconds
Started Jul 10 05:01:52 PM PDT 24
Finished Jul 10 05:02:05 PM PDT 24
Peak memory 250456 kb
Host smart-a07abb85-6164-4dfc-9ac1-81c97b6a2f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109074451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.4109074451
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.2638127105
Short name T46
Test name
Test status
Simulation time 20878435293 ps
CPU time 113.74 seconds
Started Jul 10 05:01:49 PM PDT 24
Finished Jul 10 05:03:44 PM PDT 24
Peak memory 250440 kb
Host smart-85fd8c52-f03e-423e-adb1-b44d605094bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638127105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.2638127105
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.1308388330
Short name T776
Test name
Test status
Simulation time 27890967 ps
CPU time 1.08 seconds
Started Jul 10 05:01:50 PM PDT 24
Finished Jul 10 05:01:54 PM PDT 24
Peak memory 211268 kb
Host smart-eb6df75f-d039-4c87-91a4-0588a8b2b6e8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308388330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.1308388330
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.4108620151
Short name T102
Test name
Test status
Simulation time 19640836 ps
CPU time 1.18 seconds
Started Jul 10 05:02:00 PM PDT 24
Finished Jul 10 05:02:03 PM PDT 24
Peak memory 208460 kb
Host smart-a7a87023-e5c6-4b4e-84df-7c3fed01c46a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108620151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.4108620151
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.2191201456
Short name T787
Test name
Test status
Simulation time 2583765499 ps
CPU time 16.4 seconds
Started Jul 10 05:02:00 PM PDT 24
Finished Jul 10 05:02:18 PM PDT 24
Peak memory 218428 kb
Host smart-1e568b2c-e6df-481e-ade5-8d4b6d186c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191201456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.2191201456
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.2145446519
Short name T826
Test name
Test status
Simulation time 831353840 ps
CPU time 5.77 seconds
Started Jul 10 05:01:57 PM PDT 24
Finished Jul 10 05:02:05 PM PDT 24
Peak memory 217076 kb
Host smart-6cb90485-a47d-46e3-9473-c033c186fd22
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145446519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.2145446519
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.813500042
Short name T47
Test name
Test status
Simulation time 6908986822 ps
CPU time 51.61 seconds
Started Jul 10 05:01:59 PM PDT 24
Finished Jul 10 05:02:53 PM PDT 24
Peak memory 218336 kb
Host smart-136642d9-291e-4e61-a363-05e0bf6ba9d1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813500042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_err
ors.813500042
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.566731615
Short name T412
Test name
Test status
Simulation time 1360276794 ps
CPU time 3.32 seconds
Started Jul 10 05:01:59 PM PDT 24
Finished Jul 10 05:02:04 PM PDT 24
Peak memory 217136 kb
Host smart-c5849506-e1fd-4289-adb3-00d5cd04df22
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566731615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.566731615
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.3047792644
Short name T280
Test name
Test status
Simulation time 201998147 ps
CPU time 3.92 seconds
Started Jul 10 05:01:59 PM PDT 24
Finished Jul 10 05:02:05 PM PDT 24
Peak memory 222248 kb
Host smart-406bb4c1-b5db-423b-908e-60e4d63d4071
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047792644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.3047792644
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.2232918527
Short name T111
Test name
Test status
Simulation time 1917587879 ps
CPU time 14.62 seconds
Started Jul 10 05:01:56 PM PDT 24
Finished Jul 10 05:02:12 PM PDT 24
Peak memory 217008 kb
Host smart-4c1ff6f6-48a4-4d9c-9ae7-2fbb2b5237f0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232918527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.2232918527
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.3148366077
Short name T470
Test name
Test status
Simulation time 4088078217 ps
CPU time 14.99 seconds
Started Jul 10 05:02:01 PM PDT 24
Finished Jul 10 05:02:18 PM PDT 24
Peak memory 217052 kb
Host smart-8961633f-2001-4f2a-8726-506e66eea625
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148366077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
3148366077
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.1987718957
Short name T289
Test name
Test status
Simulation time 1329866264 ps
CPU time 32.72 seconds
Started Jul 10 05:02:02 PM PDT 24
Finished Jul 10 05:02:36 PM PDT 24
Peak memory 267140 kb
Host smart-ce009190-cf89-4d54-8917-08f53412bc36
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987718957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.1987718957
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.1171774666
Short name T447
Test name
Test status
Simulation time 639189407 ps
CPU time 24.25 seconds
Started Jul 10 05:01:58 PM PDT 24
Finished Jul 10 05:02:24 PM PDT 24
Peak memory 250312 kb
Host smart-11019dd1-1fb4-4aad-8700-58f6dc35f757
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171774666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.1171774666
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.2658702292
Short name T578
Test name
Test status
Simulation time 98969279 ps
CPU time 1.41 seconds
Started Jul 10 05:02:01 PM PDT 24
Finished Jul 10 05:02:04 PM PDT 24
Peak memory 221216 kb
Host smart-7254f1c7-3f08-4419-8ac9-0ed53061e991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658702292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.2658702292
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.2132005165
Short name T804
Test name
Test status
Simulation time 941160170 ps
CPU time 12.87 seconds
Started Jul 10 05:01:58 PM PDT 24
Finished Jul 10 05:02:12 PM PDT 24
Peak memory 213428 kb
Host smart-39b22891-51c5-4ddc-ab02-37e0275692a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132005165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.2132005165
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.860660555
Short name T231
Test name
Test status
Simulation time 323089828 ps
CPU time 10.53 seconds
Started Jul 10 05:02:33 PM PDT 24
Finished Jul 10 05:02:45 PM PDT 24
Peak memory 225440 kb
Host smart-dbd07515-89bd-492b-a319-5d41a81716da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860660555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_dig
est.860660555
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.2646967297
Short name T833
Test name
Test status
Simulation time 219732567 ps
CPU time 6.33 seconds
Started Jul 10 05:02:01 PM PDT 24
Finished Jul 10 05:02:09 PM PDT 24
Peak memory 224144 kb
Host smart-75277bc4-7cee-45ac-9658-d118800b936e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646967297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.2
646967297
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.1495396121
Short name T347
Test name
Test status
Simulation time 2413130836 ps
CPU time 10.16 seconds
Started Jul 10 05:01:57 PM PDT 24
Finished Jul 10 05:02:09 PM PDT 24
Peak memory 217784 kb
Host smart-4270a03f-6857-4bbe-b996-35336dcdb6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495396121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.1495396121
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.1128175089
Short name T645
Test name
Test status
Simulation time 61263464 ps
CPU time 2.88 seconds
Started Jul 10 05:01:56 PM PDT 24
Finished Jul 10 05:02:00 PM PDT 24
Peak memory 217080 kb
Host smart-34857a0b-d533-4b7e-bd3a-57d83aa954bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128175089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.1128175089
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.3572797059
Short name T617
Test name
Test status
Simulation time 267742540 ps
CPU time 37.75 seconds
Started Jul 10 05:02:00 PM PDT 24
Finished Jul 10 05:02:40 PM PDT 24
Peak memory 250400 kb
Host smart-d641ae5b-c0de-458f-b792-5de5c3e1571d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572797059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.3572797059
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.3995172928
Short name T233
Test name
Test status
Simulation time 54614808 ps
CPU time 8.96 seconds
Started Jul 10 05:01:57 PM PDT 24
Finished Jul 10 05:02:08 PM PDT 24
Peak memory 250412 kb
Host smart-6eeac4e8-8fdf-40cb-8609-e243334101f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995172928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.3995172928
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.1196825829
Short name T790
Test name
Test status
Simulation time 11765418833 ps
CPU time 239.07 seconds
Started Jul 10 05:01:57 PM PDT 24
Finished Jul 10 05:05:58 PM PDT 24
Peak memory 250516 kb
Host smart-cb21a04f-fbf5-4ea2-a62c-3d3c13fc8dd5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196825829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.1196825829
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.2543907226
Short name T404
Test name
Test status
Simulation time 14039136 ps
CPU time 0.97 seconds
Started Jul 10 05:01:57 PM PDT 24
Finished Jul 10 05:01:59 PM PDT 24
Peak memory 211304 kb
Host smart-e866974c-b62a-45f5-acab-3114afbf4000
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543907226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.2543907226
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.107963641
Short name T623
Test name
Test status
Simulation time 30489628 ps
CPU time 0.82 seconds
Started Jul 10 05:02:03 PM PDT 24
Finished Jul 10 05:02:04 PM PDT 24
Peak memory 208468 kb
Host smart-591a666c-b37f-496b-8cd8-2694e2f127ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107963641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.107963641
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.1915928847
Short name T666
Test name
Test status
Simulation time 11104887 ps
CPU time 0.82 seconds
Started Jul 10 05:02:03 PM PDT 24
Finished Jul 10 05:02:06 PM PDT 24
Peak memory 208448 kb
Host smart-a585a330-7622-47bf-92ce-74128184558b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915928847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.1915928847
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.883194169
Short name T747
Test name
Test status
Simulation time 473211218 ps
CPU time 13.68 seconds
Started Jul 10 05:02:04 PM PDT 24
Finished Jul 10 05:02:19 PM PDT 24
Peak memory 225480 kb
Host smart-07e489de-c8c3-4e5a-9201-5e5b7688d3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883194169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.883194169
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.2009782424
Short name T565
Test name
Test status
Simulation time 622568886 ps
CPU time 7.26 seconds
Started Jul 10 05:02:09 PM PDT 24
Finished Jul 10 05:02:17 PM PDT 24
Peak memory 216688 kb
Host smart-49a6075e-81bd-4285-83f6-76408325da97
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009782424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.2009782424
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.4159690498
Short name T606
Test name
Test status
Simulation time 5817094023 ps
CPU time 75.73 seconds
Started Jul 10 05:02:04 PM PDT 24
Finished Jul 10 05:03:21 PM PDT 24
Peak memory 217776 kb
Host smart-af8e4be2-8b1d-45ff-a702-f22798ef8407
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159690498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.4159690498
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.2946738248
Short name T567
Test name
Test status
Simulation time 188731803 ps
CPU time 2.97 seconds
Started Jul 10 05:02:05 PM PDT 24
Finished Jul 10 05:02:09 PM PDT 24
Peak memory 217100 kb
Host smart-f30734fb-ec99-4dc6-8ced-9d26203edc75
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946738248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.2
946738248
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.1427314856
Short name T365
Test name
Test status
Simulation time 1356469199 ps
CPU time 5.24 seconds
Started Jul 10 05:02:05 PM PDT 24
Finished Jul 10 05:02:11 PM PDT 24
Peak memory 222320 kb
Host smart-49ad3541-bf99-4c69-9719-4e11b2704cbe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427314856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.1427314856
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.4127983308
Short name T325
Test name
Test status
Simulation time 6792455910 ps
CPU time 24.59 seconds
Started Jul 10 05:02:05 PM PDT 24
Finished Jul 10 05:02:31 PM PDT 24
Peak memory 217068 kb
Host smart-a1885769-2ce5-4b5a-bc39-4b274f308219
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127983308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.4127983308
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.1137518324
Short name T753
Test name
Test status
Simulation time 1090470094 ps
CPU time 8.01 seconds
Started Jul 10 05:02:03 PM PDT 24
Finished Jul 10 05:02:12 PM PDT 24
Peak memory 216996 kb
Host smart-5acf7ee5-21d1-48af-acc4-024955e99272
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137518324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
1137518324
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.3277938663
Short name T242
Test name
Test status
Simulation time 5086053301 ps
CPU time 52.19 seconds
Started Jul 10 05:02:03 PM PDT 24
Finished Jul 10 05:02:57 PM PDT 24
Peak memory 266832 kb
Host smart-c731d9c4-59ed-4df5-ba1f-28b936c15915
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277938663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.3277938663
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.704863657
Short name T547
Test name
Test status
Simulation time 369359061 ps
CPU time 13.96 seconds
Started Jul 10 05:02:06 PM PDT 24
Finished Jul 10 05:02:20 PM PDT 24
Peak memory 250328 kb
Host smart-8a659e59-7d20-4825-8e7d-5c7f5bd1dc22
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704863657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_state_post_trans.704863657
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.2065029633
Short name T368
Test name
Test status
Simulation time 91902528 ps
CPU time 3.22 seconds
Started Jul 10 05:02:09 PM PDT 24
Finished Jul 10 05:02:13 PM PDT 24
Peak memory 217532 kb
Host smart-e95c6eee-cb2b-498a-b8fd-e23d5214f1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065029633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.2065029633
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.1412215546
Short name T861
Test name
Test status
Simulation time 244844035 ps
CPU time 16.93 seconds
Started Jul 10 05:02:03 PM PDT 24
Finished Jul 10 05:02:21 PM PDT 24
Peak memory 214032 kb
Host smart-82ab728b-e1ac-476f-8b37-154577776583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412215546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.1412215546
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.870649853
Short name T768
Test name
Test status
Simulation time 566028842 ps
CPU time 9.35 seconds
Started Jul 10 05:02:03 PM PDT 24
Finished Jul 10 05:02:14 PM PDT 24
Peak memory 225140 kb
Host smart-281bd820-54c6-4f67-8d48-0616034b90bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870649853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.870649853
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.140447543
Short name T178
Test name
Test status
Simulation time 524044441 ps
CPU time 13.62 seconds
Started Jul 10 05:02:03 PM PDT 24
Finished Jul 10 05:02:19 PM PDT 24
Peak memory 217684 kb
Host smart-1591cb15-c21d-4800-acc5-3cb0ed12e543
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140447543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_dig
est.140447543
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.1736940235
Short name T259
Test name
Test status
Simulation time 555229995 ps
CPU time 11.53 seconds
Started Jul 10 05:02:06 PM PDT 24
Finished Jul 10 05:02:18 PM PDT 24
Peak memory 217616 kb
Host smart-b3dad770-b726-4512-bdbb-ca7beb09707a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736940235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.1
736940235
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.343766634
Short name T174
Test name
Test status
Simulation time 466518439 ps
CPU time 11.13 seconds
Started Jul 10 05:02:09 PM PDT 24
Finished Jul 10 05:02:21 PM PDT 24
Peak memory 217712 kb
Host smart-e4bf21bf-2c5e-432d-93a6-e5a52ea48b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343766634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.343766634
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.2224335295
Short name T74
Test name
Test status
Simulation time 21421176 ps
CPU time 1.08 seconds
Started Jul 10 05:01:57 PM PDT 24
Finished Jul 10 05:01:59 PM PDT 24
Peak memory 211428 kb
Host smart-48eb8b79-6bdd-44f5-99b2-915d039ddb5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224335295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.2224335295
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.221143997
Short name T279
Test name
Test status
Simulation time 741991179 ps
CPU time 19.22 seconds
Started Jul 10 05:02:02 PM PDT 24
Finished Jul 10 05:02:23 PM PDT 24
Peak memory 244100 kb
Host smart-e4b55281-099e-4ae0-a3b5-a80e074c92f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221143997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.221143997
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.4137892670
Short name T843
Test name
Test status
Simulation time 314184763 ps
CPU time 8.53 seconds
Started Jul 10 05:02:03 PM PDT 24
Finished Jul 10 05:02:12 PM PDT 24
Peak memory 250708 kb
Host smart-f466dbd5-1a7e-483e-a953-f31724162bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137892670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.4137892670
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.1147835612
Short name T77
Test name
Test status
Simulation time 10987156049 ps
CPU time 78.51 seconds
Started Jul 10 05:02:03 PM PDT 24
Finished Jul 10 05:03:23 PM PDT 24
Peak memory 248716 kb
Host smart-93cc1d44-d82a-4689-b7ca-b804627bab05
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147835612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.1147835612
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.865854190
Short name T479
Test name
Test status
Simulation time 38595254 ps
CPU time 0.79 seconds
Started Jul 10 05:02:03 PM PDT 24
Finished Jul 10 05:02:05 PM PDT 24
Peak memory 208120 kb
Host smart-28e96449-72b2-4b50-9ed7-bbb8525c3d43
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865854190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctr
l_volatile_unlock_smoke.865854190
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.3275605362
Short name T94
Test name
Test status
Simulation time 17326673 ps
CPU time 0.9 seconds
Started Jul 10 05:02:19 PM PDT 24
Finished Jul 10 05:02:22 PM PDT 24
Peak memory 208392 kb
Host smart-093f7314-daa1-489b-90f0-c91dcab09e93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275605362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.3275605362
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.4240023197
Short name T324
Test name
Test status
Simulation time 12187832 ps
CPU time 1.02 seconds
Started Jul 10 05:02:12 PM PDT 24
Finished Jul 10 05:02:15 PM PDT 24
Peak memory 208304 kb
Host smart-ceba6a16-28c1-40af-94d1-dfc4d5688224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240023197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.4240023197
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.3035329
Short name T240
Test name
Test status
Simulation time 512647644 ps
CPU time 13.45 seconds
Started Jul 10 05:02:12 PM PDT 24
Finished Jul 10 05:02:27 PM PDT 24
Peak memory 217664 kb
Host smart-1da3d918-fa4b-480c-a48e-aed065c6c4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.3035329
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.2504670923
Short name T658
Test name
Test status
Simulation time 1448522296 ps
CPU time 4.45 seconds
Started Jul 10 05:02:11 PM PDT 24
Finished Jul 10 05:02:16 PM PDT 24
Peak memory 217080 kb
Host smart-ecc3c3bf-e0aa-41d6-b763-fcc16acdcf88
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504670923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.2504670923
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.2065262823
Short name T544
Test name
Test status
Simulation time 3990586130 ps
CPU time 59.88 seconds
Started Jul 10 05:02:12 PM PDT 24
Finished Jul 10 05:03:14 PM PDT 24
Peak memory 218296 kb
Host smart-e4c2ed4d-ca47-4d32-866e-2576294f1330
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065262823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.2065262823
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.2691317464
Short name T543
Test name
Test status
Simulation time 1636720891 ps
CPU time 9.88 seconds
Started Jul 10 05:02:09 PM PDT 24
Finished Jul 10 05:02:20 PM PDT 24
Peak memory 217144 kb
Host smart-35f5c0b6-d891-495f-9d56-85c06df5d757
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691317464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.2
691317464
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.3504837486
Short name T820
Test name
Test status
Simulation time 539528448 ps
CPU time 5.44 seconds
Started Jul 10 05:02:11 PM PDT 24
Finished Jul 10 05:02:18 PM PDT 24
Peak memory 217644 kb
Host smart-4ebd4c0a-1a3e-4961-8153-7491a709e6a5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504837486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.3504837486
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.1231471323
Short name T590
Test name
Test status
Simulation time 692564544 ps
CPU time 12.66 seconds
Started Jul 10 05:02:10 PM PDT 24
Finished Jul 10 05:02:24 PM PDT 24
Peak memory 217028 kb
Host smart-218442c7-6fcd-4f21-81fa-3fc1ba79b2b8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231471323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.1231471323
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.1824053665
Short name T394
Test name
Test status
Simulation time 652761062 ps
CPU time 4.94 seconds
Started Jul 10 05:02:11 PM PDT 24
Finished Jul 10 05:02:18 PM PDT 24
Peak memory 217044 kb
Host smart-490aa8e2-ef16-407d-8917-4b4def39d7f4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824053665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
1824053665
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.2827686312
Short name T362
Test name
Test status
Simulation time 4304455164 ps
CPU time 35.32 seconds
Started Jul 10 05:02:09 PM PDT 24
Finished Jul 10 05:02:45 PM PDT 24
Peak memory 266792 kb
Host smart-ee0f7979-cd92-4fc7-b59c-c2125f491363
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827686312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.2827686312
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.3733355513
Short name T229
Test name
Test status
Simulation time 888363239 ps
CPU time 7.65 seconds
Started Jul 10 05:02:11 PM PDT 24
Finished Jul 10 05:02:21 PM PDT 24
Peak memory 222352 kb
Host smart-26550007-b14d-42b2-b7b2-84d9de813853
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733355513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.3733355513
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.3536380920
Short name T182
Test name
Test status
Simulation time 141288681 ps
CPU time 2.73 seconds
Started Jul 10 05:02:10 PM PDT 24
Finished Jul 10 05:02:15 PM PDT 24
Peak memory 221844 kb
Host smart-73a5f2be-ef5f-4a1b-9539-2abc95311c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536380920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.3536380920
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.1045329939
Short name T554
Test name
Test status
Simulation time 1143885897 ps
CPU time 13.37 seconds
Started Jul 10 05:02:11 PM PDT 24
Finished Jul 10 05:02:27 PM PDT 24
Peak memory 217072 kb
Host smart-94bb9a8a-b952-47b4-ac3d-1c76c1cb80bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045329939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.1045329939
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.2216203065
Short name T836
Test name
Test status
Simulation time 782652931 ps
CPU time 11.15 seconds
Started Jul 10 05:02:11 PM PDT 24
Finished Jul 10 05:02:23 PM PDT 24
Peak memory 218360 kb
Host smart-6edecca8-decd-4fe7-887d-373e8ed1da52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216203065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.2216203065
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.4016420395
Short name T664
Test name
Test status
Simulation time 570346470 ps
CPU time 15.24 seconds
Started Jul 10 05:02:11 PM PDT 24
Finished Jul 10 05:02:28 PM PDT 24
Peak memory 225444 kb
Host smart-f4851104-10a5-40b2-8a90-dd3196f12b90
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016420395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.4016420395
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.1688005067
Short name T345
Test name
Test status
Simulation time 236047046 ps
CPU time 5.79 seconds
Started Jul 10 05:02:13 PM PDT 24
Finished Jul 10 05:02:20 PM PDT 24
Peak memory 217600 kb
Host smart-5795c27b-96cc-44b2-a65e-0a65eef9221d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688005067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.1
688005067
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.3926748330
Short name T656
Test name
Test status
Simulation time 228233722 ps
CPU time 9.46 seconds
Started Jul 10 05:02:11 PM PDT 24
Finished Jul 10 05:02:22 PM PDT 24
Peak memory 225532 kb
Host smart-357d2f21-c41c-4989-a780-38ac67e2b247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926748330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.3926748330
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.3638048580
Short name T503
Test name
Test status
Simulation time 142200629 ps
CPU time 3.2 seconds
Started Jul 10 05:02:10 PM PDT 24
Finished Jul 10 05:02:15 PM PDT 24
Peak memory 222536 kb
Host smart-b86842d4-91d0-4b4a-9aab-70e70f73d08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638048580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.3638048580
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.27962072
Short name T607
Test name
Test status
Simulation time 1563050937 ps
CPU time 29.61 seconds
Started Jul 10 05:02:12 PM PDT 24
Finished Jul 10 05:02:43 PM PDT 24
Peak memory 250416 kb
Host smart-3f191399-e56c-4951-8564-66c0fcd22725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27962072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.27962072
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.838577438
Short name T860
Test name
Test status
Simulation time 389486518 ps
CPU time 3.74 seconds
Started Jul 10 05:02:11 PM PDT 24
Finished Jul 10 05:02:17 PM PDT 24
Peak memory 221984 kb
Host smart-9955c1e8-d4cd-408d-9c28-b12a52bc01aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838577438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.838577438
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.148776022
Short name T629
Test name
Test status
Simulation time 6212815016 ps
CPU time 204.39 seconds
Started Jul 10 05:02:19 PM PDT 24
Finished Jul 10 05:05:45 PM PDT 24
Peak memory 404336 kb
Host smart-e0a0dcc4-00d4-4fa5-bee6-2990b486e4f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148776022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.148776022
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.273441868
Short name T825
Test name
Test status
Simulation time 115667442 ps
CPU time 1.01 seconds
Started Jul 10 05:02:25 PM PDT 24
Finished Jul 10 05:02:28 PM PDT 24
Peak memory 208404 kb
Host smart-88c8ec08-0018-4a39-9f1b-80a84b89f1de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273441868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.273441868
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.1020302828
Short name T478
Test name
Test status
Simulation time 3331216479 ps
CPU time 9.5 seconds
Started Jul 10 05:02:18 PM PDT 24
Finished Jul 10 05:02:29 PM PDT 24
Peak memory 218672 kb
Host smart-2449e5c7-edde-466b-984d-b7e730408a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020302828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.1020302828
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.859079136
Short name T581
Test name
Test status
Simulation time 398004576 ps
CPU time 7.1 seconds
Started Jul 10 05:02:19 PM PDT 24
Finished Jul 10 05:02:28 PM PDT 24
Peak memory 217188 kb
Host smart-c725ae27-33f4-41cd-8c7b-1b4f8e2d82e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859079136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.859079136
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.246679104
Short name T738
Test name
Test status
Simulation time 2830100932 ps
CPU time 42.13 seconds
Started Jul 10 05:02:19 PM PDT 24
Finished Jul 10 05:03:03 PM PDT 24
Peak memory 217656 kb
Host smart-6657d29e-75f8-4e12-9d87-b11a4b325eac
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246679104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_err
ors.246679104
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.1690651002
Short name T7
Test name
Test status
Simulation time 3332376849 ps
CPU time 2.96 seconds
Started Jul 10 05:02:22 PM PDT 24
Finished Jul 10 05:02:27 PM PDT 24
Peak memory 217272 kb
Host smart-bf915a77-9605-4e61-83ad-39b1a2f666ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690651002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.1
690651002
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.766077581
Short name T277
Test name
Test status
Simulation time 3588205042 ps
CPU time 20.62 seconds
Started Jul 10 05:02:18 PM PDT 24
Finished Jul 10 05:02:40 PM PDT 24
Peak memory 217636 kb
Host smart-70740325-560f-4c10-bae0-5588300ac11f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766077581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_
prog_failure.766077581
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.996200130
Short name T644
Test name
Test status
Simulation time 4308004668 ps
CPU time 16.26 seconds
Started Jul 10 05:02:19 PM PDT 24
Finished Jul 10 05:02:37 PM PDT 24
Peak memory 217064 kb
Host smart-6653be34-6147-4fb5-b4b9-892e1c9dfd15
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996200130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j
tag_regwen_during_op.996200130
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.953413436
Short name T661
Test name
Test status
Simulation time 121060378 ps
CPU time 4.36 seconds
Started Jul 10 05:02:20 PM PDT 24
Finished Jul 10 05:02:27 PM PDT 24
Peak memory 217080 kb
Host smart-ac04d203-f20e-4d7c-9c2a-845217fc889a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953413436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.953413436
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.1899024746
Short name T502
Test name
Test status
Simulation time 1405277856 ps
CPU time 70.16 seconds
Started Jul 10 05:02:20 PM PDT 24
Finished Jul 10 05:03:32 PM PDT 24
Peak memory 283060 kb
Host smart-3435bab3-ef4d-41f4-a6e1-e6d63bc36479
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899024746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.1899024746
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.3091299325
Short name T285
Test name
Test status
Simulation time 2400387367 ps
CPU time 8.56 seconds
Started Jul 10 05:02:18 PM PDT 24
Finished Jul 10 05:02:28 PM PDT 24
Peak memory 223576 kb
Host smart-9182ee07-7979-407f-9c1f-8aecce9913d2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091299325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.3091299325
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.2841120315
Short name T180
Test name
Test status
Simulation time 40342698 ps
CPU time 1.4 seconds
Started Jul 10 05:02:19 PM PDT 24
Finished Jul 10 05:02:23 PM PDT 24
Peak memory 217656 kb
Host smart-8d03ec5c-d46d-47b3-9c25-bfa55dfd434d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841120315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.2841120315
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.3405356488
Short name T628
Test name
Test status
Simulation time 279444842 ps
CPU time 15.96 seconds
Started Jul 10 05:02:19 PM PDT 24
Finished Jul 10 05:02:37 PM PDT 24
Peak memory 217116 kb
Host smart-4e0ac490-d538-4210-ba89-8148a683fc49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405356488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.3405356488
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.1381487894
Short name T824
Test name
Test status
Simulation time 2672736445 ps
CPU time 10.67 seconds
Started Jul 10 05:02:20 PM PDT 24
Finished Jul 10 05:02:33 PM PDT 24
Peak memory 218368 kb
Host smart-0ffef79b-1b7c-44ba-8f55-e869b8e8dce9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381487894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.1381487894
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.2483152631
Short name T307
Test name
Test status
Simulation time 253344871 ps
CPU time 10.4 seconds
Started Jul 10 05:02:21 PM PDT 24
Finished Jul 10 05:02:33 PM PDT 24
Peak memory 225400 kb
Host smart-f9ae76c8-e1e0-4e73-aaa7-501525a1fd3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483152631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.2483152631
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.40196967
Short name T506
Test name
Test status
Simulation time 1838333679 ps
CPU time 8.93 seconds
Started Jul 10 05:02:20 PM PDT 24
Finished Jul 10 05:02:31 PM PDT 24
Peak memory 217592 kb
Host smart-2e536551-93ad-483d-8136-35e87049e004
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40196967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.40196967
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.1263816864
Short name T243
Test name
Test status
Simulation time 338315310 ps
CPU time 9.32 seconds
Started Jul 10 05:02:19 PM PDT 24
Finished Jul 10 05:02:30 PM PDT 24
Peak memory 225448 kb
Host smart-f1b7d8dc-b831-4150-9b3e-387fe50bb3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263816864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.1263816864
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.2914451507
Short name T540
Test name
Test status
Simulation time 44285036 ps
CPU time 3.09 seconds
Started Jul 10 05:02:20 PM PDT 24
Finished Jul 10 05:02:26 PM PDT 24
Peak memory 213956 kb
Host smart-bfcc8bd3-5489-4ea1-9039-014994c86444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914451507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.2914451507
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.3118952551
Short name T616
Test name
Test status
Simulation time 366895110 ps
CPU time 24.76 seconds
Started Jul 10 05:02:18 PM PDT 24
Finished Jul 10 05:02:44 PM PDT 24
Peak memory 250384 kb
Host smart-b2851594-a605-474e-8c97-a461266fd085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118952551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.3118952551
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.1016410956
Short name T236
Test name
Test status
Simulation time 128299125 ps
CPU time 6.59 seconds
Started Jul 10 05:02:20 PM PDT 24
Finished Jul 10 05:02:29 PM PDT 24
Peak memory 242224 kb
Host smart-f83f44f0-0ef4-446c-a1f1-f9443960d41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016410956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.1016410956
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.2890413816
Short name T545
Test name
Test status
Simulation time 13696962922 ps
CPU time 447.04 seconds
Started Jul 10 05:02:21 PM PDT 24
Finished Jul 10 05:09:50 PM PDT 24
Peak memory 250536 kb
Host smart-821b6227-cc1f-430c-bfc4-72be80352dd3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890413816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.2890413816
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.515220723
Short name T164
Test name
Test status
Simulation time 28279174383 ps
CPU time 304.28 seconds
Started Jul 10 05:02:26 PM PDT 24
Finished Jul 10 05:07:34 PM PDT 24
Peak memory 372480 kb
Host smart-64848eda-e393-4be0-8c4d-765276ef954c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=515220723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all_with_rand_reset.515220723
Directory /workspace/9.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.2652728569
Short name T385
Test name
Test status
Simulation time 59751010 ps
CPU time 0.79 seconds
Started Jul 10 05:02:23 PM PDT 24
Finished Jul 10 05:02:25 PM PDT 24
Peak memory 208184 kb
Host smart-dd4482d1-113d-4d5e-a9a4-597ff2cb897a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652728569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.2652728569
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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