Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

105727421

1

T1

381281

T2

74517

T3

113923

auto[1]

1434515

1

T1

39979

T8

198

T9

297

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

105722059

1

T1

381134

T2

74517

T3

113923

auto[1]

1439877

1

T1

41456

T8

693

T9

297

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7243413	1			T1	226367		T2	10195		T3	832
auto[IdleSt]	22502029	1			T1	446390		T2	9308		T3	11900
auto[ClkMuxSt]	36525	1			T1	1073		T2	80		T3	9
auto[CntIncrSt]	36258	1			T1	1072		T2	80		T3	9
auto[CntProgSt]	1558978	1			T1	1851		T2	36689		T3	67
auto[TransCheckSt]	28357	1			T1	793		T2	80		T3	9
auto[TokenHashSt]	43480343	1			T1	237545		T2	2540		T3	98541
auto[FlashRmaSt]	35764	1			T1	1078		T3	9		T9	5
auto[TokenCheck0St]	13003	1			T1	401		T3	9		T9	5
auto[TokenCheck1St]	9613	1			T1	320		T3	9		T9	5
auto[TransProgSt]	408415	1			T1	622		T3	84		T9	171
auto[PostTransSt]	13416940	1			T1	368938		T2	15545		T3	2445
auto[ScrapSt]	202546	1			T1	636		T12	4342		T15	3
auto[EscalateSt]	6819373	1			T1	185717		T8	1246		T9	1084
auto[InvalidSt]	11368403	1			T1	242009		T9	444		T11	3730

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1976	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	11368403	1			T1	242009		T9	444		T11	3730
EscalateSt	6819373	1			T1	185717		T8	1246		T9	1084
ScrapSt	202546	1			T1	636		T12	4342		T15	3
PostTransSt	13416940	1			T1	368938		T2	15545		T3	2445
TransProgSt	408415	1			T1	622		T3	84		T9	171
TokenCheck1St	9613	1			T1	320		T3	9		T9	5
TokenCheck0St	13003	1			T1	401		T3	9		T9	5
FlashRmaSt	35764	1			T1	1078		T3	9		T9	5
TokenHashSt	43480343	1			T1	237545		T2	2540		T3	98541
TransCheckSt	28357	1			T1	793		T2	80		T3	9
CntProgSt	1558978	1			T1	1851		T2	36689		T3	67
CntIncrSt	36258	1			T1	1072		T2	80		T3	9
ClkMuxSt	36525	1			T1	1073		T2	80		T3	9
IdleSt	22502029	1			T1	446390		T2	9308		T3	11900
ResetSt	7243413	1			T1	226367		T2	10195		T3	832
arcs[ResetSt=>IdleSt]	55608	1			T1	1850		T2	81		T3	9
arcs[IdleSt=>ScrapSt]	341	1			T1	8		T12	5		T15	1
arcs[IdleSt=>ClkMuxSt]	36322	1			T1	1072		T2	80		T3	9
arcs[ClkMuxSt=>CntIncrSt]	36258	1			T1	1072		T2	80		T3	9
arcs[CntIncrSt=>PostTransSt]	1939	1			T1	104		T12	5		T13	26
arcs[CntIncrSt=>CntProgSt]	34248	1			T1	968		T2	80		T3	9
arcs[CntProgSt=>PostTransSt]	4952	1			T1	175		T8	9		T11	13
arcs[CntProgSt=>TransCheckSt]	28357	1			T1	793		T2	80		T3	9
arcs[TransCheckSt=>PostTransSt]	3887	1			T1	95		T12	4		T13	22
arcs[TransCheckSt=>TokenHashSt]	24319	1			T1	698		T2	80		T3	9
arcs[TokenHashSt=>PostTransSt]	10456	1			T1	294		T2	80		T11	6
arcs[TokenHashSt=>FlashRmaSt]	13090	1			T1	401		T3	9		T9	5
arcs[FlashRmaSt=>TokenCheck0St]	13003	1			T1	401		T3	9		T9	5
arcs[TokenCheck0St=>PostTransSt]	3345	1			T1	81		T11	17		T12	6
arcs[TokenCheck0St=>TokenCheck1St]	9613	1			T1	320		T3	9		T9	5
arcs[TokenCheck1St=>PostTransSt]	653	1			T1	7		T11	1		T13	4
arcs[TransProgSt=>PostTransSt]	8144	1			T1	313		T3	9		T9	5
arcs[IdleSt=>EscalateSt]	236	1			T15	10		T40	3		T41	4
arcs[ClkMuxSt=>EscalateSt]	64	1			T15	4		T40	3		T41	4
arcs[CntIncrSt=>EscalateSt]	71	1			T15	2		T42	2		T43	3
arcs[CntProgSt=>EscalateSt]	939	1			T15	33		T40	29		T41	8
arcs[TransCheckSt=>EscalateSt]	151	1			T41	15		T45	9		T42	5
arcs[TokenHashSt=>EscalateSt]	773	1			T1	3		T12	1		T14	1
arcs[FlashRmaSt=>EscalateSt]	87	1			T15	2		T40	1		T41	4
arcs[TokenCheck0St=>EscalateSt]	45	1			T15	2		T41	1		T44	2
arcs[TokenCheck1St=>EscalateSt]	143	1			T15	4		T40	2		T41	4
arcs[TransProgSt=>EscalateSt]	673	1			T15	22		T40	14		T41	11
arcs[PostTransSt=>EscalateSt]	5244	1			T1	177		T8	9		T11	13
arcs[InvalidSt=>EscalateSt]	14538	1			T1	645		T9	6		T11	20

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7243223	1			T1	226367		T2	10195		T3	832
auto[0]	auto[IdleSt]	22501861	1			T1	446390		T2	9308		T3	11900
auto[0]	auto[ClkMuxSt]	36483	1			T1	1073		T2	80		T3	9
auto[0]	auto[CntIncrSt]	36212	1			T1	1072		T2	80		T3	9
auto[0]	auto[CntProgSt]	1558360	1			T1	1851		T2	36689		T3	67
auto[0]	auto[TransCheckSt]	28255	1			T1	793		T2	80		T3	9
auto[0]	auto[TokenHashSt]	43479853	1			T1	237544		T2	2540		T3	98541
auto[0]	auto[FlashRmaSt]	35711	1			T1	1078		T3	9		T9	5
auto[0]	auto[TokenCheck0St]	12978	1			T1	401		T3	9		T9	5
auto[0]	auto[TokenCheck1St]	9523	1			T1	320		T3	9		T9	5
auto[0]	auto[TransProgSt]	407973	1			T1	622		T3	84		T9	171
auto[0]	auto[PostTransSt]	13414221	1			T1	368851		T2	15545		T3	2445
auto[0]	auto[ScrapSt]	202495	1			T1	636		T12	4342		T15	2
auto[0]	auto[EscalateSt]	5397159	1			T1	146143		T8	1050		T9	790
auto[0]	auto[InvalidSt]	11361138	1			T1	241693		T9	441		T11	3722
auto[1]	auto[ResetSt]	190	1			T15	5		T40	4		T44	1
auto[1]	auto[IdleSt]	168	1			T15	8		T40	1		T41	2
auto[1]	auto[ClkMuxSt]	42	1			T15	1		T40	2		T41	4
auto[1]	auto[CntIncrSt]	46	1			T15	2		T42	2		T43	2
auto[1]	auto[CntProgSt]	618	1			T15	20		T40	18		T41	3
auto[1]	auto[TransCheckSt]	102	1			T41	8		T45	7		T42	5
auto[1]	auto[TokenHashSt]	490	1			T1	2		T12	1		T15	8
auto[1]	auto[FlashRmaSt]	53	1			T15	1		T40	1		T41	3
auto[1]	auto[TokenCheck0St]	25	1			T15	1		T44	1		T187	1
auto[1]	auto[TokenCheck1St]	90	1			T15	3		T40	2		T41	3
auto[1]	auto[TransProgSt]	442	1			T15	12		T40	4		T41	5
auto[1]	auto[PostTransSt]	2719	1			T1	87		T8	2		T11	5
auto[1]	auto[ScrapSt]	51	1			T15	1		T45	1		T43	1
auto[1]	auto[EscalateSt]	1422214	1			T1	39574		T8	196		T9	294
auto[1]	auto[InvalidSt]	7265	1			T1	316		T9	3		T11	8

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7243232	1			T1	226367		T2	10195		T3	832
auto[0]	auto[IdleSt]	22501881	1			T1	446390		T2	9308		T3	11900
auto[0]	auto[ClkMuxSt]	36478	1			T1	1073		T2	80		T3	9
auto[0]	auto[CntIncrSt]	36208	1			T1	1072		T2	80		T3	9
auto[0]	auto[CntProgSt]	1558350	1			T1	1851		T2	36689		T3	67
auto[0]	auto[TransCheckSt]	28249	1			T1	793		T2	80		T3	9
auto[0]	auto[TokenHashSt]	43479823	1			T1	237545		T2	2540		T3	98541
auto[0]	auto[FlashRmaSt]	35709	1			T1	1078		T3	9		T9	5
auto[0]	auto[TokenCheck0St]	12969	1			T1	401		T3	9		T9	5
auto[0]	auto[TokenCheck1St]	9508	1			T1	320		T3	9		T9	5
auto[0]	auto[TransProgSt]	407953	1			T1	622		T3	84		T9	171
auto[0]	auto[PostTransSt]	13414322	1			T1	368848		T2	15545		T3	2445
auto[0]	auto[ScrapSt]	202493	1			T1	636		T12	4342		T15	3
auto[0]	auto[EscalateSt]	5391778	1			T1	144681		T8	560		T9	790
auto[0]	auto[InvalidSt]	11361130	1			T1	241680		T9	441		T11	3718
auto[1]	auto[ResetSt]	181	1			T15	4		T40	6		T44	2
auto[1]	auto[IdleSt]	148	1			T15	7		T40	2		T41	4
auto[1]	auto[ClkMuxSt]	47	1			T15	4		T40	2		T41	2
auto[1]	auto[CntIncrSt]	50	1			T15	1		T42	1		T43	2
auto[1]	auto[CntProgSt]	628	1			T15	22		T40	17		T41	7
auto[1]	auto[TransCheckSt]	108	1			T41	12		T45	4		T42	1
auto[1]	auto[TokenHashSt]	520	1			T1	1		T14	1		T15	5
auto[1]	auto[FlashRmaSt]	55	1			T15	1		T41	2		T42	1
auto[1]	auto[TokenCheck0St]	34	1			T15	2		T41	1		T44	2
auto[1]	auto[TokenCheck1St]	105	1			T15	3		T40	1		T41	1
auto[1]	auto[TransProgSt]	462	1			T15	17		T40	12		T41	10
auto[1]	auto[PostTransSt]	2618	1			T1	90		T8	7		T11	8
auto[1]	auto[ScrapSt]	53	1			T41	1		T42	2		T43	1
auto[1]	auto[EscalateSt]	1427595	1			T1	41036		T8	686		T9	294
auto[1]	auto[InvalidSt]	7273	1			T1	329		T9	3		T11	12